2c597855aa
Copy the devicetree source for the H2+/H3/H5 SoCs and all existing boards from the Linux v5.18-rc1 tag. To maintain ABI compatibility with existing LTS kernels, one change moving some IP blocks to the r_intc interrupt controller is excluded. This effectively reverts Linux commits 994e5818392c and 9fdef3c3d8c2. This commit also adds the following new board devicetree: - sun8i-h3-nanopi-r1.dts This update should not impact any existing U-Boot functionality. Signed-off-by: Samuel Holland <samuel@sholland.org>
80 lines
1.8 KiB
Plaintext
80 lines
1.8 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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// Copyright (C) 2020 Chen-Yu Tsai <wens@csie.org>
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/ {
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cpu_opp_table: opp-table-cpu {
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compatible = "operating-points-v2";
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opp-shared;
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opp-408000000 {
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opp-hz = /bits/ 64 <408000000>;
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opp-microvolt = <1000000 1000000 1310000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp-648000000 {
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opp-hz = /bits/ 64 <648000000>;
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opp-microvolt = <1040000 1040000 1310000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp-816000000 {
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opp-hz = /bits/ 64 <816000000>;
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opp-microvolt = <1080000 1080000 1310000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp-912000000 {
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opp-hz = /bits/ 64 <912000000>;
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opp-microvolt = <1120000 1120000 1310000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp-960000000 {
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opp-hz = /bits/ 64 <960000000>;
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opp-microvolt = <1160000 1160000 1310000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp-1008000000 {
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opp-hz = /bits/ 64 <1008000000>;
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opp-microvolt = <1200000 1200000 1310000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp-1056000000 {
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opp-hz = /bits/ 64 <1056000000>;
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opp-microvolt = <1240000 1240000 1310000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp-1104000000 {
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opp-hz = /bits/ 64 <1104000000>;
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opp-microvolt = <1260000 1260000 1310000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp-1152000000 {
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opp-hz = /bits/ 64 <1152000000>;
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opp-microvolt = <1300000 1300000 1310000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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};
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};
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&cpu0 {
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operating-points-v2 = <&cpu_opp_table>;
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};
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&cpu1 {
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operating-points-v2 = <&cpu_opp_table>;
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};
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&cpu2 {
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operating-points-v2 = <&cpu_opp_table>;
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};
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&cpu3 {
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operating-points-v2 = <&cpu_opp_table>;
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};
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