64f5e3b492
System controllers are pretty much the same on the all boards that's why use autodetection based on i2c eeprom. This should end up with having only one BSP for all SCs with only DT overlays to cover different i2c structures. All MIOs are fixed by the spec that's why not a problem to description pinctrl setting. Apart from eth phy reset, it also set proper phy delays. The TI DP83867 PHY datasheet says: T1: Post RESET stabilization time == 195us T3: Hardware configuration pins transition to output drivers == 64us T4: RESET pulse width == 1us So with a little overhead set 'reset-assert-us' to 100us (T4) and 'reset-deassert-us' to 280us (T1+T3). NOTE: The tuning of TI DP83867 phy reset delay is derived from linux upstream commit: 5dbadc848259(arm64: dts: fsl: add support for Kontron pitx-imx8m board). i2c structure on Xilinx Versal evaluation platforms contain a lot of devices but also connection to connectors like SFP. Because of this complicated structure with also all level shifters, i2c muxes, etc. not all devices are able to reliably work on 400kHz even if they are compatible with this speed. That's why set i2c frequency to 100KHz to increase reliability of the i2c bus. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/c8092340f92144f0cc9096194198f227015bc013.1695808407.git.michal.simek@amd.com
431 lines
9.6 KiB
Plaintext
431 lines
9.6 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* dts file for Xilinx ZynqMP Generic System Controller
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*
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* (C) Copyright 2021 - 2022, Xilinx, Inc.
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* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
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*
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* Michal Simek <michal.simek@amd.com>
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*/
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/dts-v1/;
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#include "zynqmp.dtsi"
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#include "zynqmp-clk-ccf.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/net/ti-dp83867.h>
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#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
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#include <dt-bindings/phy/phy.h>
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/ {
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model = "ZynqMP Generic System Controller";
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compatible = "xlnx,zynqmp-sc-revB", "xlnx,zynqmp-sc", "xlnx,zynqmp";
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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mmc0 = &sdhci0;
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mmc1 = &sdhci1;
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nvmem0 = &eeprom;
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rtc0 = &rtc;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &dcc;
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spi0 = &qspi;
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spi1 = &spi0;
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spi2 = &spi1;
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "serial1:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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gpio-keys {
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compatible = "gpio-keys";
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autorepeat;
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fwuen {
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label = "sw16";
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gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
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linux,code = <BTN_MISC>;
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wakeup-source;
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autorepeat;
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};
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};
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leds {
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compatible = "gpio-leds";
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ds40-led {
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label = "heartbeat";
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gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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ds44-led {
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label = "status";
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gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
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};
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};
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si5332_2: si5332_2 { /* u42 */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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};
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pwm-fan {
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compatible = "pwm-fan";
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status = "okay";
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pwms = <&ttc0 2 40000 1>;
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};
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};
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&gpio {
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status = "okay";
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gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
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"QSPI_CS_B", "", "LED1", "LED2", "", /* 5 - 9 */
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"", "ZU4_TRIGGER", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
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"EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
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"EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "I2C1_SCL", /* 20 - 24 */
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"I2C1_SDA", "UART0_RXD", "UART0_TXD", "", "", /* 25 - 29 */
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"", "", "", "", "I2C0_SCL", /* 30 - 34 */
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"I2C0_SDA", "UART1_TXD", "UART1_RXD", "GEM_TX_CLK", "GEM_TX_D0", /* 35 - 39 */
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"GEM_TX_D1", "GEM_TX_D2", "GEM_TX_D3", "GEM_TX_CTL", "GEM_RX_CLK", /* 40 - 44 */
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"GEM_RX_D0", "GEM_RX_D1", "GEM_RX_D2", "GEM_RX_D3", "GEM_RX_CTL", /* 45 - 49 */
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"GEM_MDC", "GEM_MDIO", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
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"USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
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"USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */
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"", "", "", "", "", /* 65 - 69 */
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"", "", "", "", "", /* 70 - 74 */
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"", "", "ETH_RESET_B", /* 75 - 77, MIO end and EMIO start */
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"", "", /* 78 - 79 */
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"", "", "", "", "", /* 80 - 84 */
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"", "", "", "", "", /* 85 -89 */
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"", "", "", "", "", /* 90 - 94 */
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"", "", "", "", "", /* 95 - 99 */
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"", "", "", "", "", /* 100 - 104 */
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"", "", "", "", "", /* 105 - 109 */
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"", "", "", "", "", /* 110 - 114 */
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"", "", "", "", "", /* 115 - 119 */
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"", "", "", "", "", /* 120 - 124 */
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"", "", "", "", "", /* 125 - 129 */
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"", "", "", "", "", /* 130 - 134 */
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"", "", "", "", "", /* 135 - 139 */
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"", "", "", "", "", /* 140 - 144 */
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"", "", "", "", "", /* 145 - 149 */
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"", "", "", "", "", /* 150 - 154 */
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"", "", "", "", "", /* 155 - 159 */
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"", "", "", "", "", /* 160 - 164 */
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"", "", "", "", "", /* 165 - 169 */
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"", "", "", ""; /* 170 - 173 */
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};
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&gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */
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status = "okay";
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phy-mode = "rgmii-id";
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phy-handle = <&phy0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gem1_default>;
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mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@1 {
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#phy-cells = <1>;
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compatible = "ethernet-phy-id2000.a231";
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reg = <1>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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ti,dp83867-rxctrl-strap-quirk;
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reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>;
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reset-assert-us = <100>;
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reset-deassert-us = <280>;
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};
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};
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};
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&i2c0 {
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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clock-frequency = <100000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c0_default>;
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pinctrl-1 = <&pinctrl_i2c0_gpio>;
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scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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};
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&i2c1 { /* i2c1 MIO 24-25 */
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status = "okay";
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bootph-all;
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clock-frequency = <100000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c1_default>;
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pinctrl-1 = <&pinctrl_i2c1_gpio>;
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scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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/* Use for storing information about SC board */
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eeprom: eeprom@54 { /* u34 - m24128 16kB */
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compatible = "st,24c128", "atmel,24c128";
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reg = <0x54>; /* & 0x5c */
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bootph-all;
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};
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};
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/* USB 3.0 only */
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&psgtr {
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status = "okay";
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/* nc, nc, usb3 */
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clocks = <&si5332_2>;
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clock-names = "ref2";
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};
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&qspi { /* MIO 0-5 */
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status = "okay";
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/* QSPI should also have PINCTRL setup */
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flash@0 {
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compatible = "mt25qu512a", "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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spi-max-frequency = <40000000>; /* 40MHz */
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partition@0 {
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label = "Image Selector";
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reg = <0x0 0x80000>; /* 512KB */
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read-only;
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lock;
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};
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partition@80000 {
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label = "Image Selector Golden";
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reg = <0x80000 0x80000>; /* 512KB */
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read-only;
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lock;
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};
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partition@100000 {
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label = "Persistent Register";
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reg = <0x100000 0x20000>; /* 128KB */
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};
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partition@120000 {
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label = "Persistent Register Backup";
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reg = <0x120000 0x20000>; /* 128KB */
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};
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partition@140000 {
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label = "Open_1";
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reg = <0x140000 0xC0000>; /* 768KB */
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};
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partition@200000 {
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label = "Image A (FSBL, PMU, ATF, U-Boot)";
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reg = <0x200000 0xD00000>; /* 13MB */
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};
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partition@f00000 {
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label = "ImgSel Image A Catch";
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reg = <0xF00000 0x80000>; /* 512KB */
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read-only;
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lock;
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};
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partition@f80000 {
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label = "Image B (FSBL, PMU, ATF, U-Boot)";
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reg = <0xF80000 0xD00000>; /* 13MB */
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};
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partition@1c80000 {
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label = "ImgSel Image B Catch";
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reg = <0x1C80000 0x80000>; /* 512KB */
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read-only;
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lock;
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};
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partition@1d00000 {
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label = "Open_2";
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reg = <0x1D00000 0x100000>; /* 1MB */
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};
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partition@1e00000 {
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label = "Recovery Image";
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reg = <0x1E00000 0x200000>; /* 2MB */
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read-only;
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lock;
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};
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partition@2000000 {
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label = "Recovery Image Backup";
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reg = <0x2000000 0x200000>; /* 2MB */
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read-only;
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lock;
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};
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partition@2200000 {
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label = "U-Boot storage variables";
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reg = <0x2200000 0x20000>; /* 128KB */
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};
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partition@2220000 {
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label = "U-Boot storage variables backup";
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reg = <0x2220000 0x20000>; /* 128KB */
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};
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partition@2240000 {
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label = "SHA256";
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reg = <0x2240000 0x40000>; /* 256B but 256KB sector */
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read-only;
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lock;
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};
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partition@2280000 {
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label = "Secure OS Storage";
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reg = <0x2280000 0x20000>; /* 128KB */
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};
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partition@22A0000 {
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label = "User";
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reg = <0x22A0000 0x1d60000>; /* 29.375 MB */
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};
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};
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};
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&sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */
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status = "okay";
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non-removable;
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disable-wp;
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bus-width = <8>;
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xlnx,mio-bank = <0>;
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};
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&ttc0 {
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status = "okay";
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#pwm-cells = <3>;
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};
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&uart1 { /* uart0 MIO36-37 */
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1_default>;
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};
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&pinctrl0 { /* required by spec */
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status = "okay";
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pinctrl_uart1_default: uart1-default {
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conf {
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groups = "uart1_9_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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drive-strength = <12>;
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};
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conf-rx {
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pins = "MIO37";
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bias-high-impedance;
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};
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conf-tx {
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pins = "MIO36";
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bias-disable;
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};
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mux {
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groups = "uart1_9_grp";
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function = "uart1";
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};
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};
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pinctrl_i2c0_default: i2c0-default {
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mux {
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groups = "i2c0_8_grp";
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function = "i2c0";
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};
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conf {
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groups = "i2c0_8_grp";
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bias-pull-up;
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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};
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pinctrl_i2c0_gpio: i2c0-gpio {
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mux {
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groups = "gpio0_34_grp", "gpio0_35_grp";
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function = "gpio0";
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};
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conf {
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groups = "gpio0_34_grp", "gpio0_35_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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};
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pinctrl_i2c1_default: i2c1-default {
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conf {
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groups = "i2c1_6_grp";
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bias-pull-up;
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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mux {
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groups = "i2c1_6_grp";
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function = "i2c1";
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};
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};
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pinctrl_i2c1_gpio: i2c1-gpio {
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conf {
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groups = "gpio0_24_grp", "gpio0_25_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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mux {
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groups = "gpio0_24_grp", "gpio0_25_grp";
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function = "gpio0";
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};
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};
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pinctrl_gem1_default: gem1-default {
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conf {
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groups = "ethernet1_0_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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conf-rx {
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pins = "MIO44", "MIO46", "MIO48";
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bias-high-impedance;
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low-power-disable;
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};
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conf-bootstrap {
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pins = "MIO45", "MIO47", "MIO49";
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bias-disable;
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low-power-disable;
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};
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conf-tx {
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pins = "MIO38", "MIO39", "MIO40",
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"MIO41", "MIO42", "MIO43";
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bias-disable;
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low-power-enable;
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};
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conf-mdio {
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groups = "mdio1_0_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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bias-disable;
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};
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mux-mdio {
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function = "mdio1";
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groups = "mdio1_0_grp";
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};
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mux {
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function = "ethernet1";
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groups = "ethernet1_0_grp";
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};
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};
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};
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