255 lines
3.9 KiB
Plaintext
255 lines
3.9 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
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/*
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* Copyright : STMicroelectronics 2018
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*
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* Copyright (C) Linaro Ltd 2019 - All Rights Reserved
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* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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* Copyright (C) 2020 Marek Vasut <marex@denx.de>
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*/
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#include <dt-bindings/clock/stm32mp1-clksrc.h>
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#include "stm32mp15-u-boot.dtsi"
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#include "stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi"
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#include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi"
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#include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
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/ {
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bootph-all;
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aliases {
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eeprom0 = &eeprom0;
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};
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config {
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dh,ddr3-coding-gpios = <&gpiog 0 0>, <&gpiog 1 0>;
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dh,som-coding-gpios = <&gpioz 7 0>, <&gpiof 3 0>;
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};
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};
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&flash0 {
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bootph-pre-ram;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "fsbl1";
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reg = <0x00000000 0x00040000>;
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};
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partition@40000 {
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label = "fsbl2";
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reg = <0x00040000 0x00040000>;
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};
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partition@80000 {
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label = "uboot";
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reg = <0x00080000 0x00160000>;
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};
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partition@1e0000 {
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label = "env1";
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reg = <0x001E0000 0x00010000>;
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};
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partition@1f0000 {
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label = "env2";
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reg = <0x001F0000 0x00010000>;
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};
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};
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};
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&i2c4 {
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bootph-all;
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bootph-pre-ram;
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eeprom0: eeprom@53 {
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};
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};
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&i2c4_pins_a {
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bootph-all;
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pins {
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bootph-all;
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};
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};
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&pmic {
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bootph-all;
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bootph-pre-ram;
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regulators {
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bootph-pre-ram;
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};
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};
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&pwr_regulators {
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bootph-pre-ram;
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};
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&qspi {
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bootph-pre-ram;
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};
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&qspi_clk_pins_a {
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bootph-pre-ram;
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pins {
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bootph-pre-ram;
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};
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};
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&qspi_bk1_pins_a {
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bootph-pre-ram;
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pins {
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bootph-pre-ram;
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};
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};
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&qspi_cs1_pins_a {
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bootph-pre-ram;
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pins {
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bootph-pre-ram;
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};
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};
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&rcc {
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st,clksrc = <
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CLK_MPU_PLL1P
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CLK_AXI_PLL2P
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CLK_MCU_PLL3P
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CLK_PLL12_HSE
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CLK_PLL3_HSE
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CLK_PLL4_HSE
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CLK_RTC_LSE
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CLK_MCO1_DISABLED
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CLK_MCO2_DISABLED
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>;
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st,clkdiv = <
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1 /*MPU*/
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0 /*AXI*/
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0 /*MCU*/
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1 /*APB1*/
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1 /*APB2*/
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1 /*APB3*/
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1 /*APB4*/
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2 /*APB5*/
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23 /*RTC*/
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0 /*MCO1*/
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0 /*MCO2*/
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>;
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st,pkcs = <
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CLK_CKPER_HSE
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CLK_FMC_ACLK
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CLK_QSPI_ACLK
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CLK_ETH_DISABLED
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CLK_SDMMC12_PLL4P
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CLK_DSI_DSIPLL
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CLK_STGEN_HSE
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CLK_USBPHY_HSE
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CLK_SPI2S1_PLL3Q
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CLK_SPI2S23_PLL3Q
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CLK_SPI45_HSI
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CLK_SPI6_HSI
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CLK_I2C46_HSI
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CLK_SDMMC3_PLL4P
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CLK_USBO_USBPHY
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CLK_ADC_CKPER
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CLK_CEC_LSE
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CLK_I2C12_HSI
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CLK_I2C35_HSI
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CLK_UART1_HSI
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CLK_UART24_HSI
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CLK_UART35_HSI
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CLK_UART6_HSI
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CLK_UART78_HSI
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CLK_SPDIF_PLL4P
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CLK_FDCAN_PLL4R
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CLK_SAI1_PLL3Q
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CLK_SAI2_PLL3Q
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CLK_SAI3_PLL3Q
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CLK_SAI4_PLL3Q
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CLK_RNG1_LSI
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CLK_RNG2_LSI
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CLK_LPTIM1_PCLK1
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CLK_LPTIM23_PCLK3
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CLK_LPTIM45_LSE
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>;
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/*
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* cfg = < DIVM1 DIVN P Q R PQR(p,q,r) >;
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* frac = < f >;
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*
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* PRQ(p,q,r) ... for p,q,r: 0-output disabled / 1-output enabled
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* DIVN ... actually multiplier, but RCC_PLL1CFGR1 calls the field DIVN
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* m ... for PLL1,2: m=2 ; for PLL3,4: m=1
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* XTAL = 24 MHz
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*
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* VCO = ( XTAL / (DIVM1 + 1) ) * m * ( DIVN + 1 + ( f / 8192 ) )
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* P = VCO / (P + 1)
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* Q = VCO / (Q + 1)
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* R = VCO / (R + 1)
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*/
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/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
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pll2: st,pll@1 {
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compatible = "st,stm32mp1-pll";
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reg = <1>;
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cfg = < 2 65 1 0 0 PQR(1,1,1) >;
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frac = < 0x1400 >;
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bootph-all;
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};
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/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
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pll3: st,pll@2 {
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compatible = "st,stm32mp1-pll";
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reg = <2>;
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cfg = < 1 33 1 16 36 PQR(1,1,1) >;
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frac = < 0x1a04 >;
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bootph-all;
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};
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/* VCO = 594.0 MHz => P = 99, Q = 74, R = 99 */
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pll4: st,pll@3 {
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compatible = "st,stm32mp1-pll";
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reg = <3>;
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cfg = < 3 98 5 7 5 PQR(1,1,1) >;
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bootph-all;
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};
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};
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®11 {
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bootph-pre-ram;
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};
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®18 {
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bootph-pre-ram;
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};
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&usb33 {
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bootph-pre-ram;
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};
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&usbotg_hs_pins_a {
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bootph-pre-ram;
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};
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&usbotg_hs {
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bootph-pre-ram;
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};
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&usbphyc {
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bootph-pre-ram;
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};
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&usbphyc_port0 {
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bootph-pre-ram;
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};
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&usbphyc_port1 {
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bootph-pre-ram;
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};
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&vdd_usb {
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bootph-pre-ram;
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};
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