823 lines
23 KiB
C
823 lines
23 KiB
C
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/armv7.h>
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#include <asm/cache.h>
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#include <asm/gic.h>
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#include <asm/io.h>
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#include <asm/psci.h>
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#include <asm/secure.h>
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#include <hang.h>
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#include <linux/bitops.h>
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/* PWR */
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#define PWR_CR3 0x0c
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#define PWR_MPUCR 0x10
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#define PWR_CR3_DDRSREN BIT(10)
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#define PWR_CR3_DDRRETEN BIT(12)
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#define PWR_MPUCR_PDDS BIT(0)
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#define PWR_MPUCR_CSTDBYDIS BIT(3)
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#define PWR_MPUCR_CSSF BIT(9)
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/* RCC */
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#define RCC_MSSCKSELR 0x48
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#define RCC_DDRITFCR 0xd8
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#define RCC_DDRITFCR_DDRC1EN BIT(0)
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#define RCC_DDRITFCR_DDRC1LPEN BIT(1)
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#define RCC_DDRITFCR_DDRC2EN BIT(2)
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#define RCC_DDRITFCR_DDRC2LPEN BIT(3)
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#define RCC_DDRITFCR_DDRPHYCEN BIT(4)
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#define RCC_DDRITFCR_DDRPHYCLPEN BIT(5)
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#define RCC_DDRITFCR_DDRCAPBEN BIT(6)
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#define RCC_DDRITFCR_DDRCAPBLPEN BIT(7)
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#define RCC_DDRITFCR_AXIDCGEN BIT(8)
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#define RCC_DDRITFCR_DDRPHYCAPBEN BIT(9)
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#define RCC_DDRITFCR_DDRPHYCAPBLPEN BIT(10)
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#define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20)
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#define RCC_DDRITFCR_GSKPCTRL BIT(24)
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#define RCC_MP_SREQSETR 0x104
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#define RCC_MP_SREQCLRR 0x108
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#define RCC_MP_CIER 0x414
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#define RCC_MP_CIFR 0x418
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#define RCC_MP_CIFR_WKUPF BIT(20)
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#define RCC_MCUDIVR 0x830
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#define RCC_PLL3CR 0x880
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#define RCC_PLL4CR 0x894
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/* SYSCFG */
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#define SYSCFG_CMPCR 0x20
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#define SYSCFG_CMPCR_SW_CTRL BIT(2)
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#define SYSCFG_CMPENSETR 0x24
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#define SYSCFG_CMPENCLRR 0x28
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#define SYSCFG_CMPENR_MPUEN BIT(0)
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/* DDR Controller registers offsets */
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#define DDRCTRL_STAT 0x004
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#define DDRCTRL_PWRCTL 0x030
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#define DDRCTRL_PWRTMG 0x034
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#define DDRCTRL_HWLPCTL 0x038
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#define DDRCTRL_DFIMISC 0x1b0
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#define DDRCTRL_SWCTL 0x320
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#define DDRCTRL_SWSTAT 0x324
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#define DDRCTRL_PSTAT 0x3fc
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#define DDRCTRL_PCTRL_0 0x490
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#define DDRCTRL_PCTRL_1 0x540
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/* DDR Controller Register fields */
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#define DDRCTRL_STAT_OPERATING_MODE_MASK GENMASK(2, 0)
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#define DDRCTRL_STAT_OPERATING_MODE_NORMAL 0x1
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#define DDRCTRL_STAT_OPERATING_MODE_SR 0x3
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#define DDRCTRL_STAT_SELFREF_TYPE_MASK GENMASK(5, 4)
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#define DDRCTRL_STAT_SELFREF_TYPE_ASR (0x3 << 4)
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#define DDRCTRL_STAT_SELFREF_TYPE_SR (0x2 << 4)
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#define DDRCTRL_PWRCTL_SELFREF_EN BIT(0)
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#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE BIT(3)
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#define DDRCTRL_PWRCTL_SELFREF_SW BIT(5)
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#define DDRCTRL_PWRTMG_SELFREF_TO_X32_MASK GENMASK(23, 16)
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#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 BIT(16)
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#define DDRCTRL_HWLPCTL_HW_LP_EN BIT(0)
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#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN BIT(0)
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#define DDRCTRL_SWCTL_SW_DONE BIT(0)
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#define DDRCTRL_SWSTAT_SW_DONE_ACK BIT(0)
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#define DDRCTRL_PSTAT_RD_PORT_BUSY_0 BIT(0)
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#define DDRCTRL_PSTAT_RD_PORT_BUSY_1 BIT(1)
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#define DDRCTRL_PSTAT_WR_PORT_BUSY_0 BIT(16)
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#define DDRCTRL_PSTAT_WR_PORT_BUSY_1 BIT(17)
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#define DDRCTRL_PCTRL_N_PORT_EN BIT(0)
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/* DDR PHY registers offsets */
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#define DDRPHYC_PIR 0x004
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#define DDRPHYC_PGSR 0x00c
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#define DDRPHYC_ACDLLCR 0x014
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#define DDRPHYC_ACIOCR 0x024
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#define DDRPHYC_DXCCR 0x028
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#define DDRPHYC_DSGCR 0x02c
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#define DDRPHYC_ZQ0CR0 0x180
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#define DDRPHYC_DX0DLLCR 0x1cc
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#define DDRPHYC_DX1DLLCR 0x20c
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#define DDRPHYC_DX2DLLCR 0x24c
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#define DDRPHYC_DX3DLLCR 0x28c
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/* DDR PHY Register fields */
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#define DDRPHYC_PIR_INIT BIT(0)
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#define DDRPHYC_PIR_DLLSRST BIT(1)
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#define DDRPHYC_PIR_DLLLOCK BIT(2)
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#define DDRPHYC_PIR_ITMSRST BIT(4)
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#define DDRPHYC_PGSR_IDONE BIT(0)
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#define DDRPHYC_ACDLLCR_DLLSRST BIT(30)
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#define DDRPHYC_ACDLLCR_DLLDIS BIT(31)
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#define DDRPHYC_ACIOCR_ACOE BIT(1)
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#define DDRPHYC_ACIOCR_ACPDD BIT(3)
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#define DDRPHYC_ACIOCR_ACPDR BIT(4)
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#define DDRPHYC_ACIOCR_CKPDD_MASK GENMASK(10, 8)
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#define DDRPHYC_ACIOCR_CKPDD_0 BIT(8)
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#define DDRPHYC_ACIOCR_CKPDR_MASK GENMASK(13, 11)
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#define DDRPHYC_ACIOCR_CKPDR_0 BIT(11)
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#define DDRPHYC_ACIOCR_CSPDD_MASK GENMASK(20, 18)
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#define DDRPHYC_ACIOCR_CSPDD_0 BIT(18)
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#define DDRPHYC_DXCCR_DXPDD BIT(2)
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#define DDRPHYC_DXCCR_DXPDR BIT(3)
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#define DDRPHYC_DSGCR_CKEPDD_MASK GENMASK(19, 16)
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#define DDRPHYC_DSGCR_CKEPDD_0 BIT(16)
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#define DDRPHYC_DSGCR_ODTPDD_MASK GENMASK(23, 20)
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#define DDRPHYC_DSGCR_ODTPDD_0 BIT(20)
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#define DDRPHYC_DSGCR_NL2PD BIT(24)
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#define DDRPHYC_DSGCR_CKOE BIT(28)
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#define DDRPHYC_ZQ0CRN_ZQPD BIT(31)
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#define DDRPHYC_DXNDLLCR_DLLDIS BIT(31)
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#define BOOT_API_A7_CORE0_MAGIC_NUMBER 0xca7face0
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#define BOOT_API_A7_CORE1_MAGIC_NUMBER 0xca7face1
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#define MPIDR_AFF0 GENMASK(7, 0)
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#define RCC_MP_GRSTCSETR (STM32_RCC_BASE + 0x0404)
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#define RCC_MP_GRSTCSETR_MPSYSRST BIT(0)
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#define RCC_MP_GRSTCSETR_MPUP0RST BIT(4)
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#define RCC_MP_GRSTCSETR_MPUP1RST BIT(5)
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/* IWDG */
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#define IWDG_KR 0x00
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#define IWDG_KR_RELOAD_KEY 0xaaaa
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#define IWDG_EWCR 0x14
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#define IWDG_EWCR_EWIC BIT(14)
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#define STM32MP1_PSCI_NR_CPUS 2
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#if STM32MP1_PSCI_NR_CPUS > CONFIG_ARMV7_PSCI_NR_CPUS
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#error "invalid value for CONFIG_ARMV7_PSCI_NR_CPUS"
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#endif
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u8 psci_state[STM32MP1_PSCI_NR_CPUS] __secure_data = {
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PSCI_AFFINITY_LEVEL_ON,
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PSCI_AFFINITY_LEVEL_OFF};
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static u32 __secure_data cntfrq;
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static u32 __secure cp15_read_cntfrq(void)
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{
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u32 frq;
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asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (frq));
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return frq;
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}
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static void __secure cp15_write_cntfrq(u32 frq)
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{
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asm volatile ("mcr p15, 0, %0, c14, c0, 0" : : "r" (frq));
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}
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static inline void psci_set_state(int cpu, u8 state)
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{
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psci_state[cpu] = state;
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dsb();
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isb();
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}
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static u32 __secure stm32mp_get_gicd_base_address(void)
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{
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u32 periphbase;
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/* get the GIC base address from the CBAR register */
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asm("mrc p15, 4, %0, c15, c0, 0\n" : "=r" (periphbase));
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return (periphbase & CBAR_MASK) + GIC_DIST_OFFSET;
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}
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static void __secure stm32mp_raise_sgi0(int cpu)
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{
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u32 gic_dist_addr;
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gic_dist_addr = stm32mp_get_gicd_base_address();
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/* ask cpu with SGI0 */
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writel((BIT(cpu) << 16), gic_dist_addr + GICD_SGIR);
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}
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void __secure psci_arch_cpu_entry(void)
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{
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u32 cpu = psci_get_cpu_id();
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psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON);
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/* write the saved cntfrq */
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cp15_write_cntfrq(cntfrq);
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/* reset magic in TAMP register */
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writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER);
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}
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s32 __secure psci_features(u32 function_id, u32 psci_fid)
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{
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switch (psci_fid) {
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case ARM_PSCI_0_2_FN_PSCI_VERSION:
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case ARM_PSCI_0_2_FN_CPU_OFF:
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case ARM_PSCI_0_2_FN_CPU_ON:
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case ARM_PSCI_0_2_FN_AFFINITY_INFO:
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case ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
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case ARM_PSCI_0_2_FN_SYSTEM_OFF:
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case ARM_PSCI_0_2_FN_SYSTEM_RESET:
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case ARM_PSCI_1_0_FN_SYSTEM_SUSPEND:
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return 0x0;
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}
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return ARM_PSCI_RET_NI;
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}
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u32 __secure psci_version(void)
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{
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return ARM_PSCI_VER_1_0;
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}
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s32 __secure psci_affinity_info(u32 function_id, u32 target_affinity,
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u32 lowest_affinity_level)
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{
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u32 cpu = target_affinity & MPIDR_AFF0;
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if (lowest_affinity_level > 0)
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return ARM_PSCI_RET_INVAL;
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if (target_affinity & ~MPIDR_AFF0)
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return ARM_PSCI_RET_INVAL;
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if (cpu >= STM32MP1_PSCI_NR_CPUS)
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return ARM_PSCI_RET_INVAL;
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return psci_state[cpu];
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}
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u32 __secure psci_migrate_info_type(void)
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{
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/*
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* in Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
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* return 2 = Trusted OS is either not present or does not require
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* migration, system of this type does not require the caller
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* to use the MIGRATE function.
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* MIGRATE function calls return NOT_SUPPORTED.
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*/
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return 2;
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}
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s32 __secure psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc,
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u32 context_id)
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{
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u32 cpu = target_cpu & MPIDR_AFF0;
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if (target_cpu & ~MPIDR_AFF0)
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return ARM_PSCI_RET_INVAL;
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if (cpu >= STM32MP1_PSCI_NR_CPUS)
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return ARM_PSCI_RET_INVAL;
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if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON)
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return ARM_PSCI_RET_ALREADY_ON;
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/* read and save cntfrq of current cpu to write on target cpu */
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cntfrq = cp15_read_cntfrq();
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/* reset magic in TAMP register */
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if (readl(TAMP_BACKUP_MAGIC_NUMBER))
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writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER);
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/*
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* ROM code need a first SGI0 after core reset
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* core is ready when magic is set to 0 in ROM code
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*/
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while (readl(TAMP_BACKUP_MAGIC_NUMBER))
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stm32mp_raise_sgi0(cpu);
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/* store target PC and context id*/
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psci_save(cpu, pc, context_id);
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/* write entrypoint in backup RAM register */
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writel((u32)&psci_cpu_entry, TAMP_BACKUP_BRANCH_ADDRESS);
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psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON_PENDING);
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/* write magic number in backup register */
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if (cpu == 0x01)
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writel(BOOT_API_A7_CORE1_MAGIC_NUMBER,
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TAMP_BACKUP_MAGIC_NUMBER);
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else
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writel(BOOT_API_A7_CORE0_MAGIC_NUMBER,
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TAMP_BACKUP_MAGIC_NUMBER);
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/* Generate an IT to start the core */
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stm32mp_raise_sgi0(cpu);
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return ARM_PSCI_RET_SUCCESS;
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}
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s32 __secure psci_cpu_off(void)
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{
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u32 cpu;
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cpu = psci_get_cpu_id();
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psci_cpu_off_common();
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psci_set_state(cpu, PSCI_AFFINITY_LEVEL_OFF);
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/* reset core: wfi is managed by BootRom */
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if (cpu == 0x01)
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writel(RCC_MP_GRSTCSETR_MPUP1RST, RCC_MP_GRSTCSETR);
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else
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writel(RCC_MP_GRSTCSETR_MPUP0RST, RCC_MP_GRSTCSETR);
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/* just waiting reset */
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while (1)
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wfi();
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}
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void __secure psci_system_reset(void)
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{
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/* System reset */
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writel(RCC_MP_GRSTCSETR_MPSYSRST, RCC_MP_GRSTCSETR);
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/* just waiting reset */
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while (1)
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wfi();
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}
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void __secure psci_system_off(void)
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{
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/* System Off is not managed, waiting user power off
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* TODO: handle I2C write in PMIC Main Control register bit 0 = SWOFF
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*/
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while (1)
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wfi();
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}
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static void __secure secure_udelay(unsigned int delay)
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{
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u32 freq = cp15_read_cntfrq() / 1000000;
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u64 start, end;
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delay *= freq;
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asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (start));
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for (;;) {
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asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (end));
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if ((end - start) > delay)
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break;
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}
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}
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static int __secure secure_waitbits(u32 reg, u32 mask, u32 val)
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{
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u32 freq = cp15_read_cntfrq() / 1000000;
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u32 delay = 500 * freq; /* 500 us */
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u64 start, end;
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u32 tmp;
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asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (start));
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for (;;) {
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tmp = readl(reg);
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tmp &= mask;
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if ((tmp & val) == val)
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return 0;
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asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (end));
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if ((end - start) > delay)
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return -ETIMEDOUT;
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}
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}
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static void __secure ddr_sr_mode_ssr(u32 *saved_pwrctl)
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{
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setbits_le32(STM32_RCC_BASE + RCC_DDRITFCR,
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RCC_DDRITFCR_DDRC1LPEN | RCC_DDRITFCR_DDRC1EN |
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RCC_DDRITFCR_DDRC2LPEN | RCC_DDRITFCR_DDRC2EN |
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RCC_DDRITFCR_DDRCAPBLPEN | RCC_DDRITFCR_DDRPHYCAPBLPEN |
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RCC_DDRITFCR_DDRCAPBEN | RCC_DDRITFCR_DDRPHYCAPBEN |
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RCC_DDRITFCR_DDRPHYCEN);
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clrbits_le32(STM32_RCC_BASE + RCC_DDRITFCR,
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RCC_DDRITFCR_AXIDCGEN | RCC_DDRITFCR_DDRCKMOD_MASK);
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/* Disable HW LP interface of uMCTL2 */
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clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_HWLPCTL,
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DDRCTRL_HWLPCTL_HW_LP_EN);
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/* Configure Automatic LP modes of uMCTL2 */
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clrsetbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRTMG,
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DDRCTRL_PWRTMG_SELFREF_TO_X32_MASK,
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DDRCTRL_PWRTMG_SELFREF_TO_X32_0);
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/* Save PWRCTL register to restart ASR after suspend (if applicable) */
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*saved_pwrctl = readl(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL);
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/*
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* Disable Clock disable with LP modes
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* (used in RUN mode for LPDDR2 with specific timing).
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*/
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clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL,
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DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE);
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/* Disable automatic Self-Refresh mode */
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clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL,
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DDRCTRL_PWRCTL_SELFREF_EN);
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}
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static void __secure ddr_sr_mode_restore(u32 saved_pwrctl)
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{
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saved_pwrctl &= DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE |
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DDRCTRL_PWRCTL_SELFREF_EN;
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/* Restore ASR mode in case it was enabled before suspend. */
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setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL, saved_pwrctl);
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}
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static int __secure ddr_sw_self_refresh_in(void)
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{
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int ret;
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clrbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, RCC_DDRITFCR_AXIDCGEN);
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|
|
/* Blocks AXI ports from taking anymore transactions */
|
|
clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_0,
|
|
DDRCTRL_PCTRL_N_PORT_EN);
|
|
clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_1,
|
|
DDRCTRL_PCTRL_N_PORT_EN);
|
|
|
|
/*
|
|
* Waits unit all AXI ports are idle
|
|
* Poll PSTAT.rd_port_busy_n = 0
|
|
* Poll PSTAT.wr_port_busy_n = 0
|
|
*/
|
|
ret = secure_waitbits(STM32_DDRCTRL_BASE + DDRCTRL_PSTAT,
|
|
DDRCTRL_PSTAT_RD_PORT_BUSY_0 |
|
|
DDRCTRL_PSTAT_RD_PORT_BUSY_1 |
|
|
DDRCTRL_PSTAT_WR_PORT_BUSY_0 |
|
|
DDRCTRL_PSTAT_WR_PORT_BUSY_1, 0);
|
|
if (ret)
|
|
goto pstat_failed;
|
|
|
|
/* SW Self-Refresh entry */
|
|
setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL, DDRCTRL_PWRCTL_SELFREF_SW);
|
|
|
|
/*
|
|
* Wait operating mode change in self-refresh mode
|
|
* with STAT.operating_mode[1:0]==11.
|
|
* Ensure transition to self-refresh was due to software
|
|
* by checking also that STAT.selfref_type[1:0]=2.
|
|
*/
|
|
ret = secure_waitbits(STM32_DDRCTRL_BASE + DDRCTRL_STAT,
|
|
DDRCTRL_STAT_OPERATING_MODE_MASK |
|
|
DDRCTRL_STAT_SELFREF_TYPE_MASK,
|
|
DDRCTRL_STAT_OPERATING_MODE_SR |
|
|
DDRCTRL_STAT_SELFREF_TYPE_SR);
|
|
if (ret)
|
|
goto selfref_sw_failed;
|
|
|
|
/* IOs powering down (PUBL registers) */
|
|
setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_ACPDD);
|
|
setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_ACPDR);
|
|
|
|
clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR,
|
|
DDRPHYC_ACIOCR_CKPDD_MASK,
|
|
DDRPHYC_ACIOCR_CKPDD_0);
|
|
|
|
clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR,
|
|
DDRPHYC_ACIOCR_CKPDR_MASK,
|
|
DDRPHYC_ACIOCR_CKPDR_0);
|
|
|
|
clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR,
|
|
DDRPHYC_ACIOCR_CSPDD_MASK,
|
|
DDRPHYC_ACIOCR_CSPDD_0);
|
|
|
|
/* Disable command/address output driver */
|
|
clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_ACOE);
|
|
|
|
setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DXCCR, DDRPHYC_DXCCR_DXPDD);
|
|
|
|
setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DXCCR, DDRPHYC_DXCCR_DXPDR);
|
|
|
|
clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR,
|
|
DDRPHYC_DSGCR_ODTPDD_MASK,
|
|
DDRPHYC_DSGCR_ODTPDD_0);
|
|
|
|
setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_NL2PD);
|
|
|
|
clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR,
|
|
DDRPHYC_DSGCR_CKEPDD_MASK,
|
|
DDRPHYC_DSGCR_CKEPDD_0);
|
|
|
|
/* Disable PZQ cell (PUBL register) */
|
|
setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ZQ0CR0, DDRPHYC_ZQ0CRN_ZQPD);
|
|
|
|
/* Set latch */
|
|
clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_CKOE);
|
|
|
|
/* Additional delay to avoid early latch */
|
|
secure_udelay(10);
|
|
|
|
/* Activate sw retention in PWRCTRL */
|
|
setbits_le32(STM32_PWR_BASE + PWR_CR3, PWR_CR3_DDRRETEN);
|
|
|
|
/* Switch controller clocks (uMCTL2/PUBL) to DLL ref clock */
|
|
setbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, RCC_DDRITFCR_GSKPCTRL);
|
|
|
|
/* Disable all DLLs: GLITCH window */
|
|
setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACDLLCR, DDRPHYC_ACDLLCR_DLLDIS);
|
|
|
|
setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX0DLLCR, DDRPHYC_DXNDLLCR_DLLDIS);
|
|
|
|
setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX1DLLCR, DDRPHYC_DXNDLLCR_DLLDIS);
|
|
|
|
setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX2DLLCR, DDRPHYC_DXNDLLCR_DLLDIS);
|
|
|
|
setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX3DLLCR, DDRPHYC_DXNDLLCR_DLLDIS);
|
|
|
|
/* Switch controller clocks (uMCTL2/PUBL) to DLL output clock */
|
|
clrbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, RCC_DDRITFCR_GSKPCTRL);
|
|
|
|
/* Deactivate all DDR clocks */
|
|
clrbits_le32(STM32_RCC_BASE + RCC_DDRITFCR,
|
|
RCC_DDRITFCR_DDRC1EN | RCC_DDRITFCR_DDRC2EN |
|
|
RCC_DDRITFCR_DDRCAPBEN | RCC_DDRITFCR_DDRPHYCAPBEN);
|
|
|
|
return 0;
|
|
|
|
selfref_sw_failed:
|
|
/* This bit should be cleared to restore DDR in its previous state */
|
|
clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL,
|
|
DDRCTRL_PWRCTL_SELFREF_SW);
|
|
|
|
pstat_failed:
|
|
setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_0,
|
|
DDRCTRL_PCTRL_N_PORT_EN);
|
|
setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_1,
|
|
DDRCTRL_PCTRL_N_PORT_EN);
|
|
|
|
return -EINVAL;
|
|
};
|
|
|
|
static void __secure ddr_sw_self_refresh_exit(void)
|
|
{
|
|
int ret;
|
|
|
|
/* Enable all clocks */
|
|
setbits_le32(STM32_RCC_BASE + RCC_DDRITFCR,
|
|
RCC_DDRITFCR_DDRC1EN | RCC_DDRITFCR_DDRC2EN |
|
|
RCC_DDRITFCR_DDRPHYCEN | RCC_DDRITFCR_DDRPHYCAPBEN |
|
|
RCC_DDRITFCR_DDRCAPBEN);
|
|
|
|
/* Handshake */
|
|
clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_SWCTL, DDRCTRL_SWCTL_SW_DONE);
|
|
|
|
/* Mask dfi_init_complete_en */
|
|
clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_DFIMISC,
|
|
DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
|
|
|
|
/* Ack */
|
|
setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_SWCTL, DDRCTRL_SWCTL_SW_DONE);
|
|
ret = secure_waitbits(STM32_DDRCTRL_BASE + DDRCTRL_SWSTAT,
|
|
DDRCTRL_SWSTAT_SW_DONE_ACK,
|
|
DDRCTRL_SWSTAT_SW_DONE_ACK);
|
|
if (ret)
|
|
hang();
|
|
|
|
/* Switch controller clocks (uMCTL2/PUBL) to DLL ref clock */
|
|
setbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, RCC_DDRITFCR_GSKPCTRL);
|
|
|
|
/* Enable all DLLs: GLITCH window */
|
|
clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACDLLCR,
|
|
DDRPHYC_ACDLLCR_DLLDIS);
|
|
|
|
clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX0DLLCR, DDRPHYC_DXNDLLCR_DLLDIS);
|
|
|
|
clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX1DLLCR, DDRPHYC_DXNDLLCR_DLLDIS);
|
|
|
|
clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX2DLLCR, DDRPHYC_DXNDLLCR_DLLDIS);
|
|
|
|
clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX3DLLCR, DDRPHYC_DXNDLLCR_DLLDIS);
|
|
|
|
/* Additional delay to avoid early DLL clock switch */
|
|
secure_udelay(50);
|
|
|
|
/* Switch controller clocks (uMCTL2/PUBL) to DLL ref clock */
|
|
clrbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, RCC_DDRITFCR_GSKPCTRL);
|
|
|
|
clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACDLLCR, DDRPHYC_ACDLLCR_DLLSRST);
|
|
|
|
secure_udelay(10);
|
|
|
|
setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACDLLCR, DDRPHYC_ACDLLCR_DLLSRST);
|
|
|
|
/* PHY partial init: (DLL lock and ITM reset) */
|
|
writel(DDRPHYC_PIR_DLLSRST | DDRPHYC_PIR_DLLLOCK |
|
|
DDRPHYC_PIR_ITMSRST | DDRPHYC_PIR_INIT,
|
|
STM32_DDRPHYC_BASE + DDRPHYC_PIR);
|
|
|
|
/* Need to wait at least 10 clock cycles before accessing PGSR */
|
|
secure_udelay(1);
|
|
|
|
/* Pool end of init */
|
|
ret = secure_waitbits(STM32_DDRPHYC_BASE + DDRPHYC_PGSR,
|
|
DDRPHYC_PGSR_IDONE, DDRPHYC_PGSR_IDONE);
|
|
if (ret)
|
|
hang();
|
|
|
|
/* Handshake */
|
|
clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_SWCTL, DDRCTRL_SWCTL_SW_DONE);
|
|
|
|
/* Unmask dfi_init_complete_en to uMCTL2 */
|
|
setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_DFIMISC, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
|
|
|
|
/* Ack */
|
|
setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_SWCTL, DDRCTRL_SWCTL_SW_DONE);
|
|
ret = secure_waitbits(STM32_DDRCTRL_BASE + DDRCTRL_SWSTAT,
|
|
DDRCTRL_SWSTAT_SW_DONE_ACK,
|
|
DDRCTRL_SWSTAT_SW_DONE_ACK);
|
|
if (ret)
|
|
hang();
|
|
|
|
/* Deactivate sw retention in PWR */
|
|
clrbits_le32(STM32_PWR_BASE + PWR_CR3, PWR_CR3_DDRRETEN);
|
|
|
|
/* Enable PZQ cell (PUBL register) */
|
|
clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ZQ0CR0, DDRPHYC_ZQ0CRN_ZQPD);
|
|
|
|
/* Enable pad drivers */
|
|
clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_ACPDD);
|
|
|
|
/* Enable command/address output driver */
|
|
setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_ACOE);
|
|
|
|
clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_CKPDD_MASK);
|
|
|
|
clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_CSPDD_MASK);
|
|
|
|
clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DXCCR, DDRPHYC_DXCCR_DXPDD);
|
|
|
|
clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DXCCR, DDRPHYC_DXCCR_DXPDR);
|
|
|
|
/* Release latch */
|
|
setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_CKOE);
|
|
|
|
clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_ODTPDD_MASK);
|
|
|
|
clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_NL2PD);
|
|
|
|
clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_CKEPDD_MASK);
|
|
|
|
/* Remove selfrefresh */
|
|
clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL, DDRCTRL_PWRCTL_SELFREF_SW);
|
|
|
|
/* Wait operating_mode == normal */
|
|
ret = secure_waitbits(STM32_DDRCTRL_BASE + DDRCTRL_STAT,
|
|
DDRCTRL_STAT_OPERATING_MODE_MASK,
|
|
DDRCTRL_STAT_OPERATING_MODE_NORMAL);
|
|
if (ret)
|
|
hang();
|
|
|
|
/* AXI ports are no longer blocked from taking transactions */
|
|
setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_0, DDRCTRL_PCTRL_N_PORT_EN);
|
|
setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_1, DDRCTRL_PCTRL_N_PORT_EN);
|
|
|
|
setbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, RCC_DDRITFCR_AXIDCGEN);
|
|
}
|
|
|
|
void __secure psci_system_suspend(u32 __always_unused function_id,
|
|
u32 ep, u32 context_id)
|
|
{
|
|
u32 saved_mcudivr, saved_pll3cr, saved_pll4cr, saved_mssckselr;
|
|
u32 gicd_addr = stm32mp_get_gicd_base_address();
|
|
u32 cpu = psci_get_cpu_id();
|
|
u32 sp = (u32)__secure_stack_end - (cpu << ARM_PSCI_STACK_SHIFT);
|
|
bool iwdg1_wake = false;
|
|
bool iwdg2_wake = false;
|
|
bool other_wake = false;
|
|
u32 saved_pwrctl, reg;
|
|
u32 gic_enabled[8];
|
|
u32 irqs;
|
|
int i;
|
|
|
|
/* Cache enable mask of all 256 SPI */
|
|
for (i = 0; i < ARRAY_SIZE(gic_enabled); i++)
|
|
gic_enabled[i] = readl(gicd_addr + GICD_ISENABLERn + 0x4 + 4 * i);
|
|
|
|
/* Disable IO compensation */
|
|
|
|
/* Place current APSRC/ANSRC into RAPSRC/RANSRC */
|
|
reg = readl(STM32_SYSCFG_BASE + SYSCFG_CMPCR);
|
|
reg >>= 8;
|
|
reg &= 0xff << 16;
|
|
reg |= SYSCFG_CMPCR_SW_CTRL;
|
|
writel(reg, STM32_SYSCFG_BASE + SYSCFG_CMPCR);
|
|
writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENCLRR);
|
|
|
|
writel(RCC_MP_CIFR_WKUPF, STM32_RCC_BASE + RCC_MP_CIFR);
|
|
setbits_le32(STM32_RCC_BASE + RCC_MP_CIER, RCC_MP_CIFR_WKUPF);
|
|
|
|
setbits_le32(STM32_PWR_BASE + PWR_MPUCR,
|
|
PWR_MPUCR_CSSF | PWR_MPUCR_CSTDBYDIS);
|
|
|
|
saved_mcudivr = readl(STM32_RCC_BASE + RCC_MCUDIVR);
|
|
saved_pll3cr = readl(STM32_RCC_BASE + RCC_PLL3CR);
|
|
saved_pll4cr = readl(STM32_RCC_BASE + RCC_PLL4CR);
|
|
saved_mssckselr = readl(STM32_RCC_BASE + RCC_MSSCKSELR);
|
|
|
|
psci_v7_flush_dcache_all();
|
|
ddr_sr_mode_ssr(&saved_pwrctl);
|
|
ddr_sw_self_refresh_in();
|
|
setbits_le32(STM32_PWR_BASE + PWR_CR3, PWR_CR3_DDRSREN);
|
|
writel(0x3, STM32_RCC_BASE + RCC_MP_SREQSETR);
|
|
|
|
/* Ping the IWDG before entering suspend */
|
|
iwdg1_wake = !!(gic_enabled[4] & BIT(22)); /* SPI 150 */
|
|
iwdg2_wake = !!(gic_enabled[4] & BIT(23)); /* SPI 151 */
|
|
|
|
for (;;) {
|
|
/* Ping IWDG1 and ACK pretimer IRQ */
|
|
if (iwdg1_wake) {
|
|
writel(IWDG_KR_RELOAD_KEY, STM32_IWDG1_BASE + IWDG_KR);
|
|
writel(IWDG_EWCR_EWIC, STM32_IWDG1_BASE + IWDG_EWCR);
|
|
}
|
|
|
|
/* Ping IWDG2 and ACK pretimer IRQ */
|
|
if (iwdg2_wake) {
|
|
writel(IWDG_KR_RELOAD_KEY, STM32_IWDG2_BASE + IWDG_KR);
|
|
writel(IWDG_EWCR_EWIC, STM32_IWDG2_BASE + IWDG_EWCR);
|
|
}
|
|
|
|
iwdg1_wake = false;
|
|
iwdg2_wake = false;
|
|
|
|
/* Zzz, enter stop mode */
|
|
asm volatile(
|
|
"isb\n"
|
|
"dsb\n"
|
|
"wfi\n");
|
|
|
|
/* Determine the wake up source */
|
|
for (i = 0; i < ARRAY_SIZE(gic_enabled); i++) {
|
|
irqs = readl(gicd_addr + GICR_IGROUPMODRn + 0x4 + 4 * i);
|
|
irqs &= gic_enabled[i];
|
|
if (!irqs)
|
|
continue;
|
|
|
|
/* Test whether IWDG pretimeout triggered the wake up. */
|
|
if (i == 4) { /* SPI Num 128..159 */
|
|
iwdg1_wake = !!(irqs & BIT(22)); /* SPI 150 */
|
|
iwdg2_wake = !!(irqs & BIT(23)); /* SPI 151 */
|
|
irqs &= ~(BIT(22) | BIT(23));
|
|
}
|
|
|
|
/* Test whether there is any other wake up trigger. */
|
|
if (irqs) {
|
|
other_wake = true;
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Other wake up triggers pending, let OS deal with all of it. */
|
|
if (other_wake)
|
|
break;
|
|
}
|
|
|
|
writel(0x3, STM32_RCC_BASE + RCC_MP_SREQCLRR);
|
|
ddr_sw_self_refresh_exit();
|
|
ddr_sr_mode_restore(saved_pwrctl);
|
|
|
|
writel(saved_mcudivr, STM32_RCC_BASE + RCC_MCUDIVR);
|
|
writel(saved_pll3cr, STM32_RCC_BASE + RCC_PLL3CR);
|
|
writel(saved_pll4cr, STM32_RCC_BASE + RCC_PLL4CR);
|
|
writel(saved_mssckselr, STM32_RCC_BASE + RCC_MSSCKSELR);
|
|
|
|
writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENSETR);
|
|
clrbits_le32(STM32_SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
|
|
|
|
/*
|
|
* The system has resumed successfully. Rewrite LR register stored
|
|
* on stack with 'ep' value, so that on return from this PSCI call,
|
|
* the code would jump to that 'ep' resume entry point code path
|
|
* instead of the previous 'lr' register content which (e.g. with
|
|
* Linux) points to resume failure code path.
|
|
*
|
|
* See arch/arm/cpu/armv7/psci.S _smc_psci: for the stack layout
|
|
* used here, SP-4 is PC, SP-8 is LR, SP-12 is R7, and so on.
|
|
*/
|
|
writel(ep, sp - 8);
|
|
}
|