376 lines
9.6 KiB
C
376 lines
9.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
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/*
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* Copyright (C) 2021, STMicroelectronics - All Rights Reserved
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*/
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#define LOG_CATEGORY LOGC_ARCH
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#include <common.h>
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#include <env.h>
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#include <log.h>
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#include <asm/io.h>
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#include <asm/arch/bsec.h>
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#include <asm/arch/stm32.h>
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#include <asm/arch/sys_proto.h>
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#include <dm/device.h>
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#include <dm/uclass.h>
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#include <linux/bitfield.h>
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/* RCC register */
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#define RCC_TZCR (STM32_RCC_BASE + 0x00)
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#define RCC_BDCR (STM32_RCC_BASE + 0x0140)
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#define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208)
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#define RCC_MP_AHB5ENSETR (STM32_RCC_BASE + 0x0210)
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#define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
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#define RCC_BDCR_VSWRST BIT(31)
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#define RCC_BDCR_RTCSRC GENMASK(17, 16)
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#define RCC_DBGCFGR_DBGCKEN BIT(8)
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/* DBGMCU register */
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#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00)
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#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C)
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#define DBGMCU_APB4FZ1_IWDG2 BIT(2)
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/* Security register */
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#define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04)
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#define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10)
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#define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008)
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#define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110)
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#define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114)
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#define TAMP_CR1 (STM32_TAMP_BASE + 0x00)
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#define TAMP_SMCR (STM32_TAMP_BASE + 0x20)
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#define TAMP_SMCR_BKPRWDPROT GENMASK(7, 0)
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#define TAMP_SMCR_BKPWDPROT GENMASK(23, 16)
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#define PWR_CR1 (STM32_PWR_BASE + 0x00)
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#define PWR_MCUCR (STM32_PWR_BASE + 0x14)
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#define PWR_CR1_DBP BIT(8)
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#define PWR_MCUCR_SBF BIT(6)
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/* GPIOZ registers */
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#define GPIOZ_SECCFGR 0x54004030
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/* DBGMCU register */
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#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00)
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#define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0)
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#define DBGMCU_IDC_DEV_ID_SHIFT 0
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#define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16)
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#define DBGMCU_IDC_REV_ID_SHIFT 16
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/* boot interface from Bootrom
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* - boot instance = bit 31:16
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* - boot device = bit 15:0
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*/
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#define BOOTROM_PARAM_ADDR 0x2FFC0078
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#define BOOTROM_MODE_MASK GENMASK(15, 0)
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#define BOOTROM_MODE_SHIFT 0
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#define BOOTROM_INSTANCE_MASK GENMASK(31, 16)
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#define BOOTROM_INSTANCE_SHIFT 16
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/* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */
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#define RPN_SHIFT 0
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#define RPN_MASK GENMASK(7, 0)
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/* Package = bit 27:29 of OTP16 => STM32MP15_PKG defines
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* - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm
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* - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm
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* - 010: TFBGA361 (FFC) => AC = TFBGA 12x12mm 361 balls p. 0.5mm
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* - 001: TFBGA257 (LCC) => AD = TFBGA 10x10mm 257 balls p. 0.5mm
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* - others: Reserved
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*/
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#define PKG_SHIFT 27
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#define PKG_MASK GENMASK(2, 0)
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static void security_init(void)
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{
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/* Disable the backup domain write protection */
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/* the protection is enable at each reset by hardware */
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/* And must be disable by software */
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setbits_le32(PWR_CR1, PWR_CR1_DBP);
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while (!(readl(PWR_CR1) & PWR_CR1_DBP))
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;
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/* If RTC clock isn't enable so this is a cold boot then we need
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* to reset the backup domain
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*/
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if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) {
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setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
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while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST))
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;
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clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
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}
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/* allow non secure access in Write/Read for all peripheral */
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writel(GENMASK(25, 0), ETZPC_DECPROT0);
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/* Open SYSRAM for no secure access */
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writel(0x0, ETZPC_TZMA1_SIZE);
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/* enable TZC1 TZC2 clock */
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writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR);
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/* Region 0 set to no access by default */
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/* bit 0 / 16 => nsaid0 read/write Enable
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* bit 1 / 17 => nsaid1 read/write Enable
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* ...
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* bit 15 / 31 => nsaid15 read/write Enable
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*/
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writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0);
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/* bit 30 / 31 => Secure Global Enable : write/read */
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/* bit 0 / 1 => Region Enable for filter 0/1 */
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writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0);
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/* Enable Filter 0 and 1 */
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setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1));
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/* RCC trust zone deactivated */
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writel(0x0, RCC_TZCR);
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/* TAMP: deactivate the internal tamper
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* Bit 23 ITAMP8E: monotonic counter overflow
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* Bit 20 ITAMP5E: RTC calendar overflow
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* Bit 19 ITAMP4E: HSE monitoring
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* Bit 18 ITAMP3E: LSE monitoring
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* Bit 16 ITAMP1E: RTC power domain supply monitoring
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*/
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writel(0x0, TAMP_CR1);
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/*
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* TAMP: Configure non-zero secure protection settings. This is
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* checked by BootROM function 35ac on OTP-CLOSED device during
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* CPU core 1 release from endless loop. If secure protection
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* fields are zero, the core 1 is not released from endless
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* loop on second SGI0.
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*/
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clrsetbits_le32(TAMP_SMCR,
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TAMP_SMCR_BKPRWDPROT | TAMP_SMCR_BKPWDPROT,
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FIELD_PREP(TAMP_SMCR_BKPRWDPROT, 0x20) |
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FIELD_PREP(TAMP_SMCR_BKPWDPROT, 0x20));
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/* GPIOZ: deactivate the security */
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writel(BIT(0), RCC_MP_AHB5ENSETR);
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writel(0x0, GPIOZ_SECCFGR);
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}
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/*
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* Debug init
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*/
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void dbgmcu_init(void)
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{
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/*
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* Freeze IWDG2 if Cortex-A7 is in debug mode
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* done in TF-A for TRUSTED boot and
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* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE
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*/
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if (bsec_dbgswenable()) {
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setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
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setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
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}
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}
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void spl_board_init(void)
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{
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struct udevice *dev;
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int ret;
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dbgmcu_init();
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/* force probe of BSEC driver to shadow the upper OTP */
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ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(stm32mp_bsec), &dev);
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if (ret)
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log_warning("BSEC probe failed: %d\n", ret);
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}
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/* get bootmode from ROM code boot context: saved in TAMP register */
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static void update_bootmode(void)
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{
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u32 boot_mode;
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u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR);
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u32 bootrom_device, bootrom_instance;
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/* enable TAMP clock = RTCAPBEN */
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writel(BIT(8), RCC_MP_APB5ENSETR);
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/* read bootrom context */
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bootrom_device =
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(bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT;
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bootrom_instance =
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(bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT;
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boot_mode =
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((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) |
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((bootrom_instance << BOOT_INSTANCE_SHIFT) &
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BOOT_INSTANCE_MASK);
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/* save the boot mode in TAMP backup register */
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clrsetbits_le32(TAMP_BOOT_CONTEXT,
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TAMP_BOOT_MODE_MASK,
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boot_mode << TAMP_BOOT_MODE_SHIFT);
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}
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/* weak function: STM32MP15x mach init for boot without TFA */
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void stm32mp_cpu_init(void)
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{
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if (IS_ENABLED(CONFIG_SPL_BUILD)) {
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security_init();
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update_bootmode();
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}
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/* reset copro state in SPL, when used, or in U-Boot */
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if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_SPL_BUILD)) {
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/* Reset Coprocessor state unless it wakes up from Standby power mode */
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if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) {
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writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE);
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writel(0, TAMP_COPRO_RSC_TBL_ADDRESS);
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}
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}
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}
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static u32 read_idc(void)
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{
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/* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE */
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if (bsec_dbgswenable()) {
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setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
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return readl(DBGMCU_IDC);
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}
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return CPU_DEV_STM32MP15; /* STM32MP15x and unknown revision */
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}
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u32 get_cpu_dev(void)
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{
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return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
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}
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u32 get_cpu_rev(void)
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{
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return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
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}
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/* Get Device Part Number (RPN) from OTP */
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static u32 get_cpu_rpn(void)
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{
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return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
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}
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u32 get_cpu_type(void)
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{
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return (get_cpu_dev() << 16) | get_cpu_rpn();
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}
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int get_eth_nb(void)
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{
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return 1;
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}
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/* Get Package options from OTP */
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u32 get_cpu_package(void)
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{
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return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
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}
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static const char * const soc_type[] = {
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"????",
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"151C", "151A", "151F", "151D",
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"153C", "153A", "153F", "153D",
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"157C", "157A", "157F", "157D"
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};
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static const char * const soc_pkg[] = { "??", "AD", "AC", "AB", "AA" };
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static const char * const soc_rev[] = { "?", "A", "B", "Z", "Y"};
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static void get_cpu_string_offsets(unsigned int *type, unsigned int *pkg,
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unsigned int *rev)
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{
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u32 cpu_type = get_cpu_type();
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u32 ct = cpu_type & ~(BIT(7) | BIT(0));
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u32 cm = ((cpu_type & BIT(7)) >> 6) | (cpu_type & BIT(0));
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/* Bits 0 and 7 are the ACDF, 00:C 01:A 10:F 11:D */
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switch (ct) {
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case CPU_STM32MP151Cxx:
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*type = cm + 1;
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break;
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case CPU_STM32MP153Cxx:
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*type = cm + 5;
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break;
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case CPU_STM32MP157Cxx:
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*type = cm + 9;
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break;
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default:
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*type = 0;
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break;
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}
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/* Package */
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*pkg = get_cpu_package();
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if (*pkg > STM32MP15_PKG_AA_LBGA448)
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*pkg = STM32MP15_PKG_UNKNOWN;
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/* Revision */
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switch (get_cpu_rev()) {
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case CPU_REV1:
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*rev = 1;
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break;
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case CPU_REV2:
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*rev = 2;
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break;
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case CPU_REV2_1:
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*rev = 3;
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break;
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case CPU_REV2_2:
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*rev = 4;
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break;
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default:
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*rev = 0;
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break;
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}
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}
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void get_soc_name(char name[SOC_NAME_SIZE])
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{
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unsigned int type, pkg, rev;
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get_cpu_string_offsets(&type, &pkg, &rev);
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if (bsec_dbgswenable()) {
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snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s",
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soc_type[type], soc_pkg[pkg], soc_rev[rev]);
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} else {
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/*
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* SoC revision is only accessible via DBUMCU IDC register,
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* which requires BSEC.DENABLE DBGSWENABLE bit to be set to
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* make the register accessible, otherwise an access to the
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* register triggers bus fault. As BSEC.DBGSWENABLE is zero
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* in case of an OTP-CLOSED system, do NOT set DBGSWENABLE
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* bit as this might open a brief window for timing attacks.
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* Instead, report that this system is OTP-CLOSED and do not
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* report any SoC revision to avoid confusing users.
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*/
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snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s SEC/C",
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soc_type[type], soc_pkg[pkg]);
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}
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}
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static void setup_soc_type_pkg_rev(void)
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{
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unsigned int type, pkg, rev;
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get_cpu_string_offsets(&type, &pkg, &rev);
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env_set("soc_type", soc_type[type]);
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env_set("soc_pkg", soc_pkg[pkg]);
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env_set("soc_rev", soc_rev[rev]);
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}
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/* weak function called in arch_misc_init */
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void stm32mp_misc_init(void)
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{
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setup_soc_type_pkg_rev();
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}
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