1bc4e8eb1d
USB gadget is not working fully as expected on RK3328, it uses a board_usb_init() function to initialize the DWC2 OTG port. The board_usb_init() function does not intgrate with the generic phy framework and as a result the USB phy is not properly configured before or after USB gadget use. Having both USB_DWC2 and DWC2_OTG enabled for the same board is also causing some issues. Trying to use rockusb or ums command after usb stop result in a freeze due to usb stop is putting the phy in a suspended state. => usb start => usb stop => ums 0 mmc 0 --> freeze due to usb phy is suspended <-- Fix this by only using one of USB_DWC2 (host) or DWC2_OTG (peripheral) depending on the most likely usage of the otg port and by migrating to use DM_USB_GADGET instead of a board_usb_init() function. The nanopi-r2 and orangepi-r1-plus variants share OTG and power using a Type-C connector, mark these boards dr_mode as peripheral, the most likely usage is for recovery and image download. The rock64 and roc-cc currently use dr_mode as host, remove the DWC2_OTG driver from these boards to ensure that the USB_DWC2 driver is used. The rock-pi-e board does not enable the usb20_otg node so both USB_DWC2 and DWC2_OTG is removed from this board. Enable RockUSB and UMS on all boards with a otg port in peripheral mode. Also with the migration to DM_USB_GADGET completed the U-Boot specific change to reorder usb nodes in the soc device tree can be reverted. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
100 lines
2.4 KiB
Plaintext
100 lines
2.4 KiB
Plaintext
CONFIG_ARM=y
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CONFIG_SKIP_LOWLEVEL_INIT=y
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CONFIG_COUNTER_FREQUENCY=24000000
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_SPL_GPIO=y
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_SF_DEFAULT_SPEED=20000000
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CONFIG_ENV_OFFSET=0x3F8000
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CONFIG_DEFAULT_DEVICE_TREE="rk3328-roc-cc"
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CONFIG_DM_RESET=y
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CONFIG_ROCKCHIP_RK3328=y
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CONFIG_DEBUG_UART_BASE=0xFF130000
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CONFIG_DEBUG_UART_CLOCK=24000000
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CONFIG_SYS_LOAD_ADDR=0x800800
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CONFIG_DEBUG_UART=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_SPL_FIT_SIGNATURE=y
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CONFIG_SPL_LOAD_FIT=y
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CONFIG_LEGACY_IMAGE_FORMAT=y
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CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-roc-cc.dtb"
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# CONFIG_DISPLAY_CPUINFO is not set
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CONFIG_DISPLAY_BOARDINFO_LATE=y
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CONFIG_SPL_MAX_SIZE=0x40000
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CONFIG_SPL_PAD_TO=0x7f8000
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# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
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CONFIG_SPL_POWER=y
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CONFIG_SPL_ATF=y
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CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
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CONFIG_CMD_BOOTZ=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_GPT=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_POWEROFF=y
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CONFIG_CMD_USB=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_TIME=y
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CONFIG_CMD_REGULATOR=y
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CONFIG_SPL_OF_CONTROL=y
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CONFIG_TPL_OF_CONTROL=y
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CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
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CONFIG_TPL_OF_PLATDATA=y
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CONFIG_ENV_IS_IN_MMC=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_SYS_MMC_ENV_DEV=1
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CONFIG_TPL_DM=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_REGMAP=y
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CONFIG_SPL_REGMAP=y
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CONFIG_TPL_REGMAP=y
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CONFIG_SYSCON=y
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CONFIG_SPL_SYSCON=y
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CONFIG_TPL_SYSCON=y
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CONFIG_CLK=y
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CONFIG_SPL_CLK=y
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CONFIG_ROCKCHIP_GPIO=y
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CONFIG_SYS_I2C_ROCKCHIP=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_PHY_REALTEK=y
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CONFIG_DM_ETH_PHY=y
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CONFIG_PHY_GIGE=y
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_GMAC_ROCKCHIP=y
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CONFIG_PHY_ROCKCHIP_INNO_USB2=y
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CONFIG_PINCTRL=y
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CONFIG_SPL_PINCTRL=y
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CONFIG_DM_PMIC=y
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CONFIG_PMIC_RK8XX=y
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CONFIG_SPL_DM_REGULATOR=y
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CONFIG_DM_REGULATOR_FIXED=y
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CONFIG_SPL_DM_REGULATOR_FIXED=y
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CONFIG_DM_REGULATOR_GPIO=y
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CONFIG_REGULATOR_RK8XX=y
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CONFIG_PWM_ROCKCHIP=y
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CONFIG_RAM=y
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CONFIG_SPL_RAM=y
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CONFIG_TPL_RAM=y
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CONFIG_DM_RNG=y
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CONFIG_RNG_ROCKCHIP=y
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CONFIG_BAUDRATE=1500000
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CONFIG_DEBUG_UART_SHIFT=2
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CONFIG_SYS_NS16550_MEM32=y
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CONFIG_SYSINFO=y
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CONFIG_SYSINFO_SMBIOS=y
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CONFIG_SYSRESET=y
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# CONFIG_TPL_SYSRESET is not set
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CONFIG_USB=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_EHCI_GENERIC=y
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CONFIG_USB_OHCI_HCD=y
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CONFIG_USB_OHCI_GENERIC=y
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CONFIG_USB_DWC2=y
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CONFIG_USB_DWC3=y
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CONFIG_USB_DWC3_GENERIC=y
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CONFIG_SPL_TINY_MEMSET=y
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CONFIG_TPL_TINY_MEMSET=y
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CONFIG_ERRNO_STR=y
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