326 lines
8.7 KiB
C
326 lines
8.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2024, Marek Vasut <marex@denx.de>
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*
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* This is code moved from drivers/net/dwc_eth_qos.c , which is:
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* Copyright (c) 2016, NVIDIA CORPORATION.
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*/
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#include <asm/cache.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <clk.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <errno.h>
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#include <eth_phy.h>
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#include <log.h>
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#include <malloc.h>
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#include <memalign.h>
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#include <miiphy.h>
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#include <net.h>
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#include <netdev.h>
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#include <phy.h>
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#include <regmap.h>
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#include <reset.h>
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#include <syscon.h>
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#include <wait_bit.h>
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#include <linux/bitfield.h>
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#include <linux/delay.h>
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#include "dwc_eth_qos.h"
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/* SYSCFG registers */
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#define SYSCFG_PMCSETR 0x04
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#define SYSCFG_PMCCLRR_MP13 0x08
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#define SYSCFG_PMCCLRR_MP15 0x44
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#define SYSCFG_PMCSETR_ETH1_MASK GENMASK(23, 16)
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#define SYSCFG_PMCSETR_ETH2_MASK GENMASK(31, 24)
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#define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16)
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#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17)
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/* STM32MP15xx specific bit */
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#define SYSCFG_PMCSETR_ETH_SELMII BIT(20)
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#define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21)
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#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0x0
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#define SYSCFG_PMCSETR_ETH_SEL_RGMII 0x1
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#define SYSCFG_PMCSETR_ETH_SEL_RMII 0x4
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static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev)
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{
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struct eqos_priv __maybe_unused *eqos = dev_get_priv(dev);
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if (!CONFIG_IS_ENABLED(CLK))
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return 0;
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return clk_get_rate(&eqos->clk_master_bus);
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}
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static int eqos_start_clks_stm32(struct udevice *dev)
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{
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struct eqos_priv __maybe_unused *eqos = dev_get_priv(dev);
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int ret;
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if (!CONFIG_IS_ENABLED(CLK))
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return 0;
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dev_dbg(dev, "%s:\n", __func__);
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ret = clk_enable(&eqos->clk_master_bus);
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if (ret < 0) {
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dev_err(dev, "clk_enable(clk_master_bus) failed: %d\n", ret);
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goto err;
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}
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ret = clk_enable(&eqos->clk_rx);
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if (ret < 0) {
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dev_err(dev, "clk_enable(clk_rx) failed: %d\n", ret);
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goto err_disable_clk_master_bus;
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}
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ret = clk_enable(&eqos->clk_tx);
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if (ret < 0) {
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dev_err(dev, "clk_enable(clk_tx) failed: %d\n", ret);
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goto err_disable_clk_rx;
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}
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if (clk_valid(&eqos->clk_ck) && !eqos->clk_ck_enabled) {
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ret = clk_enable(&eqos->clk_ck);
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if (ret < 0) {
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dev_err(dev, "clk_enable(clk_ck) failed: %d\n", ret);
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goto err_disable_clk_tx;
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}
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eqos->clk_ck_enabled = true;
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}
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dev_dbg(dev, "%s: OK\n", __func__);
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return 0;
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err_disable_clk_tx:
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clk_disable(&eqos->clk_tx);
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err_disable_clk_rx:
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clk_disable(&eqos->clk_rx);
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err_disable_clk_master_bus:
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clk_disable(&eqos->clk_master_bus);
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err:
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dev_dbg(dev, "%s: FAILED: %d\n", __func__, ret);
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return ret;
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}
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static int eqos_stop_clks_stm32(struct udevice *dev)
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{
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struct eqos_priv __maybe_unused *eqos = dev_get_priv(dev);
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if (!CONFIG_IS_ENABLED(CLK))
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return 0;
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dev_dbg(dev, "%s:\n", __func__);
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clk_disable(&eqos->clk_tx);
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clk_disable(&eqos->clk_rx);
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clk_disable(&eqos->clk_master_bus);
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dev_dbg(dev, "%s: OK\n", __func__);
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return 0;
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}
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static int eqos_probe_syscfg_stm32(struct udevice *dev,
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phy_interface_t interface_type)
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{
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/* Ethernet 50MHz RMII clock selection. */
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const bool eth_ref_clk_sel = dev_read_bool(dev, "st,eth-ref-clk-sel");
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/* SoC is STM32MP13xx with two ethernet MACs */
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const bool is_mp13 = device_is_compatible(dev, "st,stm32mp13-dwmac");
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/* Gigabit Ethernet 125MHz clock selection. */
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const bool eth_clk_sel = dev_read_bool(dev, "st,eth-clk-sel");
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/* Ethernet clock source is RCC. */
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const bool ext_phyclk = dev_read_bool(dev, "st,ext-phyclk");
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struct regmap *regmap;
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u32 regmap_mask;
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u32 value;
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regmap = syscon_regmap_lookup_by_phandle(dev, "st,syscon");
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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regmap_mask = dev_read_u32_index_default(dev, "st,syscon", 2,
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SYSCFG_PMCSETR_ETH1_MASK);
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switch (interface_type) {
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case PHY_INTERFACE_MODE_MII:
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dev_dbg(dev, "PHY_INTERFACE_MODE_MII\n");
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value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
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SYSCFG_PMCSETR_ETH_SEL_GMII_MII);
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/*
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* STM32MP15xx supports both MII and GMII, STM32MP13xx MII only.
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* SYSCFG_PMCSETR ETH_SELMII is present only on STM32MP15xx and
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* acts as a selector between 0:GMII and 1:MII. As STM32MP13xx
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* supports only MII, ETH_SELMII is not present.
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*/
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if (!is_mp13) /* Select MII mode on STM32MP15xx */
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value |= SYSCFG_PMCSETR_ETH_SELMII;
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break;
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case PHY_INTERFACE_MODE_GMII: /* STM32MP15xx only */
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dev_dbg(dev, "PHY_INTERFACE_MODE_GMII\n");
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value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
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SYSCFG_PMCSETR_ETH_SEL_GMII_MII);
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/*
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* If eth_clk_sel is set, use internal ETH_CLKx clock from RCC,
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* otherwise use external clock from IO pin (requires matching
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* GPIO block AF setting of that pin).
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*/
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if (eth_clk_sel || ext_phyclk)
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value |= SYSCFG_PMCSETR_ETH_CLK_SEL;
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break;
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case PHY_INTERFACE_MODE_RMII:
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dev_dbg(dev, "PHY_INTERFACE_MODE_RMII\n");
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value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
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SYSCFG_PMCSETR_ETH_SEL_RMII);
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/*
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* If eth_ref_clk_sel is set, use internal clock from RCC,
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* otherwise use external clock from ETHn_RX_CLK/ETHn_REF_CLK
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* IO pin (requires matching GPIO block AF setting of that
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* pin).
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*/
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if (eth_ref_clk_sel || ext_phyclk)
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value |= SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
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break;
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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dev_dbg(dev, "PHY_INTERFACE_MODE_RGMII\n");
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value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
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SYSCFG_PMCSETR_ETH_SEL_RGMII);
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/*
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* If eth_clk_sel is set, use internal ETH_CLKx clock from RCC,
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* otherwise use external clock from ETHx_CLK125 pin (requires
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* matching GPIO block AF setting of that pin).
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*/
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if (eth_clk_sel || ext_phyclk)
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value |= SYSCFG_PMCSETR_ETH_CLK_SEL;
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break;
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default:
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dev_dbg(dev, "Do not manage %d interface\n",
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interface_type);
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/* Do not manage others interfaces */
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return -EINVAL;
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}
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/* Shift value at correct ethernet MAC offset in SYSCFG_PMCSETR */
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value <<= ffs(regmap_mask) - ffs(SYSCFG_PMCSETR_ETH1_MASK);
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/* Update PMCCLRR (clear register) */
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regmap_write(regmap, is_mp13 ?
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SYSCFG_PMCCLRR_MP13 : SYSCFG_PMCCLRR_MP15,
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regmap_mask);
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return regmap_update_bits(regmap, SYSCFG_PMCSETR, regmap_mask, value);
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}
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static int eqos_probe_resources_stm32(struct udevice *dev)
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{
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struct eqos_priv *eqos = dev_get_priv(dev);
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phy_interface_t interface;
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int ret;
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dev_dbg(dev, "%s:\n", __func__);
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interface = eqos->config->interface(dev);
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if (interface == PHY_INTERFACE_MODE_NA) {
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dev_err(dev, "Invalid PHY interface\n");
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return -EINVAL;
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}
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ret = eqos_probe_syscfg_stm32(dev, interface);
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if (ret)
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return -EINVAL;
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ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
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if (ret) {
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dev_err(dev, "clk_get_by_name(master_bus) failed: %d\n", ret);
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goto err_probe;
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}
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ret = clk_get_by_name(dev, "mac-clk-rx", &eqos->clk_rx);
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if (ret) {
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dev_err(dev, "clk_get_by_name(rx) failed: %d\n", ret);
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goto err_probe;
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}
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ret = clk_get_by_name(dev, "mac-clk-tx", &eqos->clk_tx);
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if (ret) {
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dev_err(dev, "clk_get_by_name(tx) failed: %d\n", ret);
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goto err_probe;
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}
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/* Get ETH_CLK clocks (optional) */
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ret = clk_get_by_name(dev, "eth-ck", &eqos->clk_ck);
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if (ret)
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dev_warn(dev, "No phy clock provided %d\n", ret);
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dev_dbg(dev, "%s: OK\n", __func__);
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return 0;
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err_probe:
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dev_dbg(dev, "%s: returns %d\n", __func__, ret);
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return ret;
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}
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static int eqos_remove_resources_stm32(struct udevice *dev)
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{
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dev_dbg(dev, "%s:\n", __func__);
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return 0;
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}
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static struct eqos_ops eqos_stm32_ops = {
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.eqos_inval_desc = eqos_inval_desc_generic,
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.eqos_flush_desc = eqos_flush_desc_generic,
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.eqos_inval_buffer = eqos_inval_buffer_generic,
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.eqos_flush_buffer = eqos_flush_buffer_generic,
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.eqos_probe_resources = eqos_probe_resources_stm32,
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.eqos_remove_resources = eqos_remove_resources_stm32,
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.eqos_stop_resets = eqos_null_ops,
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.eqos_start_resets = eqos_null_ops,
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.eqos_stop_clks = eqos_stop_clks_stm32,
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.eqos_start_clks = eqos_start_clks_stm32,
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.eqos_calibrate_pads = eqos_null_ops,
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.eqos_disable_calibration = eqos_null_ops,
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.eqos_set_tx_clk_speed = eqos_null_ops,
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.eqos_get_enetaddr = eqos_null_ops,
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.eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32
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};
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struct eqos_config __maybe_unused eqos_stm32mp13_config = {
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.reg_access_always_ok = false,
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.mdio_wait = 10000,
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.swr_wait = 50,
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.config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
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.config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
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.axi_bus_width = EQOS_AXI_WIDTH_32,
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.interface = dev_read_phy_mode,
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.ops = &eqos_stm32_ops
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};
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struct eqos_config __maybe_unused eqos_stm32mp15_config = {
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.reg_access_always_ok = false,
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.mdio_wait = 10000,
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.swr_wait = 50,
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.config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV,
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.config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
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.axi_bus_width = EQOS_AXI_WIDTH_64,
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.interface = dev_read_phy_mode,
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.ops = &eqos_stm32_ops
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};
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