451b2ea211
Enable SPL and binman to generate u-boot.img (machine mode) and u-boot.itb (supervisor mode). DTB is placed at fixed address to ensure that it is 8 byte aligned which is not ensured when dtb is attached behind SPL binary that's why SPL and U-Boot are taking DTB from the same address. Also align addresses for both defconfigs. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/85506bce5580d448f095f267d029e3932c5e9990.1707911544.git.michal.simek@amd.com
48 lines
1.3 KiB
Plaintext
48 lines
1.3 KiB
Plaintext
CONFIG_RISCV=y
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CONFIG_SYS_MALLOC_LEN=0xe00000
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x21200000
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CONFIG_ENV_SIZE=0x20000
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CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32"
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CONFIG_SPL_STACK=0x20200000
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CONFIG_SPL_SIZE_LIMIT=0x40000
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CONFIG_SPL=y
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CONFIG_DEBUG_UART_BASE=0x40600000
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CONFIG_DEBUG_UART_CLOCK=1000000
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CONFIG_SYS_CLK_FREQ=100000000
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CONFIG_BOOT_SCRIPT_OFFSET=0x0
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CONFIG_SYS_LOAD_ADDR=0x20200000
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CONFIG_TARGET_XILINX_MBV=y
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CONFIG_SPL_OPENSBI_LOAD_ADDR=0x20100000
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CONFIG_RISCV_SMODE=y
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# CONFIG_SPL_SMP is not set
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CONFIG_REMAKE_ELF=y
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CONFIG_FIT=y
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CONFIG_SPL_LOAD_FIT_ADDRESS=0x20200000
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CONFIG_DISTRO_DEFAULTS=y
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CONFIG_DISPLAY_CPUINFO=y
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CONFIG_DISPLAY_BOARDINFO=y
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# CONFIG_BOARD_LATE_INIT is not set
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CONFIG_SPL_MAX_SIZE=0x40000
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CONFIG_SPL_BSS_START_ADDR=0x24000000
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CONFIG_SPL_BSS_MAX_SIZE=0x80000
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# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
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CONFIG_SPL_SYS_MALLOC=y
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CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
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CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x2
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# CONFIG_CMD_MII is not set
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CONFIG_CMD_TIMER=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_DM_MTD=y
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CONFIG_DEBUG_UART_UARTLITE=y
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CONFIG_DEBUG_UART_ANNOUNCE=y
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CONFIG_DEBUG_UART_SKIP_INIT=y
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CONFIG_XILINX_UARTLITE=y
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# CONFIG_RISCV_TIMER is not set
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CONFIG_XILINX_TIMER=y
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# CONFIG_BINMAN_FDT is not set
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CONFIG_PANIC_HANG=y
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CONFIG_SPL_GZIP=y
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