279 lines
7.6 KiB
YAML
279 lines
7.6 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/msm/qcom,msm8998-mdss.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm MSM8998 Display MDSS
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maintainers:
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- AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
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description:
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Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
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sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
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bindings of MDSS are mentioned for MSM8998 target.
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$ref: /schemas/display/msm/mdss-common.yaml#
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properties:
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compatible:
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const: qcom,msm8998-mdss
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clocks:
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items:
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- description: Display AHB clock
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- description: Display AXI clock
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- description: Display core clock
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clock-names:
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items:
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- const: iface
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- const: bus
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- const: core
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iommus:
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maxItems: 1
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patternProperties:
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"^display-controller@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: qcom,msm8998-dpu
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"^dsi@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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items:
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- const: qcom,msm8998-dsi-ctrl
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- const: qcom,mdss-dsi-ctrl
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"^phy@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: qcom,dsi-phy-10nm-8998
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required:
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- compatible
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,mmcc-msm8998.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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display-subsystem@c900000 {
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compatible = "qcom,msm8998-mdss";
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reg = <0x0c900000 0x1000>;
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reg-names = "mdss";
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clocks = <&mmcc MDSS_AHB_CLK>,
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<&mmcc MDSS_AXI_CLK>,
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<&mmcc MDSS_MDP_CLK>;
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clock-names = "iface", "bus", "core";
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#address-cells = <1>;
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#interrupt-cells = <1>;
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#size-cells = <1>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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iommus = <&mmss_smmu 0>;
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power-domains = <&mmcc MDSS_GDSC>;
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ranges;
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display-controller@c901000 {
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compatible = "qcom,msm8998-dpu";
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reg = <0x0c901000 0x8f000>,
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<0x0c9a8e00 0xf0>,
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<0x0c9b0000 0x2008>,
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<0x0c9b8000 0x1040>;
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reg-names = "mdp", "regdma", "vbif", "vbif_nrt";
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clocks = <&mmcc MDSS_AHB_CLK>,
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<&mmcc MDSS_AXI_CLK>,
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<&mmcc MNOC_AHB_CLK>,
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<&mmcc MDSS_MDP_CLK>,
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<&mmcc MDSS_VSYNC_CLK>;
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clock-names = "iface", "bus", "mnoc", "core", "vsync";
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interrupt-parent = <&mdss>;
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interrupts = <0>;
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operating-points-v2 = <&mdp_opp_table>;
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power-domains = <&rpmpd MSM8998_VDDMX>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dpu_intf1_out: endpoint {
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remote-endpoint = <&dsi0_in>;
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};
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};
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port@1 {
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reg = <1>;
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dpu_intf2_out: endpoint {
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remote-endpoint = <&dsi1_in>;
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};
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};
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};
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};
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dsi@c994000 {
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compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
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reg = <0x0c994000 0x400>;
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reg-names = "dsi_ctrl";
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interrupt-parent = <&mdss>;
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interrupts = <4>;
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clocks = <&mmcc MDSS_BYTE0_CLK>,
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<&mmcc MDSS_BYTE0_INTF_CLK>,
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<&mmcc MDSS_PCLK0_CLK>,
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<&mmcc MDSS_ESC0_CLK>,
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<&mmcc MDSS_AHB_CLK>,
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<&mmcc MDSS_AXI_CLK>;
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clock-names = "byte",
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"byte_intf",
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"pixel",
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"core",
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"iface",
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"bus";
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assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
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assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
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operating-points-v2 = <&dsi_opp_table>;
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power-domains = <&rpmpd MSM8998_VDDCX>;
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phys = <&dsi0_phy>;
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phy-names = "dsi";
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#address-cells = <1>;
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#size-cells = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dsi0_in: endpoint {
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remote-endpoint = <&dpu_intf1_out>;
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};
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};
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port@1 {
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reg = <1>;
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dsi0_out: endpoint {
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};
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};
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};
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};
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dsi0_phy: phy@c994400 {
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compatible = "qcom,dsi-phy-10nm-8998";
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reg = <0x0c994400 0x200>,
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<0x0c994600 0x280>,
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<0x0c994a00 0x1e0>;
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reg-names = "dsi_phy",
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"dsi_phy_lane",
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"dsi_pll";
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#clock-cells = <1>;
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#phy-cells = <0>;
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clocks = <&mmcc MDSS_AHB_CLK>,
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<&rpmcc RPM_SMD_XO_CLK_SRC>;
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clock-names = "iface", "ref";
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vdds-supply = <&pm8998_l1>;
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};
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dsi@c996000 {
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compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
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reg = <0x0c996000 0x400>;
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reg-names = "dsi_ctrl";
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interrupt-parent = <&mdss>;
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interrupts = <5>;
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clocks = <&mmcc MDSS_BYTE1_CLK>,
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<&mmcc MDSS_BYTE1_INTF_CLK>,
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<&mmcc MDSS_PCLK1_CLK>,
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<&mmcc MDSS_ESC1_CLK>,
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<&mmcc MDSS_AHB_CLK>,
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<&mmcc MDSS_AXI_CLK>;
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clock-names = "byte",
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"byte_intf",
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"pixel",
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"core",
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"iface",
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"bus";
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assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
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assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
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operating-points-v2 = <&dsi_opp_table>;
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power-domains = <&rpmpd MSM8998_VDDCX>;
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phys = <&dsi1_phy>;
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phy-names = "dsi";
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#address-cells = <1>;
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#size-cells = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dsi1_in: endpoint {
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remote-endpoint = <&dpu_intf2_out>;
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};
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};
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port@1 {
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reg = <1>;
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dsi1_out: endpoint {
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};
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};
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};
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};
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dsi1_phy: phy@c996400 {
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compatible = "qcom,dsi-phy-10nm-8998";
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reg = <0x0c996400 0x200>,
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<0x0c996600 0x280>,
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<0x0c996a00 0x10e>;
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reg-names = "dsi_phy",
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"dsi_phy_lane",
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"dsi_pll";
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#clock-cells = <1>;
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#phy-cells = <0>;
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clocks = <&mmcc MDSS_AHB_CLK>,
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<&rpmcc RPM_SMD_XO_CLK_SRC>;
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clock-names = "iface", "ref";
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vdds-supply = <&pm8998_l1>;
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};
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};
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...
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