f01a399203
With the stack and text base used by U-Boot SPL and proper on RK3328 there is a high likelihood of overlapping when U-Boot proper + FDT nears or exceeded 1 MiB in size. Currently the following memory layout is typically used on RK3328: [ 0, 256K) - SPL binary [ 256K, 2M) - TF-A / reserved [ 2M, +X) - U-Boot proper binary (TEXT_BASE) [ -X, 3M) - U-Boot proper pre-reloc stack (CUSTOM_SYS_INIT_SP_ADDR) [ -8K, 3M) - pre-reloc malloc heap (SYS_MALLOC_F_LEN) [ -X, 4M) - SPL pre-reloc stack (SPL_STACK) [ -8K, 4M) - pre-reloc malloc heap (SPL_SYS_MALLOC_F_LEN) [ -X, 6M) - SPL reloc stack (SPL_STACK_R_ADDR) [ 5M, 6M) - reloc malloc heap (SPL_STACK_R_MALLOC_SIMPLE_LEN) [ 32M, +8K) - SPL bss (SPL_BSS_START_ADDR, SPL_BSS_MAX_SIZE) SPL can safely load U-Boot proper + FDT to [2M, 4M-8K) with this layout. However, the stack at [-X, 3M) used during U-Boot proper pre-reloc is restricting the safe size of U-Boot proper + FDT to be less than 1 MiB. Migrate to use common bss, stack and malloc heap size and addresses to fix this restriction and allow for a larger U-Boot proper image size. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
107 lines
2.6 KiB
Plaintext
107 lines
2.6 KiB
Plaintext
CONFIG_ARM=y
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CONFIG_SKIP_LOWLEVEL_INIT=y
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CONFIG_COUNTER_FREQUENCY=24000000
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_SPL_GPIO=y
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_SF_DEFAULT_SPEED=20000000
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CONFIG_ENV_OFFSET=0x3F8000
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CONFIG_DEFAULT_DEVICE_TREE="rk3328-roc-cc"
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CONFIG_DM_RESET=y
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CONFIG_ROCKCHIP_RK3328=y
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CONFIG_DEBUG_UART_BASE=0xFF130000
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CONFIG_DEBUG_UART_CLOCK=24000000
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CONFIG_SYS_LOAD_ADDR=0x800800
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CONFIG_DEBUG_UART=y
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# CONFIG_ANDROID_BOOT_IMAGE is not set
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_SPL_FIT_SIGNATURE=y
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CONFIG_SPL_LOAD_FIT=y
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CONFIG_LEGACY_IMAGE_FORMAT=y
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CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-roc-cc.dtb"
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# CONFIG_DISPLAY_CPUINFO is not set
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CONFIG_DISPLAY_BOARDINFO_LATE=y
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CONFIG_SPL_MAX_SIZE=0x40000
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CONFIG_SPL_PAD_TO=0x7f8000
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# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
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CONFIG_SPL_POWER=y
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CONFIG_SPL_ATF=y
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CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
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CONFIG_CMD_BOOTZ=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_GPT=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_POWEROFF=y
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CONFIG_CMD_USB=y
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CONFIG_CMD_USB_MASS_STORAGE=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_TIME=y
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CONFIG_CMD_REGULATOR=y
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CONFIG_SPL_OF_CONTROL=y
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CONFIG_TPL_OF_CONTROL=y
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CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
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CONFIG_TPL_OF_PLATDATA=y
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CONFIG_ENV_IS_IN_MMC=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_SYS_MMC_ENV_DEV=1
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CONFIG_TPL_DM=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_REGMAP=y
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CONFIG_SPL_REGMAP=y
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CONFIG_TPL_REGMAP=y
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CONFIG_SYSCON=y
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CONFIG_SPL_SYSCON=y
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CONFIG_TPL_SYSCON=y
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CONFIG_CLK=y
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CONFIG_SPL_CLK=y
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CONFIG_FASTBOOT_BUF_ADDR=0x800800
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CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
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CONFIG_ROCKCHIP_GPIO=y
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CONFIG_SYS_I2C_ROCKCHIP=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_PHY_REALTEK=y
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CONFIG_DM_ETH_PHY=y
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CONFIG_PHY_GIGE=y
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_GMAC_ROCKCHIP=y
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CONFIG_PHY_ROCKCHIP_INNO_USB2=y
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CONFIG_PINCTRL=y
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CONFIG_SPL_PINCTRL=y
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CONFIG_DM_PMIC=y
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CONFIG_PMIC_RK8XX=y
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CONFIG_SPL_DM_REGULATOR=y
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CONFIG_DM_REGULATOR_FIXED=y
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CONFIG_SPL_DM_REGULATOR_FIXED=y
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CONFIG_DM_REGULATOR_GPIO=y
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CONFIG_REGULATOR_RK8XX=y
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CONFIG_PWM_ROCKCHIP=y
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CONFIG_RAM=y
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CONFIG_SPL_RAM=y
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CONFIG_TPL_RAM=y
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CONFIG_DM_RNG=y
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CONFIG_RNG_ROCKCHIP=y
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CONFIG_BAUDRATE=1500000
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CONFIG_DEBUG_UART_SHIFT=2
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CONFIG_SYS_NS16550_MEM32=y
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CONFIG_SYSINFO=y
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CONFIG_SYSINFO_SMBIOS=y
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CONFIG_SYSRESET=y
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# CONFIG_TPL_SYSRESET is not set
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CONFIG_USB=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_EHCI_GENERIC=y
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CONFIG_USB_OHCI_HCD=y
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CONFIG_USB_OHCI_GENERIC=y
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CONFIG_USB_DWC2=y
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CONFIG_USB_DWC3=y
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# CONFIG_USB_DWC3_GADGET is not set
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CONFIG_USB_DWC3_GENERIC=y
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CONFIG_USB_GADGET=y
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CONFIG_USB_GADGET_DWC2_OTG=y
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CONFIG_SPL_TINY_MEMSET=y
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CONFIG_TPL_TINY_MEMSET=y
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CONFIG_ERRNO_STR=y
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