/*
 * Copyright 2017 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#ifndef __RTE_DEVICE_H
#define __RTE_DEVICE_H

/*Driver name mapping.*/
#define RTE_SPI0 1
#define RTE_SPI0_DMA_EN 1
#define RTE_SPI1 0
#define RTE_SPI1_DMA_EN 0

/* SPI configuration. */
#define RTE_SPI_FIFO_ENABLE 0
#define SPI0_RX_FIFO_SIZE 8
#define SPI0_TX_FIFO_SIZE 8
#define SPI1_RX_FIFO_SIZE 0
#define SPI1_TX_FIFO_SIZE 0

#define RTE_SPI0_SSEL_NUM kSPI_Ssel0
#define RTE_SPI0_DMA_TX_CH 9
#define RTE_SPI0_DMA_TX_DMA_BASE DMA0
#define RTE_SPI0_DMA_RX_CH 8
#define RTE_SPI0_DMA_RX_DMA_BASE DMA0

#define RTE_SPI1_SSEL_NUM kSPI_Ssel0
#define RTE_SPI1_DMA_TX_CH 11
#define RTE_SPI1_DMA_TX_DMA_BASE DMA0
#define RTE_SPI1_DMA_RX_CH 10
#define RTE_SPI1_DMA_RX_DMA_BASE DMA0

#endif /* __RTE_DEVICE_H */
