/*
 * Copyright 2017 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
 
#ifndef _PIN_MUX_H_
#define _PIN_MUX_H_


/*******************************************************************************
 * Definitions
 ******************************************************************************/  

/*! @brief Direction type  */
typedef enum _pin_mux_direction
{
  kPIN_MUX_DirectionInput = 0U,         /* Input direction */
  kPIN_MUX_DirectionOutput = 1U,        /* Output direction */
  kPIN_MUX_DirectionInputOrOutput = 2U  /* Input or output direction */
} pin_mux_direction_t;

/*!
 * @addtogroup pin_mux
 * @{
 */

/*******************************************************************************
 * API
 ******************************************************************************/

#if defined(__cplusplus)
extern "C" {
#endif

/*!
 * @brief Calls initialization functions.
 *
 */
void BOARD_InitBootPins(void);

/* U0_RXD (number 31), U13[4]/TO_MUX_P0_0-ISP_RX */
#define BOARD_INITPINS_DEBUG_UART_RX_PERIPHERAL                           USART0   /*!< Device name: USART0 */
#define BOARD_INITPINS_DEBUG_UART_RX_SIGNAL                                  RXD   /*!< USART0 signal: RXD */
#define BOARD_INITPINS_DEBUG_UART_RX_PIN_NAME                             U0_RXD   /*!< Pin name */
#define BOARD_INITPINS_DEBUG_UART_RX_LABEL           "U13[4]/TO_MUX_P0_0-ISP_RX"   /*!< Label */
#define BOARD_INITPINS_DEBUG_UART_RX_NAME                        "DEBUG_UART_RX"   /*!< Identifier name */

/* U0_TXD (number 32), U15[3]/U4[4]/P0_1-ISP_TX */
#define BOARD_INITPINS_DEBUG_UART_TX_PERIPHERAL                           USART0   /*!< Device name: USART0 */
#define BOARD_INITPINS_DEBUG_UART_TX_SIGNAL                                  TXD   /*!< USART0 signal: TXD */
#define BOARD_INITPINS_DEBUG_UART_TX_PIN_NAME                             U0_TXD   /*!< Pin name */
#define BOARD_INITPINS_DEBUG_UART_TX_LABEL            "U15[3]/U4[4]/P0_1-ISP_TX"   /*!< Label */
#define BOARD_INITPINS_DEBUG_UART_TX_NAME                        "DEBUG_UART_TX"   /*!< Identifier name */

/*!
 * @brief Configures pin routing and optionally pin electrical features.
 *
 */
void BOARD_InitPins(void); /* Function assigned for the Cortex-M0P */

/* SPI0_MOSI (number 47), J3[2]/U8[J2]/BRIDGE_MOSI */
#define SPI0_INITPINS_BRIDGE_T_MOSI_PERIPHERAL                              SPI0   /*!< Device name: SPI0 */
#define SPI0_INITPINS_BRIDGE_T_MOSI_SIGNAL                                  MOSI   /*!< SPI0 signal: MOSI */
#define SPI0_INITPINS_BRIDGE_T_MOSI_PIN_NAME                           SPI0_MOSI   /*!< Pin name */
#define SPI0_INITPINS_BRIDGE_T_MOSI_LABEL             "J3[2]/U8[J2]/BRIDGE_MOSI"   /*!< Label */
#define SPI0_INITPINS_BRIDGE_T_MOSI_NAME                         "BRIDGE_T_MOSI"   /*!< Identifier name */

/* SPI0_MISO (number 48), J3[3]/U8[J1]/BRIDGE_MISO */
#define SPI0_INITPINS_BRIDGE_T_MISO_PERIPHERAL                              SPI0   /*!< Device name: SPI0 */
#define SPI0_INITPINS_BRIDGE_T_MISO_SIGNAL                                  MISO   /*!< SPI0 signal: MISO */
#define SPI0_INITPINS_BRIDGE_T_MISO_PIN_NAME                           SPI0_MISO   /*!< Pin name */
#define SPI0_INITPINS_BRIDGE_T_MISO_LABEL             "J3[3]/U8[J1]/BRIDGE_MISO"   /*!< Label */
#define SPI0_INITPINS_BRIDGE_T_MISO_NAME                         "BRIDGE_T_MISO"   /*!< Identifier name */

/* SPI0_SSEL0 (number 49), J3[1]/U8[K10]/BRIDGE_SSEL */
#define SPI0_INITPINS_BRIDGE_T_SSEL_PERIPHERAL                              SPI0   /*!< Device name: SPI0 */
#define SPI0_INITPINS_BRIDGE_T_SSEL_SIGNAL                                 SSEL0   /*!< SPI0 signal: SSEL0 */
#define SPI0_INITPINS_BRIDGE_T_SSEL_PIN_NAME                          SPI0_SSEL0   /*!< Pin name */
#define SPI0_INITPINS_BRIDGE_T_SSEL_LABEL            "J3[1]/U8[K10]/BRIDGE_SSEL"   /*!< Label */
#define SPI0_INITPINS_BRIDGE_T_SSEL_NAME                         "BRIDGE_T_SSEL"   /*!< Identifier name */

/* SPI0_SCK (number 17), J3[4]/U8[K9]/BRIDGE_SCK */
#define SPI0_INITPINS_BRIDGE_T_SCK_PERIPHERAL                               SPI0   /*!< Device name: SPI0 */
#define SPI0_INITPINS_BRIDGE_T_SCK_SIGNAL                                    SCK   /*!< SPI0 signal: SCK */
#define SPI0_INITPINS_BRIDGE_T_SCK_PIN_NAME                             SPI0_SCK   /*!< Pin name */
#define SPI0_INITPINS_BRIDGE_T_SCK_LABEL               "J3[4]/U8[K9]/BRIDGE_SCK"   /*!< Label */
#define SPI0_INITPINS_BRIDGE_T_SCK_NAME                           "BRIDGE_T_SCK"   /*!< Identifier name */

/*!
 * @brief Configures pin routing and optionally pin electrical features.
 *
 */
void SPI0_InitPins(void); /* Function assigned for the Cortex-M0P */

/* ADC_6 (number 17), J3[4]/U8[K9]/BRIDGE_SCK */
#define SPI0_DEINITPINS_BRIDGE_T_SCK_PERIPHERAL                             ADC0   /*!< Device name: ADC0 */
#define SPI0_DEINITPINS_BRIDGE_T_SCK_SIGNAL                                   CH   /*!< ADC0 signal: CH */
#define SPI0_DEINITPINS_BRIDGE_T_SCK_CHANNEL                                   6   /*!< ADC0 channel: 6 */
#define SPI0_DEINITPINS_BRIDGE_T_SCK_PIN_NAME                              ADC_6   /*!< Pin name */
#define SPI0_DEINITPINS_BRIDGE_T_SCK_LABEL             "J3[4]/U8[K9]/BRIDGE_SCK"   /*!< Label */
#define SPI0_DEINITPINS_BRIDGE_T_SCK_NAME                         "BRIDGE_T_SCK"   /*!< Identifier name */

/* CT32B2_MAT3 (number 47), J3[2]/U8[J2]/BRIDGE_MOSI */
#define SPI0_DEINITPINS_BRIDGE_T_MOSI_PERIPHERAL                          CT32B2   /*!< Device name: CT32B2 */
#define SPI0_DEINITPINS_BRIDGE_T_MOSI_SIGNAL                               MATCH   /*!< CT32B2 signal: MATCH */
#define SPI0_DEINITPINS_BRIDGE_T_MOSI_CHANNEL                                  3   /*!< CT32B2 MATCH channel: 3 */
#define SPI0_DEINITPINS_BRIDGE_T_MOSI_PIN_NAME                       CT32B2_MAT3   /*!< Pin name */
#define SPI0_DEINITPINS_BRIDGE_T_MOSI_LABEL           "J3[2]/U8[J2]/BRIDGE_MOSI"   /*!< Label */
#define SPI0_DEINITPINS_BRIDGE_T_MOSI_NAME                       "BRIDGE_T_MOSI"   /*!< Identifier name */

/* CT32B2_MAT0 (number 48), J3[3]/U8[J1]/BRIDGE_MISO */
#define SPI0_DEINITPINS_BRIDGE_T_MISO_PERIPHERAL                          CT32B2   /*!< Device name: CT32B2 */
#define SPI0_DEINITPINS_BRIDGE_T_MISO_SIGNAL                               MATCH   /*!< CT32B2 signal: MATCH */
#define SPI0_DEINITPINS_BRIDGE_T_MISO_CHANNEL                                  0   /*!< CT32B2 MATCH channel: 0 */
#define SPI0_DEINITPINS_BRIDGE_T_MISO_PIN_NAME                       CT32B2_MAT0   /*!< Pin name */
#define SPI0_DEINITPINS_BRIDGE_T_MISO_LABEL           "J3[3]/U8[J1]/BRIDGE_MISO"   /*!< Label */
#define SPI0_DEINITPINS_BRIDGE_T_MISO_NAME                       "BRIDGE_T_MISO"   /*!< Identifier name */

/* CT32B2_MAT1 (number 49), J3[1]/U8[K10]/BRIDGE_SSEL */
#define SPI0_DEINITPINS_BRIDGE_T_SSEL_PERIPHERAL                          CT32B2   /*!< Device name: CT32B2 */
#define SPI0_DEINITPINS_BRIDGE_T_SSEL_SIGNAL                               MATCH   /*!< CT32B2 signal: MATCH */
#define SPI0_DEINITPINS_BRIDGE_T_SSEL_CHANNEL                                  1   /*!< CT32B2 MATCH channel: 1 */
#define SPI0_DEINITPINS_BRIDGE_T_SSEL_PIN_NAME                       CT32B2_MAT1   /*!< Pin name */
#define SPI0_DEINITPINS_BRIDGE_T_SSEL_LABEL          "J3[1]/U8[K10]/BRIDGE_SSEL"   /*!< Label */
#define SPI0_DEINITPINS_BRIDGE_T_SSEL_NAME                       "BRIDGE_T_SSEL"   /*!< Identifier name */

/*!
 * @brief Configures pin routing and optionally pin electrical features.
 *
 */
void SPI0_DeinitPins(void); /* Function assigned for the Cortex-M0P */

#if defined(__cplusplus)
}
#endif

/*!
 * @}
 */
#endif /* _PIN_MUX_H_ */

/*******************************************************************************
 * EOF
 ******************************************************************************/
