nxp.com
LPC54102_cm0plus
1.0
LPC54102J256BD64,LPC54102J256UK49,LPC54102J512BD64,LPC54102J512UK49
Copyright 2016-2019 NXP
All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
CM0PLUS
r0p0
little
false
false
true
2
false
8
32
GPIO
LPC5410x General Purpose I/O (GPIO)
GPIO
0x1C000000
0
0x2488
registers
50
0x1
B[%s]
Byte pin registers for all port 0 and 1 GPIO pins
0
8
read-write
0
0x1
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
50
0x4
W[%s]
Word pin registers for all port 0 and 1 GPIO pins
0x1000
32
read-write
0
0xFFFFFFFF
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
read-write
2
0x4
DIR[%s]
Direction registers
0x2000
32
read-write
0
0xFFFFFFFF
DIRP
Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output.
0
32
read-write
2
0x4
MASK[%s]
Mask register
0x2080
32
read-write
0
0xFFFFFFFF
MASKP
Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.
0
32
read-write
2
0x4
PIN[%s]
Port pin register
0x2100
32
read-write
0
0xFFFFFFFF
PORT
Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.
0
32
read-write
2
0x4
MPIN[%s]
Masked port register
0x2180
32
read-write
0
0xFFFFFFFF
MPORTP
Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.
0
32
read-write
2
0x4
SET[%s]
Write: Set register for port Read: output bits for port
0x2200
32
read-write
0
0xFFFFFFFF
SETP
Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.
0
32
read-write
2
0x4
CLR[%s]
Clear port
0x2280
32
write-only
0
0
CLRP
Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit.
0
32
write-only
2
0x4
NOT[%s]
Toggle port
0x2300
32
write-only
0
0
NOTP
Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit.
0
32
write-only
2
0x4
DIRSET[%s]
Set pin direction bits for port
0x2380
32
write-only
0
0
DIRSETP
Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Set direction bit.
0
29
write-only
2
0x4
DIRCLR[%s]
Clear pin direction bits for port
0x2400
32
write-only
0
0
DIRCLRP
Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit.
0
29
write-only
2
0x4
DIRNOT[%s]
Toggle pin direction bits for port
0x2480
32
write-only
0
0
DIRNOTP
Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle direction bit.
0
29
write-only
DMA0
LPC5410x DMA controller
DMA
0x1C004000
0
0x55C
registers
DMA0
3
CTRL
DMA control.
0
32
read-write
0
0x1
ENABLE
DMA controller master enable.
0
1
read-write
DISABLED
Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when disabled, but does not prevent re-triggering when the DMA controller is re-enabled.
0
ENABLED
Enabled. The DMA controller is enabled.
0x1
INTSTAT
Interrupt status.
0x4
32
read-only
0
0x6
ACTIVEINT
Summarizes whether any enabled interrupts (other than error interrupts) are pending.
1
1
read-only
NOT_PENDING
Not pending. No enabled interrupts are pending.
0
PENDING
Pending. At least one enabled interrupt is pending.
0x1
ACTIVEERRINT
Summarizes whether any error interrupts are pending.
2
1
read-only
NOT_PENDING
Not pending. No error interrupts are pending.
0
PENDING
Pending. At least one error interrupt is pending.
0x1
SRAMBASE
SRAM address of the channel configuration table.
0x8
32
read-write
0
0xFFFFFE00
OFFSET
Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the table must begin on a 512 byte boundary.
9
23
read-write
ENABLESET0
Channel Enable read and Set for all DMA channels.
0x20
32
read-write
0
0xFFFFFFFF
ENA
Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled.
0
22
read-write
ENABLECLR0
Channel Enable Clear for all DMA channels.
0x28
32
write-only
0
0
CLR
Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits are reserved.
0
22
write-only
ACTIVE0
Channel Active status for all DMA channels.
0x30
32
read-write
0
0xFFFFFFFF
ACT
Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active.
0
22
read-write
BUSY0
Channel Busy status for all DMA channels.
0x38
32
read-write
0
0xFFFFFFFF
BSY
Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy.
0
22
read-write
ERRINT0
Error Interrupt status for all DMA channels.
0x40
32
read-write
0
0xFFFFFFFF
ERR
Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is not active. 1 = error interrupt is active.
0
22
read-write
INTENSET0
Interrupt Enable read and Set for all DMA channels.
0x48
32
read-write
0
0xFFFFFFFF
INTEN
Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled.
0
22
read-write
INTENCLR0
Interrupt Enable Clear for all DMA channels.
0x50
32
write-only
0
0
CLR
Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved.
0
22
write-only
INTA0
Interrupt A status for all DMA channels.
0x58
32
read-write
0
0xFFFFFFFF
IA
Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active.
0
22
read-write
INTB0
Interrupt B status for all DMA channels.
0x60
32
read-write
0
0xFFFFFFFF
IB
Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active.
0
22
read-write
SETVALID0
Set ValidPending control bits for all DMA channels.
0x68
32
write-only
0
0
SV
SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n
0
22
write-only
SETTRIG0
Set Trigger control bits for all DMA channels.
0x70
32
write-only
0
0
TRIG
Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the TRIG bit for DMA channel n.
0
22
write-only
ABORT0
Channel Abort control for all DMA channels.
0x78
32
write-only
0
0
ABORTCTRL
Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n.
0
22
write-only
22
0x10
CHANNEL[%s]
no description available
0x400
CFG
Configuration register for DMA channel .
0
32
read-write
0
0x7CF73
PERIPHREQEN
Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
0
1
read-write
DISABLED
Disabled. Peripheral DMA requests are disabled.
0
ENABLED
Enabled. Peripheral DMA requests are enabled.
0x1
HWTRIGEN
Hardware Triggering Enable for this channel.
1
1
read-write
DISABLED
Disabled. Hardware triggering is not used.
0
ENABLED
Enabled. Use hardware triggering.
0x1
TRIGPOL
Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
4
1
read-write
ACTIVE_LOW_FALLING
Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
0
ACTIVE_HIGH_RISING
Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
0x1
TRIGTYPE
Trigger Type. Selects hardware trigger as edge triggered or level triggered.
5
1
read-write
EDGE
Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
0
LEVEL
Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
0x1
TRIGBURST
Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
6
1
read-write
SINGLE
Single transfer. Hardware trigger causes a single transfer.
0
BURST
Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
0x1
BURSTPOWER
Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
8
4
read-write
SRCBURSTWRAP
Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
14
1
read-write
DISABLED
Disabled. Source burst wrapping is not enabled for this DMA channel.
0
ENABLED
Enabled. Source burst wrapping is enabled for this DMA channel.
0x1
DSTBURSTWRAP
Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
15
1
read-write
DISABLED
Disabled. Destination burst wrapping is not enabled for this DMA channel.
0
ENABLED
Enabled. Destination burst wrapping is enabled for this DMA channel.
0x1
CHPRIORITY
Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority.
16
3
read-write
CTLSTAT
Control and status register for DMA channel .
0x4
32
read-only
0
0x5
VALIDPENDING
Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
0
1
read-only
NO_EFFECT
No effect. No effect on DMA operation.
0
VALID_PENDING
Valid pending.
0x1
TRIG
Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
2
1
read-only
NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
0
TRIGGERED
Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
0x1
XFERCFG
Transfer configuration register for DMA channel .
0x8
32
read-write
0
0x3FFF33F
CFGVALID
Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
0
1
read-write
NOT_VALID
Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
0
VALID
Valid. The current channel descriptor is considered valid.
0x1
RELOAD
Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
1
1
read-write
DISABLED
Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
0
ENABLED
Enabled. Reload the channels' control structure when the current descriptor is exhausted.
0x1
SWTRIG
Software Trigger.
2
1
read-write
NOT_SET
Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
0
SET
Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
0x1
CLRTRIG
Clear Trigger.
3
1
read-write
NOT_CLEARED
Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.
0
CLEARED
Cleared. The trigger is cleared when this descriptor is exhausted
0x1
SETINTA
Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
4
1
read-write
NO_EFFECT
No effect.
0
SET
Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
0x1
SETINTB
Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
5
1
read-write
NO_EFFECT
No effect.
0
SET
Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
0x1
WIDTH
Transfer width used for this DMA channel.
8
2
read-write
BIT_8
8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
0
BIT_16
16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
0x1
BIT_32
32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
0x2
SRCINC
Determines whether the source address is incremented for each DMA transfer.
12
2
read-write
NO_INCREMENT
No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0
WIDTH_X_1
1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x1
WIDTH_X_2
2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x2
WIDTH_X_4
4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
0x3
DSTINC
Determines whether the destination address is incremented for each DMA transfer.
14
2
read-write
NO_INCREMENT
No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0
WIDTH_X_1
1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x1
WIDTH_X_2
2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x2
WIDTH_X_4
4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
0x3
XFERCOUNT
Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed.
16
10
read-write
CRC_ENGINE
LPC5410x CRC engine
CRC
0x1C010000
0
0xC
registers
MODE
CRC mode register
0
32
read-write
0
0x3F
CRC_POLY
CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial
0
2
read-write
BIT_RVS_WR
Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte)
2
1
read-write
CMPL_WR
Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA
3
1
read-write
BIT_RVS_SUM
CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM
4
1
read-write
CMPL_SUM
CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM
5
1
read-write
SEED
CRC seed register
0x4
32
read-write
0xFFFF
0xFFFFFFFF
CRC_SEED
A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1's complement pre-processes. A write access to this register will overrule the CRC calculation in progresses.
0
32
read-write
SUM
CRC checksum register
SUM_WR_DATA
0x8
32
read-only
0xFFFF
0xFFFFFFFF
CRC_SUM
The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes.
0
32
read-only
WR_DATA
CRC data register
SUM_WR_DATA
0x8
32
write-only
0
0
CRC_WR_DATA
Data written to this register will be taken to perform CRC calculation with selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions.
0
32
write-only
SCT0
SCTimer/PWM (SCT)
SCT
0x1C018000
0
0x540
registers
SCT0
16
CONFIG
SCT configuration register
0
32
read-write
0x1E00
0x61FFF
UNIFY
SCT operation
0
1
read-write
DUAL_COUNTER
The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H.
0
UNIFIED_COUNTER
The SCT operates as a unified 32-bit counter.
0x1
CLKMODE
SCT clock mode
1
2
read-write
SYSTEM_CLOCK_MODE
System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers.
0
SAMPLED_SYSTEM_CLOCK_MODE
Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the high-performance, sampled-clock mode.
0x1
SCT_INPUT_CLOCK_MODE
SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode.
0x2
ASYNCHRONOUS_MODE
Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system clock. The input clock rate must be at least half the system clock rate and can be the same or faster than the system clock.
0x3
CKSEL
SCT clock select. The specific functionality of the designated input/edge is dependent on the CLKMODE bit selection in this register.
3
4
read-write
INPUT_0_RISING_EDGES
Rising edges on input 0.
0
INPUT_0_FALLING_EDGE
Falling edges on input 0.
0x1
INPUT_1_RISING_EDGES
Rising edges on input 1.
0x2
INPUT_1_FALLING_EDGE
Falling edges on input 1.
0x3
INPUT_2_RISING_EDGES
Rising edges on input 2.
0x4
INPUT_2_FALLING_EDGE
Falling edges on input 2.
0x5
INPUT_3_RISING_EDGES
Rising edges on input 3.
0x6
INPUT_3_FALLING_EDGE
Falling edges on input 3.
0x7
INPUT_4_RISING_EDGES
Rising edges on input 4.
0x8
INPUT_4_FALLING_EDGE
Falling edges on input 4.
0x9
INPUT_5_RISING_EDGES
Rising edges on input 5.
0xA
INPUT_5_FALLING_EDGE
Falling edges on input 5.
0xB
INPUT_6_RISING_EDGES
Rising edges on input 6.
0xC
INPUT_6_FALLING_EDGE
Falling edges on input 6.
0xD
INPUT_7_RISING_EDGES
Rising edges on input 7.
0xE
INPUT_7_FALLING_EDGE
Falling edges on input 7.
0xF
NORELOAD_L
A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.
7
1
read-write
NORELOAD_H
A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set.
8
1
read-write
INSYNC
Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is known to already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. It does not apply to the clock input specified in the CKSEL field.
9
4
read-write
AUTOLIMIT_L
A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.
17
1
read-write
AUTOLIMIT_H
A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set.
18
1
read-write
CTRL
SCT control register
0x4
32
read-write
0x40004
0x1FFF1FFF
DOWN_L
This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0.
0
1
read-write
STOP_L
When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events related to the counter can occur. If a designated start event occurs, this bit is cleared and counting resumes.
1
1
read-write
HALT_L
When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, only software can clear this bit to restore counter operation. This bit is set on reset.
2
1
read-write
CLRCTR_L
Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.
3
1
read-write
BIDIR_L
L or unified counter direction select
4
1
read-write
UP
Up. The counter counts up to a limit condition, then is cleared to zero.
0
UP_DOWN
Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0.
0x1
PRE_L
Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
5
8
read-write
DOWN_H
This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0.
16
1
read-write
STOP_H
When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes.
17
1
read-write
HALT_H
When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit can only be cleared by software to restore counter operation. This bit is set on reset.
18
1
read-write
CLRCTR_H
Writing a 1 to this bit clears the H counter. This bit always reads as 0.
19
1
read-write
BIDIR_H
Direction select
20
1
read-write
UP
The H counter counts up to its limit condition, then is cleared to zero.
0
UP_DOWN
The H counter counts up to its limit, then counts down to a limit condition or to 0.
0x1
PRE_H
Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
21
8
read-write
LIMIT
SCT limit event select register
0x8
32
read-write
0
0xFFFFFFFF
LIMMSK_L
If bit n is one, event n is used as a counter limit for the L or unified counter (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
0
16
read-write
LIMMSK_H
If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
16
16
read-write
HALT
SCT halt event select register
0xC
32
read-write
0
0xFFFFFFFF
HALTMSK_L
If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
0
16
read-write
HALTMSK_H
If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
16
16
read-write
STOP
SCT stop event select register
0x10
32
read-write
0
0xFFFFFFFF
STOPMSK_L
If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
0
16
read-write
STOPMSK_H
If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
16
16
read-write
START
SCT start event select register
0x14
32
read-write
0
0xFFFFFFFF
STARTMSK_L
If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
0
16
read-write
STARTMSK_H
If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
16
16
read-write
COUNT
SCT counter register
0x40
32
read-write
0
0xFFFFFFFF
CTR_L
When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter.
0
16
read-write
CTR_H
When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter.
16
16
read-write
STATE
SCT state register
0x44
32
read-write
0
0x1F001F
STATE_L
State variable.
0
5
read-write
STATE_H
State variable.
16
5
read-write
INPUT
SCT input register
0x48
32
read-only
0
0xFFFFFFFF
AIN0
Input 0 state. Input 0 state on the last SCT clock edge.
0
1
read-only
AIN1
Input 1 state. Input 1 state on the last SCT clock edge.
1
1
read-only
AIN2
Input 2 state. Input 2 state on the last SCT clock edge.
2
1
read-only
AIN3
Input 3 state. Input 3 state on the last SCT clock edge.
3
1
read-only
AIN4
Input 4 state. Input 4 state on the last SCT clock edge.
4
1
read-only
AIN5
Input 5 state. Input 5 state on the last SCT clock edge.
5
1
read-only
AIN6
Input 6 state. Input 6 state on the last SCT clock edge.
6
1
read-only
AIN7
Input 7 state. Input 7 state on the last SCT clock edge.
7
1
read-only
AIN8
Input 8 state. Input 8 state on the last SCT clock edge.
8
1
read-only
AIN9
Input 9 state. Input 9 state on the last SCT clock edge.
9
1
read-only
AIN10
Input 10 state. Input 10 state on the last SCT clock edge.
10
1
read-only
AIN11
Input 11 state. Input 11 state on the last SCT clock edge.
11
1
read-only
AIN12
Input 12 state. Input 12 state on the last SCT clock edge.
12
1
read-only
AIN13
Input 13 state. Input 13 state on the last SCT clock edge.
13
1
read-only
AIN14
Input 14 state. Input 14 state on the last SCT clock edge.
14
1
read-only
AIN15
Input 15 state. Input 15 state on the last SCT clock edge.
15
1
read-only
SIN0
Input 0 state. Input 0 state following the synchronization specified by INSYNC.
16
1
read-only
SIN1
Input 1 state. Input 1 state following the synchronization specified by INSYNC.
17
1
read-only
SIN2
Input 2 state. Input 2 state following the synchronization specified by INSYNC.
18
1
read-only
SIN3
Input 3 state. Input 3 state following the synchronization specified by INSYNC.
19
1
read-only
SIN4
Input 4 state. Input 4 state following the synchronization specified by INSYNC.
20
1
read-only
SIN5
Input 5 state. Input 5 state following the synchronization specified by INSYNC.
21
1
read-only
SIN6
Input 6 state. Input 6 state following the synchronization specified by INSYNC.
22
1
read-only
SIN7
Input 7 state. Input 7 state following the synchronization specified by INSYNC.
23
1
read-only
SIN8
Input 8 state. Input 8 state following the synchronization specified by INSYNC.
24
1
read-only
SIN9
Input 9 state. Input 9 state following the synchronization specified by INSYNC.
25
1
read-only
SIN10
Input 10 state. Input 10 state following the synchronization specified by INSYNC.
26
1
read-only
SIN11
Input 11 state. Input 11 state following the synchronization specified by INSYNC.
27
1
read-only
SIN12
Input 12 state. Input 12 state following the synchronization specified by INSYNC.
28
1
read-only
SIN13
Input 13 state. Input 13 state following the synchronization specified by INSYNC.
29
1
read-only
SIN14
Input 14 state. Input 14 state following the synchronization specified by INSYNC.
30
1
read-only
SIN15
Input 15 state. Input 15 state following the synchronization specified by INSYNC.
31
1
read-only
REGMODE
SCT match/capture mode register
0x4C
32
read-write
0
0xFFFFFFFF
REGMOD_L
Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match register. 1 = register operates as capture register.
0
16
read-write
REGMOD_H
Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match registers. 1 = register operates as capture registers.
16
16
read-write
OUTPUT
SCT output register
0x50
32
read-write
0
0xFFFF
OUT
Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT.
0
16
read-write
OUTPUTDIRCTRL
SCT output counter direction control register
0x54
32
read-write
0
0xFFFFFFFF
SETCLR0
Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.
0
2
read-write
INDEPENDENT
Set and clear do not depend on the direction of any counter.
0
L_REVERSED
Set and clear are reversed when counter L or the unified counter is counting down.
0x1
H_REVERSED
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
0x2
SETCLR1
Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.
2
2
read-write
INDEPENDENT
Set and clear do not depend on the direction of any counter.
0
L_REVERSED
Set and clear are reversed when counter L or the unified counter is counting down.
0x1
H_REVERSED
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
0x2
SETCLR2
Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.
4
2
read-write
INDEPENDENT
Set and clear do not depend on the direction of any counter.
0
L_REVERSED
Set and clear are reversed when counter L or the unified counter is counting down.
0x1
H_REVERSED
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
0x2
SETCLR3
Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.
6
2
read-write
INDEPENDENT
Set and clear do not depend on the direction of any counter.
0
L_REVERSED
Set and clear are reversed when counter L or the unified counter is counting down.
0x1
H_REVERSED
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
0x2
SETCLR4
Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value.
8
2
read-write
INDEPENDENT
Set and clear do not depend on the direction of any counter.
0
L_REVERSED
Set and clear are reversed when counter L or the unified counter is counting down.
0x1
H_REVERSED
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
0x2
SETCLR5
Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.
10
2
read-write
INDEPENDENT
Set and clear do not depend on the direction of any counter.
0
L_REVERSED
Set and clear are reversed when counter L or the unified counter is counting down.
0x1
H_REVERSED
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
0x2
SETCLR6
Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value.
12
2
read-write
INDEPENDENT
Set and clear do not depend on the direction of any counter.
0
L_REVERSED
Set and clear are reversed when counter L or the unified counter is counting down.
0x1
H_REVERSED
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
0x2
SETCLR7
Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value.
14
2
read-write
INDEPENDENT
Set and clear do not depend on the direction of any counter.
0
L_REVERSED
Set and clear are reversed when counter L or the unified counter is counting down.
0x1
H_REVERSED
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
0x2
SETCLR8
Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value.
16
2
read-write
INDEPENDENT
Set and clear do not depend on the direction of any counter.
0
L_REVERSED
Set and clear are reversed when counter L or the unified counter is counting down.
0x1
H_REVERSED
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
0x2
SETCLR9
Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value.
18
2
read-write
INDEPENDENT
Set and clear do not depend on the direction of any counter.
0
L_REVERSED
Set and clear are reversed when counter L or the unified counter is counting down.
0x1
H_REVERSED
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
0x2
SETCLR10
Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value.
20
2
read-write
INDEPENDENT
Set and clear do not depend on the direction of any counter.
0
L_REVERSED
Set and clear are reversed when counter L or the unified counter is counting down.
0x1
H_REVERSED
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
0x2
SETCLR11
Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value.
22
2
read-write
INDEPENDENT
Set and clear do not depend on the direction of any counter.
0
L_REVERSED
Set and clear are reversed when counter L or the unified counter is counting down.
0x1
H_REVERSED
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
0x2
SETCLR12
Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value.
24
2
read-write
INDEPENDENT
Set and clear do not depend on the direction of any counter.
0
L_REVERSED
Set and clear are reversed when counter L or the unified counter is counting down.
0x1
H_REVERSED
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
0x2
SETCLR13
Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value.
26
2
read-write
INDEPENDENT
Set and clear do not depend on the direction of any counter.
0
L_REVERSED
Set and clear are reversed when counter L or the unified counter is counting down.
0x1
H_REVERSED
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
0x2
SETCLR14
Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value.
28
2
read-write
INDEPENDENT
Set and clear do not depend on the direction of any counter.
0
L_REVERSED
Set and clear are reversed when counter L or the unified counter is counting down.
0x1
H_REVERSED
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
0x2
SETCLR15
Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value.
30
2
read-write
INDEPENDENT
Set and clear do not depend on the direction of any counter.
0
L_REVERSED
Set and clear are reversed when counter L or the unified counter is counting down.
0x1
H_REVERSED
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
0x2
RES
SCT conflict resolution register
0x58
32
read-write
0
0xFFFFFFFF
O0RES
Effect of simultaneous set and clear on output 0.
0
2
read-write
NO_CHANGE
No change.
0
SET
Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register).
0x1
CLEAR
Clear output (or set based on the SETCLR0 field).
0x2
TOGGLE_OUTPUT
Toggle output.
0x3
O1RES
Effect of simultaneous set and clear on output 1.
2
2
read-write
NO_CHANGE
No change.
0
SET
Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register).
0x1
CLEAR
Clear output (or set based on the SETCLR1 field).
0x2
TOGGLE_OUTPUT
Toggle output.
0x3
O2RES
Effect of simultaneous set and clear on output 2.
4
2
read-write
NO_CHANGE
No change.
0
SET
Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register).
0x1
CLEAR
Clear output n (or set based on the SETCLR2 field).
0x2
TOGGLE_OUTPUT
Toggle output.
0x3
O3RES
Effect of simultaneous set and clear on output 3.
6
2
read-write
NO_CHANGE
No change.
0
SET
Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register).
0x1
CLEAR
Clear output (or set based on the SETCLR3 field).
0x2
TOGGLE_OUTPUT
Toggle output.
0x3
O4RES
Effect of simultaneous set and clear on output 4.
8
2
read-write
NO_CHANGE
No change.
0
SET
Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register).
0x1
CLEAR
Clear output (or set based on the SETCLR4 field).
0x2
TOGGLE_OUTPUT
Toggle output.
0x3
O5RES
Effect of simultaneous set and clear on output 5.
10
2
read-write
NO_CHANGE
No change.
0
SET
Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register).
0x1
CLEAR
Clear output (or set based on the SETCLR5 field).
0x2
TOGGLE_OUTPUT
Toggle output.
0x3
O6RES
Effect of simultaneous set and clear on output 6.
12
2
read-write
NO_CHANGE
No change.
0
SET
Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register).
0x1
CLEAR
Clear output (or set based on the SETCLR6 field).
0x2
TOGGLE_OUTPUT
Toggle output.
0x3
O7RES
Effect of simultaneous set and clear on output 7.
14
2
read-write
NO_CHANGE
No change.
0
SET
Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register).
0x1
CLEAR
Clear output n (or set based on the SETCLR7 field).
0x2
TOGGLE_OUTPUT
Toggle output.
0x3
O8RES
Effect of simultaneous set and clear on output 8.
16
2
read-write
NO_CHANGE
No change.
0
SET
Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register).
0x1
CLEAR
Clear output (or set based on the SETCLR8 field).
0x2
TOGGLE_OUTPUT
Toggle output.
0x3
O9RES
Effect of simultaneous set and clear on output 9.
18
2
read-write
NO_CHANGE
No change.
0
SET
Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register).
0x1
CLEAR
Clear output (or set based on the SETCLR9 field).
0x2
TOGGLE_OUTPUT
Toggle output.
0x3
O10RES
Effect of simultaneous set and clear on output 10.
20
2
read-write
NO_CHANGE
No change.
0
SET
Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register).
0x1
CLEAR
Clear output (or set based on the SETCLR10 field).
0x2
TOGGLE_OUTPUT
Toggle output.
0x3
O11RES
Effect of simultaneous set and clear on output 11.
22
2
read-write
NO_CHANGE
No change.
0
SET
Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register).
0x1
CLEAR
Clear output (or set based on the SETCLR11 field).
0x2
TOGGLE_OUTPUT
Toggle output.
0x3
O12RES
Effect of simultaneous set and clear on output 12.
24
2
read-write
NO_CHANGE
No change.
0
SET
Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register).
0x1
CLEAR
Clear output (or set based on the SETCLR12 field).
0x2
TOGGLE_OUTPUT
Toggle output.
0x3
O13RES
Effect of simultaneous set and clear on output 13.
26
2
read-write
NO_CHANGE
No change.
0
SET
Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register).
0x1
CLEAR
Clear output (or set based on the SETCLR13 field).
0x2
TOGGLE_OUTPUT
Toggle output.
0x3
O14RES
Effect of simultaneous set and clear on output 14.
28
2
read-write
NO_CHANGE
No change.
0
SET
Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register).
0x1
CLEAR
Clear output (or set based on the SETCLR14 field).
0x2
TOGGLE_OUTPUT
Toggle output.
0x3
O15RES
Effect of simultaneous set and clear on output 15.
30
2
read-write
NO_CHANGE
No change.
0
SET
Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register).
0x1
CLEAR
Clear output (or set based on the SETCLR15 field).
0x2
TOGGLE_OUTPUT
Toggle output.
0x3
DMAREQ0
SCT DMA request 0 register
0x5C
32
read-write
0
0xC000FFFF
DEV_0
If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
0
16
read-write
DRL0
A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers.
30
1
read-write
DRQ0
This read-only bit indicates the state of DMA Request 0. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup.
31
1
read-write
DMAREQ1
SCT DMA request 1 register
0x60
32
read-write
0
0xC000FFFF
DEV_1
If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
0
16
read-write
DRL1
A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers.
30
1
read-write
DRQ1
This read-only bit indicates the state of DMA Request 1. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup.
31
1
read-write
EVEN
SCT event interrupt enable register
0xF0
32
read-write
0
0xFFFF
IEN
The SCT requests an interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
0
16
read-write
EVFLAG
SCT event flag register
0xF4
32
read-write
0
0xFFFF
FLAG
Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
0
16
read-write
CONEN
SCT conflict interrupt enable register
0xF8
32
read-write
0
0xFFFF
NCEN
The SCT requests an interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT.
0
16
read-write
CONFLAG
SCT conflict flag register
0xFC
32
read-write
0
0xC000FFFF
NCFLAG
Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT.
0
16
read-write
BUSERRL
The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful.
30
1
read-write
BUSERRH
The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted.
31
1
read-write
CAP0
SCT capture register of capture channel
CAP_MATCH
0x100
32
read-write
0
0xFFFFFFFF
CAPn_L
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
0
16
read-write
CAPn_H
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
16
16
read-write
MATCH0
SCT match value register of match channels
CAP_MATCH
0x100
32
read-write
0
0xFFFFFFFF
MATCHn_L
When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
0
16
read-write
MATCHn_H
When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
16
16
read-write
CAP1
SCT capture register of capture channel
CAP_MATCH
0x104
32
read-write
0
0xFFFFFFFF
CAPn_L
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
0
16
read-write
CAPn_H
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
16
16
read-write
MATCH1
SCT match value register of match channels
CAP_MATCH
0x104
32
read-write
0
0xFFFFFFFF
MATCHn_L
When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
0
16
read-write
MATCHn_H
When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
16
16
read-write
CAP2
SCT capture register of capture channel
CAP_MATCH
0x108
32
read-write
0
0xFFFFFFFF
CAPn_L
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
0
16
read-write
CAPn_H
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
16
16
read-write
MATCH2
SCT match value register of match channels
CAP_MATCH
0x108
32
read-write
0
0xFFFFFFFF
MATCHn_L
When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
0
16
read-write
MATCHn_H
When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
16
16
read-write
CAP3
SCT capture register of capture channel
CAP_MATCH
0x10C
32
read-write
0
0xFFFFFFFF
CAPn_L
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
0
16
read-write
CAPn_H
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
16
16
read-write
MATCH3
SCT match value register of match channels
CAP_MATCH
0x10C
32
read-write
0
0xFFFFFFFF
MATCHn_L
When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
0
16
read-write
MATCHn_H
When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
16
16
read-write
CAP4
SCT capture register of capture channel
CAP_MATCH
0x110
32
read-write
0
0xFFFFFFFF
CAPn_L
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
0
16
read-write
CAPn_H
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
16
16
read-write
MATCH4
SCT match value register of match channels
CAP_MATCH
0x110
32
read-write
0
0xFFFFFFFF
MATCHn_L
When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
0
16
read-write
MATCHn_H
When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
16
16
read-write
CAP5
SCT capture register of capture channel
CAP_MATCH
0x114
32
read-write
0
0xFFFFFFFF
CAPn_L
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
0
16
read-write
CAPn_H
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
16
16
read-write
MATCH5
SCT match value register of match channels
CAP_MATCH
0x114
32
read-write
0
0xFFFFFFFF
MATCHn_L
When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
0
16
read-write
MATCHn_H
When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
16
16
read-write
CAP6
SCT capture register of capture channel
CAP_MATCH
0x118
32
read-write
0
0xFFFFFFFF
CAPn_L
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
0
16
read-write
CAPn_H
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
16
16
read-write
MATCH6
SCT match value register of match channels
CAP_MATCH
0x118
32
read-write
0
0xFFFFFFFF
MATCHn_L
When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
0
16
read-write
MATCHn_H
When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
16
16
read-write
CAP7
SCT capture register of capture channel
CAP_MATCH
0x11C
32
read-write
0
0xFFFFFFFF
CAPn_L
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
0
16
read-write
CAPn_H
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
16
16
read-write
MATCH7
SCT match value register of match channels
CAP_MATCH
0x11C
32
read-write
0
0xFFFFFFFF
MATCHn_L
When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
0
16
read-write
MATCHn_H
When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
16
16
read-write
CAP8
SCT capture register of capture channel
CAP_MATCH
0x120
32
read-write
0
0xFFFFFFFF
CAPn_L
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
0
16
read-write
CAPn_H
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
16
16
read-write
MATCH8
SCT match value register of match channels
CAP_MATCH
0x120
32
read-write
0
0xFFFFFFFF
MATCHn_L
When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
0
16
read-write
MATCHn_H
When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
16
16
read-write
CAP9
SCT capture register of capture channel
CAP_MATCH
0x124
32
read-write
0
0xFFFFFFFF
CAPn_L
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
0
16
read-write
CAPn_H
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
16
16
read-write
MATCH9
SCT match value register of match channels
CAP_MATCH
0x124
32
read-write
0
0xFFFFFFFF
MATCHn_L
When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
0
16
read-write
MATCHn_H
When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
16
16
read-write
CAP10
SCT capture register of capture channel
CAP_MATCH
0x128
32
read-write
0
0xFFFFFFFF
CAPn_L
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
0
16
read-write
CAPn_H
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
16
16
read-write
MATCH10
SCT match value register of match channels
CAP_MATCH
0x128
32
read-write
0
0xFFFFFFFF
MATCHn_L
When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
0
16
read-write
MATCHn_H
When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
16
16
read-write
CAP11
SCT capture register of capture channel
CAP_MATCH
0x12C
32
read-write
0
0xFFFFFFFF
CAPn_L
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
0
16
read-write
CAPn_H
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
16
16
read-write
MATCH11
SCT match value register of match channels
CAP_MATCH
0x12C
32
read-write
0
0xFFFFFFFF
MATCHn_L
When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
0
16
read-write
MATCHn_H
When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
16
16
read-write
CAP12
SCT capture register of capture channel
CAP_MATCH
0x130
32
read-write
0
0xFFFFFFFF
CAPn_L
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
0
16
read-write
CAPn_H
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
16
16
read-write
MATCH12
SCT match value register of match channels
CAP_MATCH
0x130
32
read-write
0
0xFFFFFFFF
MATCHn_L
When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
0
16
read-write
MATCHn_H
When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
16
16
read-write
CAPCTRL0
SCT capture control register
CAPCTRL_MATCHREL
0x200
32
read-write
0
0xFFFFFFFF
CAPCONn_L
If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.
0
16
read-write
CAPCONn_H
If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
16
16
read-write
MATCHREL0
SCT match reload value register
CAPCTRL_MATCHREL
0x200
32
read-write
0
0xFFFFFFFF
RELOADn_L
When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
0
16
read-write
RELOADn_H
When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
16
16
read-write
CAPCTRL1
SCT capture control register
CAPCTRL_MATCHREL
0x204
32
read-write
0
0xFFFFFFFF
CAPCONn_L
If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.
0
16
read-write
CAPCONn_H
If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
16
16
read-write
MATCHREL1
SCT match reload value register
CAPCTRL_MATCHREL
0x204
32
read-write
0
0xFFFFFFFF
RELOADn_L
When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
0
16
read-write
RELOADn_H
When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
16
16
read-write
CAPCTRL2
SCT capture control register
CAPCTRL_MATCHREL
0x208
32
read-write
0
0xFFFFFFFF
CAPCONn_L
If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.
0
16
read-write
CAPCONn_H
If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
16
16
read-write
MATCHREL2
SCT match reload value register
CAPCTRL_MATCHREL
0x208
32
read-write
0
0xFFFFFFFF
RELOADn_L
When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
0
16
read-write
RELOADn_H
When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
16
16
read-write
CAPCTRL3
SCT capture control register
CAPCTRL_MATCHREL
0x20C
32
read-write
0
0xFFFFFFFF
CAPCONn_L
If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.
0
16
read-write
CAPCONn_H
If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
16
16
read-write
MATCHREL3
SCT match reload value register
CAPCTRL_MATCHREL
0x20C
32
read-write
0
0xFFFFFFFF
RELOADn_L
When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
0
16
read-write
RELOADn_H
When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
16
16
read-write
CAPCTRL4
SCT capture control register
CAPCTRL_MATCHREL
0x210
32
read-write
0
0xFFFFFFFF
CAPCONn_L
If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.
0
16
read-write
CAPCONn_H
If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
16
16
read-write
MATCHREL4
SCT match reload value register
CAPCTRL_MATCHREL
0x210
32
read-write
0
0xFFFFFFFF
RELOADn_L
When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
0
16
read-write
RELOADn_H
When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
16
16
read-write
CAPCTRL5
SCT capture control register
CAPCTRL_MATCHREL
0x214
32
read-write
0
0xFFFFFFFF
CAPCONn_L
If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.
0
16
read-write
CAPCONn_H
If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
16
16
read-write
MATCHREL5
SCT match reload value register
CAPCTRL_MATCHREL
0x214
32
read-write
0
0xFFFFFFFF
RELOADn_L
When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
0
16
read-write
RELOADn_H
When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
16
16
read-write
CAPCTRL6
SCT capture control register
CAPCTRL_MATCHREL
0x218
32
read-write
0
0xFFFFFFFF
CAPCONn_L
If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.
0
16
read-write
CAPCONn_H
If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
16
16
read-write
MATCHREL6
SCT match reload value register
CAPCTRL_MATCHREL
0x218
32
read-write
0
0xFFFFFFFF
RELOADn_L
When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
0
16
read-write
RELOADn_H
When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
16
16
read-write
CAPCTRL7
SCT capture control register
CAPCTRL_MATCHREL
0x21C
32
read-write
0
0xFFFFFFFF
CAPCONn_L
If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.
0
16
read-write
CAPCONn_H
If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
16
16
read-write
MATCHREL7
SCT match reload value register
CAPCTRL_MATCHREL
0x21C
32
read-write
0
0xFFFFFFFF
RELOADn_L
When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
0
16
read-write
RELOADn_H
When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
16
16
read-write
CAPCTRL8
SCT capture control register
CAPCTRL_MATCHREL
0x220
32
read-write
0
0xFFFFFFFF
CAPCONn_L
If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.
0
16
read-write
CAPCONn_H
If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
16
16
read-write
MATCHREL8
SCT match reload value register
CAPCTRL_MATCHREL
0x220
32
read-write
0
0xFFFFFFFF
RELOADn_L
When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
0
16
read-write
RELOADn_H
When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
16
16
read-write
CAPCTRL9
SCT capture control register
CAPCTRL_MATCHREL
0x224
32
read-write
0
0xFFFFFFFF
CAPCONn_L
If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.
0
16
read-write
CAPCONn_H
If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
16
16
read-write
MATCHREL9
SCT match reload value register
CAPCTRL_MATCHREL
0x224
32
read-write
0
0xFFFFFFFF
RELOADn_L
When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
0
16
read-write
RELOADn_H
When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
16
16
read-write
CAPCTRL10
SCT capture control register
CAPCTRL_MATCHREL
0x228
32
read-write
0
0xFFFFFFFF
CAPCONn_L
If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.
0
16
read-write
CAPCONn_H
If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
16
16
read-write
MATCHREL10
SCT match reload value register
CAPCTRL_MATCHREL
0x228
32
read-write
0
0xFFFFFFFF
RELOADn_L
When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
0
16
read-write
RELOADn_H
When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
16
16
read-write
CAPCTRL11
SCT capture control register
CAPCTRL_MATCHREL
0x22C
32
read-write
0
0xFFFFFFFF
CAPCONn_L
If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.
0
16
read-write
CAPCONn_H
If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
16
16
read-write
MATCHREL11
SCT match reload value register
CAPCTRL_MATCHREL
0x22C
32
read-write
0
0xFFFFFFFF
RELOADn_L
When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
0
16
read-write
RELOADn_H
When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
16
16
read-write
CAPCTRL12
SCT capture control register
CAPCTRL_MATCHREL
0x230
32
read-write
0
0xFFFFFFFF
CAPCONn_L
If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.
0
16
read-write
CAPCONn_H
If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
16
16
read-write
MATCHREL12
SCT match reload value register
CAPCTRL_MATCHREL
0x230
32
read-write
0
0xFFFFFFFF
RELOADn_L
When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
0
16
read-write
RELOADn_H
When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
16
16
read-write
13
0x8
EV[%s]
no description available
0x300
EV_STATE
SCT event state register 0
0
32
read-write
0
0xFFFF
STATEMSKn
If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT.
0
16
read-write
EV_CTRL
SCT event control register 0
0x4
32
read-write
0
0x7FFFFF
MATCHSEL
Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
0
4
read-write
HEVENT
Select L/H counter. Do not set this bit if UNIFY = 1.
4
1
read-write
L_COUNTER
Selects the L state and the L match register selected by MATCHSEL.
0
H_COUNTER
Selects the H state and the H match register selected by MATCHSEL.
0x1
OUTSEL
Input/output select
5
1
read-write
INPUT
Selects the inputs selected by IOSEL.
0
OUTPUT
Selects the outputs selected by IOSEL.
0x1
IOSEL
Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
6
4
read-write
IOCOND
Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
10
2
read-write
LOW
LOW
0
RISE
Rise
0x1
FALL
Fall
0x2
HIGH
HIGH
0x3
COMBMODE
Selects how the specified match and I/O condition are used and combined.
12
2
read-write
OR
OR. The event occurs when either the specified match or I/O condition occurs.
0
MATCH
MATCH. Uses the specified match only.
0x1
IO
IO. Uses the specified I/O condition only.
0x2
AND
AND. The event occurs when the specified match and I/O condition occur simultaneously.
0x3
STATELD
This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
14
1
read-write
ADD
STATEV value is added into STATE (the carry-out is ignored).
0
LOAD
STATEV value is loaded into STATE.
0x1
STATEV
This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
15
5
read-write
MATCHMEM
If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
20
1
read-write
DIRECTION
Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
21
2
read-write
DIRECTION_INDEPENDENT
Direction independent. This event is triggered regardless of the count direction.
0
COUNTING_UP
Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x1
COUNTING_DOWN
Counting down. This event is triggered only during down-counting when BIDIR = 1.
0x2
8
0x8
OUT[%s]
no description available
0x500
OUT_SET
SCT output 0 set register
0
32
read-write
0
0xFFFF
SET
A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
0
16
read-write
OUT_CLR
SCT output 0 clear register
0x4
32
read-write
0
0xFFFF
CLR
A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
0
16
read-write
MAILBOX
LPC5410x Mailbox
MAILBOX
0x1C02C000
0
0xFC
registers
MAILBOX
31
2
0x10
MBOXIRQ[%s]
no description available
0
IRQ
Interrupt request register for the Cortex-M0+ CPU.
0
32
read-write
0
0xFFFFFFFF
INTREQ
If any bit is set, an interrupt request is sent to the Cortex-M0+ interrupt controller.
0
32
read-write
IRQSET
Set bits in IRQ0
0x4
32
write-only
0
0
INTREQSET
Writing 1 sets the corresponding bit in the IRQ0 register.
0
32
write-only
IRQCLR
Clear bits in IRQ0
0x8
32
write-only
0
0
INTREQCLR
Writing 1 clears the corresponding bit in the IRQ0 register.
0
32
write-only
MUTEX
Mutual exclusion register[1]
0xF8
32
read-write
0x1
0x1
EX
Cleared when read, set when written. See usage description above.
0
1
read-write
ADC0
LPC5410x 12-bit ADC controller (ADC)
ADC
0x1C034000
0
0x74
registers
ADC0_SEQA
26
ADC0_SEQB
27
ADC0_THCMP
28
CTRL
ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls.
0
32
read-write
0x600
0x7FFF
CLKDIV
In synchronous mode only, the system clock is divided by this value plus one to produce the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically, software should program the smallest value in this field that yields this maximum clock rate or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. This field is ignored in the asynchronous operating mode.
0
8
read-write
ASYNMODE
Select clock mode.
8
1
read-write
SYNCHRONOUS_MODE
Synchronous mode. The ADC clock is derived from the system clock based on the divide value selected in the CLKDIV field. The ADC clock will be started in a controlled fashion in response to a trigger to eliminate any uncertainty in the launching of an ADC conversion in response to any synchronous (on-chip) trigger. In Synchronous mode with the SYNCBYPASS bit (in a sequence control register) set, sampling of the ADC input and start of conversion will initiate 2 system clocks after the leading edge of a (synchronous) trigger pulse.
0
ASYNCHRONOUS_MODE
Asynchronous mode. The ADC clock is based on the output of the ADC clock divider ADCCLKSEL in the SYSCON block.
0x1
RESOL
The number of bits of ADC resolution. Accuracy can be reduced to achieve higher conversion rates. A single conversion (including one conversion in a burst or sequence) requires the selected number of bits of resolution plus 3 ADC clocks. This field must only be altered when the ADC is fully idle. Changing it during any kind of ADC operation may have unpredictable results. ADC clock frequencies for various resolutions must not exceed: - 5x the system clock rate for 12-bit resolution - 4.3x the system clock rate for 10-bit resolution - 3.6x the system clock for 8-bit resolution - 3x the bus clock rate for 6-bit resolution
9
2
read-write
RESOLUTION_6_BIT
6-bit resolution. An ADC conversion requires 9 ADC clocks, plus any clocks specified by the TSAMP field.
0
RESOLUTION_8_BIT
8-bit resolution. An ADC conversion requires 11 ADC clocks, plus any clocks specified by the TSAMP field.
0x1
RESOLUTION_10_BIT
10-bit resolution. An ADC conversion requires 13 ADC clocks, plus any clocks specified by the TSAMP field.
0x2
RESOLUTION_12_BIT
12-bit resolution. An ADC conversion requires 15 ADC clocks, plus any clocks specified by the TSAMP field.
0x3
BYPASSCAL
Bypass Calibration. This bit may be set to avoid the need to calibrate if offset error is not a concern in the application.
11
1
read-write
CALIBRATE
Calibrate. The stored calibration value will be applied to the ADC during conversions to compensated for offset error. A calibration cycle must be performed each time the chip is powered-up. Re-calibration may be warranted periodically - especially if operating conditions have changed.
0
BYPASS_CALIBRATION
Bypass calibration. Calibration is not utilized. Less time is required when enabling the ADC - particularly following chip power-up. Attempts to launch a calibration cycle are blocked when this bit is set.
0x1
TSAMP
Sample Time. The default sampling period (TSAMP = '000') at the start of each conversion is 2.5 ADC clock periods. Depending on a variety of factors, including operating conditions and the output impedance of the analog source, longer sampling times may be required. See Section 28.7.10. The TSAMP field specifies the number of additional ADC clock cycles, from zero to seven, by which the sample period will be extended. The total conversion time will increase by the same number of clocks. 000 - The sample period will be the default 2.5 ADC clocks. A complete conversion with 12-bits of accuracy will require 15 clocks. 001- The sample period will be extended by one ADC clock to a total of 3.5 clock periods. A complete 12-bit conversion will require 16 clocks. 010 - The sample period will be extended by two clocks to 4.5 ADC clock cycles. A complete 12-bit conversion will require 17 ADC clocks. 111 - The sample period will be extended by seven clocks to 9.5 ADC clock cycles. A complete 12-bit conversion will require 22 ADC clocks.
12
3
read-write
2
0x4
A,B
SEQ_CTRL%s
ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n.
0x8
32
read-write
0
0xFC0FFFFF
CHANNELS
Selects which one or more of the ADC channels will be sampled and converted when this sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 and so forth. When this conversion sequence is triggered, either by a hardware trigger or via software command, ADC conversions will be performed on each enabled channel, in sequence, beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31) is LOW. It is allowed to change this field and set bit 31 in the same write.
0
12
read-write
TRIGGER
Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field. See Table 476. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
12
6
read-write
TRIGPOL
Select the polarity of the selected input trigger for this conversion sequence. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
18
1
read-write
NEGATIVE_EDGE
Negative edge. A negative edge launches the conversion sequence on the selected trigger input.
0
POSITIVE_EDGE
Positive edge. A positive edge launches the conversion sequence on the selected trigger input.
0x1
SYNCBYPASS
Setting this bit allows the hardware trigger input to bypass synchronization flip-flop stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0): Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period.
19
1
read-write
ENABLE_TRIGGER_SYNCH
Enable trigger synchronization. The hardware trigger bypass is not enabled.
0
BYPASS_TRIGGER_SYNCH
Bypass trigger synchronization. The hardware trigger bypass is enabled.
0x1
START
Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a conversion sequence. It will consequently always read back as a zero.
26
1
read-write
BURST
Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions can be halted by clearing this bit. The sequence currently in progress will be completed before conversions are terminated. Note that a new sequence could begin just before BURST is cleared.
27
1
read-write
SINGLESTEP
When this bit is set, a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels comprising a sequence have been converted, a subsequent trigger will repeat the sequence beginning with the first enabled channel. Interrupt generation will still occur either after each individual conversion or at the end of the entire sequence, depending on the state of the MODE bit.
28
1
read-write
LOWPRIO
Set priority for sequence A.
29
1
read-write
LOW_PRIORITY
Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost.
0
HIGH_PRIORITY
High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion currently in progress will be terminated. The A sequence that was interrupted will automatically resume after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the conversion sequence will resume from that point.
0x1
MODE
Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQA_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which overrun conditions contribute to an overrun interrupt as described below.
30
1
read-write
END_OF_CONVERSION
End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger if enabled.
0
END_OF_SEQUENCE
End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun interrupt/DMA trigger since it is assumed this register may not be utilized in this mode.
0x1
SEQ_ENA
Sequence Enable. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled.
31
1
read-write
DISABLED
Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel.
0
ENABLED
Enabled. Sequence n is enabled.
0x1
2
0x4
A,B
SEQ_GDAT%s
ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n.
0x10
32
read-only
0
0xFC0FFFF0
RESULT
This field contains the 12-bit ADC conversion result from the most recent conversion performed under conversion sequence associated with this register. The result is a binary fraction representing the voltage on the currently-selected input channel as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this result has not yet been read.
4
12
read-only
THCMPRANGE
Indicates whether the result of the last conversion performed was above, below or within the range established by the designated threshold comparison registers (THRn_LOW and THRn_HIGH).
16
2
read-only
THCMPCROSS
Indicates whether the result of the last conversion performed represented a crossing of the threshold level established by the designated LOW threshold comparison register (THRn_LOW) and, if so, in what direction the crossing occurred.
18
2
read-only
CHN
These bits contain the channel from which the RESULT bits were converted (e.g. 0000 identifies channel 0, 0001 channel 1, etc.).
26
4
read-only
OVERRUN
This bit is set if a new conversion result is loaded into the RESULT field before a previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set to '0' (and if the overrun interrupt is enabled).
30
1
read-only
DATAVALID
This bit is set to '1' at the end of each conversion when a new result is loaded into the RESULT field. It is cleared whenever this register is read. This bit will cause a conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that sequence is set to 0 (and if the interrupt is enabled).
31
1
read-only
12
0x4
DAT[%s]
ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0.
0x20
32
read-only
0
0xFC0FFFF0
RESULT
This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
4
12
read-only
THCMPRANGE
Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.
16
2
read-only
THCMPCROSS
Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
18
2
read-only
CHANNEL
This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)
26
4
read-only
OVERRUN
This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
30
1
read-only
DATAVALID
This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
31
1
read-only
THR0_LOW
ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0.
0x50
32
read-write
0
0xFFF0
THRLOW
Low threshold value against which ADC results will be compared
4
12
read-write
THR1_LOW
ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1.
0x54
32
read-write
0
0xFFF0
THRLOW
Low threshold value against which ADC results will be compared
4
12
read-write
THR0_HIGH
ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0.
0x58
32
read-write
0
0xFFF0
THRHIGH
High threshold value against which ADC results will be compared
4
12
read-write
THR1_HIGH
ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1.
0x5C
32
read-write
0
0xFFF0
THRHIGH
High threshold value against which ADC results will be compared
4
12
read-write
CHAN_THRSEL
ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel
0x60
32
read-write
0
0xFFF
CH0_THRSEL
Threshold select for channel 0.
0
1
read-write
THRESHOLD0
Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
0
THRESHOLD1
Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
0x1
CH1_THRSEL
Threshold select for channel 1. See description for channel 0.
1
1
read-write
CH2_THRSEL
Threshold select for channel 2. See description for channel 0.
2
1
read-write
CH3_THRSEL
Threshold select for channel 3. See description for channel 0.
3
1
read-write
CH4_THRSEL
Threshold select for channel 4. See description for channel 0.
4
1
read-write
CH5_THRSEL
Threshold select for channel 5. See description for channel 0.
5
1
read-write
CH6_THRSEL
Threshold select for channel 6. See description for channel 0.
6
1
read-write
CH7_THRSEL
Threshold select for channel 7. See description for channel 0.
7
1
read-write
CH8_THRSEL
Threshold select for channel 8. See description for channel 0.
8
1
read-write
CH9_THRSEL
Threshold select for channel 9. See description for channel 0.
9
1
read-write
CH10_THRSEL
Threshold select for channel 10. See description for channel 0.
10
1
read-write
CH11_THRSEL
Threshold select for channel 11. See description for channel 0.
11
1
read-write
INTEN
ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated.
0x64
32
read-write
0
0x7FFFFFF
SEQA_INTEN
Sequence A interrupt enable.
0
1
read-write
DISABLED
Disabled. The sequence A interrupt/DMA trigger is disabled.
0
ENABLED
Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of conversions, depending on the MODE bit in the SEQA_CTRL register.
0x1
SEQB_INTEN
Sequence B interrupt enable.
1
1
read-write
DISABLED
Disabled. The sequence B interrupt/DMA trigger is disabled.
0
ENABLED
Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of conversions, depending on the MODE bit in the SEQB_CTRL register.
0x1
OVR_INTEN
Overrun interrupt enable.
2
1
read-write
DISABLED
Disabled. The overrun interrupt is disabled.
0
ENABLED
Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular sequence is 0, then an overrun in the global data register for that sequence will also cause this interrupt/DMA trigger to be asserted.
0x1
ADCMPINTEN0
Threshold comparison interrupt enable for channel 0.
3
2
read-write
DISABLED
Disabled.
0
OUTSIDE_THRESHOLD
Outside threshold.
0x1
CROSSING_THRESHOLD
Crossing threshold.
0x2
ADCMPINTEN1
Channel 1 threshold comparison interrupt enable. See description for channel 0.
5
2
read-write
ADCMPINTEN2
Channel 2 threshold comparison interrupt enable. See description for channel 0.
7
2
read-write
ADCMPINTEN3
Channel 3 threshold comparison interrupt enable. See description for channel 0.
9
2
read-write
ADCMPINTEN4
Channel 4 threshold comparison interrupt enable. See description for channel 0.
11
2
read-write
ADCMPINTEN5
Channel 5 threshold comparison interrupt enable. See description for channel 0.
13
2
read-write
ADCMPINTEN6
Channel 6 threshold comparison interrupt enable. See description for channel 0.
15
2
read-write
ADCMPINTEN7
Channel 7 threshold comparison interrupt enable. See description for channel 0.
17
2
read-write
ADCMPINTEN8
Channel 8 threshold comparison interrupt enable. See description for channel 0.
19
2
read-write
ADCMPINTEN9
Channel 9 threshold comparison interrupt enable. See description for channel 0.
21
2
read-write
ADCMPINTEN10
Channel 10 threshold comparison interrupt enable. See description for channel 0.
23
2
read-write
ADCMPINTEN11
Channel 21 threshold comparison interrupt enable. See description for channel 0.
25
2
read-write
FLAGS
ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers).
0x68
32
read-write
0
0xF3FFFFFF
THCMP0
Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1.
0
1
read-write
THCMP1
Threshold comparison event on Channel 1. See description for channel 0.
1
1
read-write
THCMP2
Threshold comparison event on Channel 2. See description for channel 0.
2
1
read-write
THCMP3
Threshold comparison event on Channel 3. See description for channel 0.
3
1
read-write
THCMP4
Threshold comparison event on Channel 4. See description for channel 0.
4
1
read-write
THCMP5
Threshold comparison event on Channel 5. See description for channel 0.
5
1
read-write
THCMP6
Threshold comparison event on Channel 6. See description for channel 0.
6
1
read-write
THCMP7
Threshold comparison event on Channel 7. See description for channel 0.
7
1
read-write
THCMP8
Threshold comparison event on Channel 8. See description for channel 0.
8
1
read-write
THCMP9
Threshold comparison event on Channel 9. See description for channel 0.
9
1
read-write
THCMP10
Threshold comparison event on Channel 10. See description for channel 0.
10
1
read-write
THCMP11
Threshold comparison event on Channel 11. See description for channel 0.
11
1
read-write
OVERRUN0
Mirrors the OVERRRUN status flag from the result register for ADC channel 0
12
1
read-only
OVERRUN1
Mirrors the OVERRRUN status flag from the result register for ADC channel 1
13
1
read-only
OVERRUN2
Mirrors the OVERRRUN status flag from the result register for ADC channel 2
14
1
read-only
OVERRUN3
Mirrors the OVERRRUN status flag from the result register for ADC channel 3
15
1
read-only
OVERRUN4
Mirrors the OVERRRUN status flag from the result register for ADC channel 4
16
1
read-only
OVERRUN5
Mirrors the OVERRRUN status flag from the result register for ADC channel 5
17
1
read-only
OVERRUN6
Mirrors the OVERRRUN status flag from the result register for ADC channel 6
18
1
read-only
OVERRUN7
Mirrors the OVERRRUN status flag from the result register for ADC channel 7
19
1
read-only
OVERRUN8
Mirrors the OVERRRUN status flag from the result register for ADC channel 8
20
1
read-only
OVERRUN9
Mirrors the OVERRRUN status flag from the result register for ADC channel 9
21
1
read-only
OVERRUN10
Mirrors the OVERRRUN status flag from the result register for ADC channel 10
22
1
read-only
OVERRUN11
Mirrors the OVERRRUN status flag from the result register for ADC channel 11
23
1
read-only
SEQA_OVR
Mirrors the global OVERRUN status flag in the SEQA_GDAT register
24
1
read-only
SEQB_OVR
Mirrors the global OVERRUN status flag in the SEQB_GDAT register
25
1
read-only
SEQA_INT
Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which is set at the end of every ADC conversion performed as part of sequence A. It will be cleared automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register is 1, this flag will be set upon completion of an entire A sequence. In this case it must be cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN register.
28
1
read-only
SEQB_INT
Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which is set at the end of every ADC conversion performed as part of sequence B. It will be cleared automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register is 1, this flag will be set upon completion of an entire B sequence. In this case it must be cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN register.
29
1
read-only
THCMP_INT
Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in the lower bits of this register are set to 1 (due to an enabled out-of-range or threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be individually enabled in the INTEN register to cause this interrupt. This bit will be cleared when all of the individual threshold flags are cleared via writing 1s to those bits.
30
1
read-only
OVR_INT
Overrun Interrupt flag. Any overrun bit in any of the individual channel data registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all of the individual overrun bits have been cleared via reading the corresponding data registers.
31
1
read-only
STARTUP
ADC Startup register.
0x6C
32
read-write
0
0x3
ADC_ENA
ADC Enable bit. This bit can only be set to a 1 by software. It is cleared automatically whenever the ADC is powered down. This bit must not be set until at least 10 microseconds after the ADC is powered up (typically by altering a system-level ADC power control bit).
0
1
read-write
ADC_INIT
ADC Initialization. After enabling the ADC (setting the ADC_ENA bit), the API routine will EITHER set this bit or the CALIB bit in the CALIB register, depending on whether or not calibration is required. Setting this bit will launch the 'dummy' conversion cycle that is required if a calibration is not performed. It will also reload the stored calibration value from a previous calibration unless the BYPASSCAL bit is set. This bit should only be set AFTER the ADC_ENA bit is set and after the CALIREQD bit is tested to determine whether a calibration or an ADC dummy conversion cycle is required. It should not be set during the same write that sets the ADC_ENA bit. This bit can only be set to a '1' by software. It is cleared automatically when the 'dummy' conversion cycle completes.
1
1
read-write
CALIB
ADC Calibration register.
0x70
32
read-write
0x2
0x1FF
CALIB
Calibration request. Setting this bit will launch an ADC calibration cycle. This bit can only be set to a '1' by software. It is cleared automatically when the calibration cycle completes.
0
1
read-write
CALREQD
Calibration required. This read-only bit indicates if calibration is required when enabling the ADC. CALREQD will be '1' if no calibration has been run since the chip was powered-up and if the BYPASSCAL bit in the CTRL register is low. Software will test this bit to determine whether to initiate a calibration cycle or whether to set the ADC_INIT bit (in the STARTUP register) to launch the ADC initialization process which includes a 'dummy' conversion cycle. Note: A 'dummy' conversion cycle requires approximately 6 ADC clocks as opposed to 81 clocks required for calibration.
1
1
read-write
CALVALUE
Calibration Value. This read-only field displays the calibration value established during last calibration cycle. This value is not typically of any use to the user.
2
7
read-write
VFIFO
System FIFO for Serial Peripherals
VFIFO
0x1C038000
0
0x211C
registers
FIFOCTLUSART
USART FIFO global control register. These registers are byte, halfword, and word addressable.The upper 16 bits of these registers provide information about the System FIFO configuration, and are specific to each device type.
0x100
32
read-write
0x707
0xFFFFFFFF
RXPAUSE
Pause all USARTs receive FIFO operations. This can be used to prepare the System FIFO to reconfigure FIFO allocations among the USART receivers.
0
1
read-write
RXPAUSED
All USART receive FIFOs are paused.
1
1
read-write
RXEMPTY
All USART receive FIFOs are empty.
2
1
read-write
TXPAUSE
Pause all USARTs transmit FIFO operations. This can be used to prepare the System FIFO to reconfigure FIFO allocations among the USART transmitters.
8
1
read-write
TXPAUSED
All USART transmit FIFOs are paused.
9
1
read-write
TXEMPTY
All USART transmit FIFOs are empty.
10
1
read-write
RXFIFOTOTAL
Reports the receive FIFO space available for USARTs on this FIFO. The reset value is device specific.
16
8
read-write
TXFIFOTOTAL
Reports the transmit FIFO space available for USARTs on this FIFO. The reset value is device specific.
24
8
read-write
FIFOUPDATEUSART
USART FIFO global update register
0x104
32
read-write
0
0
USART0RXUPDATESIZE
Writing 1 updates USART0 Rx FIFO size to match the USART0 RXSIZE. Must be done for all USARTs when any USART RXSIZE is changed.
0
1
read-write
USART1RXUPDATESIZE
Writing 1 updates USART1 Rx FIFO size to match the USART1 RXSIZE. Must be done for all USARTs when any USART RXSIZE is changed.
1
1
read-write
USART2RXUPDATESIZE
Writing 1 updates USART2 Rx FIFO size to match the USART2 RXSIZE. Must be done for all USARTs when any USART RXSIZE is changed.
2
1
read-write
USART3RXUPDATESIZE
Writing 1 updates USART3 Rx FIFO size to match the USART3 RXSIZE. Must be done for all USARTs when any USART RXSIZE is changed.
3
1
read-write
USART0TXUPDATESIZE
Writing 1 updates USART0 Tx FIFO size to match the USART0 TXSIZE. Must be done for all USARTs when any USART TXSIZE is changed.
16
1
read-write
USART1TXUPDATESIZE
Writing 1 updates USART1 Tx FIFO size to match the USART1 TXSIZE. Must be done for all USARTs when any USART TXSIZE is changed.
17
1
read-write
USART2TXUPDATESIZE
Writing 1 updates USART2 Tx FIFO size to match the USART2 TXSIZE. Must be done for all USARTs when any USART TXSIZE is changed.
18
1
read-write
USART3TXUPDATESIZE
Writing 1 updates USART3 Tx FIFO size to match the USART3 TXSIZE. Must be done for all USARTs when any USART TXSIZE is changed.
19
1
read-write
4
0x4
FIFOCFGUSART[%s]
FIFO configuration register for USART0
0x110
32
read-write
0
0xFFFFFFFF
RXSIZE
Configures the USART receive FIFO size. A zero values provides no System FIFO service for the related USART receiver.
0
8
read-write
TXSIZE
Configures the USART transmit FIFO size. A zero values provides no System FIFO service for the related USART transmitter.
8
8
read-write
FIFOCTLSPI
SPI FIFO global control register. These registers are byte, halfword, and word addressable. The upper 16 bits of these registers provide information about the System FIFO configuration, and are specific to each device type.
0x200
32
read-write
0x707
0xFFFFFFFF
RXPAUSE
Pause all SPIs receive FIFO operations. This can be used to prepare the System FIFO to reconfigure FIFO allocations among the SPI receivers.
0
1
read-write
RXPAUSED
All SPI receive FIFOs are paused.
1
1
read-write
RXEMPTY
All SPI receive FIFOs are empty.
2
1
read-write
TXPAUSE
Pause all SPIs transmit FIFO operations. This can be used to prepare the System FIFO to reconfigure FIFO allocations among the SPI transmitters.
8
1
read-write
TXPAUSED
All SPI transmit FIFOs are paused.
9
1
read-write
TXEMPTY
All SPI transmit FIFOs are empty.
10
1
read-write
RXFIFOTOTAL
Reports the receive FIFO space available for SPIs on the System FIFO. The reset value is device specific.
16
8
read-write
TXFIFOTOTAL
Reports the transmit FIFO space available for SPIs on the System FIFO. The reset value is device specific.
24
8
read-write
FIFOUPDATESPI
SPI FIFO global update register
0x204
32
read-write
0
0
SPI0RXUPDATESIZE
Writing 1 updates SPI0 Rx FIFO size to match the SPI0 RXSIZE. Must be done for all SPIs when any SPI RXSIZE is changed.
0
1
read-write
SPI1RXUPDATESIZE
Writing 1 updates SPI1 Rx FIFO size to match the SPI1 RXSIZE. Must be done for all SPIs when any SPI RXSIZE is changed.
1
1
read-write
SPI0TXUPDATESIZE
Writing 1 updates SPI0 Tx FIFO size to match the SPI0 TXSIZE. Must be done for all SPIs when any SPI TXSIZE is changed.
16
1
read-write
SPI1TXUPDATESIZE
Writing 1 updates SPI1 Tx FIFO size to match the SPI1 TXSIZE. Must be done for all SPIs when any SPI TXSIZE is changed.
17
1
read-write
2
0x4
FIFOCFGSPI[%s]
FIFO configuration register for SPI0
0x210
32
read-write
0
0xFFFFFFFF
RXSIZE
Configures the SPI receive FIFO size. A zero values provides no System FIFO service for the related SPI receiver.
0
8
read-write
TXSIZE
Configures the SPI transmit FIFO size. A zero values provides no System FIFO service for the related SPI transmitter.
8
8
read-write
4
0x100
USART[%s]
no description available
0x1000
CFGUSART
USART0 configuration
0
32
read-write
0
0xFFFFFFFF
TIMEOUTCONTONWRITE
Timeout Continue On Write. When 0, the timeout for the related peripheral is reset every time data is transferred from the peripheral into the receive FIFO. When 1, the timeout for the related peripheral is not reset every time data is transferred into the receive FIFO. This allows the timeout to be applied to accumulated data, perhaps related to the FIFO threshold.
4
1
read-write
TIMEOUTCONTONEMPTY
Timeout Continue On Empty. When 0, the timeout for the related peripheral is reset when the receive FIFO becomes empty. When 1, the timeout for the related peripheral is not reset when the receive FIFO becomes empty. This allows the timeout to be used to flag idle peripherals, and could potentially be used to indicate the end of a transmission of indeterminate length.
5
1
read-write
TIMEOUTBASE
Specifies the least significant timer bit to compare to TimeoutValue. See Section 24.5.7.1 below. Value can be 0 through 15.
8
4
read-write
TIMEOUTVALUE
Specifies the maximum time value for timeout at the timer position identified by TimeoutBase. Minimum time TimeoutValue - 1. is See Section 24.5.7.1 below. TimeoutValue should not be 0 or 1 when timeout is enabled.
12
4
read-write
RXTHRESHOLD
Receive FIFO Threshold. The System FIFO indicates that the threshold has been reached when the number of entries in the receive FIFO is greater than this value. For example, when RxThreshold = 0, the threshold is exceeded when there is at least one entry in the receive FIFO. An interrupt can be generated when the RxThreshold has been reached (see Section 24.5.10), but has no effect on DMA requests, which are generated whenever the receiver FIFO is not empty.
16
8
read-write
TXTHRESHOLD
Transmit FIFO Threshold. The System FIFO indicates that the threshold has been reached when the number of free entries in the transmit FIFO is less than or equal to this value. For example, when TxThreshold = 0, the threshold is exceeded when there is at least one free entry in the transmit FIFO. An interrupt can be generated when the TxThreshold has been reached (see Section 24.5.10), but has no effect on DMA requests, which are generated whenever the transmit FIFO has any free entries.
24
8
read-write
STATUSART
USART0 status
0x4
32
read-write
0x300
0xFFFFFFFF
RXTH
Receive FIFO Threshold. When 1, the receive FIFO threshold has been reached. This is a read-only bit.
0
1
read-write
TXTH
Transmit FIFO Threshold. When 1, the transmit FIFO threshold has been reached. This is a read-only bit.
1
1
read-write
RXTIMEOUT
Receive FIFO Timeout. When 1, the receive FIFO has timed out, based on the timeout configuration in the CFGUSART register. The timeout condition can be cleared by writing a 1 to this bit, by enabling or disabling the timeout interrupt, or by writing a 1 to the timeout interrupt enable.
4
1
read-write
BUSERR
Bus Error. When 1, a bus error has occurred while processing data for USARTn. The bus error flag can be cleared by writing a 1 to this bit.
7
1
read-write
RXEMPTY
Receive FIFO Empty. When 1, the receive FIFO is currently empty. This is a read-only bit.
8
1
read-write
TXEMPTY
Transmit FIFO Empty. When 1, the transmit FIFO is currently empty. This is a read-only bit.
9
1
read-write
RXCOUNT
Receive FIFO Count. Indicates how many entries may be read from the receive FIFO. 0 = FIFO empty. This is a read-only field.
16
8
read-write
TXCOUNT
Transmit FIFO Count. Indicates how many entries may be written to the transmit FIFO. 0 = FIFO full. This is a read-only field that is valid only when the TxFIFO is fully configured and enabled.
24
8
read-write
INTSTATUSART
USART0 interrupt status
0x8
32
read-write
0x300
0xFFFFFFFF
RXTH
Receive FIFO Threshold. When 1, the receive FIFO threshold has been reached, and the related interrupt is enabled.
0
1
read-write
TXTH
Transmit FIFO Threshold. When 1, the transmit FIFO threshold has been reached, and the related interrupt is enabled.
1
1
read-write
RXTIMEOUT
Receive Timeout. When 1, the receive FIFO has timed out, based on the timeout configuration in the CFGUSART register, and the related interrupt is enabled.
4
1
read-write
BUSERR
Bus Error. This is simply a copy of the same bit in the STATUSART register. The bus error interrupt is always enabled.
7
1
read-write
RXEMPTY
Receive FIFO Empty. This is simply a copy of the same bit in the STATUSART register.
8
1
read-write
TXEMPTY
Transmit FIFO Empty. This is simply a copy of the same bit in the STATUSART register.
9
1
read-write
RXCOUNT
Receive FIFO Count. This is simply a copy of the same field in the STATUSART register, included here so an ISR can read all needed status information in one read.
16
8
read-write
TXCOUNT
Transmit FIFO Available. This is simply a copy of the same field in the STATUSART register, included here so an ISR can read all needed status information in one read.
24
8
read-write
CTLSETUSART
USART0 control read and set register. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
0xC
32
read-write
0
0xFFFFFFFF
RXTHINTEN
Receive FIFO Threshold Interrupt Enable.
0
1
read-write
TXTHINTEN
Transmit FIFO Threshold Interrupt Enable.
1
1
read-write
RXTIMEOUTINTEN
Receive FIFO Timeout Interrupt Enable. When enabled, this also enables the timeout for this USART. Writing a 1 to this bit resets the USART timeout logic.
4
1
read-write
RXFLUSH
Receive FIFO flush. Writing a 1 to this bit forces the receive FIFO to be empty.
8
1
read-write
TXFLUSH
Transmit FIFO flush. Writing a 1 to this bit forces the transmit FIFO to be empty.
9
1
read-write
CTLCLRUSART
USART0 control clear register. Writing a 1 to any implemented bit position causes the corresponding bit in the related CTLSET register to be cleared.
0x10
32
read-write
0
0
RXTHINTCLR
Receive FIFO Threshold Interrupt clear.
0
1
read-write
TXTHINTCLR
Transmit FIFO Threshold Interrupt clear.
1
1
read-write
RXTIMEOUTINTCLR
Receive FIFO Time-out Interrupt clear.
4
1
read-write
RXFLUSHCLR
Receive FIFO flush clear.
8
1
read-write
TXFLUSHCLR
Transmit FIFO flush clear.
9
1
read-write
RXDATUSART
USART0 received data
0x14
32
read-write
0
0
RXDAT
The UART Receiver Data register contains the next received character. The number of bits that are relevant depends on the UART configuration settings.
0
9
read-write
RXDATSTATUSART
USART0 received data with status
0x18
32
read-write
0
0
RXDAT
The UART Receiver Data register contains the next received character. The number of bits that are relevant depends on the UART configuration settings.
0
9
read-write
FRAMERR
Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.
13
1
read-write
PARITYERR
Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character.
14
1
read-write
RXNOISE
Received Noise flag.
15
1
read-write
TXDATUSART
USART0 transmit data
0x1C
32
read-write
0
0xFFFFFFFF
TXDAT
Writing to the UART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and the condition for transmitting data is met: TXDIS bit = 0.
0
9
read-write
2
0x100
SPI[%s]
no description available
0x2000
CFGSPI
SPI0 configuration
0
32
read-write
0
0xFFFFFFFF
TIMEOUTCONTONWRITE
Timeout Continue On Write. When 0, the timeout for the related peripheral is reset every time data is transferred from the peripheral into the receive FIFO. When 1, the timeout for the related peripheral is not reset every time data is transferred into the receive FIFO. This allows the timeout to be applied to accumulated data, perhaps related to the FIFO threshold.
4
1
read-write
TIMEOUTCONTONEMPTY
Timeout Continue On Empty. When 0, the timeout for the related peripheral is reset when the receive FIFO becomes empty. When 1, the timeout for the related peripheral is not reset when the receive FIFO becomes empty. This allows the timeout to be used to flag idle peripherals, and could potentially be used to indicate the end of a transmission of indeterminate length.
5
1
read-write
TIMEOUTBASE
Specifies the least significant timer bit to compare to TimeoutValue. Value can be 0 through 15.
8
4
read-write
TIMEOUTVALUE
Specifies the maximum time value for timeout at the timer position identified by TimeoutBase. Minimum time TimeoutValue - 1. TimeoutValue should not be 0 or 1 when timeout is enabled.
12
4
read-write
RXTHRESHOLD
Receive FIFO Threshold. The System FIFO indicates that the threshold has been reached when the number of entries in the receive FIFO is greater than this value. For example, when RxThreshold = 0, the threshold is exceeded when there is at least one entry in the receive FIFO. An interrupt can be generated when the RxThreshold has been reached, but has no effect on DMA requests, which are generated whenever the receiver FIFO is not empty.
16
8
read-write
TXTHRESHOLD
Transmit FIFO Threshold. The System FIFO indicates that the threshold has been reached when the number of free entries in the transmit FIFO is less than or equal to this value. For example, when TxThreshold = 0, the threshold is exceeded when there is at least one free entry in the transmit FIFO. An interrupt can be generated when the TxThreshold has been reached, but has no effect on DMA requests, which are generated whenever the transmit FIFO has any free entries.
24
8
read-write
STATSPI
SPI0 status
0x4
32
read-write
0x300
0xFFFFFFFF
RXTH
Receive FIFO Threshold. When 1, the receive FIFO threshold has been reached. This is a read-only bit.
0
1
read-write
TXTH
Transmit FIFO Threshold. When 1, the transmit FIFO threshold has been reached. This is a read-only bit.
1
1
read-write
RXTIMEOUT
Receive FIFO Timeout. When 1, the receive FIFO has timed out, based on the timeout configuration in the CFGSPI register. The timeout condition can be cleared by writing a 1 to this bit, by enabling or disabling the timeout interrupt, or by writing a 1 to the timeout interrupt enable.
4
1
read-write
BUSERR
Bus Error. When 1, a bus error has occurred while processing data for SPI. The bus error flag can be cleared by writing a 1 to this bit.
7
1
read-write
RXEMPTY
Receive FIFO Empty. When 1, the receive FIFO is currently empty. This is a read-only bit.
8
1
read-write
TXEMPTY
Transmit FIFO Empty. When 1, the transmit FIFO is currently empty. This is a read-only bit.
9
1
read-write
RXCOUNT
Receive FIFO Count. Indicates how many entries may be read from the receive FIFO. 0 = FIFO empty. This is a read-only field.
16
8
read-write
TXCOUNT
Transmit FIFO Count. Indicates how many entries may be written to the transmit FIFO. 0 = FIFO full. This is a read-only field that is valid only when the TxFIFO is fully configured and enabled.
24
8
read-write
INTSTATSPI
SPI0 interrupt status
0x8
32
read-write
0x300
0xFFFFFFFF
RXTH
Receive FIFO Threshold. When 1, the receive FIFO threshold has been reached, and the related interrupt is enabled.
0
1
read-write
TXTH
Transmit FIFO Threshold. When 1, the transmit FIFO threshold has been reached, and the related interrupt is enabled.
1
1
read-write
RXTIMEOUT
Receive Timeout. When 1, the receive FIFO has timed out, based on the timeout configuration in the CFGSPI register, and the related interrupt is enabled.
4
1
read-write
BUSERR
Bus Error. This is simply a copy of the same bit in the STATSPI register. The bus error interrupt is always enabled.
7
1
read-write
RXEMPTY
Receive FIFO Empty. This is simply a copy of the same bit in the STATSPI register.
8
1
read-write
TXEMPTY
Transmit FIFO Empty. This is simply a copy of the same bit in the STATSPI register.
9
1
read-write
RXCOUNT
Receive FIFO Count. This is simply a copy of the same field in the STATSPI register, included here so an ISR can read all needed status information in one read.
16
8
read-write
TXCOUNT
Transmit FIFO Available. This is simply a copy of the same field in the STATSPI register, included here so an ISR can read all needed status information in one read.
24
8
read-write
CTLSETSPI
SPI0 control read and set register. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
0xC
32
read-write
0
0xFFFFFFFF
RXTHINTEN
Receive FIFO Threshold Interrupt Enable.
0
1
read-write
TXTHINTEN
Transmit FIFO Threshold Interrupt Enable.
1
1
read-write
RXTIMEOUTINTEN
Receive FIFO Timeout Interrupt Enable. When enabled, this also enables the timeout for this SPI. Writing a 1 to this bit resets the SPI timeout logic.
4
1
read-write
RXFLUSH
Receive FIFO flush. Writing a 1 to this bit forces the receive FIFO to be empty.
8
1
read-write
TXFLUSH
Transmit FIFO flush. Writing a 1 to this bit forces the transmit FIFO to be empty.
9
1
read-write
CTLCLRSPI
SPI0 control clear register. Writing a 1 to any implemented bit position causes the corresponding bit in the related CTLSET register to be cleared.
0x10
32
read-write
0
0
RXTHINTCLR
Receive FIFO Threshold Interrupt clear.
0
1
read-write
TXTHINTCLR
Transmit FIFO Threshold Interrupt clear.
1
1
read-write
RXTIMEOUTINTCLR
Receive FIFO Timeout Interrupt clear.
4
1
read-write
RXFLUSHCLR
Receive FIFO flush clear. do the clear bits 8 and 9 do anything?
8
1
read-write
TXFLUSHCLR
Transmit FIFO flush clear.
9
1
read-write
RXDATSPI
SPI0 received data. These registers are half word addressable.
0x14
32
read-write
0
0
RXDAT
Receiver Data. This contains the next piece of received data. The number of bits that are used depends on the LEN setting in TXCTL / TXDATCTL.
0
16
read-write
RXSSEL0_N
Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
16
1
read-write
RXSSEL1_N
Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
17
1
read-write
RXSSEL2_N
Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
18
1
read-write
RXSSEL3_N
Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
19
1
read-write
SOT
Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the transfer length is greater than 16 bit.
20
1
read-write
TXDATSPI
SPI0 transmit data. These registers are half word addressable.
0x18
32
read-write
0
0
TXDAT
Transmit Data. This field provides from 1 to 16 bits of data to be transmitted.
0
16
read-write
TXSSEL0_N
Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. The active state of the SSEL0 pin is configured by bits in the CFG register.
16
1
read-write
ASSERTED
Asserted. SSEL0 asserted.
0
NOT_ASSERTED
Not asserted. SSEL0 not asserted.
0x1
TXSSEL1_N
Transmit Slave Select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. The active state of the SSEL1 pin is configured by bits in the CFG register.
17
1
read-write
ASSERTED
Asserted. SSEL1 asserted.
0
NOT_ASSERTED
Not asserted. SSEL1 not asserted.
0x1
TXSSEL2_N
Transmit Slave Select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. The active state of the SSEL2 pin is configured by bits in the CFG register.
18
1
read-write
ASSERTED
Asserted. SSEL2 asserted.
0
NOT_ASSERTED
Not asserted. SSEL2 not asserted.
0x1
TXSSEL3_N
Transmit Slave Select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. The active state of the SSEL3 pin is configured by bits in the CFG register.
19
1
read-write
ASSERTED
Asserted. SSEL3 asserted.
0
NOT_ASSERTED
Not asserted. SSEL3 not asserted.
0x1
EOT
End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain so for at least the time specified by the Transfer_delay value in the DLY register.
20
1
read-write
NOT_DEASSERTED
Not deasserted. SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.
0
DEASSERTED
Deasserted. SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data.
0x1
EOF
End of Frame. Between frames, a delay may be inserted, as defined by the FRAME_DELAY value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for frame lengths greater than 16 bits.
21
1
read-write
DATA_NOT_EOF
Data not EOF. This piece of data transmitted is not treated as the end of a frame.
0
DATA_EOF
Data EOF. This piece of data is treated as the end of a frame, causing the FRAME_DELAY time to be inserted before subsequent data is transmitted.
0x1
RXIGNORE
Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver to simplify the transmit process and can be used with the DMA.
22
1
read-write
READ_RECEIVED_DATA
Read received data. Received data must be read in order to allow transmission to progress. In slave mode, an overrun error will occur if received data is not read before new data is received.
0
IGNORE_RECEIVED_DATA
Ignore received data. Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated.
0x1
LEN
Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential data transmits. 0x0 = Data transfer is 1 bit in length. 0x1 = Data transfer is 2 bits in length. 0x2 = Data transfer is 3 bits in length. ... 0xF = Data transfer is 16 bits in length.
24
4
read-write
SYSCON
System configuration
SYSCON
0x40000000
0
0x2C048
registers
SYSMEMREMAP
System memory remap
0
32
read-write
0
0xFFFFFFFF
MAP
System memory remap. Value 0x3 is reserved.
0
2
read-write
BOOT_LOADER_MODE
Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM.
0
USER_RAM_MODE
User RAM Mode. Interrupt vectors are re-mapped to Static RAM.
0x1
USER_FLASH_MODE
User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash.
0x2
AHBMATPRIO
AHB multilayer matrix priority control
0x4
32
read-write
0
0xFFFFFFFF
PRI_ICODE
I-Code bus priority. Should be lower than PRI_DCODE for proper operation.
0
2
read-write
PRI_DCODE
D-Code bus priority.
2
2
read-write
PRI_SYS
System bus priority.
4
2
read-write
PRI_DMA
DMA controller priority.
8
2
read-write
PRI_FIFO
System FIFO bus priority
14
2
read-write
PRI_M0
Cortex-M0+ bus priority.
16
2
read-write
SYSTCKCAL
System tick counter calibration
0x14
32
read-write
0
0xFFFFFFFF
CAL
System tick timer calibration value.
0
24
read-write
SKEW
Initial value for the Systick timer.
24
1
read-write
NOREF
Initial value for the Systick timer.
25
1
read-write
NMISRC
NMI Source Select
0x1C
32
read-write
0
0xFFFFFFFF
IRQM4
The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M4, if enabled by NMIENM4.
0
6
read-write
IRQM0
The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M0+, if enabled by NMIENM0.
8
6
read-write
NMIENM0
Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM0.
30
1
read-write
NMIENM4
Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM4.
31
1
read-write
ASYNCAPBCTRL
Asynchronous APB Control
0x20
32
read-write
0x1
0xFFFFFFFF
ENABLE
Enables the asynchronous APB bridge and subsystem.
0
1
read-write
DISABLED
Disabled. Asynchronous APB bridge is disabled.
0
ENABLED
Enabled. Asynchronous APB bridge is enabled.
0x1
SYSRSTSTAT
System reset status register
0x40
32
read-write
0
0xFFFFFFFF
POR
POR reset status
0
1
read-write
NO_POR_DETECTED
No POR detected
0
POR_DETECTED
POR detected. Writing a one clears this reset.
0x1
EXTRST
Status of the external RESET pin. External reset status.
1
1
read-write
NO_RESET_EVENT_DETEC
No reset event detected.
0
RESET_DETECTED
Reset detected. Writing a one clears this reset.
0x1
WDT
Status of the Watchdog reset
2
1
read-write
NO_WDT_RESET_DETECTE
No WDT reset detected
0
WDT_RESET_DETECTED
WDT reset detected. Writing a one clears this reset.
0x1
BOD
Status of the Brown-out detect reset
3
1
read-write
NO_BOD_RESET_DETECTE
No BOD reset detected
0
BOD_RESET_DETECTED
BOD reset detected. Writing a one clears this reset.
0x1
SYSRST
Status of the software system reset
4
1
read-write
NO_SYSTEM_RESET_DETE
No System reset detected
0
SYSTEM_RESET_DETECTE
System reset detected. Writing a one clears this reset.
0x1
PRESETCTRL0
Peripheral reset control n
0x44
32
read-write
0
0xFFFFFFFF
FLASH_RST
Flash controller reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
7
1
read-write
FMC_RST
Flash accelerator reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
8
1
read-write
MUX_RST
Input mux reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
11
1
read-write
IOCON_RST
IOCON reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
13
1
read-write
GPIO0_RST
GPIO0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
14
1
read-write
GPIO1_RST
GPIO1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
15
1
read-write
PINT_RST
Pin interrupt (PINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
18
1
read-write
GINT_RST
Grouped interrupt (GINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
19
1
read-write
DMA_RST
DMA reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
20
1
read-write
CRC_RST
CRC generator reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
21
1
read-write
WWDT_RST
Watchdog timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
22
1
read-write
ADC0_RST
ADC0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
27
1
read-write
PRESETCTRL1
Peripheral reset control n
0x48
32
read-write
0
0xFFFFFFFF
MRT_RST
Multi-rate timer (MRT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
0
1
read-write
RIT_RST
Repetitive interrupt timer (RIT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
1
1
read-write
SCT0_RST
State configurable timer 0 (SCT0) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
2
1
read-write
FIFO_RST
System FIFO reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
9
1
read-write
UTICK_RST
Micro-tick Timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
10
1
read-write
CT32B2_RST
CT32B 2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
22
1
read-write
CT32B3_RST
CT32B 3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
26
1
read-write
CT32B4_RST
CT32B 4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
27
1
read-write
2
0x4
PRESETCTRLSET[%s]
Set bits in PRESETCTRL n
0x4C
32
read-write
0
0
RST_SET
Writing ones to this register sets the corresponding bit or bits in the PRESETCTRL n register, if they are implemented. Bits that do not correspond to defined bits in PRESETCTRL0 are reserved and only zeroes should be written to them.
0
32
read-write
2
0x4
PRESETCTRLCLR[%s]
Clear bits in PRESETCTRL n
0x54
32
read-write
0
0
RST_CLR
Writing ones to this register clears the corresponding bit or bits in the PRESETCTRL n register, if they are implemented. Bits that do not correspond to defined bits in PRESETCTRL0 are reserved and only zeroes should be written to them.
0
32
read-write
PIOPORCAP0
POR captured PIO status 0
0x5C
32
read-write
0
0
PIOPORSTAT
State of PIO0_31 through PIO0_0 at power-on reset
0
32
read-write
PIOPORCAP1
POR captured PIO status 1
0x60
32
read-write
0
0
PIOPORSTAT
State of PIO1_31 through PIO1_0 at power-on reset
0
32
read-write
PIORESCAP0
Reset captured PIO status 0
0x68
32
read-write
0
0
PIORESSTAT
State of PIO0_31 through PIO0_0 for resets other than power-on reset.
0
32
read-write
PIORESCAP1
Reset captured PIO status 1
0x6C
32
read-write
0
0
PIORESSTAT
State of PIO1_31 through PIO1_0 for resets other than power-on reset.
0
32
read-write
MAINCLKSELA
Main clock source select A
0x80
32
read-write
0
0xFFFFFFFF
SEL
Clock source for main clock source selector A
0
2
read-write
IRC_OSCILLATOR
IRC Oscillator
0
CLKIN
CLKIN
0x1
WATCHDOG_OSCILLATOR
Watchdog oscillator
0x2
MAINCLKSELB
Main clock source select B
0x84
32
read-write
0
0xFFFFFFFF
SEL
Clock source for main clock source selector B. Selects the clock source for the main clock.
0
2
read-write
MAINCLKSELA
MAINCLKSELA. Use the clock source selected in MAINCLKSELA register.
0
SYSTEM_PLL_INPUT
System PLL input.
0x1
SYSTEM_PLL_OUTPUT
System PLL output.
0x2
RTC_OSC_OUTPUT
RTC osc output. RTC oscillator 32 kHz output.
0x3
ADCCLKSEL
ADC clock source select
0x8C
32
read-write
0
0xFFFFFFFF
SEL
ADC clock source.
0
2
read-write
MAIN_CLOCK
Main clock
0
SYSTEM_PLL_OUTPUT
System PLL output
0x1
IRC_OSCILLATOR
IRC Oscillator
0x2
CLKOUTSELA
CLKOUT clock source select A
0x94
32
read-write
0
0xFFFFFFFF
SEL
CLKOUT clock source
0
2
read-write
MAIN_CLOCK
Main clock
0
CLKIN
CLKIN
0x1
WATCHDOG_OSCILLATOR
Watchdog oscillator
0x2
IRC_OSCILLATOR
IRC oscillator
0x3
CLKOUTSELB
CLKOUT clock source select B
0x98
32
read-write
0
0xFFFFFFFF
SEL
CLKOUT clock source
0
2
read-write
CLKOUTSELA
CLKOUTSELA. Clock source selected in the CLKOUTSELA register.
0
RTC_32_KHZ_CLOCK
RTC 32 kHz clock
0x3
SYSPLLCLKSEL
PLL clock source select
0xA0
32
read-write
0
0xFFFFFFFF
SEL
System PLL clock source
0
2
read-write
IRC_OSCILLATOR
IRC Oscillator
0
CLKIN
CLKIN
0x1
WATCHDOG_OSCILLATOR
Watchdog oscillator
0x2
RTC_32_KHZ_CLOCK
RTC 32 kHz clock
0x3
AHBCLKCTRL0
AHB Clock control n
0xC0
32
read-write
0x10B
0xFFFFFFFF
ROM
Enables the clock for the Boot ROM. 0 = Disable; 1 = Enable.
1
1
read-write
SRAM1
Enables the clock for SRAM1. 0 = Disable; 1 = Enable.
3
1
read-write
SRAM2
Enables the clock for SRAM2. 0 = Disable; 1 = Enable.
4
1
read-write
FLASH
Enables the clock for the flash controller. 0 = Disable; 1 = Enable.
7
1
read-write
FMC
Enables the clock for the Flash accelerator. 0 = Disable; 1 = Enable.
8
1
read-write
INPUTMUX
Enables the clock for the input muxes. 0 = Disable; 1 = Enable.
11
1
read-write
IOCON
Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.
13
1
read-write
GPIO0
Enables the clock for the GPIO0 port registers. 0 = Disable; 1 = Enable.
14
1
read-write
GPIO1
Enables the clock for the GPIO1 port registers. 0 = Disable; 1 = Enable.
15
1
read-write
PINT
Enables the clock for the pin interrupt block.0 = Disable; 1 = Enable.
18
1
read-write
GINT
Enables the clock for the grouped pin interrupt block. 0 = Disable; 1 = Enable.
19
1
read-write
DMA
Enables the clock for the DMA controller. 0 = Disable; 1 = Enable.
20
1
read-write
CRC
Enables the clock for the CRC engine. 0 = Disable; 1 = Enable.
21
1
read-write
WWDT
Enables the clock for the Watchdog Timer. 0 = Disable; 1 = Enable.
22
1
read-write
RTC
Enables the clock for the RTC. 0 = Disable; 1 = Enable.
23
1
read-write
MAILBOX
Enables the clock for the Mailbox. 0 = Disable; 1 = Enable.
26
1
read-write
ADC0
Enables the clock for the ADC0 register interface. 0 = Disable; 1 = Enable.
27
1
read-write
AHBCLKCTRL1
AHB Clock control n
0xC4
32
read-write
0
0xFFFFFFFF
MRT
Enables the clock for the Multi-Rate Timer. 0 = Disable; 1 = Enable.
0
1
read-write
RIT
Enables the clock for the repetitive interrupt timer. 0 = Disable; 1 = Enable.
1
1
read-write
SCT0
Enables the clock for SCT0. 0 = Disable; 1 = Enable.
2
1
read-write
FIFO
Enables the clock for system FIFOs. 0 = Disable; 1 = Enable.
9
1
read-write
UTICK
Enables the clock for the Micro-tick Timer. 0 = Disable; 1 = Enable.
10
1
read-write
CT32B2
Enables the clock for CT32B 2. 0 = Disable; 1 = Enable.
22
1
read-write
CT32B3
Enables the clock for CT32B 3. 0 = Disable; 1 = Enable.
26
1
read-write
CT32B4
Enables the clock for CT32B 4. 0 = Disable; 1 = Enable.
27
1
read-write
2
0x4
AHBCLKCTRLSET[%s]
Set bits in AHBCLKCTRL n
0xC8
32
read-write
0
0
CLK_SET
Writing ones to this register sets the corresponding bit or bits in the AHBCLKCTRL0 register, if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRL0 are reserved and only zeroes should be written to them.
0
32
read-write
2
0x4
AHBCLKCTRLCLR[%s]
Clear bits in AHBCLKCTRL n
0xD0
32
read-write
0
0
CLK_CLR
Writing ones to this register clears the corresponding bit or bits in the AHBCLKCTRL0 register, if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRL0 are reserved and only zeroes should be written to them.
0
32
read-write
SYSTICKCLKDIV
SYSTICK clock divider
0xE0
32
read-write
0
0xFFFFFFFF
DIV
SYSTICK clock divider value. 0: Disable SYSTICK timer clock. 1: Divide by 1. to 255: Divide by 255.
0
8
read-write
TRACECLKDIV
TRACE clock divider
0xE4
32
read-write
0
0xFFFFFFFF
DIV
TRACE clock divider value. 0: Disable TRACE clock. 1: Divide by 1. to 255: Divide by 255.
0
8
read-write
AHBCLKDIV
System clock divider
0x100
32
read-write
0x1
0xFFFFFFFF
DIV
System AHB clock divider value. 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255.
0
8
read-write
ADCCLKDIV
ADC clock divider
0x108
32
read-write
0
0xFFFFFFFF
DIV
ADC clock divider value. 0: Disable ADC clock. 1: Divide by 1. to 255: Divide by 255.
0
8
read-write
CLKOUTDIV
CLKOUT clock divider
0x10C
32
read-write
0
0xFFFFFFFF
DIV
CLKOUT clock divider value. 0: Disable CLKOUT clock divider. 1: Divide by 1. to 255: Divide by 255.
0
8
read-write
FREQMECTRL
Frequency measure register
0x120
32
read-write
0
0xFFFFFFFF
CAPVAL
Stores the capture result which is used to calculate the frequency of the target clock. This field is read-only.
0
14
read-write
PROG
Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit when the measurement cycle has completed and there is valid capture data in the CAPVAL field (bits 13:0).
31
1
read-write
FLASHCFG
Flash wait states configuration
0x124
32
read-write
0x5000
0xFFFFFFFF
FETCHCFG
Instruction fetch configuration. This field determines how flash accelerator buffers are used for instruction fetches.
0
2
read-write
DATACFG
Data read configuration. This field determines how flash accelerator buffers are used for data accesses.
2
2
read-write
ACCEL
Acceleration enable.
4
1
read-write
PREFEN
Prefetch enable.
5
1
read-write
PREFOVR
Prefetch override.
6
1
read-write
FLASHTIM
Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access.
12
4
read-write
FLASHTIM_1_CLOCK_CYCLE
1 clock cycle. 1 system clock flash access time (for system clock frequencies of up to MHz).
0
FLASHTIM_2_CLOCK_CYCLES
2 clock cycles. 2 system clocks flash access time (for system clock frequencies of up to MHz).
0x1
FLASHTIM_3_CLOCK_CYCLES
3 clock cycles. 3 system clocks flash access time (for system clock frequencies of up to MHz).
0x2
FLASHTIM_4_CLOCK_CYCLES
4 clock cycles. 4 system clocks flash access time.
0x3
FLASHTIM_5_CLOCK_CYCLES
5 clock cycles. 5 system clocks flash access time.
0x4
FLASHTIM_6_CLOCK_CYCLES
6 clock cycles. 6 system clocks flash access time.
0x5
FLASHTIM_7_CLOCK_CYCLES
7 clock cycles. 7 system clocks flash access time.
0x6
FLASHTIM_8_CLOCK_CYCLES
8 clock cycles. 8 system clocks flash access time.
0x7
FIFOCTRL
Serial interface FIFO enables
0x148
32
read-write
0
0xFFFFFFFF
U0TXFIFOEN
USART0 transmitter FIFO enable
0
1
read-write
U1TXFIFOEN
USART1 transmitter FIFO enable
1
1
read-write
U2TXFIFOEN
USART2 transmitter FIFO enable
2
1
read-write
U3TXFIFOEN
USART3 transmitter FIFO enable
3
1
read-write
SPI0TXFIFOEN
SPI0 transmitter FIFO enable
4
1
read-write
SPI1TXFIFOEN
SPI1 transmitter FIFO enable
5
1
read-write
U0RXFIFOEN
USART0 receiver FIFO enable
8
1
read-write
U1RXFIFOEN
USART1 receiver FIFO enable
9
1
read-write
U2RXFIFOEN
USART2 receiver FIFO enable
10
1
read-write
U3RXFIFOEN
USART3 receiver FIFO enable
11
1
read-write
SPI0RXFIFOEN
SPI0 receiver FIFO enable
12
1
read-write
SPI1RXFIFOEN
SPI1 receiver FIFO enable
13
1
read-write
IRCCTRL
IRC oscillator control
0x184
32
read-write
0x80
0xFFFFFFFF
TRIM
Trim value
0
8
read-write
RTCOSCCTRL
RTC oscillator 32 kHz output control
0x190
32
read-write
0x1
0xFFFFFFFF
EN
RTC 32 kHz clock enable.
0
1
read-write
DISABLED
Disabled. RTC clock off.
0
ENABLED
Enabled. RTC clock on.
0x1
SYSPLLCTRL
PLL control
0x1B0
32
read-write
0x8000
0xFFFFFFFF
SELR
Bandwidth select R value
0
4
read-write
SELI
Bandwidth select I value
4
6
read-write
SELP
Bandwidth select P value
10
5
read-write
BYPASS
PLL bypass control
15
1
read-write
DISABLED
Disabled. PLL CCO is used to create the PLL output.
0
ENABLED
Enabled. PLL is bypassed, the PLL input clock is routed directly to the PLL output (default).
0x1
BYPASSCCODIV2
Bypass feedback clock divide by 2.
16
1
read-write
DIVIDE_BY_2
Divide by 2. The CCO feedback clock is divided by 2 in addition to the programmed M divide.
0
BYPASS
Bypass. The CCO feedback clock is divided only by the programmed M divide.
0x1
UPLIMOFF
Enable spread spectrum/fractional mode
17
1
read-write
NORMAL_MODE
Normal mode.
0
SSGC_MODE
SSGC mode. Spread spectrum/fractional mode.
0x1
BANDSEL
PLL filter control. Set this bit to one when the SSGC is disabled or at low frequencies.
18
1
read-write
SSCG_CONTROL
SSCG control. The PLL filter uses the parameters derived from the SSCG decoder.
0
MDEC_CONTROL
MDEC control. The PLL filter uses the programmable fields SELP, SELR, and SELI in this register to control the filter constants.
0x1
DIRECTI
PLL0 direct input enable
19
1
read-write
DISABLED
Disabled. The PLL input divider (N divider) output is used to drive the PLL CCO.
0
ENABLED
Enabled. The PLL input divider (N divider) is bypassed. the PLL input clock is used directly to drive the PLL CCO.
0x1
DIRECTO
PLL0 direct output enable
20
1
read-write
DISABLED
Disabled. The PLL output divider (P divider) is used to create the PLL output.
0
ENABLED
Enabled. The PLL output divider (P divider) is bypassed, the PLL CCO output is used as the PLL output.
0x1
SYSPLLSTAT
PLL status
0x1B4
32
read-write
0
0xFFFFFFFF
LOCK
PLL0 lock indicator
0
1
read-write
SYSPLLNDEC
PLL N decoder
0x1B8
32
read-write
0
0xFFFFFFFF
NDEC
Decoded N-divider coefficient value
0
10
read-write
NREQ
NDEC reload request. When a 1 is written to this bit, the NDEC value is loaded into the PLL. Must be cleared by software for any subsequent load, or the PLL can be powered down and back up via the PDEN_SYS_PLL bit in the PDRUNCFG register if the NDEC value is changed.
10
1
read-write
SYSPLLPDEC
PLL P decoder
0x1BC
32
read-write
0
0xFFFFFFFF
PDEC
Decoded P-divider coefficient value
0
7
read-write
PREQ
PDEC reload request. When a 1 is written to this bit, the PDEC value is loaded into the PLL. Must be cleared by software for any subsequent load, or the PLL can be powered down and back up via the PDEN_SYS_PLL bit in the PDRUNCFG register if the PDEC value is changed.
7
1
read-write
SYSPLLSSCTRL0
PLL spread spectrum control 0
0x1C0
32
read-write
0
0xFFFFFFFF
MDEC
Decoded M-divider coefficient value
0
17
read-write
MREQ
MDEC reload request. When a 1 is written to this bit, the MDEC value is loaded into the PLL. Must be cleared by software for any subsequent load, or the PLL can be powered down and back up via the PDEN_SYS_PLL bit in the PDRUNCFG register if the MDEC value is changed.
17
1
read-write
SEL_EXT
Select spread spectrum mode.
18
1
read-write
SPREAD_SPECTRUM_MODE
Spread spectrum mode. Spread spectrum mode enabled.
0
MDEC_ENABLED
MDEC enabled. Spread spectrum clock generator not used.
0x1
SYSPLLSSCTRL1
PLL spread spectrum control 1
0x1C4
32
read-write
0x10000000
0xFFFFFFFF
MD
M- divider value with fraction. MD[18:11] : integer portion of the feedback divider value. MD[10:0] : fractional portion of the feedback divider value.
0
19
read-write
MDREQ
MD reload request. When a 1 is written to this bit, the MD value is loaded into the PLL. This bit is cleared when the load is complete.
19
1
read-write
MF
Programmable modulation frequency fm = Fref/Nss with Fref = Fin/N 0b000 => Nss = 512 (fm = 3.9 - 7.8 kHz) 0b001 => Nss = 384 (fm = 5.2 - 10.4 kHz) 0b010 => Nss = 256 (fm = 7.8 - 15.6 kHz) 0b011 => Nss = 128 (fm = 15.6 - 31.3 kHz) 0b100 => Nss = 64 (fm = 32.3 - 64.5 kHz) 0b101 => Nss = 32 (fm = 62.5- 125 kHz) 0b110 => Nss = 24 (fm = 83.3- 166.6 kHz) 0b111 => Nss = 16 (fm = 125- 250 kHz)
20
3
read-write
MR
Programmable frequency modulation depth deltafmodpk-pk = Fref x k/Fcco = k/MDdec 0 = no spread 0b000 => k = 0 (no spread spectrum) 0b001 => k = 1 0b010 => k = 1.5 0b011 => k = 2 0b100 => k = 3 0b101 => k = 4 0b110 => k = 6 0b111 => k = 8
23
3
read-write
MC
Modulation waveform control 0 = no compensation Compensation for low pass filtering of the PLL to get a triangular modulation at the output of the PLL, giving a flat frequency spectrum. 0b00 => no compensation 0b10 => recommended setting 0b11 => max. compensation
26
2
read-write
PD
Power down.
28
1
read-write
ENABLED
Enabled. Spread spectrum controller is enabled
0
DISABLED
Disabled. Spread spectrum controller is disabled
0x1
DITHER
Select modulation frequency.
29
1
read-write
FIXED
Fixed. Fixed modulation frequency.
0
DITHER
Dither. Randomly dither between two modulation frequencies.
0x1
PDRUNCFG
Power configuration register
0x210
32
read-write
0xD80500
0xFFFFFFFF
PDEN_IRC_OSC
IRC oscillator output. 0 = Powered; 1 = Powered down.
3
1
read-write
PDEN_IRC
IRC oscillator. 0 = Powered; 1 = Powered down.
4
1
read-write
PDEN_FLASH
Flash memory. 0 = Powered; 1 = Powered down.
5
1
read-write
PDEN_BOD_RST
Brown-out Detect reset. 0 = Powered; 1 = Powered down.
7
1
read-write
PDEN_BOD_INTR
Brown-out Detect interrupt. 0 = Powered; 1 = Powered down.
8
1
read-write
PDEN_ADC0
ADC0. 0 = Powered; 1 = Powered down.
10
1
read-write
PDEN_SRAM0A
First 8 kB of SRAM0). 0 = Powered; 1 = Powered down.
13
1
read-write
PDEN_SRAM0B
Remaining portion of SRAM0). 0 = Powered; 1 = Powered down.
14
1
read-write
PDEN_SRAM1
SRAM1. 0 = Powered; 1 = Powered down.
15
1
read-write
PDEN_SRAM2
SRAM2 (undedicated 8 kB RAM). 0 = Powered; 1 = Powered down.
16
1
read-write
PDEN_ROM
ROM. 0 = Powered; 1 = Powered down.
17
1
read-write
PDEN_VDDA
Vdda to the ADC, must be enabled for the ADC to work. Also see bit 23. 0 = Powered; 1 = Powered down.
19
1
read-write
PDEN_WDT_OSC
Watchdog oscillator. 0 = Powered; 1 = Powered down.
20
1
read-write
PDEN_SYS_PLL
PLL0. 0 = Powered; 1 = Powered down.
22
1
read-write
PDEN_VREFP
Vrefp to the ADC, must be enabled for the ADC to work. Also see bit 19. 0 = Powered; 1 = Powered down.
23
1
read-write
PDEN_32K_OSC
32 kHz RTC oscillator. 0 = Powered; 1 = Powered down.
24
1
read-write
PDRUNCFGSET
Set bits in PDRUNCFG
0x214
32
read-write
0
0
PD_SET
Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG register, if they are implemented. Bits that do not correspond to defined bits in PDRUNCFG are reserved and only zeroes should be written to them.
0
32
read-write
PDRUNCFGCLR
Clear bits in PDRUNCFG
0x218
32
read-write
0
0
PD_CLR
Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG register, if they are implemented. Bits that do not correspond to defined bits in PDRUNCFG are reserved and only zeroes should be written to them.
0
32
read-write
STARTER0
Start logic n wake-up enable register
0x240
32
read-write
0
0xFFFFFFFF
WWDT
WWDT interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
0
1
read-write
BOD
BOD interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
1
1
read-write
DMA
DMA wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Typically used in sleep mode only.
3
1
read-write
GINT0
Group interrupt 0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
4
1
read-write
PINT0
GPIO pin interrupt 0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match.
5
1
read-write
PINT1
GPIO pin interrupt 1 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match.
6
1
read-write
PINT2
GPIO pin interrupt 2 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match.
7
1
read-write
PINT3
GPIO pin interrupt 3 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match.
8
1
read-write
UTICK
Micro-tick Timer wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
9
1
read-write
MRT
Multi-Rate Timer wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Typically used in sleep mode only.
10
1
read-write
CT32B0
CT32B 0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only.
11
1
read-write
CT32B1
CT32B 1 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only.
12
1
read-write
CT32B2
CT32B 2 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only.
13
1
read-write
CT32B3
CT32B 3 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only.
14
1
read-write
CT32B4
CT32B 4 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only.
15
1
read-write
SCT0
SCT0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only.
16
1
read-write
USART0
USART0 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt.
17
1
read-write
USART1
USART1 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt.
18
1
read-write
USART2
USART2 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt.
19
1
read-write
USART3
USART2 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt.
20
1
read-write
I2C0
I2C0 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt.
21
1
read-write
I2C1
I2C1 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt.
22
1
read-write
I2C2
I2C2 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt.
23
1
read-write
SPI0
SPI0 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt.
24
1
read-write
SPI1
SPI1 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt.
25
1
read-write
ADC0_SEQA
ADC0 sequence A interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only.
26
1
read-write
ADC0_SEQB
ADC0 sequence B interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only.
27
1
read-write
ADC0_THCMP
ADC0 threshold and error interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only.
28
1
read-write
RTC
RTC interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
29
1
read-write
MAILBOX
Mailbox interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only.
31
1
read-write
STARTER1
Start logic n wake-up enable register
0x244
32
read-write
0
0xFFFFFFFF
GINT1
Group interrupt 0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
0
1
read-write
PINT4
GPIO pin interrupt 4 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match.
1
1
read-write
PINT5
GPIO pin interrupt 5 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match.
2
1
read-write
PINT6
GPIO pin interrupt 6 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match.
3
1
read-write
PINT7
GPIO pin interrupt 7 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match.
4
1
read-write
RIT
Repetitive Interrupt Timer interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Typically used in sleep mode only.
8
1
read-write
2
0x4
STARTERSET[%s]
Set bits in STARTERP n
0x248
32
read-write
0
0
START_SET
Writing ones to this register sets the corresponding bit or bits in the STARTERP n register, if they are implemented. Bits that do not correspond to defined bits in STARTERP0 are reserved and only zeroes should be written to them.
0
32
read-write
2
0x4
STARTERCLR[%s]
Clear bits in STARTER n
0x250
32
read-write
0
0
START_CLR
Writing ones to this register clears the corresponding bit or bits in the STARTERP n register, if they are implemented. Bits that do not correspond to defined bits in STARTERP0 are reserved and only zeroes should be written to them.
0
32
read-write
CPUCTRL
CPU Control for multiple processors
0x300
32
read-write
0x4D
0xFFFFFFFF
MASTERCPU
Determines which CPU is considered the master. The master CPU cannot have its clock turned off via the related CMnCLKEN bit or be reset via the related CMxRSTEN in this register. The slave CPU wakes up briefly following device reset, then goes back to sleep until activated by the master CPU.
0
1
read-write
M0P
M0+. Cortex-M0+ is the master CPU.
0
M4
M4. Cortex-M4 is the master CPU.
0x1
CM4CLKEN
Cortex-M4 clock enable.
2
1
read-write
DISABLED
Disabled. The Cortex-M4 clock is not enabled.
0
ENABLED
Enabled. The Cortex-M4 clock is enabled.
0x1
CM0CLKEN
Cortex-M0+ clock enable.
3
1
read-write
DISABLED
Disabled. The Cortex-M0+ clock is not enabled.
0
ENABLED
Enabled. The Cortex-M0+ clock is enabled.
0x1
CM4RSTEN
Cortex-M4 reset.
4
1
read-write
DISABLED
Disabled. The Cortex-M4 is not being reset.
0
ENABLED
Enabled. The Cortex-M4 is being reset.
0x1
CM0RSTEN
Cortex-M0+ reset.
5
1
read-write
DISABLED
Disabled. The Cortex-M0+ is not being reset.
0
ENABLED
Enabled. The Cortex-M0+ is being reset.
0x1
POWERCPU
Identifies the owner of reduced power mode control: which CPU can cause the device to enter Sleep, Deep Sleep, Power-down, and Deep Power-down modes.
6
1
read-write
M0P
M0+. Cortex-M0+ is the owner of reduced power mode control.
0
M4
M4. Cortex-M4 is the owner of reduced power mode control.
0x1
CPBOOT
Coprocessor Boot Address
0x304
32
read-write
0
0xFFFFFFFF
BOOTADDR
Slave processor boot address.
0
32
read-write
CPSTACK
Coprocessor Stack Address
0x308
32
read-write
0
0xFFFFFFFF
STACKADDR
Slave processor stack address.
0
32
read-write
CPSTAT
Coprocessor Status
0x30C
32
read-write
0
0xFFFFFFFF
CM4SLEEPING
When 1, the Cortex-M4 CPU is sleeping.
0
1
read-write
CM0SLEEPING
When 1, the Cortex-M0+ CPU is sleeping.
1
1
read-write
CM4LOCKUP
When 1, the Cortex-M4 CPU is in lockup.
2
1
read-write
CM0LOCKUP
When 1, the Cortex-M0+ CPU is in lockup.
3
1
read-write
JTAGIDCODE
JTAG ID code register
0x3F4
32
read-write
0
0
JTAGID
JTAG ID code.
0
32
read-write
DEVICE_ID0
Part ID register
0x3F8
32
read-write
0
0
PARTID
Part ID
0
32
read-write
DEVICE_ID1
Part ID register
0x3FC
32
read-write
0
0
REVID
Revision.
0
32
read-write
BODCTRL
Brown-Out Detect control
0x2C044
32
read-write
0
0xFFFFFFFF
BODRSTLEV
BOD reset level
0
2
read-write
LEVEL_0_1
Level 0: 1.5 V
0
LEVEL_1_1
Level 1: 1.85 V
0x1
LEVEL_2_2
Level 2: 2.0 V
0x2
LEVEL_3_2
Level 3: 2.3 V
0x3
BODRSTENA
BOD reset enable
2
1
read-write
DISABLE_RESET_FUNCTI
Disable reset function.
0
ENABLE_RESET_FUNCTIO
Enable reset function.
0x1
BODINTLEV
BOD interrupt level
3
2
read-write
LEVEL_0_2
Level 0: 2.05 V
0
LEVEL_1_2
Level 1: 2.45 V
0x1
LEVEL_2_2
Level 2: 2.75 V
0x2
LEVEL_3_3
Level 3: 3.05 V
0x3
BODINTENA
BOD interrupt enable
5
1
read-write
DISABLE_RESET_FUNCTI
Disable interrupt function.
0
ENABLE_RESET_FUNCTIO
Enable reset function.
0x1
BODRSTSTAT
BOD reset status
6
1
read-write
BODINTSTAT
BOD interrupt status
7
1
read-write
GINT0
LPC5410x Group GPIO input interrupt (GINT0/1)
GINT
GINT
0x40010000
0
0x48
registers
GINT0
4
CTRL
GPIO grouped interrupt control register
0
32
read-write
0
0x7
INT
Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.
0
1
read-write
NO_REQUEST
No request. No interrupt request is pending.
0
REQUEST_ACTIVE
Request active. Interrupt request is active.
0x1
COMB
Combine enabled inputs for group interrupt
1
1
read-write
OR
Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity).
0
AND
And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity).
0x1
TRIG
Group interrupt trigger
2
1
read-write
EDGE_TRIGGERED
Edge-triggered.
0
LEVEL_TRIGGERED
Level-triggered.
0x1
2
0x4
PORT_POL[%s]
GPIO grouped interrupt port 0 polarity register
0x20
32
read-write
0xFFFFFFFF
0xFFFFFFFF
POL
Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.
0
32
read-write
2
0x4
PORT_ENA[%s]
GPIO grouped interrupt port 0 enable register
0x40
32
read-write
0
0xFFFFFFFF
ENA
Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.
0
32
read-write
GINT1
LPC5410x Group GPIO input interrupt (GINT0/1)
GINT
0x40014000
0
0x48
registers
PINT
LPC5410x Pin interrupt and pattern match (PINT)
PINT
0x40018000
0
0x34
registers
PIN_INT0
5
PIN_INT1
6
PIN_INT2
7
PIN_INT3
8
ISEL
Pin Interrupt Mode register
0
32
read-write
0
0xFF
PMODE
Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive
0
8
read-write
IENR
Pin interrupt level or rising edge interrupt enable register
0x4
32
read-write
0
0xFF
ENRL
Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.
0
8
read-write
SIENR
Pin interrupt level or rising edge interrupt set register
0x8
32
write-only
0
0
SETENRL
Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt.
0
8
write-only
CIENR
Pin interrupt level (rising edge interrupt) clear register
0xC
32
write-only
0
0
CENRL
Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.
0
8
write-only
IENF
Pin interrupt active level or falling edge interrupt enable register
0x10
32
read-write
0
0xFF
ENAF
Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.
0
8
read-write
SIENF
Pin interrupt active level or falling edge interrupt set register
0x14
32
write-only
0
0
SETENAF
Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.
0
8
write-only
CIENF
Pin interrupt active level or falling edge interrupt clear register
0x18
32
write-only
0
0
CENAF
Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.
0
8
write-only
RISE
Pin interrupt rising edge register
0x1C
32
read-write
0
0xFF
RDET
Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.
0
8
read-write
FALL
Pin interrupt falling edge register
0x20
32
read-write
0
0xFF
FDET
Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.
0
8
read-write
IST
Pin interrupt status register
0x24
32
read-write
0
0xFF
PSTAT
Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register).
0
8
read-write
PMCTRL
Pattern match interrupt control register
0x28
32
read-write
0
0xFF000003
SEL_PMATCH
Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function.
0
1
read-write
PIN_INTERRUPT
Pin interrupt. Interrupts are driven in response to the standard pin interrupt function.
0
PATTERN_MATCH
Pattern match. Interrupts are driven in response to pattern matches.
0x1
ENA_RXEV
Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true.
1
1
read-write
DISABLED
Disabled. RXEV output to the CPU is disabled.
0
ENABLED
Enabled. RXEV output to the CPU is enabled.
0x1
PMAT
This field displays the current state of pattern matches. A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs.
24
8
read-write
PMSRC
Pattern match interrupt bit-slice source register
0x2C
32
read-write
0
0xFFFFFF00
SRC0
Selects the input source for bit slice 0
8
3
read-write
INPUT0
Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0.
0
INPUT1
Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0.
0x1
INPUT2
Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0.
0x2
INPUT3
Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0.
0x3
INPUT4
Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0.
0x4
INPUT5
Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0.
0x5
INPUT6
Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0.
0x6
INPUT7
Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0.
0x7
SRC1
Selects the input source for bit slice 1
11
3
read-write
INPUT0
Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1.
0
INPUT1
Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1.
0x1
INPUT2
Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1.
0x2
INPUT3
Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1.
0x3
INPUT4
Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1.
0x4
INPUT5
Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1.
0x5
INPUT6
Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1.
0x6
INPUT7
Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1.
0x7
SRC2
Selects the input source for bit slice 2
14
3
read-write
INPUT0
Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2.
0
INPUT1
Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2.
0x1
INPUT2
Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2.
0x2
INPUT3
Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2.
0x3
INPUT4
Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2.
0x4
INPUT5
Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2.
0x5
INPUT6
Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2.
0x6
INPUT7
Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2.
0x7
SRC3
Selects the input source for bit slice 3
17
3
read-write
INPUT0
Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3.
0
INPUT1
Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3.
0x1
INPUT2
Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3.
0x2
INPUT3
Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3.
0x3
INPUT4
Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3.
0x4
INPUT5
Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3.
0x5
INPUT6
Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3.
0x6
INPUT7
Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3.
0x7
SRC4
Selects the input source for bit slice 4
20
3
read-write
INPUT0
Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4.
0
INPUT1
Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4.
0x1
INPUT2
Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4.
0x2
INPUT3
Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4.
0x3
INPUT4
Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4.
0x4
INPUT5
Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4.
0x5
INPUT6
Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4.
0x6
INPUT7
Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4.
0x7
SRC5
Selects the input source for bit slice 5
23
3
read-write
INPUT0
Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5.
0
INPUT1
Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5.
0x1
INPUT2
Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5.
0x2
INPUT3
Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5.
0x3
INPUT4
Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5.
0x4
INPUT5
Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5.
0x5
INPUT6
Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5.
0x6
INPUT7
Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5.
0x7
SRC6
Selects the input source for bit slice 6
26
3
read-write
INPUT0
Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6.
0
INPUT1
Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6.
0x1
INPUT2
Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6.
0x2
INPUT3
Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6.
0x3
INPUT4
Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6.
0x4
INPUT5
Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6.
0x5
INPUT6
Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6.
0x6
INPUT7
Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6.
0x7
SRC7
Selects the input source for bit slice 7
29
3
read-write
INPUT0
Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7.
0
INPUT1
Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7.
0x1
INPUT2
Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7.
0x2
INPUT3
Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7.
0x3
INPUT4
Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7.
0x4
INPUT5
Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7.
0x5
INPUT6
Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7.
0x6
INPUT7
Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7.
0x7
PMCFG
Pattern match interrupt bit slice configuration register
0x30
32
read-write
0
0xFFFFFF7F
PROD_ENDPTS0
Determines whether slice 0 is an endpoint.
0
1
read-write
NO_EFFECT
No effect. Slice 0 is not an endpoint.
0
ENDPOINT
endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true.
0x1
PROD_ENDPTS1
Determines whether slice 1 is an endpoint.
1
1
read-write
NO_EFFECT
No effect. Slice 1 is not an endpoint.
0
ENDPOINT
endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true.
0x1
PROD_ENDPTS2
Determines whether slice 2 is an endpoint.
2
1
read-write
NO_EFFECT
No effect. Slice 2 is not an endpoint.
0
ENDPOINT
endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true.
0x1
PROD_ENDPTS3
Determines whether slice 3 is an endpoint.
3
1
read-write
NO_EFFECT
No effect. Slice 3 is not an endpoint.
0
ENDPOINT
endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true.
0x1
PROD_ENDPTS4
Determines whether slice 4 is an endpoint.
4
1
read-write
NO_EFFECT
No effect. Slice 4 is not an endpoint.
0
ENDPOINT
endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true.
0x1
PROD_ENDPTS5
Determines whether slice 5 is an endpoint.
5
1
read-write
NO_EFFECT
No effect. Slice 5 is not an endpoint.
0
ENDPOINT
endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true.
0x1
PROD_ENDPTS6
Determines whether slice 6 is an endpoint.
6
1
read-write
NO_EFFECT
No effect. Slice 6 is not an endpoint.
0
ENDPOINT
endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true.
0x1
CFG0
Specifies the match contribution condition for bit slice 0.
8
3
read-write
CONSTANT_HIGH
Constant HIGH. This bit slice always contributes to a product term match.
0
STICKY_RISING_EDGE
Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x1
STICKY_FALLING_EDGE
Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2
STICKY_RISING_FALLING_EDGE
Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3
HIGH_LEVEL
High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x4
LOW_LEVEL
Low level. Match occurs when there is a low level on the specified input.
0x5
CONSTANT_ZERO
Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x6
EVENT
Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.
0x7
CFG1
Specifies the match contribution condition for bit slice 1.
11
3
read-write
CONSTANT_HIGH
Constant HIGH. This bit slice always contributes to a product term match.
0
STICKY_RISING_EDGE
Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x1
STICKY_FALLING_EDGE
Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2
STICKY_RISING_FALLING_EDGE
Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3
HIGH_LEVEL
High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x4
LOW_LEVEL
Low level. Match occurs when there is a low level on the specified input.
0x5
CONSTANT_ZERO
Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x6
EVENT
Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.
0x7
CFG2
Specifies the match contribution condition for bit slice 2.
14
3
read-write
CONSTANT_HIGH
Constant HIGH. This bit slice always contributes to a product term match.
0
STICKY_RISING_EDGE
Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x1
STICKY_FALLING_EDGE
Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2
STICKY_RISING_FALLING_EDGE
Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3
HIGH_LEVEL
High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x4
LOW_LEVEL
Low level. Match occurs when there is a low level on the specified input.
0x5
CONSTANT_ZERO
Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x6
EVENT
Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.
0x7
CFG3
Specifies the match contribution condition for bit slice 3.
17
3
read-write
CONSTANT_HIGH
Constant HIGH. This bit slice always contributes to a product term match.
0
STICKY_RISING_EDGE
Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x1
STICKY_FALLING_EDGE
Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2
STICKY_RISING_FALLING_EDGE
Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3
HIGH_LEVEL
High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x4
LOW_LEVEL
Low level. Match occurs when there is a low level on the specified input.
0x5
CONSTANT_ZERO
Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x6
EVENT
Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.
0x7
CFG4
Specifies the match contribution condition for bit slice 4.
20
3
read-write
CONSTANT_HIGH
Constant HIGH. This bit slice always contributes to a product term match.
0
STICKY_RISING_EDGE
Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x1
STICKY_FALLING_EDGE
Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2
STICKY_RISING_FALLING_EDGE
Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3
HIGH_LEVEL
High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x4
LOW_LEVEL
Low level. Match occurs when there is a low level on the specified input.
0x5
CONSTANT_ZERO
Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x6
EVENT
Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.
0x7
CFG5
Specifies the match contribution condition for bit slice 5.
23
3
read-write
CONSTANT_HIGH
Constant HIGH. This bit slice always contributes to a product term match.
0
STICKY_RISING_EDGE
Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x1
STICKY_FALLING_EDGE
Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2
STICKY_RISING_FALLING_EDGE
Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3
HIGH_LEVEL
High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x4
LOW_LEVEL
Low level. Match occurs when there is a low level on the specified input.
0x5
CONSTANT_ZERO
Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x6
EVENT
Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.
0x7
CFG6
Specifies the match contribution condition for bit slice 6.
26
3
read-write
CONSTANT_HIGH
Constant HIGH. This bit slice always contributes to a product term match.
0
STICKY_RISING_EDGE
Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x1
STICKY_FALLING_EDGE
Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2
STICKY_RISING_FALLING_EDGE
Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3
HIGH_LEVEL
High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x4
LOW_LEVEL
Low level. Match occurs when there is a low level on the specified input.
0x5
CONSTANT_ZERO
Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x6
EVENT
Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.
0x7
CFG7
Specifies the match contribution condition for bit slice 7.
29
3
read-write
CONSTANT_HIGH
Constant HIGH. This bit slice always contributes to a product term match.
0
STICKY_RISING_EDGE
Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x1
STICKY_FALLING_EDGE
Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2
STICKY_RISING_FALLING_EDGE
Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3
HIGH_LEVEL
High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x4
LOW_LEVEL
Low level. Match occurs when there is a low level on the specified input.
0x5
CONSTANT_ZERO
Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x6
EVENT
Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.
0x7
IOCON
LPC5410x I/O pin configuration (IOCON)
IOCON
0x4001C000
0
0x100
registers
PIO00
Digital I/O control for port 0 pins PIO0_0
0
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO01
Digital I/O control for port 0 pins PIO0_1
0x4
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO02
Digital I/O control for port 0 pins PIO0_2
0x8
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO03
Digital I/O control for port 0 pins PIO0_3
0xC
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO04
Digital I/O control for port 0 pins PIO0_4
0x10
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO05
Digital I/O control for port 0 pins PIO0_5
0x14
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO06
Digital I/O control for port 0 pins PIO0_6
0x18
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO07
Digital I/O control for port 0 pins PIO0_7
0x1C
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO08
Digital I/O control for port 0 pins PIO0_8
0x20
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO09
Digital I/O control for port 0 pins PIO0_9
0x24
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO010
Digital I/O control for port 0 pins PIO0_10
0x28
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO011
Digital I/O control for port 0 pins PIO0_11
0x2C
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO012
Digital I/O control for port 0 pins PIO0_12
0x30
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO013
Digital I/O control for port 0 pins PIO0_13
0x34
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO014
Digital I/O control for port 0 pins PIO0_14
0x38
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO015
Digital I/O control for port 0 pins PIO0_15
0x3C
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO016
Digital I/O control for port 0 pins PIO0_16
0x40
32
read-write
0x195
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO017
Digital I/O control for port 0 pins PIO0_17
0x44
32
read-write
0x195
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO018
Digital I/O control for port 0 pins PIO0_18
0x48
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO019
Digital I/O control for port 0 pins PIO0_19
0x4C
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO020
Digital I/O control for port 0 pins PIO0_20
0x50
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO021
Digital I/O control for port 0 pins PIO0_21
0x54
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO022
Digital I/O control for port 0 pins PIO0_22
0x58
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO023
Digital I/O control for port 0 pins PIO0_23
0x5C
32
read-write
0x1A0
0x7E7
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
I2CSLEW
Controls slew rate of I2C pad.
5
1
read-write
I2C_MODE
I2C mode.
0
GPIO_MODE
GPIO mode.
0x1
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
I2CDRIVE
Controls the current sink capability of the pin.
9
1
read-write
LOW
Low drive. Output drive sink is 4 mA. This is sufficient for standard and fast mode I2C.
0
HIGH
High drive. Output drive sink is 20 mA. This is needed for Fast Mode Plus I 2C. Refer to the appropriate specific device data sheet for details.
0x1
I2CFILTER
Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation.
10
1
read-write
ENABLED
Enabled. I2C 50 ns glitch filter enabled.
0
DISABLED
Disabled. I2C 50 ns glitch filter disabled.
0x1
PIO024
Digital I/O control for port 0 pins PIO0_24
0x60
32
read-write
0x1A0
0x7E7
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
I2CSLEW
Controls slew rate of I2C pad.
5
1
read-write
I2C_MODE
I2C mode.
0
GPIO_MODE
GPIO mode.
0x1
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
I2CDRIVE
Controls the current sink capability of the pin.
9
1
read-write
LOW
Low drive. Output drive sink is 4 mA. This is sufficient for standard and fast mode I2C.
0
HIGH
High drive. Output drive sink is 20 mA. This is needed for Fast Mode Plus I 2C. Refer to the appropriate specific device data sheet for details.
0x1
I2CFILTER
Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation.
10
1
read-write
ENABLED
Enabled. I2C 50 ns glitch filter enabled.
0
DISABLED
Disabled. I2C 50 ns glitch filter disabled.
0x1
PIO025
Digital I/O control for port 0 pins PIO0_25
0x64
32
read-write
0x1A0
0x7E7
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
I2CSLEW
Controls slew rate of I2C pad.
5
1
read-write
I2C_MODE
I2C mode.
0
GPIO_MODE
GPIO mode.
0x1
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
I2CDRIVE
Controls the current sink capability of the pin.
9
1
read-write
LOW
Low drive. Output drive sink is 4 mA. This is sufficient for standard and fast mode I2C.
0
HIGH
High drive. Output drive sink is 20 mA. This is needed for Fast Mode Plus I 2C. Refer to the appropriate specific device data sheet for details.
0x1
I2CFILTER
Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation.
10
1
read-write
ENABLED
Enabled. I2C 50 ns glitch filter enabled.
0
DISABLED
Disabled. I2C 50 ns glitch filter disabled.
0x1
PIO026
Digital I/O control for port 0 pins PIO0_26
0x68
32
read-write
0x1A0
0x7E7
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
I2CSLEW
Controls slew rate of I2C pad.
5
1
read-write
I2C_MODE
I2C mode.
0
GPIO_MODE
GPIO mode.
0x1
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
I2CDRIVE
Controls the current sink capability of the pin.
9
1
read-write
LOW
Low drive. Output drive sink is 4 mA. This is sufficient for standard and fast mode I2C.
0
HIGH
High drive. Output drive sink is 20 mA. This is needed for Fast Mode Plus I 2C. Refer to the appropriate specific device data sheet for details.
0x1
I2CFILTER
Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation.
10
1
read-write
ENABLED
Enabled. I2C 50 ns glitch filter enabled.
0
DISABLED
Disabled. I2C 50 ns glitch filter disabled.
0x1
PIO027
Digital I/O control for port 0 pins PIO0_27
0x6C
32
read-write
0x1A0
0x7E7
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
I2CSLEW
Controls slew rate of I2C pad.
5
1
read-write
I2C_MODE
I2C mode.
0
GPIO_MODE
GPIO mode.
0x1
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
I2CDRIVE
Controls the current sink capability of the pin.
9
1
read-write
LOW
Low drive. Output drive sink is 4 mA. This is sufficient for standard and fast mode I2C.
0
HIGH
High drive. Output drive sink is 20 mA. This is needed for Fast Mode Plus I 2C. Refer to the appropriate specific device data sheet for details.
0x1
I2CFILTER
Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation.
10
1
read-write
ENABLED
Enabled. I2C 50 ns glitch filter enabled.
0
DISABLED
Disabled. I2C 50 ns glitch filter disabled.
0x1
PIO028
Digital I/O control for port 0 pins PIO0_28
0x70
32
read-write
0x1A0
0x7E7
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
I2CSLEW
Controls slew rate of I2C pad.
5
1
read-write
I2C_MODE
I2C mode.
0
GPIO_MODE
GPIO mode.
0x1
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
I2CDRIVE
Controls the current sink capability of the pin.
9
1
read-write
LOW
Low drive. Output drive sink is 4 mA. This is sufficient for standard and fast mode I2C.
0
HIGH
High drive. Output drive sink is 20 mA. This is needed for Fast Mode Plus I 2C. Refer to the appropriate specific device data sheet for details.
0x1
I2CFILTER
Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation.
10
1
read-write
ENABLED
Enabled. I2C 50 ns glitch filter enabled.
0
DISABLED
Disabled. I2C 50 ns glitch filter disabled.
0x1
PIO029
Digital I/O control for port 0 pins PIO0_29
0x74
32
read-write
0x190
0x5DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO030
Digital I/O control for port 0 pins PIO0_30
0x78
32
read-write
0x190
0x5DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO031
Digital I/O control for port 0 pins PIO0_31
0x7C
32
read-write
0x190
0x5DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO10
Digital I/O control for port 1 pins PIO1_0
0x80
32
read-write
0x190
0x5DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO11
Digital I/O control for port 1 pins PIO1_1
0x84
32
read-write
0x190
0x5DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO12
Digital I/O control for port 1 pins PIO1_2
0x88
32
read-write
0x190
0x5DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO13
Digital I/O control for port 1 pins PIO1_3
0x8C
32
read-write
0x190
0x5DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO14
Digital I/O control for port 1 pins PIO1_4
0x90
32
read-write
0x190
0x5DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO15
Digital I/O control for port 1 pins PIO1_5
0x94
32
read-write
0x190
0x5DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO16
Digital I/O control for port 1 pins PIO1_6
0x98
32
read-write
0x190
0x5DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO17
Digital I/O control for port 1 pins PIO1_7
0x9C
32
read-write
0x190
0x5DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO18
Digital I/O control for port 1 pins PIO1_8
0xA0
32
read-write
0x190
0x5DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO19
Digital I/O control for port 1 pins PIO1_9
0xA4
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO110
Digital I/O control for port 1 pins PIO1_10
0xA8
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO111
Digital I/O control for port 1 pins PIO1_11
0xAC
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO112
Digital I/O control for port 1 pins PIO1_12
0xB0
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO113
Digital I/O control for port 1 pins PIO1_13
0xB4
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO114
Digital I/O control for port 1 pins PIO1_14
0xB8
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO115
Digital I/O control for port 1 pins PIO1_15
0xBC
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO116
Digital I/O control for port 1 pins PIO1_16
0xC0
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO117
Digital I/O control for port 1 pins PIO1_17
0xC4
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO118
Digital I/O control for port 1 pins PIO1_18
0xC8
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO119
Digital I/O control for port 1 pins PIO1_19
0xCC
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO120
Digital I/O control for port 1 pins PIO1_20
0xD0
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO121
Digital I/O control for port 1 pins PIO1_21
0xD4
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO122
Digital I/O control for port 1 pins PIO1_22
0xD8
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO123
Digital I/O control for port 1 pins PIO1_23
0xDC
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO124
Digital I/O control for port 1 pins PIO1_24
0xE0
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO125
Digital I/O control for port 1 pins PIO1_25
0xE4
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO126
Digital I/O control for port 1 pins PIO1_26
0xE8
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO127
Digital I/O control for port 1 pins PIO1_27
0xEC
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO128
Digital I/O control for port 1 pins PIO1_28
0xF0
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO129
Digital I/O control for port 1 pins PIO1_29
0xF4
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO130
Digital I/O control for port 1 pins PIO1_30
0xF8
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
PIO131
Digital I/O control for port 1 pins PIO1_31
0xFC
32
read-write
0x190
0x7DF
FUNC
Selects pin function.
0
3
read-write
ALT0
Alternative connection 0.
0
ALT1
Alternative connection 1.
0x1
ALT2
Alternative connection 2.
0x2
ALT3
Alternative connection 3.
0x3
ALT4
Alternative connection 4.
0x4
ALT5
Alternative connection 5.
0x5
ALT6
Alternative connection 6.
0x6
ALT7
Alternative connection 7.
0x7
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
INVERT
Input polarity.
6
1
read-write
DISABLED
Disabled. Input function is not inverted.
0
ENABLED
Enabled. Input is function inverted.
0x1
DIGIMODE
Select Analog/Digital mode.
7
1
read-write
ANALOG
Analog mode.
0
DIGITAL
Digital mode.
0x1
FILTEROFF
Controls input glitch filter.
8
1
read-write
ENABLED
Filter enabled. Noise pulses below approximately 10 ns are filtered out.
0
DISABLED
Filter disabled. No input filtering is done.
0x1
SLEW
Driver slew rate.
9
1
read-write
STANDARD
Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
0
FAST
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
0x1
OD
Controls open-drain mode.
10
1
read-write
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive disabled).
0x1
UTICK0
LPC5410x Micro-tick Timer (UTICK)
UTICK
0x40020000
0
0x20
registers
UTICK0
9
CTRL
Control register.
0
32
read-write
0
0xFFFFFFFF
DELAYVAL
Tick interval value. The delay will be equal to DELAYVAL + 1 periods of the timer clock. The minimum usable value is 1, for a delay of 2 timer clocks. A value of 0 stops the timer.
0
31
read-write
REPEAT
Repeat delay. 0 = One-time delay. 1 = Delay repeats continuously.
31
1
read-write
STAT
Status register.
0x4
32
read-write
0
0x3
INTR
Interrupt flag. 0 = No interrupt is pending. 1 = An interrupt is pending. A write of any value to this register clears this flag.
0
1
read-write
ACTIVE
Active flag. 0 = The Micro-Tick Timer is stopped. 1 = The Micro-Tick Timer is currently active.
1
1
read-write
CFG
Capture configuration register.
0x8
32
read-write
0
0xF0F
CAPEN0
Enable Capture 0. 1 = Enabled, 0 = Disabled.
0
1
read-write
CAPEN1
Enable Capture 1. 1 = Enabled, 0 = Disabled.
1
1
read-write
CAPEN2
Enable Capture 2. 1 = Enabled, 0 = Disabled.
2
1
read-write
CAPEN3
Enable Capture 3. 1 = Enabled, 0 = Disabled.
3
1
read-write
CAPPOL0
Capture Polarity 0. 0 = Positive edge capture, 1 = Negative edge capture.
8
1
read-write
CAPPOL1
Capture Polarity 1. 0 = Positive edge capture, 1 = Negative edge capture.
9
1
read-write
CAPPOL2
Capture Polarity 2. 0 = Positive edge capture, 1 = Negative edge capture.
10
1
read-write
CAPPOL3
Capture Polarity 3. 0 = Positive edge capture, 1 = Negative edge capture.
11
1
read-write
CAPCLR
Capture clear register.
0xC
32
write-only
0
0
CAPCLR0
Clear capture 0. Writing 1 to this bit clears the CAP0 register value.
0
1
write-only
CAPCLR1
Clear capture 1. Writing 1 to this bit clears the CAP1 register value.
1
1
write-only
CAPCLR2
Clear capture 2. Writing 1 to this bit clears the CAP2 register value.
2
1
write-only
CAPCLR3
Clear capture 3. Writing 1 to this bit clears the CAP3 register value.
3
1
write-only
4
0x4
CAP[%s]
Capture register .
0x10
32
read-only
0
0xFFFFFFFF
CAP_VALUE
Capture value for the related capture event (UTICK_CAPn. Note: the value is 1 lower than the actual value of the Micro-tick Timer at the moment of the capture event.
0
31
read-only
VALID
Capture Valid. When 1, a value has been captured based on a transition of the related UTICK_CAPn pin. Cleared by writing to the related bit in the CAPCLR register.
31
1
read-only
WWDT
LPC5410x Windowed Watchdog Timer (WWDT)
WWDT
0x40038000
0
0x1C
registers
WDT
0
MOD
Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer.
0
32
read-write
0
0x3F
WDEN
Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the watchdog timer will run permanently.
0
1
read-write
STOP
Stop. The watchdog timer is stopped.
0
RUN
Run. The watchdog timer is running.
0x1
WDRESET
Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0.
1
1
read-write
INTERRUPT
Interrupt. A watchdog time-out will not cause a chip reset.
0
RESET
Reset. A watchdog time-out will cause a chip reset.
0x1
WDTOF
Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software. Causes a chip reset if WDRESET = 1.
2
1
read-write
WDINT
Warning interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software.
3
1
read-write
WDPROTECT
Watchdog update mode. This bit can be set once by software and is only cleared by a reset.
4
1
read-write
FLEXIBLE
Flexible. The watchdog time-out value (TC) can be changed at any time.
0
THRESHOLD
Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW.
0x1
LOCK
Once this bit is set to one and a watchdog feed is performed, disabling or powering down the watchdog oscillator is prevented by hardware. This bit can be set once by software and is only cleared by any reset.
5
1
read-write
TC
Watchdog timer constant register. This 24-bit register determines the time-out value.
0x4
32
read-write
0xFF
0xFFFFFF
COUNT
Watchdog time-out value.
0
24
read-write
FEED
Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC.
0x8
32
write-only
0
0
FEED
Feed value should be 0xAA followed by 0x55.
0
8
write-only
TV
Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer.
0xC
32
read-only
0xFF
0xFFFFFF
COUNT
Counter timer value.
0
24
read-only
WARNINT
Watchdog Warning Interrupt compare value.
0x14
32
read-write
0
0x3FF
WARNINT
Watchdog warning interrupt compare value.
0
10
read-write
WINDOW
Watchdog Window compare value.
0x18
32
read-write
0xFFFFFF
0xFFFFFF
WINDOW
Watchdog window value.
0
24
read-write
RTC
LPC5410x Real-Time Clock (RTC)
RTC
0x4003C000
0
0x10
registers
RTC
29
CTRL
RTC control register
0
32
read-write
0xF
0xFFFFFFFF
SWRESET
Software reset control
0
1
read-write
NOT_IN_RESET
Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC.
0
IN_RESET
In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes to set any of the other bits within this register. Do not attempt to write to any bits of this register at the same time that the reset bit is being cleared.
0x1
OFD
Oscillator fail detect status.
1
1
read-write
RUN
Run. The RTC oscillator is running properly. Writing a 0 has no effect.
0
FAIL
Fail. RTC oscillator fail detected. Clear this flag after the following power-up. Writing a 1 clears this bit.
0x1
ALARM1HZ
RTC 1 Hz timer alarm flag status.
2
1
read-write
NO_MATCH
No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect.
0
MATCH
Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit.
0x1
WAKE1KHZ
RTC 1 kHz timer wake-up flag status.
3
1
read-write
RUN
Run. The RTC 1 kHz timer is running. Writing a 0 has no effect.
0
TIME_OUT
Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit.
0x1
ALARMDPD_EN
RTC 1 Hz timer alarm enable for Deep power-down.
4
1
read-write
DISABLE
Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode.
0
ENABLE
Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode.
0x1
WAKEDPD_EN
RTC 1 kHz timer wake-up enable for Deep power-down.
5
1
read-write
DISABLE
Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode.
0
ENABLE
Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode.
0x1
RTC1KHZ_EN
RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0).
6
1
read-write
DISABLE
Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode.
0
ENABLE
Enable. The 1 kHz RTC timer is enabled.
0x1
RTC_EN
RTC enable.
7
1
read-write
DISABLE
Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should be 0 when writing to load a value in the RTC counter register.
0
ENABLE
Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the high-resolution, 1 kHz clock, set bit 6 in this register.
0x1
MATCH
RTC match register
0x4
32
read-write
0xFFFFFFFF
0xFFFFFFFF
MATVAL
Contains the match value against which the 1 Hz RTC timer will be compared to set the alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled.
0
32
read-write
COUNT
RTC counter register
0x8
32
read-write
0
0xFFFFFFFF
VAL
A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this register when the RTC_EN bit in the RTC CTRL Register is 0. The counter increments one second after the RTC_EN bit is set.
0
32
read-write
WAKE
High-resolution/wake-up timer control register
0xC
32
read-write
0
0xFFFF
VAL
A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads a start count value into the wake-up timer and initializes a count-down sequence. Do not write to this register while counting is in progress.
0
16
read-write
INPUTMUX
LPC5410x Input multiplexing (INPUT MUX)
INPUTMUX
0x40050000
0
0x168
registers
8
0x4
PINTSEL[%s]
Pin interrupt select register
0xC0
32
read-write
0
0xFF
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO1_31 correspond to numbers 0 to 63).
0
8
read-write
22
0x4
DMA_ITRIG_INMUX[%s]
Trigger select register for DMA channel
0xE0
32
read-write
0x1F
0x1F
INP
Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match 0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3
0
5
read-write
4
0x4
DMA_OTRIG_INMUX[%s]
DMA output trigger selection to become DMA trigger
0x140
32
read-write
0x1F
0x1F
INP
DMA trigger output number (decimal value) for DMA channel n (n = 0 to 19).
0
5
read-write
FREQMEAS_REF
Selection for frequency measurement reference clock
0x160
32
read-write
0x1F
0x1F
CLKIN
Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4
0
5
read-write
FREQMEAS_TARGET
Selection for frequency measurement target clock
0x164
32
read-write
0x1F
0x1F
CLKIN
Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4
0
5
read-write
RIT
Repetitive Interrupt Timer
RIT
0x40070000
0
0x20
registers
COMPVAL
Compare value LSB register. Holds the 32 LSBs of the compare value.
0
32
read-write
0xFFFFFFFF
0xFFFFFFFF
RICOMP
Compare register. Holds the 32 LSBs of the value which is compared to the counter.
0
32
read-write
MASK
Mask LSB register. This register holds the 32 LSB s of the mask value. A 1 written to any bit will force the compare to be true for the corresponding bit of the counter and compare register.
0x4
32
read-write
0
0xFFFFFFFF
RIMASK
Mask register. This register holds the 32 LSBs of the mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true).
0
32
read-write
CTRL
Control register.
0x8
32
read-write
0xC
0xFFFFFFFF
RITINT
Interrupt flag
0
1
read-write
NOMTCH
The counter value does not equal the masked compare value.
0
MATCH
This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect.
0x1
RITENCLR
Timer enable clear
1
1
read-write
NOCLEAR
The timer will not be cleared to 0.
0
CLEAR
The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of COMPVAL/COMPVAL_H and MASK/MASK_H registers. This will occur on the same clock that sets the interrupt flag.
0x1
RITENBR
Timer enable for debug
2
1
read-write
DEBUG
Debug has no effect on the timer operation.
0
HALT
The timer is halted when the processor is halted for debugging.
0x1
RITEN
Timer enable.
3
1
read-write
TIMER_DISABLED
Timer disabled.
0
TIMER_ENABLED
Timer enabled. This can be overruled by a debug halt if enabled in bit 2.
0x1
COUNTER
Counter LSB register. 32 LSBs of the counter.
0xC
32
read-write
0
0xFFFFFFFF
RICOUNTER
32 LSBs of the up counter. Counts continuously unless RITEN bit in CTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software.
0
32
read-write
COMPVAL_H
Compare value MSB register. Holds the 16 MSBs of the compare value.
0x10
32
read-write
0xFFFF
0xFFFFFFFF
RICOMP
Compare value MSB register. Holds the 16 MSBs of the value which is compared to the counter.
0
16
read-write
MASK_H
Mask MSB register. This register holds the 16 MSBs of the mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register.
0x14
32
read-write
0
0xFFFFFFFF
RIMASK
Mask register. This register holds the 16 MSBs of the mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true).
0
16
read-write
COUNTER_H
Counter MSB register. 16 MSBs of the counter.
0x1C
32
read-write
0
0xFFFFFFFF
RICOUNTER
16 LSBs of the up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software.
0
16
read-write
MRT0
LPC5410x Multi-Rate Timer (MRT)
MRT
0x40074000
0
0xFC
registers
MRT0
10
4
0x10
CHANNEL[%s]
no description available
0
INTVAL
MRT Time interval value register. This value is loaded into the TIMER register.
0
32
read-write
0
0x80FFFFFF
IVALUE
Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval.
0
24
read-write
LOAD
Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0.
31
1
read-write
NO_FORCE_LOAD
No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected.
0
FORCE_LOAD
Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.
0x1
TIMER
MRT Timer register. This register reads the value of the down-counter.
0x4
32
read-only
0xFFFFFF
0xFFFFFF
VALUE
Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF).
0
24
read-only
CTRL
MRT Control register. This register controls the MRT modes.
0x8
32
read-write
0
0x7
INTEN
Enable the TIMERn interrupt.
0
1
read-write
DISABLED
Disabled. TIMERn interrupt is disabled.
0
ENABLED
Enabled. TIMERn interrupt is enabled.
0x1
MODE
Selects timer mode.
1
2
read-write
REPEAT_INTERRUPT_MODE
Repeat interrupt mode.
0
ONE_SHOT_INTERRUPT_MODE
One-shot interrupt mode.
0x1
ONE_SHOT_STALL_MODE
One-shot stall mode.
0x2
STAT
MRT Status register.
0xC
32
read-write
0
0x7
INTFLAG
Monitors the interrupt flag.
0
1
read-write
NO_PENDING_INTERRUPT
No pending interrupt. Writing a zero is equivalent to no operation.
0
PENDING_INTERRUPT
Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.
0x1
RUN
Indicates the state of TIMERn. This bit is read-only.
1
1
read-write
IDLE_STATE
Idle state. TIMERn is stopped.
0
RUNNING
Running. TIMERn is running.
0x1
INUSE
Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating modes.
2
1
read-write
NO
This channel is not in use.
0
YES
This channel is in use.
0x1
MODCFG
Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature.
0xF0
32
read-write
0x173
0x800001FF
NOC
Identifies the number of channels in this MRT.(4 channels on this device.)
0
4
read-write
NOB
Identifies the number of timer bits in this MRT. (24 bits wide on this device.)
4
5
read-write
MULTITASK
Selects the operating mode for the INUSE flags and the IDLE_CH register.
31
1
read-write
HARDWARE_STATUS_MODE
Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset.
0
MULTI_TASK_MODE
Multi-task mode.
0x1
IDLE_CH
Idle channel register. This register returns the number of the first idle channel.
0xF4
32
read-only
0
0xF0
CHAN
Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is positioned such that it can be used as an offset from the MRT base address in order to access the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See text above for more details.
4
4
read-only
IRQ_FLAG
Global interrupt flag register
0xF8
32
read-write
0
0xF
GFLAG0
Monitors the interrupt flag of TIMER0.
0
1
read-write
NO_PENDING_INTERRUPT
No pending interrupt. Writing a zero is equivalent to no operation.
0
PENDING_INTERRUPT
Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.
0x1
GFLAG1
Monitors the interrupt flag of TIMER1. See description of channel 0.
1
1
read-write
GFLAG2
Monitors the interrupt flag of TIMER2. See description of channel 0.
2
1
read-write
GFLAG3
Monitors the interrupt flag of TIMER3. See description of channel 0.
3
1
read-write
ASYNC_SYSCON
LPC5410x Asynchronous system configuration (ASYNC_SYSCON)
ASYNC_SYSCON
0x40080000
0
0x34
registers
ASYNCPRESETCTRL
Async peripheral reset control
0
32
read-write
0
0x6000
USART0
USART0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
1
1
read-write
USART1
USART1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
2
1
read-write
USART2
USART2 reset control.0 = Clear reset to this function. 1 = Assert reset to this function.
3
1
read-write
USART3
USART3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
4
1
read-write
I2C0
I2C0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
5
1
read-write
I2C1
I2C1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
6
1
read-write
I2C2
I2C2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
7
1
read-write
SPI0
SPI0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
9
1
read-write
SPI1
SPI1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
10
1
read-write
CT32B0
CT32B 0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
13
1
read-write
CT32B1
CT32B 1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
14
1
read-write
FRG0
FRG reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
15
1
read-write
ASYNCPRESETCTRLSET
Set bits in ASYNCPRESETCTRL
0x4
32
write-only
0
0
ARST_SET
Writing ones to this register sets the corresponding bit or bits in the ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
0
32
write-only
ASYNCPRESETCTRLCLR
Clear bits in ASYNCPRESETCTRL
0x8
32
write-only
0
0
ARST_CLR
Writing ones to this register clears the corresponding bit or bits in the ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
0
32
write-only
ASYNCAPBCLKCTRL
Async peripheral clock control
0x10
32
read-write
0
0x6000
USART0
Controls the clock for USART0. 0 = Disable; 1 = Enable.
1
1
read-write
USART1
Controls the clock for USART1. 0 = Disable; 1 = Enable.
2
1
read-write
USART2
Controls the clock for USART2. 0 = Disable; 1 = Enable.
3
1
read-write
USART3
Controls the clock for USART3. 0 = Disable; 1 = Enable.
4
1
read-write
I2C0
Controls the clock for I2C0. 0 = Disable; 1 = Enable.
5
1
read-write
I2C1
Controls the clock for I2C1. 0 = Disable; 1 = Enable.
6
1
read-write
I2C2
Controls the clock for I2C2. 0 = Disable; 1 = Enable.
7
1
read-write
SPI0
Controls the clock for SPI0. 0 = Disable; 1 = Enable.
9
1
read-write
SPI1
Controls the clock for SPI1. 0 = Disable; 1 = Enable.
10
1
read-write
CT32B0
Controls the clock for CT32B0. 0 = Disable; 1 = Enable.
13
1
read-write
CT32B1
Controls the clock for CT32B1. 0 = Disable; 1 = Enable.
14
1
read-write
FRG0
Controls the clock for the Fractional Rate Generator used with the USARTs. 0 = Disable; 1 = Enable.
15
1
read-write
ASYNCAPBCLKCTRLSET
Set bits in ASYNCAPBCLKCTRL
0x14
32
write-only
0
0
ACLK_SET
Writing ones to this register sets the corresponding bit or bits in the ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
0
32
write-only
ASYNCAPBCLKCTRLCLR
Clear bits in ASYNCAPBCLKCTRL
0x18
32
write-only
0
0
ACLK_CLR
Writing ones to this register clears the corresponding bit or bits in the ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in ASYNCAPBCLKCTRL are reserved and only zeroes should be written to them.
0
32
write-only
ASYNCAPBCLKSELA
Async APB clock source select A
0x20
32
read-write
0
0xFFFFFFFF
SEL
Clock source for asynchronous clock source selector A
0
2
read-write
IRC_OSCILLATOR
IRC Oscillator
0
WATCHDOG_OSCILLATOR
Watchdog oscillator
0x1
ASYNCAPBCLKSELB
Async APB clock source select B
0x24
32
read-write
0
0xFFFFFFFF
SEL
Clock source for asynchronous clock source selector B.
0
2
read-write
MAIN_CLOCK
Main clock
0
CLKIN
CLKIN
0x1
SYSTEM_PLL_OUTPUT
System PLL output.
0x2
ASYNCAPBCLKSELA
ASYNCAPBCLKSELA. Clock selected by the ASYNCAPBCLKSELA register.
0x3
ASYNCCLKDIV
Async APB clock divider
0x28
32
read-write
0x1
0xFFFFFFFF
DIV
Asynchronous APB clock divider value. 0: Clock disabled. 1: Divide by 1. to 255: Divide by 255.
0
8
read-write
FRGCTRL
USART fractional rate generator control
0x30
32
read-write
0xFF
0xFFFFFFFF
DIV
Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator.
0
8
read-write
MULT
Numerator of the fractional divider. MULT is equal to the programmed value.
8
8
read-write
USART0
USART
USART
USART
0x40084000
0
0x30
registers
USART0
17
CFG
USART Configuration register. Basic USART configuration settings that typically are not changed during operation.
0
32
read-write
0
0xFFFFFFFF
ENABLE
USART Enable.
0
1
read-write
DISABLED
Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. For instance, when re-enabled, the USART will immediately generate a TxRdy interrupt (if enabled in the INTENSET register) or a DMA transfer request because the transmitter has been reset and is therefore available.
0
ENABLED
Enabled. The USART is enabled for operation.
0x1
DATALEN
Selects the data size for the USART.
2
2
read-write
DATALEN_7_BIT_DATA_LENGTH
7 bit Data length.
0
DATALEN_8_BIT_DATA_LENGTH
8 bit Data length.
0x1
DATALEN_9_BIT_DATA_LENGTH
9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register.
0x2
PARITYSEL
Selects what type of parity is used by the USART.
4
2
read-write
NO_PARITY
No parity.
0
EVEN_PARITY
Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even.
0x2
ODD_PARITY
Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd.
0x3
STOPLEN
Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.
6
1
read-write
STOPLEN_1_STOP_BIT
1 stop bit.
0
STOPLEN_2_STOP_BITS
2 stop bits. This setting should only be used for asynchronous communication.
0x1
MODE32K
Selects standard or 32 kHz clocking mode.
7
1
read-write
DISABLED
Disabled. USART uses standard clocking.
0
ENABLED
Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme.
0x1
LINMODE
LIN break mode enable.
8
1
read-write
DISABLED
Disabled. Break detect and generate is configured for normal operation.
0
ENABLED
Enabled. Break detect and generate is configured for LIN bus operation.
0x1
CTSEN
CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled.
9
1
read-write
NO_FLOW_CONTROL
No flow control. The transmitter does not receive any automatic flow control signal.
0
FLOW_CONTROL_ENABLED
Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.
0x1
SYNCEN
Selects synchronous or asynchronous operation.
11
1
read-write
ASYNCHRONOUS_MODE
Asynchronous mode.
0
SYNCHRONOUS_MODE
Synchronous mode.
0x1
CLKPOL
Selects the clock polarity and sampling edge of received data in synchronous mode.
12
1
read-write
FALLING_EDGE
Falling edge. Un_RXD is sampled on the falling edge of SCLK.
0
RISING_EDGE
Rising edge. Un_RXD is sampled on the rising edge of SCLK.
0x1
SYNCMST
Synchronous mode Master select.
14
1
read-write
SLAVE
Slave. When synchronous mode is enabled, the USART is a slave.
0
MASTER
Master. When synchronous mode is enabled, the USART is a master.
0x1
LOOP
Selects data loopback mode.
15
1
read-write
NORMAL_OPERATION
Normal operation.
0
LOOPBACK_MODE
Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN.
0x1
OETA
Output Enable Turnaround time enable for RS-485 operation.
18
1
read-write
DISABLED
Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission.
0
ENABLED
Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted.
0x1
AUTOADDR
Automatic Address matching enable.
19
1
read-write
DISABLED
Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address).
0
ENABLED
Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match.
0x1
OESEL
Output Enable Select.
20
1
read-write
STANDARD
Standard. The RTS signal is used as the standard flow control function.
0
RS_485
RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver.
0x1
OEPOL
Output Enable Polarity.
21
1
read-write
LOW
Low. If selected by OESEL, the output enable is active low.
0
HIGH
High. If selected by OESEL, the output enable is active high.
0x1
RXPOL
Receive data polarity.
22
1
read-write
STANDARD
Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.
0
INVERTED
Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.
0x1
TXPOL
Transmit data polarity.
23
1
read-write
STANDARD
Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.
0
INVERTED
Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.
0x1
CTL
USART Control register. USART control settings that are more likely to change during operation.
0x4
32
read-write
0
0xFFFFFFFF
TXBRKEN
Break Enable.
1
1
read-write
NORMAL_OPERATION
Normal operation.
0
CONTINUOUS_BREAK
Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN.
0x1
ADDRDET
Enable address detect mode.
2
1
read-write
DISABLED
Disabled. The USART presents all incoming data.
0
ENABLED
Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally.
0x1
TXDIS
Transmit Disable.
6
1
read-write
NOT_DISABLED
Not disabled. USART transmitter is not disabled.
0
DISABLED
Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control.
0x1
CC
Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.
8
1
read-write
CLOCK_ON_CHARACTER
Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received.
0
CONTINUOUS_CLOCK
Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD).
0x1
CLRCCONRX
Clear Continuous Clock.
9
1
read-write
NO_EFFECT
No effect. No effect on the CC bit.
0
AUTO_CLEAR
Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time.
0x1
AUTOBAUD
Autobaud enable.
16
1
read-write
DISABLED
Disabled. USART is in normal operating mode.
0
ENABLED
Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR.
0x1
STAT
USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.
0x8
32
read-write
0xE
0xFFFFFFFF
RXRDY
Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers.
0
1
read-write
RXIDLE
Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data.
1
1
read-write
TXRDY
Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift register.
2
1
read-write
TXIDLE
Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data.
3
1
read-write
CTS
This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled.
4
1
read-write
DELTACTS
This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software.
5
1
read-write
TXDISSTAT
Transmitter Disabled Status flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1).
6
1
read-write
OVERRUNINT
Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost.
8
1
read-write
RXBRK
Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high.
10
1
read-write
DELTARXBRK
This bit is set when a change in the state of receiver break detection occurs. Cleared by software.
11
1
read-write
START
This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software.
12
1
read-write
FRAMERRINT
Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.
13
1
read-write
PARITYERRINT
Parity Error interrupt flag. This flag is set when a parity error is detected in a received character..
14
1
read-write
RXNOISEINT
Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception.
15
1
read-write
ABERR
Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an auto baud time-out.
16
1
read-write
INTENSET
Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
0xC
32
read-write
0
0xFFFFFFFF
RXRDYEN
When 1, enables an interrupt when there is a received character available to be read from the RXDAT register.
0
1
read-write
TXRDYEN
When 1, enables an interrupt when the TXDAT register is available to take another character to transmit.
2
1
read-write
TXIDLEEN
When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1).
3
1
read-write
DELTACTSEN
When 1, enables an interrupt when there is a change in the state of the CTS input.
5
1
read-write
TXDISEN
When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details.
6
1
read-write
OVERRUNEN
When 1, enables an interrupt when an overrun error occurred.
8
1
read-write
DELTARXBRKEN
When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted).
11
1
read-write
STARTEN
When 1, enables an interrupt when a received start bit has been detected.
12
1
read-write
FRAMERREN
When 1, enables an interrupt when a framing error has been detected.
13
1
read-write
PARITYERREN
When 1, enables an interrupt when a parity error has been detected.
14
1
read-write
RXNOISEEN
When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 311.
15
1
read-write
ABERREN
When 1, enables an interrupt when an auto baud error occurs.
16
1
read-write
INTENCLR
Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.
0x10
32
read-write
0
0
RXRDYCLR
Writing 1 clears the corresponding bit in the INTENSET register.
0
1
read-write
TXRDYCLR
Writing 1 clears the corresponding bit in the INTENSET register.
2
1
read-write
TXIDLECLR
Writing 1 clears the corresponding bit in the INTENSET register.
3
1
read-write
DELTACTSCLR
Writing 1 clears the corresponding bit in the INTENSET register.
5
1
read-write
TXDISCLR
Writing 1 clears the corresponding bit in the INTENSET register.
6
1
read-write
OVERRUNCLR
Writing 1 clears the corresponding bit in the INTENSET register.
8
1
read-write
DELTARXBRKCLR
Writing 1 clears the corresponding bit in the INTENSET register.
11
1
read-write
STARTCLR
Writing 1 clears the corresponding bit in the INTENSET register.
12
1
read-write
FRAMERRCLR
Writing 1 clears the corresponding bit in the INTENSET register.
13
1
read-write
PARITYERRCLR
Writing 1 clears the corresponding bit in the INTENSET register.
14
1
read-write
RXNOISECLR
Writing 1 clears the corresponding bit in the INTENSET register.
15
1
read-write
ABERRCLR
Writing 1 clears the corresponding bit in the INTENSET register.
16
1
read-write
RXDAT
Receiver Data register. Contains the last character received.
0x14
32
read-write
0
0
DATA
The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings.
0
9
read-write
RXDATSTAT
Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together.
0x18
32
read-write
0
0
RXDATA
The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings.
0
9
read-write
FRAMERR
Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.
13
1
read-write
PARITYERR
Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character.
14
1
read-write
RXNOISE
Received Noise flag. See description of the RxNoiseInt bit in Table 311.
15
1
read-write
TXDAT
Transmit Data register. Data to be transmitted is written here.
0x1C
32
read-write
0
0xFFFFFFFF
TXDATA
Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0.
0
9
read-write
BRG
Baud Rate Generator register. 16-bit integer baud rate divisor value.
0x20
32
read-write
0
0xFFFFFFFF
BRGVAL
This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = The FRG clock is used directly by the USART function. 1 = The FRG clock is divided by 2 before use by the USART function. 2 = The FRG clock is divided by 3 before use by the USART function. ... 0xFFFF = The FRG clock is divided by 65,536 before use by the USART function.
0
16
read-write
INTSTAT
Interrupt status register. Reflects interrupts that are currently enabled.
0x24
32
read-write
0x5
0xFFFFFFFF
RXRDY
Receiver Ready flag.
0
1
read-write
TXRDY
Transmitter Ready flag.
2
1
read-write
TXIDLE
Transmitter Idle status.
3
1
read-write
DELTACTS
This bit is set when a change in the state of the CTS input is detected.
5
1
read-write
TXDISINT
Transmitter Disabled Interrupt flag.
6
1
read-write
OVERRUNINT
Overrun Error interrupt flag.
8
1
read-write
DELTARXBRK
This bit is set when a change in the state of receiver break detection occurs.
11
1
read-write
START
This bit is set when a start is detected on the receiver input.
12
1
read-write
FRAMERRINT
Framing Error interrupt flag.
13
1
read-write
PARITYERRINT
Parity Error interrupt flag.
14
1
read-write
RXNOISEINT
Received Noise interrupt flag.
15
1
read-write
ABERRINT
Auto baud Error Interrupt flag.
16
1
read-write
OSR
Oversample selection register for asynchronous communication.
0x28
32
read-write
0xF
0xFFFFFFFF
OSRVAL
Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 peripheral clocks are used to transmit and receive each data bit. 0x5 = 6 peripheral clocks are used to transmit and receive each data bit. ... 0xF= 16 peripheral clocks are used to transmit and receive each data bit.
0
4
read-write
ADDR
Address register for automatic address matching.
0x2C
32
read-write
0
0xFFFFFFFF
ADDRESS
8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1).
0
8
read-write
USART1
USART
USART
0x40088000
0
0x30
registers
USART1
18
USART2
USART
USART
0x4008C000
0
0x30
registers
USART2
19
USART3
USART
USART
0x40090000
0
0x30
registers
USART3
20
I2C0
I2C-bus interface 0
I2C
I2C
0x40094000
0
0x84
registers
I2C0
21
CFG
Configuration for shared functions.
0
32
read-write
0
0xFFFFFFFF
MSTEN
Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset.
0
1
read-write
DISABLED
Disabled. The I2C Master function is disabled.
0
ENABLED
Enabled. The I2C Master function is enabled.
0x1
SLVEN
Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset.
1
1
read-write
DISABLED
Disabled. The I2C slave function is disabled.
0
ENABLED
Enabled. The I2C slave function is enabled.
0x1
MONEN
Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset.
2
1
read-write
DISABLED
Disabled. The I2C monitor function is disabled.
0
ENABLED
Enabled. The I2C monitor function is enabled.
0x1
TIMEOUTEN
I2C bus Time-out Enable. When disabled, the time-out function is internally reset.
3
1
read-write
DISABLED
Disabled. Time-out function is disabled.
0
ENABLED
Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system.
0x1
MONCLKSTR
Monitor function Clock Stretching.
4
1
read-write
DISABLED
Disabled. The monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical.
0
ENABLED
Enabled. The monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the monitor function.
0x1
HSCAPABLE
High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies to all functions: master, slave, and monitor.
5
1
read-write
FAST_MODE_PLUS
Fast-mode plus. The I2C block will support Standard-mode, Fast-mode, and Fast-mode Plus, to the extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, such as changing the drive strength or filtering, must be made by software via the IOCON register associated with each I2C pin,
0
HIGH_SPEED
High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C block will support High-speed mode to the extent that the pin electronics support these modes. See Section 23.7.1.2 for more information.
0x1
STAT
Status register for Master, Slave, and Monitor functions.
0x4
32
read-write
0x801
0xFFFFFFFF
MSTPENDING
Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt.
0
1
read-write
IN_PROGRESS
In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.
0
PENDING
Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit.
0x1
MSTSTATE
Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 346 for details of state values and appropriate responses.
1
3
read-write
IDLE
Idle. The Master function is available to be used for a new transaction.
0
RECEIVE_READY
Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.
0x1
TRANSMIT_READY
Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.
0x2
NACK_ADDRESS
NACK Address. Slave NACKed address.
0x3
NACK_DATA
NACK Data. Slave NACKed transmitted data.
0x4
MSTARBLOSS
Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
4
1
read-write
NO_ARBITRATION_LOSS
No Arbitration Loss has occurred.
0
ARBITRATION_LOSS
Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.
0x1
MSTSTSTPERR
Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
6
1
read-write
NO_STARTSTOP_ERROR
No Start/Stop Error has occurred.
0
THE_MASTER_FUNCTION
The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled.
0x1
SLVPENDING
Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the MSTCTL register. The point in time when SlvPending is set depends on whether the I2C block is in HSCAPABLE mode. See Section 23.7.1.2.2. When the I2C block is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched.
8
1
read-write
IN_PROGRESS
In progress. The Slave function does not currently need service.
0
PENDING
Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.
0x1
SLVSTATE
Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 347 for state values and actions.
9
2
read-write
SLAVE_ADDRESS
Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.
0
SLAVE_RECEIVE
Slave receive. Received data is available (Slave Receiver mode).
0x1
SLAVE_TRANSMIT
Slave transmit. Data can be transmitted (Slave Transmitter mode).
0x2
SLVNOTSTR
Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time.
11
1
read-write
STRETCHING
Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.
0
NOT_STRETCHING
Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time.
0x1
SLVIDX
Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here.
12
2
read-write
ADDRESS_0
Address 0. Slave address 0 was matched.
0
ADDRESS_1
Address 1. Slave address 1 was matched.
0x1
ADDRESS_2
Address 2. Slave address 2 was matched.
0x2
ADDRESS_3
Address 3. Slave address 3 was matched.
0x3
SLVSEL
Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, or when there is a Stop detected on the bus. SLVSEL is not cleared if software NACKs data.
14
1
read-write
NOT_SELECTED
Not selected. The Slave function is not currently selected.
0
SELECTED
Selected. The Slave function is currently selected.
0x1
SLVDESEL
Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit.
15
1
read-write
NOT_DESELECTED
Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag.
0
DESELECTED
Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.
0x1
MONRDY
Monitor Ready. This flag is cleared when the MONRXDAT register is read.
16
1
read-write
NO_DATA
No data. The Monitor function does not currently have data available.
0
DATA_WAITING
Data waiting. The Monitor function has data waiting to be read.
0x1
MONOV
Monitor Overflow flag.
17
1
read-write
NO_OVERRUN
No overrun. Monitor data has not overrun.
0
OVERRUN
Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.
0x1
MONACTIVE
Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop.
18
1
read-write
INACTIVE
Inactive. The Monitor function considers the I2C bus to be inactive.
0
ACTIVE
Active. The Monitor function considers the I2C bus to be active.
0x1
MONIDLE
Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit.
19
1
read-write
NOT_IDLE
Not idle. The I2C bus is not idle, or this flag has been cleared by software.
0
IDLE
Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software.
0x1
EVENTTIMEOUT
Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle.
24
1
read-write
NO_TIME_OUT
No time-out. I2C bus events have not caused a time-out.
0
EVENT_TIME_OUT
Event time-out. The time between I2C bus events has been longer than the time specified by the I2C TIMEOUT register.
0x1
SCLTIMEOUT
SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit.
25
1
read-write
NO_TIME_OUT
No time-out. SCL low time has not caused a time-out.
0
TIME_OUT
Time-out. SCL low time has caused a time-out.
0x1
INTENSET
Interrupt Enable Set and read register.
0x8
32
read-write
0
0xFFFFFFFF
MSTPENDINGEN
Master Pending interrupt Enable.
0
1
read-write
DISABLED
Disabled. The MstPending interrupt is disabled.
0
ENABLED
Enabled. The MstPending interrupt is enabled.
0x1
MSTARBLOSSEN
Master Arbitration Loss interrupt Enable.
4
1
read-write
DISABLED
Disabled. The MstArbLoss interrupt is disabled.
0
ENABLED
Enabled. The MstArbLoss interrupt is enabled.
0x1
MSTSTSTPERREN
Master Start/Stop Error interrupt Enable.
6
1
read-write
DISABLED
Disabled. The MstStStpErr interrupt is disabled.
0
ENABLED
Enabled. The MstStStpErr interrupt is enabled.
0x1
SLVPENDINGEN
Slave Pending interrupt Enable.
8
1
read-write
DISABLED
Disabled. The SlvPending interrupt is disabled.
0
ENABLED
Enabled. The SlvPending interrupt is enabled.
0x1
SLVNOTSTREN
Slave Not Stretching interrupt Enable.
11
1
read-write
DISABLED
Disabled. The SlvNotStr interrupt is disabled.
0
ENABLED
Enabled. The SlvNotStr interrupt is enabled.
0x1
SLVDESELEN
Slave Deselect interrupt Enable.
15
1
read-write
DISABLED
Disabled. The SlvDeSel interrupt is disabled.
0
ENABLED
Enabled. The SlvDeSel interrupt is enabled.
0x1
MONRDYEN
Monitor data Ready interrupt Enable.
16
1
read-write
DISABLED
Disabled. The MonRdy interrupt is disabled.
0
ENABLED
Enabled. The MonRdy interrupt is enabled.
0x1
MONOVEN
Monitor Overrun interrupt Enable.
17
1
read-write
DISABLED
Disabled. The MonOv interrupt is disabled.
0
ENABLED
Enabled. The MonOv interrupt is enabled.
0x1
MONIDLEEN
Monitor Idle interrupt Enable.
19
1
read-write
DISABLED
Disabled. The MonIdle interrupt is disabled.
0
ENABLED
Enabled. The MonIdle interrupt is enabled.
0x1
EVENTTIMEOUTEN
Event time-out interrupt Enable.
24
1
read-write
DISABLED
Disabled. The Event time-out interrupt is disabled.
0
ENABLED
Enabled. The Event time-out interrupt is enabled.
0x1
SCLTIMEOUTEN
SCL time-out interrupt Enable.
25
1
read-write
DISABLED
Disabled. The SCL time-out interrupt is disabled.
0
ENABLED
Enabled. The SCL time-out interrupt is enabled.
0x1
INTENCLR
Interrupt Enable Clear register.
0xC
32
read-write
0
0
MSTPENDINGCLR
Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented.
0
1
read-write
MSTARBLOSSCLR
Master Arbitration Loss interrupt clear.
4
1
read-write
MSTSTSTPERRCLR
Master Start/Stop Error interrupt clear.
6
1
read-write
SLVPENDINGCLR
Slave Pending interrupt clear.
8
1
read-write
SLVNOTSTRCLR
Slave Not Stretching interrupt clear.
11
1
read-write
SLVDESELCLR
Slave Deselect interrupt clear.
15
1
read-write
MONRDYCLR
Monitor data Ready interrupt clear.
16
1
read-write
MONOVCLR
Monitor Overrun interrupt clear.
17
1
read-write
MONIDLECLR
Monitor Idle interrupt clear.
19
1
read-write
EVENTTIMEOUTCLR
Event time-out interrupt clear.
24
1
read-write
SCLTIMEOUTCLR
SCL time-out interrupt clear.
25
1
read-write
TIMEOUT
Time-out value register.
0x10
32
read-write
0xFFFF
0xFFFFFFFF
TOMIN
Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks.
0
4
read-write
TO
Time-out time value. Specifies the time-out interval value in increments of 16 I2C function clocks, as defined by the CLKDIV register. To change this value while I 2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. ... 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock.
4
12
read-write
CLKDIV
Clock pre-divider for the entire I2C block. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function.
0x14
32
read-write
0
0xFFFFFFFF
DIVVAL
This field controls how the clock (PCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = PCLK is used directly by the I2C. 0x0001 = PCLK is divided by 2 before use. 0x0002 = PCLK is divided by 3 before use. ... 0xFFFF = PCLK is divided by 65,536 before use.
0
16
read-write
INTSTAT
Interrupt Status register for Master, Slave, and Monitor functions.
0x18
32
read-write
0
0xFFFFFFFF
MSTPENDING
Master Pending.
0
1
read-write
MSTARBLOSS
Master Arbitration Loss flag.
4
1
read-write
MSTSTSTPERR
Master Start/Stop Error flag.
6
1
read-write
SLVPENDING
Slave Pending.
8
1
read-write
SLVNOTSTR
Slave Not Stretching status.
11
1
read-write
SLVDESEL
Slave Deselected flag.
15
1
read-write
MONRDY
Monitor Ready.
16
1
read-write
MONOV
Monitor Overflow flag.
17
1
read-write
MONIDLE
Monitor Idle flag.
19
1
read-write
EVENTTIMEOUT
Event time-out Interrupt flag.
24
1
read-write
SCLTIMEOUT
SCL time-out Interrupt flag.
25
1
read-write
MSTCTL
Master control register.
0x20
32
read-write
0
0xFFFFFFFF
MSTCONTINUE
Master Continue. This bit is write-only.
0
1
read-write
NO_EFFECT
No effect.
0
CONTINUE
Continue. Informs the Master function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation.
0x1
MSTSTART
Master Start control. This bit is write-only.
1
1
read-write
NO_EFFECT
No effect.
0
START
Start. A Start will be generated on the I2C bus at the next allowed time.
0x1
MSTSTOP
Master Stop control. This bit is write-only.
2
1
read-write
NO_EFFECT
No effect.
0
STOP
Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode).
0x1
MSTDMA
Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write.
3
1
read-write
DISABLE
Disable. No DMA requests are generated for master operation.
0
ENABLE
Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically.
0x1
MSTTIME
Master timing configuration.
0x24
32
read-write
0x77
0xFFFFFFFF
MSTSCLLOW
Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter tLOW in the I2C bus specification. I2C bus specification parameters tBUF and t SU;STA have the same values and are also controlled by MSTSCLLOW.
0
3
read-write
CLOCKS_2
2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.
0
CLOCKS_3
3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.
0x1
CLOCKS_4
4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.
0x2
CLOCKS_5
5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.
0x3
CLOCKS_6
6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.
0x4
CLOCKS_7
7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.
0x5
CLOCKS_8
8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.
0x6
CLOCKS_9
9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.
0x7
MSTSCLHIGH
Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH.
4
3
read-write
CLOCKS_2
2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider.
0
CLOCKS_3
3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .
0x1
CLOCKS_4
4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider.
0x2
CLOCKS_5
5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider.
0x3
CLOCKS_6
6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider.
0x4
CLOCKS_7
7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider.
0x5
CLOCKS_8
8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider.
0x6
CLOCKS_9
9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.
0x7
MSTDAT
Combined Master receiver and transmitter data register.
0x28
32
read-write
0
0
DATA
Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function.
0
8
read-write
SLVCTL
Slave control register.
0x40
32
read-write
0
0xFFFFFFFF
SLVCONTINUE
Slave Continue.
0
1
read-write
NO_EFFECT
No effect.
0
CONTINUE
Continue. Informs the Slave function to continue to the next operation. This must be done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation.
0x1
SLVNACK
Slave NACK.
1
1
read-write
NO_EFFECT
No effect.
0
NACK
NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode).
0x1
SLVDMA
Slave DMA enable.
3
1
read-write
DISABLED
Disabled. No DMA requests are issued for Slave mode operation.
0
ENABLED
Enabled. DMA requests are issued for I2C slave data transmission and reception.
0x1
SLVDAT
Combined Slave receiver and transmitter data register.
0x44
32
read-write
0
0
DATA
Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function.
0
8
read-write
4
0x4
SLVADR[%s]
Slave address 0.
0x48
32
read-write
0x1
0xFFFFFFFF
SADISABLE
Slave Address n Disable.
0
1
read-write
ENABLED
Enabled. Slave Address n is enabled.
0
IGNORED_SLAVE_ADDRES
Ignored Slave Address n is ignored.
0x1
SLVADR
Slave Address. Seven bit slave address that is compared to received addresses if enabled.
1
7
read-write
SLVQUAL0
Slave Qualification for address 0.
0x58
32
read-write
0
0xFFFFFFFF
QUALMODE0
Qualify mode for slave address 0.
0
1
read-write
MASK
Mask. The SLVQUAL0 field is used as a logical mask for matching address 0.
0
EXTEND
Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses.
0x1
SLVQUAL0
Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]).
1
7
read-write
MONRXDAT
Monitor receiver data register.
0x80
32
read-write
0
0xFFFFFFFF
MONRXDAT
Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins.
0
8
read-write
MONSTART
Monitor Received Start.
8
1
read-write
NO_START_DETECTED
No start detected. The monitor function has not detected a Start event on the I2C bus.
0
START_DETECTED
Start detected. The monitor function has detected a Start event on the I2C bus.
0x1
MONRESTART
Monitor Received Repeated Start.
9
1
read-write
NO_REPEATED_START_DE
No repeated start detected. The monitor function has not detected a Repeated Start event on the I2C bus.
0
REPEATED_START_DETEC
Repeated start detected. The monitor function has detected a Repeated Start event on the I2C bus.
0x1
MONNACK
Monitor Received NACK.
10
1
read-write
ACKNOWLEDGED
Acknowledged. The data currently being provided by the monitor function was acknowledged by at least one master or slave receiver.
0
NOT_ACKNOWLEDGED
Not acknowledged. The data currently being provided by the monitor function was not acknowledged by any receiver.
0x1
I2C1
I2C-bus interface 0
I2C
0x40098000
0
0x84
registers
I2C1
22
I2C2
I2C-bus interface 0
I2C
0x4009C000
0
0x84
registers
I2C2
23
SPI0
SPI
SPI
SPI
0x400A4000
0
0x2C
registers
SPI0
24
CFG
SPI Configuration register
0
32
read-write
0
0xFFFFFFFF
ENABLE
SPI enable.
0
1
read-write
DISABLED
Disabled. The SPI is disabled and the internal state machine and counters are reset.
0
ENABLED
Enabled. The SPI is enabled for operation.
0x1
MASTER
Master mode select.
2
1
read-write
SLAVE_MODE
Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output.
0
MASTER_MODE
Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input.
0x1
LSBF
LSB First mode enable.
3
1
read-write
STANDARD
Standard. Data is transmitted and received in standard MSB first order.
0
REVERSE
Reverse. Data is transmitted and received in reverse order (LSB first).
0x1
CPHA
Clock Phase select.
4
1
read-write
CHANGE
Change. The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge.
0
CAPTURE
Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge.
0x1
CPOL
Clock Polarity select.
5
1
read-write
LOW
Low. The rest state of the clock (between transfers) is low.
0
HIGH
High. The rest state of the clock (between transfers) is high.
0x1
LOOP
Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing.
7
1
read-write
DISABLED
Disabled.
0
ENABLED
Enabled.
0x1
SPOL0
SSEL0 Polarity select.
8
1
read-write
LOW
Low. The SSEL0 pin is active low. The value in the SSEL0 fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL0 is not inverted relative to the pins.
0
HIGH
High. The SSEL0 pin is active high. The value in the SSEL0 fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL0 is inverted relative to the pins.
0x1
SPOL1
SSEL1 Polarity select.
9
1
read-write
LOW
Low. The SSEL1 pin is active low. The value in the SSEL1 fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL1 is not inverted relative to the pins.
0
HIGH
High. The SSEL1 pin is active high. The value in the SSEL1 fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL1 is inverted relative to the pins.
0x1
SPOL2
SSEL2 Polarity select.
10
1
read-write
LOW
Low. The SSEL2 pin is active low. The value in the SSEL2 fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL2 is not inverted relative to the pins.
0
HIGH
High. The SSEL2 pin is active high. The value in the SSEL2 fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL2 is inverted relative to the pins.
0x1
SPOL3
SSEL3 Polarity select.
11
1
read-write
LOW
Low. The SSEL3 pin is active low. The value in the SSEL3 fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL3 is not inverted relative to the pins.
0
HIGH
High. The SSEL3 pin is active high. The value in the SSEL3 fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL3 is inverted relative to the pins.
0x1
DLY
SPI Delay register
0x4
32
read-write
0
0xFFFFFFFF
PRE_DELAY
Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. ... 0xF = 15 SPI clock times are inserted.
0
4
read-write
POST_DELAY
Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. ... 0xF = 15 SPI clock times are inserted.
4
4
read-write
FRAME_DELAY
If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. ... 0xF = 15 SPI clock times are inserted.
8
4
read-write
TRANSFER_DELAY
Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. ... 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times.
12
4
read-write
STAT
SPI Status. Some status flags can be cleared by writing a 1 to that bit position
0x8
32
read-write
0x102
0xFFFFFFFF
RXRDY
Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT register.
0
1
read-write
TXRDY
Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT or TXDATCTL until the data is moved to the transmit shift register.
1
1
read-write
RXOV
Receiver Overrun interrupt flag. This flag applies only to slave mode (Master = 0). This flag is set when the beginning of a received character is detected while the receiver buffer is still in use. If this occurs, the receiver buffer contents are preserved, and the incoming data is lost. Data received by the SPI should be considered undefined if RxOv is set.
2
1
read-write
TXUR
Transmitter Underrun interrupt flag. This flag applies only to slave mode (Master = 0). In this case, the transmitter must begin sending new data on the next input clock if the transmitter is idle. If that data is not available in the transmitter holding register at that point, there is no data to transmit and the TXUR flag is set. Data transmitted by the SPI should be considered undefined if TXUR is set.
3
1
read-write
SSA
Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software.
4
1
read-write
SSD
Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software.
5
1
read-write
STALLED
Stalled status flag. This indicates whether the SPI is currently in a stall condition.
6
1
read-write
ENDTRANSFER
End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted.
7
1
read-write
MSTIDLE
Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data.
8
1
read-write
INTENSET
SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
0xC
32
read-write
0
0xFFFFFFFF
RXRDYEN
RX ready interrupt enable. Determines whether an interrupt occurs when receiver data is available.
0
1
read-write
DISABLED
Disabled. No interrupt will be generated when receiver data is available.
0
ENABLED
Enabled. An interrupt will be generated when receiver data is available in the RXDAT register.
0x1
TXRDYEN
TX ready interrupt enable. Determines whether an interrupt occurs when the transmitter holding register is available.
1
1
read-write
DISABLED
Disabled. No interrupt will be generated when the transmitter holding register is available.
0
ENABLED
Enabled. An interrupt will be generated when data may be written to TXDAT.
0x1
RXOVEN
RX overrun interrupt enable. Determines whether an interrupt occurs when a receiver overrun occurs. This happens in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use. The interface prevents receiver overrun in Master mode by not allowing a new transmission to begin when a receiver overrun would otherwise occur.
2
1
read-write
DISABLED
Disabled. No interrupt will be generated when a receiver overrun occurs.
0
ENABLED
Enabled. An interrupt will be generated if a receiver overrun occurs.
0x1
TXUREN
TX underrun interrupt enable. Determines whether an interrupt occurs when a transmitter underrun occurs. This happens in slave mode when there is a need to transmit data when none is available.
3
1
read-write
DISABLED
Disabled. No interrupt will be generated when the transmitter underruns.
0
ENABLED
Enabled. An interrupt will be generated if the transmitter underruns.
0x1
SSAEN
Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted.
4
1
read-write
DISABLED
Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted.
0
ENABLED
Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted.
0x1
SSDEN
Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted.
5
1
read-write
DISABLED
Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted.
0
ENABLED
Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted.
0x1
MSTIDLEEN
Master idle interrupt enable
8
1
read-write
DISABLED
Disabled. No interrupt will be generated when the SPI master function is idle.
0
ENABLED
Enabled. An interrupt will be generated when the SPI master function is idle.
0x1
INTENCLR
SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared.
0x10
32
read-write
0
0
RXRDYEN
Writing 1 clears the corresponding bits in the INTENSET register.
0
1
read-write
TXRDYEN
Writing 1 clears the corresponding bits in the INTENSET register.
1
1
read-write
RXOVEN
Writing 1 clears the corresponding bits in the INTENSET register.
2
1
read-write
TXUREN
Writing 1 clears the corresponding bits in the INTENSET register.
3
1
read-write
SSAEN
Writing 1 clears the corresponding bits in the INTENSET register.
4
1
read-write
SSDEN
Writing 1 clears the corresponding bits in the INTENSET register.
5
1
read-write
MSTIDLE
Writing 1 clears the corresponding bits in the MSTIDLE register.
8
1
read-write
RXDAT
SPI Receive Data
0x14
32
read-write
0
0
RXDAT
Receiver Data. This contains the next piece of received data. The number of bits that are used depends on the LEN setting in TXCTL / TXDATCTL.
0
16
read-write
RXSSEL0_N
Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
16
1
read-write
RXSSEL1_N
Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
17
1
read-write
RXSSEL2_N
Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
18
1
read-write
RXSSEL3_N
Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
19
1
read-write
SOT
Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the transfer length is greater than 16 bit.
20
1
read-write
TXDATCTL
SPI Transmit Data with Control
0x18
32
read-write
0
0xFFFFFFFF
TXDAT
Transmit Data. This field provides from 1 to 16 bits of data to be transmitted.
0
16
read-write
TXSSEL0_N
Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. The active state of the SSEL0 pin is configured by bits in the CFG register.
16
1
read-write
SSEL0_ASSERTED
SSEL0 asserted.
0
SSEL0_NOT_ASSERTED
SSEL0 not asserted.
0x1
TXSSEL1_N
Transmit Slave Select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. The active state of the SSEL1 pin is configured by bits in the CFG register.
17
1
read-write
SSEL1_ASSERTED
SSEL1 asserted.
0
SSEL1_NOT_ASSERTED
SSEL1 not asserted.
0x1
TXSSEL2_N
Transmit Slave Select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. The active state of the SSEL2 pin is configured by bits in the CFG register.
18
1
read-write
SSEL2_ASSERTED
SSEL2 asserted.
0
SSEL2_NOT_ASSERTED
SSEL2 not asserted.
0x1
TXSSEL3_N
Transmit Slave Select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. The active state of the SSEL3 pin is configured by bits in the CFG register.
19
1
read-write
SSEL3_ASSERTED
SSEL3 asserted.
0
SSEL3_NOT_ASSERTED
SSEL3 not asserted.
0x1
EOT
End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain so for at least the time specified by the Transfer_delay value in the DLY register.
20
1
read-write
SSEL_NOT_DEASSERTED
SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.
0
SSEL_DEASSERTED
SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data.
0x1
EOF
End of Frame. Between frames, a delay may be inserted, as defined by the FRAME_DELAY value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for frame lengths greater than 16 bits.
21
1
read-write
DATA_NOT_EOF
Data not EOF. This piece of data transmitted is not treated as the end of a frame.
0
DATA_EOF
Data EOF. This piece of data is treated as the end of a frame, causing the FRAME_DELAY time to be inserted before subsequent data is transmitted.
0x1
RXIGNORE
Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver.Setting this bit simplifies the transmit process and can be used with the DMA.
22
1
read-write
READ_RECEIVED_DATA
Read received data. Received data must be read in order to allow transmission to progress. In slave mode, an overrun error will occur if received data is not read before new data is received.
0
IGNORE_RECEIVED_DATA
Ignore received data. Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated.
0x1
LEN
Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data transfer is 1 bit in length. 0x1 = Data transfer is 2 bits in length. 0x2 = Data transfer is 3 bits in length. ... 0xF = Data transfer is 16 bits in length.
24
4
read-write
TXDAT
SPI Transmit Data
0x1C
32
read-write
0
0xFFFFFFFF
DATA
Transmit Data. This field provides from 4 to 16 bits of data to be transmitted.
0
16
read-write
TXCTL
SPI Transmit Control
0x20
32
read-write
0
0xFFFFFFFF
TXSSEL0_N
Transmit Slave Select 0.
16
1
read-write
TXSSEL1_N
Transmit Slave Select 1.
17
1
read-write
TXSSEL2_N
Transmit Slave Select 2.
18
1
read-write
TXSSEL3_n
Transmit Slave Select 3.
19
1
read-write
EOT
End of Transfer.
20
1
read-write
EOF
End of Frame.
21
1
read-write
RXIGNORE
Receive Ignore.
22
1
read-write
LEN
Data transfer Length.
24
4
read-write
DIV
SPI clock Divider
0x24
32
read-write
0
0xFFFFFFFF
DIVVAL
Rate divider value. Specifies how the PCLK for the SPI is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in PCLK/1, the value 1 results in PCLK/2, up to the maximum possible divide value of 0xFFFF, which results in PCLK/65536.
0
16
read-write
INTSTAT
SPI Interrupt Status
0x28
32
read-write
0
0xFFFFFFFF
RXRDY
Receiver Ready flag.
0
1
read-write
TXRDY
Transmitter Ready flag.
1
1
read-write
RXOV
Receiver Overrun interrupt flag.
2
1
read-write
TXUR
Transmitter Underrun interrupt flag.
3
1
read-write
SSA
Slave Select Assert.
4
1
read-write
SSD
Slave Select Deassert.
5
1
read-write
MSTIDLE
Master Idle status flag.
8
1
read-write
SPI1
SPI
SPI
0x400A8000
0
0x2C
registers
SPI1
25
CTIMER0
LPC5410x Standard counter/timers (CTIMER0 to 4)
CTIMER
CTIMER
0x400B4000
0
0x78
registers
CTIMER0
11
IR
Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending.
0
32
read-write
0
0xFF
MR0INT
Interrupt flag for match channel 0.
0
1
read-write
MR1INT
Interrupt flag for match channel 1.
1
1
read-write
MR2INT
Interrupt flag for match channel 2.
2
1
read-write
MR3INT
Interrupt flag for match channel 3.
3
1
read-write
CR0INT
Interrupt flag for capture channel 0 event.
4
1
read-write
CR1INT
Interrupt flag for capture channel 1 event.
5
1
read-write
CR2INT
Interrupt flag for capture channel 2 event.
6
1
read-write
CR3INT
Interrupt flag for capture channel 3 event.
7
1
read-write
TCR
Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.
0x4
32
read-write
0
0x3
CEN
Counter enable.
0
1
read-write
DISABLED
Disabled.The counters are disabled.
0
ENABLED
Enabled. The Timer Counter and Prescale Counter are enabled.
0x1
CRST
Counter reset.
1
1
read-write
DISABLED
Disabled. Do nothing.
0
ENABLED
Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of the APB bus clock. The counters remain reset until TCR[1] is returned to zero.
0x1
TC
Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR.
0x8
32
read-write
0
0xFFFFFFFF
TCVAL
Timer counter value.
0
32
read-write
PR
Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC.
0xC
32
read-write
0
0xFFFFFFFF
PRVAL
Prescale counter value.
0
32
read-write
PC
Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.
0x10
32
read-write
0
0xFFFFFFFF
PCVAL
Prescale counter value.
0
32
read-write
MCR
Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.
0x14
32
read-write
0
0xFFF
MR0I
Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 = disabled. 1 = enabled.
0
1
read-write
MR0R
Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled.
1
1
read-write
MR0S
Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled.
2
1
read-write
MR1I
Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 = disabled. 1 = enabled. 0 = disabled. 1 = enabled.
3
1
read-write
MR1R
Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled.
4
1
read-write
MR1S
Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled.
5
1
read-write
MR2I
Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled.
6
1
read-write
MR2R
Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled.
7
1
read-write
MR2S
Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled.
8
1
read-write
MR3I
Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled.
9
1
read-write
MR3R
Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled.
10
1
read-write
MR3S
Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled.
11
1
read-write
4
0x4
MR[%s]
Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
0x18
32
read-write
0
0xFFFFFFFF
MATCH
Timer counter match value.
0
32
read-write
CCR
Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.
0x28
32
read-write
0
0xFFF
CAP0RE
Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
0
1
read-write
CAP0FE
Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
1
1
read-write
CAP0I
Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.
2
1
read-write
CAP1RE
Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
3
1
read-write
CAP1FE
Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
4
1
read-write
CAP1I
Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.
5
1
read-write
CAP2RE
Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
6
1
read-write
CAP2FE
Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
7
1
read-write
CAP2I
Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.
8
1
read-write
CAP3RE
Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
9
1
read-write
CAP3FE
Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
10
1
read-write
CAP3I
Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt.
11
1
read-write
4
0x4
CR[%s]
Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.
0x2C
32
read-only
0
0xFFFFFFFF
CAP
Timer counter capture value.
0
32
read-only
EMR
External Match Register. The EMR controls the match function and the external match pins.
0x3C
32
read-write
0
0xFFF
EM0
External Match 0. This bit reflects the state of output MAT0, whether or not this output is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
0
1
read-write
EM1
External Match 1. This bit reflects the state of output MAT1, whether or not this output is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
1
1
read-write
EM2
External Match 2. This bit reflects the state of output MAT2, whether or not this output is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
2
1
read-write
EM3
External Match 3. This bit reflects the state of output MAT3, whether or not this output is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
3
1
read-write
EMC0
External Match Control 0. Determines the functionality of External Match 0.
4
2
read-write
DO_NOTHING
Do Nothing.
0
CLEAR
Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out).
0x1
SET
Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out).
0x2
TOGGLE
Toggle. Toggle the corresponding External Match bit/output.
0x3
EMC1
External Match Control 1. Determines the functionality of External Match 1.
6
2
read-write
DO_NOTHING
Do Nothing.
0
CLEAR
Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out).
0x1
SET
Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out).
0x2
TOGGLE
Toggle. Toggle the corresponding External Match bit/output.
0x3
EMC2
External Match Control 2. Determines the functionality of External Match 2.
8
2
read-write
DO_NOTHING
Do Nothing.
0
CLEAR
Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out).
0x1
SET
Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out).
0x2
TOGGLE
Toggle. Toggle the corresponding External Match bit/output.
0x3
EMC3
External Match Control 3. Determines the functionality of External Match 3.
10
2
read-write
DO_NOTHING
Do Nothing.
0
CLEAR
Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out).
0x1
SET
Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out).
0x2
TOGGLE
Toggle. Toggle the corresponding External Match bit/output.
0x3
CTCR
Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.
0x70
32
read-write
0
0xFF
CTMODE
Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.
0
2
read-write
TIMER
Timer Mode. Incremented every rising APB bus clock edge.
0
COUNTER_RISING_EDGE
Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2.
0x1
COUNTER_FALLING_EDGE
Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2.
0x2
COUNTER_DUAL_EDGE
Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2.
0x3
CINSEL
Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.
2
2
read-write
CHANNEL_0
Channel 0. CAPn.0 for CTIMERn
0
CHANNEL_1
Channel 1. CAPn.1 for CTIMERn
0x1
CHANNEL_2
Channel 2. CAPn.2 for CTIMERn
0x2
CHANNEL_3
Channel 3. CAPn.3 for CTIMERn
0x3
ENCC
Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs.
4
1
read-write
SELCC
Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved.
5
3
read-write
CHANNEL_0_RISING
Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
0
CHANNEL_0_FALLING
Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
0x1
CHANNEL_1_RISING
Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
0x2
CHANNEL_1_FALLING
Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
0x3
CHANNEL_2_RISING
Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
0x4
CHANNEL_2_FALLING
Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
0x5
PWMC
PWM Control Register. The PWMCON enables PWM mode for the external match pins.
0x74
32
read-write
0
0xF
PWMEN0
PWM mode enable for channel0.
0
1
read-write
MATCH
Match. CTIMERn_MAT0 is controlled by EM0.
0
PWM
PWM. PWM mode is enabled for CTIMERn_MAT0.
0x1
PWMEN1
PWM mode enable for channel1.
1
1
read-write
MATCH
Match. CTIMERn_MAT01 is controlled by EM1.
0
PWM
PWM. PWM mode is enabled for CTIMERn_MAT1.
0x1
PWMEN2
PWM mode enable for channel2.
2
1
read-write
MATCH
Match. CTIMERn_MAT2 is controlled by EM2.
0
PWM
PWM. PWM mode is enabled for CTIMERn_MAT2.
0x1
PWMEN3
PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.
3
1
read-write
MATCH
Match. CTIMERn_MAT3 is controlled by EM3.
0
PWM
PWM. PWM mode is enabled for CT132Bn_MAT3.
0x1
CTIMER2
LPC5410x Standard counter/timers (CTIMER0 to 4)
CTIMER
0x40004000
0
0x78
registers
CTIMER2
13
CTIMER3
LPC5410x Standard counter/timers (CTIMER0 to 4)
CTIMER
0x40008000
0
0x78
registers
CTIMER3
14
CTIMER4
LPC5410x Standard counter/timers (CTIMER0 to 4)
CTIMER
0x4000C000
0
0x78
registers
CTIMER4
15
CTIMER1
LPC5410x Standard counter/timers (CTIMER0 to 4)
CTIMER
0x400B8000
0
0x78
registers
CTIMER1
12
ITM
Instrumentation Trace Macrocell Registers
ITM
ITM_
0xE0000000
0
0x1000
registers
STIM0_READ
Stimulus Port Register 0 (for reading)
STIM0_READ_STIM0_WRITE
0
32
read-write
0
0xFFFFFFFE
FIFOREADY
no description available
0
1
read-write
STIM0_WRITE
Stimulus Port Register 0 (for writing)
STIM0_READ_STIM0_WRITE
0
32
read-write
0
0
STIMULUS
Data write to the stimulus port FIFO, for forwarding as a software event packet.
0
32
read-write
STIM1_READ
Stimulus Port Register 1 (for reading)
STIM1_READ_STIM1_WRITE
0x4
32
read-write
0
0xFFFFFFFE
FIFOREADY
no description available
0
1
read-write
STIM1_WRITE
Stimulus Port Register 1 (for writing)
STIM1_READ_STIM1_WRITE
0x4
32
read-write
0
0
STIMULUS
Data write to the stimulus port FIFO, for forwarding as a software event packet.
0
32
read-write
STIM2_READ
Stimulus Port Register 2 (for reading)
STIM2_READ_STIM2_WRITE
0x8
32
read-write
0
0xFFFFFFFE
FIFOREADY
no description available
0
1
read-write
STIM2_WRITE
Stimulus Port Register 2 (for writing)
STIM2_READ_STIM2_WRITE
0x8
32
read-write
0
0
STIMULUS
Data write to the stimulus port FIFO, for forwarding as a software event packet.
0
32
read-write
STIM3_READ
Stimulus Port Register 3 (for reading)
STIM3_READ_STIM3_WRITE
0xC
32
read-write
0
0xFFFFFFFE
FIFOREADY
no description available
0
1
read-write
STIM3_WRITE
Stimulus Port Register 3 (for writing)
STIM3_READ_STIM3_WRITE
0xC
32
read-write
0
0
STIMULUS
Data write to the stimulus port FIFO, for forwarding as a software event packet.
0
32
read-write
STIM4_READ
Stimulus Port Register 4 (for reading)
STIM4_READ_STIM4_WRITE
0x10
32
read-write
0
0xFFFFFFFE
FIFOREADY
no description available
0
1
read-write
STIM4_WRITE
Stimulus Port Register 4 (for writing)
STIM4_READ_STIM4_WRITE
0x10
32
read-write
0
0
STIMULUS
Data write to the stimulus port FIFO, for forwarding as a software event packet.
0
32
read-write
STIM5_READ
Stimulus Port Register 5 (for reading)
STIM5_READ_STIM5_WRITE
0x14
32
read-write
0
0xFFFFFFFE
FIFOREADY
no description available
0
1
read-write
STIM5_WRITE
Stimulus Port Register 5 (for writing)
STIM5_READ_STIM5_WRITE
0x14
32
read-write
0
0
STIMULUS
Data write to the stimulus port FIFO, for forwarding as a software event packet.
0
32
read-write
STIM6_READ
Stimulus Port Register 6 (for reading)
STIM6_READ_STIM6_WRITE
0x18
32
read-write
0
0xFFFFFFFE
FIFOREADY
no description available
0
1
read-write
STIM6_WRITE
Stimulus Port Register 6 (for writing)
STIM6_READ_STIM6_WRITE
0x18
32
read-write
0
0
STIMULUS
Data write to the stimulus port FIFO, for forwarding as a software event packet.
0
32
read-write
STIM7_READ
Stimulus Port Register 7 (for reading)
STIM7_READ_STIM7_WRITE
0x1C
32
read-write
0
0xFFFFFFFE
FIFOREADY
no description available
0
1
read-write
STIM7_WRITE
Stimulus Port Register 7 (for writing)
STIM7_READ_STIM7_WRITE
0x1C
32
read-write
0
0
STIMULUS
Data write to the stimulus port FIFO, for forwarding as a software event packet.
0
32
read-write
STIM8_READ
Stimulus Port Register 8 (for reading)
STIM8_READ_STIM8_WRITE
0x20
32
read-write
0
0xFFFFFFFE
FIFOREADY
no description available
0
1
read-write
STIM8_WRITE
Stimulus Port Register 8 (for writing)
STIM8_READ_STIM8_WRITE
0x20
32
read-write
0
0
STIMULUS
Data write to the stimulus port FIFO, for forwarding as a software event packet.
0
32
read-write
STIM9_READ
Stimulus Port Register 9 (for reading)
STIM9_READ_STIM9_WRITE
0x24
32
read-write
0
0xFFFFFFFE
FIFOREADY
no description available
0
1
read-write
STIM9_WRITE
Stimulus Port Register 9 (for writing)
STIM9_READ_STIM9_WRITE
0x24
32
read-write
0
0
STIMULUS
Data write to the stimulus port FIFO, for forwarding as a software event packet.
0
32
read-write
STIM10_READ
Stimulus Port Register 10 (for reading)
STIM10_READ_STIM10_WRITE
0x28
32
read-write
0
0xFFFFFFFE
FIFOREADY
no description available
0
1
read-write
STIM10_WRITE
Stimulus Port Register 10 (for writing)
STIM10_READ_STIM10_WRITE
0x28
32
read-write
0
0
STIMULUS
Data write to the stimulus port FIFO, for forwarding as a software event packet.
0
32
read-write
STIM11_READ
Stimulus Port Register 11 (for reading)
STIM11_READ_STIM11_WRITE
0x2C
32
read-write
0
0xFFFFFFFE
FIFOREADY
no description available
0
1
read-write
STIM11_WRITE
Stimulus Port Register 11 (for writing)
STIM11_READ_STIM11_WRITE
0x2C
32
read-write
0
0
STIMULUS
Data write to the stimulus port FIFO, for forwarding as a software event packet.
0
32
read-write
STIM12_READ
Stimulus Port Register 12 (for reading)
STIM12_READ_STIM12_WRITE
0x30
32
read-write
0
0xFFFFFFFE
FIFOREADY
no description available
0
1
read-write
STIM12_WRITE
Stimulus Port Register 12 (for writing)
STIM12_READ_STIM12_WRITE
0x30
32
read-write
0
0
STIMULUS
Data write to the stimulus port FIFO, for forwarding as a software event packet.
0
32
read-write
STIM13_READ
Stimulus Port Register 13 (for reading)
STIM13_READ_STIM13_WRITE
0x34
32
read-write
0
0xFFFFFFFE
FIFOREADY
no description available
0
1
read-write
STIM13_WRITE
Stimulus Port Register 13 (for writing)
STIM13_READ_STIM13_WRITE
0x34
32
read-write
0
0
STIMULUS
Data write to the stimulus port FIFO, for forwarding as a software event packet.
0
32
read-write
STIM14_READ
Stimulus Port Register 14 (for reading)
STIM14_READ_STIM14_WRITE
0x38
32
read-write
0
0xFFFFFFFE
FIFOREADY
no description available
0
1
read-write
STIM14_WRITE
Stimulus Port Register 14 (for writing)
STIM14_READ_STIM14_WRITE
0x38
32
read-write
0
0
STIMULUS
Data write to the stimulus port FIFO, for forwarding as a software event packet.
0
32
read-write
STIM15_READ
Stimulus Port Register 15 (for reading)
STIM15_READ_STIM15_WRITE
0x3C
32
read-write
0
0xFFFFFFFE
FIFOREADY
no description available
0
1
read-write
STIM15_WRITE
Stimulus Port Register 15 (for writing)
STIM15_READ_STIM15_WRITE
0x3C
32
read-write
0
0
STIMULUS
Data write to the stimulus port FIFO, for forwarding as a software event packet.
0
32
read-write
STIM16_READ
Stimulus Port Register 16 (for reading)
STIM16_READ_STIM16_WRITE
0x40
32
read-write
0
0xFFFFFFFE
FIFOREADY
no description available
0
1
read-write
STIM16_WRITE
Stimulus Port Register 16 (for writing)
STIM16_READ_STIM16_WRITE
0x40
32
read-write
0
0
STIMULUS
Data write to the stimulus port FIFO, for forwarding as a software event packet.
0
32
read-write
STIM17_READ
Stimulus Port Register 17 (for reading)
STIM17_READ_STIM17_WRITE
0x44
32
read-write
0
0xFFFFFFFE
FIFOREADY
no description available
0
1
read-write
STIM17_WRITE
Stimulus Port Register 17 (for writing)
STIM17_READ_STIM17_WRITE
0x44
32
read-write
0
0
STIMULUS
Data write to the stimulus port FIFO, for forwarding as a software event packet.
0
32
read-write
STIM18_READ
Stimulus Port Register 18 (for reading)
STIM18_READ_STIM18_WRITE
0x48
32
read-write
0
0xFFFFFFFE
FIFOREADY
no description available
0
1
read-write
STIM18_WRITE
Stimulus Port Register 18 (for writing)
STIM18_READ_STIM18_WRITE
0x48
32
read-write
0
0
STIMULUS
Data write to the stimulus port FIFO, for forwarding as a software event packet.
0
32
read-write
STIM19_READ
Stimulus Port Register 19 (for reading)
STIM19_READ_STIM19_WRITE
0x4C
32
read-write
0
0xFFFFFFFE
FIFOREADY
no description available
0
1
read-write
STIM19_WRITE
Stimulus Port Register 19 (for writing)
STIM19_READ_STIM19_WRITE
0x4C
32
read-write
0
0
STIMULUS
Data write to the stimulus port FIFO, for forwarding as a software event packet.
0
32
read-write
STIM20_READ
Stimulus Port Register 20 (for reading)
STIM20_READ_STIM20_WRITE
0x50
32
read-write
0
0xFFFFFFFE
FIFOREADY
no description available
0
1
read-write
STIM20_WRITE
Stimulus Port Register 20 (for writing)
STIM20_READ_STIM20_WRITE
0x50
32
read-write
0
0
STIMULUS
Data write to the stimulus port FIFO, for forwarding as a software event packet.
0
32
read-write
STIM21_READ
Stimulus Port Register 21 (for reading)
STIM21_READ_STIM21_WRITE
0x54
32
read-write
0
0xFFFFFFFE
FIFOREADY
no description available
0
1
read-write
STIM21_WRITE
Stimulus Port Register 21 (for writing)
STIM21_READ_STIM21_WRITE
0x54
32
read-write
0
0
STIMULUS
Data write to the stimulus port FIFO, for forwarding as a software event packet.
0
32
read-write
STIM22_READ
Stimulus Port Register 22 (for reading)
STIM22_READ_STIM22_WRITE
0x58
32
read-write
0
0xFFFFFFFE
FIFOREADY
no description available
0
1
read-write
STIM22_WRITE
Stimulus Port Register 22 (for writing)
STIM22_READ_STIM22_WRITE
0x58
32
read-write
0
0
STIMULUS
Data write to the stimulus port FIFO, for forwarding as a software event packet.
0
32
read-write
STIM23_READ
Stimulus Port Register 23 (for reading)
STIM23_READ_STIM23_WRITE
0x5C
32
read-write
0
0xFFFFFFFE
FIFOREADY
no description available
0
1
read-write
STIM23_WRITE
Stimulus Port Register 23 (for writing)
STIM23_READ_STIM23_WRITE
0x5C
32
read-write
0
0
STIMULUS
Data write to the stimulus port FIFO, for forwarding as a software event packet.
0
32
read-write
STIM24_READ
Stimulus Port Register 24 (for reading)
STIM24_READ_STIM24_WRITE
0x60
32
read-write
0
0xFFFFFFFE
FIFOREADY
no description available
0
1
read-write
STIM24_WRITE
Stimulus Port Register 24 (for writing)
STIM24_READ_STIM24_WRITE
0x60
32
read-write
0
0
STIMULUS
Data write to the stimulus port FIFO, for forwarding as a software event packet.
0
32
read-write
STIM25_READ
Stimulus Port Register 25 (for reading)
STIM25_READ_STIM25_WRITE
0x64
32
read-write
0
0xFFFFFFFE
FIFOREADY
no description available
0
1
read-write
STIM25_WRITE
Stimulus Port Register 25 (for writing)
STIM25_READ_STIM25_WRITE
0x64
32
read-write
0
0
STIMULUS
Data write to the stimulus port FIFO, for forwarding as a software event packet.
0
32
read-write
STIM26_READ
Stimulus Port Register 26 (for reading)
STIM26_READ_STIM26_WRITE
0x68
32
read-write
0
0xFFFFFFFE
FIFOREADY
no description available
0
1
read-write
STIM26_WRITE
Stimulus Port Register 26 (for writing)
STIM26_READ_STIM26_WRITE
0x68
32
read-write
0
0
STIMULUS
Data write to the stimulus port FIFO, for forwarding as a software event packet.
0
32
read-write
STIM27_READ
Stimulus Port Register 27 (for reading)
STIM27_READ_STIM27_WRITE
0x6C
32
read-write
0
0xFFFFFFFE
FIFOREADY
no description available
0
1
read-write
STIM27_WRITE
Stimulus Port Register 27 (for writing)
STIM27_READ_STIM27_WRITE
0x6C
32
read-write
0
0
STIMULUS
Data write to the stimulus port FIFO, for forwarding as a software event packet.
0
32
read-write
STIM28_READ
Stimulus Port Register 28 (for reading)
STIM28_READ_STIM28_WRITE
0x70
32
read-write
0
0xFFFFFFFE
FIFOREADY
no description available
0
1
read-write
STIM28_WRITE
Stimulus Port Register 28 (for writing)
STIM28_READ_STIM28_WRITE
0x70
32
read-write
0
0
STIMULUS
Data write to the stimulus port FIFO, for forwarding as a software event packet.
0
32
read-write
STIM29_READ
Stimulus Port Register 29 (for reading)
STIM29_READ_STIM29_WRITE
0x74
32
read-write
0
0xFFFFFFFE
FIFOREADY
no description available
0
1
read-write
STIM29_WRITE
Stimulus Port Register 29 (for writing)
STIM29_READ_STIM29_WRITE
0x74
32
read-write
0
0
STIMULUS
Data write to the stimulus port FIFO, for forwarding as a software event packet.
0
32
read-write
STIM30_READ
Stimulus Port Register 30 (for reading)
STIM30_READ_STIM30_WRITE
0x78
32
read-write
0
0xFFFFFFFE
FIFOREADY
no description available
0
1
read-write
STIM30_WRITE
Stimulus Port Register 30 (for writing)
STIM30_READ_STIM30_WRITE
0x78
32
read-write
0
0
STIMULUS
Data write to the stimulus port FIFO, for forwarding as a software event packet.
0
32
read-write
STIM31_READ
Stimulus Port Register 31 (for reading)
STIM31_READ_STIM31_WRITE
0x7C
32
read-write
0
0xFFFFFFFE
FIFOREADY
no description available
0
1
read-write
STIM31_WRITE
Stimulus Port Register 31 (for writing)
STIM31_READ_STIM31_WRITE
0x7C
32
read-write
0
0
STIMULUS
Data write to the stimulus port FIFO, for forwarding as a software event packet.
0
32
read-write
TER
Trace Enable Register
0xE00
32
read-write
0
0xFFFFFFFF
STIMENA
For bit STIMENA[n], in register ITM_TERx: 0 = Stimulus port (32x + n) disabled 1 = Stimulus port (32x + n) enabled
0
32
read-write
TPR
Trace Privilege Register
0xE40
32
read-write
0
0xFFFFFFFF
PRIVMASK
Bit mask to enable tracing on ITM stimulus ports: Bit [0] = stimulus port [7:0] Bit [1] = stimulus port [15:8] Bit [2] = stimulus port [23:16] Bit [3] = stimulus port [31:24]
0
4
read-write
TCR
Trace Control Register
0xE80
32
read-write
0
0xFFFFFFFF
ITMENA
no description available
0
1
read-write
ITMENA_0
Disabled.
0
ITMENA_1
Enabled.
0x1
TSENA
no description available
1
1
read-write
TSENA_0
Disabled.
0
TSENA_1
Enabled.
0x1
SYNCENA
no description available
2
1
read-write
SYNCENA_0
Disabled.
0
SYNCENA_1
Enabled.
0x1
TXENA
no description available
3
1
read-write
TXENA_0
Disabled.
0
TXENA_1
Enabled.
0x1
SWOENA
no description available
4
1
read-write
SWOENA_0
Timestamp counter uses the processor system clock.
0
SWOENA_1
Timestamp counter uses asynchronous clock from the TPIU interface.
0x1
TSPrescale
Local timestamp prescaler, used with the trace packet reference clock.
8
2
read-write
TSPrescale_0
No prescaling.
0
TSPrescale_1
Divide by 4.
0x1
TSPrescale_2
Divide by 16.
0x2
TSPrescale_3
Divide by 64.
0x3
GTSFREQ
Global timestamp frequency. Defines how often the ITM generates a global timestamp, based on the global timestamp clock frequency, or disables generation of global timestamps.
10
2
read-write
GTSFREQ_0
Disable generation of global timestamps.
0
GTSFREQ_1
Generate timestamp request whenever the ITM detects a change in global timestamp counter bits [47:7]. This is approximately every 128 cycles.
0x1
GTSFREQ_2
Generate timestamp request whenever the ITM detects a change in global timestamp counter bits [47:13]. This is approximately every 8192 cycles.
0x2
GTSFREQ_3
Generate a timestamp after every packet, if the output FIFO is empty.
0x3
TraceBusID
Identifier for multi-source trace stream formatting. If multi-source trace is in use, the debugger must write a non-zero value to this field.
16
7
read-write
BUSY
Indicates whether the ITM is currently processing events: 0: ITM is not processing any events. 1: ITM events present and being drained.
23
1
read-only
BUSY_0
ITM is not processing any events.
0
BUSY_1
ITM events present and beeing drained.
0x1
LAR
Lock Access Register
0xFB0
32
read-write
0
0
WriteAccessCode
Write Access Code. A write of 0xC5ACCE55 enables further write access to this device. An invalid write will have the affect of removing write access.
0
32
read-write
LSR
Lock Status Register
0xFB4
32
read-only
0x1
0xFFFFFFFD
IMP
Lock mechanism is implemented. This bit always reads 1.
0
1
read-only
STATUS
Lock Status. This bit is HIGH when the device is locked, and LOW when unlocked.
1
1
read-only
s8BIT
Access Lock Register size. This bit reads 0 to indicate a 32-bit register is present.
2
1
read-only
PID4
Peripheral Identification Register 4.
0xFD0
32
read-only
0x4
0xFFFFFFFF
JEP106
JEP106 continuation code.
0
4
read-only
c4KB
4KB Count
4
4
read-only
PID5
Peripheral Identification Register 5.
0xFD4
32
read-only
0
0xFFFFFFFF
PID6
Peripheral Identification Register 6.
0xFD8
32
read-only
0
0xFFFFFFFF
PID7
Peripheral Identification Register 7.
0xFDC
32
read-only
0
0xFFFFFFFF
PID0
Peripheral Identification Register 0.
0xFE0
32
read-only
0x2
0xFFFFFFFF
PartNumber
Part Number [7:0]
0
8
read-only
PID1
Peripheral Identification Register 1.
0xFE4
32
read-only
0xB0
0xFFFFFFFF
PartNumber
Part Number [11:8]
0
4
read-only
JEP106_identity_code
JEP106 identity code [3:0]
4
4
read-only
PID2
Peripheral Identification Register 2.
0xFE8
32
read-only
0x3B
0xFFFFFFFF
JEP106_identity_code
JEP106 identity code [6:4]
0
3
read-only
Revision
Revision
4
4
read-only
PID3
Peripheral Identification Register 3.
0xFEC
32
read-only
0
0xFFFFFFFF
CustomerModified
Customer Modified.
0
4
read-only
RevAnd
RevAnd
4
4
read-only
CID0
Component Identification Register 0.
0xFF0
32
read-only
0xD
0xFFFFFFFF
Preamble
Preamble
0
8
read-only
CID1
Component Identification Register 1.
0xFF4
32
read-only
0xE0
0xFFFFFFFF
Preamble
Preamble
0
4
read-only
ComponentClass
Component class
4
4
read-only
ComponentClass_1
ROM table.
0x1
ComponentClass_9
CoreSight component.
0x9
ComponentClass_15
PrimeCell of system component with no standardized register layout, for backward compatibility.
0xF
CID2
Component Identification Register 2.
0xFF8
32
read-only
0x5
0xFFFFFFFF
Preamble
Preamble
0
8
read-only
CID3
Component Identification Register 3.
0xFFC
32
read-only
0xB1
0xFFFFFFFF
Preamble
Preamble
0
8
read-only
SystemControl
System Control Block
SCB
SCB_
0xE000E000
0
0xD40
registers
ACTLR
Auxiliary Control Register,
0x8
32
read-write
0
0xFFFFFFFF
DISMCYCINT
Disables interruption of multi-cycle instructions.
0
1
read-write
DISDEFWBUF
Disables write buffer use during default memory map accesses.
1
1
read-write
DISFOLD
Disables folding of IT instructions.
2
1
read-write
CPUID
CPUID Base Register
0xD00
32
read-only
0x410FC240
0xFFFFFFFF
REVISION
Indicates patch release: 0x0 = Patch 0
0
4
read-only
PARTNO
Indicates part number
4
12
read-only
VARIANT
Indicates processor revision: 0x2 = Revision 2
20
4
read-only
IMPLEMENTER
Implementer code
24
8
read-only
ICSR
Interrupt Control and State Register
0xD04
32
read-write
0
0xFFFFFFFF
VECTACTIVE
Active exception number
0
9
read-only
RETTOBASE
no description available
11
1
read-only
RETTOBASE_0
there are preempted active exceptions to execute
0
RETTOBASE_1
there are no active exceptions, or the currently-executing exception is the only active exception
0x1
VECTPENDING
Exception number of the highest priority pending enabled exception
12
6
read-only
ISRPENDING
no description available
22
1
read-only
ISRPREEMPT
no description available
23
1
read-only
ISRPREEMPT_0
Will not service
0
ISRPREEMPT_1
Will service a pending exception
0x1
PENDSTCLR
no description available
25
1
write-only
PENDSTCLR_0
no effect
0
PENDSTCLR_1
removes the pending state from the SysTick exception
0x1
PENDSTSET
no description available
26
1
read-write
PENDSTSET_0
write: no effect; read: SysTick exception is not pending
0
PENDSTSET_1
write: changes SysTick exception state to pending; read: SysTick exception is pending
0x1
PENDSVCLR
no description available
27
1
write-only
PENDSVCLR_0
no effect
0
PENDSVCLR_1
removes the pending state from the PendSV exception
0x1
PENDSVSET
no description available
28
1
read-write
PENDSVSET_0
write: no effect; read: PendSV exception is not pending
0
PENDSVSET_1
write: changes PendSV exception state to pending; read: PendSV exception is pending
0x1
NMIPENDSET
no description available
31
1
read-write
NMIPENDSET_0
write: no effect; read: NMI exception is not pending
0
NMIPENDSET_1
write: changes NMI exception state to pending; read: NMI exception is pending
0x1
VTOR
Vector Table Offset Register
0xD08
32
read-write
0
0xFFFFFFFF
TBLOFF
Vector table base offset
7
25
read-write
AIRCR
Application Interrupt and Reset Control Register
0xD0C
32
read-write
0xFA050000
0xFFFFFFFF
VECTRESET
no description available
0
1
write-only
VECTCLRACTIVE
no description available
1
1
write-only
SYSRESETREQ
no description available
2
1
write-only
SYSRESETREQ_0
no system reset request
0
SYSRESETREQ_1
asserts a signal to the outer system that requests a reset
0x1
PRIGROUP
Interrupt priority grouping field. This field determines the split of group priority from subpriority.
8
3
read-write
ENDIANNESS
no description available
15
1
read-only
ENDIANNESS_0
Little-endian
0
ENDIANNESS_1
Big-endian
0x1
VECTKEY
Register key
16
16
read-write
SCR
System Control Register
0xD10
32
read-write
0
0xFFFFFFFF
SLEEPONEXIT
no description available
1
1
read-write
SLEEPONEXIT_0
o not sleep when returning to Thread mode
0
SLEEPONEXIT_1
enter sleep, or deep sleep, on return from an ISR
0x1
SLEEPDEEP
no description available
2
1
read-write
SLEEPDEEP_0
sleep
0
SLEEPDEEP_1
deep sleep
0x1
SEVONPEND
no description available
4
1
read-write
SEVONPEND_0
only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded
0
SEVONPEND_1
enabled events and all interrupts, including disabled interrupts, can wakeup the processor
0x1
CCR
Configuration and Control Register
0xD14
32
read-write
0
0xFFFFFFFF
NONBASETHRDENA
no description available
0
1
read-write
NONBASETHRDENA_0
processor can enter Thread mode only when no exception is active
0
NONBASETHRDENA_1
processor can enter Thread mode from any level under the control of an EXC_RETURN value
0x1
USERSETMPEND
Enables unprivileged software access to the STIR
1
1
read-write
USERSETMPEND_0
disable
0
USERSETMPEND_1
enable
0x1
UNALIGN_TRP
Enables unaligned access traps
3
1
read-write
UNALIGN_TRP_0
do not trap unaligned halfword and word accesses
0
UNALIGN_TRP_1
trap unaligned halfword and word accesses
0x1
DIV_0_TRP
Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0
4
1
read-write
DIV_0_TRP_0
do not trap divide by 0
0
DIV_0_TRP_1
trap divide by 0
0x1
BFHFNMIGN
Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions.
8
1
read-write
BFHFNMIGN_0
data bus faults caused by load and store instructions cause a lock-up
0
BFHFNMIGN_1
handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions
0x1
STKALIGN
Indicates stack alignment on exception entry
9
1
read-write
STKALIGN_0
4-byte aligned
0
STKALIGN_1
8-byte aligned
0x1
SHPR1
System Handler Priority Register 1
0xD18
32
read-write
0
0xFFFFFFFF
PRI_4
Priority of system handler 4, MemManage
0
8
read-write
PRI_5
Priority of system handler 5, BusFault
8
8
read-write
PRI_6
Priority of system handler 6, UsageFault
16
8
read-write
SHPR2
System Handler Priority Register 2
0xD1C
32
read-write
0
0xFFFFFFFF
PRI_11
Priority of system handler 11, SVCall
24
8
read-write
SHPR3
System Handler Priority Register 3
0xD20
32
read-write
0
0xFFFFFFFF
PRI_14
Priority of system handler 14, PendSV
16
8
read-write
PRI_15
Priority of system handler 15, SysTick exception
24
8
read-write
SHCSR
System Handler Control and State Register
0xD24
32
read-write
0
0xFFFFFFFF
MEMFAULTACT
no description available
0
1
read-write
MEMFAULTACT_0
exception is not active
0
MEMFAULTACT_1
exception is active
0x1
BUSFAULTACT
no description available
1
1
read-write
BUSFAULTACT_0
exception is not active
0
BUSFAULTACT_1
exception is active
0x1
USGFAULTACT
no description available
3
1
read-write
USGFAULTACT_0
exception is not active
0
USGFAULTACT_1
exception is active
0x1
SVCALLACT
no description available
7
1
read-write
SVCALLACT_0
exception is not active
0
SVCALLACT_1
exception is active
0x1
MONITORACT
no description available
8
1
read-write
MONITORACT_0
exception is not active
0
MONITORACT_1
exception is active
0x1
PENDSVACT
no description available
10
1
read-write
PENDSVACT_0
exception is not active
0
PENDSVACT_1
exception is active
0x1
SYSTICKACT
no description available
11
1
read-write
SYSTICKACT_0
exception is not active
0
SYSTICKACT_1
exception is active
0x1
USGFAULTPENDED
no description available
12
1
read-write
USGFAULTPENDED_0
exception is not pending
0
USGFAULTPENDED_1
exception is pending
0x1
MEMFAULTPENDED
no description available
13
1
read-write
MEMFAULTPENDED_0
exception is not pending
0
MEMFAULTPENDED_1
exception is pending
0x1
BUSFAULTPENDED
no description available
14
1
read-write
BUSFAULTPENDED_0
exception is not pending
0
BUSFAULTPENDED_1
exception is pending
0x1
SVCALLPENDED
no description available
15
1
read-write
SVCALLPENDED_0
exception is not pending
0
SVCALLPENDED_1
exception is pending
0x1
MEMFAULTENA
no description available
16
1
read-write
MEMFAULTENA_0
disable the exception
0
MEMFAULTENA_1
enable the exception
0x1
BUSFAULTENA
no description available
17
1
read-write
BUSFAULTENA_0
disable the exception
0
BUSFAULTENA_1
enable the exception
0x1
USGFAULTENA
no description available
18
1
read-write
USGFAULTENA_0
disable the exception
0
USGFAULTENA_1
enable the exception
0x1
CFSR
Configurable Fault Status Registers
0xD28
32
read-write
0
0xFFFFFFFF
IACCVIOL
no description available
0
1
read-write
IACCVIOL_0
no instruction access violation fault
0
IACCVIOL_1
the processor attempted an instruction fetch from a location that does not permit execution
0x1
DACCVIOL
no description available
1
1
read-write
DACCVIOL_0
no data access violation fault
0
DACCVIOL_1
the processor attempted a load or store at a location that does not permit the operation
0x1
MUNSTKERR
no description available
3
1
read-write
MUNSTKERR_0
no unstacking fault
0
MUNSTKERR_1
unstack for an exception return has caused one or more access violations
0x1
MSTKERR
no description available
4
1
read-write
MSTKERR_0
no stacking fault
0
MSTKERR_1
stacking for an exception entry has caused one or more access violations
0x1
MLSPERR
no description available
5
1
read-write
MLSPERR_0
No MemManage fault occurred during floating-point lazy state preservation
0
MLSPERR_1
A MemManage fault occurred during floating-point lazy state preservation
0x1
MMARVALID
no description available
7
1
read-write
MMARVALID_0
value in MMAR is not a valid fault address
0
MMARVALID_1
MMAR holds a valid fault address
0x1
IBUSERR
no description available
8
1
read-write
IBUSERR_0
no instruction bus error
0
IBUSERR_1
instruction bus error
0x1
PRECISERR
no description available
9
1
read-write
PRECISERR_0
no precise data bus error
0
PRECISERR_1
a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault
0x1
IMPRECISERR
no description available
10
1
read-write
IMPRECISERR_0
no imprecise data bus error
0
IMPRECISERR_1
a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error
0x1
UNSTKERR
no description available
11
1
read-write
UNSTKERR_0
no unstacking fault
0
UNSTKERR_1
unstack for an exception return has caused one or more BusFaults
0x1
STKERR
no description available
12
1
read-write
STKERR_0
no stacking fault
0
STKERR_1
stacking for an exception entry has caused one or more BusFaults
0x1
LSPERR
no description available
13
1
read-write
LSPERR_0
No bus fault occurred during floating-point lazy state preservation
0
LSPERR_1
A bus fault occurred during floating-point lazy state preservation
0x1
BFARVALID
no description available
15
1
read-write
BFARVALID_0
value in BFAR is not a valid fault address
0
BFARVALID_1
BFAR holds a valid fault address
0x1
UNDEFINSTR
no description available
16
1
read-write
UNDEFINSTR_0
no undefined instruction UsageFault
0
UNDEFINSTR_1
the processor has attempted to execute an undefined instruction
0x1
INVSTATE
no description available
17
1
read-write
INVSTATE_0
no invalid state UsageFault
0
INVSTATE_1
the processor has attempted to execute an instruction that makes illegal use of the EPSR
0x1
INVPC
no description available
18
1
read-write
INVPC_0
no invalid PC load UsageFault
0
INVPC_1
the processor has attempted an illegal load of EXC_RETURN to the PC
0x1
NOCP
no description available
19
1
read-write
NOCP_0
no UsageFault caused by attempting to access a coprocessor
0
NOCP_1
the processor has attempted to access a coprocessor
0x1
UNALIGNED
no description available
24
1
read-write
UNALIGNED_0
no unaligned access fault, or unaligned access trapping not enabled
0
UNALIGNED_1
the processor has made an unaligned memory access
0x1
DIVBYZERO
no description available
25
1
read-write
DIVBYZERO_0
no divide by zero fault, or divide by zero trapping not enabled
0
DIVBYZERO_1
the processor has executed an SDIV or UDIV instruction with a divisor of 0
0x1
HFSR
HardFault Status register
0xD2C
32
read-write
0
0xFFFFFFFF
VECTTBL
no description available
1
1
read-write
VECTTBL_0
no BusFault on vector table read
0
VECTTBL_1
BusFault on vector table read
0x1
FORCED
no description available
30
1
read-write
FORCED_0
no forced HardFault
0
FORCED_1
forced HardFault
0x1
DEBUGEVT
no description available
31
1
read-write
DFSR
Debug Fault Status Register
0xD30
32
read-write
0
0xFFFFFFFF
HALTED
no description available
0
1
read-write
HALTED_0
No active halt request debug event
0
HALTED_1
Halt request debug event active
0x1
BKPT
no description available
1
1
read-write
BKPT_0
No current breakpoint debug event
0
BKPT_1
At least one current breakpoint debug event
0x1
DWTTRAP
no description available
2
1
read-write
DWTTRAP_0
No current debug events generated by the DWT
0
DWTTRAP_1
At least one current debug event generated by the DWT
0x1
VCATCH
no description available
3
1
read-write
VCATCH_0
No Vector catch triggered
0
VCATCH_1
Vector catch triggered
0x1
EXTERNAL
no description available
4
1
read-write
EXTERNAL_0
No EDBGRQ debug event
0
EXTERNAL_1
EDBGRQ debug event
0x1
MMFAR
MemManage Address Register
0xD34
32
read-write
0
0xFFFFFFFF
ADDRESS
Address of MemManage fault location
0
32
read-write
BFAR
BusFault Address Register
0xD38
32
read-write
0
0xFFFFFFFF
ADDRESS
Address of the BusFault location
0
32
read-write
AFSR
Auxiliary Fault Status Register
0xD3C
32
read-write
0
0xFFFFFFFF
AUXFAULT
Latched version of the AUXFAULT inputs
0
32
read-write
SysTick
System timer
SysTick
SYST_
0xE000E010
0
0x10
registers
CSR
SysTick Control and Status Register
0
32
read-write
0x4
0xFFFFFFFF
ENABLE
no description available
0
1
read-write
ENABLE_0
counter disabled
0
ENABLE_1
counter enabled
0x1
TICKINT
no description available
1
1
read-write
TICKINT_0
counting down to 0 does not assert the SysTick exception request
0
TICKINT_1
counting down to 0 asserts the SysTick exception request
0x1
CLKSOURCE
no description available
2
1
read-write
CLKSOURCE_0
external clock
0
CLKSOURCE_1
processor clock
0x1
COUNTFLAG
no description available
16
1
read-write
RVR
SysTick Reload Value Register
0x4
32
read-write
0
0xFFFFFFFF
RELOAD
Value to load into the SysTick Current Value Register when the counter reaches 0
0
24
read-write
CVR
SysTick Current Value Register
0x8
32
read-write
0
0xFFFFFFFF
CURRENT
Current value at the time the register is accessed
0
24
read-write
CALIB
SysTick Calibration Value Register
0xC
32
read-only
0x80000000
0xFFFFFFFF
TENMS
Reload value to use for 10ms timing
0
24
read-only
SKEW
no description available
30
1
read-only
SKEW_0
10ms calibration value is exact
0
SKEW_1
10ms calibration value is inexact, because of the clock frequency
0x1
NOREF
no description available
31
1
read-only
NOREF_0
The reference clock is provided
0
NOREF_1
The reference clock is not provided
0x1
NVIC
Nested Vectored Interrupt Controller
NVIC
0xE000E100
0
0xE04
registers
NVICISER0
Interrupt Set Enable Register n
0
32
read-write
0
0xFFFFFFFF
SETENA
Interrupt set enable bits
0
32
read-write
NVICISER1
Interrupt Set Enable Register n
0x4
32
read-write
0
0xFFFFFFFF
SETENA
Interrupt set enable bits
0
32
read-write
NVICISER2
Interrupt Set Enable Register n
0x8
32
read-write
0
0xFFFFFFFF
SETENA
Interrupt set enable bits
0
32
read-write
NVICISER3
Interrupt Set Enable Register n
0xC
32
read-write
0
0xFFFFFFFF
SETENA
Interrupt set enable bits
0
32
read-write
NVICICER0
Interrupt Clear Enable Register n
0x80
32
read-write
0
0xFFFFFFFF
CLRENA
Interrupt clear-enable bits
0
32
read-write
NVICICER1
Interrupt Clear Enable Register n
0x84
32
read-write
0
0xFFFFFFFF
CLRENA
Interrupt clear-enable bits
0
32
read-write
NVICICER2
Interrupt Clear Enable Register n
0x88
32
read-write
0
0xFFFFFFFF
CLRENA
Interrupt clear-enable bits
0
32
read-write
NVICICER3
Interrupt Clear Enable Register n
0x8C
32
read-write
0
0xFFFFFFFF
CLRENA
Interrupt clear-enable bits
0
32
read-write
NVICISPR0
Interrupt Set Pending Register n
0x100
32
read-write
0
0xFFFFFFFF
SETPEND
Interrupt set-pending bits
0
32
read-write
NVICISPR1
Interrupt Set Pending Register n
0x104
32
read-write
0
0xFFFFFFFF
SETPEND
Interrupt set-pending bits
0
32
read-write
NVICISPR2
Interrupt Set Pending Register n
0x108
32
read-write
0
0xFFFFFFFF
SETPEND
Interrupt set-pending bits
0
32
read-write
NVICISPR3
Interrupt Set Pending Register n
0x10C
32
read-write
0
0xFFFFFFFF
SETPEND
Interrupt set-pending bits
0
32
read-write
NVICICPR0
Interrupt Clear Pending Register n
0x180
32
read-write
0
0xFFFFFFFF
CLRPEND
Interrupt clear-pending bits
0
32
read-write
NVICICPR1
Interrupt Clear Pending Register n
0x184
32
read-write
0
0xFFFFFFFF
CLRPEND
Interrupt clear-pending bits
0
32
read-write
NVICICPR2
Interrupt Clear Pending Register n
0x188
32
read-write
0
0xFFFFFFFF
CLRPEND
Interrupt clear-pending bits
0
32
read-write
NVICICPR3
Interrupt Clear Pending Register n
0x18C
32
read-write
0
0xFFFFFFFF
CLRPEND
Interrupt clear-pending bits
0
32
read-write
NVICIABR0
Interrupt Active bit Register n
0x200
32
read-write
0
0xFFFFFFFF
ACTIVE
Interrupt active flags
0
32
read-write
NVICIABR1
Interrupt Active bit Register n
0x204
32
read-write
0
0xFFFFFFFF
ACTIVE
Interrupt active flags
0
32
read-write
NVICIABR2
Interrupt Active bit Register n
0x208
32
read-write
0
0xFFFFFFFF
ACTIVE
Interrupt active flags
0
32
read-write
NVICIABR3
Interrupt Active bit Register n
0x20C
32
read-write
0
0xFFFFFFFF
ACTIVE
Interrupt active flags
0
32
read-write
NVICIP0
Interrupt Priority Register n
0x300
8
read-write
0
0xFF
PRI0
Priority of interrupt 0
0
8
read-write
NVICIP1
Interrupt Priority Register n
0x301
8
read-write
0
0xFF
PRI1
Priority of interrupt 1
0
8
read-write
NVICIP2
Interrupt Priority Register n
0x302
8
read-write
0
0xFF
PRI2
Priority of interrupt 2
0
8
read-write
NVICIP3
Interrupt Priority Register n
0x303
8
read-write
0
0xFF
PRI3
Priority of interrupt 3
0
8
read-write
NVICIP4
Interrupt Priority Register n
0x304
8
read-write
0
0xFF
PRI4
Priority of interrupt 4
0
8
read-write
NVICIP5
Interrupt Priority Register n
0x305
8
read-write
0
0xFF
PRI5
Priority of interrupt 5
0
8
read-write
NVICIP6
Interrupt Priority Register n
0x306
8
read-write
0
0xFF
PRI6
Priority of interrupt 6
0
8
read-write
NVICIP7
Interrupt Priority Register n
0x307
8
read-write
0
0xFF
PRI7
Priority of interrupt 7
0
8
read-write
NVICIP8
Interrupt Priority Register n
0x308
8
read-write
0
0xFF
PRI8
Priority of interrupt 8
0
8
read-write
NVICIP9
Interrupt Priority Register n
0x309
8
read-write
0
0xFF
PRI9
Priority of interrupt 9
0
8
read-write
NVICIP10
Interrupt Priority Register n
0x30A
8
read-write
0
0xFF
PRI10
Priority of interrupt 10
0
8
read-write
NVICIP11
Interrupt Priority Register n
0x30B
8
read-write
0
0xFF
PRI11
Priority of interrupt 11
0
8
read-write
NVICIP12
Interrupt Priority Register n
0x30C
8
read-write
0
0xFF
PRI12
Priority of interrupt 12
0
8
read-write
NVICIP13
Interrupt Priority Register n
0x30D
8
read-write
0
0xFF
PRI13
Priority of interrupt 13
0
8
read-write
NVICIP14
Interrupt Priority Register n
0x30E
8
read-write
0
0xFF
PRI14
Priority of interrupt 14
0
8
read-write
NVICIP15
Interrupt Priority Register n
0x30F
8
read-write
0
0xFF
PRI15
Priority of interrupt 15
0
8
read-write
NVICIP16
Interrupt Priority Register n
0x310
8
read-write
0
0xFF
PRI16
Priority of interrupt 16
0
8
read-write
NVICIP17
Interrupt Priority Register n
0x311
8
read-write
0
0xFF
PRI17
Priority of interrupt 17
0
8
read-write
NVICIP18
Interrupt Priority Register n
0x312
8
read-write
0
0xFF
PRI18
Priority of interrupt 18
0
8
read-write
NVICIP19
Interrupt Priority Register n
0x313
8
read-write
0
0xFF
PRI19
Priority of interrupt 19
0
8
read-write
NVICIP20
Interrupt Priority Register n
0x314
8
read-write
0
0xFF
PRI20
Priority of interrupt 20
0
8
read-write
NVICIP21
Interrupt Priority Register n
0x315
8
read-write
0
0xFF
PRI21
Priority of interrupt 21
0
8
read-write
NVICIP22
Interrupt Priority Register n
0x316
8
read-write
0
0xFF
PRI22
Priority of interrupt 22
0
8
read-write
NVICIP23
Interrupt Priority Register n
0x317
8
read-write
0
0xFF
PRI23
Priority of interrupt 23
0
8
read-write
NVICIP24
Interrupt Priority Register n
0x318
8
read-write
0
0xFF
PRI24
Priority of interrupt 24
0
8
read-write
NVICIP25
Interrupt Priority Register n
0x319
8
read-write
0
0xFF
PRI25
Priority of interrupt 25
0
8
read-write
NVICIP26
Interrupt Priority Register n
0x31A
8
read-write
0
0xFF
PRI26
Priority of interrupt 26
0
8
read-write
NVICIP27
Interrupt Priority Register n
0x31B
8
read-write
0
0xFF
PRI27
Priority of interrupt 27
0
8
read-write
NVICIP28
Interrupt Priority Register n
0x31C
8
read-write
0
0xFF
PRI28
Priority of interrupt 28
0
8
read-write
NVICIP29
Interrupt Priority Register n
0x31D
8
read-write
0
0xFF
PRI29
Priority of interrupt 29
0
8
read-write
NVICIP30
Interrupt Priority Register n
0x31E
8
read-write
0
0xFF
PRI30
Priority of interrupt 30
0
8
read-write
NVICIP31
Interrupt Priority Register n
0x31F
8
read-write
0
0xFF
PRI31
Priority of interrupt 31
0
8
read-write
NVICIP32
Interrupt Priority Register n
0x320
8
read-write
0
0xFF
PRI32
Priority of interrupt 32
0
8
read-write
NVICIP33
Interrupt Priority Register n
0x321
8
read-write
0
0xFF
PRI33
Priority of interrupt 33
0
8
read-write
NVICIP34
Interrupt Priority Register n
0x322
8
read-write
0
0xFF
PRI34
Priority of interrupt 34
0
8
read-write
NVICIP35
Interrupt Priority Register n
0x323
8
read-write
0
0xFF
PRI35
Priority of interrupt 35
0
8
read-write
NVICIP36
Interrupt Priority Register n
0x324
8
read-write
0
0xFF
PRI36
Priority of interrupt 36
0
8
read-write
NVICIP37
Interrupt Priority Register n
0x325
8
read-write
0
0xFF
PRI37
Priority of interrupt 37
0
8
read-write
NVICIP38
Interrupt Priority Register n
0x326
8
read-write
0
0xFF
PRI38
Priority of interrupt 38
0
8
read-write
NVICIP39
Interrupt Priority Register n
0x327
8
read-write
0
0xFF
PRI39
Priority of interrupt 39
0
8
read-write
NVICIP40
Interrupt Priority Register n
0x328
8
read-write
0
0xFF
PRI40
Priority of interrupt 40
0
8
read-write
NVICIP41
Interrupt Priority Register n
0x329
8
read-write
0
0xFF
PRI41
Priority of interrupt 41
0
8
read-write
NVICIP42
Interrupt Priority Register n
0x32A
8
read-write
0
0xFF
PRI42
Priority of interrupt 42
0
8
read-write
NVICIP43
Interrupt Priority Register n
0x32B
8
read-write
0
0xFF
PRI43
Priority of interrupt 43
0
8
read-write
NVICIP44
Interrupt Priority Register n
0x32C
8
read-write
0
0xFF
PRI44
Priority of interrupt 44
0
8
read-write
NVICIP45
Interrupt Priority Register n
0x32D
8
read-write
0
0xFF
PRI45
Priority of interrupt 45
0
8
read-write
NVICIP46
Interrupt Priority Register n
0x32E
8
read-write
0
0xFF
PRI46
Priority of interrupt 46
0
8
read-write
NVICIP47
Interrupt Priority Register n
0x32F
8
read-write
0
0xFF
PRI47
Priority of interrupt 47
0
8
read-write
NVICIP48
Interrupt Priority Register n
0x330
8
read-write
0
0xFF
PRI48
Priority of interrupt 48
0
8
read-write
NVICIP49
Interrupt Priority Register n
0x331
8
read-write
0
0xFF
PRI49
Priority of interrupt 49
0
8
read-write
NVICIP50
Interrupt Priority Register n
0x332
8
read-write
0
0xFF
PRI50
Priority of interrupt 50
0
8
read-write
NVICIP51
Interrupt Priority Register n
0x333
8
read-write
0
0xFF
PRI51
Priority of interrupt 51
0
8
read-write
NVICIP52
Interrupt Priority Register n
0x334
8
read-write
0
0xFF
PRI52
Priority of interrupt 52
0
8
read-write
NVICIP53
Interrupt Priority Register n
0x335
8
read-write
0
0xFF
PRI53
Priority of interrupt 53
0
8
read-write
NVICIP54
Interrupt Priority Register n
0x336
8
read-write
0
0xFF
PRI54
Priority of interrupt 54
0
8
read-write
NVICIP55
Interrupt Priority Register n
0x337
8
read-write
0
0xFF
PRI55
Priority of interrupt 55
0
8
read-write
NVICIP56
Interrupt Priority Register n
0x338
8
read-write
0
0xFF
PRI56
Priority of interrupt 56
0
8
read-write
NVICIP57
Interrupt Priority Register n
0x339
8
read-write
0
0xFF
PRI57
Priority of interrupt 57
0
8
read-write
NVICIP58
Interrupt Priority Register n
0x33A
8
read-write
0
0xFF
PRI58
Priority of interrupt 58
0
8
read-write
NVICIP59
Interrupt Priority Register n
0x33B
8
read-write
0
0xFF
PRI59
Priority of interrupt 59
0
8
read-write
NVICIP60
Interrupt Priority Register n
0x33C
8
read-write
0
0xFF
PRI60
Priority of interrupt 60
0
8
read-write
NVICIP61
Interrupt Priority Register n
0x33D
8
read-write
0
0xFF
PRI61
Priority of interrupt 61
0
8
read-write
NVICIP62
Interrupt Priority Register n
0x33E
8
read-write
0
0xFF
PRI62
Priority of interrupt 62
0
8
read-write
NVICIP63
Interrupt Priority Register n
0x33F
8
read-write
0
0xFF
PRI63
Priority of interrupt 63
0
8
read-write
NVICIP64
Interrupt Priority Register n
0x340
8
read-write
0
0xFF
PRI64
Priority of interrupt 64
0
8
read-write
NVICIP65
Interrupt Priority Register n
0x341
8
read-write
0
0xFF
PRI65
Priority of interrupt 65
0
8
read-write
NVICIP66
Interrupt Priority Register n
0x342
8
read-write
0
0xFF
PRI66
Priority of interrupt 66
0
8
read-write
NVICIP67
Interrupt Priority Register n
0x343
8
read-write
0
0xFF
PRI67
Priority of interrupt 67
0
8
read-write
NVICIP68
Interrupt Priority Register n
0x344
8
read-write
0
0xFF
PRI68
Priority of interrupt 68
0
8
read-write
NVICIP69
Interrupt Priority Register n
0x345
8
read-write
0
0xFF
PRI69
Priority of interrupt 69
0
8
read-write
NVICIP70
Interrupt Priority Register n
0x346
8
read-write
0
0xFF
PRI70
Priority of interrupt 70
0
8
read-write
NVICIP71
Interrupt Priority Register n
0x347
8
read-write
0
0xFF
PRI71
Priority of interrupt 71
0
8
read-write
NVICIP72
Interrupt Priority Register n
0x348
8
read-write
0
0xFF
PRI72
Priority of interrupt 72
0
8
read-write
NVICIP73
Interrupt Priority Register n
0x349
8
read-write
0
0xFF
PRI73
Priority of interrupt 73
0
8
read-write
NVICIP74
Interrupt Priority Register n
0x34A
8
read-write
0
0xFF
PRI74
Priority of interrupt 74
0
8
read-write
NVICIP75
Interrupt Priority Register n
0x34B
8
read-write
0
0xFF
PRI75
Priority of interrupt 75
0
8
read-write
NVICIP76
Interrupt Priority Register n
0x34C
8
read-write
0
0xFF
PRI76
Priority of interrupt 76
0
8
read-write
NVICIP77
Interrupt Priority Register n
0x34D
8
read-write
0
0xFF
PRI77
Priority of interrupt 77
0
8
read-write
NVICIP78
Interrupt Priority Register n
0x34E
8
read-write
0
0xFF
PRI78
Priority of interrupt 78
0
8
read-write
NVICIP79
Interrupt Priority Register n
0x34F
8
read-write
0
0xFF
PRI79
Priority of interrupt 79
0
8
read-write
NVICIP80
Interrupt Priority Register n
0x350
8
read-write
0
0xFF
PRI80
Priority of interrupt 80
0
8
read-write
NVICIP81
Interrupt Priority Register n
0x351
8
read-write
0
0xFF
PRI81
Priority of interrupt 81
0
8
read-write
NVICIP82
Interrupt Priority Register n
0x352
8
read-write
0
0xFF
PRI82
Priority of interrupt 82
0
8
read-write
NVICIP83
Interrupt Priority Register n
0x353
8
read-write
0
0xFF
PRI83
Priority of interrupt 83
0
8
read-write
NVICIP84
Interrupt Priority Register n
0x354
8
read-write
0
0xFF
PRI84
Priority of interrupt 84
0
8
read-write
NVICIP85
Interrupt Priority Register n
0x355
8
read-write
0
0xFF
PRI85
Priority of interrupt 85
0
8
read-write
NVICIP86
Interrupt Priority Register n
0x356
8
read-write
0
0xFF
PRI86
Priority of interrupt 86
0
8
read-write
NVICIP87
Interrupt Priority Register n
0x357
8
read-write
0
0xFF
PRI87
Priority of interrupt 87
0
8
read-write
NVICIP88
Interrupt Priority Register n
0x358
8
read-write
0
0xFF
PRI88
Priority of interrupt 88
0
8
read-write
NVICIP89
Interrupt Priority Register n
0x359
8
read-write
0
0xFF
PRI89
Priority of interrupt 89
0
8
read-write
NVICIP90
Interrupt Priority Register n
0x35A
8
read-write
0
0xFF
PRI90
Priority of interrupt 90
0
8
read-write
NVICIP91
Interrupt Priority Register n
0x35B
8
read-write
0
0xFF
PRI91
Priority of interrupt 91
0
8
read-write
NVICIP92
Interrupt Priority Register n
0x35C
8
read-write
0
0xFF
PRI92
Priority of interrupt 92
0
8
read-write
NVICIP93
Interrupt Priority Register n
0x35D
8
read-write
0
0xFF
PRI93
Priority of interrupt 93
0
8
read-write
NVICIP94
Interrupt Priority Register n
0x35E
8
read-write
0
0xFF
PRI94
Priority of interrupt 94
0
8
read-write
NVICIP95
Interrupt Priority Register n
0x35F
8
read-write
0
0xFF
PRI95
Priority of interrupt 95
0
8
read-write
NVICIP96
Interrupt Priority Register n
0x360
8
read-write
0
0xFF
PRI96
Priority of interrupt 96
0
8
read-write
NVICIP97
Interrupt Priority Register n
0x361
8
read-write
0
0xFF
PRI97
Priority of interrupt 97
0
8
read-write
NVICIP98
Interrupt Priority Register n
0x362
8
read-write
0
0xFF
PRI98
Priority of interrupt 98
0
8
read-write
NVICIP99
Interrupt Priority Register n
0x363
8
read-write
0
0xFF
PRI99
Priority of interrupt 99
0
8
read-write
NVICIP100
Interrupt Priority Register n
0x364
8
read-write
0
0xFF
PRI100
Priority of interrupt 100
0
8
read-write
NVICIP101
Interrupt Priority Register n
0x365
8
read-write
0
0xFF
PRI101
Priority of interrupt 101
0
8
read-write
NVICIP102
Interrupt Priority Register n
0x366
8
read-write
0
0xFF
PRI102
Priority of interrupt 102
0
8
read-write
NVICIP103
Interrupt Priority Register n
0x367
8
read-write
0
0xFF
PRI103
Priority of interrupt 103
0
8
read-write
NVICIP104
Interrupt Priority Register n
0x368
8
read-write
0
0xFF
PRI104
Priority of interrupt 104
0
8
read-write
NVICIP105
Interrupt Priority Register n
0x369
8
read-write
0
0xFF
PRI105
Priority of interrupt 105
0
8
read-write
NVICSTIR
Software Trigger Interrupt Register
0xE00
32
read-write
0
0xFFFFFFFF
INTID
Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of 0x03 specifies interrupt IRQ3.
0
9
read-write