203 lines
7.3 KiB
C
203 lines
7.3 KiB
C
/*
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** ###################################################################
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** Version: rev. 1.0, 2016-05-09
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** Build: b190304
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**
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** Abstract:
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** Chip specific module features.
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**
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** Copyright 2016 Freescale Semiconductor, Inc.
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** Copyright 2016-2019 NXP
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** All rights reserved.
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**
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** SPDX-License-Identifier: BSD-3-Clause
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**
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** http: www.nxp.com
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** mail: support@nxp.com
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**
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** Revisions:
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** - rev. 1.0 (2016-05-09)
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** Initial version.
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**
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** ###################################################################
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*/
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#ifndef _LPC54102_cm0plus_FEATURES_H_
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#define _LPC54102_cm0plus_FEATURES_H_
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/* SOC module features */
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/* @brief ADC availability on the SoC. */
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#define FSL_FEATURE_SOC_ADC_COUNT (1)
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/* @brief ASYNC_SYSCON availability on the SoC. */
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#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (1)
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/* @brief CRC availability on the SoC. */
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#define FSL_FEATURE_SOC_CRC_COUNT (1)
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/* @brief CTIMER availability on the SoC. */
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#define FSL_FEATURE_SOC_CTIMER_COUNT (5)
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/* @brief DMA availability on the SoC. */
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#define FSL_FEATURE_SOC_DMA_COUNT (1)
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/* @brief GINT availability on the SoC. */
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#define FSL_FEATURE_SOC_GINT_COUNT (2)
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/* @brief GPIO availability on the SoC. */
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#define FSL_FEATURE_SOC_GPIO_COUNT (1)
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/* @brief I2C availability on the SoC. */
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#define FSL_FEATURE_SOC_I2C_COUNT (3)
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/* @brief INPUTMUX availability on the SoC. */
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#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
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/* @brief IOCON availability on the SoC. */
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#define FSL_FEATURE_SOC_IOCON_COUNT (1)
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/* @brief MAILBOX availability on the SoC. */
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#define FSL_FEATURE_SOC_MAILBOX_COUNT (1)
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/* @brief MRT availability on the SoC. */
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#define FSL_FEATURE_SOC_MRT_COUNT (1)
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/* @brief PINT availability on the SoC. */
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#define FSL_FEATURE_SOC_PINT_COUNT (1)
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/* @brief RIT availability on the SoC. */
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#define FSL_FEATURE_SOC_RIT_COUNT (1)
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/* @brief RTC availability on the SoC. */
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#define FSL_FEATURE_SOC_RTC_COUNT (1)
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/* @brief SCT availability on the SoC. */
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#define FSL_FEATURE_SOC_SCT_COUNT (1)
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/* @brief SPI availability on the SoC. */
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#define FSL_FEATURE_SOC_SPI_COUNT (2)
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/* @brief SYSCON availability on the SoC. */
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#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
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/* @brief USART availability on the SoC. */
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#define FSL_FEATURE_SOC_USART_COUNT (4)
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/* @brief UTICK availability on the SoC. */
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#define FSL_FEATURE_SOC_UTICK_COUNT (1)
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/* @brief VFIFO availability on the SoC. */
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#define FSL_FEATURE_SOC_VFIFO_COUNT (1)
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/* @brief WWDT availability on the SoC. */
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#define FSL_FEATURE_SOC_WWDT_COUNT (1)
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/* ADC module features */
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/* @brief Do not has input select (register INSEL). */
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#define FSL_FEATURE_ADC_HAS_NO_INSEL (1)
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/* @brief Has ASYNMODE bitfile in CTRL reigster. */
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#define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (1)
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/* @brief Has ASYNMODE bitfile in CTRL reigster. */
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#define FSL_FEATURE_ADC_HAS_CTRL_RESOL (1)
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/* @brief Has ASYNMODE bitfile in CTRL reigster. */
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#define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (1)
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/* @brief Has ASYNMODE bitfile in CTRL reigster. */
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#define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (1)
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/* @brief Has ASYNMODE bitfile in CTRL reigster. */
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#define FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE (0)
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/* @brief Has ASYNMODE bitfile in CTRL reigster. */
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#define FSL_FEATURE_ADC_HAS_CTRL_CALMODE (0)
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/* @brief Has startup register. */
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#define FSL_FEATURE_ADC_HAS_STARTUP_REG (1)
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/* @brief Has ADTrim register */
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#define FSL_FEATURE_ADC_HAS_TRIM_REG (0)
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/* @brief Has Calibration register. */
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#define FSL_FEATURE_ADC_HAS_CALIB_REG (1)
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/* DMA module features */
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/* @brief Number of channels */
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#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (22)
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/* @brief Align size of DMA descriptor */
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#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512)
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/* @brief DMA head link descriptor table align size */
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#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U)
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/* MAILBOX module features */
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/* @brief Mailbox side for current core */
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#define FSL_FEATURE_MAILBOX_SIDE_B (1)
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/* @brief Mailbox has no reset control */
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#define FSL_FEATURE_MAILBOX_HAS_NO_RESET (1)
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/* MRT module features */
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/* @brief number of channels. */
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#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4)
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/* interrupt module features */
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/* @brief Lowest interrupt request number. */
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#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
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/* @brief Highest interrupt request number. */
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#define FSL_FEATURE_INTERRUPT_IRQ_MAX (105)
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/* PINT module features */
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/* @brief Number of connected outputs */
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#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (4)
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/* RTC module features */
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/* @brief Has CTRL:RTC_OSC_PD Bit */
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#define FSL_FEATURE_RTC_HAS_NO_OSC_PD (1)
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/* @brief RTC has no reset control */
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#define FSL_FEATURE_RTC_HAS_NO_RESET (1)
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/* SCT module features */
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/* @brief Number of events */
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#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (13)
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/* @brief Number of states */
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#define FSL_FEATURE_SCT_NUMBER_OF_STATES (13)
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/* @brief Number of match capture */
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#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (13)
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/* @brief Number of outputs */
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#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (8)
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/* SYSCON module features */
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#if defined(CPU_LPC54102J256BD64) || defined(CPU_LPC54102J256UK49)
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/* @brief Pointer to ROM IAP entry functions */
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#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)
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/* @brief Flash page size in bytes */
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#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (256)
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/* @brief Flash sector size in bytes */
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#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768)
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/* @brief Flash size in bytes */
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#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (262144)
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/* @brief IAP has Flash read & write function */
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#define FSL_FEATURE_IAP_HAS_FLASH_FUNCTION (1)
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/* @brief IAP has read Flash signature function */
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#define FSL_FEATURE_IAP_HAS_FLASH_SIGNATURE_READ (1)
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/* @brief IAP has read extended Flash signature function */
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#define FSL_FEATURE_IAP_HAS_FLASH_EXTENDED_SIGNATURE_READ (0)
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#elif defined(CPU_LPC54102J512BD64) || defined(CPU_LPC54102J512UK49)
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/* @brief Pointer to ROM IAP entry functions */
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#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)
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/* @brief Flash page size in bytes */
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#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (256)
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/* @brief Flash sector size in bytes */
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#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768)
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/* @brief Flash size in bytes */
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#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (524288)
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/* @brief IAP has Flash read & write function */
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#define FSL_FEATURE_IAP_HAS_FLASH_FUNCTION (1)
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/* @brief IAP has read Flash signature function */
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#define FSL_FEATURE_IAP_HAS_FLASH_SIGNATURE_READ (1)
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/* @brief IAP has read extended Flash signature function */
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#define FSL_FEATURE_IAP_HAS_FLASH_EXTENDED_SIGNATURE_READ (0)
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#endif /* defined(CPU_LPC54102J256BD64) || defined(CPU_LPC54102J256UK49) */
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/* SysTick module features */
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/* @brief Systick has external reference clock. */
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#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0)
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/* @brief Systick external reference clock is core clock divided by this value. */
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#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0)
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/* VFIFO module features */
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/* @brief FIFO entries for USART receive */
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#define FSL_FEATURE_VFIFO_USART_RX_TOTAL (16)
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/* @brief FIFO entries for USART transmit */
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#define FSL_FEATURE_VFIFO_USART_TX_TOTAL (16)
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/* @brief FIFO entries for SPI receive */
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#define FSL_FEATURE_VFIFO_SPI_RX_TOTAL (8)
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/* @brief FIFO entries for SPI transmit */
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#define FSL_FEATURE_VFIFO_SPI_TX_TOTAL (8)
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#endif /* _LPC54102_cm0plus_FEATURES_H_ */
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