227 lines
5.8 KiB
C
227 lines
5.8 KiB
C
/*
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* Copyright 2017 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _FSL_POWER_H_
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#define _FSL_POWER_H_
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#include "fsl_common.h"
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/*! @addtogroup power */
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/*! @{ */
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/*! @file */
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @name Driver version */
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/*@{*/
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/*! @brief power driver version 2.0.0. */
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#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
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/*@}*/
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#define MAKE_PD_BITS(reg, slot) (((reg) << 8) | (slot))
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#define PDRCFG0 0x0U
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typedef enum pd_bits
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{
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kPDRUNCFG_PD_IRC_OSC = MAKE_PD_BITS(PDRCFG0, 3U),
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kPDRUNCFG_PD_IRC = MAKE_PD_BITS(PDRCFG0, 4U),
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kPDRUNCFG_PD_FLASH = MAKE_PD_BITS(PDRCFG0, 5U),
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kPDRUNCFG_PD_BOD_RST = MAKE_PD_BITS(PDRCFG0, 7U),
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kPDRUNCFG_PD_BOD_INTR = MAKE_PD_BITS(PDRCFG0, 8U),
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kPDRUNCFG_PD_ADC0 = MAKE_PD_BITS(PDRCFG0, 10U),
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kPDRUNCFG_PD_SRAM0A = MAKE_PD_BITS(PDRCFG0, 13U),
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kPDRUNCFG_PD_SRAM0B = MAKE_PD_BITS(PDRCFG0, 14U),
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kPDRUNCFG_PD_SRAM1 = MAKE_PD_BITS(PDRCFG0, 15U),
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kPDRUNCFG_PD_SRAM2 = MAKE_PD_BITS(PDRCFG0, 16U),
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kPDRUNCFG_PD_ROM = MAKE_PD_BITS(PDRCFG0, 17U),
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kPDRUNCFG_PD_VDDA = MAKE_PD_BITS(PDRCFG0, 19U),
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kPDRUNCFG_PD_WDT_OSC = MAKE_PD_BITS(PDRCFG0, 20U),
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kPDRUNCFG_PD_SYS_PLL = MAKE_PD_BITS(PDRCFG0, 22U),
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kPDRUNCFG_PD_VREFP = MAKE_PD_BITS(PDRCFG0, 23U),
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kPDRUNCFG_PD_32K_OSC = MAKE_PD_BITS(PDRCFG0, 24U),
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/*
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This enum member has no practical meaning,it is used to avoid MISRA issue,
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user should not trying to use it.
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*/
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kPDRUNCFG_ForceUnsigned = (int)0x80000000U
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} pd_bit_t;
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/* Power mode configuration API parameter */
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typedef enum _power_mode_config
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{
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kPmu_Sleep = 0U,
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kPmu_Deep_Sleep = 1U,
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kPmu_Power_Down = 2U,
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kPmu_Deep_PowerDown = 3U,
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} power_mode_cfg_t;
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/*******************************************************************************
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* API
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******************************************************************************/
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*!
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* @name Power Configuration
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* @{
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*/
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/*!
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* @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral
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*
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* @param en peripheral for which to enable the PDRUNCFG bit
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* @return none
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*/
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static inline void POWER_EnablePD(pd_bit_t en)
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{
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/* PDRUNCFGSET */
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SYSCON->PDRUNCFGSET = (1UL << (en & 0xffU));
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}
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/*!
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* @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral
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*
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* @param en peripheral for which to disable the PDRUNCFG bit
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* @return none
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*/
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static inline void POWER_DisablePD(pd_bit_t en)
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{
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/* PDRUNCFGCLR */
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SYSCON->PDRUNCFGCLR = (1UL << (en & 0xffU));
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}
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/*!
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* @brief API to enable deep sleep bit in the ARM Core.
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*
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* @return none
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*/
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static inline void POWER_EnableDeepSleep(void)
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{
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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}
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/*!
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* @brief API to disable deep sleep bit in the ARM Core.
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*
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* @return none
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*/
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static inline void POWER_DisableDeepSleep(void)
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{
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SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
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}
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/*!
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* @brief API in power lib to power down flash.
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*
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* @return none
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*/
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void Chip_POWER_SetFLASHPower(uint32_t new_power_mode);
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/*!
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* @brief API to power down flash controller.
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*
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* @return none
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*/
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static inline void POWER_PowerDownFlash(void)
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{
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Chip_POWER_SetFLASHPower(0U);
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* TURN OFF clock for Flash Controller (only needed for FLASH programming, will be turned on by ROM API) */
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CLOCK_DisableClock(kCLOCK_Flash);
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/* TURN OFF clock for Flash Accelerator */
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CLOCK_DisableClock(kCLOCK_Fmc);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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/*!
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* @brief API to power up flash controller.
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*
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* @return none
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*/
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static inline void POWER_PowerUpFlash(void)
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{
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Chip_POWER_SetFLASHPower(1U);
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* TURN ON clock for flash controller */
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CLOCK_EnableClock(kCLOCK_Fmc);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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/*!
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* @brief Power Library API to enter different power mode.
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*
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* @param exclude_from_pd Bit mask of the PDRUNCFG bits that needs to be powered on during deep sleep
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* @return none
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*/
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void POWER_EnterPowerMode(power_mode_cfg_t mode, uint64_t exclude_from_pd);
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/*!
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* @brief Power Library API to enter sleep mode.
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*
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* @return none
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*/
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void POWER_EnterSleep(void);
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/*!
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* @brief Power Library API to enter deep sleep mode.
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*
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* @param exclude_from_pd Bit mask of the PDRUNCFG bits that needs to be powered on during deep sleep
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* @return none
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*/
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void POWER_EnterDeepSleep(uint64_t exclude_from_pd);
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/*!
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* @brief Power Library API to enter power down mode.
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*
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* @param exclude_from_pd Bit mask of the PDRUNCFG bits that needs to be powered on during deep sleep
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* @return none
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*/
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void POWER_EnterPowerDown(uint64_t exclude_from_pd);
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/*!
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* @brief Power Library API to enter deep power down mode.
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*
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* @param exclude_from_pd Bit mask of the PDRUNCFG bits that needs to be powered on during deep power down mode,
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* but this is has no effect as the voltages are cut off.
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* @return none
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*/
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void POWER_EnterDeepPowerDown(uint64_t exclude_from_pd);
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/*!
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* @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency.
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*
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* @param freq - The desired frequency at which the part would like to operate,
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* note that the voltage and flash wait states should be set before changing frequency
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* @return none
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*/
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void POWER_SetVoltageForFreq(uint32_t freq);
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/*!
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* @brief Power Library API to return the library version.
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*
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* @return version number of the power library
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*/
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uint32_t POWER_GetLibVersion(void);
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/* @} */
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#ifdef __cplusplus
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}
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#endif
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/*! @} */
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#endif /* _FSL_POWER_H_ */
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