137 lines
7.4 KiB
C
137 lines
7.4 KiB
C
/*
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* Copyright 2017-2019 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/***********************************************************************************************************************
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* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
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* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
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**********************************************************************************************************************/
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/* clang-format off */
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/*
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* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!GlobalInfo
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product: Pins v6.0
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processor: LPC55S69
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package_id: LPC55S69JBD100
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mcu_data: ksdk2_0
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processor_version: 0.0.0
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pin_labels:
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- {pin_num: '64', pin_signal: PIO1_18/SD1_POW_EN/SCT0_OUT5/PLU_OUT0, label: S2 button}
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- {pin_num: '88', pin_signal: PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5, label: S1 button}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
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*/
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/* clang-format on */
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#include "fsl_common.h"
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#include "fsl_iocon.h"
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#include "pin_mux.h"
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/* FUNCTION ************************************************************************************************************
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*
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* Function Name : BOARD_InitBootPins
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* Description : Calls initialization functions.
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*
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* END ****************************************************************************************************************/
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void BOARD_InitBootPins(void)
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{
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BOARD_InitPins();
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}
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/* clang-format off */
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/*
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* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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BOARD_InitPins:
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- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
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- pin_list:
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- {pin_num: '92', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_29/FC0_RXD_SDA_MOSI_DATA/SD1_D2/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29,
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mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled}
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- {pin_num: '94', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_30/FC0_TXD_SCL_MISO_WS/SD1_D3/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30, mode: inactive,
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slew_rate: standard, invert: disabled, open_drain: disabled}
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- {pin_num: '88', peripheral: SECGPIO, signal: 'SECPIO0, 5', pin_signal: PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5,
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mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled}
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- {pin_num: '64', peripheral: GPIO, signal: 'PIO1, 18', pin_signal: PIO1_18/SD1_POW_EN/SCT0_OUT5/PLU_OUT0, mode: inactive, slew_rate: standard, invert: disabled,
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open_drain: disabled}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
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*/
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/* clang-format on */
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/* FUNCTION ************************************************************************************************************
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*
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* Function Name : BOARD_InitPins
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* Description : Configures pin routing and optionally pin electrical features.
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*
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* END ****************************************************************************************************************/
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/* Function assigned for the Cortex-M33 (Core #0) */
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void BOARD_InitPins(void)
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{
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/* Enables the clock for the I/O controller.: Enable Clock. */
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CLOCK_EnableClock(kCLOCK_Iocon);
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const uint32_t port0_pin29_config = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */
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IOCON_PIO_FUNC1 |
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/* No addition pin function */
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IOCON_PIO_MODE_INACT |
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/* Standard mode, output slew rate control is enabled */
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IOCON_PIO_SLEW_STANDARD |
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/* Input function is not inverted */
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IOCON_PIO_INV_DI |
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/* Enables digital function */
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IOCON_PIO_DIGITAL_EN |
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/* Open drain is disabled */
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IOCON_PIO_OPENDRAIN_DI);
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/* PORT0 PIN29 (coords: 92) is configured as FC0_RXD_SDA_MOSI_DATA */
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IOCON_PinMuxSet(IOCON, 0U, 29U, port0_pin29_config);
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const uint32_t port0_pin30_config = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */
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IOCON_PIO_FUNC1 |
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/* No addition pin function */
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IOCON_PIO_MODE_INACT |
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/* Standard mode, output slew rate control is enabled */
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IOCON_PIO_SLEW_STANDARD |
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/* Input function is not inverted */
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IOCON_PIO_INV_DI |
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/* Enables digital function */
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IOCON_PIO_DIGITAL_EN |
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/* Open drain is disabled */
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IOCON_PIO_OPENDRAIN_DI);
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/* PORT0 PIN30 (coords: 94) is configured as FC0_TXD_SCL_MISO_WS */
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IOCON_PinMuxSet(IOCON, 0U, 30U, port0_pin30_config);
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const uint32_t port0_pin5_config = (/* Pin is configured as SECURE_GPIO0_5 */
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IOCON_PIO_FUNC10 |
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/* No addition pin function */
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IOCON_PIO_MODE_INACT |
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/* Standard mode, output slew rate control is enabled */
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IOCON_PIO_SLEW_STANDARD |
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/* Input function is not inverted */
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IOCON_PIO_INV_DI |
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/* Enables digital function */
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IOCON_PIO_DIGITAL_EN |
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/* Open drain is disabled */
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IOCON_PIO_OPENDRAIN_DI);
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/* PORT0 PIN5 (coords: 88) is configured as SECURE_GPIO0_5 */
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IOCON_PinMuxSet(IOCON, 0U, 5U, port0_pin5_config);
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const uint32_t port1_pin18_config = (/* Pin is configured as PIO1_18 */
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IOCON_PIO_FUNC0 |
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/* No addition pin function */
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IOCON_PIO_MODE_INACT |
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/* Standard mode, output slew rate control is enabled */
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IOCON_PIO_SLEW_STANDARD |
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/* Input function is not inverted */
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IOCON_PIO_INV_DI |
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/* Enables digital function */
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IOCON_PIO_DIGITAL_EN |
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/* Open drain is disabled */
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IOCON_PIO_OPENDRAIN_DI);
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/* PORT1 PIN18 (coords: 64) is configured as PIO1_18 */
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IOCON_PinMuxSet(IOCON, 1U, 18U, port1_pin18_config);
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}
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/***********************************************************************************************************************
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* EOF
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**********************************************************************************************************************/
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