95 lines
2.6 KiB
C
95 lines
2.6 KiB
C
/*
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* Copyright 2018 NXP
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* All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_common.h"
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#include "fsl_adapter_crc.h"
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/*******************************************************************************
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* Code
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******************************************************************************/
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uint32_t HAL_CrcCompute(hal_crc_config_t *crcConfig, uint8_t *dataIn, uint32_t length)
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{
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uint32_t shiftReg = crcConfig->crcSeed << ((4U - crcConfig->crcSize) << 3U);
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uint32_t crcPoly = crcConfig->crcPoly << ((4U - crcConfig->crcSize) << 3U);
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uint32_t crcXorOut = crcConfig->crcXorOut << ((4U - crcConfig->crcSize) << 3U);
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uint16_t startOffset = crcConfig->crcStartByte;
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uint8_t crcBits = 8U * crcConfig->crcSize;
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uint32_t computedCRC = 0;
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uint32_t i, j;
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uint8_t data = 0;
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uint8_t bit;
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/* Size 0 will bypass CRC calculation. */
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if (crcConfig->crcSize != 0U)
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{
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for (i = 0UL + startOffset; i < length; i++)
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{
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data = dataIn[i];
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if (crcConfig->crcRefIn == KHAL_CrcRefInput)
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{
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bit = 0U;
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for (j = 0U; j < 8U; j++)
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{
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bit = (bit << 1);
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bit |= ((data & 1U) != 0U) ? 1U : 0U;
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data = (data >> 1);
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}
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data = bit;
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}
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for (j = 0; j < 8U; j++)
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{
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bit = ((data & 0x80U) != 0U) ? 1U : 0U;
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data = (data << 1);
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if ((shiftReg & 1UL << 31) != 0U)
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{
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bit = (bit != 0U) ? 0U : 1U;
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}
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shiftReg = (shiftReg << 1);
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if (bit != 0U)
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{
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shiftReg ^= crcPoly;
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}
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if ((bool)bit && ((crcPoly & (1UL << (32U - crcBits))) != 0U))
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{
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shiftReg |= (1UL << (32U - crcBits));
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}
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else
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{
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shiftReg &= ~(1UL << (32U - crcBits));
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}
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}
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}
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shiftReg ^= crcXorOut;
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if (crcConfig->crcByteOrder == KHAL_CrcMSByteFirst)
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{
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computedCRC = (shiftReg >> (32U - crcBits));
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}
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else
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{
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computedCRC = 0;
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j = 1U;
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for (i = 0; i < 32U; i++)
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{
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computedCRC = (computedCRC << 1);
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computedCRC |= ((shiftReg & j) != 0U) ? 1U : 0U;
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j = (j << 1);
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}
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}
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}
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return computedCRC;
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}
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