502 lines
19 KiB
C
502 lines
19 KiB
C
/*
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** ###################################################################
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** Version: rev. 1.1, 2019-05-16
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** Build: b231017
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**
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** Abstract:
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** Chip specific module features.
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**
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** Copyright 2016 Freescale Semiconductor, Inc.
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** Copyright 2016-2023 NXP
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** SPDX-License-Identifier: BSD-3-Clause
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**
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** http: www.nxp.com
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** mail: support@nxp.com
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**
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** Revisions:
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** - rev. 1.0 (2018-08-22)
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** Initial version based on v0.2UM
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** - rev. 1.1 (2019-05-16)
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** Initial A1 version based on v1.3UM
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**
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** ###################################################################
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*/
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#ifndef _LPC55S69_cm33_core1_FEATURES_H_
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#define _LPC55S69_cm33_core1_FEATURES_H_
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/* SOC module features */
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/* @brief CASPER availability on the SoC. */
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#define FSL_FEATURE_SOC_CASPER_COUNT (1)
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/* @brief CRC availability on the SoC. */
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#define FSL_FEATURE_SOC_CRC_COUNT (1)
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/* @brief CTIMER availability on the SoC. */
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#define FSL_FEATURE_SOC_CTIMER_COUNT (5)
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/* @brief DMA availability on the SoC. */
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#define FSL_FEATURE_SOC_DMA_COUNT (2)
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/* @brief FLASH availability on the SoC. */
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#define FSL_FEATURE_SOC_FLASH_COUNT (1)
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/* @brief FLEXCOMM availability on the SoC. */
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#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9)
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/* @brief GINT availability on the SoC. */
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#define FSL_FEATURE_SOC_GINT_COUNT (2)
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/* @brief GPIO availability on the SoC. */
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#define FSL_FEATURE_SOC_GPIO_COUNT (1)
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/* @brief SECGPIO availability on the SoC. */
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#define FSL_FEATURE_SOC_SECGPIO_COUNT (1)
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/* @brief HASHCRYPT availability on the SoC. */
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#define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1)
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/* @brief I2C availability on the SoC. */
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#define FSL_FEATURE_SOC_I2C_COUNT (8)
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/* @brief I2S availability on the SoC. */
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#define FSL_FEATURE_SOC_I2S_COUNT (8)
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/* @brief INPUTMUX availability on the SoC. */
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#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
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/* @brief IOCON availability on the SoC. */
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#define FSL_FEATURE_SOC_IOCON_COUNT (1)
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/* @brief LPADC availability on the SoC. */
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#define FSL_FEATURE_SOC_LPADC_COUNT (1)
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/* @brief MAILBOX availability on the SoC. */
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#define FSL_FEATURE_SOC_MAILBOX_COUNT (1)
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/* @brief MPU availability on the SoC. */
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#define FSL_FEATURE_SOC_MPU_COUNT (1)
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/* @brief MRT availability on the SoC. */
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#define FSL_FEATURE_SOC_MRT_COUNT (1)
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/* @brief OSTIMER availability on the SoC. */
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#define FSL_FEATURE_SOC_OSTIMER_COUNT (1)
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/* @brief PINT availability on the SoC. */
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#define FSL_FEATURE_SOC_PINT_COUNT (1)
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/* @brief SECPINT availability on the SoC. */
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#define FSL_FEATURE_SOC_SECPINT_COUNT (1)
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/* @brief PMC availability on the SoC. */
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#define FSL_FEATURE_SOC_PMC_COUNT (1)
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/* @brief POWERQUAD availability on the SoC. */
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#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1)
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/* @brief PUF availability on the SoC. */
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#define FSL_FEATURE_SOC_PUF_COUNT (1)
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/* @brief LPC_RNG1 availability on the SoC. */
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#define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1)
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/* @brief RTC availability on the SoC. */
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#define FSL_FEATURE_SOC_RTC_COUNT (1)
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/* @brief SCT availability on the SoC. */
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#define FSL_FEATURE_SOC_SCT_COUNT (1)
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/* @brief SDIF availability on the SoC. */
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#define FSL_FEATURE_SOC_SDIF_COUNT (1)
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/* @brief SPI availability on the SoC. */
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#define FSL_FEATURE_SOC_SPI_COUNT (9)
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/* @brief SYSCON availability on the SoC. */
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#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
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/* @brief SYSCTL1 availability on the SoC. */
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#define FSL_FEATURE_SOC_SYSCTL1_COUNT (1)
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/* @brief USART availability on the SoC. */
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#define FSL_FEATURE_SOC_USART_COUNT (8)
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/* @brief USB availability on the SoC. */
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#define FSL_FEATURE_SOC_USB_COUNT (1)
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/* @brief USBFSH availability on the SoC. */
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#define FSL_FEATURE_SOC_USBFSH_COUNT (1)
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/* @brief USBHSD availability on the SoC. */
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#define FSL_FEATURE_SOC_USBHSD_COUNT (1)
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/* @brief USBHSH availability on the SoC. */
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#define FSL_FEATURE_SOC_USBHSH_COUNT (1)
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/* @brief USBPHY availability on the SoC. */
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#define FSL_FEATURE_SOC_USBPHY_COUNT (1)
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/* @brief UTICK availability on the SoC. */
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#define FSL_FEATURE_SOC_UTICK_COUNT (1)
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/* @brief WWDT availability on the SoC. */
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#define FSL_FEATURE_SOC_WWDT_COUNT (1)
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/* LPADC module features */
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/* @brief FIFO availability on the SoC. */
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#define FSL_FEATURE_LPADC_FIFO_COUNT (2)
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/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */
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#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1)
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/* @brief Has differential mode (bitfield CMDLn[DIFF]). */
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#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0)
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/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */
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#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0)
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/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */
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#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1)
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/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */
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#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1)
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/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */
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#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1)
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/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */
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#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1)
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/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */
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#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1)
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/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */
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#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1)
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/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */
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#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1)
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/* @brief Has internal clock (bitfield CFG[ADCKEN]). */
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#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0)
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/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */
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#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0)
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/* @brief Has calibration (bitfield CFG[CALOFS]). */
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#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0)
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/* @brief Has offset trim (register OFSTRIM). */
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#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1)
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/* @brief OFSTRIM availability on the SoC. */
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#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2)
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/* @brief Has Trigger status register. */
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#define FSL_FEATURE_LPADC_HAS_TSTAT (1)
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/* @brief Has power select (bitfield CFG[PWRSEL]). */
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#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1)
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/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */
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#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0)
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/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */
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#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0)
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/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */
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#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0)
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/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */
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#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0)
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/* @brief Conversion averaged bitfiled width. */
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#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3)
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/* @brief Has B side channels. */
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#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1)
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/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */
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#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1)
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/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */
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#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1)
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/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */
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#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1)
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/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */
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#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1)
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/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */
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#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1)
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/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */
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#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1)
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/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */
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#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1)
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/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */
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#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1)
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/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */
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#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1)
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/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */
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#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2)
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/* @brief Has internal temperature sensor. */
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#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1)
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/* @brief Chip Rev 0A Temperature sensor parameter A (slope). */
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#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A_CHIP_REV_0A (770.0f)
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/* @brief Chip Rev 0A Temperature sensor parameter B (offset). */
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#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B_CHIP_REV_0A (289.4f)
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/* @brief Chip Rev 0A Temperature sensor parameter Alpha. */
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#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA_CHIP_REV_0A (9.5f)
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/* @brief Chip Rev 1B Temperature sensor parameter A (slope). */
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#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A_CHIP_REV_1B (804.0f)
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/* @brief Chip Rev 1B Temperature sensor parameter B (offset). */
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#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B_CHIP_REV_1B (280.0f)
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/* @brief Chip Rev 1B Temperature sensor parameter Alpha. */
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#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA_CHIP_REV_1B (8.5f)
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/* @brief the buffer size of temperature sensor. */
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#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (4U)
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/* ANALOGCTRL module features */
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/* @brief Has PLL_USB_OUT_BIT_FIELD bitfile in XO32M_CTRL reigster. */
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#define FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD (1)
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/* @brief Has XO32M_ADC_CLK_MODE bitfile in DUMMY_CTRL reigster. */
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#define FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD (0)
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/* @brief Has auxiliary bias(register AUX_BIAS). */
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#define FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG (1)
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/* CASPER module features */
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/* @brief Base address of the CASPER dedicated RAM */
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#define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000)
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/* @brief SW interleaving of the CASPER dedicated RAM */
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#define FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED (1)
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/* @brief CASPER dedicated RAM offset */
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#define FSL_FEATURE_CASPER_RAM_OFFSET (0xE)
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/* CTIMER module features */
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/* @brief CTIMER has no capture channel. */
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#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0)
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/* @brief CTIMER has no capture 2 interrupt. */
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#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0)
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/* @brief CTIMER capture 3 interrupt. */
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#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1)
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/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */
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#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0)
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/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */
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#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1)
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/* @brief CTIMER Has register MSR */
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#define FSL_FEATURE_CTIMER_HAS_MSR (1)
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/* DMA module features */
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/* @brief Number of channels */
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#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (23)
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/* @brief Align size of DMA descriptor */
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#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512)
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/* @brief DMA head link descriptor table align size */
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#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U)
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/* FLEXCOMM module features */
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/* @brief FLEXCOMM0 USART INDEX 0 */
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#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0)
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/* @brief FLEXCOMM0 SPI INDEX 0 */
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#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0)
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/* @brief FLEXCOMM0 I2C INDEX 0 */
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#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0)
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/* @brief FLEXCOMM0 I2S INDEX 0 */
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#define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0)
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/* @brief FLEXCOMM1 USART INDEX 1 */
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#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1)
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/* @brief FLEXCOMM1 SPI INDEX 1 */
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#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1)
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/* @brief FLEXCOMM1 I2C INDEX 1 */
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#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1)
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/* @brief FLEXCOMM1 I2S INDEX 1 */
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#define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1)
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/* @brief FLEXCOMM2 USART INDEX 2 */
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#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2)
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/* @brief FLEXCOMM2 SPI INDEX 2 */
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#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2)
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/* @brief FLEXCOMM2 I2C INDEX 2 */
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#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2)
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/* @brief FLEXCOMM2 I2S INDEX 2 */
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#define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2)
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/* @brief FLEXCOMM3 USART INDEX 3 */
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#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3)
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/* @brief FLEXCOMM3 SPI INDEX 3 */
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#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3)
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/* @brief FLEXCOMM3 I2C INDEX 3 */
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#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3)
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/* @brief FLEXCOMM3 I2S INDEX 3 */
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#define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3)
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/* @brief FLEXCOMM4 USART INDEX 4 */
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#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4)
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/* @brief FLEXCOMM4 SPI INDEX 4 */
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#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4)
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/* @brief FLEXCOMM4 I2C INDEX 4 */
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#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4)
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/* @brief FLEXCOMM4 I2S INDEX 4 */
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#define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4)
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/* @brief FLEXCOMM5 USART INDEX 5 */
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#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5)
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/* @brief FLEXCOMM5 SPI INDEX 5 */
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#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5)
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/* @brief FLEXCOMM5 I2C INDEX 5 */
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#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5)
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/* @brief FLEXCOMM5 I2S INDEX 5 */
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#define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5)
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/* @brief FLEXCOMM6 USART INDEX 6 */
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#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6)
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/* @brief FLEXCOMM6 SPI INDEX 6 */
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#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6)
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/* @brief FLEXCOMM6 I2C INDEX 6 */
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#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6)
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/* @brief FLEXCOMM6 I2S INDEX 6 */
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#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6)
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/* @brief FLEXCOMM7 USART INDEX 7 */
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#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7)
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/* @brief FLEXCOMM7 SPI INDEX 7 */
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#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7)
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/* @brief FLEXCOMM7 I2C INDEX 7 */
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#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7)
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/* @brief FLEXCOMM7 I2S INDEX 7 */
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#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7)
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/* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */
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#define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8)
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/* @brief I2S has DMIC interconnection */
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#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0)
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/* GINT module features */
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/* @brief The count of th port which are supported in GINT. */
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#define FSL_FEATURE_GINT_PORT_COUNT (2)
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/* HASHCRYPT module features */
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/* @brief the address of alias offset */
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#define FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET (0x00000000)
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/* I2S module features */
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/* @brief I2S support dual channel transfer. */
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#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (0)
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/* @brief I2S has DMIC interconnection */
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#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0)
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/* INPUTMUX module features */
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/* @brief Inputmux has DMA Request Enable */
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#define FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA (0)
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/* @brief Inputmux has channel mux control */
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#define FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX (0)
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/* IOCON module features */
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/* @brief Func bit field width */
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#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4)
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/* MAILBOX module features */
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/* @brief Mailbox side for current core */
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#define FSL_FEATURE_MAILBOX_SIDE_B (1)
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/* MRT module features */
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/* @brief number of channels. */
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#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4)
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/* PINT module features */
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/* @brief Number of connected outputs */
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#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8)
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/* PLU module features */
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/* @brief Has WAKEINT_CTRL register. */
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#define FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG (1)
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/* PMC module features */
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/* @brief UTICK does not support PD configure. */
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#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1)
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/* @brief WDT OSC does not support PD configure. */
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#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1)
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/* POWERLIB module features */
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/* @brief Powerlib API is different with other LPC series devices. */
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#define FSL_FEATURE_POWERLIB_EXTEND (1)
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/* POWERQUAD module features */
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/* @brief Sine and Cossine fix errata */
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#define FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA (1)
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/* PUF module features */
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/* @brief Number of PUF key slots available on device. */
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#define FSL_FEATURE_PUF_HAS_KEYSLOTS (4)
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/* @brief the shift status value */
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#define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1)
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/* @brief Puf Activation Code Address. */
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#define FSL_FEATURE_PUF_ACTIVATION_CODE_ADDRESS (648704)
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/* @brief Puf Activation Code Size. */
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#define FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE (1192)
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/* RTC module features */
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/* @brief Has SUBSEC Register (register SUBSEC) */
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#define FSL_FEATURE_RTC_HAS_SUBSEC (1)
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/* SCT module features */
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/* @brief Number of events */
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#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16)
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/* @brief Number of states */
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#define FSL_FEATURE_SCT_NUMBER_OF_STATES (32)
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/* @brief Number of match capture */
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#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16)
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/* @brief Number of outputs */
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#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10)
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/* SDIF module features */
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/* @brief FIFO depth, every location is a WORD */
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#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64)
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/* @brief Max DMA buffer size */
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#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096)
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/* @brief Max source clock in HZ */
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#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000)
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/* @brief support 2 cards */
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#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1)
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/* SECPINT module features */
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/* @brief Number of connected outputs */
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#define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2)
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/* SPI module features */
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/* @brief SSEL pin count. */
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#define FSL_FEATURE_SPI_SSEL_COUNT (4)
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/* SYSCON module features */
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/* @brief Flash page size in bytes */
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#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512)
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/* @brief Flash sector size in bytes */
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#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768)
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/* @brief Flash size in bytes */
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#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (645120)
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/* @brief Has Power Down mode */
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#define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1)
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/* @brief CCM_ANALOG availability on the SoC. */
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#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1)
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/* @brief Starter register discontinuous. */
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#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1)
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/* SYSCTL1 module features */
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/* No feature definitions */
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/* USB module features */
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/* @brief Size of the USB dedicated RAM */
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#define FSL_FEATURE_USB_USB_RAM (0x00004000)
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/* @brief Base address of the USB dedicated RAM */
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#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000)
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/* @brief USB version */
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#define FSL_FEATURE_USB_VERSION (200)
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/* @brief Number of the endpoint in USB FS */
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#define FSL_FEATURE_USB_EP_NUM (5)
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/* USBFSH module features */
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/* @brief Size of the USB dedicated RAM */
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#define FSL_FEATURE_USBFSH_USB_RAM (0x00004000)
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/* @brief Base address of the USB dedicated RAM */
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#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000)
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/* @brief USBFSH version */
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#define FSL_FEATURE_USBFSH_VERSION (200)
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/* USBHSD module features */
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/* @brief Size of the USB dedicated RAM */
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#define FSL_FEATURE_USBHSD_USB_RAM (0x00004000)
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/* @brief Base address of the USB dedicated RAM */
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#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000)
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/* @brief USBHSD version */
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#define FSL_FEATURE_USBHSD_VERSION (300)
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/* @brief Number of the endpoint in USB HS */
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#define FSL_FEATURE_USBHSD_EP_NUM (6)
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/* USBHSH module features */
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/* @brief Size of the USB dedicated RAM */
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#define FSL_FEATURE_USBHSH_USB_RAM (0x00004000)
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/* @brief Base address of the USB dedicated RAM */
|
|
#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000)
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/* @brief USBHSH version */
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#define FSL_FEATURE_USBHSH_VERSION (300)
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/* USBPHY module features */
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/* @brief Size of the USB dedicated RAM */
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#define FSL_FEATURE_USBPHY_USB_RAM (0x00004000)
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/* @brief Base address of the USB dedicated RAM */
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|
#define FSL_FEATURE_USBPHY_USB_RAM_BASE_ADDRESS (0x40100000)
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/* @brief USBHSD version */
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#define FSL_FEATURE_USBPHY_VERSION (300)
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/* @brief Number of the endpoint in USB HS */
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#define FSL_FEATURE_USBPHY_EP_NUM (6)
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/* WWDT module features */
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/* @brief Has no RESET register. */
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#define FSL_FEATURE_WWDT_HAS_NO_RESET (1)
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/* @brief WWDT does not support oscillator lock. */
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#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1)
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#endif /* _LPC55S69_cm33_core1_FEATURES_H_ */
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