578 lines
20 KiB
C
578 lines
20 KiB
C
/*
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2022 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_ctimer.h"
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.ctimer"
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#endif
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Gets the instance from the base address
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*
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* @param base Ctimer peripheral base address
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*
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* @return The Timer instance
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*/
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static uint32_t CTIMER_GetInstance(CTIMER_Type *base);
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/*!
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* @brief CTIMER generic IRQ handle function.
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*
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* @param index FlexCAN peripheral instance index.
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*/
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static void CTIMER_GenericIRQHandler(uint32_t index);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*! @brief Pointers to Timer bases for each instance. */
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static CTIMER_Type *const s_ctimerBases[] = CTIMER_BASE_PTRS;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/*! @brief Pointers to Timer clocks for each instance. */
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static const clock_ip_name_t s_ctimerClocks[] = CTIMER_CLOCKS;
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET))
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#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
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#if defined(FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET
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/*! @brief Pointers to Timer resets for each instance, writing a zero asserts the reset */
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static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS_N;
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#else
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/*! @brief Pointers to Timer resets for each instance, writing a one asserts the reset */
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static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS;
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#endif
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#endif
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#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
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/*! @brief Pointers real ISRs installed by drivers for each instance. */
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static ctimer_callback_t *s_ctimerCallback[sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])] = {0};
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/*! @brief Callback type installed by drivers for each instance. */
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static ctimer_callback_type_t ctimerCallbackType[sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])] = {
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kCTIMER_SingleCallback};
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/*! @brief Array to map timer instance to IRQ number. */
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static const IRQn_Type s_ctimerIRQ[] = CTIMER_IRQS;
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/*******************************************************************************
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* Code
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******************************************************************************/
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static uint32_t CTIMER_GetInstance(CTIMER_Type *base)
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{
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uint32_t instance;
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uint32_t ctimerArrayCount = (sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0]));
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ctimerArrayCount; instance++)
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{
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if (s_ctimerBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ctimerArrayCount);
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return instance;
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}
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/*!
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* brief Ungates the clock and configures the peripheral for basic operation.
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*
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* note This API should be called at the beginning of the application before using the driver.
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*
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* param base Ctimer peripheral base address
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* param config Pointer to the user configuration structure.
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*/
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void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config)
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{
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assert(config != NULL);
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Enable the timer clock*/
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CLOCK_EnableClock(s_ctimerClocks[CTIMER_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
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/* Reset the module. */
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#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET))
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RESET_PeripheralReset(s_ctimerResets[CTIMER_GetInstance(base)]);
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#endif
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#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
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/* Setup the cimer mode and count select */
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#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE))
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base->CTCR = CTIMER_CTCR_CTMODE(config->mode) | CTIMER_CTCR_CINSEL(config->input);
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#endif
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/* Setup the timer prescale value */
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base->PR = CTIMER_PR_PRVAL(config->prescale);
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}
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/*!
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* brief Gates the timer clock.
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*
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* param base Ctimer peripheral base address
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*/
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void CTIMER_Deinit(CTIMER_Type *base)
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{
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uint32_t index = CTIMER_GetInstance(base);
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/* Stop the timer */
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base->TCR &= ~CTIMER_TCR_CEN_MASK;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Disable the timer clock*/
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CLOCK_DisableClock(s_ctimerClocks[index]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* Disable IRQ at NVIC Level */
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(void)DisableIRQ(s_ctimerIRQ[index]);
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}
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/*!
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* brief Fills in the timers configuration structure with the default settings.
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*
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* The default values are:
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* code
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* config->mode = kCTIMER_TimerMode;
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* config->input = kCTIMER_Capture_0;
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* config->prescale = 0;
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* endcode
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* param config Pointer to the user configuration structure.
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*/
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void CTIMER_GetDefaultConfig(ctimer_config_t *config)
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{
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assert(config != NULL);
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/* Initializes the configure structure to zero. */
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(void)memset(config, 0, sizeof(*config));
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/* Run as a timer */
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config->mode = kCTIMER_TimerMode;
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/* This field is ignored when mode is timer */
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config->input = kCTIMER_Capture_0;
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/* Timer counter is incremented on every APB bus clock */
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config->prescale = 0;
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}
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/*!
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* brief Configures the PWM signal parameters.
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*
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* Enables PWM mode on the match channel passed in and will then setup the match value
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* and other match parameters to generate a PWM signal.
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* This function can manually assign the specified channel to set the PWM cycle.
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*
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* note When setting PWM output from multiple output pins, all should use the same PWM
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* frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution.
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*
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* param base Ctimer peripheral base address
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* param pwmPeriodChannel Specify the channel to control the PWM period
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* param matchChannel Match pin to be used to output the PWM signal
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* param dutyCyclePercent PWM pulse width; the value should be between 0 to 100
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* param pwmFreq_Hz PWM signal frequency in Hz
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* param srcClock_Hz Timer counter clock in Hz
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* param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse,
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* if it is 0 then no interrupt will be generated.
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*
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* return kStatus_Success on success
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* kStatus_Fail If matchChannel is equal to pwmPeriodChannel; this channel is reserved to set the PWM cycle
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*/
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status_t CTIMER_SetupPwm(CTIMER_Type *base,
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const ctimer_match_t pwmPeriodChannel,
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ctimer_match_t matchChannel,
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uint8_t dutyCyclePercent,
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uint32_t pwmFreq_Hz,
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uint32_t srcClock_Hz,
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bool enableInt)
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{
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assert(pwmFreq_Hz > 0U);
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uint32_t reg;
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uint32_t period, pulsePeriod = 0;
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uint32_t timerClock = srcClock_Hz / (base->PR + 1U);
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uint32_t index = CTIMER_GetInstance(base);
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if (matchChannel == pwmPeriodChannel)
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{
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return kStatus_Fail;
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}
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/* Enable PWM mode on the match channel */
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base->PWMC |= (1UL << (uint32_t)matchChannel);
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/* Clear the stop, reset and interrupt bits for this channel */
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reg = base->MCR;
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reg &=
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~(((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK))
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<< ((uint32_t)matchChannel * 3U));
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/* If call back function is valid then enable match interrupt for the channel */
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if (enableInt)
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{
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reg |= (((uint32_t)CTIMER_MCR_MR0I_MASK) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U)));
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}
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/* Reset the counter when match on PWM period channel (pwmPeriodChannel) */
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reg |= ((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK) << ((uint32_t)pwmPeriodChannel * 3U));
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base->MCR = reg;
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/* Calculate PWM period match value */
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period = (timerClock / pwmFreq_Hz) - 1U;
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/* Calculate pulse width match value */
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if (dutyCyclePercent == 0U)
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{
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pulsePeriod = period + 1U;
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}
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else
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{
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pulsePeriod = (period * (100U - (uint32_t)dutyCyclePercent)) / 100U;
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}
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/* Specified channel pwmPeriodChannel will define the PWM period */
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base->MR[pwmPeriodChannel] = period;
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/* This will define the PWM pulse period */
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base->MR[matchChannel] = pulsePeriod;
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/* Clear status flags */
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CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel);
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/* If call back function is valid then enable interrupt and update the call back function */
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if (enableInt)
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{
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(void)EnableIRQ(s_ctimerIRQ[index]);
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}
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return kStatus_Success;
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}
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/*!
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* brief Configures the PWM signal parameters.
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*
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* Enables PWM mode on the match channel passed in and will then setup the match value
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* and other match parameters to generate a PWM signal.
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* This function can manually assign the specified channel to set the PWM cycle.
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*
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* note When setting PWM output from multiple output pins, all should use the same PWM
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* period
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*
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* param base Ctimer peripheral base address
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* param pwmPeriodChannel Specify the channel to control the PWM period
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* param matchChannel Match pin to be used to output the PWM signal
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* param pwmPeriod PWM period match value
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* param pulsePeriod Pulse width match value
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* param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse,
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* if it is 0 then no interrupt will be generated.
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*
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* return kStatus_Success on success
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* kStatus_Fail If matchChannel is equal to pwmPeriodChannel; this channel is reserved to set the PWM period
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*/
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status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base,
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const ctimer_match_t pwmPeriodChannel,
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ctimer_match_t matchChannel,
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uint32_t pwmPeriod,
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uint32_t pulsePeriod,
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bool enableInt)
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{
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/* Some CTimers only have 16bits , so the value is limited*/
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#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B
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assert(!((FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32) && (pulsePeriod > 0xFFFFU)));
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#endif
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uint32_t reg;
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uint32_t index = CTIMER_GetInstance(base);
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if (matchChannel == pwmPeriodChannel)
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{
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return kStatus_Fail;
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}
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/* Enable PWM mode on PWM pulse channel */
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base->PWMC |= (1UL << (uint32_t)matchChannel);
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/* Clear the stop, reset and interrupt bits for PWM pulse channel */
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reg = base->MCR;
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reg &=
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~((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK)
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<< ((uint32_t)matchChannel * 3U));
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/* If call back function is valid then enable match interrupt for PWM pulse channel */
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if (enableInt)
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{
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reg |= (((uint32_t)CTIMER_MCR_MR0I_MASK) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U)));
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}
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/* Reset the counter when match on PWM period channel (pwmPeriodChannel) */
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reg |= ((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK) << ((uint32_t)pwmPeriodChannel * 3U));
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base->MCR = reg;
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/* Specified channel pwmPeriodChannel will define the PWM period */
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base->MR[pwmPeriodChannel] = pwmPeriod;
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/* This will define the PWM pulse period */
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base->MR[matchChannel] = pulsePeriod;
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/* Clear status flags */
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CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel);
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/* If call back function is valid then enable interrupt and update the call back function */
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if (enableInt)
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{
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(void)EnableIRQ(s_ctimerIRQ[index]);
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}
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return kStatus_Success;
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}
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/*!
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* brief Updates the duty cycle of an active PWM signal.
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*
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* note Please use CTIMER_SetupPwmPeriod to update the PWM with high resolution.
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* This function can manually assign the specified channel to set the PWM cycle.
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*
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* param base Ctimer peripheral base address
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* param pwmPeriodChannel Specify the channel to control the PWM period
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* param matchChannel Match pin to be used to output the PWM signal
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* param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100
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*/
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void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base,
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const ctimer_match_t pwmPeriodChannel,
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ctimer_match_t matchChannel,
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uint8_t dutyCyclePercent)
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{
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uint32_t pulsePeriod = 0, period;
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/* Specified channel pwmPeriodChannel defines the PWM period */
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period = base->MR[pwmPeriodChannel];
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/* For 0% dutycyle, make pulse period greater than period so the event will never occur */
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if (dutyCyclePercent == 0U)
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{
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pulsePeriod = period + 1U;
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}
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else
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{
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pulsePeriod = (period * (100U - (uint32_t)dutyCyclePercent)) / 100U;
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}
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/* Update dutycycle */
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base->MR[matchChannel] = pulsePeriod;
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}
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/*!
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* brief Setup the match register.
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*
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* User configuration is used to setup the match value and action to be taken when a match occurs.
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*
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* param base Ctimer peripheral base address
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* param matchChannel Match register to configure
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* param config Pointer to the match configuration structure
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*/
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void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config)
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{
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/* Some CTimers only have 16bits , so the value is limited*/
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#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B
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assert(!(FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32 && config->matchValue > 0xFFFFU));
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#endif
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uint32_t reg;
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uint32_t index = CTIMER_GetInstance(base);
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/* Set the counter operation when a match on this channel occurs */
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reg = base->MCR;
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reg &=
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~((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK)
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<< ((uint32_t)matchChannel * 3U));
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reg |= ((uint32_t)(config->enableCounterReset) << (CTIMER_MCR_MR0R_SHIFT + ((uint32_t)matchChannel * 3U)));
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reg |= ((uint32_t)(config->enableCounterStop) << (CTIMER_MCR_MR0S_SHIFT + ((uint32_t)matchChannel * 3U)));
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reg |= ((uint32_t)(config->enableInterrupt) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U)));
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base->MCR = reg;
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reg = base->EMR;
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/* Set the match output operation when a match on this channel occurs */
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reg &= ~(((uint32_t)CTIMER_EMR_EMC0_MASK) << ((uint32_t)matchChannel * 2U));
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reg |= ((uint32_t)config->outControl) << (CTIMER_EMR_EMC0_SHIFT + ((uint32_t)matchChannel * 2U));
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/* Set the initial state of the EM bit/output */
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reg &= ~(((uint32_t)CTIMER_EMR_EM0_MASK) << (uint32_t)matchChannel);
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reg |= ((uint32_t)config->outPinInitState) << (uint32_t)matchChannel;
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base->EMR = reg;
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/* Set the match value */
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base->MR[matchChannel] = config->matchValue;
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/* Clear status flags */
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CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel);
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/* If interrupt is enabled then enable interrupt and update the call back function */
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if (config->enableInterrupt)
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{
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(void)EnableIRQ(s_ctimerIRQ[index]);
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}
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}
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/*!
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* brief Get the status of output match.
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*
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* This function gets the status of output MAT, whether or not this output is connected to a pin.
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* This status is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
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*
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* param base Ctimer peripheral base address
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* param matchChannel External match channel, user can obtain the status of multiple match channels
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* at the same time by using the logic of "|"
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* enumeration ::ctimer_external_match_t
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* return The mask of external match channel status flags. Users need to use the
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* _ctimer_external_match type to decode the return variables.
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*/
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uint32_t CTIMER_GetOutputMatchStatus(CTIMER_Type *base, uint32_t matchChannel)
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{
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return (base->EMR & matchChannel);
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}
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#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE))
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/*!
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* brief Setup the capture.
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*
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* param base Ctimer peripheral base address
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* param capture Capture channel to configure
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* param edge Edge on the channel that will trigger a capture
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* param enableInt Flag to enable channel interrupts, if enabled then the registered call back
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* is called upon capture
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*/
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void CTIMER_SetupCapture(CTIMER_Type *base,
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ctimer_capture_channel_t capture,
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ctimer_capture_edge_t edge,
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bool enableInt)
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{
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uint32_t reg = base->CCR;
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uint32_t index = CTIMER_GetInstance(base);
|
|
|
|
/* Set the capture edge */
|
|
reg &= ~((uint32_t)((uint32_t)CTIMER_CCR_CAP0RE_MASK | (uint32_t)CTIMER_CCR_CAP0FE_MASK |
|
|
(uint32_t)CTIMER_CCR_CAP0I_MASK)
|
|
<< ((uint32_t)capture * 3U));
|
|
reg |= ((uint32_t)edge) << (CTIMER_CCR_CAP0RE_SHIFT + ((uint32_t)capture * 3U));
|
|
/* Clear status flags */
|
|
CTIMER_ClearStatusFlags(base, (((uint32_t)kCTIMER_Capture0Flag) << (uint32_t)capture));
|
|
/* If call back function is valid then enable capture interrupt for the channel and update the call back function */
|
|
if (enableInt)
|
|
{
|
|
reg |= ((uint32_t)CTIMER_CCR_CAP0I_MASK) << ((uint32_t)capture * 3U);
|
|
(void)EnableIRQ(s_ctimerIRQ[index]);
|
|
}
|
|
base->CCR = reg;
|
|
}
|
|
#endif
|
|
|
|
/*!
|
|
* brief Register callback.
|
|
*
|
|
* param base Ctimer peripheral base address
|
|
* param cb_func callback function
|
|
* param cb_type callback function type, singular or multiple
|
|
*/
|
|
void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type)
|
|
{
|
|
uint32_t index = CTIMER_GetInstance(base);
|
|
s_ctimerCallback[index] = cb_func;
|
|
ctimerCallbackType[index] = cb_type;
|
|
}
|
|
|
|
/*!
|
|
* brief CTIMER generic IRQ handle function.
|
|
*
|
|
* param index FlexCAN peripheral instance index.
|
|
*/
|
|
static void CTIMER_GenericIRQHandler(uint32_t index)
|
|
{
|
|
uint32_t int_stat, i, mask;
|
|
/* Get Interrupt status flags */
|
|
int_stat = CTIMER_GetStatusFlags(s_ctimerBases[index]);
|
|
/* Clear the status flags that were set */
|
|
CTIMER_ClearStatusFlags(s_ctimerBases[index], int_stat);
|
|
if (ctimerCallbackType[index] == kCTIMER_SingleCallback)
|
|
{
|
|
if (s_ctimerCallback[index][0] != NULL)
|
|
{
|
|
s_ctimerCallback[index][0](int_stat);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
#if defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE
|
|
for (i = 0; i <= CTIMER_IR_MR3INT_SHIFT; i++)
|
|
#else
|
|
#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT
|
|
for (i = 0; i <= CTIMER_IR_CR3INT_SHIFT; i++)
|
|
#else
|
|
#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) && FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT)
|
|
for (i = 0; i <= CTIMER_IR_CR2INT_SHIFT; i++)
|
|
#else
|
|
for (i = 0; i <= CTIMER_IR_CR1INT_SHIFT; i++)
|
|
#endif /* FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT */
|
|
#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */
|
|
#endif
|
|
{
|
|
mask = 0x01UL << i;
|
|
/* For each status flag bit that was set call the callback function if it is valid */
|
|
if (((int_stat & mask) != 0U) && (s_ctimerCallback[index][i] != NULL))
|
|
{
|
|
s_ctimerCallback[index][i](int_stat);
|
|
}
|
|
}
|
|
}
|
|
SDK_ISR_EXIT_BARRIER;
|
|
}
|
|
|
|
/* IRQ handler functions overloading weak symbols in the startup */
|
|
#if defined(CTIMER0)
|
|
void CTIMER0_DriverIRQHandler(void);
|
|
void CTIMER0_DriverIRQHandler(void)
|
|
{
|
|
CTIMER_GenericIRQHandler(0);
|
|
SDK_ISR_EXIT_BARRIER;
|
|
}
|
|
#endif
|
|
|
|
#if defined(CTIMER1)
|
|
void CTIMER1_DriverIRQHandler(void);
|
|
void CTIMER1_DriverIRQHandler(void)
|
|
{
|
|
CTIMER_GenericIRQHandler(1);
|
|
SDK_ISR_EXIT_BARRIER;
|
|
}
|
|
#endif
|
|
|
|
#if defined(CTIMER2)
|
|
void CTIMER2_DriverIRQHandler(void);
|
|
void CTIMER2_DriverIRQHandler(void)
|
|
{
|
|
CTIMER_GenericIRQHandler(2);
|
|
SDK_ISR_EXIT_BARRIER;
|
|
}
|
|
#endif
|
|
|
|
#if defined(CTIMER3)
|
|
void CTIMER3_DriverIRQHandler(void);
|
|
void CTIMER3_DriverIRQHandler(void)
|
|
{
|
|
CTIMER_GenericIRQHandler(3);
|
|
SDK_ISR_EXIT_BARRIER;
|
|
}
|
|
#endif
|
|
|
|
#if defined(CTIMER4)
|
|
void CTIMER4_DriverIRQHandler(void);
|
|
void CTIMER4_DriverIRQHandler(void)
|
|
{
|
|
CTIMER_GenericIRQHandler(4);
|
|
SDK_ISR_EXIT_BARRIER;
|
|
}
|
|
#endif
|