314 lines
11 KiB
C
314 lines
11 KiB
C
/*
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2023 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef FSL_MAILBOX_H_
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#define FSL_MAILBOX_H_
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#include "fsl_common.h"
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/*!
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* @addtogroup mailbox
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* @{
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*/
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/*! @file */
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/******************************************************************************
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* Definitions
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*****************************************************************************/
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.mailbox"
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#endif
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/*! @name Driver version */
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/*! @{ */
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/*! @brief MAILBOX driver version 2.3.0. */
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#define FSL_MAILBOX_DRIVER_VERSION (MAKE_VERSION(2, 3, 1))
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/*! @} */
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/*!
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* @brief CPU ID.
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*/
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#if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES) || \
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defined(LPC55S66_cm33_core0_SERIES) || defined(LPC55S66_cm33_core1_SERIES))
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typedef enum _mailbox_cpu_id
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{
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kMAILBOX_CM33_Core1 = 0,
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kMAILBOX_CM33_Core0
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} mailbox_cpu_id_t;
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#elif ((defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES)))
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typedef enum _mailbox_cpu_id
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{
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kMAILBOX_CM0Plus = 0,
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kMAILBOX_CM4
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} mailbox_cpu_id_t;
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#elif (defined(MCXN947_cm33_core0_SERIES) || defined(MCXN947_cm33_core1_SERIES) || \
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defined(MCXN547_cm33_core0_SERIES) || defined(MCXN547_cm33_core1_SERIES))
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typedef enum _mailbox_cpu_id
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{
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kMAILBOX_CM33_Core0 = 0,
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kMAILBOX_CM33_Core1
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} mailbox_cpu_id_t;
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#endif
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#if (defined(CPU_NXH2004J640UK48))
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typedef enum _mailbox_id
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{
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kMAILBOX_CM0Plus_Core0 = 0,
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kMAILBOX_CM0Plus_Core1,
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kMAILBOX_CM0Plus_Sw_Irq0,
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kMAILBOX_CM0Plus_Sw_Irq1,
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kMAILBOX_CM0Plus_Sw_Irq2,
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kMAILBOX_CM0Plus_Sw_Irq3
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} mailbox_id_t;
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#endif
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/*******************************************************************************
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* API
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******************************************************************************/
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*!
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* @name MAILBOX initialization
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* @{
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*/
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/*!
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* @brief Initializes the MAILBOX module.
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*
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* This function enables the MAILBOX clock only.
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*
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* @param base MAILBOX peripheral base address.
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*/
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static inline void MAILBOX_Init(MAILBOX_Type *base)
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{
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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CLOCK_EnableClock(kCLOCK_Mailbox);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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#if !(defined(FSL_FEATURE_MAILBOX_HAS_NO_RESET) && FSL_FEATURE_MAILBOX_HAS_NO_RESET)
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/* Reset the MAILBOX module */
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RESET_PeripheralReset(kMAILBOX_RST_SHIFT_RSTn);
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#endif
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}
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/*!
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* @brief De-initializes the MAILBOX module.
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*
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* This function disables the MAILBOX clock only.
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*
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* @param base MAILBOX peripheral base address.
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*/
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static inline void MAILBOX_Deinit(MAILBOX_Type *base)
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{
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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CLOCK_DisableClock(kCLOCK_Mailbox);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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/*! @} */
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#if ((defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES)) || \
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defined(LPC55S66_cm33_core0_SERIES) || defined(LPC55S66_cm33_core1_SERIES) || \
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defined(MCXN947_cm33_core0_SERIES) || defined(MCXN947_cm33_core1_SERIES) || defined(MCXN547_cm33_core0_SERIES) || \
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defined(MCXN547_cm33_core1_SERIES) || defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES))
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/*!
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* @brief Set data value in the mailbox based on the CPU ID.
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*
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* @param base MAILBOX peripheral base address.
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* @param cpu_id CPU id, kMAILBOX_CM0Plus or kMAILBOX_CM4 for LPC5410x and LPC5411x devices,
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* kMAILBOX_CM33_Core0 or kMAILBOX_CM33_Core1 for LPC55S69 devices.
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* @param mboxData Data to send in the mailbox.
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*
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* @note Sets a data value to send via the MAILBOX to the other core.
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*/
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static inline void MAILBOX_SetValue(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id, uint32_t mboxData)
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{
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#if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES) || \
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defined(LPC55S66_cm33_core0_SERIES) || defined(LPC55S66_cm33_core1_SERIES) || \
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defined(MCXN947_cm33_core0_SERIES) || defined(MCXN947_cm33_core1_SERIES) || defined(MCXN547_cm33_core0_SERIES) || \
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defined(MCXN547_cm33_core1_SERIES))
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assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1));
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#elif ((defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES)))
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assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4));
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#endif
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base->MBOXIRQ[cpu_id].IRQ = mboxData;
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}
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/*!
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* @brief Get data in the mailbox based on the CPU ID.
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*
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* @param base MAILBOX peripheral base address.
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* @param cpu_id CPU id, kMAILBOX_CM0Plus or kMAILBOX_CM4 for LPC5410x and LPC5411x devices,
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* kMAILBOX_CM33_Core0 or kMAILBOX_CM33_Core1 for LPC55S69 devices.
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*
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* @return Current mailbox data.
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*/
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static inline uint32_t MAILBOX_GetValue(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id)
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{
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#if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES) || \
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defined(LPC55S66_cm33_core0_SERIES) || defined(LPC55S66_cm33_core1_SERIES) || \
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defined(MCXN947_cm33_core0_SERIES) || defined(MCXN947_cm33_core1_SERIES) || defined(MCXN547_cm33_core0_SERIES) || \
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defined(MCXN547_cm33_core1_SERIES))
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assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1));
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#elif ((defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES)))
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assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4));
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#endif
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return base->MBOXIRQ[cpu_id].IRQ;
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}
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/*!
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* @brief Set data bits in the mailbox based on the CPU ID.
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*
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* @param base MAILBOX peripheral base address.
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* @param cpu_id CPU id, kMAILBOX_CM0Plus or kMAILBOX_CM4 for LPC5410x and LPC5411x devices,
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* kMAILBOX_CM33_Core0 or kMAILBOX_CM33_Core1 for LPC55S69 devices.
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* @param mboxSetBits Data bits to set in the mailbox.
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*
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* @note Sets data bits to send via the MAILBOX to the other core. A value of 0 will
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* do nothing. Only sets bits selected with a 1 in it's bit position.
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*/
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static inline void MAILBOX_SetValueBits(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id, uint32_t mboxSetBits)
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{
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#if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES) || \
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defined(LPC55S66_cm33_core0_SERIES) || defined(LPC55S66_cm33_core1_SERIES) || \
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defined(MCXN947_cm33_core0_SERIES) || defined(MCXN947_cm33_core1_SERIES) || defined(MCXN547_cm33_core0_SERIES) || \
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defined(MCXN547_cm33_core1_SERIES))
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assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1));
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#elif ((defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES)))
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assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4));
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#endif
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base->MBOXIRQ[cpu_id].IRQSET = mboxSetBits;
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}
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/*!
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* @brief Clear data bits in the mailbox based on the CPU ID.
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*
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* @param base MAILBOX peripheral base address.
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* @param cpu_id CPU id, kMAILBOX_CM0Plus or kMAILBOX_CM4 for LPC5410x and LPC5411x devices,
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* kMAILBOX_CM33_Core0 or kMAILBOX_CM33_Core1 for LPC55S69 devices.
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* @param mboxClrBits Data bits to clear in the mailbox.
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*
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* @note Clear data bits to send via the MAILBOX to the other core. A value of 0 will
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* do nothing. Only clears bits selected with a 1 in it's bit position.
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*/
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static inline void MAILBOX_ClearValueBits(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id, uint32_t mboxClrBits)
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{
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#if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES) || \
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defined(LPC55S66_cm33_core0_SERIES) || defined(LPC55S66_cm33_core1_SERIES) || \
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defined(MCXN947_cm33_core0_SERIES) || defined(MCXN947_cm33_core1_SERIES) || defined(MCXN547_cm33_core0_SERIES) || \
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defined(MCXN547_cm33_core1_SERIES))
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assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1));
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#elif ((defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES)))
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assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4));
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#endif
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base->MBOXIRQ[cpu_id].IRQCLR = mboxClrBits;
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}
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#elif (defined(CPU_NXH2004J640UK48))
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/*!
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* @brief Set data value in the mailbox based on the Mailbox ID.
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*
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* @param base MAILBOX peripheral base address.
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* @param id Mailbox Index for NXH2004 devices
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* @param mboxData Data to send in the mailbox.
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*
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*/
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static inline void MAILBOX_SetValue(MAILBOX_Type *base, mailbox_id_t id, uint32_t mboxData)
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{
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assert((id >= kMAILBOX_CM0Plus_Core0) && (id <= kMAILBOX_CM0Plus_Sw_Irq3));
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base->MBOXIRQ[id].IRQ = mboxData;
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}
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/*!
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* @brief Get data in the mailbox based on the Mailbox ID.
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*
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* @param base MAILBOX peripheral base address.
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* @param id, Mailbox index for NXH2004 devies.
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*
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* @return Current mailbox data.
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*/
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static inline uint32_t MAILBOX_GetValue(MAILBOX_Type *base, mailbox_id_t id)
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{
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assert((id >= kMAILBOX_CM0Plus_Core0) && (id <= kMAILBOX_CM0Plus_Sw_Irq3));
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return base->MBOXIRQ[id].IRQ;
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}
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/*!
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* @brief Set data bits in the mailbox based on the Mailbox Index.
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*
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* @param base MAILBOX peripheral base address.
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* @param id Mailbox Index for NXH2004 devices
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* @param mboxSetBits Data bits to set in the mailbox.
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*
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* @note Sets data bits to send via the MAILBOX. A value of 0 will
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* do nothing. Only sets bits selected with a 1 in it's bit position.
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*/
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static inline void MAILBOX_SetValueBits(MAILBOX_Type *base, mailbox_id_t id, uint32_t mboxSetBits)
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{
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assert((id >= kMAILBOX_CM0Plus_Core0) && (id <= kMAILBOX_CM0Plus_Sw_Irq3));
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base->MBOXIRQ[id].IRQSET = mboxSetBits;
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}
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/*!
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* @brief Clear data bits in the mailbox based on the Mailbox ID.
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*
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* @param base MAILBOX peripheral base address.
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* @param id, Index to Mailbox for NXH2004 devices.
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* @param mboxClrBits Data bits to clear in the mailbox.
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*
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* @note Clear data bits to send via the MAILBOX. A value of 0 will do
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* nothing. Only clears bits selected with a 1 in it's bit position.
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*/
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static inline void MAILBOX_ClearValueBits(MAILBOX_Type *base, mailbox_id_t id, uint32_t mboxClrBits)
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{
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assert((id >= kMAILBOX_CM0Plus_Core0) && (id <= kMAILBOX_CM0Plus_Sw_Irq3));
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base->MBOXIRQ[id].IRQCLR = mboxClrBits;
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}
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#endif /*CPU_NXH2004J640UK48*/
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/*!
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* @brief Get MUTEX state and lock mutex
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*
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* @param base MAILBOX peripheral base address.
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*
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* @return See note
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*
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* @note Returns '1' if the mutex was taken or '0' if another resources has the
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* mutex locked. Once a mutex is taken, it can be returned with the MAILBOX_SetMutex()
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* function.
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*/
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static inline uint32_t MAILBOX_GetMutex(MAILBOX_Type *base)
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{
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return (base->MUTEX & MAILBOX_MUTEX_EX_MASK);
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}
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/*!
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* @brief Set MUTEX state
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*
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* @param base MAILBOX peripheral base address.
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*
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* @note Sets mutex state to '1' and allows other resources to get the mutex.
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*/
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static inline void MAILBOX_SetMutex(MAILBOX_Type *base)
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{
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base->MUTEX = MAILBOX_MUTEX_EX_MASK;
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}
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#if defined(__cplusplus)
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}
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#endif /*_cplusplus*/
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/*! @} */
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#endif /* FSL_MAILBOX_H_ */
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