1029 lines
32 KiB
C
1029 lines
32 KiB
C
/*
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2023 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_pint.h"
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.pint"
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#endif
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/*******************************************************************************
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* Variables
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******************************************************************************/
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#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
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/*! @brief Irq number array */
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static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS +
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FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS;
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/*! @brief Callback function array for SECPINT(s). */
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static pint_cb_t s_secpintCallback[FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS];
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#else
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/*! @brief Irq number array */
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static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS;
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#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */
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/*! @brief Callback function array for PINT(s). */
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static pint_cb_t s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS];
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/*******************************************************************************
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* Code
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******************************************************************************/
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/*!
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* brief Initialize PINT peripheral.
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* This function initializes the PINT peripheral and enables the clock.
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*
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* param base Base address of the PINT peripheral.
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*
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* retval None.
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*/
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void PINT_Init(PINT_Type *base)
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{
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uint32_t i;
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uint32_t pmcfg = 0;
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uint8_t pintcount = 0;
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assert(base != NULL);
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if (base == PINT)
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{
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pintcount = FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS;
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/* clear PINT callback array*/
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for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
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{
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s_pintCallback[i] = NULL;
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}
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}
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else
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{
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#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
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pintcount = FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS;
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/* clear SECPINT callback array*/
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for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
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{
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s_secpintCallback[i] = NULL;
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}
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#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */
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}
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/* Disable all bit slices for pint*/
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for (i = 0; i < pintcount; i++)
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{
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pmcfg = pmcfg | ((uint32_t)kPINT_PatternMatchNever << (PININT_BITSLICE_CFG_START + (i * 3U)));
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}
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#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1)
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Enable the clock. */
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CLOCK_EnableClock(kCLOCK_GpioInt);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
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/* Reset the module. */
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RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn);
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#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
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#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0)
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if (base == PINT)
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{
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Enable the clock. */
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CLOCK_EnableClock(kCLOCK_Gpio0);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
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/* Reset the module. */
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RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn);
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#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
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}
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else
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{
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#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Enable the clock. */
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CLOCK_EnableClock(kCLOCK_Gpio_Sec);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
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/* Reset the module. */
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RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn);
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#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
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#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */
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}
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#else
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if (base == PINT)
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{
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Enable the clock. */
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CLOCK_EnableClock(kCLOCK_Pint);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
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/* Reset the module. */
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RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn);
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#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
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}
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else
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{
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/* if need config SECURE PINT device,then enable secure pint interrupt clock */
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#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Enable the clock. */
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CLOCK_EnableClock(kCLOCK_Gpio_Sec_Int);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
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/* Reset the module. */
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RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn);
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#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
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#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */
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}
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#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */
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/* Disable all pattern match bit slices */
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base->PMCFG = pmcfg;
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}
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/*!
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* brief Configure PINT peripheral pin interrupt.
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* This function configures a given pin interrupt.
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*
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* param base Base address of the PINT peripheral.
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* param intr Pin interrupt.
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* param enable Selects detection logic.
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* param callback Callback.
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*
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* retval None.
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*/
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void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback)
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{
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assert(base != NULL);
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/* Clear Rise and Fall flags first */
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PINT_PinInterruptClrRiseFlag(base, intr);
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PINT_PinInterruptClrFallFlag(base, intr);
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/* Security PINT uses additional callback array */
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if (base == PINT)
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{
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s_pintCallback[intr] = callback;
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}
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else
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{
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#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
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s_secpintCallback[intr] = callback;
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#endif
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}
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/* select level or edge sensitive */
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base->ISEL = (base->ISEL & ~(1UL << (uint32_t)intr)) |
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((((uint32_t)enable & PINT_PIN_INT_LEVEL) != 0U) ? (1UL << (uint32_t)intr) : 0U);
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/* enable rising or level interrupt */
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if (((unsigned)enable & (PINT_PIN_INT_LEVEL | PINT_PIN_INT_RISE)) != 0U)
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{
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base->SIENR = 1UL << (uint32_t)intr;
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}
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else
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{
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base->CIENR = 1UL << (uint32_t)intr;
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}
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/* Enable falling or select high level */
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if (((unsigned)enable & PINT_PIN_INT_FALL_OR_HIGH_LEVEL) != 0U)
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{
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base->SIENF = 1UL << (uint32_t)intr;
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}
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else
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{
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base->CIENF = 1UL << (uint32_t)intr;
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}
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}
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/*!
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* brief Get PINT peripheral pin interrupt configuration.
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* This function returns the configuration of a given pin interrupt.
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*
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* param base Base address of the PINT peripheral.
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* param pintr Pin interrupt.
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* param enable Pointer to store the detection logic.
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* param callback Callback.
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*
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* retval None.
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*/
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void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback)
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{
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uint32_t mask;
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bool level;
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assert(base != NULL);
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*enable = kPINT_PinIntEnableNone;
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level = false;
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mask = 1UL << (uint32_t)pintr;
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if ((base->ISEL & mask) != 0U)
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{
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/* Pin interrupt is level sensitive */
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level = true;
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}
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if ((base->IENR & mask) != 0U)
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{
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if (level)
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{
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/* Level interrupt is enabled */
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*enable = kPINT_PinIntEnableLowLevel;
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}
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else
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{
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/* Rising edge interrupt */
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*enable = kPINT_PinIntEnableRiseEdge;
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}
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}
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if ((base->IENF & mask) != 0U)
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{
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if (level)
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{
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/* Level interrupt is active high */
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*enable = kPINT_PinIntEnableHighLevel;
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}
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else
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{
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/* Either falling or both edge */
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if (*enable == kPINT_PinIntEnableRiseEdge)
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{
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/* Rising and faling edge */
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*enable = kPINT_PinIntEnableBothEdges;
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}
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else
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{
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/* Falling edge */
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*enable = kPINT_PinIntEnableFallEdge;
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}
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}
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}
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/* Security PINT uses additional callback array */
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if (base == PINT)
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{
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*callback = s_pintCallback[pintr];
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}
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else
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{
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#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
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*callback = s_secpintCallback[pintr];
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#endif
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}
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}
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/*!
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* brief Configure PINT pattern match.
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* This function configures a given pattern match bit slice.
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*
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* param base Base address of the PINT peripheral.
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* param bslice Pattern match bit slice number.
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* param cfg Pointer to bit slice configuration.
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*
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* retval None.
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*/
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void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg)
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{
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uint32_t src_shift;
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uint32_t cfg_shift;
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uint32_t pmcfg;
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uint32_t tmp_src_shift = PININT_BITSLICE_SRC_MASK;
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uint32_t tmp_cfg_shift = PININT_BITSLICE_CFG_MASK;
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assert(base != NULL);
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src_shift = PININT_BITSLICE_SRC_START + ((uint32_t)bslice * 3UL);
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cfg_shift = PININT_BITSLICE_CFG_START + ((uint32_t)bslice * 3UL);
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/* Input source selection for selected bit slice */
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base->PMSRC = (base->PMSRC & ~(tmp_src_shift << src_shift)) | ((uint32_t)(cfg->bs_src) << src_shift);
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/* Bit slice configuration */
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pmcfg = base->PMCFG;
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pmcfg = (pmcfg & ~(tmp_cfg_shift << cfg_shift)) | ((uint32_t)(cfg->bs_cfg) << cfg_shift);
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/* If end point is true, enable the bits */
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if ((uint32_t)bslice != 7UL)
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{
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if (cfg->end_point)
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{
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pmcfg |= (1UL << (uint32_t)bslice);
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}
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else
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{
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pmcfg &= ~(1UL << (uint32_t)bslice);
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}
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}
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base->PMCFG = pmcfg;
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/* Save callback pointer */
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if (base == PINT)
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{
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if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS)
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{
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s_pintCallback[bslice] = cfg->callback;
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}
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}
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else
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{
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#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
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if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
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{
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s_secpintCallback[bslice] = cfg->callback;
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}
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#endif
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}
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}
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/*!
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* brief Get PINT pattern match configuration.
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* This function returns the configuration of a given pattern match bit slice.
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*
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* param base Base address of the PINT peripheral.
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* param bslice Pattern match bit slice number.
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* param cfg Pointer to bit slice configuration.
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*
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* retval None.
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*/
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void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg)
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{
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uint32_t src_shift;
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uint32_t cfg_shift;
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uint32_t tmp_src_shift = PININT_BITSLICE_SRC_MASK;
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uint32_t tmp_cfg_shift = PININT_BITSLICE_CFG_MASK;
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assert(base != NULL);
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src_shift = PININT_BITSLICE_SRC_START + ((uint32_t)bslice * 3UL);
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cfg_shift = PININT_BITSLICE_CFG_START + ((uint32_t)bslice * 3UL);
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cfg->bs_src = (pint_pmatch_input_src_t)(uint32_t)((base->PMSRC & (tmp_src_shift << src_shift)) >> src_shift);
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cfg->bs_cfg = (pint_pmatch_bslice_cfg_t)(uint32_t)((base->PMCFG & (tmp_cfg_shift << cfg_shift)) >> cfg_shift);
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if ((uint32_t)bslice == 7U)
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{
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cfg->end_point = true;
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}
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else
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{
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cfg->end_point = (((base->PMCFG & (1UL << (uint32_t)bslice)) >> (uint32_t)bslice) != 0U) ? true : false;
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}
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if (base == PINT)
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{
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if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS)
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{
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cfg->callback = s_pintCallback[bslice];
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}
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}
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else
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{
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#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
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if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
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{
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cfg->callback = s_secpintCallback[bslice];
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}
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#endif
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}
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}
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/*!
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* brief Reset pattern match detection logic.
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* This function resets the pattern match detection logic if any of the product term is matching.
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*
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* param base Base address of the PINT peripheral.
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*
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* retval pmstatus Each bit position indicates the match status of corresponding bit slice.
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* = 0 Match was detected. = 1 Match was not detected.
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*/
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uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base)
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{
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uint32_t pmctrl;
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uint32_t pmstatus;
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uint32_t pmsrc;
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pmctrl = base->PMCTRL;
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pmstatus = pmctrl >> PINT_PMCTRL_PMAT_SHIFT;
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if (pmstatus != 0UL)
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{
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/* Reset Pattern match engine detection logic */
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pmsrc = base->PMSRC;
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base->PMSRC = pmsrc;
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}
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return (pmstatus);
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}
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/*!
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* @brief Clear Selected pin interrupt status only when the pin was triggered by edge-sensitive.
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* This function clears the selected pin interrupt status.
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*
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* @param base Base address of the PINT peripheral.
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* @param pintr Pin interrupt.
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*
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* @retval None.
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*/
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void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr)
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{
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uint32_t pinIntMode = base->ISEL & (1UL << (uint32_t)pintr);
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uint32_t pinIntStatus = base->IST & (1UL << (uint32_t)pintr);
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/* Edge sensitive and pin interrupt that is currently requesting an interrupt. */
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if ((pinIntMode == 0x0UL) && (pinIntStatus != 0x0UL))
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{
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base->IST = (1UL << (uint32_t)pintr);
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}
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}
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/*!
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* @brief Clear all pin interrupts status only when pins were triggered by edge-sensitive.
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* This function clears the status of all pin interrupts.
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*
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* @param base Base address of the PINT peripheral.
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*
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* @retval None.
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*/
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void PINT_PinInterruptClrStatusAll(PINT_Type *base)
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{
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uint32_t pinIntMode = 0;
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uint32_t pinIntStatus = 0;
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uint32_t pinIntCount = 0;
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uint32_t mask = 0;
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uint32_t i;
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if (base == PINT)
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{
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|
pinIntCount = (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS;
|
|
}
|
|
else
|
|
{
|
|
#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
|
|
pinIntCount = (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS;
|
|
#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */
|
|
}
|
|
|
|
for (i = 0; i < pinIntCount; i++)
|
|
{
|
|
pinIntMode = base->ISEL & (1UL << i);
|
|
pinIntStatus = base->IST & (1UL << i);
|
|
|
|
/* Edge sensitive and pin interrupt that is currently requesting an interrupt. */
|
|
if ((pinIntMode == 0x0UL) && (pinIntStatus != 0x0UL))
|
|
{
|
|
mask |= 1UL << i;
|
|
}
|
|
}
|
|
|
|
base->IST = mask;
|
|
}
|
|
|
|
/*!
|
|
* brief Enable callback.
|
|
|
|
* This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored
|
|
* as soon as they are enabled, the callback function is not enabled until this function is called.
|
|
*
|
|
* param base Base address of the PINT peripheral.
|
|
*
|
|
* retval None.
|
|
*/
|
|
void PINT_EnableCallback(PINT_Type *base)
|
|
{
|
|
uint32_t i;
|
|
|
|
assert(base != NULL);
|
|
|
|
if (base == PINT)
|
|
{
|
|
#if defined(FSL_FEATURE_PINT_INTERRUPT_COMBINE) && (FSL_FEATURE_PINT_INTERRUPT_COMBINE == 1)
|
|
for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
|
|
{
|
|
PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i);
|
|
}
|
|
NVIC_ClearPendingIRQ(s_pintIRQ[0]);
|
|
(void)EnableIRQ(s_pintIRQ[0]);
|
|
#else
|
|
for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
|
|
{
|
|
PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i);
|
|
NVIC_ClearPendingIRQ(s_pintIRQ[i]);
|
|
(void)EnableIRQ(s_pintIRQ[i]);
|
|
}
|
|
#endif
|
|
}
|
|
else
|
|
{
|
|
#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
|
|
for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
|
|
{
|
|
PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i);
|
|
NVIC_ClearPendingIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]);
|
|
(void)EnableIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]);
|
|
}
|
|
#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */
|
|
}
|
|
}
|
|
|
|
/*!
|
|
* brief enable callback by pin index.
|
|
|
|
* This function enables callback by pin index instead of enabling all pins.
|
|
*
|
|
* param base Base address of the peripheral.
|
|
* param pinIdx pin index.
|
|
*
|
|
* retval None.
|
|
*/
|
|
void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx)
|
|
{
|
|
assert(base != NULL);
|
|
|
|
PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx);
|
|
|
|
#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
|
|
/* Get the right security pint irq index in array */
|
|
if ((base == SECPINT) && ((uint32_t)pintIdx < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS))
|
|
{
|
|
pintIdx =
|
|
(pint_pin_int_t)(uint32_t)((uint32_t)pintIdx + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS);
|
|
}
|
|
#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */
|
|
|
|
#if defined(FSL_FEATURE_PINT_INTERRUPT_COMBINE) && (FSL_FEATURE_PINT_INTERRUPT_COMBINE == 1)
|
|
NVIC_ClearPendingIRQ(s_pintIRQ[0]);
|
|
(void)EnableIRQ(s_pintIRQ[0]);
|
|
#else
|
|
NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]);
|
|
(void)EnableIRQ(s_pintIRQ[pintIdx]);
|
|
#endif
|
|
}
|
|
|
|
/*!
|
|
* brief Disable callback.
|
|
|
|
* This function disables the interrupt for the selected PINT peripheral. Although the pins are still
|
|
* being monitored but the callback function is not called.
|
|
*
|
|
* param base Base address of the peripheral.
|
|
*
|
|
* retval None.
|
|
*/
|
|
void PINT_DisableCallback(PINT_Type *base)
|
|
{
|
|
uint32_t i;
|
|
|
|
assert(base != NULL);
|
|
|
|
if (base == PINT)
|
|
{
|
|
#if defined(FSL_FEATURE_PINT_INTERRUPT_COMBINE) && (FSL_FEATURE_PINT_INTERRUPT_COMBINE == 1)
|
|
(void)DisableIRQ(s_pintIRQ[0]);
|
|
for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
|
|
{
|
|
PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i);
|
|
}
|
|
NVIC_ClearPendingIRQ(s_pintIRQ[0]);
|
|
#else
|
|
for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
|
|
{
|
|
(void)DisableIRQ(s_pintIRQ[i]);
|
|
PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i);
|
|
NVIC_ClearPendingIRQ(s_pintIRQ[i]);
|
|
}
|
|
#endif
|
|
}
|
|
else
|
|
{
|
|
#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
|
|
for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
|
|
{
|
|
(void)DisableIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]);
|
|
PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i);
|
|
NVIC_ClearPendingIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]);
|
|
}
|
|
#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */
|
|
}
|
|
}
|
|
|
|
/*!
|
|
* brief disable callback by pin index.
|
|
|
|
* This function disables callback by pin index instead of disabling all pins.
|
|
*
|
|
* param base Base address of the peripheral.
|
|
* param pinIdx pin index.
|
|
*
|
|
* retval None.
|
|
*/
|
|
void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx)
|
|
{
|
|
assert(base != NULL);
|
|
|
|
if (base == PINT)
|
|
{
|
|
#if defined(FSL_FEATURE_PINT_INTERRUPT_COMBINE) && (FSL_FEATURE_PINT_INTERRUPT_COMBINE == 1)
|
|
(void)DisableIRQ(s_pintIRQ[0]);
|
|
PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx);
|
|
NVIC_ClearPendingIRQ(s_pintIRQ[0]);
|
|
#else
|
|
(void)DisableIRQ(s_pintIRQ[pintIdx]);
|
|
PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx);
|
|
NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]);
|
|
#endif
|
|
}
|
|
else
|
|
{
|
|
#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
|
|
(void)DisableIRQ(s_pintIRQ[(uint32_t)pintIdx + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]);
|
|
PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx);
|
|
NVIC_ClearPendingIRQ(s_pintIRQ[(uint32_t)pintIdx + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]);
|
|
#endif
|
|
}
|
|
}
|
|
|
|
/*!
|
|
* brief Deinitialize PINT peripheral.
|
|
|
|
* This function disables the PINT clock.
|
|
*
|
|
* param base Base address of the PINT peripheral.
|
|
*
|
|
* retval None.
|
|
*/
|
|
void PINT_Deinit(PINT_Type *base)
|
|
{
|
|
uint32_t i;
|
|
|
|
assert(base != NULL);
|
|
|
|
/* Cleanup */
|
|
PINT_DisableCallback(base);
|
|
if (base == PINT)
|
|
{
|
|
/* clear PINT callback array*/
|
|
for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
|
|
{
|
|
s_pintCallback[i] = NULL;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
|
|
/* clear SECPINT callback array */
|
|
for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
|
|
{
|
|
s_secpintCallback[i] = NULL;
|
|
}
|
|
#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */
|
|
}
|
|
|
|
#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1)
|
|
|
|
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
/* Enable the clock. */
|
|
CLOCK_DisableClock(kCLOCK_GpioInt);
|
|
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
|
|
/* Reset the module. */
|
|
RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn);
|
|
#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
|
|
|
|
#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0)
|
|
|
|
if (base == PINT)
|
|
{
|
|
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
/* Enable the clock. */
|
|
CLOCK_DisableClock(kCLOCK_Gpio0);
|
|
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
|
|
/* Reset the module. */
|
|
RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn);
|
|
#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
|
|
}
|
|
else
|
|
{
|
|
#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
|
|
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
/* Enable the clock. */
|
|
CLOCK_DisableClock(kCLOCK_Gpio_Sec);
|
|
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
|
|
/* Reset the module. */
|
|
RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn);
|
|
#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
|
|
#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */
|
|
}
|
|
|
|
#else
|
|
|
|
if (base == PINT)
|
|
{
|
|
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
/* Enable the clock. */
|
|
CLOCK_DisableClock(kCLOCK_Pint);
|
|
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
|
|
/* Reset the module. */
|
|
RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn);
|
|
#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
|
|
}
|
|
else
|
|
{
|
|
/* if need config SECURE PINT device,then enable secure pint interrupt clock */
|
|
#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
|
|
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
/* Enable the clock. */
|
|
CLOCK_DisableClock(kCLOCK_Gpio_Sec_Int);
|
|
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
|
|
/* Reset the module. */
|
|
RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn);
|
|
#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
|
|
#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */
|
|
}
|
|
#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */
|
|
}
|
|
#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
|
|
/* IRQ handler functions overloading weak symbols in the startup */
|
|
void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void);
|
|
void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void)
|
|
{
|
|
uint32_t pmstatus = 0;
|
|
|
|
/* Reset pattern match detection */
|
|
pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT);
|
|
/* Call user function */
|
|
if (s_secpintCallback[kPINT_SecPinInt0] != NULL)
|
|
{
|
|
s_secpintCallback[kPINT_SecPinInt0](kPINT_SecPinInt0, pmstatus);
|
|
}
|
|
if ((SECPINT->ISEL & 0x1U) == 0x0U)
|
|
{
|
|
/* Edge sensitive: clear Pin interrupt after callback */
|
|
PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt0);
|
|
}
|
|
SDK_ISR_EXIT_BARRIER;
|
|
}
|
|
|
|
#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U)
|
|
/* IRQ handler functions overloading weak symbols in the startup */
|
|
void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void);
|
|
void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void)
|
|
{
|
|
uint32_t pmstatus;
|
|
|
|
/* Reset pattern match detection */
|
|
pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT);
|
|
/* Call user function */
|
|
if (s_secpintCallback[kPINT_SecPinInt1] != NULL)
|
|
{
|
|
s_secpintCallback[kPINT_SecPinInt1](kPINT_SecPinInt1, pmstatus);
|
|
}
|
|
if ((SECPINT->ISEL & 0x1U) == 0x0U)
|
|
{
|
|
/* Edge sensitive: clear Pin interrupt after callback */
|
|
PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt1);
|
|
}
|
|
SDK_ISR_EXIT_BARRIER;
|
|
}
|
|
#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */
|
|
#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */
|
|
|
|
void PINT0_DriverIRQHandler(void);
|
|
void PINT0_DriverIRQHandler(void)
|
|
{
|
|
uint32_t flags = (PINT->IST & PINT_IST_PSTAT_MASK) | PINT_PatternMatchGetStatusAll(PINT);
|
|
uint32_t pmstatus;
|
|
|
|
for (uint8_t i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
|
|
{
|
|
if ((flags & (1UL << i)) != 0UL)
|
|
{
|
|
/* Reset pattern match detection */
|
|
pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
|
|
/* Call user function */
|
|
if (s_pintCallback[i] != NULL)
|
|
{
|
|
s_pintCallback[i]((pint_pin_int_t)i, pmstatus);
|
|
}
|
|
if ((PINT->ISEL & (1UL << i)) == 0x0UL)
|
|
{
|
|
/* Edge sensitive: clear Pin interrupt after callback */
|
|
PINT_PinInterruptClrStatus(PINT, (pint_pin_int_t)i);
|
|
}
|
|
}
|
|
}
|
|
|
|
SDK_ISR_EXIT_BARRIER;
|
|
}
|
|
|
|
/* IRQ handler functions overloading weak symbols in the startup */
|
|
void PIN_INT0_DriverIRQHandler(void);
|
|
void PIN_INT0_DriverIRQHandler(void)
|
|
{
|
|
uint32_t pmstatus;
|
|
|
|
/* Reset pattern match detection */
|
|
pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
|
|
/* Call user function */
|
|
if (s_pintCallback[kPINT_PinInt0] != NULL)
|
|
{
|
|
s_pintCallback[kPINT_PinInt0](kPINT_PinInt0, pmstatus);
|
|
}
|
|
if ((PINT->ISEL & 0x1U) == 0x0U)
|
|
{
|
|
/* Edge sensitive: clear Pin interrupt after callback */
|
|
PINT_PinInterruptClrStatus(PINT, kPINT_PinInt0);
|
|
}
|
|
SDK_ISR_EXIT_BARRIER;
|
|
}
|
|
|
|
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U)
|
|
void PIN_INT1_DriverIRQHandler(void);
|
|
void PIN_INT1_DriverIRQHandler(void)
|
|
{
|
|
uint32_t pmstatus;
|
|
|
|
/* Reset pattern match detection */
|
|
pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
|
|
/* Call user function */
|
|
if (s_pintCallback[kPINT_PinInt1] != NULL)
|
|
{
|
|
s_pintCallback[kPINT_PinInt1](kPINT_PinInt1, pmstatus);
|
|
}
|
|
if ((PINT->ISEL & 0x2U) == 0x0U)
|
|
{
|
|
/* Edge sensitive: clear Pin interrupt after callback */
|
|
PINT_PinInterruptClrStatus(PINT, kPINT_PinInt1);
|
|
}
|
|
SDK_ISR_EXIT_BARRIER;
|
|
}
|
|
#endif
|
|
|
|
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U)
|
|
void PIN_INT2_DriverIRQHandler(void);
|
|
void PIN_INT2_DriverIRQHandler(void)
|
|
{
|
|
uint32_t pmstatus;
|
|
|
|
/* Reset pattern match detection */
|
|
pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
|
|
/* Call user function */
|
|
if (s_pintCallback[kPINT_PinInt2] != NULL)
|
|
{
|
|
s_pintCallback[kPINT_PinInt2](kPINT_PinInt2, pmstatus);
|
|
}
|
|
if ((PINT->ISEL & 0x4U) == 0x0U)
|
|
{
|
|
/* Edge sensitive: clear Pin interrupt after callback */
|
|
PINT_PinInterruptClrStatus(PINT, kPINT_PinInt2);
|
|
}
|
|
SDK_ISR_EXIT_BARRIER;
|
|
}
|
|
#endif
|
|
|
|
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U)
|
|
void PIN_INT3_DriverIRQHandler(void);
|
|
void PIN_INT3_DriverIRQHandler(void)
|
|
{
|
|
uint32_t pmstatus;
|
|
|
|
/* Reset pattern match detection */
|
|
pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
|
|
/* Call user function */
|
|
if (s_pintCallback[kPINT_PinInt3] != NULL)
|
|
{
|
|
s_pintCallback[kPINT_PinInt3](kPINT_PinInt3, pmstatus);
|
|
}
|
|
if ((PINT->ISEL & 0x8U) == 0x0U)
|
|
{
|
|
/* Edge sensitive: clear Pin interrupt after callback */
|
|
PINT_PinInterruptClrStatus(PINT, kPINT_PinInt3);
|
|
}
|
|
SDK_ISR_EXIT_BARRIER;
|
|
}
|
|
#endif
|
|
|
|
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U)
|
|
void PIN_INT4_DriverIRQHandler(void);
|
|
void PIN_INT4_DriverIRQHandler(void)
|
|
{
|
|
uint32_t pmstatus;
|
|
|
|
/* Reset pattern match detection */
|
|
pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
|
|
/* Call user function */
|
|
if (s_pintCallback[kPINT_PinInt4] != NULL)
|
|
{
|
|
s_pintCallback[kPINT_PinInt4](kPINT_PinInt4, pmstatus);
|
|
}
|
|
if ((PINT->ISEL & 0x10U) == 0x0U)
|
|
{
|
|
/* Edge sensitive: clear Pin interrupt after callback */
|
|
PINT_PinInterruptClrStatus(PINT, kPINT_PinInt4);
|
|
}
|
|
SDK_ISR_EXIT_BARRIER;
|
|
}
|
|
#endif
|
|
|
|
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U)
|
|
#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER
|
|
void PIN_INT5_DAC1_IRQHandler(void);
|
|
void PIN_INT5_DAC1_IRQHandler(void)
|
|
#else
|
|
void PIN_INT5_DriverIRQHandler(void);
|
|
void PIN_INT5_DriverIRQHandler(void)
|
|
#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */
|
|
{
|
|
uint32_t pmstatus;
|
|
|
|
/* Reset pattern match detection */
|
|
pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
|
|
/* Call user function */
|
|
if (s_pintCallback[kPINT_PinInt5] != NULL)
|
|
{
|
|
s_pintCallback[kPINT_PinInt5](kPINT_PinInt5, pmstatus);
|
|
}
|
|
if ((PINT->ISEL & 0x20U) == 0x0U)
|
|
{
|
|
/* Edge sensitive: clear Pin interrupt after callback */
|
|
PINT_PinInterruptClrStatus(PINT, kPINT_PinInt5);
|
|
}
|
|
SDK_ISR_EXIT_BARRIER;
|
|
}
|
|
#endif
|
|
|
|
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U)
|
|
#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER
|
|
void PIN_INT6_USART3_IRQHandler(void);
|
|
void PIN_INT6_USART3_IRQHandler(void)
|
|
#else
|
|
void PIN_INT6_DriverIRQHandler(void);
|
|
void PIN_INT6_DriverIRQHandler(void)
|
|
#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */
|
|
{
|
|
uint32_t pmstatus;
|
|
|
|
/* Reset pattern match detection */
|
|
pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
|
|
/* Call user function */
|
|
if (s_pintCallback[kPINT_PinInt6] != NULL)
|
|
{
|
|
s_pintCallback[kPINT_PinInt6](kPINT_PinInt6, pmstatus);
|
|
}
|
|
if ((PINT->ISEL & 0x40U) == 0x0U)
|
|
{
|
|
/* Edge sensitive: clear Pin interrupt after callback */
|
|
PINT_PinInterruptClrStatus(PINT, kPINT_PinInt6);
|
|
}
|
|
SDK_ISR_EXIT_BARRIER;
|
|
}
|
|
#endif
|
|
|
|
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U)
|
|
#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER
|
|
void PIN_INT7_USART4_IRQHandler(void);
|
|
void PIN_INT7_USART4_IRQHandler(void)
|
|
#else
|
|
void PIN_INT7_DriverIRQHandler(void);
|
|
void PIN_INT7_DriverIRQHandler(void)
|
|
#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */
|
|
{
|
|
uint32_t pmstatus;
|
|
|
|
/* Reset pattern match detection */
|
|
pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
|
|
/* Call user function */
|
|
if (s_pintCallback[kPINT_PinInt7] != NULL)
|
|
{
|
|
s_pintCallback[kPINT_PinInt7](kPINT_PinInt7, pmstatus);
|
|
}
|
|
if ((PINT->ISEL & 0x80U) == 0x0U)
|
|
{
|
|
/* Edge sensitive: clear Pin interrupt after callback */
|
|
PINT_PinInterruptClrStatus(PINT, kPINT_PinInt7);
|
|
}
|
|
SDK_ISR_EXIT_BARRIER;
|
|
}
|
|
#endif
|