375 lines
17 KiB
C
375 lines
17 KiB
C
/*
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* Copyright 2018-2019 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef FSL_PLU_H_
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#define FSL_PLU_H_
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#include "fsl_common.h"
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/*!
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* @addtogroup plu
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* @{
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @name Driver version */
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/*! @{ */
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#define FSL_PLU_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) /*!< Version 2.2.1 */
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/*! @} */
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/*! @brief Index of LUT */
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typedef enum _plu_lut_index
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{
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kPLU_LUT_0 = 0U, /*!< 5-input Look-up Table 0 */
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kPLU_LUT_1 = 1U, /*!< 5-input Look-up Table 1 */
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kPLU_LUT_2 = 2U, /*!< 5-input Look-up Table 2 */
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kPLU_LUT_3 = 3U, /*!< 5-input Look-up Table 3 */
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kPLU_LUT_4 = 4U, /*!< 5-input Look-up Table 4 */
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kPLU_LUT_5 = 5U, /*!< 5-input Look-up Table 5 */
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kPLU_LUT_6 = 6U, /*!< 5-input Look-up Table 6 */
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kPLU_LUT_7 = 7U, /*!< 5-input Look-up Table 7 */
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kPLU_LUT_8 = 8U, /*!< 5-input Look-up Table 8 */
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kPLU_LUT_9 = 9U, /*!< 5-input Look-up Table 9 */
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kPLU_LUT_10 = 10U, /*!< 5-input Look-up Table 10 */
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kPLU_LUT_11 = 11U, /*!< 5-input Look-up Table 11 */
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kPLU_LUT_12 = 12U, /*!< 5-input Look-up Table 12 */
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kPLU_LUT_13 = 13U, /*!< 5-input Look-up Table 13 */
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kPLU_LUT_14 = 14U, /*!< 5-input Look-up Table 14 */
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kPLU_LUT_15 = 15U, /*!< 5-input Look-up Table 15 */
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kPLU_LUT_16 = 16U, /*!< 5-input Look-up Table 16 */
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kPLU_LUT_17 = 17U, /*!< 5-input Look-up Table 17 */
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kPLU_LUT_18 = 18U, /*!< 5-input Look-up Table 18 */
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kPLU_LUT_19 = 19U, /*!< 5-input Look-up Table 19 */
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kPLU_LUT_20 = 20U, /*!< 5-input Look-up Table 20 */
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kPLU_LUT_21 = 21U, /*!< 5-input Look-up Table 21 */
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kPLU_LUT_22 = 22U, /*!< 5-input Look-up Table 22 */
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kPLU_LUT_23 = 23U, /*!< 5-input Look-up Table 23 */
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kPLU_LUT_24 = 24U, /*!< 5-input Look-up Table 24 */
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kPLU_LUT_25 = 25U /*!< 5-input Look-up Table 25 */
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} plu_lut_index_t;
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/*! @brief Inputs of LUT. 5 input present for each LUT. */
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typedef enum _plu_lut_in_index
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{
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kPLU_LUT_IN_0 = 0U, /*!< LUT input 0 */
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kPLU_LUT_IN_1 = 1U, /*!< LUT input 1 */
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kPLU_LUT_IN_2 = 2U, /*!< LUT input 2 */
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kPLU_LUT_IN_3 = 3U, /*!< LUT input 3 */
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kPLU_LUT_IN_4 = 4U /*!< LUT input 4 */
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} plu_lut_in_index_t;
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/*! @brief Available sources of LUT input */
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typedef enum _plu_lut_input_source
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{
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kPLU_LUT_IN_SRC_PLU_IN_0 = 0U, /*!< Select PLU input 0 to be connected to LUTn Input x */
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kPLU_LUT_IN_SRC_PLU_IN_1 = 1U, /*!< Select PLU input 1 to be connected to LUTn Input x */
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kPLU_LUT_IN_SRC_PLU_IN_2 = 2U, /*!< Select PLU input 2 to be connected to LUTn Input x */
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kPLU_LUT_IN_SRC_PLU_IN_3 = 3U, /*!< Select PLU input 3 to be connected to LUTn Input x */
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kPLU_LUT_IN_SRC_PLU_IN_4 = 4U, /*!< Select PLU input 4 to be connected to LUTn Input x */
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kPLU_LUT_IN_SRC_PLU_IN_5 = 5U, /*!< Select PLU input 5 to be connected to LUTn Input x */
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kPLU_LUT_IN_SRC_LUT_OUT_0 = 6U, /*!< Select LUT output 0 to be connected to LUTn Input x */
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kPLU_LUT_IN_SRC_LUT_OUT_1 = 7U, /*!< Select LUT output 1 to be connected to LUTn Input x */
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kPLU_LUT_IN_SRC_LUT_OUT_2 = 8U, /*!< Select LUT output 2 to be connected to LUTn Input x */
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kPLU_LUT_IN_SRC_LUT_OUT_3 = 9U, /*!< Select LUT output 3 to be connected to LUTn Input x */
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kPLU_LUT_IN_SRC_LUT_OUT_4 = 10U, /*!< Select LUT output 4 to be connected to LUTn Input x */
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kPLU_LUT_IN_SRC_LUT_OUT_5 = 11U, /*!< Select LUT output 5 to be connected to LUTn Input x */
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kPLU_LUT_IN_SRC_LUT_OUT_6 = 12U, /*!< Select LUT output 6 to be connected to LUTn Input x */
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kPLU_LUT_IN_SRC_LUT_OUT_7 = 13U, /*!< Select LUT output 7 to be connected to LUTn Input x */
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kPLU_LUT_IN_SRC_LUT_OUT_8 = 14U, /*!< Select LUT output 8 to be connected to LUTn Input x */
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kPLU_LUT_IN_SRC_LUT_OUT_9 = 15U, /*!< Select LUT output 9 to be connected to LUTn Input x */
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kPLU_LUT_IN_SRC_LUT_OUT_10 = 16U, /*!< Select LUT output 10 to be connected to LUTn Input x */
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kPLU_LUT_IN_SRC_LUT_OUT_11 = 17U, /*!< Select LUT output 11 to be connected to LUTn Input x */
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kPLU_LUT_IN_SRC_LUT_OUT_12 = 18U, /*!< Select LUT output 12 to be connected to LUTn Input x */
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kPLU_LUT_IN_SRC_LUT_OUT_13 = 19U, /*!< Select LUT output 13 to be connected to LUTn Input x */
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kPLU_LUT_IN_SRC_LUT_OUT_14 = 20U, /*!< Select LUT output 14 to be connected to LUTn Input x */
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kPLU_LUT_IN_SRC_LUT_OUT_15 = 21U, /*!< Select LUT output 15 to be connected to LUTn Input x */
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kPLU_LUT_IN_SRC_LUT_OUT_16 = 22U, /*!< Select LUT output 16 to be connected to LUTn Input x */
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kPLU_LUT_IN_SRC_LUT_OUT_17 = 23U, /*!< Select LUT output 17 to be connected to LUTn Input x */
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kPLU_LUT_IN_SRC_LUT_OUT_18 = 24U, /*!< Select LUT output 18 to be connected to LUTn Input x */
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kPLU_LUT_IN_SRC_LUT_OUT_19 = 25U, /*!< Select LUT output 19 to be connected to LUTn Input x */
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kPLU_LUT_IN_SRC_LUT_OUT_20 = 26U, /*!< Select LUT output 20 to be connected to LUTn Input x */
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kPLU_LUT_IN_SRC_LUT_OUT_21 = 27U, /*!< Select LUT output 21 to be connected to LUTn Input x */
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kPLU_LUT_IN_SRC_LUT_OUT_22 = 28U, /*!< Select LUT output 22 to be connected to LUTn Input x */
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kPLU_LUT_IN_SRC_LUT_OUT_23 = 29U, /*!< Select LUT output 23 to be connected to LUTn Input x */
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kPLU_LUT_IN_SRC_LUT_OUT_24 = 30U, /*!< Select LUT output 24 to be connected to LUTn Input x */
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kPLU_LUT_IN_SRC_LUT_OUT_25 = 31U, /*!< Select LUT output 25 to be connected to LUTn Input x */
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kPLU_LUT_IN_SRC_FLIPFLOP_0 = 32U, /*!< Select Flip-Flops state 0 to be connected to LUTn Input x */
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kPLU_LUT_IN_SRC_FLIPFLOP_1 = 33U, /*!< Select Flip-Flops state 1 to be connected to LUTn Input x */
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kPLU_LUT_IN_SRC_FLIPFLOP_2 = 34U, /*!< Select Flip-Flops state 2 to be connected to LUTn Input x */
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kPLU_LUT_IN_SRC_FLIPFLOP_3 = 35U /*!< Select Flip-Flops state 3 to be connected to LUTn Input x */
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} plu_lut_input_source_t;
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/*! @brief PLU output multiplexer registers */
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typedef enum _plu_output_index
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{
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kPLU_OUTPUT_0 = 0U, /*!< PLU OUTPUT 0 */
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kPLU_OUTPUT_1 = 1U, /*!< PLU OUTPUT 1 */
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kPLU_OUTPUT_2 = 2U, /*!< PLU OUTPUT 2 */
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kPLU_OUTPUT_3 = 3U, /*!< PLU OUTPUT 3 */
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kPLU_OUTPUT_4 = 4U, /*!< PLU OUTPUT 4 */
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kPLU_OUTPUT_5 = 5U, /*!< PLU OUTPUT 5 */
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kPLU_OUTPUT_6 = 6U, /*!< PLU OUTPUT 6 */
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kPLU_OUTPUT_7 = 7U /*!< PLU OUTPUT 7 */
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} plu_output_index_t;
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/*! @brief Available sources of PLU output */
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typedef enum _plu_output_source
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{
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kPLU_OUT_SRC_LUT_0 = 0U, /*!< Select LUT0 output to be connected to PLU output */
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kPLU_OUT_SRC_LUT_1 = 1U, /*!< Select LUT1 output to be connected to PLU output */
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kPLU_OUT_SRC_LUT_2 = 2U, /*!< Select LUT2 output to be connected to PLU output */
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kPLU_OUT_SRC_LUT_3 = 3U, /*!< Select LUT3 output to be connected to PLU output */
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kPLU_OUT_SRC_LUT_4 = 4U, /*!< Select LUT4 output to be connected to PLU output */
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kPLU_OUT_SRC_LUT_5 = 5U, /*!< Select LUT5 output to be connected to PLU output */
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kPLU_OUT_SRC_LUT_6 = 6U, /*!< Select LUT6 output to be connected to PLU output */
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kPLU_OUT_SRC_LUT_7 = 7U, /*!< Select LUT7 output to be connected to PLU output */
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kPLU_OUT_SRC_LUT_8 = 8U, /*!< Select LUT8 output to be connected to PLU output */
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kPLU_OUT_SRC_LUT_9 = 9U, /*!< Select LUT9 output to be connected to PLU output */
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kPLU_OUT_SRC_LUT_10 = 10U, /*!< Select LUT10 output to be connected to PLU output */
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kPLU_OUT_SRC_LUT_11 = 11U, /*!< Select LUT11 output to be connected to PLU output */
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kPLU_OUT_SRC_LUT_12 = 12U, /*!< Select LUT12 output to be connected to PLU output */
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kPLU_OUT_SRC_LUT_13 = 13U, /*!< Select LUT13 output to be connected to PLU output */
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kPLU_OUT_SRC_LUT_14 = 14U, /*!< Select LUT14 output to be connected to PLU output */
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kPLU_OUT_SRC_LUT_15 = 15U, /*!< Select LUT15 output to be connected to PLU output */
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kPLU_OUT_SRC_LUT_16 = 16U, /*!< Select LUT16 output to be connected to PLU output */
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kPLU_OUT_SRC_LUT_17 = 17U, /*!< Select LUT17 output to be connected to PLU output */
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kPLU_OUT_SRC_LUT_18 = 18U, /*!< Select LUT18 output to be connected to PLU output */
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kPLU_OUT_SRC_LUT_19 = 19U, /*!< Select LUT19 output to be connected to PLU output */
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kPLU_OUT_SRC_LUT_20 = 20U, /*!< Select LUT20 output to be connected to PLU output */
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kPLU_OUT_SRC_LUT_21 = 21U, /*!< Select LUT21 output to be connected to PLU output */
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kPLU_OUT_SRC_LUT_22 = 22U, /*!< Select LUT22 output to be connected to PLU output */
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kPLU_OUT_SRC_LUT_23 = 23U, /*!< Select LUT23 output to be connected to PLU output */
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kPLU_OUT_SRC_LUT_24 = 24U, /*!< Select LUT24 output to be connected to PLU output */
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kPLU_OUT_SRC_LUT_25 = 25U, /*!< Select LUT25 output to be connected to PLU output */
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kPLU_OUT_SRC_FLIPFLOP_0 = 26U, /*!< Select Flip-Flops state(0) to be connected to PLU output */
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kPLU_OUT_SRC_FLIPFLOP_1 = 27U, /*!< Select Flip-Flops state(1) to be connected to PLU output */
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kPLU_OUT_SRC_FLIPFLOP_2 = 28U, /*!< Select Flip-Flops state(2) to be connected to PLU output */
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kPLU_OUT_SRC_FLIPFLOP_3 = 29U /*!< Select Flip-Flops state(3) to be connected to PLU output */
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} plu_output_source_t;
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#if defined(FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG) && FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG
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/*! @brief The enumerator of PLU Interrupt. */
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enum _plu_interrupt_mask
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{
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kPLU_OUTPUT_0_INTERRUPT_MASK = 1 << 0, /*!< Select PLU output 0 contribute to interrupt/wake-up generation */
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kPLU_OUTPUT_1_INTERRUPT_MASK = 1 << 1, /*!< Select PLU output 1 contribute to interrupt/wake-up generation */
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kPLU_OUTPUT_2_INTERRUPT_MASK = 1 << 2, /*!< Select PLU output 2 contribute to interrupt/wake-up generation */
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kPLU_OUTPUT_3_INTERRUPT_MASK = 1 << 3, /*!< Select PLU output 3 contribute to interrupt/wake-up generation */
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kPLU_OUTPUT_4_INTERRUPT_MASK = 1 << 4, /*!< Select PLU output 4 contribute to interrupt/wake-up generation */
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kPLU_OUTPUT_5_INTERRUPT_MASK = 1 << 5, /*!< Select PLU output 5 contribute to interrupt/wake-up generation */
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kPLU_OUTPUT_6_INTERRUPT_MASK = 1 << 6, /*!< Select PLU output 6 contribute to interrupt/wake-up generation */
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kPLU_OUTPUT_7_INTERRUPT_MASK = 1 << 7 /*!< Select PLU output 7 contribute to interrupt/wake-up generation */
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};
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/*! @brief Control input of the PLU, add filtering for glitch. */
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typedef enum _plu_wakeint_filter_mode
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{
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kPLU_WAKEINT_FILTER_MODE_BYPASS = 0U, /*!< Select Bypass mode */
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kPLU_WAKEINT_FILTER_MODE_1_CLK_PERIOD = 1U, /*!< Filter 1 clock period */
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kPLU_WAKEINT_FILTER_MODE_2_CLK_PERIOD = 2U, /*!< Filter 2 clock period */
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kPLU_WAKEINT_FILTER_MODE_3_CLK_PERIOD = 3U /*!< Filter 3 clock period */
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} plu_wakeint_filter_mode_t;
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/*! @brief Clock source for filter mode. */
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typedef enum _plu_wakeint_filter_clock_source
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{
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kPLU_WAKEINT_FILTER_CLK_SRC_1MHZ_LPOSC = 0U, /*!< Select the 1MHz low-power oscillator as the filter clock */
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kPLU_WAKEINT_FILTER_CLK_SRC_12MHZ_FRO = 1U, /*!< Select the 12MHz FRO as the filer clock */
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kPLU_WAKEINT_FILTER_CLK_SRC_ALT = 2U /*!< Select a third clock source */
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} plu_wakeint_filter_clock_source_t;
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/*! @brief Wake configuration. */
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typedef struct _plu_wakeint_config
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{
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plu_wakeint_filter_mode_t filterMode; /*!< Filter Mode. */
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plu_wakeint_filter_clock_source_t clockSource; /*!< The clock source for filter mode. */
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} plu_wakeint_config_t;
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#endif /* FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG */
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/*******************************************************************************
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* API
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/*!
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* @name Initialization and deinitialization
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* @{
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*/
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/*!
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* @brief Enable the PLU clock and reset the module.
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*
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* @note This API should be called at the beginning of the application using the PLU driver.
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*
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* @param base PLU peripheral base address
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*/
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void PLU_Init(PLU_Type *base);
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/*!
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* @brief Gate the PLU clock
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*
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* @param base PLU peripheral base address
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*/
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void PLU_Deinit(PLU_Type *base);
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/*! @}*/
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/*!
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* @name Set input/output source and Truth Table
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* @{
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*/
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/*!
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* @brief Set Input source of LUT.
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*
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* Note: An external clock must be applied to the PLU_CLKIN input when using FFs.
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* For each LUT, the slot associated with the output from LUTn itself is tied low.
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*
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* @param base PLU peripheral base address.
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* @param lutIndex LUT index (see @ref plu_lut_index_t typedef enumeration).
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* @param lutInIndex LUT input index (see @ref plu_lut_in_index_t typedef enumeration).
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* @param inputSrc LUT input source (see @ref plu_lut_input_source_t typedef enumeration).
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*/
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static inline void PLU_SetLutInputSource(PLU_Type *base,
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plu_lut_index_t lutIndex,
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plu_lut_in_index_t lutInIndex,
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plu_lut_input_source_t inputSrc)
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{
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PLU->LUT[lutIndex].INP_MUX[lutInIndex] = (uint32_t)inputSrc;
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}
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/*!
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* @brief Set Output source of PLU.
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*
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* Note: An external clock must be applied to the PLU_CLKIN input when using FFs.
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*
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* @param base PLU peripheral base address.
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* @param outputIndex PLU output index (see @ref plu_output_index_t typedef enumeration).
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* @param outputSrc PLU output source (see @ref plu_output_source_t typedef enumeration).
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*/
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static inline void PLU_SetOutputSource(PLU_Type *base, plu_output_index_t outputIndex, plu_output_source_t outputSrc)
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{
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base->OUTPUT_MUX[outputIndex] = (uint32_t)outputSrc;
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}
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/*!
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* @brief Set Truth Table of LUT.
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*
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* @param base PLU peripheral base address.
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* @param lutIndex LUT index (see @ref plu_lut_index_t typedef enumeration).
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* @param truthTable Truth Table value.
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*/
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static inline void PLU_SetLutTruthTable(PLU_Type *base, plu_lut_index_t lutIndex, uint32_t truthTable)
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{
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base->LUT_TRUTH[lutIndex] = truthTable;
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}
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/*! @}*/
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/*!
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* @name Read current Output State
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* @{
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*/
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/*!
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* @brief Read the current state of the 8 designated PLU Outputs.
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*
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* Note: The PLU bus clock must be re-enabled prior to reading the Outpus Register if PLU bus clock is
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* shut-off.
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*
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* @param base PLU peripheral base address.
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* @return Current PLU output state value.
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*/
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static inline uint32_t PLU_ReadOutputState(PLU_Type *base)
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{
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return (base->OUTPUTS & PLU_OUTPUTS_OUTPUT_STATE_MASK);
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}
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/*! @}*/
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#if defined(FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG) && FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG
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/*!
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* @name Wake-up/Interrupt Control
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* @{
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*/
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/*!
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* @brief Gets an available pre-defined settings for wakeup/interrupt control.
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*
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* This function initializes the initial configuration structure with an available settings. The default values are:
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* @code
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* config->filterMode = kPLU_WAKEINT_FILTER_MODE_BYPASS;
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* config->clockSource = kPLU_WAKEINT_FILTER_CLK_SRC_1MHZ_LPOSC;
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* @endcode
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* @param config Pointer to configuration structure.
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*/
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void PLU_GetDefaultWakeIntConfig(plu_wakeint_config_t *config);
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/*!
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* @brief Enable PLU outputs wakeup/interrupt request.
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*
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* This function enables Any of the eight selected PLU outputs to contribute to an asynchronous wake-up or an interrupt
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* request.
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*
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* Note: If a PLU_CLKIN is provided, the raw wake-up/interrupt request will be set on the rising-edge of the PLU_CLKIN
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* whenever the raw request signal is high. This registered signal will be glitch-free and just use the default wakeint
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* config by PLU_GetDefaultWakeIntConfig(). If not, have to specify the filter mode and clock source to eliminate the
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* glitches caused by long and widely disparate delays through the network of LUTs making up the PLU. This way may
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* increase power consumption in low-power operating modes and inject delay before the wake-up/interrupt request is
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* generated.
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*
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* @param base PLU peripheral base address.
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* @param interruptMask PLU interrupt mask (see @ref _plu_interrupt_mask enumeration).
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* @param config Pointer to configuration structure (see @ref plu_wakeint_config_t typedef enumeration)
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*/
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void PLU_EnableWakeIntRequest(PLU_Type *base, uint32_t interruptMask, const plu_wakeint_config_t *config);
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/*!
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* @brief Latch an interrupt
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*
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* This function latches the interrupt and then it can be cleared with PLU_ClearLatchedInterrupt().
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*
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* Note: This mode is not compatible with use of the glitch filter. If this bit is set, the FILTER MODE should be set
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* to kPLU_WAKEINT_FILTER_MODE_BYPASS (Bypass Mode) and PLU_CLKIN should be provided. If this bit is set, the
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* wake-up/interrupt request will be set on the rising-edge of PLU_CLKIN whenever the raw wake-up/interrupt signal is
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* high. The request must be cleared by software.
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*
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* @param base PLU peripheral base address.
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*/
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static inline void PLU_LatchInterrupt(PLU_Type *base)
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{
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base->WAKEINT_CTRL |= PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK;
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}
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/*!
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* @brief Clear the latched interrupt
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*
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* This function clears the wake-up/interrupt request flag latched by PLU_LatchInterrupt()
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*
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* Note: It is not necessary for the PLU bus clock to be enabled in order to write-to or read-back this bit.
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*
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* @param base PLU peripheral base address.
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*/
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void PLU_ClearLatchedInterrupt(PLU_Type *base);
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/*! @}*/
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#endif /* FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG */
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#if defined(__cplusplus)
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}
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#endif
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/*! @}*/
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#endif /* FSL_PLU_H_ */
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