822 lines
31 KiB
C
822 lines
31 KiB
C
/*
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2023 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_sctimer.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.sctimer"
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#endif
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#if defined(SCT_RSTS_N) || defined(SCT_RSTS)
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#define FSL_FEATURE_SCT_HAS_RESET
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#endif
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/*! @brief Typedef for interrupt handler. */
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typedef void (*sctimer_isr_t)(SCT_Type *base);
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Gets the instance from the base address
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*
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* @param base SCTimer peripheral base address
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*
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* @return The SCTimer instance
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*/
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static uint32_t SCTIMER_GetInstance(SCT_Type *base);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*! @brief Pointers to SCT bases for each instance. */
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static SCT_Type *const s_sctBases[] = SCT_BASE_PTRS;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/*! @brief Pointers to SCT clocks for each instance. */
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static const clock_ip_name_t s_sctClocks[] = SCT_CLOCKS;
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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#if defined(FSL_FEATURE_SCT_HAS_RESET)
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#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
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#if defined(FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET
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/*! @brief Pointers to SCT resets for each instance, writing a zero asserts the reset */
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static const reset_ip_name_t s_sctResets[] = SCT_RSTS_N;
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#else
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/*! @brief Pointers to SCT resets for each instance, writing a one asserts the reset */
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static const reset_ip_name_t s_sctResets[] = SCT_RSTS;
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#endif
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#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
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#endif /* FSL_FEATURE_SCT_HAS_RESET */
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/*!< @brief SCTimer event Callback function. */
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static sctimer_event_callback_t s_eventCallback[FSL_FEATURE_SCT_NUMBER_OF_EVENTS];
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/*!< @brief Keep track of SCTimer event number */
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static uint32_t s_currentEvent;
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/*!< @brief Keep track of SCTimer state number */
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static uint32_t s_currentState;
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/*!< @brief Keep track of SCTimer unify 32-bit or low 16-bit match/capture register number. */
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static uint32_t s_currentMatch;
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/*!< @brief Keep track of SCTimer high 16-bit match/capture register number. */
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static uint32_t s_currentMatchhigh;
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/*! @brief Pointer to SCTimer IRQ handler */
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static sctimer_isr_t s_sctimerIsr;
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/*******************************************************************************
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* Code
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******************************************************************************/
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static uint32_t SCTIMER_GetInstance(SCT_Type *base)
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{
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uint32_t instance;
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uint32_t sctArrayCount = (sizeof(s_sctBases) / sizeof(s_sctBases[0]));
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < sctArrayCount; instance++)
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{
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if (s_sctBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < sctArrayCount);
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return instance;
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}
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/*!
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* brief Ungates the SCTimer clock and configures the peripheral for basic operation.
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*
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* note This API should be called at the beginning of the application using the SCTimer driver.
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*
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* param base SCTimer peripheral base address
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* param config Pointer to the user configuration structure.
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*
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* return kStatus_Success indicates success; Else indicates failure.
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*/
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status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config)
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{
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assert(NULL != config);
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uint32_t i;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Enable the SCTimer clock*/
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CLOCK_EnableClock(s_sctClocks[SCTIMER_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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#if defined(FSL_FEATURE_SCT_HAS_RESET)
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#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
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/* Reset the module. */
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RESET_PeripheralReset(s_sctResets[SCTIMER_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
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#endif /* FSL_FEATURE_SCT_HAS_RESET */
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/* Setup the counter operation. For Current Driver interface SCTIMER_Init don't know detail
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* frequency of input clock, but User know it. So the INSYNC have to set by user level. */
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base->CONFIG = SCT_CONFIG_CKSEL(config->clockSelect) | SCT_CONFIG_CLKMODE(config->clockMode) |
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SCT_CONFIG_UNIFY(config->enableCounterUnify) | SCT_CONFIG_INSYNC(config->inputsync);
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/* Write to the control register, keep the counters halted. */
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base->CTRL =
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SCT_CTRL_BIDIR_L(config->enableBidirection_l) | SCT_CTRL_PRE_L(config->prescale_l) | SCT_CTRL_HALT_L_MASK;
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/* Clear the counter after changing the PRE value. */
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base->CTRL |= SCT_CTRL_CLRCTR_L_MASK;
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if (!(config->enableCounterUnify))
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{
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base->CTRL |=
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SCT_CTRL_BIDIR_H(config->enableBidirection_h) | SCT_CTRL_PRE_H(config->prescale_h) | SCT_CTRL_HALT_H_MASK;
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base->CTRL |= SCT_CTRL_CLRCTR_H_MASK;
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}
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/* Initial state of channel output */
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base->OUTPUT = config->outInitState;
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/* Clear the global variables */
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s_currentEvent = 0U;
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s_currentState = 0U;
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s_currentMatch = 0U;
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s_currentMatchhigh = 0U;
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/* Clear the callback array */
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for (i = 0; i < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS; i++)
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{
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s_eventCallback[i] = NULL;
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}
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/* Save interrupt handler */
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s_sctimerIsr = SCTIMER_EventHandleIRQ;
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return kStatus_Success;
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}
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/*!
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* brief Gates the SCTimer clock.
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*
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* param base SCTimer peripheral base address
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*/
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void SCTIMER_Deinit(SCT_Type *base)
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{
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/* Halt the counters */
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base->CTRL |= (SCT_CTRL_HALT_L_MASK | SCT_CTRL_HALT_H_MASK);
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Disable the SCTimer clock*/
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CLOCK_DisableClock(s_sctClocks[SCTIMER_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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/*!
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* brief Fills in the SCTimer configuration structure with the default settings.
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*
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* The default values are:
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* code
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* config->enableCounterUnify = true;
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* config->clockMode = kSCTIMER_System_ClockMode;
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* config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0;
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* config->enableBidirection_l = false;
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* config->enableBidirection_h = false;
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* config->prescale_l = 0U;
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* config->prescale_h = 0U;
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* config->outInitState = 0U;
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* config->inputsync = 0xFU;
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* endcode
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* param config Pointer to the user configuration structure.
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*/
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void SCTIMER_GetDefaultConfig(sctimer_config_t *config)
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{
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assert(NULL != config);
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/* Initializes the configure structure to zero. */
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(void)memset(config, 0, sizeof(*config));
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/* SCT operates as a unified 32-bit counter */
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config->enableCounterUnify = true;
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/* System clock clocks the entire SCT module */
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config->clockMode = kSCTIMER_System_ClockMode;
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/* This is used only by certain clock modes */
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config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0;
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/* Up count mode only for the unified counter */
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config->enableBidirection_l = false;
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/* Up count mode only for Counte_H */
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config->enableBidirection_h = false;
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/* Prescale factor of 1 */
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config->prescale_l = 0U;
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/* Prescale factor of 1 for Counter_H*/
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config->prescale_h = 0U;
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/* Clear outputs */
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config->outInitState = 0U;
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/* Default value is 0xFU, it can be clear as 0 when speical conditions met.
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* Condition can be clear as 0: (for all Clock Modes):
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* (1) The corresponding input is already synchronous to the SCTimer/PWM clock.
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* (2) The SCTimer/PWM clock frequency does not exceed 100 MHz.
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* Note: The SCTimer/PWM clock is the bus/system clock for CKMODE 0-2 or asynchronous input
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* clock for CKMODE3.
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* Another condition can be clear as 0: (for CKMODE2 only)
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* (1) The corresponding input is synchronous to the designated CKMODE2 input clock.
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* (2) The CKMODE2 input clock frequency is less than one-third the frequency of the bus/system clock.
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* Default value set as 0U, input0~input3 are set as bypasses. */
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config->inputsync = 0xFU;
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}
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/*!
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* brief Configures the PWM signal parameters.
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*
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* Call this function to configure the PWM signal period, mode, duty cycle, and edge. This
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* function will create 2 events; one of the events will trigger on match with the pulse value
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* and the other will trigger when the counter matches the PWM period. The PWM period event is
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* also used as a limit event to reset the counter or change direction. Both events are enabled
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* for the same state. The state number can be retrieved by calling the function
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* SCTIMER_GetCurrentStateNumber().
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* The counter is set to operate as one 32-bit counter (unify bit is set to 1).
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* The counter operates in bi-directional mode when generating a center-aligned PWM.
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*
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* note When setting PWM output from multiple output pins, they all should use the same PWM mode
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* i.e all PWM's should be either edge-aligned or center-aligned.
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* When using this API, the PWM signal frequency of all the initialized channels must be the same.
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* Otherwise all the initialized channels' PWM signal frequency is equal to the last call to the
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* API's pwmFreq_Hz.
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*
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* param base SCTimer peripheral base address
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* param pwmParams PWM parameters to configure the output
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* param mode PWM operation mode, options available in enumeration ::sctimer_pwm_mode_t
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* param pwmFreq_Hz PWM signal frequency in Hz
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* param srcClock_Hz SCTimer counter clock in Hz
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* param event Pointer to a variable where the PWM period event number is stored
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*
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* return kStatus_Success on success
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* kStatus_Fail If we have hit the limit in terms of number of events created or if
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* an incorrect PWM dutycylce is passed in.
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*/
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status_t SCTIMER_SetupPwm(SCT_Type *base,
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const sctimer_pwm_signal_param_t *pwmParams,
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sctimer_pwm_mode_t mode,
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uint32_t pwmFreq_Hz,
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uint32_t srcClock_Hz,
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uint32_t *event)
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{
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assert(NULL != pwmParams);
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assert(0U != srcClock_Hz);
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assert(0U != pwmFreq_Hz);
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assert((uint32_t)pwmParams->output < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS);
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assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK));
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/* If we do not have enough events available (this function will create two events),
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* the function will return fail.
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*/
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status_t status = kStatus_Fail;
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status_t status2;
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uint32_t period, pulsePeriod = 0;
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uint32_t sctClock = srcClock_Hz / (((base->CTRL & SCT_CTRL_PRE_L_MASK) >> SCT_CTRL_PRE_L_SHIFT) + 1U);
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uint32_t periodEvent = 0, pulseEvent = 0;
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uint32_t reg;
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if ((s_currentEvent + 2U) <= (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS)
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{
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/* Use bi-directional mode for center-aligned PWM */
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if (mode == kSCTIMER_CenterAlignedPwm)
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{
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base->CTRL |= SCT_CTRL_BIDIR_L_MASK;
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}
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/* Calculate PWM period match value */
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if (mode == kSCTIMER_EdgeAlignedPwm)
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{
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period = (sctClock / pwmFreq_Hz) - 1U;
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}
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else
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{
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period = sctClock / (pwmFreq_Hz * 2U);
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}
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/* For 100% dutycyle, make pulse period greater than period so the event will never occur */
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if (pwmParams->dutyCyclePercent >= 100U)
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{
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pulsePeriod = period + 2U;
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}
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else
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{
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pulsePeriod = (uint32_t)(((uint64_t)period * pwmParams->dutyCyclePercent) / 100U);
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}
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/* Schedule an event when we reach the PWM period */
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status =
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SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, period, 0, kSCTIMER_Counter_U, &periodEvent);
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/* Schedule an event when we reach the pulse width */
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status2 = SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, pulsePeriod, 0, kSCTIMER_Counter_U,
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&pulseEvent);
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if ((kStatus_Success == status) && (kStatus_Success == status2))
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{
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/* Reset the counter when we reach the PWM period */
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SCTIMER_SetupCounterLimitAction(base, kSCTIMER_Counter_U, periodEvent);
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/* Return the period event to the user */
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*event = periodEvent;
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/* For high-true level */
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if ((uint32_t)pwmParams->level == (uint32_t)kSCTIMER_HighTrue)
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{
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if (mode == kSCTIMER_EdgeAlignedPwm)
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{
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/* Set the initial output level to low which is the inactive state */
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base->OUTPUT &= ~(1UL << (uint32_t)pwmParams->output);
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/* Set the output when we reach the PWM period */
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SCTIMER_SetupOutputSetAction(base, (uint32_t)pwmParams->output, periodEvent);
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/* Clear the output when we reach the PWM pulse value */
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SCTIMER_SetupOutputClearAction(base, (uint32_t)pwmParams->output, pulseEvent);
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}
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else
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{
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/* Set the initial output level to high which is the active state */
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base->OUTPUT |= (1UL << (uint32_t)pwmParams->output);
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/* Clear the output when we reach the PWM pulse event */
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SCTIMER_SetupOutputClearAction(base, (uint32_t)pwmParams->output, pulseEvent);
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/* Reverse output when down counting */
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reg = base->OUTPUTDIRCTRL;
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reg &= ~((uint32_t)SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2U * (uint32_t)pwmParams->output));
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reg |= (1UL << (2U * (uint32_t)pwmParams->output));
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base->OUTPUTDIRCTRL = reg;
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}
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}
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/* For low-true level */
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else
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{
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if (mode == kSCTIMER_EdgeAlignedPwm)
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{
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/* Set the initial output level to high which is the inactive state */
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base->OUTPUT |= (1UL << (uint32_t)pwmParams->output);
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/* Clear the output when we reach the PWM period */
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SCTIMER_SetupOutputClearAction(base, (uint32_t)pwmParams->output, periodEvent);
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/* Set the output when we reach the PWM pulse value */
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SCTIMER_SetupOutputSetAction(base, (uint32_t)pwmParams->output, pulseEvent);
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}
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else
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{
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/* Set the initial output level to low which is the active state */
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base->OUTPUT &= ~(1UL << (uint32_t)pwmParams->output);
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/* Set the output when we reach the PWM pulse event */
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SCTIMER_SetupOutputSetAction(base, (uint32_t)pwmParams->output, pulseEvent);
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/* Reverse output when down counting */
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reg = base->OUTPUTDIRCTRL;
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reg &= ~((uint32_t)SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2U * (uint32_t)pwmParams->output));
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reg |= (1UL << (2U * (uint32_t)pwmParams->output));
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base->OUTPUTDIRCTRL = reg;
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}
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}
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}
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else
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{
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status = kStatus_Fail;
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}
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}
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return status;
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}
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/*!
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* brief Updates the duty cycle of an active PWM signal.
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*
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* Before calling this function, the counter is set to operate as one 32-bit counter (unify bit is set to 1).
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*
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* param base SCTimer peripheral base address
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* param output The output to configure
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* param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100
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* param event Event number associated with this PWM signal. This was returned to the user by the
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* function SCTIMER_SetupPwm().
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*/
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void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event)
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{
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assert(dutyCyclePercent <= 100U);
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assert((uint32_t)output < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS);
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assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK));
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uint32_t periodMatchReg, pulseMatchReg;
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uint32_t pulsePeriod = 0, period;
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bool isHighTrue = (0U != (base->OUT[output].CLR & (1UL << (event + 1U))));
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/* Retrieve the match register number for the PWM period */
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periodMatchReg = base->EV[event].CTRL & SCT_EV_CTRL_MATCHSEL_MASK;
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/* Retrieve the match register number for the PWM pulse period */
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pulseMatchReg = base->EV[event + 1U].CTRL & SCT_EV_CTRL_MATCHSEL_MASK;
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period = base->MATCH[periodMatchReg];
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/* Stop the counter before updating match register */
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SCTIMER_StopTimer(base, (uint32_t)kSCTIMER_Counter_U);
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/* For 100% dutycyle, make pulse period greater than period so the event will never occur */
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if (dutyCyclePercent >= 100U)
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{
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pulsePeriod = period + 2U;
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/* Set the initial output level base on output mode */
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if (isHighTrue)
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{
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base->OUTPUT |= (1UL << (uint32_t)output);
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}
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else
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{
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base->OUTPUT &= ~(1UL << (uint32_t)output);
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}
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}
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else
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{
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pulsePeriod = (uint32_t)(((uint64_t)period * dutyCyclePercent) / 100U);
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}
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/* Update dutycycle */
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base->MATCH[pulseMatchReg] = pulsePeriod;
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base->MATCHREL[pulseMatchReg] = pulsePeriod;
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/* Restart the counter */
|
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SCTIMER_StartTimer(base, (uint32_t)kSCTIMER_Counter_U);
|
|
}
|
|
|
|
/*!
|
|
* brief Create an event that is triggered on a match or IO and schedule in current state.
|
|
*
|
|
* This function will configure an event using the options provided by the user. If the event type uses
|
|
* the counter match, then the function will set the user provided match value into a match register
|
|
* and put this match register number into the event control register.
|
|
* The event is enabled for the current state and the event number is increased by one at the end.
|
|
* The function returns the event number; this event number can be used to configure actions to be
|
|
* done when this event is triggered.
|
|
*
|
|
* param base SCTimer peripheral base address
|
|
* param howToMonitor Event type; options are available in the enumeration ::sctimer_interrupt_enable_t
|
|
* param matchValue The match value that will be programmed to a match register
|
|
* param whichIO The input or output that will be involved in event triggering. This field
|
|
* is ignored if the event type is "match only"
|
|
* param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H,
|
|
* In 32-bit mode, we can select Counter_U.
|
|
* param event Pointer to a variable where the new event number is stored
|
|
*
|
|
* return kStatus_Success on success
|
|
* kStatus_Error if we have hit the limit in terms of number of events created or
|
|
if we have reached the limit in terms of number of match registers
|
|
*/
|
|
status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base,
|
|
sctimer_event_t howToMonitor,
|
|
uint32_t matchValue,
|
|
uint32_t whichIO,
|
|
sctimer_counter_t whichCounter,
|
|
uint32_t *event)
|
|
{
|
|
uint32_t combMode = (((uint32_t)howToMonitor & SCT_EV_CTRL_COMBMODE_MASK) >> SCT_EV_CTRL_COMBMODE_SHIFT);
|
|
uint32_t currentCtrlVal = (uint32_t)howToMonitor;
|
|
status_t status = kStatus_Success;
|
|
uint32_t temp = 0;
|
|
|
|
if (s_currentEvent < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS)
|
|
{
|
|
if (2U == combMode)
|
|
{
|
|
base->EV[s_currentEvent].CTRL = currentCtrlVal | SCT_EV_CTRL_IOSEL(whichIO);
|
|
}
|
|
else
|
|
{
|
|
if ((0U == combMode) || (3U == combMode))
|
|
{
|
|
currentCtrlVal |= SCT_EV_CTRL_IOSEL(whichIO);
|
|
}
|
|
|
|
if ((kSCTIMER_Counter_L == whichCounter) && (0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)))
|
|
{
|
|
if (s_currentMatch < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE)
|
|
{
|
|
currentCtrlVal |= SCT_EV_CTRL_MATCHSEL(s_currentMatch);
|
|
|
|
/* Use Counter_L bits if user wants to setup the Low counter */
|
|
base->MATCH_ACCESS16BIT[s_currentMatch].MATCHL = (uint16_t)matchValue;
|
|
base->MATCHREL_ACCESS16BIT[s_currentMatch].MATCHRELL = (uint16_t)matchValue;
|
|
base->EV[s_currentEvent].CTRL = currentCtrlVal;
|
|
|
|
/* Increment the match register number */
|
|
s_currentMatch++;
|
|
}
|
|
else
|
|
{
|
|
/* An error would occur if we have hit the limit in terms of number of match registers */
|
|
status = kStatus_Fail;
|
|
}
|
|
}
|
|
else if ((kSCTIMER_Counter_H == whichCounter) && (0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)))
|
|
{
|
|
if (s_currentMatchhigh < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE)
|
|
{
|
|
currentCtrlVal |= SCT_EV_CTRL_MATCHSEL(s_currentMatchhigh);
|
|
|
|
/* Use Counter_H bits if user wants to setup the High counter */
|
|
currentCtrlVal |= SCT_EV_CTRL_HEVENT(1U);
|
|
temp = base->MATCH_ACCESS16BIT[s_currentMatchhigh].MATCHL;
|
|
base->MATCH[s_currentMatchhigh] = temp | (matchValue << 16U);
|
|
temp = base->MATCHREL_ACCESS16BIT[s_currentMatchhigh].MATCHRELL;
|
|
base->MATCHREL[s_currentMatchhigh] = temp | (matchValue << 16U);
|
|
|
|
base->EV[s_currentEvent].CTRL = currentCtrlVal;
|
|
/* Increment the match register number */
|
|
s_currentMatchhigh++;
|
|
}
|
|
else
|
|
{
|
|
/* An error would occur if we have hit the limit in terms of number of match registers */
|
|
status = kStatus_Fail;
|
|
}
|
|
}
|
|
else if ((kSCTIMER_Counter_U == whichCounter) && (0U != (base->CONFIG & SCT_CONFIG_UNIFY_MASK)))
|
|
{
|
|
if (s_currentMatch < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE)
|
|
{
|
|
/* Use Counter_L bits if counter is operating in 32-bit mode */
|
|
currentCtrlVal |= SCT_EV_CTRL_MATCHSEL(s_currentMatch);
|
|
|
|
base->MATCH[s_currentMatch] = matchValue;
|
|
base->MATCHREL[s_currentMatch] = matchValue;
|
|
base->EV[s_currentEvent].CTRL = currentCtrlVal;
|
|
|
|
/* Increment the match register number */
|
|
s_currentMatch++;
|
|
}
|
|
else
|
|
{
|
|
/* An error would occur if we have hit the limit in terms of number of match registers */
|
|
status = kStatus_Fail;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* The used counter must match the CONFIG[UNIFY] bit selection */
|
|
status = kStatus_Fail;
|
|
}
|
|
}
|
|
|
|
if (kStatus_Success == status)
|
|
{
|
|
/* Enable the event in the current state */
|
|
base->EV[s_currentEvent].STATE = (1UL << s_currentState);
|
|
|
|
/* Return the event number */
|
|
*event = s_currentEvent;
|
|
|
|
/* Increment the event number */
|
|
s_currentEvent++;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* An error would occur if we have hit the limit in terms of number of events created */
|
|
status = kStatus_Fail;
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
/*!
|
|
* brief Enable an event in the current state.
|
|
*
|
|
* This function will allow the event passed in to trigger in the current state. The event must
|
|
* be created earlier by either calling the function SCTIMER_SetupPwm() or function
|
|
* SCTIMER_CreateAndScheduleEvent() .
|
|
*
|
|
* param base SCTimer peripheral base address
|
|
* param event Event number to enable in the current state
|
|
*
|
|
*/
|
|
void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event)
|
|
{
|
|
/* Enable event in the current state */
|
|
base->EV[event].STATE |= (1UL << s_currentState);
|
|
}
|
|
|
|
/*!
|
|
* brief Increase the state by 1
|
|
*
|
|
* All future events created by calling the function SCTIMER_ScheduleEvent() will be enabled in this new
|
|
* state.
|
|
*
|
|
* param base SCTimer peripheral base address
|
|
*
|
|
* return kStatus_Success on success
|
|
* kStatus_Error if we have hit the limit in terms of states used
|
|
|
|
*/
|
|
status_t SCTIMER_IncreaseState(SCT_Type *base)
|
|
{
|
|
status_t status = kStatus_Success;
|
|
|
|
/* Return an error if we have hit the limit in terms of states used */
|
|
if (s_currentState >= (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES)
|
|
{
|
|
status = kStatus_Fail;
|
|
}
|
|
else
|
|
{
|
|
s_currentState++;
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
/*!
|
|
* brief Provides the current state
|
|
*
|
|
* User can use this to set the next state by calling the function SCTIMER_SetupNextStateAction().
|
|
*
|
|
* param base SCTimer peripheral base address
|
|
*
|
|
* return The current state
|
|
*/
|
|
uint32_t SCTIMER_GetCurrentState(SCT_Type *base)
|
|
{
|
|
return s_currentState;
|
|
}
|
|
|
|
/*!
|
|
* brief Toggle the output level.
|
|
*
|
|
* This change in the output level is triggered by the event number that is passed in by the user.
|
|
*
|
|
* param base SCTimer peripheral base address
|
|
* param whichIO The output to toggle
|
|
* param event Event number that will trigger the output change
|
|
*/
|
|
void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event)
|
|
{
|
|
assert(whichIO < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS);
|
|
|
|
uint32_t reg;
|
|
|
|
/* Set the same event to set and clear the output */
|
|
base->OUT[whichIO].CLR |= (1UL << event);
|
|
base->OUT[whichIO].SET |= (1UL << event);
|
|
|
|
/* Set the conflict resolution to toggle output */
|
|
reg = base->RES;
|
|
reg &= ~(((uint32_t)SCT_RES_O0RES_MASK) << (2U * whichIO));
|
|
reg |= ((uint32_t)(kSCTIMER_ResolveToggle)) << (2U * whichIO);
|
|
base->RES = reg;
|
|
}
|
|
|
|
/*!
|
|
* brief Setup capture of the counter value on trigger of a selected event
|
|
*
|
|
* param base SCTimer peripheral base address
|
|
* param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H,
|
|
* In 32-bit mode, we can select Counter_U.
|
|
* param captureRegister Pointer to a variable where the capture register number will be returned. User
|
|
* can read the captured value from this register when the specified event is triggered.
|
|
* param event Event number that will trigger the capture
|
|
*
|
|
* return kStatus_Success on success
|
|
* kStatus_Error if we have hit the limit in terms of number of match/capture registers available
|
|
*/
|
|
status_t SCTIMER_SetupCaptureAction(SCT_Type *base,
|
|
sctimer_counter_t whichCounter,
|
|
uint32_t *captureRegister,
|
|
uint32_t event)
|
|
{
|
|
status_t status;
|
|
uint32_t temp = 0;
|
|
|
|
if ((kSCTIMER_Counter_L == whichCounter) || (kSCTIMER_Counter_U == whichCounter))
|
|
{
|
|
if (s_currentMatch < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE)
|
|
{
|
|
/* Set the bit to enable event */
|
|
base->CAPCTRL_ACCESS16BIT[s_currentMatch].CAPCTRLL |= SCT_CAPCTRLL_CAPCTRLL(1UL << event);
|
|
|
|
/* Set this resource to be a capture rather than match */
|
|
base->REGMODE_ACCESS16BIT.REGMODEL |= SCT_REGMODEL_REGMODEL(1UL << s_currentMatch);
|
|
|
|
/* Return the match register number */
|
|
*captureRegister = s_currentMatch;
|
|
|
|
/* Increase the match register number */
|
|
s_currentMatch++;
|
|
|
|
status = kStatus_Success;
|
|
}
|
|
else
|
|
{
|
|
/* Return an error if we have hit the limit in terms of number of capture/match registers used */
|
|
status = kStatus_Fail;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (s_currentMatchhigh < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE)
|
|
{
|
|
/* Set bit to enable event */
|
|
temp = base->CAPCTRL_ACCESS16BIT[s_currentMatchhigh].CAPCTRLL;
|
|
base->CAPCTRL[s_currentMatchhigh] = temp | ((uint32_t)((uint32_t)(1UL << event) << 16U) & 0xFFFF000U);
|
|
/* Set this resource to be a capture rather than match */
|
|
temp = base->REGMODE_ACCESS16BIT.REGMODEL;
|
|
base->REGMODE = temp | ((uint32_t)((uint32_t)(1UL << s_currentMatchhigh) << 16U) & 0xFFFF000U);
|
|
|
|
/* Return the match register number */
|
|
*captureRegister = s_currentMatchhigh;
|
|
|
|
/* Increase the match register number */
|
|
s_currentMatchhigh++;
|
|
|
|
status = kStatus_Success;
|
|
}
|
|
else
|
|
{
|
|
/* Return an error if we have hit the limit in terms of number of capture/match registers used */
|
|
status = kStatus_Fail;
|
|
}
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
/*!
|
|
* brief Receive noticification when the event trigger an interrupt.
|
|
*
|
|
* If the interrupt for the event is enabled by the user, then a callback can be registered
|
|
* which will be invoked when the event is triggered
|
|
*
|
|
* param base SCTimer peripheral base address
|
|
* param event Event number that will trigger the interrupt
|
|
* param callback Function to invoke when the event is triggered
|
|
*/
|
|
|
|
void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event)
|
|
{
|
|
s_eventCallback[event] = callback;
|
|
}
|
|
|
|
/*!
|
|
* brief SCTimer interrupt handler.
|
|
*
|
|
* param base SCTimer peripheral base address.
|
|
*/
|
|
void SCTIMER_EventHandleIRQ(SCT_Type *base)
|
|
{
|
|
uint32_t eventFlag = base->EVFLAG;
|
|
/* Only clear the flags whose interrupt field is enabled */
|
|
uint32_t clearFlag = (eventFlag & base->EVEN);
|
|
uint32_t mask = eventFlag;
|
|
uint32_t i;
|
|
|
|
/* Invoke the callback for certain events */
|
|
for (i = 0; i < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS; i++)
|
|
{
|
|
if ((mask & 0x1U) != 0U)
|
|
{
|
|
if (s_eventCallback[i] != NULL)
|
|
{
|
|
s_eventCallback[i]();
|
|
}
|
|
}
|
|
mask >>= 1UL;
|
|
|
|
if (0U == mask)
|
|
{
|
|
/* All events have been handled. */
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Clear event interrupt flag */
|
|
base->EVFLAG = clearFlag;
|
|
}
|
|
|
|
#if defined(SCT0)
|
|
void SCT0_DriverIRQHandler(void);
|
|
void SCT0_DriverIRQHandler(void)
|
|
{
|
|
s_sctimerIsr(SCT0);
|
|
SDK_ISR_EXIT_BARRIER;
|
|
}
|
|
#endif
|
|
|
|
#if defined(SCT)
|
|
void SCT_DriverIRQHandler(void);
|
|
void SCT_DriverIRQHandler(void)
|
|
{
|
|
s_sctimerIsr(SCT);
|
|
SDK_ISR_EXIT_BARRIER;
|
|
}
|
|
#endif
|