759 lines
26 KiB
C
759 lines
26 KiB
C
/*
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2020,2022 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef FSL_SPI_H_
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#define FSL_SPI_H_
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#include "fsl_common.h"
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#include "fsl_flexcomm.h"
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/*!
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* @addtogroup spi_driver
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* @{
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*/
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/*! @file */
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @name Driver version */
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/*! @{ */
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/*! @brief SPI driver version. */
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#define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 3, 1))
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/*! @} */
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/*! @brief SPI default SSEL COUNT*/
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#if !(defined(FSL_FEATURE_SPI_SSEL_COUNT) || defined(FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE))
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#define FSL_FEATURE_SPI_SSEL_COUNT (4U)
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#endif
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/*! @brief Global variable for dummy data value setting. */
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extern volatile uint8_t s_dummyData[];
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#ifndef SPI_DUMMYDATA
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/*! @brief SPI dummy transfer data, the data is sent while txBuff is NULL. */
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#define SPI_DUMMYDATA (0x00U)
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#endif
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/*! @brief Retry times for waiting flag. */
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#ifndef SPI_RETRY_TIMES
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#define SPI_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */
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#endif
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#define SPI_DATA(n) (((uint32_t)(n)) & 0xFFFFUL)
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#define SPI_CTRLMASK (0xFFFF0000U)
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#define SPI_ASSERTNUM_SSEL(n) ((~(1UL << ((n) + 16UL))) & 0xF0000UL)
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#define SPI_DEASSERTNUM_SSEL(n) (1UL << ((n) + 16UL))
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#define SPI_DEASSERT_ALL (0xF0000UL)
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#define SPI_FIFOWR_FLAGS_MASK (~(SPI_DEASSERT_ALL | SPI_FIFOWR_TXDATA_MASK | SPI_FIFOWR_LEN_MASK))
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#define SPI_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_TXLVL_MASK) >> SPI_FIFOTRIG_TXLVL_SHIFT)
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#define SPI_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_RXLVL_MASK) >> SPI_FIFOTRIG_RXLVL_SHIFT)
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/*! @brief SPI transfer option.*/
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typedef enum _spi_xfer_option
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{
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kSPI_FrameDelay = (SPI_FIFOWR_EOF_MASK), /*!< A delay may be inserted, defined in the DLY register.*/
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kSPI_FrameAssert = (SPI_FIFOWR_EOT_MASK), /*!< SSEL will be deasserted at the end of a transfer */
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} spi_xfer_option_t;
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/*! @brief SPI data shifter direction options.*/
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typedef enum _spi_shift_direction
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{
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kSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit. */
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kSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit. */
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} spi_shift_direction_t;
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/*! @brief SPI clock polarity configuration.*/
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typedef enum _spi_clock_polarity
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{
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kSPI_ClockPolarityActiveHigh = 0x0U, /*!< Active-high SPI clock (idles low). */
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kSPI_ClockPolarityActiveLow /*!< Active-low SPI clock (idles high). */
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} spi_clock_polarity_t;
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/*! @brief SPI clock phase configuration.*/
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typedef enum _spi_clock_phase
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{
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kSPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SCK occurs at the middle of the first
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* cycle of a data transfer. */
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kSPI_ClockPhaseSecondEdge /*!< First edge on SCK occurs at the start of the
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* first cycle of a data transfer. */
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} spi_clock_phase_t;
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/*! @brief txFIFO watermark values */
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typedef enum _spi_txfifo_watermark
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{
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kSPI_TxFifo0 = 0, /*!< SPI tx watermark is empty */
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kSPI_TxFifo1 = 1, /*!< SPI tx watermark at 1 item */
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kSPI_TxFifo2 = 2, /*!< SPI tx watermark at 2 items */
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kSPI_TxFifo3 = 3, /*!< SPI tx watermark at 3 items */
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kSPI_TxFifo4 = 4, /*!< SPI tx watermark at 4 items */
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kSPI_TxFifo5 = 5, /*!< SPI tx watermark at 5 items */
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kSPI_TxFifo6 = 6, /*!< SPI tx watermark at 6 items */
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kSPI_TxFifo7 = 7, /*!< SPI tx watermark at 7 items */
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} spi_txfifo_watermark_t;
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/*! @brief rxFIFO watermark values */
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typedef enum _spi_rxfifo_watermark
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{
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kSPI_RxFifo1 = 0, /*!< SPI rx watermark at 1 item */
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kSPI_RxFifo2 = 1, /*!< SPI rx watermark at 2 items */
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kSPI_RxFifo3 = 2, /*!< SPI rx watermark at 3 items */
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kSPI_RxFifo4 = 3, /*!< SPI rx watermark at 4 items */
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kSPI_RxFifo5 = 4, /*!< SPI rx watermark at 5 items */
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kSPI_RxFifo6 = 5, /*!< SPI rx watermark at 6 items */
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kSPI_RxFifo7 = 6, /*!< SPI rx watermark at 7 items */
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kSPI_RxFifo8 = 7, /*!< SPI rx watermark at 8 items */
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} spi_rxfifo_watermark_t;
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/*! @brief Transfer data width */
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typedef enum _spi_data_width
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{
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kSPI_Data4Bits = 3, /*!< 4 bits data width */
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kSPI_Data5Bits = 4, /*!< 5 bits data width */
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kSPI_Data6Bits = 5, /*!< 6 bits data width */
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kSPI_Data7Bits = 6, /*!< 7 bits data width */
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kSPI_Data8Bits = 7, /*!< 8 bits data width */
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kSPI_Data9Bits = 8, /*!< 9 bits data width */
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kSPI_Data10Bits = 9, /*!< 10 bits data width */
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kSPI_Data11Bits = 10, /*!< 11 bits data width */
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kSPI_Data12Bits = 11, /*!< 12 bits data width */
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kSPI_Data13Bits = 12, /*!< 13 bits data width */
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kSPI_Data14Bits = 13, /*!< 14 bits data width */
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kSPI_Data15Bits = 14, /*!< 15 bits data width */
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kSPI_Data16Bits = 15, /*!< 16 bits data width */
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} spi_data_width_t;
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/*! @brief Slave select */
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typedef enum _spi_ssel
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{
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kSPI_Ssel0 = 0, /*!< Slave select 0 */
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kSPI_Ssel1 = 1, /*!< Slave select 1 */
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kSPI_Ssel2 = 2, /*!< Slave select 2 */
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kSPI_Ssel3 = 3, /*!< Slave select 3 */
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} spi_ssel_t;
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/*! @brief ssel polarity */
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typedef enum _spi_spol
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{
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kSPI_Spol0ActiveHigh = SPI_CFG_SPOL0(1),
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kSPI_Spol1ActiveHigh = SPI_CFG_SPOL1(1),
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#if ((defined(FSL_FEATURE_SPI_SSEL_COUNT) && (FSL_FEATURE_SPI_SSEL_COUNT > 2)) || \
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(defined(FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) && \
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(FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE)))
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kSPI_Spol2ActiveHigh = SPI_CFG_SPOL2(1),
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#endif
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#if defined(FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) && (FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE)
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kSPI_SpolActiveAllHigh = (kSPI_Spol0ActiveHigh | kSPI_Spol1ActiveHigh | kSPI_Spol2ActiveHigh),
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#else
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#if (defined(FSL_FEATURE_SPI_SSEL_COUNT) && (FSL_FEATURE_SPI_SSEL_COUNT == 2))
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kSPI_SpolActiveAllHigh = (kSPI_Spol0ActiveHigh | kSPI_Spol1ActiveHigh),
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#else
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kSPI_Spol3ActiveHigh = SPI_CFG_SPOL3(1),
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kSPI_SpolActiveAllHigh =
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(kSPI_Spol0ActiveHigh | kSPI_Spol1ActiveHigh | kSPI_Spol2ActiveHigh | kSPI_Spol3ActiveHigh),
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#endif /* FSL_FEATURE_SPI_SSEL_COUNT == 2 */
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#endif /* FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE */
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kSPI_SpolActiveAllLow = 0,
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} spi_spol_t;
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/*!
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* @brief SPI delay time configure structure.
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* Note:
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* The DLY register controls several programmable delays related to SPI signalling,
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* it stands for how many SPI clock time will be inserted.
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* The maxinun value of these delay time is 15.
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*/
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typedef struct _spi_delay_config
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{
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uint8_t preDelay; /*!< Delay between SSEL assertion and the beginning of transfer. */
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uint8_t postDelay; /*!< Delay between the end of transfer and SSEL deassertion. */
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uint8_t frameDelay; /*!< Delay between frame to frame. */
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uint8_t transferDelay; /*!< Delay between transfer to transfer. */
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} spi_delay_config_t;
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/*! @brief SPI master user configure structure.*/
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typedef struct _spi_master_config
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{
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bool enableLoopback; /*!< Enable loopback for test purpose */
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bool enableMaster; /*!< Enable SPI at initialization time */
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spi_clock_polarity_t polarity; /*!< Clock polarity */
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spi_clock_phase_t phase; /*!< Clock phase */
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spi_shift_direction_t direction; /*!< MSB or LSB */
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uint32_t baudRate_Bps; /*!< Baud Rate for SPI in Hz */
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spi_data_width_t dataWidth; /*!< Width of the data */
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spi_ssel_t sselNum; /*!< Slave select number */
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spi_spol_t sselPol; /*!< Configure active CS polarity */
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uint8_t txWatermark; /*!< txFIFO watermark */
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uint8_t rxWatermark; /*!< rxFIFO watermark */
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spi_delay_config_t delayConfig; /*!< Delay configuration. */
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} spi_master_config_t;
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/*! @brief SPI slave user configure structure.*/
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typedef struct _spi_slave_config
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{
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bool enableSlave; /*!< Enable SPI at initialization time */
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spi_clock_polarity_t polarity; /*!< Clock polarity */
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spi_clock_phase_t phase; /*!< Clock phase */
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spi_shift_direction_t direction; /*!< MSB or LSB */
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spi_data_width_t dataWidth; /*!< Width of the data */
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spi_spol_t sselPol; /*!< Configure active CS polarity */
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uint8_t txWatermark; /*!< txFIFO watermark */
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uint8_t rxWatermark; /*!< rxFIFO watermark */
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} spi_slave_config_t;
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/*! @brief SPI transfer status.*/
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enum
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{
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kStatus_SPI_Busy = MAKE_STATUS(kStatusGroup_LPC_SPI, 0), /*!< SPI bus is busy */
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kStatus_SPI_Idle = MAKE_STATUS(kStatusGroup_LPC_SPI, 1), /*!< SPI is idle */
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kStatus_SPI_Error = MAKE_STATUS(kStatusGroup_LPC_SPI, 2), /*!< SPI error */
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kStatus_SPI_BaudrateNotSupport =
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MAKE_STATUS(kStatusGroup_LPC_SPI, 3), /*!< Baudrate is not support in current clock source */
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kStatus_SPI_Timeout = MAKE_STATUS(kStatusGroup_LPC_SPI, 4) /*!< SPI timeout polling status flags. */
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};
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/*! @brief SPI interrupt sources.*/
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enum _spi_interrupt_enable
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{
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kSPI_RxLvlIrq = SPI_FIFOINTENSET_RXLVL_MASK, /*!< Rx level interrupt */
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kSPI_TxLvlIrq = SPI_FIFOINTENSET_TXLVL_MASK, /*!< Tx level interrupt */
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};
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/*! @brief SPI status flags.*/
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enum _spi_statusflags
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{
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kSPI_TxEmptyFlag = SPI_FIFOSTAT_TXEMPTY_MASK, /*!< txFifo is empty */
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kSPI_TxNotFullFlag = SPI_FIFOSTAT_TXNOTFULL_MASK, /*!< txFifo is not full */
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kSPI_RxNotEmptyFlag = SPI_FIFOSTAT_RXNOTEMPTY_MASK, /*!< rxFIFO is not empty */
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kSPI_RxFullFlag = SPI_FIFOSTAT_RXFULL_MASK, /*!< rxFIFO is full */
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};
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/*! @brief SPI transfer structure */
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typedef struct _spi_transfer
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{
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uint8_t *txData; /*!< Send buffer */
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uint8_t *rxData; /*!< Receive buffer */
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uint32_t configFlags; /*!< Additional option to control transfer, @ref spi_xfer_option_t. */
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size_t dataSize; /*!< Transfer bytes */
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} spi_transfer_t;
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/*! @brief SPI half-duplex(master only) transfer structure */
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typedef struct _spi_half_duplex_transfer
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{
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uint8_t *txData; /*!< Send buffer */
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uint8_t *rxData; /*!< Receive buffer */
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size_t txDataSize; /*!< Transfer bytes for transmit */
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size_t rxDataSize; /*!< Transfer bytes */
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uint32_t configFlags; /*!< Transfer configuration flags, @ref spi_xfer_option_t. */
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bool isPcsAssertInTransfer; /*!< If PCS pin keep assert between transmit and receive. true for assert and false for
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deassert. */
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bool isTransmitFirst; /*!< True for transmit first and false for receive first. */
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} spi_half_duplex_transfer_t;
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/*! @brief Internal configuration structure used in 'spi' and 'spi_dma' driver */
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typedef struct _spi_config
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{
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spi_data_width_t dataWidth;
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spi_ssel_t sselNum;
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} spi_config_t;
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/*! @brief Master handle type */
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typedef struct _spi_master_handle spi_master_handle_t;
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/*! @brief Slave handle type */
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typedef spi_master_handle_t spi_slave_handle_t;
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/*! @brief SPI master callback for finished transmit */
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typedef void (*spi_master_callback_t)(SPI_Type *base, spi_master_handle_t *handle, status_t status, void *userData);
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/*! @brief SPI slave callback for finished transmit */
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typedef void (*spi_slave_callback_t)(SPI_Type *base, spi_slave_handle_t *handle, status_t status, void *userData);
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/*! @brief SPI transfer handle structure */
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struct _spi_master_handle
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{
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uint8_t *volatile txData; /*!< Transfer buffer */
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uint8_t *volatile rxData; /*!< Receive buffer */
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volatile size_t txRemainingBytes; /*!< Number of data to be transmitted [in bytes] */
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volatile size_t rxRemainingBytes; /*!< Number of data to be received [in bytes] */
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volatile int8_t toReceiveCount; /*!< The number of data expected to receive in data width. Since the received count
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and sent count should be the same to complete the transfer, if the sent count is
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x and the received count is y, toReceiveCount is x-y. */
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size_t totalByteCount; /*!< A number of transfer bytes */
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volatile uint32_t state; /*!< SPI internal state */
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spi_master_callback_t callback; /*!< SPI callback */
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void *userData; /*!< Callback parameter */
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uint8_t dataWidth; /*!< Width of the data [Valid values: 1 to 16] */
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uint8_t sselNum; /*!< Slave select number to be asserted when transferring data [Valid values: 0 to 3] */
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uint32_t configFlags; /*!< Additional option to control transfer */
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uint8_t txWatermark; /*!< txFIFO watermark */
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uint8_t rxWatermark; /*!< rxFIFO watermark */
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};
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/*! @brief Typedef for master interrupt handler. */
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typedef void (*flexcomm_spi_master_irq_handler_t)(SPI_Type *base, spi_master_handle_t *handle);
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/*! @brief Typedef for slave interrupt handler. */
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typedef void (*flexcomm_spi_slave_irq_handler_t)(SPI_Type *base, spi_slave_handle_t *handle);
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/*! @} */
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/*******************************************************************************
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* API
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/*! @brief Returns instance number for SPI peripheral base address. */
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uint32_t SPI_GetInstance(SPI_Type *base);
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/*!
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* @name Initialization and deinitialization
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* @{
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*/
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/*!
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* @brief Sets the SPI master configuration structure to default values.
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*
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* The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit().
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* User may use the initialized structure unchanged in SPI_MasterInit(), or modify
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* some fields of the structure before calling SPI_MasterInit(). After calling this API,
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* the master is ready to transfer.
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* Example:
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@code
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spi_master_config_t config;
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SPI_MasterGetDefaultConfig(&config);
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@endcode
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*
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* @param config pointer to master config structure
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*/
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void SPI_MasterGetDefaultConfig(spi_master_config_t *config);
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/*!
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* @brief Initializes the SPI with master configuration.
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*
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* The configuration structure can be filled by user from scratch, or be set with default
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* values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer.
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* Example
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@code
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spi_master_config_t config = {
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.baudRate_Bps = 400000,
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...
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};
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SPI_MasterInit(SPI0, &config);
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@endcode
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*
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* @param base SPI base pointer
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* @param config pointer to master configuration structure
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* @param srcClock_Hz Source clock frequency.
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*/
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status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz);
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/*!
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* @brief Sets the SPI slave configuration structure to default values.
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*
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* The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit().
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* Modify some fields of the structure before calling SPI_SlaveInit().
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* Example:
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@code
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spi_slave_config_t config;
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SPI_SlaveGetDefaultConfig(&config);
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@endcode
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*
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* @param config pointer to slave configuration structure
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*/
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void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config);
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/*!
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* @brief Initializes the SPI with slave configuration.
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*
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* The configuration structure can be filled by user from scratch or be set with
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* default values by SPI_SlaveGetDefaultConfig().
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* After calling this API, the slave is ready to transfer.
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* Example
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@code
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spi_slave_config_t config = {
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.polarity = flexSPIClockPolarity_ActiveHigh;
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.phase = flexSPIClockPhase_FirstEdge;
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.direction = flexSPIMsbFirst;
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...
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};
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SPI_SlaveInit(SPI0, &config);
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@endcode
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*
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* @param base SPI base pointer
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* @param config pointer to slave configuration structure
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*/
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status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config);
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/*!
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* @brief De-initializes the SPI.
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*
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* Calling this API resets the SPI module, gates the SPI clock.
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* The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module.
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*
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* @param base SPI base pointer
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*/
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void SPI_Deinit(SPI_Type *base);
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/*!
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* @brief Enable or disable the SPI Master or Slave
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* @param base SPI base pointer
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* @param enable or disable ( true = enable, false = disable)
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*/
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static inline void SPI_Enable(SPI_Type *base, bool enable)
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{
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if (enable)
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{
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base->CFG |= SPI_CFG_ENABLE_MASK;
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}
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else
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{
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base->CFG &= ~SPI_CFG_ENABLE_MASK;
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}
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}
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/*! @} */
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/*!
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* @name Status
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* @{
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*/
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/*!
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* @brief Gets the status flag.
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*
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* @param base SPI base pointer
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* @return SPI Status, use status flag to AND @ref _spi_statusflags could get the related status.
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*/
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static inline uint32_t SPI_GetStatusFlags(SPI_Type *base)
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{
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assert(NULL != base);
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return base->FIFOSTAT;
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}
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/*! @} */
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/*!
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* @name Interrupts
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* @{
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*/
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/*!
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* @brief Enables the interrupt for the SPI.
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*
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* @param base SPI base pointer
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* @param irqs SPI interrupt source. The parameter can be any combination of the following values:
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* @arg kSPI_RxLvlIrq
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|
* @arg kSPI_TxLvlIrq
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|
*/
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static inline void SPI_EnableInterrupts(SPI_Type *base, uint32_t irqs)
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|
{
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assert(NULL != base);
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base->FIFOINTENSET = irqs;
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}
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|
/*!
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|
* @brief Disables the interrupt for the SPI.
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*
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* @param base SPI base pointer
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* @param irqs SPI interrupt source. The parameter can be any combination of the following values:
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* @arg kSPI_RxLvlIrq
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* @arg kSPI_TxLvlIrq
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|
*/
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static inline void SPI_DisableInterrupts(SPI_Type *base, uint32_t irqs)
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|
{
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assert(NULL != base);
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base->FIFOINTENCLR = irqs;
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}
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/*! @} */
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/*!
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* @name DMA Control
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* @{
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|
*/
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|
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/*!
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* @brief Enables the DMA request from SPI txFIFO.
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*
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* @param base SPI base pointer
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* @param enable True means enable DMA, false means disable DMA
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|
*/
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void SPI_EnableTxDMA(SPI_Type *base, bool enable);
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/*!
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* @brief Enables the DMA request from SPI rxFIFO.
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*
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* @param base SPI base pointer
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* @param enable True means enable DMA, false means disable DMA
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*/
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void SPI_EnableRxDMA(SPI_Type *base, bool enable);
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/*! @} */
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|
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/*!
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* @name Bus Operations
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* @{
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|
*/
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/*!
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|
* @brief Returns the configurations.
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*
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* @param base SPI peripheral address.
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* @return return configurations which contain datawidth and SSEL numbers.
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* return data type is a pointer of spi_config_t.
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|
*/
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|
void *SPI_GetConfig(SPI_Type *base);
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|
/*!
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* @brief Sets the baud rate for SPI transfer. This is only used in master.
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*
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* @param base SPI base pointer
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* @param baudrate_Bps baud rate needed in Hz.
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* @param srcClock_Hz SPI source clock frequency in Hz.
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|
*/
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status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz);
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|
|
|
/*!
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|
* @brief Writes a data into the SPI data register.
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|
*
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|
* @param base SPI base pointer
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* @param data needs to be write.
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* @param configFlags transfer configuration options @ref spi_xfer_option_t
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|
*/
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|
void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags);
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|
/*!
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|
* @brief Gets a data from the SPI data register.
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*
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* @param base SPI base pointer
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|
* @return Data in the register.
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|
*/
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|
static inline uint32_t SPI_ReadData(SPI_Type *base)
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|
{
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|
assert(NULL != base);
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|
return base->FIFORD;
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|
}
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|
|
|
/*!
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|
* @brief Set delay time for transfer.
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|
* the delay uint is SPI clock time, maximum value is 0xF.
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|
* @param base SPI base pointer
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|
* @param config configuration for delay option @ref spi_delay_config_t.
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|
*/
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|
static inline void SPI_SetTransferDelay(SPI_Type *base, const spi_delay_config_t *config)
|
|
{
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|
assert(NULL != base);
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|
assert(NULL != config);
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|
base->DLY = (SPI_DLY_PRE_DELAY(config->preDelay) | SPI_DLY_POST_DELAY(config->postDelay) |
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SPI_DLY_FRAME_DELAY(config->frameDelay) | SPI_DLY_TRANSFER_DELAY(config->transferDelay));
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|
}
|
|
|
|
/*!
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|
* @brief Set up the dummy data.
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|
*
|
|
* @param base SPI peripheral address.
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|
* @param dummyData Data to be transferred when tx buffer is NULL.
|
|
*/
|
|
void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData);
|
|
|
|
/*! @} */
|
|
|
|
/*!
|
|
* @name Transactional
|
|
* @{
|
|
*/
|
|
|
|
/*!
|
|
* @brief Initializes the SPI master handle.
|
|
*
|
|
* This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually,
|
|
* for a specified SPI instance, call this API once to get the initialized handle.
|
|
*
|
|
* @param base SPI peripheral base address.
|
|
* @param handle SPI handle pointer.
|
|
* @param callback Callback function.
|
|
* @param userData User data.
|
|
*/
|
|
status_t SPI_MasterTransferCreateHandle(SPI_Type *base,
|
|
spi_master_handle_t *handle,
|
|
spi_master_callback_t callback,
|
|
void *userData);
|
|
|
|
/*!
|
|
* @brief Transfers a block of data using a polling method.
|
|
*
|
|
* @param base SPI base pointer
|
|
* @param xfer pointer to spi_xfer_config_t structure
|
|
* @retval kStatus_Success Successfully start a transfer.
|
|
* @retval kStatus_InvalidArgument Input argument is invalid.
|
|
* @retval kStatus_SPI_Timeout The transfer timed out and was aborted.
|
|
*/
|
|
status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer);
|
|
|
|
/*!
|
|
* @brief Performs a non-blocking SPI interrupt transfer.
|
|
*
|
|
* @param base SPI peripheral base address.
|
|
* @param handle pointer to spi_master_handle_t structure which stores the transfer state
|
|
* @param xfer pointer to spi_xfer_config_t structure
|
|
* @retval kStatus_Success Successfully start a transfer.
|
|
* @retval kStatus_InvalidArgument Input argument is invalid.
|
|
* @retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
|
|
*/
|
|
status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer);
|
|
|
|
/*!
|
|
* @brief Transfers a block of data using a polling method.
|
|
*
|
|
* This function will do a half-duplex transfer for SPI master, This is a blocking function,
|
|
* which does not retuen until all transfer have been completed. And data transfer mechanism is half-duplex,
|
|
* users can set transmit first or receive first.
|
|
*
|
|
* @param base SPI base pointer
|
|
* @param xfer pointer to spi_half_duplex_transfer_t structure
|
|
* @return status of status_t.
|
|
*/
|
|
status_t SPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, spi_half_duplex_transfer_t *xfer);
|
|
|
|
/*!
|
|
* @brief Performs a non-blocking SPI interrupt transfer.
|
|
*
|
|
* This function using polling way to do the first half transimission and using interrupts to
|
|
* do the second half transimission, the transfer mechanism is half-duplex.
|
|
* When do the second half transimission, code will return right away. When all data is transferred,
|
|
* the callback function is called.
|
|
*
|
|
* @param base SPI peripheral base address.
|
|
* @param handle pointer to spi_master_handle_t structure which stores the transfer state
|
|
* @param xfer pointer to spi_half_duplex_transfer_t structure
|
|
* @return status of status_t.
|
|
*/
|
|
status_t SPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base,
|
|
spi_master_handle_t *handle,
|
|
spi_half_duplex_transfer_t *xfer);
|
|
|
|
/*!
|
|
* @brief Gets the master transfer count.
|
|
*
|
|
* This function gets the master transfer count.
|
|
*
|
|
* @param base SPI peripheral base address.
|
|
* @param handle Pointer to the spi_master_handle_t structure which stores the transfer state.
|
|
* @param count The number of bytes transferred by using the non-blocking transaction.
|
|
* @return status of status_t.
|
|
*/
|
|
status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count);
|
|
|
|
/*!
|
|
* @brief SPI master aborts a transfer using an interrupt.
|
|
*
|
|
* This function aborts a transfer using an interrupt.
|
|
*
|
|
* @param base SPI peripheral base address.
|
|
* @param handle Pointer to the spi_master_handle_t structure which stores the transfer state.
|
|
*/
|
|
void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle);
|
|
|
|
/*!
|
|
* @brief Interrupts the handler for the SPI.
|
|
*
|
|
* @param base SPI peripheral base address.
|
|
* @param handle pointer to spi_master_handle_t structure which stores the transfer state.
|
|
*/
|
|
void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle);
|
|
|
|
/*!
|
|
* @brief Initializes the SPI slave handle.
|
|
*
|
|
* This function initializes the SPI slave handle which can be used for other SPI slave transactional APIs. Usually,
|
|
* for a specified SPI instance, call this API once to get the initialized handle.
|
|
*
|
|
* @param base SPI peripheral base address.
|
|
* @param handle SPI handle pointer.
|
|
* @param callback Callback function.
|
|
* @param userData User data.
|
|
*/
|
|
static inline status_t SPI_SlaveTransferCreateHandle(SPI_Type *base,
|
|
spi_slave_handle_t *handle,
|
|
spi_slave_callback_t callback,
|
|
void *userData)
|
|
{
|
|
return SPI_MasterTransferCreateHandle(base, handle, callback, userData);
|
|
}
|
|
|
|
/*!
|
|
* @brief Performs a non-blocking SPI slave interrupt transfer.
|
|
*
|
|
* @note The API returns immediately after the transfer initialization is finished.
|
|
*
|
|
* @param base SPI peripheral base address.
|
|
* @param handle pointer to spi_master_handle_t structure which stores the transfer state
|
|
* @param xfer pointer to spi_xfer_config_t structure
|
|
* @retval kStatus_Success Successfully start a transfer.
|
|
* @retval kStatus_InvalidArgument Input argument is invalid.
|
|
* @retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
|
|
*/
|
|
static inline status_t SPI_SlaveTransferNonBlocking(SPI_Type *base, spi_slave_handle_t *handle, spi_transfer_t *xfer)
|
|
{
|
|
return SPI_MasterTransferNonBlocking(base, handle, xfer);
|
|
}
|
|
|
|
/*!
|
|
* @brief Gets the slave transfer count.
|
|
*
|
|
* This function gets the slave transfer count.
|
|
*
|
|
* @param base SPI peripheral base address.
|
|
* @param handle Pointer to the spi_master_handle_t structure which stores the transfer state.
|
|
* @param count The number of bytes transferred by using the non-blocking transaction.
|
|
* @return status of status_t.
|
|
*/
|
|
static inline status_t SPI_SlaveTransferGetCount(SPI_Type *base, spi_slave_handle_t *handle, size_t *count)
|
|
{
|
|
return SPI_MasterTransferGetCount(base, (spi_master_handle_t *)handle, count);
|
|
}
|
|
|
|
/*!
|
|
* @brief SPI slave aborts a transfer using an interrupt.
|
|
*
|
|
* This function aborts a transfer using an interrupt.
|
|
*
|
|
* @param base SPI peripheral base address.
|
|
* @param handle Pointer to the spi_slave_handle_t structure which stores the transfer state.
|
|
*/
|
|
static inline void SPI_SlaveTransferAbort(SPI_Type *base, spi_slave_handle_t *handle)
|
|
{
|
|
SPI_MasterTransferAbort(base, (spi_master_handle_t *)handle);
|
|
}
|
|
|
|
/*!
|
|
* @brief Interrupts a handler for the SPI slave.
|
|
*
|
|
* @param base SPI peripheral base address.
|
|
* @param handle pointer to spi_slave_handle_t structure which stores the transfer state
|
|
*/
|
|
static inline void SPI_SlaveTransferHandleIRQ(SPI_Type *base, spi_slave_handle_t *handle)
|
|
{
|
|
SPI_MasterTransferHandleIRQ(base, handle);
|
|
}
|
|
|
|
/*! @} */
|
|
|
|
#if defined(__cplusplus)
|
|
}
|
|
#endif
|
|
|
|
/*! @} */
|
|
|
|
#endif /* FSL_SPI_H_*/
|