57 lines
1.7 KiB
C
57 lines
1.7 KiB
C
//*****************************************************************************
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// boot_multicore_slave.c
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//
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// Provides simple functions to boot slave core in LPC55xx multicore system
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//
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// Version : 181106
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//
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//*****************************************************************************
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//
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// Copyright 2016-2019 NXP
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// All rights reserved.
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//
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// SPDX-License-Identifier: BSD-3-Clause
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//*****************************************************************************
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#if defined(__MULTICORE_MASTER)
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#include <stdint.h>
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//#define SYSCON_BASE ((uint32_t) 0x40000000)
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#define SYSCON_BASE ((uint32_t)0x50000000)
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#define CPBOOT (((volatile uint32_t *)(SYSCON_BASE + 0x804)))
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#define CPUCTRL (((volatile uint32_t *)(SYSCON_BASE + 0x800)))
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#define CPUCFG (((volatile uint32_t *)(SYSCON_BASE + 0xFD4)))
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#define CPUCTRL_KEY ((uint32_t)(0x0000C0C4 << 16))
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#define CORE1_CLK_ENA (1 << 3)
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#define CORE1_RESET_ENA (1 << 5)
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#define CORE1_ENABLE (1 << 2)
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extern uint8_t __core_m33slave_START__;
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void boot_multicore_slave(void)
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{
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volatile uint32_t *u32REG, u32Val;
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unsigned int *slavevectortable_ptr = (unsigned int *)&__core_m33slave_START__;
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// Enable CPU1 in SYSCON->CPUCFG
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*CPUCFG |= CORE1_ENABLE;
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// Set CPU1 boot address in SYSCON->CPBoot
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*CPBOOT = (uint32_t)slavevectortable_ptr;
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// Read SYSCON->CPUCTRL and set key value in bits 31:16
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u32REG = (uint32_t *)CPUCTRL;
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u32Val = *u32REG | CPUCTRL_KEY;
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// Enable slave clock and reset in SYSCON->CPUCTRL
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*u32REG = u32Val | CORE1_CLK_ENA | CORE1_RESET_ENA;
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// Clear slave reset in SYSCON->CPUCTRL
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*u32REG = (u32Val | CORE1_CLK_ENA) & (~CORE1_RESET_ENA);
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}
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#endif // defined (__MULTICORE_MASTER)
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