192 lines
6.5 KiB
C
192 lines
6.5 KiB
C
/*
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MMA8491Q_H_
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#define MMA8491Q_H_
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/**
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**
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** MMA8491Q Sensor Internal Registers
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*/
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enum
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{
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MMA8491Q_STATUS = 0x00,
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MMA8491Q_OUT_X_MSB = 0x01,
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MMA8491Q_OUT_X_LSB = 0x02,
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MMA8491Q_OUT_Y_MSB = 0x03,
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MMA8491Q_OUT_Y_LSB = 0x04,
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MMA8491Q_OUT_Z_MSB = 0x05,
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MMA8491Q_OUT_Z_LSB = 0x06,
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};
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#define MMA8491Q_I2C_ADDRESS (0x55) /* MMA8491Q I2C Slave Address. */
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#define MMA8491Q_T_RST_MIN (1U) /* Approx time between falling edge of EN and next rising edge of EN. */
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#define MMA8491Q_T_ON_TYPICAL (1U) /* Approx time taken for Data to become available after rising edge of EN. */
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/*--------------------------------
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** Register: STATUS
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** Enum: MMA8491Q_STATUS
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** --
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** Offset : 0x00 - Data-ready status information
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** ------------------------------*/
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typedef union
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{
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struct
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{
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uint8_t xdr : 1; /* - X-Axis new Data Available. */
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uint8_t ydr : 1; /* - Y-Axis new data available. */
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uint8_t zdr : 1; /* - Z-Axis new data available. */
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uint8_t zyxdr : 1; /* - X or Y or Z-Axis new data available. */
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uint8_t reserved : 4; /* - Reserved bits (Will always be set to zero). */
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} b;
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uint8_t w;
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} MMA8491Q_STATUS_t;
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/*
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** STATUS - Bit field mask definitions
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*/
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#define MMA8491Q_STATUS_XDR_MASK ((uint8_t)0x01)
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#define MMA8491Q_STATUS_XDR_SHIFT ((uint8_t)0)
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#define MMA8491Q_STATUS_YDR_MASK ((uint8_t)0x02)
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#define MMA8491Q_STATUS_YDR_SHIFT ((uint8_t)1)
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#define MMA8491Q_STATUS_ZDR_MASK ((uint8_t)0x04)
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#define MMA8491Q_STATUS_ZDR_SHIFT ((uint8_t)2)
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#define MMA8491Q_STATUS_ZYXDR_MASK ((uint8_t)0x08)
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#define MMA8491Q_STATUS_ZYXDR_SHIFT ((uint8_t)3)
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#define MMA8491Q_STATUS_RESERVED_MASK ((uint8_t)0xF0)
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#define MMA8491Q_STATUS_RESERVED_SHIFT ((uint8_t)4)
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/*
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** STATUS - Bit field value definitions
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*/
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#define MMA8491Q_STATUS_XDR_DRDY ((uint8_t)0x01) /* - Set to 1 whenever new X-axis data acquisition is */
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/* completed. XDR is cleared any time OUT_X_MSB register */
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/* is read. */
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#define MMA8491Q_STATUS_YDR_DRDY ((uint8_t)0x02) /* - Set to 1 whenever new Y-axis data acquisition is */
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/* completed. YDR is cleared any time OUT_Y_MSB register */
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/* is read. */
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#define MMA8491Q_STATUS_ZDR_DRDY ((uint8_t)0x04) /* - Set to 1 whenever new Z-axis data acquisition is */
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/* completed. ZDR is cleared any time OUT_Z_MSB register */
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/* is read. */
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#define MMA8491Q_STATUS_ZYXDR_DRDY ((uint8_t)0x08) /* - Signals that new acquisition for any of the enabled */
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/* channels is available. ZYXDR is cleared when the */
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/* high-bytes of the acceleration data (OUT_X_MSB, */
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/* OUT_Y_MSB, OUT_Z_MSB) of all channels are read. */
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#define MMA8491Q_STATUS_RESERVED_ZERO ((uint8_t)0x00) /* - Value of reserved field. */
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/*------------------------------*/
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/*--------------------------------
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** Register: OUT_X_MSB
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** Enum: MMA8491Q_OUT_X_MSB
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** --
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** Offset : 0x01 - Bits 8-15 of 14-bit X-Axis output sample data (expressed as 2's complement numbers).
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** ------------------------------*/
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typedef uint8_t MMA8491Q_OUT_X_MSB_t;
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/*--------------------------------
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** Register: OUT_X_LSB
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** Enum: MMA8491Q_OUT_X_LSB
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** --
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** Offset : 0x02 - Bits 0-7 of 14-bit X-Axis output sample data (expressed as 2's complement numbers).
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** ------------------------------*/
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typedef union
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{
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struct
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{
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uint8_t _reserved_ : 2;
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uint8_t out_x_lsb : 6; /* - OUT_X_LSB register bits 2-7. (Bit 0 and 1 will always be 0). */
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} b;
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uint8_t w;
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} MMA8491Q_OUT_X_LSB_t;
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/*
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** OUT_X_LSB - Bit field mask definitions
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*/
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#define MMA8491Q_OUT_X_LSB_OUT_X_LSB_MASK ((uint8_t)0xFC)
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#define MMA8491Q_OUT_X_LSB_OUT_X_LSB_SHIFT ((uint8_t)2)
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/*------------------------------*/
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/*--------------------------------
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** Register: OUT_Y_MSB
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** Enum: MMA8491Q_OUT_Y_MSB
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** --
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** Offset : 0x03 - Bits 8-15 of 14-bit Y-Axis output sample data (expressed as 2's complement numbers).
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** ------------------------------*/
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typedef uint8_t MMA8491Q_OUT_Y_MSB_t;
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/*--------------------------------
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** Register: OUT_Y_LSB
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** Enum: MMA8491Q_OUT_Y_LSB
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** --
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** Offset : 0x04 - Bits 0-7 of 14-bit Y-Axis output sample data (expressed as 2's complement numbers).
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** ------------------------------*/
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typedef union
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{
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struct
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{
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uint8_t _reserved_ : 2;
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uint8_t out_y_lsb : 6; /* - OUT_Y_LSB register bits 2-7. (Bit 0 and 1 will always be 0). */
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} b;
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uint8_t w;
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} MMA8491Q_OUT_Y_LSB_t;
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/*
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** OUT_Y_LSB - Bit field mask definitions
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*/
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#define MMA8491Q_OUT_Y_LSB_OUT_Y_LSB_MASK ((uint8_t)0xFC)
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#define MMA8491Q_OUT_Y_LSB_OUT_Y_LSB_SHIFT ((uint8_t)2)
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/*------------------------------*/
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/*--------------------------------
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** Register: OUT_Z_MSB
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** Enum: MMA8491Q_OUT_Z_MSB
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** --
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** Offset : 0x05 - Bits 8-15 of 14-bit Z-Axis output sample data (expressed as 2's complement numbers).
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** ------------------------------*/
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typedef uint8_t MMA8491Q_OUT_Z_MSB_t;
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/*--------------------------------
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** Register: OUT_Z_LSB
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** Enum: MMA8491Q_OUT_Z_LSB
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** --
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** Offset : 0x06 - Bits 0-7 of 14-bit Z-Axis output sample data (expressed as 2's complement numbers).
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** ------------------------------*/
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typedef union
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{
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struct
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{
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uint8_t _reserved_ : 2;
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uint8_t out_z_lsb : 6; /* - OUT_Z_LSB register bits 2-7. (Bit 0 and 1 will always be 0). */
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} b;
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uint8_t w;
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} MMA8491Q_OUT_Z_LSB_t;
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/*
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** OUT_Z_LSB - Bit field mask definitions
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*/
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#define MMA8491Q_OUT_Z_LSB_OUT_Z_LSB_MASK ((uint8_t)0xFC)
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#define MMA8491Q_OUT_Z_LSB_OUT_Z_LSB_SHIFT ((uint8_t)2)
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/*------------------------------*/
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#endif /* MMA8491Q_H_ */
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