185 lines
5.7 KiB
Plaintext
185 lines
5.7 KiB
Plaintext
/*
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* Copyright 2021 NXP.
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* Processors: LPC55S69JBD100_cm33_core0
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* LPC55S69JBD64_cm33_core0
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* LPC55S69JEV98_cm33_core0
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*/
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/******************************************************************************/
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/****************** LIBRARY *******************************************/
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/******************************************************************************/
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GROUP (
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"libcr_semihost_nf.a"
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"libcr_c.a"
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"libcr_eabihelpers.a"
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"libgcc.a"
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)
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/******************************************************************************/
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/****************** USER CONFIGURATION PART ***************************/
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/******************************************************************************/
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/* FLASH memory boundaries. */
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__ROM_start__ = 0x00000000;
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__ROM_end__ = 0x00071FFF;
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/* RAM memory boundaries. */
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__RAM_start__ = 0x20000000;
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__RAM_end__ = 0x200317FF;
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/* Sizes of objects in RAM. */
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__size_cstack__ = 0x0400; /* Stack size. */
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stack_test_block_size = 0x10; /* Safety stack test pattern. */
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ram_test_backup_size = 0x20; /* Safety RAM test backup size. */
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wd_test_backup_size = 0x20; /* Safety WDOG test data size. */
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/* Sizes of objects in FLASH. */
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__vector_table_size__ = 0x130;
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__PC_test_size = 0x20;
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__size_flash_crc__ = 0x10;
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__flash_cfg_size = 0x10;
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__VECTOR_TABLE = __ROM_start__;
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__size_heap__ = 0x40; /* 2x heap and heap2stackfill */
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/******************************************************************************/
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/****************** SYMBOLS *******************************************/
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/******************************************************************************/
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/* Assemble RAM addresses. */
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m_ram_test_backup = (__RAM_end__ - ram_test_backup_size + 0x1);
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m_wd_test_backup = (m_ram_test_backup - wd_test_backup_size);
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m_pc_test_flag = (m_wd_test_backup - 0x4);
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m_safety_error_code = (m_pc_test_flag - 0x4);
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m_stack_test_p_4 = (m_safety_error_code - 0x4);
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m_stack_test_p_3 = (m_stack_test_p_4 - stack_test_block_size +0x4);
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__BOOT_STACK_ADDRESS = (m_stack_test_p_3 - 0x4);
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m_stack_test_p_2 = (__BOOT_STACK_ADDRESS - __size_cstack__);
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m_stack_test_p_1 = (m_stack_test_p_2 - stack_test_block_size + 0x4);
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m_safety_ram_start = __RAM_start__;
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/* Assemble FLASH addresses. */
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m_intvec_table_start = (__ROM_start__);
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m_intvec_table_end = (m_intvec_table_start + __vector_table_size__ - 0x1);
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__PC_test_start__ = (m_intvec_table_end + 0x1);
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__PC_test_end__ = (__PC_test_start__ + __PC_test_size - 0x1);
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m_flash_start = (__PC_test_end__ + 0x1);
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m_fs_flash_crc_end = (__ROM_end__);
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m_fs_flash_crc_start = (m_fs_flash_crc_end - __size_flash_crc__ + 0x1);
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m_flash_end = (m_fs_flash_crc_start - 0x1);
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MEMORY
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{
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/* Define each memory region */
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MEM_FLASH (rx) : ORIGIN = __ROM_start__, LENGTH = (__ROM_end__ - __ROM_start__ + 1)
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MEM_RAM (rwx) : ORIGIN = __RAM_start__, LENGTH = (__RAM_end__ - __RAM_start__ + 1)
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}
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/******************************************************************************/
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/****************** PLACING *******************************************/
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/******************************************************************************/
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ENTRY(ResetISR)
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SECTIONS
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{
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/* Safety-related code and read-only data section. */
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.SEC_FS_ROM : ALIGN(4)
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{
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FILL(0xff)
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/* The interrupt vector table. */
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. = m_intvec_table_start;
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KEEP(*(.intvec*))
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/* PC test object. */
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. = __PC_test_start__;
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KEEP(*iec60730b_cm33_pc_object.o(.text*))
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/* Safety-related FLASH code and RO data. */
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. = m_flash_start;
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*(.rodata*)
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. = . + 1;
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. = ALIGN(4);
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} >MEM_FLASH
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/* The safety-related RAM. */
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.SEC_FS_RAM m_safety_ram_start : AT (ADDR(.SEC_FS_ROM) + SIZEOF(.SEC_FS_ROM))
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{
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m_sec_fs_ram_load_start = LOADADDR(.SEC_FS_RAM);
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m_sec_fs_ram_start = .;
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*(.safety_ram*)
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*main.o(.data*)
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*safety_test_items.o(.data*)
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. = . + 1;
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. = ALIGN(4);
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m_sec_fs_ram_load_end = LOADADDR (.SEC_FS_RAM) + SIZEOF(.SEC_FS_RAM);
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m_sec_fs_ram_end = .;
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/* The end of safety-related FLASH memory. */
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m_safety_flash_end = LOADADDR (.SEC_FS_RAM) + SIZEOF(.SEC_FS_RAM);
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} >MEM_RAM
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/* The non-safety RW data. */
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.SEC_RWRAM m_sec_fs_ram_end : AT (m_safety_flash_end)
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{
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m_sec_rwram_load_start = LOADADDR(.SEC_RWRAM);
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m_sec_rwram_start = .;
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*(.data*)
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. = . + 1;
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. = ALIGN(4);
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m_sec_rwram_load_end = LOADADDR(.SEC_RWRAM) + SIZEOF(.SEC_RWRAM);
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m_sec_rwram_end = .;
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} >MEM_RAM
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/* The non-safety code and RO data. */
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.SEC_ROM m_sec_rwram_load_end : ALIGN(4)
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{
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FILL(0xff)
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*(.text*)
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KEEP(*(.rodata .rodata.* .constdata .constdata.*))
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. = . + 1;
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. = ALIGN(4);
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} >MEM_FLASH
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/* The safety FLASH CRC. */
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.SEC_CRC m_fs_flash_crc_start : ALIGN(4)
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{
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FILL(0xff)
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KEEP(*(.flshcrc*))
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} >MEM_FLASH
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/* Stack memory. */
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stack (__BOOT_STACK_ADDRESS - __size_cstack__) : ALIGN(4)
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{
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. = ALIGN(4);
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} > MEM_RAM
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/* The zero-initialized RW data. */
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.SEC_BSS m_sec_rwram_end : ALIGN(4)
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{
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m_sec_bss_start = .;
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*(.bss*)
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*(COMMON)
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. = . + 1;
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. = ALIGN(4);
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m_sec_bss_end = .;
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} >MEM_RAM
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/* Reserve and place Heap within memory map */
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_HeapSize = __size_heap__;
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.heap : ALIGN(4)
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{
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_pvHeapStart = .;
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. += _HeapSize;
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. = ALIGN(4);
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_pvHeapLimit = .;
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} > MEM_RAM
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}
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