136 lines
4.3 KiB
C
136 lines
4.3 KiB
C
/*
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* Copyright 2021 NXP.
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _SAFETY_CONFIG_H_
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#define _SAFETY_CONFIG_H_
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#include "LPC55S69_cm33_core0.h"
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#include "iec60730b.h"
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#include "iec60730b_core.h"
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#include "safety_test_items.h"
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#include "project_setup_lpcxpresso55s69.h"
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#include "safety_cm33_lpc.h"
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#include "pin_mux.h"
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#ifndef NULL
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#ifdef __cplusplus
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#define NULL (0)
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#else
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#define NULL ((void *)0)
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#endif
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#endif
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/* This macro enables infinity while loop in SafetyErrorHandling() function */
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#define SAFETY_ERROR_ACTION 1
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/* TEST SWITCHES - for debugging it is better to turn the flash test and watchdog OFF */
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#define ADC_TEST_ENABLED 0
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#define CLOCK_TEST_ENABLED 1
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#define DIO_TEST_ENABLED 1
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#define FLASH_TEST_ENABLED 1
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#define RAM_TEST_ENABLED 1
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#define PC_TEST_ENABLED 1
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#define WATCHDOG_ENABLED 0
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#define FMSTR_SERIAL_ENABLE 1
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/* CLOCK test */
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#define USE_WKT 0 /*USE CTIMER = 0 USE WKT = 1 */
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#define CLOCK_ERROR_HANDLING 1
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#define REF_TIMER_USED CTIMER0
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#define REF_TIMER_CLOCK_FREQUENCY 96e06
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#define SYSTICK_RELOAD_VALUE 150000
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#define ISR_FREQUENCY 1000 /* Hz */
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#define CLOCK_TEST_TOLERANCE 20 /* % */
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/********* Watchdog *********/
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#define WDOG_REF_TIMER_BASE CTIMER0
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#define RESET_DETECT_REGISTER &(PMC->AOREG1)
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#define RESET_DETECT_MASK 0x10U
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#define REG_WIDE FS_WDOG_SRS_WIDE_32b
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#define Watchdog_refresh \
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WWDT->FEED = 0xAA; \
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WWDT->FEED = 0x55
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#define USED_WDOG WWDT
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#define ENDLESS_LOOP_ENABLE 1 /* set 1 or 0 */
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#define WATCHDOG_RESETS_LIMIT 1000
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#define WATCHDOG_REFRESH_RATIO 1
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#define WATCHDOG_TIMEOUT_VALUE 500 /* 2ms refresh period (500 / 250kHz) */
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#define WD_REF_TIMER_CLOCK_FREQUENCY 96e06
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#define WATCHDOG_CLOCK 250000
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#define WD_TEST_TOLERANCE 40 /* % */
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#define WD_RUN_TEST_CONDITION \
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(PMC_AOREG1_POR_MASK | PMC_AOREG1_PADRESET_MASK | PMC_AOREG1_BODRESET_MASK | PMC_AOREG1_SYSTEMRESET_MASK | \
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PMC_AOREG1_DPDRESET_WAKEUPIO_MASK | PMC_AOREG1_DPDRESET_RTC_MASK | PMC_AOREG1_DPDRESET_OSTIMER_MASK)
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#define WD_CHECK_TEST_CONDITION PMC_AOREG1_WDTRESET_MASK
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/********* Watchdog END *********/
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/* GPIO macros */
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#define PIN_DIRECTION_IN 0
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#define PIN_DIRECTION_OUT 1
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#define PIN_PULL_DISABLE 0
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#define PIN_PULL_DOWN 1
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#define PIN_PULL_UP 2
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#define LOGICAL_ONE 1
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#define LOGICAL_ZERO 0
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/* Dio port settings */
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#define DIO_EXPECTED_VALUE 0
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#define DIO_WAIT_CYCLE 75
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#define DIO_BACKUP_ENABLE 1
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#define DIO_BACKUP_DISABLE 0
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#define DIO_BACKUP DIO_BACKUP_ENABLE
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#define DIO_SHORT_TO_GND_TEST 1
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#define DIO_SHORT_TO_VDD_TEST 0
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/* Program Counter TEST */
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#define PC_TEST_PATTERN 0x20001000 /* test address for Program counter test (in RAM region) */
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/* UART macros */
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#define UART_BAUD_RATE 9600
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/* FLASH TEST MACROS */
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#define HW_FLASH_TEST 1 /* Use HW = 1 SW = 0 flash TEST*/
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#define FLASH_TEST_BLOCK_SIZE 0x20
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#define CRC_BASE CRC_ENGINE_BASE
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#define FLASH_TEST_CONDITION_SEED 0x0000 /* 0xFFFFFFFF CRC32, 0x0000 CRC16 */
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#if defined(__GNUC__) || defined(__ARMCC_VERSION)
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/*! @note The following flash test settings must be in consistence with
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"User AFTER BUILD = srec_cat!*/
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/* The CRC16 of safety-related FLASH memory. */
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#define FS_CFG_FLASH_TST_CRC (0xFFFFU)
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#endif
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#define RAM_TEST_BLOCK_SIZE 0x4 /* size of block for runtime testing */
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#if defined(__IAR_SYSTEMS_ICC__) || (defined(__GNUC__) && (__ARMCC_VERSION >= 6010050)) /* IAR + KEIL */
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#define RAM_TEST_BACKUP_SIZE 0x20 /* must fit with the setup from linker configuration file */
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#define STACK_TEST_BLOCK_SIZE 0x10 /* must fit with the setup from linker configuration file */
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#endif
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#define STACK_TEST_PATTERN 0x77777777
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#define TESTED_ADC ADC0 /*which ADC is use for AIO test*/
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#define ADC_RESOLUTION 16
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#define ADC_REFERENCE 3.3
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#define ADC_BANDGAP_LEVEL 1.65 /* depends on power supply configuration */
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#define ADC_DEVIATION_PERCENT 20
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#endif /* _SAFETY_CONFIG_H_ */
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