/*
 * Copyright 2021 NXP.
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#ifndef _SAFETY_CONFIG_H_
#define _SAFETY_CONFIG_H_

#include "LPC804.h"
#include "iec60730b.h"
#include "iec60730b_core.h"
#include "safety_test_items.h"
#include "project_setup_lpcxpresso804.h"
#include "safety_cm0_lpc.h"

#ifndef NULL
#ifdef __cplusplus
#define NULL (0)
#else
#define NULL ((void *)0)
#endif
#endif


/*******************************************************************************
 * Definitions
 ******************************************************************************/
/* This macro enables infinity while loop in SafetyErrorHandling() function */
#define SAFETY_ERROR_ACTION 1

/* TEST SWITCHES - for debugging it is better to turn the flash test and watchdog OFF */
#define ADC_TEST_ENABLED    0
#define CLOCK_TEST_ENABLED  1
#define DIO_TEST_ENABLED    1
#define FLASH_TEST_ENABLED  1
#define RAM_TEST_ENABLED    1
#define PC_TEST_ENABLED     1
#define WATCHDOG_ENABLED    0
#define FMSTR_SERIAL_ENABLE 0

/* CLOCK test */
#define REF_TIMER_USED            WKT
#define REF_TIMER_CLOCK_FREQUENCY 1e06
#define SYSTICK_RELOAD_VALUE      15000
#define ISR_FREQUENCY             1000  /* Hz */
#define START_VALUE               10000 /* Start value for WKT timer, this timer decreasing */
#define CLOCK_TEST_TOLERANCE      100   /* % */

/*WDOG test */
#define WDOG_REF_TIMER_BASE   CTIMER0
#define USED_WDOG             WWDT
#define RESET_DETECT_REGISTER &(SYSCON->SYSRSTSTAT) /* Address of detect register */
#define RESET_DETECT_MASK     SYSCON_SYSRSTSTAT_WDT_MASK
#define REFRESH_INDEX
#define CLEAR_FLAG 0
#define REG_WIDE   FS_WDOG_SRS_WIDE_32b

#define Watchdog_refresh \
    WWDT->FEED = 0xAA;   \
    WWDT->FEED = 0x55;

#define ENDLESS_LOOP_ENABLE          1 /* set 1 or 0 */
#define WATCHDOG_RESETS_LIMIT        1000
#define WATCHDOG_REFRESH_RATIO       1
#define WATCHDOG_TIMEOUT_VALUE       12500 /* Wdog TICK number for  */
#define WD_REF_TIMER_CLOCK_FREQUENCY 15e06
#define WATCHDOG_CLOCK               250e3
#define WD_TEST_TOLERANCE            25 /* % */

/* GPIO macros */
#define PIN_DIRECTION_IN  0
#define PIN_DIRECTION_OUT 1

#define PIN_PULL_DISABLE 0
#define PIN_PULL_DOWN    1
#define PIN_PULL_UP      2

#define LOGICAL_ONE  1
#define LOGICAL_ZERO 0

/* DIO test */
#define DIO_WAIT_CYCLE 75

#define DIO_BACKUP_ENABLE  1
#define DIO_BACKUP_DISABLE 0
#define DIO_BACKUP         DIO_BACKUP_ENABLE

#define DIO_SHORT_TO_GND_TEST 1
#define DIO_SHORT_TO_VDD_TEST 0

/* Program Counter TEST */
#define PC_TEST_PATTERN 0x10000A00 /* test address for Program counter test (in RAM region) */

/* UART macros */
#define UART_BAUD_RATE 9600

/* FLASH test */
#define HW_FLASH_TEST             1 /* HW=1, SW=0 */
#define FLASH_TEST_BLOCK_SIZE     0x20
#define FLASH_TEST_CONDITION_SEED 0x0000

#if defined(__GNUC__) || defined(__ARMCC_VERSION)
/*! @note The following flash test settings must be in consistence with
          "User AFTER BUILD = srec_cat!*/
/* The CRC16 of safety-related FALSH memory. */
#define FS_CFG_FLASH_TST_CRC (0xFFFFU)
#endif

/* RAM test */
#define RAM_TEST_BLOCK_SIZE 0x4 /* size of block for runtime testing */

#if defined(__IAR_SYSTEMS_ICC__) || (defined(__GNUC__) && (__ARMCC_VERSION >= 6010050)) /* IAR + KEIL */
#define RAM_TEST_BACKUP_SIZE  0x20 /* must fit with the setup from linker configuration file */
#define STACK_TEST_BLOCK_SIZE 0x10 /* must fit with the setup from linker configuration file */
#endif

/* STACK test */
#define STACK_TEST_PATTERN 0x77777777

/* ADC test */
#define TESTED_ADC              ADC /*which ADC is use for AIO test*/
#define ADC_RESOLUTION          12
#define ADC_REFERENCE           3.3
#define ADC_BANDGAP_LEVEL       1.65 /* depends on power supply configuration */
#define ADC_DEVIATION_PERCENT   25

#endif /* _SAFETY_CONFIG_H_ */
