diff --git a/CMSIS/CMSIS_v3.yml b/CMSIS/CMSIS_v3.yml new file mode 100644 index 0000000..41284b7 --- /dev/null +++ b/CMSIS/CMSIS_v3.yml @@ -0,0 +1,2188 @@ +--- +# yaml-language-server: $schema=../../schema/component_set_schema.json + +## CMSIS Core component +CMSIS_Include_core_cm: + section-type: component + contents: + repo_base_path: CMSIS/Core/Include + project_base_path: CMSIS + cc-include: + - repo_relative_path: "./" + files: + - source: cmsis_armcc.h + compilers: armcc + - source: cmsis_armclang.h + compilers: armclang + - source: cmsis_armclang_ltm.h + compilers: armclang + - source: cmsis_compiler.h + compilers: armclang armcc gcc iar + - source: cmsis_gcc.h + compilers: gcc + - source: cmsis_iccarm.h + compilers: iar + - source: cmsis_version.h + compilers: armclang armcc gcc iar + - source: core_cm0.h + cores: cm0 + - source: core_cm0plus.h + cores: cm0p + - source: core_cm23.h + cores: cm23 + - source: core_cm3.h + cores: cm3 + - source: core_cm33.h + cores: cm33 cm33f + - source: core_cm4.h + cores: cm4 cm4f + - source: core_cm7.h + cores: cm7 cm7f + - source: cachel1_armv7.h + cores: cm7 cm7f + - source: mpu_armv7.h + cores: cm0 cm0p cm3 cm4 cm4f cm7 cm7f + - source: mpu_armv8.h + cores: cm23 cm33 cm33f + - source: tz_context.h + trustzone: TZ + cores: cm23 cm33 cm33f + section_info: + version: 5.5.0 + type: CMSIS_Include + full_name: CMSIS Include For Cortex-M, ARMv8-M, ARMv8.1-M + description: CMSIS-CORE for Cortex-M, ARMv8-M, ARMv8.1-M + display_name: CMSIS_Include_CM + taxonomy: + belong_to: CMSIS + cgroup: CORE + belong_to: set.CMSIS + +CMSIS_Include_core_ca7: + section-type: component + contents: + repo_base_path: CMSIS/Core_A + project_base_path: CMSIS + cc-include: + - repo_relative_path: "./" + files: + - source: Include/cmsis_armcc.h + compilers: armcc + - source: Include/cmsis_armclang.h + compilers: armclang + - source: Include/cmsis_gcc.h + compilers: gcc + - source: Include/cmsis_compiler.h + compilers: armclang armcc gcc iar + - source: Include/cmsis_cp15.h + compilers: armclang armcc gcc iar + - source: Include/cmsis_iccarm.h + compilers: iar + - source: Include/core_ca.h + cores: ca7 + - source: Include/irq_ctrl.h + compilers: armclang armcc gcc iar + - source: Source/irq_ctrl_gic.c + compilers: armclang armcc gcc iar + dependency: + allOf: + - core: + - ca7 + section_info: + version: 1.2.1 + type: CMSIS_Include + full_name: CMSIS Include For Cortex-A + description: CMSIS-CORE for Cortex-A + display_name: CMSIS_Include_CA7 + taxonomy: + belong_to: CMSIS + cgroup: CORE + belong_to: set.CMSIS + +# Only KEX needs such container to make sure that all files are packed. +container.CMSIS_all_files: + section-type: container + contents: + repo_base_path: CMSIS + package_base_path: CMSIS + files: + - source: Driver/** + - source: "*.*" + - source: DSP/Source/** + section_info: + product: + cmsis_pack: + supported: false + belong_to: set.CMSIS + +CMSIS_DSP_Include: + section-type: component + contents: + repo_base_path: CMSIS/DSP + project_base_path: CMSIS/DSP + cc-include: + - repo_relative_path: Include + - repo_relative_path: PrivateInclude + files: + - source: README.md + hidden: true + exclude: true + - source: Include/arm_common_tables.h + - source: Include/arm_const_structs.h + - source: Include/arm_math.h + - source: Include/arm_common_tables_f16.h + - source: Include/arm_const_structs_f16.h + - source: Include/arm_helium_utils.h + - source: Include/arm_math_f16.h + - source: Include/arm_math_memory.h + - source: Include/arm_math_types.h + - source: Include/arm_math_types_f16.h + - source: Include/arm_mve_tables.h + - source: Include/arm_mve_tables_f16.h + - source: Include/arm_vec_math.h + - source: Include/arm_vec_math_f16.h + - source: Include/dsp/basic_math_functions.h + - source: Include/dsp/basic_math_functions_f16.h + - source: Include/dsp/bayes_functions.h + - source: Include/dsp/bayes_functions_f16.h + - source: Include/dsp/complex_math_functions.h + - source: Include/dsp/complex_math_functions_f16.h + - source: Include/dsp/controller_functions.h + - source: Include/dsp/controller_functions_f16.h + - source: Include/dsp/distance_functions.h + - source: Include/dsp/distance_functions_f16.h + - source: Include/dsp/fast_math_functions.h + - source: Include/dsp/fast_math_functions_f16.h + - source: Include/dsp/filtering_functions.h + - source: Include/dsp/filtering_functions_f16.h + - source: Include/dsp/interpolation_functions.h + - source: Include/dsp/interpolation_functions_f16.h + - source: Include/dsp/matrix_functions.h + - source: Include/dsp/matrix_functions_f16.h + - source: Include/dsp/none.h + - source: Include/dsp/quaternion_math_functions.h + - source: Include/dsp/statistics_functions.h + - source: Include/dsp/statistics_functions_f16.h + - source: Include/dsp/support_functions.h + - source: Include/dsp/support_functions_f16.h + - source: Include/dsp/svm_defines.h + - source: Include/dsp/svm_functions.h + - source: Include/dsp/svm_functions_f16.h + - source: Include/dsp/transform_functions.h + - source: Include/dsp/transform_functions_f16.h + - source: Include/dsp/utils.h + - source: PrivateInclude/arm_sorting.h + - source: PrivateInclude/arm_vec_fft.h + - source: PrivateInclude/arm_vec_filtering.h + section_info: + version: 1.9.0 + type: CMSIS_driver + full_name: CMSIS DSP Library Header + description: CMSIS-DSP Library Header + display_name: CMSIS_DSP_Library_Header + taxonomy: + belong_to: CMSIS + cgroup: DSP + csub: include + product: + cmsis_pack: + supported: false + belong_to: set.CMSIS_DSP_Lib + +CMSIS_DSP_Source: + section-type: component + contents: + configuration: + cc-define: + DISABLEFLOAT16: + repo_base_path: CMSIS/DSP + project_base_path: CMSIS/DSP + cc-include: + - repo_relative_path: Include + - repo_relative_path: PrivateInclude + - repo_relative_path: Source/DistanceFunctions + files: + - source: README.md + hidden: true + exclude: true + - source: Include/arm_common_tables.h + - source: Include/arm_const_structs.h + - source: Include/arm_math.h + - source: Include/arm_common_tables_f16.h + - source: Include/arm_const_structs_f16.h + - source: Include/arm_helium_utils.h + - source: Include/arm_math_f16.h + - source: Include/arm_math_memory.h + - source: Include/arm_math_types.h + - source: Include/arm_math_types_f16.h + - source: Include/arm_mve_tables.h + - source: Include/arm_mve_tables_f16.h + - source: Include/arm_vec_math.h + - source: Include/arm_vec_math_f16.h + - source: Include/dsp/basic_math_functions.h + - source: Include/dsp/basic_math_functions_f16.h + - source: Include/dsp/bayes_functions.h + - source: Include/dsp/bayes_functions_f16.h + - source: Include/dsp/complex_math_functions.h + - source: Include/dsp/complex_math_functions_f16.h + - source: Include/dsp/controller_functions.h + - source: Include/dsp/controller_functions_f16.h + - source: Include/dsp/distance_functions.h + - source: Include/dsp/distance_functions_f16.h + - source: Include/dsp/fast_math_functions.h + - source: Include/dsp/fast_math_functions_f16.h + - source: Include/dsp/filtering_functions.h + - source: Include/dsp/filtering_functions_f16.h + - source: Include/dsp/interpolation_functions.h + - source: Include/dsp/interpolation_functions_f16.h + - source: Include/dsp/matrix_functions.h + - source: Include/dsp/matrix_functions_f16.h + - source: Include/dsp/none.h + - source: Include/dsp/quaternion_math_functions.h + - source: Include/dsp/statistics_functions.h + - source: Include/dsp/statistics_functions_f16.h + - source: Include/dsp/support_functions.h + - source: Include/dsp/support_functions_f16.h + - source: Include/dsp/svm_defines.h + - source: Include/dsp/svm_functions.h + - source: Include/dsp/svm_functions_f16.h + - source: Include/dsp/transform_functions.h + - source: Include/dsp/transform_functions_f16.h + - source: Include/dsp/utils.h + - source: PrivateInclude/arm_sorting.h + - source: PrivateInclude/arm_vec_fft.h + - source: PrivateInclude/arm_vec_filtering.h + + - source: Source/BasicMathFunctions/BasicMathFunctions.c + - source: Source/BasicMathFunctions/arm_abs_f32.c + exclude: true + - source: Source/BasicMathFunctions/arm_abs_q15.c + exclude: true + - source: Source/BasicMathFunctions/arm_abs_q31.c + exclude: true + - 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source: Source/TransformFunctions/arm_rfft_init_q31.c + exclude: true + - source: Source/TransformFunctions/arm_rfft_q15.c + exclude: true + - source: Source/TransformFunctions/arm_rfft_q31.c + exclude: true + + - source: Source/TransformFunctions/TransformFunctionsF16.c + - source: Source/TransformFunctions/arm_bitreversal_f16.c + exclude: true + - source: Source/TransformFunctions/arm_cfft_f16.c + exclude: true + - source: Source/TransformFunctions/arm_cfft_init_f16.c + exclude: true + - source: Source/TransformFunctions/arm_cfft_radix2_f16.c + exclude: true + - source: Source/TransformFunctions/arm_cfft_radix2_init_f16.c + exclude: true + - source: Source/TransformFunctions/arm_cfft_radix4_f16.c + exclude: true + - source: Source/TransformFunctions/arm_cfft_radix4_init_f16.c + exclude: true + - source: Source/TransformFunctions/arm_cfft_radix8_f16.c + exclude: true + - source: Source/TransformFunctions/arm_rfft_fast_f16.c + exclude: true + - source: Source/TransformFunctions/arm_rfft_fast_init_f16.c + exclude: true + section_info: + version: 1.9.0 + type: CMSIS_driver + full_name: CMSIS DSP Library Source + description: CMSIS-DSP Library + display_name: CMSIS_DSP_Library_Source + taxonomy: + belong_to: CMSIS + cgroup: DSP + csub: source + product: + cmsis_pack: + supported: false + belong_to: set.CMSIS_DSP_Lib + +CMSIS_NN_Source: + section-type: component + contents: + repo_base_path: CMSIS/NN + project_base_path: CMSIS/NN + cc-include: + - repo_relative_path: Include + files: + - source: README.md + hidden: true + exclude: true + - source: Include/arm_nn_tables.h + - source: Include/arm_nn_types.h + - source: Include/arm_nnfunctions.h + - source: Include/arm_nnsupportfunctions.h + - source: Source/ActivationFunctions/arm_nn_activations_q15.c + - source: Source/ActivationFunctions/arm_nn_activations_q7.c + - source: Source/ActivationFunctions/arm_relu6_s8.c + - source: Source/ActivationFunctions/arm_relu_q15.c + - source: Source/ActivationFunctions/arm_relu_q7.c + - source: Source/BasicMathFunctions/arm_elementwise_add_s8.c + - source: Source/BasicMathFunctions/arm_elementwise_mul_s8.c + - source: Source/ConcatenationFunctions/arm_concatenation_s8_w.c + - source: Source/ConcatenationFunctions/arm_concatenation_s8_x.c + - source: Source/ConcatenationFunctions/arm_concatenation_s8_y.c + - source: Source/ConcatenationFunctions/arm_concatenation_s8_z.c + - source: Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c + - source: Source/ConvolutionFunctions/arm_convolve_1x1_s8_fast.c + - source: Source/ConvolutionFunctions/arm_convolve_1_x_n_s8.c + - source: Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.c + - source: Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.c + - source: Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast_nonsquare.c + - source: Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c + - source: Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.c + - source: Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c + - source: Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.c + - source: Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.c + - source: Source/ConvolutionFunctions/arm_convolve_s8.c + - source: Source/ConvolutionFunctions/arm_convolve_wrapper_s8.c + - source: Source/ConvolutionFunctions/arm_depthwise_conv_3x3_s8.c + - source: Source/ConvolutionFunctions/arm_depthwise_conv_s8.c + - source: Source/ConvolutionFunctions/arm_depthwise_conv_s8_opt.c + - source: Source/ConvolutionFunctions/arm_depthwise_conv_u8_basic_ver1.c + - source: Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s8.c + - source: Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.c + - source: Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c + - source: Source/ConvolutionFunctions/arm_nn_depthwise_conv_s8_core.c + - source: Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c + - source: Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c + - source: Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_s8_s16.c + - source: Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_s8_s16_reordered.c + - source: Source/ConvolutionFunctions/arm_nn_mat_mult_s8.c + - source: Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c + - source: Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c + - source: Source/FullyConnectedFunctions/arm_fully_connected_q15.c + - source: Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c + - source: Source/FullyConnectedFunctions/arm_fully_connected_q7.c + - source: Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c + - source: Source/FullyConnectedFunctions/arm_fully_connected_s8.c + - source: Source/NNSupportFunctions/arm_nntables.c + - source: Source/NNSupportFunctions/arm_nn_accumulate_q7_to_q15.c + - source: Source/NNSupportFunctions/arm_nn_add_q7.c + - source: Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_padded_s8.c + - source: Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s8.c + - source: Source/NNSupportFunctions/arm_nn_mat_mult_nt_t_s8.c + - source: Source/NNSupportFunctions/arm_nn_mat_mul_core_1x_s8.c + - source: Source/NNSupportFunctions/arm_nn_mat_mul_core_4x_s8.c + - source: Source/NNSupportFunctions/arm_nn_mult_q15.c + - source: Source/NNSupportFunctions/arm_nn_mult_q7.c + - source: Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s8.c + - source: Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_svdf_s8.c + - source: Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c + - source: Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.c + - source: Source/NNSupportFunctions/arm_q7_to_q15_reordered_with_offset.c + - source: Source/NNSupportFunctions/arm_q7_to_q15_with_offset.c + - source: Source/PoolingFunctions/arm_avgpool_s8.c + - source: Source/PoolingFunctions/arm_max_pool_s8.c + - source: Source/PoolingFunctions/arm_pool_q7_HWC.c + - source: Source/ReshapeFunctions/arm_reshape_s8.c + - source: Source/SoftmaxFunctions/arm_softmax_q15.c + - source: Source/SoftmaxFunctions/arm_softmax_q7.c + - source: Source/SoftmaxFunctions/arm_softmax_s8.c + - source: Source/SoftmaxFunctions/arm_softmax_u8.c + - source: Source/SoftmaxFunctions/arm_softmax_with_batch_q7.c + - source: Source/SVDFunctions/arm_svdf_s8.c + section_info: + version: 3.0.0 + type: CMSIS_driver + full_name: CMSIS NN Library Source + description: CMSIS-NN Library + display_name: CMSIS_NN_Library_Source + taxonomy: + belong_to: CMSIS + cgroup: NN + cvariant: Source + product: + cmsis_pack: + supported: false + belong_to: set.CMSIS_DSP_Lib + dependency: + allOf: + - CMSIS_DSP_Source + +## CMSIS Driver Custom components +# All CMSIS Driver components in ARM.CMSIS.pdsc have template file. In SDK yml data record, we don't use +# thus don't add them. For example, CMSIS Driver USART in pdsc have Driver_USART.h and Driver_USART.c(a template file), +# in SDK yml data record, it just has Driver_USART.h. + +# SDK yml data record just abstracts it into an individual component. It is not allowed to directly require it +# in any component or application. You should require end terminal component like CMSIS.Driver_Include.USART. + +CMSIS_Driver_Include.USART: + section-type: component + contents: + repo_base_path: CMSIS/Driver + project_base_path: CMSIS_driver + cc-include: + - repo_relative_path: "Include" + files: + - source: Include/Driver_USART.h + - source: DriverTemplates/Driver_USART.c + template: true + - source: Include/Driver_Common.h + section_info: + version: 2.4.0 + type: CMSIS_driver + user_visible: never + full_name: CMSIS Driver USART + description: "Access to #include Driver_USART.h file for custom implementation" + display_name: CMSIS_Driver_USART + product: + cmsis_pack: + api: true + taxonomy: + belong_to: CMSIS_DRIVER + cgroup: USART + belong_to: set.CMSIS + +CMSIS_Driver_Include.CAN: + section-type: component + contents: + repo_base_path: CMSIS/Driver + project_base_path: CMSIS_driver + cc-include: + - repo_relative_path: "Include" + files: + - source: Include/Driver_CAN.h + - source: DriverTemplates/Driver_CAN.c + template: true + - source: Include/Driver_Common.h + section_info: + version: 1.3.0 + type: CMSIS_driver + user_visible: never + full_name: CMSIS Driver CAN + description: "Access to #include Driver_CAN.h file for custom implementation" + display_name: CMSIS_Driver_CAN + product: + cmsis_pack: + api: true + taxonomy: + belong_to: CMSIS_DRIVER + cgroup: CAN + belong_to: set.CMSIS + +# Mismatch +# In ARM.CMSIS.pdsc, the Ethernet component actually contains both Driver_ETH_MAC.h and Driver_ETH_PHY.h which is not a practical +# way we do the work. In SDK yml data record, we usually split the component into common and functionality part. +# CMSIS.Driver_Include.Ethernet is the common part for Ethernet component set. +CMSIS_Driver_Include.Ethernet: + section-type: component + contents: + repo_base_path: CMSIS/Driver + project_base_path: CMSIS_driver + cc-include: + - repo_relative_path: "Include" + files: + - source: Include/Driver_Common.h + - source: Include/Driver_ETH.h + - source: Include/Driver_ETH_MAC.h + - source: Include/Driver_ETH_PHY.h + - source: DriverTemplates/Driver_ETH_MAC.c + template: true + - source: DriverTemplates/Driver_ETH_PHY.c + template: true + section_info: + version: 2.2.0 + type: CMSIS_driver + user_visible: never + full_name: CMSIS Driver Ethernet Common + description: "Access to #include Driver_ETH.h file for custom implementation" + display_name: CMSIS_Driver_Ethernet_Common + product: + cmsis_pack: + api: true + taxonomy: + belong_to: CMSIS_DRIVER + cgroup: Ethernet + belong_to: set.CMSIS + +CMSIS_Driver_Include.Ethernet_MAC: + section-type: component + contents: + repo_base_path: CMSIS/Driver + project_base_path: CMSIS_driver + cc-include: + - repo_relative_path: "Include" + files: + - source: Include/Driver_ETH.h + - source: Include/Driver_Common.h + - source: Include/Driver_ETH_MAC.h + - source: DriverTemplates/Driver_ETH_MAC.c + template: true + section_info: + version: 2.2.0 + type: CMSIS_driver + user_visible: never + full_name: CMSIS Driver Ethernet MAC + description: "Access to #include Driver_ETH_MAC.h file for custom implementation" + display_name: CMSIS_Driver_Ethernet_MAC + product: + cmsis_pack: + api: true + taxonomy: + belong_to: CMSIS_DRIVER + cgroup: Ethernet MAC + belong_to: set.CMSIS + +CMSIS_Driver_Include.Ethernet_PHY: + section-type: component + contents: + repo_base_path: CMSIS/Driver + project_base_path: CMSIS_driver + cc-include: + - repo_relative_path: "Include" + files: + - source: Include/Driver_ETH.h + - source: Include/Driver_ETH_PHY.h + - source: DriverTemplates/Driver_ETH_PHY.c + template: true + - source: Include/Driver_Common.h + section_info: + version: 2.2.0 + type: CMSIS_driver + user_visible: never + full_name: CMSIS Driver Ethernet PHY + description: "Access to #include Driver_ETH_PHY.h file for custom implementation" + display_name: CMSIS_Driver_Ethernet_PHY + product: + cmsis_pack: + api: true + taxonomy: + belong_to: CMSIS_DRIVER + cgroup: Ethernet PHY + belong_to: set.CMSIS + +CMSIS_Driver_Include.Flash: + section-type: component + contents: + repo_base_path: CMSIS/Driver + project_base_path: CMSIS_driver + cc-include: + - repo_relative_path: "Include" + files: + - source: Include/Driver_Flash.h + - source: DriverTemplates/Driver_Flash.c + template: true + - source: Include/Driver_Common.h + section_info: + version: 2.3.0 + type: CMSIS_driver + user_visible: never + full_name: CMSIS Driver Flash + description: "Access to #include Driver_Flash.h file for custom implementation" + display_name: CMSIS_Driver_Flash + product: + cmsis_pack: + api: true + taxonomy: + belong_to: CMSIS_DRIVER + cgroup: Flash + belong_to: set.CMSIS + +CMSIS_Driver_Include.I2C: + section-type: component + contents: + repo_base_path: CMSIS/Driver + project_base_path: CMSIS_driver + cc-include: + - repo_relative_path: "Include" + files: + - source: Include/Driver_I2C.h + - source: DriverTemplates/Driver_I2C.c + template: true + - source: Include/Driver_Common.h + section_info: + version: 2.4.0 + type: CMSIS_driver + user_visible: never + full_name: CMSIS Driver I2C + description: "Access to #include Driver_I2C.h file for custom implementation" + display_name: CMSIS_Driver_I2C + product: + cmsis_pack: + api: true + taxonomy: + belong_to: CMSIS_DRIVER + cgroup: I2C + belong_to: set.CMSIS + +CMSIS_Driver_Include.MCI: + section-type: component + contents: + repo_base_path: CMSIS/Driver + project_base_path: CMSIS_driver + cc-include: + - repo_relative_path: "Include" + files: + - source: Include/Driver_MCI.h + - source: DriverTemplates/Driver_MCI.c + template: true + - source: Include/Driver_Common.h + section_info: + version: 2.4.0 + type: CMSIS_driver + user_visible: never + full_name: CMSIS Driver MCI + description: "Access to #include Driver_MCI.h file for custom implementation" + display_name: CMSIS_Driver_MCI + product: + cmsis_pack: + api: true + taxonomy: + belong_to: CMSIS_DRIVER + cgroup: MCI + belong_to: set.CMSIS + +CMSIS_Driver_Include.NAND: + section-type: component + contents: + repo_base_path: CMSIS/Driver + project_base_path: CMSIS_driver + cc-include: + - repo_relative_path: "Include" + files: + - source: Include/Driver_NAND.h + - source: DriverTemplates/Driver_NAND.c + template: true + - source: Include/Driver_Common.h + section_info: + version: 2.4.0 + type: CMSIS_driver + user_visible: never + full_name: CMSIS Driver NAND + description: "Access to #include Driver_NAND.h file for custom implementation" + display_name: CMSIS_Driver_NAND + product: + cmsis_pack: + api: true + taxonomy: + belong_to: CMSIS_DRIVER + cgroup: NAND + belong_to: set.CMSIS + +CMSIS_Driver_Include.SAI: + section-type: component + contents: + repo_base_path: CMSIS/Driver + project_base_path: CMSIS_driver + cc-include: + - repo_relative_path: "Include" + files: + - source: Include/Driver_SAI.h + - source: DriverTemplates/Driver_SAI.c + template: true + - source: Include/Driver_Common.h + section_info: + version: 1.2.0 + type: CMSIS_driver + user_visible: never + full_name: CMSIS Driver SAI + description: "Access to #include Driver_SAI.h file for custom implementation" + display_name: CMSIS_Driver_SAI + product: + cmsis_pack: + api: true + taxonomy: + belong_to: CMSIS_DRIVER + cgroup: SAI + belong_to: set.CMSIS + +CMSIS_Driver_Include.SPI: + section-type: component + contents: + repo_base_path: CMSIS/Driver + project_base_path: CMSIS_driver + cc-include: + - repo_relative_path: "Include" + files: + - source: Include/Driver_SPI.h + - source: DriverTemplates/Driver_SPI.c + template: true + - source: Include/Driver_Common.h + section_info: + version: 2.3.0 + type: CMSIS_driver + user_visible: never + full_name: CMSIS Driver SPI + description: "Access to #include Driver_SPI.h file for custom implementation" + display_name: CMSIS_Driver_SPI + product: + cmsis_pack: + api: true + taxonomy: + belong_to: CMSIS_DRIVER + cgroup: SPI + belong_to: set.CMSIS + +# Mismatch. There is no CMSIS_Driver_Include USB in ARM.CMSIS.pdsc. Such Driver_USB.h is the common head file +# included in Driver_USBD.h and Driver_USBH.h. + +CMSIS_Driver_Include.USB_Device: + section-type: component + contents: + repo_base_path: CMSIS/Driver + project_base_path: CMSIS_driver + cc-include: + - repo_relative_path: "Include" + files: + - source: Include/Driver_USBD.h + - source: DriverTemplates/Driver_USBD.c + template: true + - source: Include/Driver_USB.h + - source: Include/Driver_Common.h + section_info: + version: 2.3.0 + type: CMSIS_driver + user_visible: never + full_name: CMSIS Driver USB Device + description: "Access to #include Driver_USBD.h file for custom implementation" + display_name: CMSIS_Driver_USB_Device + product: + cmsis_pack: + api: true + taxonomy: + belong_to: CMSIS_DRIVER + cgroup: USB Device + belong_to: set.CMSIS + +CMSIS_Driver_Include.USB_Host: + section-type: component + contents: + repo_base_path: CMSIS/Driver + project_base_path: CMSIS_driver + cc-include: + - repo_relative_path: "Include" + files: + - source: Include/Driver_USBH.h + - source: DriverTemplates/Driver_USBH.c + template: true + - source: Include/Driver_USB.h + - source: Include/Driver_Common.h + section_info: + version: 2.3.0 + type: CMSIS_driver + user_visible: never + full_name: CMSIS Driver USB Host + description: "Access to #include Driver_USBH.h file for custom implementation" + display_name: CMSIS_Driver_USB_Host + product: + cmsis_pack: + api: true + taxonomy: + belong_to: CMSIS_DRIVER + cgroup: USB Host + belong_to: set.CMSIS + +CMSIS_Driver_Include.WiFi: + section-type: component + contents: + repo_base_path: CMSIS/Driver + project_base_path: CMSIS_driver + cc-include: + - repo_relative_path: "Include" + files: + - source: Include/Driver_WiFi.h + - source: DriverTemplates/Driver_WiFi.c + template: true + - source: Include/Driver_Common.h + section_info: + version: 1.1.0 + type: CMSIS_driver + user_visible: never + full_name: CMSIS Driver WiFi + description: "Access to #include Driver_WiFi.h file" + display_name: CMSIS_Driver_WiFi + product: + cmsis_pack: + api: true + taxonomy: + belong_to: CMSIS_DRIVER + cgroup: WiFi + belong_to: set.CMSIS + +# ## CMSIS Device API +# # Mismatch. In ARM.CMSIS.pdsc, an API is a special form of a software component that only defines a C/C++ Application Programming Interface (API), such OS Tick and RTOS2 are API. +# # In SDK yml data record, there is no such concept called API. So for the time being, we use component for them. +CMSIS_Device_API_OSTick: + section-type: component + contents: + repo_base_path: CMSIS/RTOS2/Include + project_base_path: CMSIS/RTOS2/Include + cc-include: + - repo_relative_path: "./" + files: + - source: os_tick.h + section_info: + # There is no version for api in ARM CMSIS, using apiversion instead + version: 1.0.1 + user_visible: never + type: CMSIS_driver + full_name: CMSIS Device API OSTick + description: Device interrupt controller interface + display_name: CMSIS_Device_API_OSTick + taxonomy: + belong_to: Device + cgroup: OS Tick + belong_to: set.CMSIS + +CMSIS_Device_API_RTOS2: + section-type: component + contents: + repo_base_path: CMSIS/RTOS2/Include + project_base_path: CMSIS/RTOS2/Include + cc-include: + - repo_relative_path: "./" + files: + - source: cmsis_os2.h + section_info: + # There is no version for api in ARM CMSIS, using apiversion instead + version: 2.1.3 + user_visible: never + type: CMSIS_driver + full_name: CMSIS Device API RTOS2 + description: CMSIS-RTOS API for Cortex-M, SC000, and SC300 + display_name: CMSIS_Device_API_RTOS2 + taxonomy: + belong_to: CMSIS + cgroup: RTOS2 + belong_to: set.CMSIS + +## CMSIS-RTOS2 Keil RTX5 component +# Mismatch. There is no CMSIS_RTOS2_Common in ARM.CMSIS.pdsc. So we remove it and add common files to CMSIS.RTOS2_Secure and CMSIS.RTOS2_NonSecure + +CMSIS_RTOS2_Secure: + section-type: component + contents: + repo_base_path: CMSIS/RTOS2 + project_base_path: CMSIS/RTOS2 + cc-include: + - repo_relative_path: RTX/Source + - repo_relative_path: RTX/Include + - repo_relative_path: RTX/Config + files: + - source: RTX/Source/rtx_core_c.h + - source: RTX/Source/rtx_core_ca.h + - source: RTX/Source/rtx_core_cm.h + - source: RTX/Source/rtx_lib.h + - source: RTX/Source/rtx_lib.c + - source: RTX/Include/rtx_evr.h + - source: RTX/Include/rtx_os.h + - source: RTX/Include/rtx_def.h + - source: RTX/Config/RTX_Config.c + - source: RTX/Config/RTX_Config.h + + - source: RTX/Library/IAR/RTX_CM0.a + toolchains: iar + attribute: extra-libraries + cores: cm0 cm0p + project_relative_path: RTX/Library + - source: RTX/Library/IAR/RTX_CM3.a + toolchains: iar + attribute: extra-libraries + cores: cm3 cm4 cm7 + project_relative_path: RTX/Library + - source: RTX/Library/IAR/RTX_CM4F.a + toolchains: iar + attribute: extra-libraries + cores: cm4f cm7f + project_relative_path: RTX/Library + - source: RTX/Library/GCC/libRTX_CM0.a + toolchains: armgcc mcux + attribute: extra-libraries + cores: cm0 cm0p + project_relative_path: RTX/Library + - source: RTX/Library/GCC/libRTX_CM3.a + toolchains: armgcc mcux + attribute: extra-libraries + cores: cm3 cm4 cm7 + project_relative_path: RTX/Library + - source: RTX/Library/GCC/libRTX_CM4F.a + toolchains: armgcc mcux + attribute: extra-libraries + cores: cm4f cm7f + project_relative_path: RTX/Library + - source: RTX/Library/ARM/RTX_CM0.lib + toolchains: mdk + attribute: extra-libraries + cores: cm0 cm0p + project_relative_path: RTX/Library + - source: RTX/Library/ARM/RTX_CM3.lib + toolchains: mdk + attribute: extra-libraries + cores: cm3 cm4 cm7 + project_relative_path: RTX/Library + - source: RTX/Library/ARM/RTX_CM4F.lib + toolchains: mdk + attribute: extra-libraries + cores: cm4f cm7f + project_relative_path: RTX/Library + + - source: RTX/Library/IAR/RTX_V8MB.a + compilers: iar + attribute: extra-libraries + cores: cm23 + project_relative_path: "./" + - source: RTX/Library/IAR/RTX_V8MMF.a + compilers: iar + attribute: extra-libraries + cores: cm33 cm33f + fpu: SP_FPU + project_relative_path: "./" + - source: RTX/Library/GCC/libRTX_V8MB.a + compilers: gcc + attribute: extra-libraries + cores: cm23 + project_relative_path: "./" + - source: RTX/Library/GCC/libRTX_V8MMF.a + compilers: gcc + attribute: extra-libraries + cores: cm33 cm33f + fpu: SP_FPU + project_relative_path: "./" + - source: RTX/Library/ARM/RTX_V8MB.lib + compilers: armclang + attribute: extra-libraries + cores: cm23 + project_relative_path: "./" + - source: RTX/Library/ARM/RTX_V8MMF.lib + compilers: armclang + attribute: extra-libraries + cores: cm33 cm33f + fpu: SP_FPU + project_relative_path: "./" + section_info: + type: CMSIS_driver + version: 2.1.3 + user_visible: never + full_name: CMSIS RTOS2 Keil RTX5 + description: CMSIS-RTOS2 RTX5 for Cortex-M, SC000, C300 and Armv8-M (Library) + display_name: CMSIS_RTOS2_Keil_RTX5 + need_require: true + taxonomy: + belong_to: CMSIS + cgroup: RTOS2 + csub: Keil RTX5 + cvariant: Library + dependency: + allOf: + - CMSIS_Device_API_OSTick + - CMSIS_Device_API_RTOS2 + belong_to: set.CMSIS + +CMSIS_RTOS2_NonSecure: + section-type: component + contents: + repo_base_path: CMSIS/RTOS2 + project_base_path: CMSIS/RTOS2 + cc-include: + - repo_relative_path: RTX/Source + - repo_relative_path: RTX/Include + - repo_relative_path: RTX/Config + files: + - source: RTX/Source/rtx_core_c.h + - source: RTX/Source/rtx_core_ca.h + - source: RTX/Source/rtx_core_cm.h + - source: RTX/Source/rtx_lib.h + - source: RTX/Source/rtx_lib.c + - source: RTX/Include/rtx_evr.h + - source: RTX/Include/rtx_os.h + - source: RTX/Include/rtx_def.h + - source: RTX/Config/RTX_Config.c + - source: RTX/Config/RTX_Config.h + + - source: RTX/Library/IAR/RTX_CM0.a + toolchains: iar + attribute: extra-libraries + cores: cm0 cm0p + project_relative_path: RTX/Library + - source: RTX/Library/IAR/RTX_CM3.a + toolchains: iar + attribute: extra-libraries + cores: cm3 cm4 cm7 + project_relative_path: RTX/Library + - source: RTX/Library/IAR/RTX_CM4F.a + toolchains: iar + attribute: extra-libraries + cores: cm4f cm7f + project_relative_path: RTX/Library + - source: RTX/Library/GCC/libRTX_CM0.a + toolchains: armgcc mcux + attribute: extra-libraries + cores: cm0 cm0p + project_relative_path: RTX/Library + - source: RTX/Library/GCC/libRTX_CM3.a + toolchains: armgcc mcux + attribute: extra-libraries + cores: cm3 cm4 cm7 + project_relative_path: RTX/Library + - source: RTX/Library/GCC/libRTX_CM4F.a + toolchains: armgcc mcux + attribute: extra-libraries + cores: cm4f cm7f + project_relative_path: RTX/Library + - source: RTX/Library/ARM/RTX_CM0.lib + toolchains: mdk + attribute: extra-libraries + cores: cm0 cm0p + project_relative_path: RTX/Library + - source: RTX/Library/ARM/RTX_CM3.lib + toolchains: mdk + attribute: extra-libraries + cores: cm3 cm4 cm7 + project_relative_path: RTX/Library + - source: RTX/Library/ARM/RTX_CM4F.lib + toolchains: mdk + attribute: extra-libraries + cores: cm4f cm7f + project_relative_path: RTX/Library + + - source: RTX/Library/IAR/RTX_V8MBN.a + compilers: iar + attribute: extra-libraries + cores: cm23 + project_relative_path: "./" + - source: RTX/Library/IAR/RTX_V8MMFN.a + compilers: iar + attribute: extra-libraries + cores: cm33 cm33f + fpu: SP_FPU + project_relative_path: "./" + - source: RTX/Library/GCC/libRTX_V8MBN.a + compilers: gcc + attribute: extra-libraries + cores: cm23 + project_relative_path: "./" + - source: RTX/Library/GCC/libRTX_V8MMFN.a + compilers: gcc + attribute: extra-libraries + cores: cm33 cm33f + fpu: SP_FPU + project_relative_path: "./" + - source: RTX/Library/ARM/RTX_V8MBN.lib + compilers: armclang + attribute: extra-libraries + cores: cm23 + project_relative_path: "./" + - source: RTX/Library/ARM/RTX_V8MMFN.lib + compilers: armclang + attribute: extra-libraries + cores: cm33 cm33f + fpu: SP_FPU + project_relative_path: "./" + section_info: + type: CMSIS_driver + version: 2.1.3 + user_visible: never + full_name: CMSIS RTOS2 Keil RTX5 Non Secure + description: CMSIS-RTOS2 RTX5 for Armv8-M Non-Secure Domain (Library) + display_name: CMSIS_RTOS2_Keil_RTX5_NS + need_require: true + taxonomy: + belong_to: CMSIS + cgroup: RTOS2 + csub: Keil RTX5 + cvariant: Library_NS + belong_to: set.CMSIS + dependency: + allOf: + - CMSIS_Device_API_OSTick + - CMSIS_Device_API_RTOS2 + +set.CMSIS: + section-type: set + section_info: + fixed_id: CMSIS + version: 1.9.0 + description: CMSIS Software + type: CMSIS + display_name: CMSIS Software + full_name: CMSIS Software + vendor: ARM + set_location: + repo_base_path: ./CMSIS + component_taxonomy: + CMSIS: + cclass: CMSIS + Device: + cclass: Device + CMSIS_DRIVER: + cclass: CMSIS Driver + product: + kex_package: + kex_web_ui: + ui_control: false + ui_control_default: false + ui_release_specific: false + cmsis_pack: + external_pack: true + vendor: ARM + pack_root: + pack_type: SWP + pack_name: CMSIS + pack_version: 5.8.0 + pack_url: http://www.keil.com/pack/ + belong_to: set.CMSIS + +set.CMSIS_DSP_Lib: + section-type: set + section_info: + fixed_id: CMSIS_DSP_Library + version: 1.9.0 + description: CMSIS DSP Software Library + type: middleware + display_name: CMSIS DSP Library + full_name: CMSIS DSP Software Library + vendor: ARM + set_location: + repo_base_path: ./CMSIS + component_taxonomy: + CMSIS: + cclass: CMSIS + product: + scr: + - scr.CMSIS + cmsis_pack: + vendor: ARM + supported: false + kex_package: + kex_web_ui: + ui_category: CMSIS DSP Lib + ui_control: true + ui_control_default: true + ui_release_specific: true + belong_to: set.CMSIS_DSP_Lib + +scr.CMSIS: + section-type: scr + belong_to: set.CMSIS + contents: + license: + - license.CMSIS + Name: CMSIS + Version: 5.8.0 + Format: source code + Description: Vendor-independent hardware abstraction layer for microcontrollers + that are based on Arm Cortex processors, distributed by ARM. cores + Location: CMSIS/ + Origin: NXP (Apache License 2.0) + +license.CMSIS: + section-type: license + belong_to: set.CMSIS + contents: + repo_base_path: CMSIS + files: + - source: LICENSE.txt + section_info: + Outgoing License: Apache License 2.0 \ No newline at end of file diff --git a/CMSIS/Core/Include/CMSIS_Include_core_cm.cmake b/CMSIS/Core/Include/CMSIS_Include_core_cm.cmake new file mode 100644 index 0000000..8f8fd1c --- /dev/null +++ b/CMSIS/Core/Include/CMSIS_Include_core_cm.cmake @@ -0,0 +1,9 @@ +# Add set(CONFIG_USE_CMSIS_Include_core_cm true) in config.cmake to use this component + +include_guard(GLOBAL) +message("${CMAKE_CURRENT_LIST_FILE} component is included.") + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/. +) + diff --git a/CMSIS/Core/Include/CMSIS_Include_core_cm_LPC804.cmake b/CMSIS/Core/Include/CMSIS_Include_core_cm_LPC804.cmake deleted file mode 100644 index 4092d00..0000000 --- a/CMSIS/Core/Include/CMSIS_Include_core_cm_LPC804.cmake +++ /dev/null @@ -1,8 +0,0 @@ -include_guard() -message("CMSIS_Include_core_cm component is included.") - - -target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC - ${CMAKE_CURRENT_LIST_DIR}/. -) - diff --git a/CMSIS/DSP/CMSIS_DSP_Include.cmake b/CMSIS/DSP/CMSIS_DSP_Include.cmake new file mode 100644 index 0000000..79dcba4 --- /dev/null +++ b/CMSIS/DSP/CMSIS_DSP_Include.cmake @@ -0,0 +1,10 @@ +# Add set(CONFIG_USE_CMSIS_DSP_Include true) in config.cmake to use this component + +include_guard(GLOBAL) +message("${CMAKE_CURRENT_LIST_FILE} component is included.") + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/Include + ${CMAKE_CURRENT_LIST_DIR}/PrivateInclude +) + diff --git a/CMSIS/DSP/CMSIS_DSP_Source.cmake b/CMSIS/DSP/CMSIS_DSP_Source.cmake new file mode 100644 index 0000000..c947787 --- /dev/null +++ b/CMSIS/DSP/CMSIS_DSP_Source.cmake @@ -0,0 +1,51 @@ +# Add set(CONFIG_USE_CMSIS_DSP_Source true) in config.cmake to use this component + +include_guard(GLOBAL) +message("${CMAKE_CURRENT_LIST_FILE} component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/Source/BasicMathFunctions/BasicMathFunctions.c + ${CMAKE_CURRENT_LIST_DIR}/Source/BasicMathFunctions/BasicMathFunctionsF16.c + ${CMAKE_CURRENT_LIST_DIR}/Source/BayesFunctions/BayesFunctions.c + ${CMAKE_CURRENT_LIST_DIR}/Source/BayesFunctions/BayesFunctionsF16.c + ${CMAKE_CURRENT_LIST_DIR}/Source/CommonTables/CommonTables.c + ${CMAKE_CURRENT_LIST_DIR}/Source/CommonTables/CommonTablesF16.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ComplexMathFunctions/ComplexMathFunctions.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ComplexMathFunctions/ComplexMathFunctionsF16.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ControllerFunctions/ControllerFunctions.c + ${CMAKE_CURRENT_LIST_DIR}/Source/DistanceFunctions/DistanceFunctions.c + ${CMAKE_CURRENT_LIST_DIR}/Source/DistanceFunctions/DistanceFunctionsF16.c + ${CMAKE_CURRENT_LIST_DIR}/Source/FastMathFunctions/FastMathFunctions.c + ${CMAKE_CURRENT_LIST_DIR}/Source/FastMathFunctions/FastMathFunctionsF16.c + ${CMAKE_CURRENT_LIST_DIR}/Source/FilteringFunctions/FilteringFunctions.c + ${CMAKE_CURRENT_LIST_DIR}/Source/FilteringFunctions/FilteringFunctionsF16.c + ${CMAKE_CURRENT_LIST_DIR}/Source/InterpolationFunctions/InterpolationFunctions.c + ${CMAKE_CURRENT_LIST_DIR}/Source/InterpolationFunctions/InterpolationFunctionsF16.c + ${CMAKE_CURRENT_LIST_DIR}/Source/MatrixFunctions/MatrixFunctions.c + ${CMAKE_CURRENT_LIST_DIR}/Source/MatrixFunctions/MatrixFunctionsF16.c + ${CMAKE_CURRENT_LIST_DIR}/Source/QuaternionMathFunctions/QuaternionMathFunctions.c + ${CMAKE_CURRENT_LIST_DIR}/Source/SVMFunctions/SVMFunctions.c + ${CMAKE_CURRENT_LIST_DIR}/Source/SVMFunctions/SVMFunctionsF16.c + ${CMAKE_CURRENT_LIST_DIR}/Source/StatisticsFunctions/StatisticsFunctions.c + ${CMAKE_CURRENT_LIST_DIR}/Source/StatisticsFunctions/StatisticsFunctionsF16.c + ${CMAKE_CURRENT_LIST_DIR}/Source/SupportFunctions/SupportFunctions.c + ${CMAKE_CURRENT_LIST_DIR}/Source/SupportFunctions/SupportFunctionsF16.c + ${CMAKE_CURRENT_LIST_DIR}/Source/TransformFunctions/TransformFunctions.c + ${CMAKE_CURRENT_LIST_DIR}/Source/TransformFunctions/TransformFunctionsF16.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/Include + ${CMAKE_CURRENT_LIST_DIR}/PrivateInclude + ${CMAKE_CURRENT_LIST_DIR}/Source/DistanceFunctions +) + +if(CONFIG_USE_COMPONENT_CONFIGURATION) + message("===>Import configuration from ${CMAKE_CURRENT_LIST_FILE}") + + target_compile_definitions(${MCUX_SDK_PROJECT_NAME} PUBLIC + -DDISABLEFLOAT16 + ) + +endif() + diff --git a/CMSIS/Driver/CMSIS_Driver_Include_CAN.cmake b/CMSIS/Driver/CMSIS_Driver_Include_CAN.cmake new file mode 100644 index 0000000..b1ac6e5 --- /dev/null +++ b/CMSIS/Driver/CMSIS_Driver_Include_CAN.cmake @@ -0,0 +1,12 @@ +# Add set(CONFIG_USE_CMSIS_Driver_Include_CAN true) in config.cmake to use this component + +include_guard(GLOBAL) +message("${CMAKE_CURRENT_LIST_FILE} component is included.") + +# template file +# ${CMAKE_CURRENT_LIST_DIR}/DriverTemplates/Driver_CAN.c + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/Include +) + diff --git a/CMSIS/Driver/CMSIS_Driver_Include_Ethernet.cmake b/CMSIS/Driver/CMSIS_Driver_Include_Ethernet.cmake new file mode 100644 index 0000000..f0b9a57 --- /dev/null +++ b/CMSIS/Driver/CMSIS_Driver_Include_Ethernet.cmake @@ -0,0 +1,13 @@ +# Add set(CONFIG_USE_CMSIS_Driver_Include_Ethernet true) in config.cmake to use this component + +include_guard(GLOBAL) +message("${CMAKE_CURRENT_LIST_FILE} component is included.") + +# template file +# ${CMAKE_CURRENT_LIST_DIR}/DriverTemplates/Driver_ETH_MAC.c +# ${CMAKE_CURRENT_LIST_DIR}/DriverTemplates/Driver_ETH_PHY.c + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/Include +) + diff --git a/CMSIS/Driver/CMSIS_Driver_Include_Ethernet_MAC.cmake b/CMSIS/Driver/CMSIS_Driver_Include_Ethernet_MAC.cmake new file mode 100644 index 0000000..2084058 --- /dev/null +++ b/CMSIS/Driver/CMSIS_Driver_Include_Ethernet_MAC.cmake @@ -0,0 +1,12 @@ +# Add set(CONFIG_USE_CMSIS_Driver_Include_Ethernet_MAC true) in config.cmake to use this component + +include_guard(GLOBAL) +message("${CMAKE_CURRENT_LIST_FILE} component is included.") + +# template file +# ${CMAKE_CURRENT_LIST_DIR}/DriverTemplates/Driver_ETH_MAC.c + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/Include +) + diff --git a/CMSIS/Driver/CMSIS_Driver_Include_Ethernet_PHY.cmake b/CMSIS/Driver/CMSIS_Driver_Include_Ethernet_PHY.cmake new file mode 100644 index 0000000..250799f --- /dev/null +++ b/CMSIS/Driver/CMSIS_Driver_Include_Ethernet_PHY.cmake @@ -0,0 +1,12 @@ +# Add set(CONFIG_USE_CMSIS_Driver_Include_Ethernet_PHY true) in config.cmake to use this component + +include_guard(GLOBAL) +message("${CMAKE_CURRENT_LIST_FILE} component is included.") + +# template file +# ${CMAKE_CURRENT_LIST_DIR}/DriverTemplates/Driver_ETH_PHY.c + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/Include +) + diff --git a/CMSIS/Driver/CMSIS_Driver_Include_Flash.cmake b/CMSIS/Driver/CMSIS_Driver_Include_Flash.cmake new file mode 100644 index 0000000..0866719 --- /dev/null +++ b/CMSIS/Driver/CMSIS_Driver_Include_Flash.cmake @@ -0,0 +1,12 @@ +# Add set(CONFIG_USE_CMSIS_Driver_Include_Flash true) in config.cmake to use this component + +include_guard(GLOBAL) +message("${CMAKE_CURRENT_LIST_FILE} component is included.") + +# template file +# ${CMAKE_CURRENT_LIST_DIR}/DriverTemplates/Driver_Flash.c + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/Include +) + diff --git a/CMSIS/Driver/CMSIS_Driver_Include_I2C.cmake b/CMSIS/Driver/CMSIS_Driver_Include_I2C.cmake new file mode 100644 index 0000000..46030df --- /dev/null +++ b/CMSIS/Driver/CMSIS_Driver_Include_I2C.cmake @@ -0,0 +1,12 @@ +# Add set(CONFIG_USE_CMSIS_Driver_Include_I2C true) in config.cmake to use this component + +include_guard(GLOBAL) +message("${CMAKE_CURRENT_LIST_FILE} component is included.") + +# template file +# ${CMAKE_CURRENT_LIST_DIR}/DriverTemplates/Driver_I2C.c + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/Include +) + diff --git a/CMSIS/Driver/CMSIS_Driver_Include_MCI.cmake b/CMSIS/Driver/CMSIS_Driver_Include_MCI.cmake new file mode 100644 index 0000000..4f388a0 --- /dev/null +++ b/CMSIS/Driver/CMSIS_Driver_Include_MCI.cmake @@ -0,0 +1,12 @@ +# Add set(CONFIG_USE_CMSIS_Driver_Include_MCI true) in config.cmake to use this component + +include_guard(GLOBAL) +message("${CMAKE_CURRENT_LIST_FILE} component is included.") + +# template file +# ${CMAKE_CURRENT_LIST_DIR}/DriverTemplates/Driver_MCI.c + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/Include +) + diff --git a/CMSIS/Driver/CMSIS_Driver_Include_NAND.cmake b/CMSIS/Driver/CMSIS_Driver_Include_NAND.cmake new file mode 100644 index 0000000..58f4ce4 --- /dev/null +++ b/CMSIS/Driver/CMSIS_Driver_Include_NAND.cmake @@ -0,0 +1,12 @@ +# Add set(CONFIG_USE_CMSIS_Driver_Include_NAND true) in config.cmake to use this component + +include_guard(GLOBAL) +message("${CMAKE_CURRENT_LIST_FILE} component is included.") + +# template file +# ${CMAKE_CURRENT_LIST_DIR}/DriverTemplates/Driver_NAND.c + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/Include +) + diff --git a/CMSIS/Driver/CMSIS_Driver_Include_SAI.cmake b/CMSIS/Driver/CMSIS_Driver_Include_SAI.cmake new file mode 100644 index 0000000..a7dfcb7 --- /dev/null +++ b/CMSIS/Driver/CMSIS_Driver_Include_SAI.cmake @@ -0,0 +1,12 @@ +# Add set(CONFIG_USE_CMSIS_Driver_Include_SAI true) in config.cmake to use this component + +include_guard(GLOBAL) +message("${CMAKE_CURRENT_LIST_FILE} component is included.") + +# template file +# ${CMAKE_CURRENT_LIST_DIR}/DriverTemplates/Driver_SAI.c + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/Include +) + diff --git a/CMSIS/Driver/CMSIS_Driver_Include_SPI.cmake b/CMSIS/Driver/CMSIS_Driver_Include_SPI.cmake new file mode 100644 index 0000000..b777856 --- /dev/null +++ b/CMSIS/Driver/CMSIS_Driver_Include_SPI.cmake @@ -0,0 +1,12 @@ +# Add set(CONFIG_USE_CMSIS_Driver_Include_SPI true) in config.cmake to use this component + +include_guard(GLOBAL) +message("${CMAKE_CURRENT_LIST_FILE} component is included.") + +# template file +# ${CMAKE_CURRENT_LIST_DIR}/DriverTemplates/Driver_SPI.c + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/Include +) + diff --git a/CMSIS/Driver/CMSIS_Driver_Include_USART.cmake b/CMSIS/Driver/CMSIS_Driver_Include_USART.cmake new file mode 100644 index 0000000..ee425b8 --- /dev/null +++ b/CMSIS/Driver/CMSIS_Driver_Include_USART.cmake @@ -0,0 +1,12 @@ +# Add set(CONFIG_USE_CMSIS_Driver_Include_USART true) in config.cmake to use this component + +include_guard(GLOBAL) +message("${CMAKE_CURRENT_LIST_FILE} component is included.") + +# template file +# ${CMAKE_CURRENT_LIST_DIR}/DriverTemplates/Driver_USART.c + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/Include +) + diff --git a/CMSIS/Driver/CMSIS_Driver_Include_USB_Device.cmake b/CMSIS/Driver/CMSIS_Driver_Include_USB_Device.cmake new file mode 100644 index 0000000..d0dcdbd --- /dev/null +++ b/CMSIS/Driver/CMSIS_Driver_Include_USB_Device.cmake @@ -0,0 +1,12 @@ +# Add set(CONFIG_USE_CMSIS_Driver_Include_USB_Device true) in config.cmake to use this component + +include_guard(GLOBAL) +message("${CMAKE_CURRENT_LIST_FILE} component is included.") + +# template file +# ${CMAKE_CURRENT_LIST_DIR}/DriverTemplates/Driver_USBD.c + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/Include +) + diff --git a/CMSIS/Driver/CMSIS_Driver_Include_USB_Host.cmake b/CMSIS/Driver/CMSIS_Driver_Include_USB_Host.cmake new file mode 100644 index 0000000..2d5c66a --- /dev/null +++ b/CMSIS/Driver/CMSIS_Driver_Include_USB_Host.cmake @@ -0,0 +1,12 @@ +# Add set(CONFIG_USE_CMSIS_Driver_Include_USB_Host true) in config.cmake to use this component + +include_guard(GLOBAL) +message("${CMAKE_CURRENT_LIST_FILE} component is included.") + +# template file +# ${CMAKE_CURRENT_LIST_DIR}/DriverTemplates/Driver_USBH.c + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/Include +) + diff --git a/CMSIS/Driver/CMSIS_Driver_Include_WiFi.cmake b/CMSIS/Driver/CMSIS_Driver_Include_WiFi.cmake new file mode 100644 index 0000000..00fe68c --- /dev/null +++ b/CMSIS/Driver/CMSIS_Driver_Include_WiFi.cmake @@ -0,0 +1,12 @@ +# Add set(CONFIG_USE_CMSIS_Driver_Include_WiFi true) in config.cmake to use this component + +include_guard(GLOBAL) +message("${CMAKE_CURRENT_LIST_FILE} component is included.") + +# template file +# ${CMAKE_CURRENT_LIST_DIR}/DriverTemplates/Driver_WiFi.c + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/Include +) + diff --git a/CMSIS/NN/CMSIS_NN_Source.cmake b/CMSIS/NN/CMSIS_NN_Source.cmake new file mode 100644 index 0000000..aee99d0 --- /dev/null +++ b/CMSIS/NN/CMSIS_NN_Source.cmake @@ -0,0 +1,89 @@ +# Add set(CONFIG_USE_CMSIS_NN_Source true) in config.cmake to use this component + +include_guard(GLOBAL) +message("${CMAKE_CURRENT_LIST_FILE} component is included.") + +if(CONFIG_USE_CMSIS_DSP_Source) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/Source/ActivationFunctions/arm_nn_activations_q15.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ActivationFunctions/arm_nn_activations_q7.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ActivationFunctions/arm_relu6_s8.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ActivationFunctions/arm_relu_q15.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ActivationFunctions/arm_relu_q7.c + ${CMAKE_CURRENT_LIST_DIR}/Source/BasicMathFunctions/arm_elementwise_add_s8.c + ${CMAKE_CURRENT_LIST_DIR}/Source/BasicMathFunctions/arm_elementwise_mul_s8.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ConcatenationFunctions/arm_concatenation_s8_w.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ConcatenationFunctions/arm_concatenation_s8_x.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ConcatenationFunctions/arm_concatenation_s8_y.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ConcatenationFunctions/arm_concatenation_s8_z.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ConvolutionFunctions/arm_convolve_1x1_s8_fast.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ConvolutionFunctions/arm_convolve_1_x_n_s8.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast_nonsquare.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ConvolutionFunctions/arm_convolve_s8.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ConvolutionFunctions/arm_convolve_wrapper_s8.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ConvolutionFunctions/arm_depthwise_conv_3x3_s8.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ConvolutionFunctions/arm_depthwise_conv_s8.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ConvolutionFunctions/arm_depthwise_conv_s8_opt.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ConvolutionFunctions/arm_depthwise_conv_u8_basic_ver1.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s8.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ConvolutionFunctions/arm_nn_depthwise_conv_s8_core.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_s8_s16.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_s8_s16_reordered.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ConvolutionFunctions/arm_nn_mat_mult_s8.c + ${CMAKE_CURRENT_LIST_DIR}/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c + ${CMAKE_CURRENT_LIST_DIR}/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c + ${CMAKE_CURRENT_LIST_DIR}/Source/FullyConnectedFunctions/arm_fully_connected_q15.c + ${CMAKE_CURRENT_LIST_DIR}/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c + ${CMAKE_CURRENT_LIST_DIR}/Source/FullyConnectedFunctions/arm_fully_connected_q7.c + ${CMAKE_CURRENT_LIST_DIR}/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c + ${CMAKE_CURRENT_LIST_DIR}/Source/FullyConnectedFunctions/arm_fully_connected_s8.c + ${CMAKE_CURRENT_LIST_DIR}/Source/NNSupportFunctions/arm_nntables.c + ${CMAKE_CURRENT_LIST_DIR}/Source/NNSupportFunctions/arm_nn_accumulate_q7_to_q15.c + ${CMAKE_CURRENT_LIST_DIR}/Source/NNSupportFunctions/arm_nn_add_q7.c + ${CMAKE_CURRENT_LIST_DIR}/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_padded_s8.c + ${CMAKE_CURRENT_LIST_DIR}/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s8.c + ${CMAKE_CURRENT_LIST_DIR}/Source/NNSupportFunctions/arm_nn_mat_mult_nt_t_s8.c + ${CMAKE_CURRENT_LIST_DIR}/Source/NNSupportFunctions/arm_nn_mat_mul_core_1x_s8.c + ${CMAKE_CURRENT_LIST_DIR}/Source/NNSupportFunctions/arm_nn_mat_mul_core_4x_s8.c + ${CMAKE_CURRENT_LIST_DIR}/Source/NNSupportFunctions/arm_nn_mult_q15.c + ${CMAKE_CURRENT_LIST_DIR}/Source/NNSupportFunctions/arm_nn_mult_q7.c + ${CMAKE_CURRENT_LIST_DIR}/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s8.c + ${CMAKE_CURRENT_LIST_DIR}/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_svdf_s8.c + ${CMAKE_CURRENT_LIST_DIR}/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c + ${CMAKE_CURRENT_LIST_DIR}/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.c + ${CMAKE_CURRENT_LIST_DIR}/Source/NNSupportFunctions/arm_q7_to_q15_reordered_with_offset.c + ${CMAKE_CURRENT_LIST_DIR}/Source/NNSupportFunctions/arm_q7_to_q15_with_offset.c + ${CMAKE_CURRENT_LIST_DIR}/Source/PoolingFunctions/arm_avgpool_s8.c + ${CMAKE_CURRENT_LIST_DIR}/Source/PoolingFunctions/arm_max_pool_s8.c + ${CMAKE_CURRENT_LIST_DIR}/Source/PoolingFunctions/arm_pool_q7_HWC.c + ${CMAKE_CURRENT_LIST_DIR}/Source/ReshapeFunctions/arm_reshape_s8.c + ${CMAKE_CURRENT_LIST_DIR}/Source/SoftmaxFunctions/arm_softmax_q15.c + ${CMAKE_CURRENT_LIST_DIR}/Source/SoftmaxFunctions/arm_softmax_q7.c + ${CMAKE_CURRENT_LIST_DIR}/Source/SoftmaxFunctions/arm_softmax_s8.c + ${CMAKE_CURRENT_LIST_DIR}/Source/SoftmaxFunctions/arm_softmax_u8.c + ${CMAKE_CURRENT_LIST_DIR}/Source/SoftmaxFunctions/arm_softmax_with_batch_q7.c + ${CMAKE_CURRENT_LIST_DIR}/Source/SVDFunctions/arm_svdf_s8.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/Include +) + +else() + +message(SEND_ERROR "CMSIS_NN_Source dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() diff --git a/CMSIS/RTOS2/CMSIS_RTOS2_NonSecure.cmake b/CMSIS/RTOS2/CMSIS_RTOS2_NonSecure.cmake new file mode 100644 index 0000000..514f380 --- /dev/null +++ b/CMSIS/RTOS2/CMSIS_RTOS2_NonSecure.cmake @@ -0,0 +1,95 @@ +# Add set(CONFIG_USE_CMSIS_RTOS2_NonSecure true) in config.cmake to use this component + +include_guard(GLOBAL) +message("${CMAKE_CURRENT_LIST_FILE} component is included.") + +if(CONFIG_USE_CMSIS_Device_API_OSTick AND CONFIG_USE_CMSIS_Device_API_RTOS2) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/RTX/Source/rtx_lib.c + ${CMAKE_CURRENT_LIST_DIR}/RTX/Config/RTX_Config.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/RTX/Source + ${CMAKE_CURRENT_LIST_DIR}/RTX/Include + ${CMAKE_CURRENT_LIST_DIR}/RTX/Config +) + +if(CONFIG_TOOLCHAIN STREQUAL iar AND CONFIG_CORE STREQUAL cm0p) + target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE + -Wl,--start-group + ${CMAKE_CURRENT_LIST_DIR}/RTX/Library/IAR/RTX_CM0.a + -Wl,--end-group + ) +endif() + +if(CONFIG_TOOLCHAIN STREQUAL iar AND (CONFIG_CORE STREQUAL cm4f OR CONFIG_CORE STREQUAL cm7f)) + target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE + -Wl,--start-group + ${CMAKE_CURRENT_LIST_DIR}/RTX/Library/IAR/RTX_CM4F.a + -Wl,--end-group + ) +endif() + +if((CONFIG_TOOLCHAIN STREQUAL armgcc OR CONFIG_TOOLCHAIN STREQUAL mcux) AND CONFIG_CORE STREQUAL cm0p) + target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE + -Wl,--start-group + ${CMAKE_CURRENT_LIST_DIR}/RTX/Library/GCC/libRTX_CM0.a + -Wl,--end-group + ) +endif() + +if((CONFIG_TOOLCHAIN STREQUAL armgcc OR CONFIG_TOOLCHAIN STREQUAL mcux) AND (CONFIG_CORE STREQUAL cm4f OR CONFIG_CORE STREQUAL cm7f)) + target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE + -Wl,--start-group + ${CMAKE_CURRENT_LIST_DIR}/RTX/Library/GCC/libRTX_CM4F.a + -Wl,--end-group + ) +endif() + +if(CONFIG_TOOLCHAIN STREQUAL mdk AND CONFIG_CORE STREQUAL cm0p) + target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE + -Wl,--start-group + ${CMAKE_CURRENT_LIST_DIR}/RTX/Library/ARM/RTX_CM0.lib + -Wl,--end-group + ) +endif() + +if(CONFIG_TOOLCHAIN STREQUAL mdk AND (CONFIG_CORE STREQUAL cm4f OR CONFIG_CORE STREQUAL cm7f)) + target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE + -Wl,--start-group + ${CMAKE_CURRENT_LIST_DIR}/RTX/Library/ARM/RTX_CM4F.lib + -Wl,--end-group + ) +endif() + +if(CONFIG_COMPILER STREQUAL iar AND CONFIG_CORE STREQUAL cm33 AND CONFIG_FPU STREQUAL SP_FPU) + target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE + -Wl,--start-group + ${CMAKE_CURRENT_LIST_DIR}/RTX/Library/IAR/RTX_V8MMFN.a + -Wl,--end-group + ) +endif() + +if(CONFIG_COMPILER STREQUAL gcc AND CONFIG_CORE STREQUAL cm33 AND CONFIG_FPU STREQUAL SP_FPU) + target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE + -Wl,--start-group + ${CMAKE_CURRENT_LIST_DIR}/RTX/Library/GCC/libRTX_V8MMFN.a + -Wl,--end-group + ) +endif() + +if(CONFIG_COMPILER STREQUAL armclang AND CONFIG_CORE STREQUAL cm33 AND CONFIG_FPU STREQUAL SP_FPU) + target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE + -Wl,--start-group + ${CMAKE_CURRENT_LIST_DIR}/RTX/Library/ARM/RTX_V8MMFN.lib + -Wl,--end-group + ) +endif() + +else() + +message(SEND_ERROR "CMSIS_RTOS2_NonSecure dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() diff --git a/CMSIS/RTOS2/CMSIS_RTOS2_Secure.cmake b/CMSIS/RTOS2/CMSIS_RTOS2_Secure.cmake new file mode 100644 index 0000000..e3cecd1 --- /dev/null +++ b/CMSIS/RTOS2/CMSIS_RTOS2_Secure.cmake @@ -0,0 +1,95 @@ +# Add set(CONFIG_USE_CMSIS_RTOS2_Secure true) in config.cmake to use this component + +include_guard(GLOBAL) +message("${CMAKE_CURRENT_LIST_FILE} component is included.") + +if(CONFIG_USE_CMSIS_Device_API_OSTick AND CONFIG_USE_CMSIS_Device_API_RTOS2) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/RTX/Source/rtx_lib.c + ${CMAKE_CURRENT_LIST_DIR}/RTX/Config/RTX_Config.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/RTX/Source + ${CMAKE_CURRENT_LIST_DIR}/RTX/Include + ${CMAKE_CURRENT_LIST_DIR}/RTX/Config +) + +if(CONFIG_TOOLCHAIN STREQUAL iar AND CONFIG_CORE STREQUAL cm0p) + target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE + -Wl,--start-group + ${CMAKE_CURRENT_LIST_DIR}/RTX/Library/IAR/RTX_CM0.a + -Wl,--end-group + ) +endif() + +if(CONFIG_TOOLCHAIN STREQUAL iar AND (CONFIG_CORE STREQUAL cm4f OR CONFIG_CORE STREQUAL cm7f)) + target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE + -Wl,--start-group + ${CMAKE_CURRENT_LIST_DIR}/RTX/Library/IAR/RTX_CM4F.a + -Wl,--end-group + ) +endif() + +if((CONFIG_TOOLCHAIN STREQUAL armgcc OR CONFIG_TOOLCHAIN STREQUAL mcux) AND CONFIG_CORE STREQUAL cm0p) + target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE + -Wl,--start-group + ${CMAKE_CURRENT_LIST_DIR}/RTX/Library/GCC/libRTX_CM0.a + -Wl,--end-group + ) +endif() + +if((CONFIG_TOOLCHAIN STREQUAL armgcc OR CONFIG_TOOLCHAIN STREQUAL mcux) AND (CONFIG_CORE STREQUAL cm4f OR CONFIG_CORE STREQUAL cm7f)) + target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE + -Wl,--start-group + ${CMAKE_CURRENT_LIST_DIR}/RTX/Library/GCC/libRTX_CM4F.a + -Wl,--end-group + ) +endif() + +if(CONFIG_TOOLCHAIN STREQUAL mdk AND CONFIG_CORE STREQUAL cm0p) + target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE + -Wl,--start-group + ${CMAKE_CURRENT_LIST_DIR}/RTX/Library/ARM/RTX_CM0.lib + -Wl,--end-group + ) +endif() + +if(CONFIG_TOOLCHAIN STREQUAL mdk AND (CONFIG_CORE STREQUAL cm4f OR CONFIG_CORE STREQUAL cm7f)) + target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE + -Wl,--start-group + ${CMAKE_CURRENT_LIST_DIR}/RTX/Library/ARM/RTX_CM4F.lib + -Wl,--end-group + ) +endif() + +if(CONFIG_COMPILER STREQUAL iar AND CONFIG_CORE STREQUAL cm33 AND CONFIG_FPU STREQUAL SP_FPU) + target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE + -Wl,--start-group + ${CMAKE_CURRENT_LIST_DIR}/RTX/Library/IAR/RTX_V8MMF.a + -Wl,--end-group + ) +endif() + +if(CONFIG_COMPILER STREQUAL gcc AND CONFIG_CORE STREQUAL cm33 AND CONFIG_FPU STREQUAL SP_FPU) + target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE + -Wl,--start-group + ${CMAKE_CURRENT_LIST_DIR}/RTX/Library/GCC/libRTX_V8MMF.a + -Wl,--end-group + ) +endif() + +if(CONFIG_COMPILER STREQUAL armclang AND CONFIG_CORE STREQUAL cm33 AND CONFIG_FPU STREQUAL SP_FPU) + target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE + -Wl,--start-group + ${CMAKE_CURRENT_LIST_DIR}/RTX/Library/ARM/RTX_V8MMF.lib + -Wl,--end-group + ) +endif() + +else() + +message(SEND_ERROR "CMSIS_RTOS2_Secure dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() diff --git a/CMSIS/RTOS2/Include/CMSIS_Device_API_OSTick.cmake b/CMSIS/RTOS2/Include/CMSIS_Device_API_OSTick.cmake new file mode 100644 index 0000000..dade778 --- /dev/null +++ b/CMSIS/RTOS2/Include/CMSIS_Device_API_OSTick.cmake @@ -0,0 +1,9 @@ +# Add set(CONFIG_USE_CMSIS_Device_API_OSTick true) in config.cmake to use this component + +include_guard(GLOBAL) +message("${CMAKE_CURRENT_LIST_FILE} component is included.") + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/. +) + diff --git a/CMSIS/RTOS2/Include/CMSIS_Device_API_RTOS2.cmake b/CMSIS/RTOS2/Include/CMSIS_Device_API_RTOS2.cmake new file mode 100644 index 0000000..725d43f --- /dev/null +++ b/CMSIS/RTOS2/Include/CMSIS_Device_API_RTOS2.cmake @@ -0,0 +1,9 @@ +# Add set(CONFIG_USE_CMSIS_Device_API_RTOS2 true) in config.cmake to use this component + +include_guard(GLOBAL) +message("${CMAKE_CURRENT_LIST_FILE} component is included.") + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/. +) + diff --git a/CMSIS/RTOS2/RTX/Config/RTX_Config.c b/CMSIS/RTOS2/RTX/Config/RTX_Config.c new file mode 100644 index 0000000..737078a --- /dev/null +++ b/CMSIS/RTOS2/RTX/Config/RTX_Config.c @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2013-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.1 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + + for (;;) {} +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; + + switch (code) { + case osRtxErrorStackOverflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +} diff --git a/CMSIS/RTOS2/RTX/Config/RTX_Config.h b/CMSIS/RTOS2/RTX/Config/RTX_Config.h new file mode 100644 index 0000000..4d2f501 --- /dev/null +++ b/CMSIS/RTOS2/RTX/Config/RTX_Config.h @@ -0,0 +1,580 @@ +/* + * Copyright (c) 2013-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.5.2 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 32768 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 32768 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 0 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 1 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 0 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 3072 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 3072 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 512 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 512 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch (requires RTX source variant). +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 0 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 512 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 512 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial recording level applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Recording levels for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Recording level for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_LEVEL +#define OS_EVR_MEMORY_LEVEL 0x81U +#endif + +// Kernel +// Recording level for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_LEVEL +#define OS_EVR_KERNEL_LEVEL 0x81U +#endif + +// Thread +// Recording level for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_LEVEL +#define OS_EVR_THREAD_LEVEL 0x85U +#endif + +// Generic Wait +// Recording level for Generic Wait events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_WAIT_LEVEL +#define OS_EVR_WAIT_LEVEL 0x81U +#endif + +// Thread Flags +// Recording level for Thread Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THFLAGS_LEVEL +#define OS_EVR_THFLAGS_LEVEL 0x81U +#endif + +// Event Flags +// Recording level for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_LEVEL +#define OS_EVR_EVFLAGS_LEVEL 0x81U +#endif + +// Timer +// Recording level for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_LEVEL +#define OS_EVR_TIMER_LEVEL 0x81U +#endif + +// Mutex +// Recording level for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_LEVEL +#define OS_EVR_MUTEX_LEVEL 0x81U +#endif + +// Semaphore +// Recording level for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_LEVEL +#define OS_EVR_SEMAPHORE_LEVEL 0x81U +#endif + +// Memory Pool +// Recording level for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_LEVEL +#define OS_EVR_MEMPOOL_LEVEL 0x81U +#endif + +// Message Queue +// Recording level for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_LEVEL +#define OS_EVR_MSGQUEUE_LEVEL 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Generic Wait +// Enables Generic Wait event generation. +#ifndef OS_EVR_WAIT +#define OS_EVR_WAIT 1 +#endif + +// Thread Flags +// Enables Thread Flags event generation. +#ifndef OS_EVR_THFLAGS +#define OS_EVR_THFLAGS 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#ifndef OS_THREAD_LIBSPACE_NUM +#define OS_THREAD_LIBSPACE_NUM 4 +#endif +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/CMSIS/RTOS2/RTX/Include/rtx_def.h b/CMSIS/RTOS2/RTX/Include/rtx_def.h new file mode 100644 index 0000000..a7076a4 --- /dev/null +++ b/CMSIS/RTOS2/RTX/Include/rtx_def.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * + * This Software is licensed under an Arm proprietary license. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: RTX derived definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_DEF_H_ +#define RTX_DEF_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#endif +#include "RTX_Config.h" + +#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0)) + #define RTX_OBJ_MEM_USAGE +#endif + +#if (defined(OS_STACK_CHECK) && (OS_STACK_CHECK != 0)) + #define RTX_STACK_CHECK +#endif + +#ifdef RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS + #define DOMAIN_NS 1 +#endif + +#endif // RTX_DEF_H_ diff --git a/CMSIS/RTOS2/RTX/Include/rtx_evr.h b/CMSIS/RTOS2/RTX/Include/rtx_evr.h new file mode 100644 index 0000000..2a6899e --- /dev/null +++ b/CMSIS/RTOS2/RTX/Include/rtx_evr.h @@ -0,0 +1,1983 @@ +/* + * Copyright (c) 2013-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: RTX Event Recorder definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_EVR_H_ +#define RTX_EVR_H_ + +#include "rtx_os.h" // RTX OS definitions + +// Initial Thread configuration covered also Thread Flags and Generic Wait +#ifndef OS_EVR_THFLAGS +#define OS_EVR_THFLAGS OS_EVR_THREAD +#endif +#ifndef OS_EVR_WAIT +#define OS_EVR_WAIT OS_EVR_THREAD +#endif + +#ifdef _RTE_ +#include "RTE_Components.h" +#endif + +#ifdef RTE_Compiler_EventRecorder + +//lint -emacro((835,845),EventID) [MISRA Note 13] + +#include "EventRecorder.h" +#include "EventRecorderConf.h" + +#if ((defined(OS_EVR_INIT) && (OS_EVR_INIT != 0)) || (EVENT_TIMESTAMP_SOURCE == 2)) +#ifndef EVR_RTX_KERNEL_GET_STATE_DISABLE +#define EVR_RTX_KERNEL_GET_STATE_DISABLE +#endif +#endif + +#if (EVENT_TIMESTAMP_SOURCE == 2) +#ifndef EVR_RTX_KERNEL_GET_SYS_TIMER_COUNT_DISABLE +#define EVR_RTX_KERNEL_GET_SYS_TIMER_COUNT_DISABLE +#endif +#ifndef EVR_RTX_KERNEL_GET_SYS_TIMER_FREQ_DISABLE +#define EVR_RTX_KERNEL_GET_SYS_TIMER_FREQ_DISABLE +#endif +#endif + +/// RTOS component number +#define EvtRtxMemoryNo (0xF0U) +#define EvtRtxKernelNo (0xF1U) +#define EvtRtxThreadNo (0xF2U) +#define EvtRtxThreadFlagsNo (0xF4U) +#define EvtRtxWaitNo (0xF3U) +#define EvtRtxTimerNo (0xF6U) +#define EvtRtxEventFlagsNo (0xF5U) +#define EvtRtxMutexNo (0xF7U) +#define EvtRtxSemaphoreNo (0xF8U) +#define EvtRtxMemoryPoolNo (0xF9U) +#define EvtRtxMessageQueueNo (0xFAU) + +#endif // RTE_Compiler_EventRecorder + + +/// Extended Status codes +#define osRtxErrorKernelNotReady (-7) +#define osRtxErrorKernelNotRunning (-8) +#define osRtxErrorInvalidControlBlock (-9) +#define osRtxErrorInvalidDataMemory (-10) +#define osRtxErrorInvalidThreadStack (-11) +#define osRtxErrorInvalidPriority (-12) +#define osRtxErrorThreadNotJoinable (-13) +#define osRtxErrorMutexNotOwned (-14) +#define osRtxErrorMutexNotLocked (-15) +#define osRtxErrorMutexLockLimit (-16) +#define osRtxErrorSemaphoreCountLimit (-17) +#define osRtxErrorTZ_InitContext_S (-18) +#define osRtxErrorTZ_AllocContext_S (-19) +#define osRtxErrorTZ_FreeContext_S (-20) +#define osRtxErrorTZ_LoadContext_S (-21) +#define osRtxErrorTZ_SaveContext_S (-22) + + +// ==== Memory Events ==== + +/** + \brief Event on memory initialization (Op) + \param[in] mem pointer to memory pool. + \param[in] size size of a memory pool in bytes. + \param[in] result execution status: 1 - success, 0 - failure. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_INIT_DISABLE)) +extern void EvrRtxMemoryInit (void *mem, uint32_t size, uint32_t result); +#else +#define EvrRtxMemoryInit(mem, size, result) +#endif + +/** + \brief Event on memory allocate (Op) + \param[in] mem pointer to memory pool. + \param[in] size size of a memory block in bytes. + \param[in] type memory block type: 0 - generic, 1 - control block. + \param[in] block pointer to allocated memory block or NULL in case of no memory is available. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_ALLOC_DISABLE)) +extern void EvrRtxMemoryAlloc (void *mem, uint32_t size, uint32_t type, void *block); +#else +#define EvrRtxMemoryAlloc(mem, size, type, block) +#endif + +/** + \brief Event on memory free (Op) + \param[in] mem pointer to memory pool. + \param[in] block memory block to be returned to the memory pool. + \param[in] result execution status: 1 - success, 0 - failure. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_FREE_DISABLE)) +extern void EvrRtxMemoryFree (void *mem, void *block, uint32_t result); +#else +#define EvrRtxMemoryFree(mem, block, result) +#endif + +/** + \brief Event on memory block initialization (Op) + \param[in] mp_info memory pool info. + \param[in] block_count maximum number of memory blocks in memory pool. + \param[in] block_size size of a memory block in bytes. + \param[in] block_mem pointer to memory for block storage. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_BLOCK_INIT_DISABLE)) +extern void EvrRtxMemoryBlockInit (osRtxMpInfo_t *mp_info, uint32_t block_count, uint32_t block_size, void *block_mem); +#else +#define EvrRtxMemoryBlockInit(mp_info, block_count, block_size, block_mem) +#endif + +/** + \brief Event on memory block alloc (Op) + \param[in] mp_info memory pool info. + \param[in] block address of the allocated memory block or NULL in case of no memory is available. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_BLOCK_ALLOC_DISABLE)) +extern void EvrRtxMemoryBlockAlloc (osRtxMpInfo_t *mp_info, void *block); +#else +#define EvrRtxMemoryBlockAlloc(mp_info, block) +#endif + +/** + \brief Event on memory block free (Op) + \param[in] mp_info memory pool info. + \param[in] block address of the allocated memory block to be returned to the memory pool. + \param[in] status extended execution status. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_BLOCK_FREE_DISABLE)) +extern void EvrRtxMemoryBlockFree (osRtxMpInfo_t *mp_info, void *block, int32_t status); +#else +#define EvrRtxMemoryBlockFree(mp_info, block, status) +#endif + + +// ==== Kernel Events ==== + +/** + \brief Event on RTOS kernel error (Error) + \param[in] status extended execution status. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_ERROR_DISABLE)) +extern void EvrRtxKernelError (int32_t status); +#else +#define EvrRtxKernelError(status) +#endif + +/** + \brief Event on RTOS kernel initialize (API) +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_INITIALIZE_DISABLE)) +extern void EvrRtxKernelInitialize (void); +#else +#define EvrRtxKernelInitialize() +#endif + +/** + \brief Event on successful RTOS kernel initialize (Op) +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_INITIALIZED_DISABLE)) +extern void EvrRtxKernelInitialized (void); +#else +#define EvrRtxKernelInitialized() +#endif + +/** + \brief Event on RTOS kernel information retrieve (API) + \param[in] version pointer to buffer for retrieving version information. + \param[in] id_buf pointer to buffer for retrieving kernel identification string. + \param[in] id_size size of buffer for kernel identification string. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_INFO_DISABLE)) +extern void EvrRtxKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size); +#else +#define EvrRtxKernelGetInfo(version, id_buf, id_size) +#endif + +/** + \brief Event on successful RTOS kernel information retrieve (Op) + \param[in] version pointer to buffer for retrieving version information. + \param[in] id_buf pointer to buffer for retrieving kernel identification string. + \param[in] id_size size of buffer for kernel identification string. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_INFO_RETRIEVED_DISABLE)) +extern void EvrRtxKernelInfoRetrieved (const osVersion_t *version, const char *id_buf, uint32_t id_size); +#else +#define EvrRtxKernelInfoRetrieved(version, id_buf, id_size) +#endif + +/** + \brief Event on current RTOS Kernel state retrieve (API) + \param[in] state current RTOS Kernel state. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_STATE_DISABLE)) +extern void EvrRtxKernelGetState (osKernelState_t state); +#else +#define EvrRtxKernelGetState(state) +#endif + +/** + \brief Event on RTOS Kernel scheduler start (API) +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_START_DISABLE)) +extern void EvrRtxKernelStart (void); +#else +#define EvrRtxKernelStart() +#endif + +/** + \brief Event on successful RTOS Kernel scheduler start (Op) +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_STARTED_DISABLE)) +extern void EvrRtxKernelStarted (void); +#else +#define EvrRtxKernelStarted() +#endif + +/** + \brief Event on RTOS Kernel scheduler lock (API) +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_LOCK_DISABLE)) +extern void EvrRtxKernelLock (void); +#else +#define EvrRtxKernelLock() +#endif + +/** + \brief Event on successful RTOS Kernel scheduler lock (Op) + \param[in] lock previous lock state (1 - locked, 0 - not locked). +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_LOCKED_DISABLE)) +extern void EvrRtxKernelLocked (int32_t lock); +#else +#define EvrRtxKernelLocked(lock) +#endif + +/** + \brief Event on RTOS Kernel scheduler unlock (API) +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_UNLOCK_DISABLE)) +extern void EvrRtxKernelUnlock (void); +#else +#define EvrRtxKernelUnlock() +#endif + +/** + \brief Event on successful RTOS Kernel scheduler unlock (Op) + \param[in] lock previous lock state (1 - locked, 0 - not locked). +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_UNLOCKED_DISABLE)) +extern void EvrRtxKernelUnlocked (int32_t lock); +#else +#define EvrRtxKernelUnlocked(lock) +#endif + +/** + \brief Event on RTOS Kernel scheduler lock state restore (API) + \param[in] lock lock state obtained by \ref osKernelLock or \ref osKernelUnlock. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_RESTORE_LOCK_DISABLE)) +extern void EvrRtxKernelRestoreLock (int32_t lock); +#else +#define EvrRtxKernelRestoreLock(lock) +#endif + +/** + \brief Event on successful RTOS Kernel scheduler lock state restore (Op) + \param[in] lock new lock state (1 - locked, 0 - not locked). +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_LOCK_RESTORED_DISABLE)) +extern void EvrRtxKernelLockRestored (int32_t lock); +#else +#define EvrRtxKernelLockRestored(lock) +#endif + +/** + \brief Event on RTOS Kernel scheduler suspend (API) +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_SUSPEND_DISABLE)) +extern void EvrRtxKernelSuspend (void); +#else +#define EvrRtxKernelSuspend() +#endif + +/** + \brief Event on successful RTOS Kernel scheduler suspend (Op) + \param[in] sleep_ticks time in ticks, for how long the system can sleep or power-down. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_SUSPENDED_DISABLE)) +extern void EvrRtxKernelSuspended (uint32_t sleep_ticks); +#else +#define EvrRtxKernelSuspended(sleep_ticks) +#endif + +/** + \brief Event on RTOS Kernel scheduler resume (API) + \param[in] sleep_ticks time in ticks, for how long the system was in sleep or power-down mode. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_RESUME_DISABLE)) +extern void EvrRtxKernelResume (uint32_t sleep_ticks); +#else +#define EvrRtxKernelResume(sleep_ticks) +#endif + +/** + \brief Event on successful RTOS Kernel scheduler resume (Op) +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_RESUMED_DISABLE)) +extern void EvrRtxKernelResumed (void); +#else +#define EvrRtxKernelResumed() +#endif + +/** + \brief Event on RTOS kernel tick count retrieve (API) + \param[in] count RTOS kernel current tick count. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_TICK_COUNT_DISABLE)) +extern void EvrRtxKernelGetTickCount (uint32_t count); +#else +#define EvrRtxKernelGetTickCount(count) +#endif + +/** + \brief Event on RTOS kernel tick frequency retrieve (API) + \param[in] freq frequency of the kernel tick. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_TICK_FREQ_DISABLE)) +extern void EvrRtxKernelGetTickFreq (uint32_t freq); +#else +#define EvrRtxKernelGetTickFreq(freq) +#endif + +/** + \brief Event on RTOS kernel system timer count retrieve (API) + \param[in] count RTOS kernel current system timer count as 32-bit value. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_SYS_TIMER_COUNT_DISABLE)) +extern void EvrRtxKernelGetSysTimerCount (uint32_t count); +#else +#define EvrRtxKernelGetSysTimerCount(count) +#endif + +/** + \brief Event on RTOS kernel system timer frequency retrieve (API) + \param[in] freq frequency of the system timer. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_SYS_TIMER_FREQ_DISABLE)) +extern void EvrRtxKernelGetSysTimerFreq (uint32_t freq); +#else +#define EvrRtxKernelGetSysTimerFreq(freq) +#endif + +/** + \brief Event on RTOS kernel system error (Error) + \param[in] code error code. + \param[in] object_id object that caused the error. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_ERROR_NOTIFY_DISABLE)) +extern void EvrRtxKernelErrorNotify (uint32_t code, void *object_id); +#else +#define EvrRtxKernelErrorNotify(code, object_id) +#endif + + +// ==== Thread Events ==== + +/** + \brief Event on thread error (Error) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId or NULL when ID is unknown. + \param[in] status extended execution status. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_ERROR_DISABLE)) +extern void EvrRtxThreadError (osThreadId_t thread_id, int32_t status); +#else +#define EvrRtxThreadError(thread_id, status) +#endif + +/** + \brief Event on thread create and intialize (API) + \param[in] func thread function. + \param[in] argument pointer that is passed to the thread function as start argument. + \param[in] attr thread attributes. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_NEW_DISABLE)) +extern void EvrRtxThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr); +#else +#define EvrRtxThreadNew(func, argument, attr) +#endif + +/** + \brief Event on successful thread create (Op) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. + \param[in] thread_addr thread entry address. + \param[in] name pointer to thread object name. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_CREATED_DISABLE)) +extern void EvrRtxThreadCreated (osThreadId_t thread_id, uint32_t thread_addr, const char *name); +#else +#define EvrRtxThreadCreated(thread_id, thread_addr, name) +#endif + +/** + \brief Event on thread name retrieve (API) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. + \param[in] name pointer to thread object name. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_NAME_DISABLE)) +extern void EvrRtxThreadGetName (osThreadId_t thread_id, const char *name); +#else +#define EvrRtxThreadGetName(thread_id, name) +#endif + +/** + \brief Event on current running thread ID retrieve (API) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_ID_DISABLE)) +extern void EvrRtxThreadGetId (osThreadId_t thread_id); +#else +#define EvrRtxThreadGetId(thread_id) +#endif + +/** + \brief Event on thread state retrieve (API) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. + \param[in] state current thread state of the specified thread. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_STATE_DISABLE)) +extern void EvrRtxThreadGetState (osThreadId_t thread_id, osThreadState_t state); +#else +#define EvrRtxThreadGetState(thread_id, state) +#endif + +/** + \brief Event on thread stack size retrieve (API) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. + \param[in] stack_size stack size in bytes. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_STACK_SIZE_DISABLE)) +extern void EvrRtxThreadGetStackSize (osThreadId_t thread_id, uint32_t stack_size); +#else +#define EvrRtxThreadGetStackSize(thread_id, stack_size) +#endif + +/** + \brief Event on available stack space retrieve (API) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. + \param[in] stack_space remaining stack space in bytes. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_STACK_SPACE_DISABLE)) +extern void EvrRtxThreadGetStackSpace (osThreadId_t thread_id, uint32_t stack_space); +#else +#define EvrRtxThreadGetStackSpace(thread_id, stack_space) +#endif + +/** + \brief Event on thread priority set (API) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. + \param[in] priority new priority value for the thread function. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SET_PRIORITY_DISABLE)) +extern void EvrRtxThreadSetPriority (osThreadId_t thread_id, osPriority_t priority); +#else +#define EvrRtxThreadSetPriority(thread_id, priority) +#endif + +/** + \brief Event on thread priority updated (Op) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. + \param[in] priority new priority value for the thread function. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_PRIORITY_UPDATED_DISABLE)) +extern void EvrRtxThreadPriorityUpdated (osThreadId_t thread_id, osPriority_t priority); +#else +#define EvrRtxThreadPriorityUpdated(thread_id, priority) +#endif + +/** + \brief Event on thread priority retrieve (API) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. + \param[in] priority current priority value of the specified thread. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_PRIORITY_DISABLE)) +extern void EvrRtxThreadGetPriority (osThreadId_t thread_id, osPriority_t priority); +#else +#define EvrRtxThreadGetPriority(thread_id, priority) +#endif + +/** + \brief Event on thread yield (API) +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_YIELD_DISABLE)) +extern void EvrRtxThreadYield (void); +#else +#define EvrRtxThreadYield() +#endif + +/** + \brief Event on thread suspend (API) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SUSPEND_DISABLE)) +extern void EvrRtxThreadSuspend (osThreadId_t thread_id); +#else +#define EvrRtxThreadSuspend(thread_id) +#endif + +/** + \brief Event on successful thread suspend (Op) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SUSPENDED_DISABLE)) +extern void EvrRtxThreadSuspended (osThreadId_t thread_id); +#else +#define EvrRtxThreadSuspended(thread_id) +#endif + +/** + \brief Event on thread resume (API) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_RESUME_DISABLE)) +extern void EvrRtxThreadResume (osThreadId_t thread_id); +#else +#define EvrRtxThreadResume(thread_id) +#endif + +/** + \brief Event on successful thread resume (Op) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_RESUMED_DISABLE)) +extern void EvrRtxThreadResumed (osThreadId_t thread_id); +#else +#define EvrRtxThreadResumed(thread_id) +#endif + +/** + \brief Event on thread detach (API) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DETACH_DISABLE)) +extern void EvrRtxThreadDetach (osThreadId_t thread_id); +#else +#define EvrRtxThreadDetach(thread_id) +#endif + +/** + \brief Event on successful thread detach (Op) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DETACHED_DISABLE)) +extern void EvrRtxThreadDetached (osThreadId_t thread_id); +#else +#define EvrRtxThreadDetached(thread_id) +#endif + +/** + \brief Event on thread join (API) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_JOIN_DISABLE)) +extern void EvrRtxThreadJoin (osThreadId_t thread_id); +#else +#define EvrRtxThreadJoin(thread_id) +#endif + +/** + \brief Event on pending thread join (Op) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_JOIN_PENDING_DISABLE)) +extern void EvrRtxThreadJoinPending (osThreadId_t thread_id); +#else +#define EvrRtxThreadJoinPending(thread_id) +#endif + +/** + \brief Event on successful thread join (Op) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_JOINED_DISABLE)) +extern void EvrRtxThreadJoined (osThreadId_t thread_id); +#else +#define EvrRtxThreadJoined(thread_id) +#endif + +/** + \brief Event on thread execution block (Detail) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. + \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_BLOCKED_DISABLE)) +extern void EvrRtxThreadBlocked (osThreadId_t thread_id, uint32_t timeout); +#else +#define EvrRtxThreadBlocked(thread_id, timeout) +#endif + +/** + \brief Event on thread execution unblock (Detail) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. + \param[in] ret_val extended execution status of the thread. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_UNBLOCKED_DISABLE)) +extern void EvrRtxThreadUnblocked (osThreadId_t thread_id, uint32_t ret_val); +#else +#define EvrRtxThreadUnblocked(thread_id, ret_val) +#endif + +/** + \brief Event on running thread pre-emption (Detail) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_PREEMPTED_DISABLE)) +extern void EvrRtxThreadPreempted (osThreadId_t thread_id); +#else +#define EvrRtxThreadPreempted(thread_id) +#endif + +/** + \brief Event on running thread switch (Op) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SWITCHED_DISABLE)) +extern void EvrRtxThreadSwitched (osThreadId_t thread_id); +#else +#define EvrRtxThreadSwitched(thread_id) +#endif + +/** + \brief Event on thread exit (API) +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_EXIT_DISABLE)) +extern void EvrRtxThreadExit (void); +#else +#define EvrRtxThreadExit() +#endif + +/** + \brief Event on thread terminate (API) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_TERMINATE_DISABLE)) +extern void EvrRtxThreadTerminate (osThreadId_t thread_id); +#else +#define EvrRtxThreadTerminate(thread_id) +#endif + +/** + \brief Event on successful thread terminate (Op) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DESTROYED_DISABLE)) +extern void EvrRtxThreadDestroyed (osThreadId_t thread_id); +#else +#define EvrRtxThreadDestroyed(thread_id) +#endif + +/** + \brief Event on active thread count retrieve (API) + \param[in] count number of active threads. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_COUNT_DISABLE)) +extern void EvrRtxThreadGetCount (uint32_t count); +#else +#define EvrRtxThreadGetCount(count) +#endif + +/** + \brief Event on active threads enumerate (API) + \param[in] thread_array pointer to array for retrieving thread IDs. + \param[in] array_items maximum number of items in array for retrieving thread IDs. + \param[in] count number of enumerated threads. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_ENUMERATE_DISABLE)) +extern void EvrRtxThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items, uint32_t count); +#else +#define EvrRtxThreadEnumerate(thread_array, array_items, count) +#endif + + +// ==== Thread Flags Events ==== + +/** + \brief Event on thread flags error (Error) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId or NULL when ID is unknown. + \param[in] status extended execution status. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_ERROR_DISABLE)) +extern void EvrRtxThreadFlagsError (osThreadId_t thread_id, int32_t status); +#else +#define EvrRtxThreadFlagsError(thread_id, status) +#endif + +/** + \brief Event on thread flags set (API) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. + \param[in] flags flags of the thread that shall be set. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_SET_DISABLE)) +extern void EvrRtxThreadFlagsSet (osThreadId_t thread_id, uint32_t flags); +#else +#define EvrRtxThreadFlagsSet(thread_id, flags) +#endif + +/** + \brief Event on successful thread flags set (Op) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. + \param[in] thread_flags thread flags after setting. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_SET_DONE_DISABLE)) +extern void EvrRtxThreadFlagsSetDone (osThreadId_t thread_id, uint32_t thread_flags); +#else +#define EvrRtxThreadFlagsSetDone(thread_id, thread_flags) +#endif + +/** + \brief Event on thread flags clear (API) + \param[in] flags flags of the thread that shall be cleared. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_CLEAR_DISABLE)) +extern void EvrRtxThreadFlagsClear (uint32_t flags); +#else +#define EvrRtxThreadFlagsClear(flags) +#endif + +/** + \brief Event on successful thread flags clear (Op) + \param[in] thread_flags thread flags before clearing. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_CLEAR_DONE_DISABLE)) +extern void EvrRtxThreadFlagsClearDone (uint32_t thread_flags); +#else +#define EvrRtxThreadFlagsClearDone(thread_flags) +#endif + +/** + \brief Event on thread flags retrieve (API) + \param[in] thread_flags current thread flags. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_GET_DISABLE)) +extern void EvrRtxThreadFlagsGet (uint32_t thread_flags); +#else +#define EvrRtxThreadFlagsGet(thread_flags) +#endif + +/** + \brief Event on wait for thread flags (API) + \param[in] flags flags to wait for. + \param[in] options flags options (osFlagsXxxx). + \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_DISABLE)) +extern void EvrRtxThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout); +#else +#define EvrRtxThreadFlagsWait(flags, options, timeout) +#endif + +/** + \brief Event on pending wait for thread flags (Op) + \param[in] flags flags to wait for. + \param[in] options flags options (osFlagsXxxx). + \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_PENDING_DISABLE)) +extern void EvrRtxThreadFlagsWaitPending (uint32_t flags, uint32_t options, uint32_t timeout); +#else +#define EvrRtxThreadFlagsWaitPending(flags, options, timeout) +#endif + +/** + \brief Event on wait timeout for thread flags (Op) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_TIMEOUT_DISABLE)) +extern void EvrRtxThreadFlagsWaitTimeout (osThreadId_t thread_id); +#else +#define EvrRtxThreadFlagsWaitTimeout(thread_id) +#endif + +/** + \brief Event on successful wait for thread flags (Op) + \param[in] flags flags to wait for. + \param[in] options flags options (osFlagsXxxx). + \param[in] thread_flags thread flags before clearing. + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_COMPLETED_DISABLE)) +extern void EvrRtxThreadFlagsWaitCompleted (uint32_t flags, uint32_t options, uint32_t thread_flags, osThreadId_t thread_id); +#else +#define EvrRtxThreadFlagsWaitCompleted(flags, options, thread_flags, thread_id) +#endif + +/** + \brief Event on unsuccessful wait for thread flags (Op) + \param[in] flags flags to wait for. + \param[in] options flags options (osFlagsXxxx). +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_NOT_COMPLETED_DISABLE)) +extern void EvrRtxThreadFlagsWaitNotCompleted (uint32_t flags, uint32_t options); +#else +#define EvrRtxThreadFlagsWaitNotCompleted(flags, options) +#endif + + +// ==== Generic Wait Events ==== + +/** + \brief Event on delay error (Error) + \param[in] status extended execution status. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_ERROR_DISABLE)) +extern void EvrRtxDelayError (int32_t status); +#else +#define EvrRtxDelayError(status) +#endif + +/** + \brief Event on delay for specified time (API) + \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_DISABLE)) +extern void EvrRtxDelay (uint32_t ticks); +#else +#define EvrRtxDelay(ticks) +#endif + +/** + \brief Event on delay until specified time (API) + \param[in] ticks absolute time in ticks. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_UNTIL_DISABLE)) +extern void EvrRtxDelayUntil (uint32_t ticks); +#else +#define EvrRtxDelayUntil(ticks) +#endif + +/** + \brief Event on delay started (Op) + \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_STARTED_DISABLE)) +extern void EvrRtxDelayStarted (uint32_t ticks); +#else +#define EvrRtxDelayStarted(ticks) +#endif + +/** + \brief Event on delay until specified time started (Op) + \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_UNTIL_STARTED_DISABLE)) +extern void EvrRtxDelayUntilStarted (uint32_t ticks); +#else +#define EvrRtxDelayUntilStarted(ticks) +#endif + +/** + \brief Event on delay completed (Op) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_COMPLETED_DISABLE)) +extern void EvrRtxDelayCompleted (osThreadId_t thread_id); +#else +#define EvrRtxDelayCompleted(thread_id) +#endif + + +// ==== Timer Events ==== + +/** + \brief Event on timer error (Error) + \param[in] timer_id timer ID obtained by \ref osTimerNew or NULL when ID is unknown. + \param[in] status extended execution status. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_ERROR_DISABLE)) +extern void EvrRtxTimerError (osTimerId_t timer_id, int32_t status); +#else +#define EvrRtxTimerError(timer_id, status) +#endif + +/** + \brief Event on timer callback call (Op) + \param[in] func start address of a timer call back function. + \param[in] argument argument to the timer call back function. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_CALLBACK_DISABLE)) +extern void EvrRtxTimerCallback (osTimerFunc_t func, void *argument); +#else +#define EvrRtxTimerCallback(func, argument) +#endif + +/** + \brief Event on timer create and initialize (API) + \param[in] func start address of a timer call back function. + \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior. + \param[in] argument argument to the timer call back function. + \param[in] attr timer attributes. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_NEW_DISABLE)) +extern void EvrRtxTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr); +#else +#define EvrRtxTimerNew(func, type, argument, attr) +#endif + +/** + \brief Event on successful timer create (Op) + \param[in] timer_id timer ID obtained by \ref osTimerNew. + \param[in] name pointer to timer object name. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_CREATED_DISABLE)) +extern void EvrRtxTimerCreated (osTimerId_t timer_id, const char *name); +#else +#define EvrRtxTimerCreated(timer_id, name) +#endif + +/** + \brief Event on timer name retrieve (API) + \param[in] timer_id timer ID obtained by \ref osTimerNew. + \param[in] name pointer to timer object name. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_GET_NAME_DISABLE)) +extern void EvrRtxTimerGetName (osTimerId_t timer_id, const char *name); +#else +#define EvrRtxTimerGetName(timer_id, name) +#endif + +/** + \brief Event on timer start (API) + \param[in] timer_id timer ID obtained by \ref osTimerNew. + \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value of the timer. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_START_DISABLE)) +extern void EvrRtxTimerStart (osTimerId_t timer_id, uint32_t ticks); +#else +#define EvrRtxTimerStart(timer_id, ticks) +#endif + +/** + \brief Event on successful timer start (Op) + \param[in] timer_id timer ID obtained by \ref osTimerNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_STARTED_DISABLE)) +extern void EvrRtxTimerStarted (osTimerId_t timer_id); +#else +#define EvrRtxTimerStarted(timer_id) +#endif + +/** + \brief Event on timer stop (API) + \param[in] timer_id timer ID obtained by \ref osTimerNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_STOP_DISABLE)) +extern void EvrRtxTimerStop (osTimerId_t timer_id); +#else +#define EvrRtxTimerStop(timer_id) +#endif + +/** + \brief Event on successful timer stop (Op) + \param[in] timer_id timer ID obtained by \ref osTimerNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_STOPPED_DISABLE)) +extern void EvrRtxTimerStopped (osTimerId_t timer_id); +#else +#define EvrRtxTimerStopped(timer_id) +#endif + +/** + \brief Event on timer running state check (API) + \param[in] timer_id timer ID obtained by \ref osTimerNew. + \param[in] running running state: 0 not running, 1 running. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_IS_RUNNING_DISABLE)) +extern void EvrRtxTimerIsRunning (osTimerId_t timer_id, uint32_t running); +#else +#define EvrRtxTimerIsRunning(timer_id, running) +#endif + +/** + \brief Event on timer delete (API) + \param[in] timer_id timer ID obtained by \ref osTimerNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_DELETE_DISABLE)) +extern void EvrRtxTimerDelete (osTimerId_t timer_id); +#else +#define EvrRtxTimerDelete(timer_id) +#endif + +/** + \brief Event on successful timer delete (Op) + \param[in] timer_id timer ID obtained by \ref osTimerNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_DESTROYED_DISABLE)) +extern void EvrRtxTimerDestroyed (osTimerId_t timer_id); +#else +#define EvrRtxTimerDestroyed(timer_id) +#endif + + +// ==== Event Flags Events ==== + +/** + \brief Event on event flags error (Error) + \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew or NULL when ID is unknown. + \param[in] status extended execution status. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_ERROR_DISABLE)) +extern void EvrRtxEventFlagsError (osEventFlagsId_t ef_id, int32_t status); +#else +#define EvrRtxEventFlagsError(ef_id, status) +#endif + +/** + \brief Event on event flags create and initialize (API) + \param[in] attr event flags attributes. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_NEW_DISABLE)) +extern void EvrRtxEventFlagsNew (const osEventFlagsAttr_t *attr); +#else +#define EvrRtxEventFlagsNew(attr) +#endif + +/** + \brief Event on successful event flags create (Op) + \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. + \param[in] name pointer to event flags object name. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_CREATED_DISABLE)) +extern void EvrRtxEventFlagsCreated (osEventFlagsId_t ef_id, const char *name); +#else +#define EvrRtxEventFlagsCreated(ef_id, name) +#endif + +/** + \brief Event on event flags name retrieve (API) + \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. + \param[in] name pointer to event flags object name. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_GET_NAME_DISABLE)) +extern void EvrRtxEventFlagsGetName (osEventFlagsId_t ef_id, const char *name); +#else +#define EvrRtxEventFlagsGetName(ef_id, name) +#endif + +/** + \brief Event on event flags set (API) + \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. + \param[in] flags flags that shall be set. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_SET_DISABLE)) +extern void EvrRtxEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags); +#else +#define EvrRtxEventFlagsSet(ef_id, flags) +#endif + +/** + \brief Event on successful event flags set (Op) + \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. + \param[in] event_flags event flags after setting. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_SET_DONE_DISABLE)) +extern void EvrRtxEventFlagsSetDone (osEventFlagsId_t ef_id, uint32_t event_flags); +#else +#define EvrRtxEventFlagsSetDone(ef_id, event_flags) +#endif + +/** + \brief Event on event flags clear (API) + \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. + \param[in] flags flags that shall be cleared. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_CLEAR_DISABLE)) +extern void EvrRtxEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags); +#else +#define EvrRtxEventFlagsClear(ef_id, flags) +#endif + +/** + \brief Event on successful event flags clear (Op) + \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. + \param[in] event_flags event flags before clearing. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_CLEAR_DONE_DISABLE)) +extern void EvrRtxEventFlagsClearDone (osEventFlagsId_t ef_id, uint32_t event_flags); +#else +#define EvrRtxEventFlagsClearDone(ef_id, event_flags) +#endif + +/** + \brief Event on event flags retrieve (API) + \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. + \param[in] event_flags current event flags. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_GET_DISABLE)) +extern void EvrRtxEventFlagsGet (osEventFlagsId_t ef_id, uint32_t event_flags); +#else +#define EvrRtxEventFlagsGet(ef_id, event_flags) +#endif + +/** + \brief Event on wait for event flags (API) + \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. + \param[in] flags flags to wait for. + \param[in] options flags options (osFlagsXxxx). + \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_DISABLE)) +extern void EvrRtxEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout); +#else +#define EvrRtxEventFlagsWait(ef_id, flags, options, timeout) +#endif + +/** + \brief Event on pending wait for event flags (Op) + \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. + \param[in] flags flags to wait for. + \param[in] options flags options (osFlagsXxxx). + \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_PENDING_DISABLE)) +extern void EvrRtxEventFlagsWaitPending (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout); +#else +#define EvrRtxEventFlagsWaitPending(ef_id, flags, options, timeout) +#endif + +/** + \brief Event on wait timeout for event flags (Op) + \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_TIMEOUT_DISABLE)) +extern void EvrRtxEventFlagsWaitTimeout (osEventFlagsId_t ef_id); +#else +#define EvrRtxEventFlagsWaitTimeout(ef_id) +#endif + +/** + \brief Event on successful wait for event flags (Op) + \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. + \param[in] flags flags to wait for. + \param[in] options flags options (osFlagsXxxx). + \param[in] event_flags event flags before clearing or 0 if specified flags have not been set. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_COMPLETED_DISABLE)) +extern void EvrRtxEventFlagsWaitCompleted (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t event_flags); +#else +#define EvrRtxEventFlagsWaitCompleted(ef_id, flags, options, event_flags) +#endif + +/** + \brief Event on unsuccessful wait for event flags (Op) + \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. + \param[in] flags flags to wait for. + \param[in] options flags options (osFlagsXxxx). +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_NOT_COMPLETED_DISABLE)) +extern void EvrRtxEventFlagsWaitNotCompleted (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options); +#else +#define EvrRtxEventFlagsWaitNotCompleted(ef_id, flags, options) +#endif + +/** + \brief Event on event flags delete (API) + \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_DELETE_DISABLE)) +extern void EvrRtxEventFlagsDelete (osEventFlagsId_t ef_id); +#else +#define EvrRtxEventFlagsDelete(ef_id) +#endif + +/** + \brief Event on successful event flags delete (Op) + \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_DESTROYED_DISABLE)) +extern void EvrRtxEventFlagsDestroyed (osEventFlagsId_t ef_id); +#else +#define EvrRtxEventFlagsDestroyed(ef_id) +#endif + + +// ==== Mutex Events ==== + +/** + \brief Event on mutex error (Error) + \param[in] mutex_id mutex ID obtained by \ref osMutexNew or NULL when ID is unknown. + \param[in] status extended execution status. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ERROR_DISABLE)) +extern void EvrRtxMutexError (osMutexId_t mutex_id, int32_t status); +#else +#define EvrRtxMutexError(mutex_id, status) +#endif + +/** + \brief Event on mutex create and initialize (API) + \param[in] attr mutex attributes. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_NEW_DISABLE)) +extern void EvrRtxMutexNew (const osMutexAttr_t *attr); +#else +#define EvrRtxMutexNew(attr) +#endif + +/** + \brief Event on successful mutex create (Op) + \param[in] mutex_id mutex ID obtained by \ref osMutexNew. + \param[in] name pointer to mutex object name. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_CREATED_DISABLE)) +extern void EvrRtxMutexCreated (osMutexId_t mutex_id, const char *name); +#else +#define EvrRtxMutexCreated(mutex_id, name) +#endif + +/** + \brief Event on mutex name retrieve (API) + \param[in] mutex_id mutex ID obtained by \ref osMutexNew. + \param[in] name pointer to mutex object name. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_GET_NAME_DISABLE)) +extern void EvrRtxMutexGetName (osMutexId_t mutex_id, const char *name); +#else +#define EvrRtxMutexGetName(mutex_id, name) +#endif + +/** + \brief Event on mutex acquire (API) + \param[in] mutex_id mutex ID obtained by \ref osMutexNew. + \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRE_DISABLE)) +extern void EvrRtxMutexAcquire (osMutexId_t mutex_id, uint32_t timeout); +#else +#define EvrRtxMutexAcquire(mutex_id, timeout) +#endif + +/** + \brief Event on pending mutex acquire (Op) + \param[in] mutex_id mutex ID obtained by \ref osMutexNew. + \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRE_PENDING_DISABLE)) +extern void EvrRtxMutexAcquirePending (osMutexId_t mutex_id, uint32_t timeout); +#else +#define EvrRtxMutexAcquirePending(mutex_id, timeout) +#endif + +/** + \brief Event on mutex acquire timeout (Op) + \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRE_TIMEOUT_DISABLE)) +extern void EvrRtxMutexAcquireTimeout (osMutexId_t mutex_id); +#else +#define EvrRtxMutexAcquireTimeout(mutex_id) +#endif + +/** + \brief Event on successful mutex acquire (Op) + \param[in] mutex_id mutex ID obtained by \ref osMutexNew. + \param[in] lock current number of times mutex object is locked. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRED_DISABLE)) +extern void EvrRtxMutexAcquired (osMutexId_t mutex_id, uint32_t lock); +#else +#define EvrRtxMutexAcquired(mutex_id, lock) +#endif + +/** + \brief Event on unsuccessful mutex acquire (Op) + \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_NOT_ACQUIRED_DISABLE)) +extern void EvrRtxMutexNotAcquired (osMutexId_t mutex_id); +#else +#define EvrRtxMutexNotAcquired(mutex_id) +#endif + +/** + \brief Event on mutex release (API) + \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_RELEASE_DISABLE)) +extern void EvrRtxMutexRelease (osMutexId_t mutex_id); +#else +#define EvrRtxMutexRelease(mutex_id) +#endif + +/** + \brief Event on successful mutex release (Op) + \param[in] mutex_id mutex ID obtained by \ref osMutexNew. + \param[in] lock current number of times mutex object is locked. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_RELEASED_DISABLE)) +extern void EvrRtxMutexReleased (osMutexId_t mutex_id, uint32_t lock); +#else +#define EvrRtxMutexReleased(mutex_id, lock) +#endif + +/** + \brief Event on mutex owner retrieve (API) + \param[in] mutex_id mutex ID obtained by \ref osMutexNew. + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_GET_OWNER_DISABLE)) +extern void EvrRtxMutexGetOwner (osMutexId_t mutex_id, osThreadId_t thread_id); +#else +#define EvrRtxMutexGetOwner(mutex_id, thread_id) +#endif + +/** + \brief Event on mutex delete (API) + \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_DELETE_DISABLE)) +extern void EvrRtxMutexDelete (osMutexId_t mutex_id); +#else +#define EvrRtxMutexDelete(mutex_id) +#endif + +/** + \brief Event on successful mutex delete (Op) + \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_DESTROYED_DISABLE)) +extern void EvrRtxMutexDestroyed (osMutexId_t mutex_id); +#else +#define EvrRtxMutexDestroyed(mutex_id) +#endif + + +// ==== Semaphore Events ==== + +/** + \brief Event on semaphore error (Error) + \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew or NULL when ID is unknown. + \param[in] status extended execution status. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ERROR_DISABLE)) +extern void EvrRtxSemaphoreError (osSemaphoreId_t semaphore_id, int32_t status); +#else +#define EvrRtxSemaphoreError(semaphore_id, status) +#endif + +/** + \brief Event on semaphore create and initialize (API) + \param[in] max_count maximum number of available tokens. + \param[in] initial_count initial number of available tokens. + \param[in] attr semaphore attributes. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_NEW_DISABLE)) +extern void EvrRtxSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr); +#else +#define EvrRtxSemaphoreNew(max_count, initial_count, attr) +#endif + +/** + \brief Event on successful semaphore create (Op) + \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. + \param[in] name pointer to semaphore object name. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_CREATED_DISABLE)) +extern void EvrRtxSemaphoreCreated (osSemaphoreId_t semaphore_id, const char *name); +#else +#define EvrRtxSemaphoreCreated(semaphore_id, name) +#endif + +/** + \brief Event on semaphore name retrieve (API) + \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. + \param[in] name pointer to semaphore object name. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_GET_NAME_DISABLE)) +extern void EvrRtxSemaphoreGetName (osSemaphoreId_t semaphore_id, const char *name); +#else +#define EvrRtxSemaphoreGetName(semaphore_id, name) +#endif + +/** + \brief Event on semaphore acquire (API) + \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. + \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRE_DISABLE)) +extern void EvrRtxSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout); +#else +#define EvrRtxSemaphoreAcquire(semaphore_id, timeout) +#endif + +/** + \brief Event on pending semaphore acquire (Op) + \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. + \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRE_PENDING_DISABLE)) +extern void EvrRtxSemaphoreAcquirePending (osSemaphoreId_t semaphore_id, uint32_t timeout); +#else +#define EvrRtxSemaphoreAcquirePending(semaphore_id, timeout) +#endif + +/** + \brief Event on semaphore acquire timeout (Op) + \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRE_TIMEOUT_DISABLE)) +extern void EvrRtxSemaphoreAcquireTimeout (osSemaphoreId_t semaphore_id); +#else +#define EvrRtxSemaphoreAcquireTimeout(semaphore_id) +#endif + +/** + \brief Event on successful semaphore acquire (Op) + \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. + \param[in] tokens number of available tokens. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRED_DISABLE)) +extern void EvrRtxSemaphoreAcquired (osSemaphoreId_t semaphore_id, uint32_t tokens); +#else +#define EvrRtxSemaphoreAcquired(semaphore_id, tokens) +#endif + +/** + \brief Event on unsuccessful semaphore acquire (Op) + \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_NOT_ACQUIRED_DISABLE)) +extern void EvrRtxSemaphoreNotAcquired (osSemaphoreId_t semaphore_id); +#else +#define EvrRtxSemaphoreNotAcquired(semaphore_id) +#endif + +/** + \brief Event on semaphore release (API) + \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_RELEASE_DISABLE)) +extern void EvrRtxSemaphoreRelease (osSemaphoreId_t semaphore_id); +#else +#define EvrRtxSemaphoreRelease(semaphore_id) +#endif + +/** + \brief Event on successful semaphore release (Op) + \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. + \param[in] tokens number of available tokens. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_RELEASED_DISABLE)) +extern void EvrRtxSemaphoreReleased (osSemaphoreId_t semaphore_id, uint32_t tokens); +#else +#define EvrRtxSemaphoreReleased(semaphore_id, tokens) +#endif + +/** + \brief Event on semaphore token count retrieval (API) + \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. + \param[in] count current number of available tokens. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_GET_COUNT_DISABLE)) +extern void EvrRtxSemaphoreGetCount (osSemaphoreId_t semaphore_id, uint32_t count); +#else +#define EvrRtxSemaphoreGetCount(semaphore_id, count) +#endif + +/** + \brief Event on semaphore delete (API) + \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_DELETE_DISABLE)) +extern void EvrRtxSemaphoreDelete (osSemaphoreId_t semaphore_id); +#else +#define EvrRtxSemaphoreDelete(semaphore_id) +#endif + +/** + \brief Event on successful semaphore delete (Op) + \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_DESTROYED_DISABLE)) +extern void EvrRtxSemaphoreDestroyed (osSemaphoreId_t semaphore_id); +#else +#define EvrRtxSemaphoreDestroyed(semaphore_id) +#endif + + +// ==== Memory Pool Events ==== + +/** + \brief Event on memory pool error (Error) + \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew or NULL when ID is unknown. + \param[in] status extended execution status. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ERROR_DISABLE)) +extern void EvrRtxMemoryPoolError (osMemoryPoolId_t mp_id, int32_t status); +#else +#define EvrRtxMemoryPoolError(mp_id, status) +#endif + +/** + \brief Event on memory pool create and initialize (API) + \param[in] block_count maximum number of memory blocks in memory pool. + \param[in] block_size memory block size in bytes. + \param[in] attr memory pool attributes; NULL: default values. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_NEW_DISABLE)) +extern void EvrRtxMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr); +#else +#define EvrRtxMemoryPoolNew(block_count, block_size, attr) +#endif + +/** + \brief Event on successful memory pool create (Op) + \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. + \param[in] name pointer to memory pool object name. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_CREATED_DISABLE)) +extern void EvrRtxMemoryPoolCreated (osMemoryPoolId_t mp_id, const char *name); +#else +#define EvrRtxMemoryPoolCreated(mp_id, name) +#endif + +/** + \brief Event on memory pool name retrieve (API) + \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. + \param[in] name pointer to memory pool object name. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_NAME_DISABLE)) +extern void EvrRtxMemoryPoolGetName (osMemoryPoolId_t mp_id, const char *name); +#else +#define EvrRtxMemoryPoolGetName(mp_id, name) +#endif + +/** + \brief Event on memory pool allocation (API) + \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. + \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_DISABLE)) +extern void EvrRtxMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout); +#else +#define EvrRtxMemoryPoolAlloc(mp_id, timeout) +#endif + +/** + \brief Event on pending memory pool allocation (Op) + \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. + \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_PENDING_DISABLE)) +extern void EvrRtxMemoryPoolAllocPending (osMemoryPoolId_t mp_id, uint32_t timeout); +#else +#define EvrRtxMemoryPoolAllocPending(mp_id, timeout) +#endif + +/** + \brief Event on memory pool allocation timeout (Op) + \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_TIMEOUT_DISABLE)) +extern void EvrRtxMemoryPoolAllocTimeout (osMemoryPoolId_t mp_id); +#else +#define EvrRtxMemoryPoolAllocTimeout(mp_id) +#endif + +/** + \brief Event on successful memory pool allocation (Op) + \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. + \param[in] block address of the allocated memory block. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOCATED_DISABLE)) +extern void EvrRtxMemoryPoolAllocated (osMemoryPoolId_t mp_id, void *block); +#else +#define EvrRtxMemoryPoolAllocated(mp_id, block) +#endif + +/** + \brief Event on unsuccessful memory pool allocation (Op) + \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_FAILED_DISABLE)) +extern void EvrRtxMemoryPoolAllocFailed (osMemoryPoolId_t mp_id); +#else +#define EvrRtxMemoryPoolAllocFailed(mp_id) +#endif + +/** + \brief Event on memory pool free (API) + \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. + \param[in] block address of the allocated memory block to be returned to the memory pool. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_FREE_DISABLE)) +extern void EvrRtxMemoryPoolFree (osMemoryPoolId_t mp_id, void *block); +#else +#define EvrRtxMemoryPoolFree(mp_id, block) +#endif + +/** + \brief Event on successful memory pool free (Op) + \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. + \param[in] block address of the allocated memory block to be returned to the memory pool. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_DEALLOCATED_DISABLE)) +extern void EvrRtxMemoryPoolDeallocated (osMemoryPoolId_t mp_id, void *block); +#else +#define EvrRtxMemoryPoolDeallocated(mp_id, block) +#endif + +/** + \brief Event on unsuccessful memory pool free (Op) + \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. + \param[in] block address of the allocated memory block to be returned to the memory pool. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_FREE_FAILED_DISABLE)) +extern void EvrRtxMemoryPoolFreeFailed (osMemoryPoolId_t mp_id, void *block); +#else +#define EvrRtxMemoryPoolFreeFailed(mp_id, block) +#endif + +/** + \brief Event on memory pool capacity retrieve (API) + \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. + \param[in] capacity maximum number of memory blocks. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_CAPACITY_DISABLE)) +extern void EvrRtxMemoryPoolGetCapacity (osMemoryPoolId_t mp_id, uint32_t capacity); +#else +#define EvrRtxMemoryPoolGetCapacity(mp_id, capacity) +#endif + +/** + \brief Event on memory pool block size retrieve (API) + \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. + \param[in] block_size memory block size in bytes. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_BLOCK_SZIE_DISABLE)) +extern void EvrRtxMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id, uint32_t block_size); +#else +#define EvrRtxMemoryPoolGetBlockSize(mp_id, block_size) +#endif + +/** + \brief Event on used memory pool blocks retrieve (API) + \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. + \param[in] count number of memory blocks used. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_COUNT_DISABLE)) +extern void EvrRtxMemoryPoolGetCount (osMemoryPoolId_t mp_id, uint32_t count); +#else +#define EvrRtxMemoryPoolGetCount(mp_id, count) +#endif + +/** + \brief Event on available memory pool blocks retrieve (API) + \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. + \param[in] space number of memory blocks available. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_SPACE_DISABLE)) +extern void EvrRtxMemoryPoolGetSpace (osMemoryPoolId_t mp_id, uint32_t space); +#else +#define EvrRtxMemoryPoolGetSpace(mp_id, space) +#endif + +/** + \brief Event on memory pool delete (API) + \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_DELETE_DISABLE)) +extern void EvrRtxMemoryPoolDelete (osMemoryPoolId_t mp_id); +#else +#define EvrRtxMemoryPoolDelete(mp_id) +#endif + +/** + \brief Event on successful memory pool delete (Op) + \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_DESTROYED_DISABLE)) +extern void EvrRtxMemoryPoolDestroyed (osMemoryPoolId_t mp_id); +#else +#define EvrRtxMemoryPoolDestroyed(mp_id) +#endif + + +// ==== Message Queue Events ==== + +/** + \brief Event on message queue error (Error) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew or NULL when ID is unknown. + \param[in] status extended execution status. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_ERROR_DISABLE)) +extern void EvrRtxMessageQueueError (osMessageQueueId_t mq_id, int32_t status); +#else +#define EvrRtxMessageQueueError(mq_id, status) +#endif + +/** + \brief Event on message queue create and initialization (API) + \param[in] msg_count maximum number of messages in queue. + \param[in] msg_size maximum message size in bytes. + \param[in] attr message queue attributes; NULL: default values. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_NEW_DISABLE)) +extern void EvrRtxMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr); +#else +#define EvrRtxMessageQueueNew(msg_count, msg_size, attr) +#endif + +/** + \brief Event on successful message queue create (Op) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. + \param[in] name pointer to message queue object name. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_CREATED_DISABLE)) +extern void EvrRtxMessageQueueCreated (osMessageQueueId_t mq_id, const char *name); +#else +#define EvrRtxMessageQueueCreated(mq_id, name) +#endif + +/** + \brief Event on message queue name retrieve(API) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. + \param[in] name pointer to message queue object name. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_NAME_DISABLE)) +extern void EvrRtxMessageQueueGetName (osMessageQueueId_t mq_id, const char *name); +#else +#define EvrRtxMessageQueueGetName(mq_id, name) +#endif + +/** + \brief Event on message put (API) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. + \param[in] msg_ptr pointer to buffer with message to put into a queue. + \param[in] msg_prio message priority. + \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_PUT_DISABLE)) +extern void EvrRtxMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout); +#else +#define EvrRtxMessageQueuePut(mq_id, msg_ptr, msg_prio, timeout) +#endif + +/** + \brief Event on pending message put (Op) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. + \param[in] msg_ptr pointer to buffer with message to put into a queue. + \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_PUT_PENDING_DISABLE)) +extern void EvrRtxMessageQueuePutPending (osMessageQueueId_t mq_id, const void *msg_ptr, uint32_t timeout); +#else +#define EvrRtxMessageQueuePutPending(mq_id, msg_ptr, timeout) +#endif + +/** + \brief Event on message put timeout (Op) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_PUT_TIMEOUT_DISABLE)) +extern void EvrRtxMessageQueuePutTimeout (osMessageQueueId_t mq_id); +#else +#define EvrRtxMessageQueuePutTimeout(mq_id) +#endif + +/** + \brief Event on pending message insert (Op) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. + \param[in] msg_ptr pointer to buffer with message to put into a queue. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_INSERT_PENDING_DISABLE)) +extern void EvrRtxMessageQueueInsertPending (osMessageQueueId_t mq_id, const void *msg_ptr); +#else +#define EvrRtxMessageQueueInsertPending(mq_id, msg_ptr) +#endif + +/** + \brief Event on successful message insert (Op) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. + \param[in] msg_ptr pointer to buffer with message to put into a queue. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_INSERTED_DISABLE)) +extern void EvrRtxMessageQueueInserted (osMessageQueueId_t mq_id, const void *msg_ptr); +#else +#define EvrRtxMessageQueueInserted(mq_id, msg_ptr) +#endif + +/** + \brief Event on unsuccessful message insert (Op) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. + \param[in] msg_ptr pointer to buffer with message to put into a queue. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_NOT_INSERTED_DISABLE)) +extern void EvrRtxMessageQueueNotInserted (osMessageQueueId_t mq_id, const void *msg_ptr); +#else +#define EvrRtxMessageQueueNotInserted(mq_id, msg_ptr) +#endif + +/** + \brief Event on message get (API) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. + \param[in] msg_ptr pointer to buffer for message to get from a queue. + \param[in] msg_prio message priority. + \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_DISABLE)) +extern void EvrRtxMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout); +#else +#define EvrRtxMessageQueueGet(mq_id, msg_ptr, msg_prio, timeout) +#endif + +/** + \brief Event on pending message get (Op) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. + \param[in] msg_ptr pointer to buffer for message to get from a queue. + \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_PENDING_DISABLE)) +extern void EvrRtxMessageQueueGetPending (osMessageQueueId_t mq_id, void *msg_ptr, uint32_t timeout); +#else +#define EvrRtxMessageQueueGetPending(mq_id, msg_ptr, timeout) +#endif + +/** + \brief Event on message get timeout (Op) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_TIMEOUT_DISABLE)) +extern void EvrRtxMessageQueueGetTimeout (osMessageQueueId_t mq_id); +#else +#define EvrRtxMessageQueueGetTimeout(mq_id) +#endif + +/** + \brief Event on successful message get (Op) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. + \param[in] msg_ptr pointer to buffer for message to get from a queue. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_RETRIEVED_DISABLE)) +extern void EvrRtxMessageQueueRetrieved (osMessageQueueId_t mq_id, void *msg_ptr); +#else +#define EvrRtxMessageQueueRetrieved(mq_id, msg_ptr) +#endif + +/** + \brief Event on unsuccessful message get (Op) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. + \param[in] msg_ptr pointer to buffer for message to get from a queue. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_NOT_RETRIEVED_DISABLE)) +extern void EvrRtxMessageQueueNotRetrieved (osMessageQueueId_t mq_id, void *msg_ptr); +#else +#define EvrRtxMessageQueueNotRetrieved(mq_id, msg_ptr) +#endif + +/** + \brief Event on message queue capacity retrieve (API) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. + \param[in] capacity maximum number of messages. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_CAPACITY_DISABLE)) +extern void EvrRtxMessageQueueGetCapacity (osMessageQueueId_t mq_id, uint32_t capacity); +#else +#define EvrRtxMessageQueueGetCapacity(mq_id, capacity) +#endif + +/** + \brief Event on message queue message size retrieve (API) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. + \param[in] msg_size maximum message size in bytes. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_MSG_SIZE_DISABLE)) +extern void EvrRtxMessageQueueGetMsgSize (osMessageQueueId_t mq_id, uint32_t msg_size); +#else +#define EvrRtxMessageQueueGetMsgSize(mq_id, msg_size) +#endif + +/** + \brief Event on message queue message count retrieve (API) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. + \param[in] count number of queued messages. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_COUNT_DISABLE)) +extern void EvrRtxMessageQueueGetCount (osMessageQueueId_t mq_id, uint32_t count); +#else +#define EvrRtxMessageQueueGetCount(mq_id, count) +#endif + +/** + \brief Event on message queue message slots retrieve (API) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. + \param[in] space number of available slots for messages. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_SPACE_DISABLE)) +extern void EvrRtxMessageQueueGetSpace (osMessageQueueId_t mq_id, uint32_t space); +#else +#define EvrRtxMessageQueueGetSpace(mq_id, space) +#endif + +/** + \brief Event on message queue reset (API) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_RESET_DISABLE)) +extern void EvrRtxMessageQueueReset (osMessageQueueId_t mq_id); +#else +#define EvrRtxMessageQueueReset(mq_id) +#endif + +/** + \brief Event on successful message queue reset (Op) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_RESET_DONE_DISABLE)) +extern void EvrRtxMessageQueueResetDone (osMessageQueueId_t mq_id); +#else +#define EvrRtxMessageQueueResetDone(mq_id) +#endif + +/** + \brief Event on message queue delete (API) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_DELETE_DISABLE)) +extern void EvrRtxMessageQueueDelete (osMessageQueueId_t mq_id); +#else +#define EvrRtxMessageQueueDelete(mq_id) +#endif + +/** + \brief Event on successful message queue delete (Op) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_DESTROYED_DISABLE)) +extern void EvrRtxMessageQueueDestroyed (osMessageQueueId_t mq_id); +#else +#define EvrRtxMessageQueueDestroyed(mq_id) +#endif + + +#endif // RTX_EVR_H_ diff --git a/CMSIS/RTOS2/RTX/Include/rtx_os.h b/CMSIS/RTOS2/RTX/Include/rtx_os.h new file mode 100644 index 0000000..65e4227 --- /dev/null +++ b/CMSIS/RTOS2/RTX/Include/rtx_os.h @@ -0,0 +1,477 @@ +/* + * Copyright (c) 2013-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: RTX OS definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_OS_H_ +#define RTX_OS_H_ + +#include +#include +#include "cmsis_os2.h" +#include "rtx_def.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/// Kernel Information +#define osRtxVersionAPI 20010003 ///< API version (2.1.3) +#define osRtxVersionKernel 50050003 ///< Kernel version (5.5.3) +#define osRtxKernelId "RTX V5.5.3" ///< Kernel identification string + + +// ==== Common definitions ==== + +/// Object Identifier definitions +#define osRtxIdInvalid 0x00U +#define osRtxIdThread 0xF1U +#define osRtxIdTimer 0xF2U +#define osRtxIdEventFlags 0xF3U +#define osRtxIdMutex 0xF5U +#define osRtxIdSemaphore 0xF6U +#define osRtxIdMemoryPool 0xF7U +#define osRtxIdMessage 0xF9U +#define osRtxIdMessageQueue 0xFAU + +/// Object Flags definitions +#define osRtxFlagSystemObject 0x01U +#define osRtxFlagSystemMemory 0x02U + + +// ==== Kernel definitions ==== + +/// Kernel State definitions +#define osRtxKernelInactive ((uint8_t)osKernelInactive) +#define osRtxKernelReady ((uint8_t)osKernelReady) +#define osRtxKernelRunning ((uint8_t)osKernelRunning) +#define osRtxKernelLocked ((uint8_t)osKernelLocked) +#define osRtxKernelSuspended ((uint8_t)osKernelSuspended) + + +// ==== Thread definitions ==== + +/// Thread State definitions (extending osThreadState) +#define osRtxThreadStateMask 0x0FU + +#define osRtxThreadInactive ((uint8_t)osThreadInactive) +#define osRtxThreadReady ((uint8_t)osThreadReady) +#define osRtxThreadRunning ((uint8_t)osThreadRunning) +#define osRtxThreadBlocked ((uint8_t)osThreadBlocked) +#define osRtxThreadTerminated ((uint8_t)osThreadTerminated) + +#define osRtxThreadWaitingDelay ((uint8_t)(osRtxThreadBlocked | 0x10U)) +#define osRtxThreadWaitingJoin ((uint8_t)(osRtxThreadBlocked | 0x20U)) +#define osRtxThreadWaitingThreadFlags ((uint8_t)(osRtxThreadBlocked | 0x30U)) +#define osRtxThreadWaitingEventFlags ((uint8_t)(osRtxThreadBlocked | 0x40U)) +#define osRtxThreadWaitingMutex ((uint8_t)(osRtxThreadBlocked | 0x50U)) +#define osRtxThreadWaitingSemaphore ((uint8_t)(osRtxThreadBlocked | 0x60U)) +#define osRtxThreadWaitingMemoryPool ((uint8_t)(osRtxThreadBlocked | 0x70U)) +#define osRtxThreadWaitingMessageGet ((uint8_t)(osRtxThreadBlocked | 0x80U)) +#define osRtxThreadWaitingMessagePut ((uint8_t)(osRtxThreadBlocked | 0x90U)) + +/// Thread Flags definitions +#define osRtxThreadFlagDefStack 0x10U ///< Default Stack flag + +/// Stack Marker definitions +#define osRtxStackMagicWord 0xE25A2EA5U ///< Stack Magic Word (Stack Base) +#define osRtxStackFillPattern 0xCCCCCCCCU ///< Stack Fill Pattern + +/// Thread Control Block +typedef struct osRtxThread_s { + uint8_t id; ///< Object Identifier + uint8_t state; ///< Object State + uint8_t flags; ///< Object Flags + uint8_t attr; ///< Object Attributes + const char *name; ///< Object Name + struct osRtxThread_s *thread_next; ///< Link pointer to next Thread in Object list + struct osRtxThread_s *thread_prev; ///< Link pointer to previous Thread in Object list + struct osRtxThread_s *delay_next; ///< Link pointer to next Thread in Delay list + struct osRtxThread_s *delay_prev; ///< Link pointer to previous Thread in Delay list + struct osRtxThread_s *thread_join; ///< Thread waiting to Join + uint32_t delay; ///< Delay Time/Round Robin Time Tick + int8_t priority; ///< Thread Priority + int8_t priority_base; ///< Base Priority + uint8_t stack_frame; ///< Stack Frame (EXC_RETURN[7..0]) + uint8_t flags_options; ///< Thread/Event Flags Options + uint32_t wait_flags; ///< Waiting Thread/Event Flags + uint32_t thread_flags; ///< Thread Flags + struct osRtxMutex_s *mutex_list; ///< Link pointer to list of owned Mutexes + void *stack_mem; ///< Stack Memory + uint32_t stack_size; ///< Stack Size + uint32_t sp; ///< Current Stack Pointer + uint32_t thread_addr; ///< Thread entry address + uint32_t tz_memory; ///< TrustZone Memory Identifier +#ifdef RTX_TF_M_EXTENSION + uint32_t tz_module; ///< TrustZone Module Identifier +#endif +} osRtxThread_t; + + +// ==== Timer definitions ==== + +/// Timer State definitions +#define osRtxTimerInactive 0x00U ///< Timer Inactive +#define osRtxTimerStopped 0x01U ///< Timer Stopped +#define osRtxTimerRunning 0x02U ///< Timer Running + +/// Timer Type definitions +#define osRtxTimerPeriodic ((uint8_t)osTimerPeriodic) + +/// Timer Function Information +typedef struct { + osTimerFunc_t func; ///< Function Pointer + void *arg; ///< Function Argument +} osRtxTimerFinfo_t; + +/// Timer Control Block +typedef struct osRtxTimer_s { + uint8_t id; ///< Object Identifier + uint8_t state; ///< Object State + uint8_t flags; ///< Object Flags + uint8_t type; ///< Timer Type (Periodic/One-shot) + const char *name; ///< Object Name + struct osRtxTimer_s *prev; ///< Pointer to previous active Timer + struct osRtxTimer_s *next; ///< Pointer to next active Timer + uint32_t tick; ///< Timer current Tick + uint32_t load; ///< Timer Load value + osRtxTimerFinfo_t finfo; ///< Timer Function Info +} osRtxTimer_t; + + +// ==== Event Flags definitions ==== + +/// Event Flags Control Block +typedef struct { + uint8_t id; ///< Object Identifier + uint8_t reserved_state; ///< Object State (not used) + uint8_t flags; ///< Object Flags + uint8_t reserved; + const char *name; ///< Object Name + osRtxThread_t *thread_list; ///< Waiting Threads List + uint32_t event_flags; ///< Event Flags +} osRtxEventFlags_t; + + +// ==== Mutex definitions ==== + +/// Mutex Control Block +typedef struct osRtxMutex_s { + uint8_t id; ///< Object Identifier + uint8_t reserved_state; ///< Object State (not used) + uint8_t flags; ///< Object Flags + uint8_t attr; ///< Object Attributes + const char *name; ///< Object Name + osRtxThread_t *thread_list; ///< Waiting Threads List + osRtxThread_t *owner_thread; ///< Owner Thread + struct osRtxMutex_s *owner_prev; ///< Pointer to previous owned Mutex + struct osRtxMutex_s *owner_next; ///< Pointer to next owned Mutex + uint8_t lock; ///< Lock counter + uint8_t padding[3]; +} osRtxMutex_t; + + +// ==== Semaphore definitions ==== + +/// Semaphore Control Block +typedef struct { + uint8_t id; ///< Object Identifier + uint8_t reserved_state; ///< Object State (not used) + uint8_t flags; ///< Object Flags + uint8_t reserved; + const char *name; ///< Object Name + osRtxThread_t *thread_list; ///< Waiting Threads List + uint16_t tokens; ///< Current number of tokens + uint16_t max_tokens; ///< Maximum number of tokens +} osRtxSemaphore_t; + + +// ==== Memory Pool definitions ==== + +/// Memory Pool Information +typedef struct { + uint32_t max_blocks; ///< Maximum number of Blocks + uint32_t used_blocks; ///< Number of used Blocks + uint32_t block_size; ///< Block Size + void *block_base; ///< Block Memory Base Address + void *block_lim; ///< Block Memory Limit Address + void *block_free; ///< First free Block Address +} osRtxMpInfo_t; + +/// Memory Pool Control Block +typedef struct { + uint8_t id; ///< Object Identifier + uint8_t reserved_state; ///< Object State (not used) + uint8_t flags; ///< Object Flags + uint8_t reserved; + const char *name; ///< Object Name + osRtxThread_t *thread_list; ///< Waiting Threads List + osRtxMpInfo_t mp_info; ///< Memory Pool Info +} osRtxMemoryPool_t; + + +// ==== Message Queue definitions ==== + +/// Message Control Block +typedef struct osRtxMessage_s { + uint8_t id; ///< Object Identifier + uint8_t reserved_state; ///< Object State (not used) + uint8_t flags; ///< Object Flags + uint8_t priority; ///< Message Priority + struct osRtxMessage_s *prev; ///< Pointer to previous Message + struct osRtxMessage_s *next; ///< Pointer to next Message +} osRtxMessage_t; + +/// Message Queue Control Block +typedef struct { + uint8_t id; ///< Object Identifier + uint8_t reserved_state; ///< Object State (not used) + uint8_t flags; ///< Object Flags + uint8_t reserved; + const char *name; ///< Object Name + osRtxThread_t *thread_list; ///< Waiting Threads List + osRtxMpInfo_t mp_info; ///< Memory Pool Info + uint32_t msg_size; ///< Message Size + uint32_t msg_count; ///< Number of queued Messages + osRtxMessage_t *msg_first; ///< Pointer to first Message + osRtxMessage_t *msg_last; ///< Pointer to last Message +} osRtxMessageQueue_t; + + +// ==== Generic Object definitions ==== + +/// Generic Object Control Block +typedef struct { + uint8_t id; ///< Object Identifier + uint8_t state; ///< Object State + uint8_t flags; ///< Object Flags + uint8_t reserved; + const char *name; ///< Object Name + osRtxThread_t *thread_list; ///< Threads List +} osRtxObject_t; + + +// ==== OS Runtime Information definitions ==== + +/// OS Runtime Information structure +typedef struct { + const char *os_id; ///< OS Identification + uint32_t version; ///< OS Version + struct { ///< Kernel Info + uint8_t state; ///< State + volatile uint8_t blocked; ///< Blocked + uint8_t pendSV; ///< Pending SV + uint8_t reserved; + uint32_t tick; ///< Tick counter + } kernel; + int32_t tick_irqn; ///< Tick Timer IRQ Number + struct { ///< Thread Info + struct { ///< Thread Run Info + osRtxThread_t *curr; ///< Current running Thread + osRtxThread_t *next; ///< Next Thread to Run + } run; + osRtxObject_t ready; ///< Ready List Object + osRtxThread_t *idle; ///< Idle Thread + osRtxThread_t *delay_list; ///< Delay List + osRtxThread_t *wait_list; ///< Wait List (no Timeout) + osRtxThread_t *terminate_list; ///< Terminate Thread List + uint32_t reserved; + struct { ///< Thread Round Robin Info + osRtxThread_t *thread; ///< Round Robin Thread + uint32_t timeout; ///< Round Robin Timeout + } robin; + } thread; + struct { ///< Timer Info + osRtxTimer_t *list; ///< Active Timer List + osRtxThread_t *thread; ///< Timer Thread + osRtxMessageQueue_t *mq; ///< Timer Message Queue + void (*tick)(void); ///< Timer Tick Function + } timer; + struct { ///< ISR Post Processing Queue + uint16_t max; ///< Maximum Items + uint16_t cnt; ///< Item Count + uint16_t in; ///< Incoming Item Index + uint16_t out; ///< Outgoing Item Index + void **data; ///< Queue Data + } isr_queue; + struct { ///< ISR Post Processing functions + void (*thread)(osRtxThread_t*); ///< Thread Post Processing function + void (*event_flags)(osRtxEventFlags_t*); ///< Event Flags Post Processing function + void (*semaphore)(osRtxSemaphore_t*); ///< Semaphore Post Processing function + void (*memory_pool)(osRtxMemoryPool_t*); ///< Memory Pool Post Processing function + void (*message)(osRtxMessage_t*); ///< Message Post Processing function + } post_process; + struct { ///< Memory Pools (Variable Block Size) + void *stack; ///< Stack Memory + void *mp_data; ///< Memory Pool Data Memory + void *mq_data; ///< Message Queue Data Memory + void *common; ///< Common Memory + } mem; + struct { ///< Memory Pools (Fixed Block Size) + osRtxMpInfo_t *stack; ///< Stack for Threads + osRtxMpInfo_t *thread; ///< Thread Control Blocks + osRtxMpInfo_t *timer; ///< Timer Control Blocks + osRtxMpInfo_t *event_flags; ///< Event Flags Control Blocks + osRtxMpInfo_t *mutex; ///< Mutex Control Blocks + osRtxMpInfo_t *semaphore; ///< Semaphore Control Blocks + osRtxMpInfo_t *memory_pool; ///< Memory Pool Control Blocks + osRtxMpInfo_t *message_queue; ///< Message Queue Control Blocks + } mpi; +} osRtxInfo_t; + +extern osRtxInfo_t osRtxInfo; ///< OS Runtime Information + +/// OS Runtime Object Memory Usage structure +typedef struct { + uint32_t cnt_alloc; ///< Counter for alloc + uint32_t cnt_free; ///< Counter for free + uint32_t max_used; ///< Maximum used +} osRtxObjectMemUsage_t; + +/// OS Runtime Object Memory Usage variables +extern osRtxObjectMemUsage_t osRtxThreadMemUsage; +extern osRtxObjectMemUsage_t osRtxTimerMemUsage; +extern osRtxObjectMemUsage_t osRtxEventFlagsMemUsage; +extern osRtxObjectMemUsage_t osRtxMutexMemUsage; +extern osRtxObjectMemUsage_t osRtxSemaphoreMemUsage; +extern osRtxObjectMemUsage_t osRtxMemoryPoolMemUsage; +extern osRtxObjectMemUsage_t osRtxMessageQueueMemUsage; + + +// ==== OS API definitions ==== + +// Object Limits definitions +#define osRtxThreadFlagsLimit 31U ///< number of Thread Flags available per thread +#define osRtxEventFlagsLimit 31U ///< number of Event Flags available per object +#define osRtxMutexLockLimit 255U ///< maximum number of recursive mutex locks +#define osRtxSemaphoreTokenLimit 65535U ///< maximum number of tokens per semaphore + +// Control Block sizes +#define osRtxThreadCbSize sizeof(osRtxThread_t) +#define osRtxTimerCbSize sizeof(osRtxTimer_t) +#define osRtxEventFlagsCbSize sizeof(osRtxEventFlags_t) +#define osRtxMutexCbSize sizeof(osRtxMutex_t) +#define osRtxSemaphoreCbSize sizeof(osRtxSemaphore_t) +#define osRtxMemoryPoolCbSize sizeof(osRtxMemoryPool_t) +#define osRtxMessageQueueCbSize sizeof(osRtxMessageQueue_t) + +/// Memory size in bytes for Memory Pool storage. +/// \param block_count maximum number of memory blocks in memory pool. +/// \param block_size memory block size in bytes. +#define osRtxMemoryPoolMemSize(block_count, block_size) \ + (4*(block_count)*(((block_size)+3)/4)) + +/// Memory size in bytes for Message Queue storage. +/// \param msg_count maximum number of messages in queue. +/// \param msg_size maximum message size in bytes. +#define osRtxMessageQueueMemSize(msg_count, msg_size) \ + (4*(msg_count)*(3+(((msg_size)+3)/4))) + + +// ==== OS External Functions ==== + +// OS Error Codes +#define osRtxErrorStackUnderflow 1U ///< \deprecated Superseded by \ref osRtxErrorStackOverflow. +#define osRtxErrorStackOverflow 1U ///< Stack overflow, i.e. stack pointer below its lower memory limit for descending stacks. +#define osRtxErrorISRQueueOverflow 2U ///< ISR Queue overflow detected when inserting object. +#define osRtxErrorTimerQueueOverflow 3U ///< User Timer Callback Queue overflow detected for timer. +#define osRtxErrorClibSpace 4U ///< Standard C/C++ library libspace not available: increase \c OS_THREAD_LIBSPACE_NUM. +#define osRtxErrorClibMutex 5U ///< Standard C/C++ library mutex initialization failed. + +/// OS Error Callback function +extern uint32_t osRtxErrorNotify (uint32_t code, void *object_id); +extern uint32_t osRtxKernelErrorNotify (uint32_t code, void *object_id); + +/// OS Idle Thread +extern void osRtxIdleThread (void *argument); + +/// OS Exception handlers +extern void SVC_Handler (void); +extern void PendSV_Handler (void); +extern void SysTick_Handler (void); + +/// OS Trusted Firmware M Extension +#ifdef RTX_TF_M_EXTENSION +extern uint32_t osRtxTzGetModuleId (void); +#endif + + +// ==== OS External Configuration ==== + +/// OS Configuration flags +#define osRtxConfigPrivilegedMode (1UL<<0) ///< Threads in Privileged mode +#define osRtxConfigStackCheck (1UL<<1) ///< Stack overrun checking +#define osRtxConfigStackWatermark (1UL<<2) ///< Stack usage Watermark + +/// OS Configuration structure +typedef struct { + uint32_t flags; ///< OS Configuration Flags + uint32_t tick_freq; ///< Kernel Tick Frequency + uint32_t robin_timeout; ///< Round Robin Timeout Tick + struct { ///< ISR Post Processing Queue + void **data; ///< Queue Data + uint16_t max; ///< Maximum Items + uint16_t padding; + } isr_queue; + struct { ///< Memory Pools (Variable Block Size) + void *stack_addr; ///< Stack Memory Address + uint32_t stack_size; ///< Stack Memory Size + void *mp_data_addr; ///< Memory Pool Memory Address + uint32_t mp_data_size; ///< Memory Pool Memory Size + void *mq_data_addr; ///< Message Queue Data Memory Address + uint32_t mq_data_size; ///< Message Queue Data Memory Size + void *common_addr; ///< Common Memory Address + uint32_t common_size; ///< Common Memory Size + } mem; + struct { ///< Memory Pools (Fixed Block Size) + osRtxMpInfo_t *stack; ///< Stack for Threads + osRtxMpInfo_t *thread; ///< Thread Control Blocks + osRtxMpInfo_t *timer; ///< Timer Control Blocks + osRtxMpInfo_t *event_flags; ///< Event Flags Control Blocks + osRtxMpInfo_t *mutex; ///< Mutex Control Blocks + osRtxMpInfo_t *semaphore; ///< Semaphore Control Blocks + osRtxMpInfo_t *memory_pool; ///< Memory Pool Control Blocks + osRtxMpInfo_t *message_queue; ///< Message Queue Control Blocks + } mpi; + uint32_t thread_stack_size; ///< Default Thread Stack Size + const + osThreadAttr_t *idle_thread_attr; ///< Idle Thread Attributes + const + osThreadAttr_t *timer_thread_attr; ///< Timer Thread Attributes + void (*timer_thread)(void *); ///< Timer Thread Function + int32_t (*timer_setup)(void); ///< Timer Setup Function + const + osMessageQueueAttr_t *timer_mq_attr; ///< Timer Message Queue Attributes + uint32_t timer_mq_mcnt; ///< Timer Message Queue maximum Messages +} osRtxConfig_t; + +extern const osRtxConfig_t osRtxConfig; ///< OS Configuration + + +#ifdef __cplusplus +} +#endif + +#endif // RTX_OS_H_ diff --git a/CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM0.a b/CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM0.a new file mode 100644 index 0000000..07a62b9 Binary files /dev/null and b/CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM0.a differ diff --git a/CMSIS/RTOS2/RTX/Source/rtx_core_c.h b/CMSIS/RTOS2/RTX/Source/rtx_core_c.h new file mode 100644 index 0000000..7192a1d --- /dev/null +++ b/CMSIS/RTOS2/RTX/Source/rtx_core_c.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2013-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: Cortex Core definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CORE_C_H_ +#define RTX_CORE_C_H_ + +//lint -emacro((923,9078),SCB) "cast from unsigned long to pointer" [MISRA Note 9] +#ifndef RTE_COMPONENTS_H +#include "RTE_Components.h" +#endif +#include CMSIS_device_header + +#if ((!defined(__ARM_ARCH_6M__)) && \ + (!defined(__ARM_ARCH_7A__)) && \ + (!defined(__ARM_ARCH_7M__)) && \ + (!defined(__ARM_ARCH_7EM__)) && \ + (!defined(__ARM_ARCH_8M_BASE__)) && \ + (!defined(__ARM_ARCH_8M_MAIN__)) && \ + (!defined(__ARM_ARCH_8_1M_MAIN__))) +#error "Unknown Arm Architecture!" +#endif + +#if (defined(__ARM_ARCH_7A__) && (__ARM_ARCH_7A__ != 0)) +#include "rtx_core_ca.h" +#else +#include "rtx_core_cm.h" +#endif + +#endif // RTX_CORE_C_H_ diff --git a/CMSIS/RTOS2/RTX/Source/rtx_core_ca.h b/CMSIS/RTOS2/RTX/Source/rtx_core_ca.h new file mode 100644 index 0000000..a599516 --- /dev/null +++ b/CMSIS/RTOS2/RTX/Source/rtx_core_ca.h @@ -0,0 +1,1129 @@ +/* + * Copyright (c) 2013-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: Cortex-A Core definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CORE_CA_H_ +#define RTX_CORE_CA_H_ + +#ifndef RTX_CORE_C_H_ +#ifndef RTE_COMPONENTS_H +#include "RTE_Components.h" +#endif +#include CMSIS_device_header +#endif + +#include +typedef bool bool_t; + +#ifndef FALSE +#define FALSE ((bool_t)0) +#endif + +#ifndef TRUE +#define TRUE ((bool_t)1) +#endif + +#define DOMAIN_NS 0 +#define EXCLUSIVE_ACCESS 1 + +#define OS_TICK_HANDLER osRtxTick_Handler + +// CPSR bit definitions +#define CPSR_T_BIT 0x20U +#define CPSR_I_BIT 0x80U +#define CPSR_F_BIT 0x40U + +// CPSR mode bitmasks +#define CPSR_MODE_USER 0x10U +#define CPSR_MODE_SYSTEM 0x1FU + +/// xPSR_Initialization Value +/// \param[in] privileged true=privileged, false=unprivileged +/// \param[in] thumb true=Thumb, false=Arm +/// \return xPSR Init Value +__STATIC_INLINE uint32_t xPSR_InitVal (bool_t privileged, bool_t thumb) { + uint32_t psr; + + if (privileged) { + if (thumb) { + psr = CPSR_MODE_SYSTEM | CPSR_T_BIT; + } else { + psr = CPSR_MODE_SYSTEM; + } + } else { + if (thumb) { + psr = CPSR_MODE_USER | CPSR_T_BIT; + } else { + psr = CPSR_MODE_USER; + } + } + + return psr; +} + +// Stack Frame: +// - VFP-D32: D16-31, D0-D15, FPSCR, Reserved, R4-R11, R0-R3, R12, LR, PC, CPSR +// - VFP-D16: D0-D15, FPSCR, Reserved, R4-R11, R0-R3, R12, LR, PC, CPSR +// - Basic: R4-R11, R0-R3, R12, LR, PC, CPSR + +/// Stack Frame Initialization Value +#define STACK_FRAME_INIT_VAL 0x00U + +/// Stack Offset of Register R0 +/// \param[in] stack_frame Stack Frame +/// \return R0 Offset +__STATIC_INLINE uint32_t StackOffsetR0 (uint8_t stack_frame) { + uint32_t offset; + + if ((stack_frame & 0x04U) != 0U) { + offset = (32U*8U) + (2U*4U) + (8U*4U); + } else if ((stack_frame & 0x02U) != 0U) { + offset = (16U*8U) + (2U*4U) + (8U*4U); + } else { + offset = (8U*4U); + } + return offset; +} + + +// ==== Emulated Cortex-M functions ==== + +/// Get xPSR Register - emulate M profile: SP_usr - (8*4) +/// \return xPSR Register value +#if defined(__CC_ARM) +#pragma push +#pragma arm +static __asm uint32_t __get_PSP (void) { + sub sp, sp, #4 + stm sp, {sp}^ + pop {r0} + sub r0, r0, #32 + bx lr +} +#pragma pop +#else +#ifdef __ICCARM__ +__arm +#else +__attribute__((target("arm"))) +#endif +__STATIC_INLINE uint32_t __get_PSP (void) { + register uint32_t ret; + + __ASM volatile ( + "sub sp,sp,#4\n\t" + "stm sp,{sp}^\n\t" + "pop {%[ret]}\n\t" + "sub %[ret],%[ret],#32\n\t" + : [ret] "=&l" (ret) + : + : "memory" + ); + + return ret; +} +#endif + +/// Set Control Register - not needed for A profile +/// \param[in] control Control Register value to set +__STATIC_INLINE void __set_CONTROL(uint32_t control) { + (void)control; +} + + +// ==== Core functions ==== + +/// Check if running Privileged +/// \return true=privileged, false=unprivileged +__STATIC_INLINE bool_t IsPrivileged (void) { + return (__get_mode() != CPSR_MODE_USER); +} + +/// Check if in Exception +/// \return true=exception, false=thread +__STATIC_INLINE bool_t IsException (void) { + return ((__get_mode() != CPSR_MODE_USER) && (__get_mode() != CPSR_MODE_SYSTEM)); +} + +/// Check if IRQ is Masked +/// \return true=masked, false=not masked +__STATIC_INLINE bool_t IsIrqMasked (void) { + return FALSE; +} + + +// ==== Core Peripherals functions ==== + +extern uint8_t IRQ_PendSV; + +/// Setup SVC and PendSV System Service Calls (not needed on Cortex-A) +__STATIC_INLINE void SVC_Setup (void) { +} + +/// Get Pending SV (Service Call) Flag +/// \return Pending SV Flag +__STATIC_INLINE uint8_t GetPendSV (void) { + return (IRQ_PendSV); +} + +/// Clear Pending SV (Service Call) Flag +__STATIC_INLINE void ClrPendSV (void) { + IRQ_PendSV = 0U; +} + +/// Set Pending SV (Service Call) Flag +__STATIC_INLINE void SetPendSV (void) { + IRQ_PendSV = 1U; +} + + +// ==== Service Calls definitions ==== + +#if defined(__CC_ARM) + +#define __SVC_INDIRECT(n) __svc_indirect(n) + +#define SVC0_0N(f,t) \ +__SVC_INDIRECT(0) t svc##f (t(*)()); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (void) { \ + svc##f(svcRtx##f); \ +} + +#define SVC0_0(f,t) \ +__SVC_INDIRECT(0) t svc##f (t(*)()); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (void) { \ + return svc##f(svcRtx##f); \ +} + +#define SVC0_1N(f,t,t1) \ +__SVC_INDIRECT(0) t svc##f (t(*)(t1),t1); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1) { \ + svc##f(svcRtx##f,a1); \ +} + +#define SVC0_1(f,t,t1) \ +__SVC_INDIRECT(0) t svc##f (t(*)(t1),t1); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1) { \ + return svc##f(svcRtx##f,a1); \ +} + +#define SVC0_2(f,t,t1,t2) \ +__SVC_INDIRECT(0) t svc##f (t(*)(t1,t2),t1,t2); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1, t2 a2) { \ + return svc##f(svcRtx##f,a1,a2); \ +} + +#define SVC0_3(f,t,t1,t2,t3) \ +__SVC_INDIRECT(0) t svc##f (t(*)(t1,t2,t3),t1,t2,t3); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) { \ + return svc##f(svcRtx##f,a1,a2,a3); \ +} + +#define SVC0_4(f,t,t1,t2,t3,t4) \ +__SVC_INDIRECT(0) t svc##f (t(*)(t1,t2,t3,t4),t1,t2,t3,t4); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) { \ + return svc##f(svcRtx##f,a1,a2,a3,a4); \ +} + +#elif defined(__ICCARM__) + +#define SVC_ArgF(f) \ + __asm( \ + "mov r12,%0\n" \ + :: "r"(&f): "r12" \ + ); + +#define STRINGIFY(a) #a +#define __SVC_INDIRECT(n) _Pragma(STRINGIFY(swi_number = n)) __swi + +#define SVC0_0N(f,t) \ +__SVC_INDIRECT(0) t svc##f (); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (void) { \ + SVC_ArgF(svcRtx##f); \ + svc##f(); \ +} + +#define SVC0_0(f,t) \ +__SVC_INDIRECT(0) t svc##f (); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (void) { \ + SVC_ArgF(svcRtx##f); \ + return svc##f(); \ +} + +#define SVC0_1N(f,t,t1) \ +__SVC_INDIRECT(0) t svc##f (t1 a1); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1) { \ + SVC_ArgF(svcRtx##f); \ + svc##f(a1); \ +} + +#define SVC0_1(f,t,t1) \ +__SVC_INDIRECT(0) t svc##f (t1 a1); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1) { \ + SVC_ArgF(svcRtx##f); \ + return svc##f(a1); \ +} + +#define SVC0_2(f,t,t1,t2) \ +__SVC_INDIRECT(0) t svc##f (t1 a1, t2 a2); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1, t2 a2) { \ + SVC_ArgF(svcRtx##f); \ + return svc##f(a1,a2); \ +} + +#define SVC0_3(f,t,t1,t2,t3) \ +__SVC_INDIRECT(0) t svc##f (t1 a1, t2 a2, t3 a3); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) { \ + SVC_ArgF(svcRtx##f); \ + return svc##f(a1,a2,a3); \ +} + +#define SVC0_4(f,t,t1,t2,t3,t4) \ +__SVC_INDIRECT(0) t svc##f (t1 a1, t2 a2, t3 a3, t4 a4); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) { \ + SVC_ArgF(svcRtx##f); \ + return svc##f(a1,a2,a3,a4); \ +} + +#else // !(defined(__CC_ARM) || defined(__ICCARM__)) + +#define SVC_RegF "r12" + +#define SVC_ArgN(n) \ +register uint32_t __r##n __ASM("r"#n) + +#define SVC_ArgR(n,a) \ +register uint32_t __r##n __ASM("r"#n) = (uint32_t)a + +#define SVC_ArgF(f) \ +register uint32_t __rf __ASM(SVC_RegF) = (uint32_t)f + +#define SVC_In0 "r"(__rf) +#define SVC_In1 "r"(__rf),"r"(__r0) +#define SVC_In2 "r"(__rf),"r"(__r0),"r"(__r1) +#define SVC_In3 "r"(__rf),"r"(__r0),"r"(__r1),"r"(__r2) +#define SVC_In4 "r"(__rf),"r"(__r0),"r"(__r1),"r"(__r2),"r"(__r3) + +#define SVC_Out0 +#define SVC_Out1 "=r"(__r0) + +#define SVC_CL0 +#define SVC_CL1 "r1" +#define SVC_CL2 "r0","r1" + +#define SVC_Call0(in, out, cl) \ + __ASM volatile ("svc 0" : out : in : cl) + +#define SVC0_0N(f,t) \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (void) { \ + SVC_ArgF(svcRtx##f); \ + SVC_Call0(SVC_In0, SVC_Out0, SVC_CL2); \ +} + +#define SVC0_0(f,t) \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (void) { \ + SVC_ArgN(0); \ + SVC_ArgF(svcRtx##f); \ + SVC_Call0(SVC_In0, SVC_Out1, SVC_CL1); \ + return (t) __r0; \ +} + +#define SVC0_1N(f,t,t1) \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1) { \ + SVC_ArgR(0,a1); \ + SVC_ArgF(svcRtx##f); \ + SVC_Call0(SVC_In1, SVC_Out0, SVC_CL1); \ +} + +#define SVC0_1(f,t,t1) \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1) { \ + SVC_ArgR(0,a1); \ + SVC_ArgF(svcRtx##f); \ + SVC_Call0(SVC_In1, SVC_Out1, SVC_CL1); \ + return (t) __r0; \ +} + +#define SVC0_2(f,t,t1,t2) \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1, t2 a2) { \ + SVC_ArgR(0,a1); \ + SVC_ArgR(1,a2); \ + SVC_ArgF(svcRtx##f); \ + SVC_Call0(SVC_In2, SVC_Out1, SVC_CL0); \ + return (t) __r0; \ +} + +#define SVC0_3(f,t,t1,t2,t3) \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) { \ + SVC_ArgR(0,a1); \ + SVC_ArgR(1,a2); \ + SVC_ArgR(2,a3); \ + SVC_ArgF(svcRtx##f); \ + SVC_Call0(SVC_In3, SVC_Out1, SVC_CL0); \ + return (t) __r0; \ +} + +#define SVC0_4(f,t,t1,t2,t3,t4) \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) { \ + SVC_ArgR(0,a1); \ + SVC_ArgR(1,a2); \ + SVC_ArgR(2,a3); \ + SVC_ArgR(3,a4); \ + SVC_ArgF(svcRtx##f); \ + SVC_Call0(SVC_In4, SVC_Out1, SVC_CL0); \ + return (t) __r0; \ +} + +#endif + + +// ==== Exclusive Access Operation ==== + +#if (EXCLUSIVE_ACCESS == 1) + +/// Atomic Access Operation: Write (8-bit) +/// \param[in] mem Memory address +/// \param[in] val Value to write +/// \return Previous value +#if defined(__CC_ARM) +static __asm uint8_t atomic_wr8 (uint8_t *mem, uint8_t val) { + mov r2,r0 +1 + ldrexb r0,[r2] + strexb r3,r1,[r2] + cmp r3,#0 + bne %B1 + bx lr +} +#else +__STATIC_INLINE uint8_t atomic_wr8 (uint8_t *mem, uint8_t val) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint8_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrexb %[ret],[%[mem]]\n\t" + "strexb %[res],%[val],[%[mem]]\n\t" + "cmp %[res],#0\n\t" + "bne 1b\n\t" + : [ret] "=&l" (ret), + [res] "=&l" (res) + : [mem] "l" (mem), + [val] "l" (val) + : "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Set bits (32-bit) +/// \param[in] mem Memory address +/// \param[in] bits Bit mask +/// \return New value +#if defined(__CC_ARM) +static __asm uint32_t atomic_set32 (uint32_t *mem, uint32_t bits) { + mov r2,r0 +1 + ldrex r0,[r2] + orr r0,r0,r1 + strex r3,r0,[r2] + cmp r3,#0 + bne %B1 + bx lr +} +#else +__STATIC_INLINE uint32_t atomic_set32 (uint32_t *mem, uint32_t bits) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint32_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrex %[val],[%[mem]]\n\t" + "orr %[ret],%[val],%[bits]\n\t" + "strex %[res],%[ret],[%[mem]]\n\t" + "cmp %[res],#0\n\t" + "bne 1b\n" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem), + [bits] "l" (bits) + : "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Clear bits (32-bit) +/// \param[in] mem Memory address +/// \param[in] bits Bit mask +/// \return Previous value +#if defined(__CC_ARM) +static __asm uint32_t atomic_clr32 (uint32_t *mem, uint32_t bits) { + push {r4,lr} + mov r2,r0 +1 + ldrex r0,[r2] + bic r4,r0,r1 + strex r3,r4,[r2] + cmp r3,#0 + bne %B1 + pop {r4,pc} +} +#else +__STATIC_INLINE uint32_t atomic_clr32 (uint32_t *mem, uint32_t bits) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint32_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrex %[ret],[%[mem]]\n\t" + "bic %[val],%[ret],%[bits]\n\t" + "strex %[res],%[val],[%[mem]]\n\t" + "cmp %[res],#0\n\t" + "bne 1b\n" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem), + [bits] "l" (bits) + : "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Check if all specified bits (32-bit) are active and clear them +/// \param[in] mem Memory address +/// \param[in] bits Bit mask +/// \return Active bits before clearing or 0 if not active +#if defined(__CC_ARM) +static __asm uint32_t atomic_chk32_all (uint32_t *mem, uint32_t bits) { + push {r4,lr} + mov r2,r0 +1 + ldrex r0,[r2] + and r4,r0,r1 + cmp r4,r1 + beq %F2 + clrex + movs r0,#0 + pop {r4,pc} +2 + bic r4,r0,r1 + strex r3,r4,[r2] + cmp r3,#0 + bne %B1 + pop {r4,pc} +} +#else +__STATIC_INLINE uint32_t atomic_chk32_all (uint32_t *mem, uint32_t bits) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint32_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrex %[ret],[%[mem]]\n\t" + "and %[val],%[ret],%[bits]\n\t" + "cmp %[val],%[bits]\n\t" + "beq 2f\n\t" + "clrex\n\t" + "movs %[ret],#0\n\t" + "b 3f\n" + "2:\n\t" + "bic %[val],%[ret],%[bits]\n\t" + "strex %[res],%[val],[%[mem]]\n\t" + "cmp %[res],#0\n\t" + "bne 1b\n" + "3:" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem), + [bits] "l" (bits) + : "cc", "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Check if any specified bits (32-bit) are active and clear them +/// \param[in] mem Memory address +/// \param[in] bits Bit mask +/// \return Active bits before clearing or 0 if not active +#if defined(__CC_ARM) +static __asm uint32_t atomic_chk32_any (uint32_t *mem, uint32_t bits) { + push {r4,lr} + mov r2,r0 +1 + ldrex r0,[r2] + tst r0,r1 + bne %F2 + clrex + movs r0,#0 + pop {r4,pc} +2 + bic r4,r0,r1 + strex r3,r4,[r2] + cmp r3,#0 + bne %B1 + pop {r4,pc} +} +#else +__STATIC_INLINE uint32_t atomic_chk32_any (uint32_t *mem, uint32_t bits) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint32_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrex %[ret],[%[mem]]\n\t" + "tst %[ret],%[bits]\n\t" + "bne 2f\n\t" + "clrex\n\t" + "movs %[ret],#0\n\t" + "b 3f\n" + "2:\n\t" + "bic %[val],%[ret],%[bits]\n\t" + "strex %[res],%[val],[%[mem]]\n\t" + "cmp %[res],#0\n\t" + "bne 1b\n" + "3:" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem), + [bits] "l" (bits) + : "cc", "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Increment (32-bit) +/// \param[in] mem Memory address +/// \return Previous value +#if defined(__CC_ARM) +static __asm uint32_t atomic_inc32 (uint32_t *mem) { + mov r2,r0 +1 + ldrex r0,[r2] + adds r1,r0,#1 + strex r3,r1,[r2] + cmp r3,#0 + bne %B1 + bx lr +} +#else +__STATIC_INLINE uint32_t atomic_inc32 (uint32_t *mem) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint32_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrex %[ret],[%[mem]]\n\t" + "adds %[val],%[ret],#1\n\t" + "strex %[res],%[val],[%[mem]]\n\t" + "cmp %[res],#0\n\t" + "bne 1b\n" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem) + : "cc", "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Increment (16-bit) if Less Than +/// \param[in] mem Memory address +/// \param[in] max Maximum value +/// \return Previous value +#if defined(__CC_ARM) +static __asm uint16_t atomic_inc16_lt (uint16_t *mem, uint16_t max) { + push {r4,lr} + mov r2,r0 +1 + ldrexh r0,[r2] + cmp r1,r0 + bhi %F2 + clrex + pop {r4,pc} +2 + adds r4,r0,#1 + strexh r3,r4,[r2] + cmp r3,#0 + bne %B1 + pop {r4,pc} +} +#else +__STATIC_INLINE uint16_t atomic_inc16_lt (uint16_t *mem, uint16_t max) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint16_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrexh %[ret],[%[mem]]\n\t" + "cmp %[max],%[ret]\n\t" + "bhi 2f\n\t" + "clrex\n\t" + "b 3f\n" + "2:\n\t" + "adds %[val],%[ret],#1\n\t" + "strexh %[res],%[val],[%[mem]]\n\t" + "cmp %[res],#0\n\t" + "bne 1b\n" + "3:" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem), + [max] "l" (max) + : "cc", "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Increment (16-bit) and clear on Limit +/// \param[in] mem Memory address +/// \param[in] max Maximum value +/// \return Previous value +#if defined(__CC_ARM) +static __asm uint16_t atomic_inc16_lim (uint16_t *mem, uint16_t lim) { + push {r4,lr} + mov r2,r0 +1 + ldrexh r0,[r2] + adds r4,r0,#1 + cmp r1,r4 + bhi %F2 + movs r4,#0 +2 + strexh r3,r4,[r2] + cmp r3,#0 + bne %B1 + pop {r4,pc} +} +#else +__STATIC_INLINE uint16_t atomic_inc16_lim (uint16_t *mem, uint16_t lim) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint16_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrexh %[ret],[%[mem]]\n\t" + "adds %[val],%[ret],#1\n\t" + "cmp %[lim],%[val]\n\t" + "bhi 2f\n\t" + "movs %[val],#0\n" + "2:\n\t" + "strexh %[res],%[val],[%[mem]]\n\t" + "cmp %[res],#0\n\t" + "bne 1b\n" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem), + [lim] "l" (lim) + : "cc", "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Decrement (32-bit) +/// \param[in] mem Memory address +/// \return Previous value +#if defined(__CC_ARM) +static __asm uint32_t atomic_dec32 (uint32_t *mem) { + mov r2,r0 +1 + ldrex r0,[r2] + subs r1,r0,#1 + strex r3,r1,[r2] + cmp r3,#0 + bne %B1 + bx lr +} +#else +__STATIC_INLINE uint32_t atomic_dec32 (uint32_t *mem) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint32_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrex %[ret],[%[mem]]\n\t" + "subs %[val],%[ret],#1\n\t" + "strex %[res],%[val],[%[mem]]\n\t" + "cmp %[res],#0\n\t" + "bne 1b\n" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem) + : "cc", "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Decrement (32-bit) if Not Zero +/// \param[in] mem Memory address +/// \return Previous value +#if defined(__CC_ARM) +static __asm uint32_t atomic_dec32_nz (uint32_t *mem) { + mov r2,r0 +1 + ldrex r0,[r2] + cmp r0,#0 + bne %F2 + clrex + bx lr +2 + subs r1,r0,#1 + strex r3,r1,[r2] + cmp r3,#0 + bne %B1 + bx lr +} +#else +__STATIC_INLINE uint32_t atomic_dec32_nz (uint32_t *mem) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint32_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrex %[ret],[%[mem]]\n\t" + "cmp %[ret],#0\n\t" + "bne 2f\n" + "clrex\n\t" + "b 3f\n" + "2:\n\t" + "subs %[val],%[ret],#1\n\t" + "strex %[res],%[val],[%[mem]]\n\t" + "cmp %[res],#0\n\t" + "bne 1b\n" + "3:" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem) + : "cc", "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Decrement (16-bit) if Not Zero +/// \param[in] mem Memory address +/// \return Previous value +#if defined(__CC_ARM) +static __asm uint16_t atomic_dec16_nz (uint16_t *mem) { + mov r2,r0 +1 + ldrexh r0,[r2] + cmp r0,#0 + bne %F2 + clrex + bx lr +2 + subs r1,r0,#1 + strexh r3,r1,[r2] + cmp r3,#0 + bne %B1 + bx lr +} +#else +__STATIC_INLINE uint16_t atomic_dec16_nz (uint16_t *mem) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint16_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrexh %[ret],[%[mem]]\n\t" + "cmp %[ret],#0\n\t" + "bne 2f\n\t" + "clrex\n\t" + "b 3f\n" + "2:\n\t" + "subs %[val],%[ret],#1\n\t" + "strexh %[res],%[val],[%[mem]]\n\t" + "cmp %[res],#0\n\t" + "bne 1b\n" + "3:" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem) + : "cc", "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Link Get +/// \param[in] root Root address +/// \return Link +#if defined(__CC_ARM) +static __asm void *atomic_link_get (void **root) { + mov r2,r0 +1 + ldrex r0,[r2] + cmp r0,#0 + bne %F2 + clrex + bx lr +2 + ldr r1,[r0] + strex r3,r1,[r2] + cmp r3,#0 + bne %B1 + bx lr +} +#else +__STATIC_INLINE void *atomic_link_get (void **root) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register void *ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrex %[ret],[%[root]]\n\t" + "cmp %[ret],#0\n\t" + "bne 2f\n\t" + "clrex\n\t" + "b 3f\n" + "2:\n\t" + "ldr %[val],[%[ret]]\n\t" + "strex %[res],%[val],[%[root]]\n\t" + "cmp %[res],#0\n\t" + "bne 1b\n" + "3:" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [root] "l" (root) + : "cc", "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Link Put +/// \param[in] root Root address +/// \param[in] lnk Link +#if defined(__CC_ARM) +static __asm void atomic_link_put (void **root, void *link) { +1 + ldr r2,[r0] + str r2,[r1] + dmb + ldrex r2,[r0] + ldr r3,[r1] + cmp r3,r2 + bne %B1 + strex r3,r1,[r0] + cmp r3,#0 + bne %B1 + bx lr +} +#else +__STATIC_INLINE void atomic_link_put (void **root, void *link) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val1, val2, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldr %[val1],[%[root]]\n\t" + "str %[val1],[%[link]]\n\t" + "dmb\n\t" + "ldrex %[val1],[%[root]]\n\t" + "ldr %[val2],[%[link]]\n\t" + "cmp %[val2],%[val1]\n\t" + "bne 1b\n\t" + "strex %[res],%[link],[%[root]]\n\t" + "cmp %[res],#0\n\t" + "bne 1b\n" + : [val1] "=&l" (val1), + [val2] "=&l" (val2), + [res] "=&l" (res) + : [root] "l" (root), + [link] "l" (link) + : "cc", "memory" + ); +} +#endif + +#endif // (EXCLUSIVE_ACCESS == 1) + + +#endif // RTX_CORE_CA_H_ diff --git a/CMSIS/RTOS2/RTX/Source/rtx_core_cm.h b/CMSIS/RTOS2/RTX/Source/rtx_core_cm.h new file mode 100644 index 0000000..086b1e0 --- /dev/null +++ b/CMSIS/RTOS2/RTX/Source/rtx_core_cm.h @@ -0,0 +1,1213 @@ +/* + * Copyright (c) 2013-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: Cortex-M Core definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CORE_CM_H_ +#define RTX_CORE_CM_H_ + +#ifndef RTX_CORE_C_H_ +#ifndef RTE_COMPONENTS_H +#include "RTE_Components.h" +#endif +#include CMSIS_device_header +#endif + +#include +typedef bool bool_t; + +#ifndef FALSE +#define FALSE ((bool_t)0) +#endif + +#ifndef TRUE +#define TRUE ((bool_t)1) +#endif + +#ifndef DOMAIN_NS +#define DOMAIN_NS 0 +#endif + +#if (DOMAIN_NS == 1) +#if ((!defined(__ARM_ARCH_8M_BASE__) || (__ARM_ARCH_8M_BASE__ == 0)) && \ + (!defined(__ARM_ARCH_8M_MAIN__) || (__ARM_ARCH_8M_MAIN__ == 0)) && \ + (!defined(__ARM_ARCH_8_1M_MAIN__) || (__ARM_ARCH_8_1M_MAIN__ == 0))) +#error "Non-secure domain requires ARMv8-M Architecture!" +#endif +#endif + +#ifndef EXCLUSIVE_ACCESS +#if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ != 0)) || \ + (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ != 0)) || \ + (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \ + (defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0))) +#define EXCLUSIVE_ACCESS 1 +#else +#define EXCLUSIVE_ACCESS 0 +#endif +#endif + +#define OS_TICK_HANDLER SysTick_Handler + +/// xPSR_Initialization Value +/// \param[in] privileged true=privileged, false=unprivileged +/// \param[in] thumb true=Thumb, false=ARM +/// \return xPSR Init Value +__STATIC_INLINE uint32_t xPSR_InitVal (bool_t privileged, bool_t thumb) { + (void)privileged; + (void)thumb; + return (0x01000000U); +} + +// Stack Frame: +// - Extended: S16-S31, R4-R11, R0-R3, R12, LR, PC, xPSR, S0-S15, FPSCR +// - Basic: R4-R11, R0-R3, R12, LR, PC, xPSR + +/// Stack Frame Initialization Value (EXC_RETURN[7..0]) +#if (DOMAIN_NS == 1) +#define STACK_FRAME_INIT_VAL 0xBCU +#else +#define STACK_FRAME_INIT_VAL 0xFDU +#endif + +/// Stack Offset of Register R0 +/// \param[in] stack_frame Stack Frame (EXC_RETURN[7..0]) +/// \return R0 Offset +__STATIC_INLINE uint32_t StackOffsetR0 (uint8_t stack_frame) { +#if ((__FPU_USED == 1U) || \ + (defined(__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) + return (((stack_frame & 0x10U) == 0U) ? ((16U+8U)*4U) : (8U*4U)); +#else + (void)stack_frame; + return (8U*4U); +#endif +} + + +// ==== Core functions ==== + +//lint -sem(__get_CONTROL, pure) +//lint -sem(__get_IPSR, pure) +//lint -sem(__get_PRIMASK, pure) +//lint -sem(__get_BASEPRI, pure) + +/// Check if running Privileged +/// \return true=privileged, false=unprivileged +__STATIC_INLINE bool_t IsPrivileged (void) { + return ((__get_CONTROL() & 1U) == 0U); +} + +/// Check if in Exception +/// \return true=exception, false=thread +__STATIC_INLINE bool_t IsException (void) { + return (__get_IPSR() != 0U); +} + +/// Check if IRQ is Masked +/// \return true=masked, false=not masked +__STATIC_INLINE bool_t IsIrqMasked (void) { +#if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ != 0)) || \ + (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ != 0)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \ + (defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0))) + return ((__get_PRIMASK() != 0U) || (__get_BASEPRI() != 0U)); +#else + return (__get_PRIMASK() != 0U); +#endif +} + + +// ==== Core Peripherals functions ==== + +/// Setup SVC and PendSV System Service Calls +__STATIC_INLINE void SVC_Setup (void) { +#if ((defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \ + (defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0)) || \ + (defined(__CORTEX_M) && (__CORTEX_M == 7U))) + uint32_t p, n; + + SCB->SHPR[10] = 0xFFU; + n = 32U - (uint32_t)__CLZ(~(SCB->SHPR[10] | 0xFFFFFF00U)); + p = NVIC_GetPriorityGrouping(); + if (p >= n) { + n = p + 1U; + } + SCB->SHPR[7] = (uint8_t)(0xFEU << n); +#elif (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) + uint32_t n; + + SCB->SHPR[1] |= 0x00FF0000U; + n = SCB->SHPR[1]; + SCB->SHPR[0] |= (n << (8+1)) & 0xFC000000U; +#elif ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ != 0)) || \ + (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ != 0))) + uint32_t p, n; + + SCB->SHP[10] = 0xFFU; + n = 32U - (uint32_t)__CLZ(~(SCB->SHP[10] | 0xFFFFFF00U)); + p = NVIC_GetPriorityGrouping(); + if (p >= n) { + n = p + 1U; + } + SCB->SHP[7] = (uint8_t)(0xFEU << n); +#elif (defined(__ARM_ARCH_6M__) && (__ARM_ARCH_6M__ != 0)) + uint32_t n; + + SCB->SHP[1] |= 0x00FF0000U; + n = SCB->SHP[1]; + SCB->SHP[0] |= (n << (8+1)) & 0xFC000000U; +#endif +} + +/// Get Pending SV (Service Call) Flag +/// \return Pending SV Flag +__STATIC_INLINE uint8_t GetPendSV (void) { + return ((uint8_t)((SCB->ICSR & (SCB_ICSR_PENDSVSET_Msk)) >> 24)); +} + +/// Clear Pending SV (Service Call) Flag +__STATIC_INLINE void ClrPendSV (void) { + SCB->ICSR = SCB_ICSR_PENDSVCLR_Msk; +} + +/// Set Pending SV (Service Call) Flag +__STATIC_INLINE void SetPendSV (void) { + SCB->ICSR = SCB_ICSR_PENDSVSET_Msk; +} + + +// ==== Service Calls definitions ==== + +//lint -save -e9023 -e9024 -e9026 "Function-like macros using '#/##'" [MISRA Note 10] + +#if defined(__CC_ARM) + +#if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ != 0)) || \ + (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ != 0)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \ + (defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0))) +#define SVC_INDIRECT(n) __svc_indirect(n) +#elif ((defined(__ARM_ARCH_6M__) && (__ARM_ARCH_6M__ != 0)) || \ + (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))) +#define SVC_INDIRECT(n) __svc_indirect_r7(n) +#endif + +#define SVC0_0N(f,t) \ +SVC_INDIRECT(0) t svc##f (t(*)()); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (void) { \ + svc##f(svcRtx##f); \ +} + +#define SVC0_0(f,t) \ +SVC_INDIRECT(0) t svc##f (t(*)()); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (void) { \ + return svc##f(svcRtx##f); \ +} + +#define SVC0_1N(f,t,t1) \ +SVC_INDIRECT(0) t svc##f (t(*)(t1),t1); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1) { \ + svc##f(svcRtx##f,a1); \ +} + +#define SVC0_1(f,t,t1) \ +SVC_INDIRECT(0) t svc##f (t(*)(t1),t1); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1) { \ + return svc##f(svcRtx##f,a1); \ +} + +#define SVC0_2(f,t,t1,t2) \ +SVC_INDIRECT(0) t svc##f (t(*)(t1,t2),t1,t2); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1, t2 a2) { \ + return svc##f(svcRtx##f,a1,a2); \ +} + +#define SVC0_3(f,t,t1,t2,t3) \ +SVC_INDIRECT(0) t svc##f (t(*)(t1,t2,t3),t1,t2,t3); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) { \ + return svc##f(svcRtx##f,a1,a2,a3); \ +} + +#define SVC0_4(f,t,t1,t2,t3,t4) \ +SVC_INDIRECT(0) t svc##f (t(*)(t1,t2,t3,t4),t1,t2,t3,t4); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) { \ + return svc##f(svcRtx##f,a1,a2,a3,a4); \ +} + +#elif defined(__ICCARM__) + +#if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ != 0)) || \ + (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ != 0)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \ + (defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0))) +#define SVC_ArgF(f) \ + __asm( \ + "mov r12,%0\n" \ + :: "r"(&f): "r12" \ + ); +#elif ((defined(__ARM_ARCH_6M__) && (__ARM_ARCH_6M__ != 0)) || \ + (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))) +#define SVC_ArgF(f) \ + __asm( \ + "mov r7,%0\n" \ + :: "r"(&f): "r7" \ + ); +#endif + +#define STRINGIFY(a) #a +#define SVC_INDIRECT(n) _Pragma(STRINGIFY(swi_number = n)) __swi + +#define SVC0_0N(f,t) \ +SVC_INDIRECT(0) t svc##f (); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (void) { \ + SVC_ArgF(svcRtx##f); \ + svc##f(); \ +} + +#define SVC0_0(f,t) \ +SVC_INDIRECT(0) t svc##f (); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (void) { \ + SVC_ArgF(svcRtx##f); \ + return svc##f(); \ +} + +#define SVC0_1N(f,t,t1) \ +SVC_INDIRECT(0) t svc##f (t1 a1); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1) { \ + SVC_ArgF(svcRtx##f); \ + svc##f(a1); \ +} + +#define SVC0_1(f,t,t1) \ +SVC_INDIRECT(0) t svc##f (t1 a1); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1) { \ + SVC_ArgF(svcRtx##f); \ + return svc##f(a1); \ +} + +#define SVC0_2(f,t,t1,t2) \ +SVC_INDIRECT(0) t svc##f (t1 a1, t2 a2); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1, t2 a2) { \ + SVC_ArgF(svcRtx##f); \ + return svc##f(a1,a2); \ +} + +#define SVC0_3(f,t,t1,t2,t3) \ +SVC_INDIRECT(0) t svc##f (t1 a1, t2 a2, t3 a3); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) { \ + SVC_ArgF(svcRtx##f); \ + return svc##f(a1,a2,a3); \ +} + +#define SVC0_4(f,t,t1,t2,t3,t4) \ +SVC_INDIRECT(0) t svc##f (t1 a1, t2 a2, t3 a3, t4 a4); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) { \ + SVC_ArgF(svcRtx##f); \ + return svc##f(a1,a2,a3,a4); \ +} + +#else // !(defined(__CC_ARM) || defined(__ICCARM__)) + +//lint -esym(522,__svc*) "Functions '__svc*' are impure (side-effects)" + +#if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ != 0)) || \ + (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ != 0)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \ + (defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0))) +#define SVC_RegF "r12" +#elif ((defined(__ARM_ARCH_6M__) && (__ARM_ARCH_6M__ != 0)) || \ + (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))) +#define SVC_RegF "r7" +#endif + +#define SVC_ArgN(n) \ +register uint32_t __r##n __ASM("r"#n) + +#define SVC_ArgR(n,a) \ +register uint32_t __r##n __ASM("r"#n) = (uint32_t)a + +#define SVC_ArgF(f) \ +register uint32_t __rf __ASM(SVC_RegF) = (uint32_t)f + +#define SVC_In0 "r"(__rf) +#define SVC_In1 "r"(__rf),"r"(__r0) +#define SVC_In2 "r"(__rf),"r"(__r0),"r"(__r1) +#define SVC_In3 "r"(__rf),"r"(__r0),"r"(__r1),"r"(__r2) +#define SVC_In4 "r"(__rf),"r"(__r0),"r"(__r1),"r"(__r2),"r"(__r3) + +#define SVC_Out0 +#define SVC_Out1 "=r"(__r0) + +#define SVC_CL0 +#define SVC_CL1 "r1" +#define SVC_CL2 "r0","r1" + +#define SVC_Call0(in, out, cl) \ + __ASM volatile ("svc 0" : out : in : cl) + +#define SVC0_0N(f,t) \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (void) { \ + SVC_ArgF(svcRtx##f); \ + SVC_Call0(SVC_In0, SVC_Out0, SVC_CL2); \ +} + +#define SVC0_0(f,t) \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (void) { \ + SVC_ArgN(0); \ + SVC_ArgF(svcRtx##f); \ + SVC_Call0(SVC_In0, SVC_Out1, SVC_CL1); \ + return (t) __r0; \ +} + +#define SVC0_1N(f,t,t1) \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1) { \ + SVC_ArgR(0,a1); \ + SVC_ArgF(svcRtx##f); \ + SVC_Call0(SVC_In1, SVC_Out0, SVC_CL1); \ +} + +#define SVC0_1(f,t,t1) \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1) { \ + SVC_ArgR(0,a1); \ + SVC_ArgF(svcRtx##f); \ + SVC_Call0(SVC_In1, SVC_Out1, SVC_CL1); \ + return (t) __r0; \ +} + +#define SVC0_2(f,t,t1,t2) \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1, t2 a2) { \ + SVC_ArgR(0,a1); \ + SVC_ArgR(1,a2); \ + SVC_ArgF(svcRtx##f); \ + SVC_Call0(SVC_In2, SVC_Out1, SVC_CL0); \ + return (t) __r0; \ +} + +#define SVC0_3(f,t,t1,t2,t3) \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) { \ + SVC_ArgR(0,a1); \ + SVC_ArgR(1,a2); \ + SVC_ArgR(2,a3); \ + SVC_ArgF(svcRtx##f); \ + SVC_Call0(SVC_In3, SVC_Out1, SVC_CL0); \ + return (t) __r0; \ +} + +#define SVC0_4(f,t,t1,t2,t3,t4) \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) { \ + SVC_ArgR(0,a1); \ + SVC_ArgR(1,a2); \ + SVC_ArgR(2,a3); \ + SVC_ArgR(3,a4); \ + SVC_ArgF(svcRtx##f); \ + SVC_Call0(SVC_In4, SVC_Out1, SVC_CL0); \ + return (t) __r0; \ +} + +#endif + +//lint -restore [MISRA Note 10] + + +// ==== Exclusive Access Operation ==== + +#if (EXCLUSIVE_ACCESS == 1) + +//lint ++flb "Library Begin" [MISRA Note 12] + +/// Atomic Access Operation: Write (8-bit) +/// \param[in] mem Memory address +/// \param[in] val Value to write +/// \return Previous value +#if defined(__CC_ARM) +static __asm uint8_t atomic_wr8 (uint8_t *mem, uint8_t val) { + mov r2,r0 +1 + ldrexb r0,[r2] + strexb r3,r1,[r2] + cbz r3,%F2 + b %B1 +2 + bx lr +} +#else +__STATIC_INLINE uint8_t atomic_wr8 (uint8_t *mem, uint8_t val) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint8_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrexb %[ret],[%[mem]]\n\t" + "strexb %[res],%[val],[%[mem]]\n\t" + "cbz %[res],2f\n\t" + "b 1b\n" + "2:" + : [ret] "=&l" (ret), + [res] "=&l" (res) + : [mem] "l" (mem), + [val] "l" (val) + : "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Set bits (32-bit) +/// \param[in] mem Memory address +/// \param[in] bits Bit mask +/// \return New value +#if defined(__CC_ARM) +static __asm uint32_t atomic_set32 (uint32_t *mem, uint32_t bits) { + mov r2,r0 +1 + ldrex r0,[r2] + orr r0,r0,r1 + strex r3,r0,[r2] + cbz r3,%F2 + b %B1 +2 + bx lr +} +#else +__STATIC_INLINE uint32_t atomic_set32 (uint32_t *mem, uint32_t bits) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint32_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrex %[val],[%[mem]]\n\t" +#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) + "mov %[ret],%[val]\n\t" + "orrs %[ret],%[bits]\n\t" +#else + "orr %[ret],%[val],%[bits]\n\t" +#endif + "strex %[res],%[ret],[%[mem]]\n\t" + "cbz %[res],2f\n\t" + "b 1b\n" + "2:" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem), + [bits] "l" (bits) +#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) + : "memory", "cc" +#else + : "memory" +#endif + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Clear bits (32-bit) +/// \param[in] mem Memory address +/// \param[in] bits Bit mask +/// \return Previous value +#if defined(__CC_ARM) +static __asm uint32_t atomic_clr32 (uint32_t *mem, uint32_t bits) { + push {r4,lr} + mov r2,r0 +1 + ldrex r0,[r2] + bic r4,r0,r1 + strex r3,r4,[r2] + cbz r3,%F2 + b %B1 +2 + pop {r4,pc} +} +#else +__STATIC_INLINE uint32_t atomic_clr32 (uint32_t *mem, uint32_t bits) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint32_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrex %[ret],[%[mem]]\n\t" +#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) + "mov %[val],%[ret]\n\t" + "bics %[val],%[bits]\n\t" +#else + "bic %[val],%[ret],%[bits]\n\t" +#endif + "strex %[res],%[val],[%[mem]]\n\t" + "cbz %[res],2f\n\t" + "b 1b\n" + "2:" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem), + [bits] "l" (bits) +#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) + : "memory", "cc" +#else + : "memory" +#endif + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Check if all specified bits (32-bit) are active and clear them +/// \param[in] mem Memory address +/// \param[in] bits Bit mask +/// \return Active bits before clearing or 0 if not active +#if defined(__CC_ARM) +static __asm uint32_t atomic_chk32_all (uint32_t *mem, uint32_t bits) { + push {r4,lr} + mov r2,r0 +1 + ldrex r0,[r2] + and r4,r0,r1 + cmp r4,r1 + beq %F2 + clrex + movs r0,#0 + pop {r4,pc} +2 + bic r4,r0,r1 + strex r3,r4,[r2] + cbz r3,%F3 + b %B1 +3 + pop {r4,pc} +} +#else +__STATIC_INLINE uint32_t atomic_chk32_all (uint32_t *mem, uint32_t bits) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint32_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrex %[ret],[%[mem]]\n\t" +#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) + "mov %[val],%[ret]\n\t" + "ands %[val],%[bits]\n\t" +#else + "and %[val],%[ret],%[bits]\n\t" +#endif + "cmp %[val],%[bits]\n\t" + "beq 2f\n\t" + "clrex\n\t" + "movs %[ret],#0\n\t" + "b 3f\n" + "2:\n\t" +#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) + "mov %[val],%[ret]\n\t" + "bics %[val],%[bits]\n\t" +#else + "bic %[val],%[ret],%[bits]\n\t" +#endif + "strex %[res],%[val],[%[mem]]\n\t" + "cbz %[res],3f\n\t" + "b 1b\n" + "3:" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem), + [bits] "l" (bits) + : "cc", "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Check if any specified bits (32-bit) are active and clear them +/// \param[in] mem Memory address +/// \param[in] bits Bit mask +/// \return Active bits before clearing or 0 if not active +#if defined(__CC_ARM) +static __asm uint32_t atomic_chk32_any (uint32_t *mem, uint32_t bits) { + push {r4,lr} + mov r2,r0 +1 + ldrex r0,[r2] + tst r0,r1 + bne %F2 + clrex + movs r0,#0 + pop {r4,pc} +2 + bic r4,r0,r1 + strex r3,r4,[r2] + cbz r3,%F3 + b %B1 +3 + pop {r4,pc} +} +#else +__STATIC_INLINE uint32_t atomic_chk32_any (uint32_t *mem, uint32_t bits) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint32_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrex %[ret],[%[mem]]\n\t" + "tst %[ret],%[bits]\n\t" + "bne 2f\n\t" + "clrex\n\t" + "movs %[ret],#0\n\t" + "b 3f\n" + "2:\n\t" +#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) + "mov %[val],%[ret]\n\t" + "bics %[val],%[bits]\n\t" +#else + "bic %[val],%[ret],%[bits]\n\t" +#endif + "strex %[res],%[val],[%[mem]]\n\t" + "cbz %[res],3f\n\t" + "b 1b\n" + "3:" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem), + [bits] "l" (bits) + : "cc", "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Increment (32-bit) +/// \param[in] mem Memory address +/// \return Previous value +#if defined(__CC_ARM) +static __asm uint32_t atomic_inc32 (uint32_t *mem) { + mov r2,r0 +1 + ldrex r0,[r2] + adds r1,r0,#1 + strex r3,r1,[r2] + cbz r3,%F2 + b %B1 +2 + bx lr +} +#else +__STATIC_INLINE uint32_t atomic_inc32 (uint32_t *mem) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint32_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrex %[ret],[%[mem]]\n\t" + "adds %[val],%[ret],#1\n\t" + "strex %[res],%[val],[%[mem]]\n\t" + "cbz %[res],2f\n\t" + "b 1b\n" + "2:" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem) + : "cc", "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Increment (16-bit) if Less Than +/// \param[in] mem Memory address +/// \param[in] max Maximum value +/// \return Previous value +#if defined(__CC_ARM) +static __asm uint16_t atomic_inc16_lt (uint16_t *mem, uint16_t max) { + push {r4,lr} + mov r2,r0 +1 + ldrexh r0,[r2] + cmp r1,r0 + bhi %F2 + clrex + pop {r4,pc} +2 + adds r4,r0,#1 + strexh r3,r4,[r2] + cbz r3,%F3 + b %B1 +3 + pop {r4,pc} +} +#else +__STATIC_INLINE uint16_t atomic_inc16_lt (uint16_t *mem, uint16_t max) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint16_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrexh %[ret],[%[mem]]\n\t" + "cmp %[max],%[ret]\n\t" + "bhi 2f\n\t" + "clrex\n\t" + "b 3f\n" + "2:\n\t" + "adds %[val],%[ret],#1\n\t" + "strexh %[res],%[val],[%[mem]]\n\t" + "cbz %[res],3f\n\t" + "b 1b\n" + "3:" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem), + [max] "l" (max) + : "cc", "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Increment (16-bit) and clear on Limit +/// \param[in] mem Memory address +/// \param[in] max Maximum value +/// \return Previous value +#if defined(__CC_ARM) +static __asm uint16_t atomic_inc16_lim (uint16_t *mem, uint16_t lim) { + push {r4,lr} + mov r2,r0 +1 + ldrexh r0,[r2] + adds r4,r0,#1 + cmp r1,r4 + bhi %F2 + movs r4,#0 +2 + strexh r3,r4,[r2] + cbz r3,%F3 + b %B1 +3 + pop {r4,pc} +} +#else +__STATIC_INLINE uint16_t atomic_inc16_lim (uint16_t *mem, uint16_t lim) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint16_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrexh %[ret],[%[mem]]\n\t" + "adds %[val],%[ret],#1\n\t" + "cmp %[lim],%[val]\n\t" + "bhi 2f\n\t" + "movs %[val],#0\n" + "2:\n\t" + "strexh %[res],%[val],[%[mem]]\n\t" + "cbz %[res],3f\n\t" + "b 1b\n" + "3:" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem), + [lim] "l" (lim) + : "cc", "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Decrement (32-bit) +/// \param[in] mem Memory address +/// \return Previous value +#if defined(__CC_ARM) +static __asm uint32_t atomic_dec32 (uint32_t *mem) { + mov r2,r0 +1 + ldrex r0,[r2] + subs r1,r0,#1 + strex r3,r1,[r2] + cbz r3,%F2 + b %B1 +2 + bx lr +} +#else +__STATIC_INLINE uint32_t atomic_dec32 (uint32_t *mem) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint32_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrex %[ret],[%[mem]]\n\t" + "subs %[val],%[ret],#1\n\t" + "strex %[res],%[val],[%[mem]]\n\t" + "cbz %[res],2f\n\t" + "b 1b\n" + "2:" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem) + : "cc", "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Decrement (32-bit) if Not Zero +/// \param[in] mem Memory address +/// \return Previous value +#if defined(__CC_ARM) +static __asm uint32_t atomic_dec32_nz (uint32_t *mem) { + mov r2,r0 +1 + ldrex r0,[r2] + cbnz r0,%F2 + clrex + bx lr +2 + subs r1,r0,#1 + strex r3,r1,[r2] + cbz r3,%F3 + b %B1 +3 + bx lr +} +#else +__STATIC_INLINE uint32_t atomic_dec32_nz (uint32_t *mem) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint32_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrex %[ret],[%[mem]]\n\t" + "cbnz %[ret],2f\n\t" + "clrex\n\t" + "b 3f\n" + "2:\n\t" + "subs %[val],%[ret],#1\n\t" + "strex %[res],%[val],[%[mem]]\n\t" + "cbz %[res],3f\n\t" + "b 1b\n" + "3:" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem) + : "cc", "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Decrement (16-bit) if Not Zero +/// \param[in] mem Memory address +/// \return Previous value +#if defined(__CC_ARM) +static __asm uint16_t atomic_dec16_nz (uint16_t *mem) { + mov r2,r0 +1 + ldrexh r0,[r2] + cbnz r0,%F2 + clrex + bx lr +2 + subs r1,r0,#1 + strexh r3,r1,[r2] + cbz r3,%F3 + b %B1 +3 + bx lr +} +#else +__STATIC_INLINE uint16_t atomic_dec16_nz (uint16_t *mem) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint16_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrexh %[ret],[%[mem]]\n\t" + "cbnz %[ret],2f\n\t" + "clrex\n\t" + "b 3f\n" + "2:\n\t" + "subs %[val],%[ret],#1\n\t" + "strexh %[res],%[val],[%[mem]]\n\t" + "cbz %[res],3f\n\t" + "b 1b\n" + "3:" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem) + : "cc", "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Link Get +/// \param[in] root Root address +/// \return Link +#if defined(__CC_ARM) +static __asm void *atomic_link_get (void **root) { + mov r2,r0 +1 + ldrex r0,[r2] + cbnz r0,%F2 + clrex + bx lr +2 + ldr r1,[r0] + strex r3,r1,[r2] + cbz r3,%F3 + b %B1 +3 + bx lr +} +#else +__STATIC_INLINE void *atomic_link_get (void **root) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register void *ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrex %[ret],[%[root]]\n\t" + "cbnz %[ret],2f\n\t" + "clrex\n\t" + "b 3f\n" + "2:\n\t" + "ldr %[val],[%[ret]]\n\t" + "strex %[res],%[val],[%[root]]\n\t" + "cbz %[res],3f\n\t" + "b 1b\n" + "3:" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [root] "l" (root) + : "cc", "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Link Put +/// \param[in] root Root address +/// \param[in] lnk Link +#if defined(__CC_ARM) +static __asm void atomic_link_put (void **root, void *link) { +1 + ldr r2,[r0] + str r2,[r1] + dmb + ldrex r2,[r0] + ldr r3,[r1] + cmp r3,r2 + bne %B1 + strex r3,r1,[r0] + cbz r3,%F2 + b %B1 +2 + bx lr +} +#else +__STATIC_INLINE void atomic_link_put (void **root, void *link) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val1, val2, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldr %[val1],[%[root]]\n\t" + "str %[val1],[%[link]]\n\t" + "dmb\n\t" + "ldrex %[val1],[%[root]]\n\t" + "ldr %[val2],[%[link]]\n\t" + "cmp %[val2],%[val1]\n\t" + "bne 1b\n\t" + "strex %[res],%[link],[%[root]]\n\t" + "cbz %[res],2f\n\t" + "b 1b\n" + "2:" + : [val1] "=&l" (val1), + [val2] "=&l" (val2), + [res] "=&l" (res) + : [root] "l" (root), + [link] "l" (link) + : "cc", "memory" + ); +} +#endif + +//lint --flb "Library End" [MISRA Note 12] + +#endif // (EXCLUSIVE_ACCESS == 1) + + +#endif // RTX_CORE_CM_H_ diff --git a/CMSIS/RTOS2/RTX/Source/rtx_lib.c b/CMSIS/RTOS2/RTX/Source/rtx_lib.c new file mode 100644 index 0000000..7066316 --- /dev/null +++ b/CMSIS/RTOS2/RTX/Source/rtx_lib.c @@ -0,0 +1,770 @@ +/* + * Copyright (c) 2013-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: RTX Library Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" + +#ifdef RTE_Compiler_EventRecorder +#include "EventRecorder.h" +#include "EventRecorderConf.h" +#endif +#include "rtx_evr.h" + + +// System Configuration +// ==================== + +// Dynamic Memory +#if (OS_DYNAMIC_MEM_SIZE != 0) +#if ((OS_DYNAMIC_MEM_SIZE % 8) != 0) +#error "Invalid Dynamic Memory size!" +#endif +static uint64_t os_mem[OS_DYNAMIC_MEM_SIZE/8] \ +__attribute__((section(".bss.os"))); +#endif + +// Kernel Tick Frequency +#if (OS_TICK_FREQ < 1) +#error "Invalid Kernel Tick Frequency!" +#endif + +// ISR FIFO Queue +#if (OS_ISR_FIFO_QUEUE < 4) +#error "Invalid ISR FIFO Queue size!" +#endif +static void *os_isr_queue[OS_ISR_FIFO_QUEUE] \ +__attribute__((section(".bss.os"))); + + +// Thread Configuration +// ==================== + +#if (((OS_STACK_SIZE % 8) != 0) || (OS_STACK_SIZE < 72)) +#error "Invalid default Thread Stack size!" +#endif + +#if (((OS_IDLE_THREAD_STACK_SIZE % 8) != 0) || (OS_IDLE_THREAD_STACK_SIZE < 72)) +#error "Invalid Idle Thread Stack size!" +#endif + + +#if (OS_THREAD_OBJ_MEM != 0) + +#if (OS_THREAD_NUM == 0) +#error "Invalid number of user Threads!" +#endif + +#if ((OS_THREAD_USER_STACK_SIZE != 0) && ((OS_THREAD_USER_STACK_SIZE % 8) != 0)) +#error "Invalid total Stack size!" +#endif + +// Thread Control Blocks +static osRtxThread_t os_thread_cb[OS_THREAD_NUM] \ +__attribute__((section(".bss.os.thread.cb"))); + +// Thread Default Stack +#if (OS_THREAD_DEF_STACK_NUM != 0) +static uint64_t os_thread_def_stack[(OS_THREAD_DEF_STACK_NUM*OS_STACK_SIZE)/8] \ +__attribute__((section(".bss.os.thread.stack"))); +#endif + +// Memory Pool for Thread Control Blocks +static osRtxMpInfo_t os_mpi_thread \ +__attribute__((section(".data.os.thread.mpi"))) = +{ (uint32_t)OS_THREAD_NUM, 0U, (uint32_t)osRtxThreadCbSize, &os_thread_cb[0], NULL, NULL }; + +// Memory Pool for Thread Default Stack +#if (OS_THREAD_DEF_STACK_NUM != 0) +static osRtxMpInfo_t os_mpi_def_stack \ +__attribute__((section(".data.os.thread.mpi"))) = +{ (uint32_t)OS_THREAD_DEF_STACK_NUM, 0U, (uint32_t)OS_STACK_SIZE, &os_thread_def_stack[0], NULL, NULL }; +#endif + +// Memory Pool for Thread Stack +#if (OS_THREAD_USER_STACK_SIZE != 0) +static uint64_t os_thread_stack[(16 + (8*OS_THREAD_NUM) + OS_THREAD_USER_STACK_SIZE)/8] \ +__attribute__((section(".bss.os.thread.stack"))); +#endif + +#endif // (OS_THREAD_OBJ_MEM != 0) + + +// Idle Thread Control Block +static osRtxThread_t os_idle_thread_cb \ +__attribute__((section(".bss.os.thread.cb"))); + +// Idle Thread Stack +static uint64_t os_idle_thread_stack[OS_IDLE_THREAD_STACK_SIZE/8] \ +__attribute__((section(".bss.os.thread.idle.stack"))); + +// Idle Thread Attributes +static const osThreadAttr_t os_idle_thread_attr = { +#if defined(OS_IDLE_THREAD_NAME) + OS_IDLE_THREAD_NAME, +#else + NULL, +#endif + osThreadDetached, + &os_idle_thread_cb, + (uint32_t)sizeof(os_idle_thread_cb), + &os_idle_thread_stack[0], + (uint32_t)sizeof(os_idle_thread_stack), + osPriorityIdle, +#if defined(OS_IDLE_THREAD_TZ_MOD_ID) + (uint32_t)OS_IDLE_THREAD_TZ_MOD_ID, +#else + 0U, +#endif + 0U +}; + + +// Timer Configuration +// =================== + +#if (OS_TIMER_OBJ_MEM != 0) + +#if (OS_TIMER_NUM == 0) +#error "Invalid number of Timer objects!" +#endif + +// Timer Control Blocks +static osRtxTimer_t os_timer_cb[OS_TIMER_NUM] \ +__attribute__((section(".bss.os.timer.cb"))); + +// Memory Pool for Timer Control Blocks +static osRtxMpInfo_t os_mpi_timer \ +__attribute__((section(".data.os.timer.mpi"))) = +{ (uint32_t)OS_TIMER_NUM, 0U, (uint32_t)osRtxTimerCbSize, &os_timer_cb[0], NULL, NULL }; + +#endif // (OS_TIMER_OBJ_MEM != 0) + + +#if ((OS_TIMER_THREAD_STACK_SIZE != 0) && (OS_TIMER_CB_QUEUE != 0)) + +#if (((OS_TIMER_THREAD_STACK_SIZE % 8) != 0) || (OS_TIMER_THREAD_STACK_SIZE < 96)) +#error "Invalid Timer Thread Stack size!" +#endif + +// Timer Thread Control Block +static osRtxThread_t os_timer_thread_cb \ +__attribute__((section(".bss.os.thread.cb"))); + +// Timer Thread Stack +static uint64_t os_timer_thread_stack[OS_TIMER_THREAD_STACK_SIZE/8] \ +__attribute__((section(".bss.os.thread.timer.stack"))); + +// Timer Thread Attributes +static const osThreadAttr_t os_timer_thread_attr = { +#if defined(OS_TIMER_THREAD_NAME) + OS_TIMER_THREAD_NAME, +#else + NULL, +#endif + osThreadDetached, + &os_timer_thread_cb, + (uint32_t)sizeof(os_timer_thread_cb), + &os_timer_thread_stack[0], + (uint32_t)sizeof(os_timer_thread_stack), + //lint -e{9030} -e{9034} "cast from signed to enum" + (osPriority_t)OS_TIMER_THREAD_PRIO, +#if defined(OS_TIMER_THREAD_TZ_MOD_ID) + (uint32_t)OS_TIMER_THREAD_TZ_MOD_ID, +#else + 0U, +#endif + 0U +}; + +// Timer Message Queue Control Block +static osRtxMessageQueue_t os_timer_mq_cb \ +__attribute__((section(".bss.os.msgqueue.cb"))); + +// Timer Message Queue Data +static uint32_t os_timer_mq_data[osRtxMessageQueueMemSize(OS_TIMER_CB_QUEUE,8)/4] \ +__attribute__((section(".bss.os.msgqueue.mem"))); + +// Timer Message Queue Attributes +static const osMessageQueueAttr_t os_timer_mq_attr = { + NULL, + 0U, + &os_timer_mq_cb, + (uint32_t)sizeof(os_timer_mq_cb), + &os_timer_mq_data[0], + (uint32_t)sizeof(os_timer_mq_data) +}; + +extern int32_t osRtxTimerSetup (void); +extern void osRtxTimerThread (void *argument); + +#endif // ((OS_TIMER_THREAD_STACK_SIZE != 0) && (OS_TIMER_CB_QUEUE != 0)) + + +// Event Flags Configuration +// ========================= + +#if (OS_EVFLAGS_OBJ_MEM != 0) + +#if (OS_EVFLAGS_NUM == 0) +#error "Invalid number of Event Flags objects!" +#endif + +// Event Flags Control Blocks +static osRtxEventFlags_t os_ef_cb[OS_EVFLAGS_NUM] \ +__attribute__((section(".bss.os.evflags.cb"))); + +// Memory Pool for Event Flags Control Blocks +static osRtxMpInfo_t os_mpi_ef \ +__attribute__((section(".data.os.evflags.mpi"))) = +{ (uint32_t)OS_EVFLAGS_NUM, 0U, (uint32_t)osRtxEventFlagsCbSize, &os_ef_cb[0], NULL, NULL }; + +#endif // (OS_EVFLAGS_OBJ_MEM != 0) + + +// Mutex Configuration +// =================== + +#if (OS_MUTEX_OBJ_MEM != 0) + +#if (OS_MUTEX_NUM == 0) +#error "Invalid number of Mutex objects!" +#endif + +// Mutex Control Blocks +static osRtxMutex_t os_mutex_cb[OS_MUTEX_NUM] \ +__attribute__((section(".bss.os.mutex.cb"))); + +// Memory Pool for Mutex Control Blocks +static osRtxMpInfo_t os_mpi_mutex \ +__attribute__((section(".data.os.mutex.mpi"))) = +{ (uint32_t)OS_MUTEX_NUM, 0U, (uint32_t)osRtxMutexCbSize, &os_mutex_cb[0], NULL, NULL }; + +#endif // (OS_MUTEX_OBJ_MEM != 0) + + +// Semaphore Configuration +// ======================= + +#if (OS_SEMAPHORE_OBJ_MEM != 0) + +#if (OS_SEMAPHORE_NUM == 0) +#error "Invalid number of Semaphore objects!" +#endif + +// Semaphore Control Blocks +static osRtxSemaphore_t os_semaphore_cb[OS_SEMAPHORE_NUM] \ +__attribute__((section(".bss.os.semaphore.cb"))); + +// Memory Pool for Semaphore Control Blocks +static osRtxMpInfo_t os_mpi_semaphore \ +__attribute__((section(".data.os.semaphore.mpi"))) = +{ (uint32_t)OS_SEMAPHORE_NUM, 0U, (uint32_t)osRtxSemaphoreCbSize, &os_semaphore_cb[0], NULL, NULL }; + +#endif // (OS_SEMAPHORE_OBJ_MEM != 0) + + +// Memory Pool Configuration +// ========================= + +#if (OS_MEMPOOL_OBJ_MEM != 0) + +#if (OS_MEMPOOL_NUM == 0) +#error "Invalid number of Memory Pool objects!" +#endif + +// Memory Pool Control Blocks +static osRtxMemoryPool_t os_mp_cb[OS_MEMPOOL_NUM] \ +__attribute__((section(".bss.os.mempool.cb"))); + +// Memory Pool for Memory Pool Control Blocks +static osRtxMpInfo_t os_mpi_mp \ +__attribute__((section(".data.os.mempool.mpi"))) = +{ (uint32_t)OS_MEMPOOL_NUM, 0U, (uint32_t)osRtxMemoryPoolCbSize, &os_mp_cb[0], NULL, NULL }; + +// Memory Pool for Memory Pool Data Storage +#if (OS_MEMPOOL_DATA_SIZE != 0) +#if ((OS_MEMPOOL_DATA_SIZE % 8) != 0) +#error "Invalid Data Memory size for Memory Pools!" +#endif +static uint64_t os_mp_data[(16 + (8*OS_MEMPOOL_NUM) + OS_MEMPOOL_DATA_SIZE)/8] \ +__attribute__((section(".bss.os.mempool.mem"))); +#endif + +#endif // (OS_MEMPOOL_OBJ_MEM != 0) + + +// Message Queue Configuration +// =========================== + +#if (OS_MSGQUEUE_OBJ_MEM != 0) + +#if (OS_MSGQUEUE_NUM == 0) +#error "Invalid number of Message Queue objects!" +#endif + +// Message Queue Control Blocks +static osRtxMessageQueue_t os_mq_cb[OS_MSGQUEUE_NUM] \ +__attribute__((section(".bss.os.msgqueue.cb"))); + +// Memory Pool for Message Queue Control Blocks +static osRtxMpInfo_t os_mpi_mq \ +__attribute__((section(".data.os.msgqueue.mpi"))) = +{ (uint32_t)OS_MSGQUEUE_NUM, 0U, (uint32_t)osRtxMessageQueueCbSize, &os_mq_cb[0], NULL, NULL }; + +// Memory Pool for Message Queue Data Storage +#if (OS_MSGQUEUE_DATA_SIZE != 0) +#if ((OS_MSGQUEUE_DATA_SIZE % 8) != 0) +#error "Invalid Data Memory size for Message Queues!" +#endif +static uint64_t os_mq_data[(16 + ((8+12)*OS_MSGQUEUE_NUM) + OS_MSGQUEUE_DATA_SIZE + 7)/8] \ +__attribute__((section(".bss.os.msgqueue.mem"))); +#endif + +#endif // (OS_MSGQUEUE_OBJ_MEM != 0) + + +// Event Recorder Configuration +// ============================ + +#if (defined(OS_EVR_INIT) && (OS_EVR_INIT != 0)) + +#ifdef RTE_Compiler_EventRecorder + +// Event Recorder Initialize +__STATIC_INLINE void evr_initialize (void) { + + (void)EventRecorderInitialize(OS_EVR_LEVEL, (uint32_t)OS_EVR_START); + +#if ((OS_EVR_MEMORY_LEVEL & 0x80U) != 0U) + (void)EventRecorderEnable( OS_EVR_MEMORY_LEVEL & 0x0FU, EvtRtxMemoryNo, EvtRtxMemoryNo); + (void)EventRecorderDisable(~OS_EVR_MEMORY_LEVEL & 0x0FU, EvtRtxMemoryNo, EvtRtxMemoryNo); +#endif +#if ((OS_EVR_KERNEL_LEVEL & 0x80U) != 0U) + (void)EventRecorderEnable( OS_EVR_KERNEL_LEVEL & 0x0FU, EvtRtxKernelNo, EvtRtxKernelNo); + (void)EventRecorderDisable(~OS_EVR_KERNEL_LEVEL & 0x0FU, EvtRtxKernelNo, EvtRtxMemoryNo); +#endif +#if ((OS_EVR_THREAD_LEVEL & 0x80U) != 0U) + (void)EventRecorderEnable( OS_EVR_THREAD_LEVEL & 0x0FU, EvtRtxThreadNo, EvtRtxThreadNo); + (void)EventRecorderDisable(~OS_EVR_THREAD_LEVEL & 0x0FU, EvtRtxThreadNo, EvtRtxThreadNo); +#endif +#if ((OS_EVR_WAIT_LEVEL & 0x80U) != 0U) + (void)EventRecorderEnable( OS_EVR_WAIT_LEVEL & 0x0FU, EvtRtxWaitNo, EvtRtxWaitNo); + (void)EventRecorderDisable(~OS_EVR_WAIT_LEVEL & 0x0FU, EvtRtxWaitNo, EvtRtxWaitNo); +#endif +#if ((OS_EVR_THFLAGS_LEVEL & 0x80U) != 0U) + (void)EventRecorderEnable( OS_EVR_THFLAGS_LEVEL & 0x0FU, EvtRtxThreadFlagsNo, EvtRtxThreadFlagsNo); + (void)EventRecorderDisable(~OS_EVR_THFLAGS_LEVEL & 0x0FU, EvtRtxThreadFlagsNo, EvtRtxThreadFlagsNo); +#endif +#if ((OS_EVR_EVFLAGS_LEVEL & 0x80U) != 0U) + (void)EventRecorderEnable( OS_EVR_EVFLAGS_LEVEL & 0x0FU, EvtRtxEventFlagsNo, EvtRtxEventFlagsNo); + (void)EventRecorderDisable(~OS_EVR_EVFLAGS_LEVEL & 0x0FU, EvtRtxEventFlagsNo, EvtRtxEventFlagsNo); +#endif +#if ((OS_EVR_TIMER_LEVEL & 0x80U) != 0U) + (void)EventRecorderEnable( OS_EVR_TIMER_LEVEL & 0x0FU, EvtRtxTimerNo, EvtRtxTimerNo); + (void)EventRecorderDisable(~OS_EVR_TIMER_LEVEL & 0x0FU, EvtRtxTimerNo, EvtRtxTimerNo); +#endif +#if ((OS_EVR_MUTEX_LEVEL & 0x80U) != 0U) + (void)EventRecorderEnable( OS_EVR_MUTEX_LEVEL & 0x0FU, EvtRtxMutexNo, EvtRtxMutexNo); + (void)EventRecorderDisable(~OS_EVR_MUTEX_LEVEL & 0x0FU, EvtRtxMutexNo, EvtRtxMutexNo); +#endif +#if ((OS_EVR_SEMAPHORE_LEVEL & 0x80U) != 0U) + (void)EventRecorderEnable( OS_EVR_SEMAPHORE_LEVEL & 0x0FU, EvtRtxSemaphoreNo, EvtRtxSemaphoreNo); + (void)EventRecorderDisable(~OS_EVR_SEMAPHORE_LEVEL & 0x0FU, EvtRtxSemaphoreNo, EvtRtxSemaphoreNo); +#endif +#if ((OS_EVR_MEMPOOL_LEVEL & 0x80U) != 0U) + (void)EventRecorderEnable( OS_EVR_MEMPOOL_LEVEL & 0x0FU, EvtRtxMemoryPoolNo, EvtRtxMemoryPoolNo); + (void)EventRecorderDisable(~OS_EVR_MEMPOOL_LEVEL & 0x0FU, EvtRtxMemoryPoolNo, EvtRtxMemoryPoolNo); +#endif +#if ((OS_EVR_MSGQUEUE_LEVEL & 0x80U) != 0U) + (void)EventRecorderEnable( OS_EVR_MSGQUEUE_LEVEL & 0x0FU, EvtRtxMessageQueueNo, EvtRtxMessageQueueNo); + (void)EventRecorderDisable(~OS_EVR_MSGQUEUE_LEVEL & 0x0FU, EvtRtxMessageQueueNo, EvtRtxMessageQueueNo); +#endif +} + +#else +#warning "Event Recorder cannot be initialized (Event Recorder component is not selected)!" +#define evr_initialize() +#endif + +#endif // (OS_EVR_INIT != 0) + + +// OS Configuration +// ================ + + +const osRtxConfig_t osRtxConfig \ +__USED \ +__attribute__((section(".rodata"))) = +{ + //lint -e{835} "Zero argument to operator" + 0U // Flags +#if (OS_PRIVILEGE_MODE != 0) + | osRtxConfigPrivilegedMode +#endif +#if (OS_STACK_CHECK != 0) + | osRtxConfigStackCheck +#endif +#if (OS_STACK_WATERMARK != 0) + | osRtxConfigStackWatermark +#endif + , + (uint32_t)OS_TICK_FREQ, +#if (OS_ROBIN_ENABLE != 0) + (uint32_t)OS_ROBIN_TIMEOUT, +#else + 0U, +#endif + { &os_isr_queue[0], (uint16_t)(sizeof(os_isr_queue)/sizeof(void *)), 0U }, + { + // Memory Pools (Variable Block Size) +#if ((OS_THREAD_OBJ_MEM != 0) && (OS_THREAD_USER_STACK_SIZE != 0)) + &os_thread_stack[0], sizeof(os_thread_stack), +#else + NULL, 0U, +#endif +#if ((OS_MEMPOOL_OBJ_MEM != 0) && (OS_MEMPOOL_DATA_SIZE != 0)) + &os_mp_data[0], sizeof(os_mp_data), +#else + NULL, 0U, +#endif +#if ((OS_MSGQUEUE_OBJ_MEM != 0) && (OS_MSGQUEUE_DATA_SIZE != 0)) + &os_mq_data[0], sizeof(os_mq_data), +#else + NULL, 0U, +#endif +#if (OS_DYNAMIC_MEM_SIZE != 0) + &os_mem[0], (uint32_t)OS_DYNAMIC_MEM_SIZE, +#else + NULL, 0U +#endif + }, + { + // Memory Pools (Fixed Block Size) +#if (OS_THREAD_OBJ_MEM != 0) +#if (OS_THREAD_DEF_STACK_NUM != 0) + &os_mpi_def_stack, +#else + NULL, +#endif + &os_mpi_thread, +#else + NULL, + NULL, +#endif +#if (OS_TIMER_OBJ_MEM != 0) + &os_mpi_timer, +#else + NULL, +#endif +#if (OS_EVFLAGS_OBJ_MEM != 0) + &os_mpi_ef, +#else + NULL, +#endif +#if (OS_MUTEX_OBJ_MEM != 0) + &os_mpi_mutex, +#else + NULL, +#endif +#if (OS_SEMAPHORE_OBJ_MEM != 0) + &os_mpi_semaphore, +#else + NULL, +#endif +#if (OS_MEMPOOL_OBJ_MEM != 0) + &os_mpi_mp, +#else + NULL, +#endif +#if (OS_MSGQUEUE_OBJ_MEM != 0) + &os_mpi_mq, +#else + NULL, +#endif + }, + (uint32_t)OS_STACK_SIZE, + &os_idle_thread_attr, +#if ((OS_TIMER_THREAD_STACK_SIZE != 0) && (OS_TIMER_CB_QUEUE != 0)) + &os_timer_thread_attr, + osRtxTimerThread, + osRtxTimerSetup, + &os_timer_mq_attr, + (uint32_t)OS_TIMER_CB_QUEUE +#else + NULL, + NULL, + NULL, + NULL, + 0U +#endif +}; + + +// Non weak reference to library irq module +//lint -esym(526,irqRtxLib) "Defined by Exception handlers" +//lint -esym(714,irqRtxLibRef) "Non weak reference" +//lint -esym(765,irqRtxLibRef) "Global scope" +extern const uint8_t irqRtxLib; +extern const uint8_t * const irqRtxLibRef; + const uint8_t * const irqRtxLibRef = &irqRtxLib; + +// Default User SVC Table +//lint -esym(714,osRtxUserSVC) "Referenced by Exception handlers" +//lint -esym(765,osRtxUserSVC) "Global scope" +//lint -e{9067} "extern array declared without size" +extern void * const osRtxUserSVC[]; +__WEAK void * const osRtxUserSVC[1] = { (void *)0 }; + + +// OS Sections +// =========== + +#if defined(__CC_ARM) || \ + (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +// Initialized through linker +//lint -esym(728, __os_thread_cb_start__, __os_thread_cb_end__) +//lint -esym(728, __os_timer_cb_start__, __os_timer_cb_end__) +//lint -esym(728, __os_evflags_cb_start__, __os_evflags_cb_end__) +//lint -esym(728, __os_mutex_cb_start__, __os_mutex_cb_end__) +//lint -esym(728, __os_semaphore_cb_start__, __os_semaphore_cb_end__) +//lint -esym(728, __os_mempool_cb_start__, __os_mempool_cb_end__) +//lint -esym(728, __os_msgqueue_cb_start__, __os_msgqueue_cb_end__) +static const uint32_t __os_thread_cb_start__ __attribute__((weakref(".bss.os.thread.cb$$Base"))); +static const uint32_t __os_thread_cb_end__ __attribute__((weakref(".bss.os.thread.cb$$Limit"))); +static const uint32_t __os_timer_cb_start__ __attribute__((weakref(".bss.os.timer.cb$$Base"))); +static const uint32_t __os_timer_cb_end__ __attribute__((weakref(".bss.os.timer.cb$$Limit"))); +static const uint32_t __os_evflags_cb_start__ __attribute__((weakref(".bss.os.evflags.cb$$Base"))); +static const uint32_t __os_evflags_cb_end__ __attribute__((weakref(".bss.os.evflags.cb$$Limit"))); +static const uint32_t __os_mutex_cb_start__ __attribute__((weakref(".bss.os.mutex.cb$$Base"))); +static const uint32_t __os_mutex_cb_end__ __attribute__((weakref(".bss.os.mutex.cb$$Limit"))); +static const uint32_t __os_semaphore_cb_start__ __attribute__((weakref(".bss.os.semaphore.cb$$Base"))); +static const uint32_t __os_semaphore_cb_end__ __attribute__((weakref(".bss.os.semaphore.cb$$Limit"))); +static const uint32_t __os_mempool_cb_start__ __attribute__((weakref(".bss.os.mempool.cb$$Base"))); +static const uint32_t __os_mempool_cb_end__ __attribute__((weakref(".bss.os.mempool.cb$$Limit"))); +static const uint32_t __os_msgqueue_cb_start__ __attribute__((weakref(".bss.os.msgqueue.cb$$Base"))); +static const uint32_t __os_msgqueue_cb_end__ __attribute__((weakref(".bss.os.msgqueue.cb$$Limit"))); +#else +extern const uint32_t __os_thread_cb_start__ __attribute__((weak)); +extern const uint32_t __os_thread_cb_end__ __attribute__((weak)); +extern const uint32_t __os_timer_cb_start__ __attribute__((weak)); +extern const uint32_t __os_timer_cb_end__ __attribute__((weak)); +extern const uint32_t __os_evflags_cb_start__ __attribute__((weak)); +extern const uint32_t __os_evflags_cb_end__ __attribute__((weak)); +extern const uint32_t __os_mutex_cb_start__ __attribute__((weak)); +extern const uint32_t __os_mutex_cb_end__ __attribute__((weak)); +extern const uint32_t __os_semaphore_cb_start__ __attribute__((weak)); +extern const uint32_t __os_semaphore_cb_end__ __attribute__((weak)); +extern const uint32_t __os_mempool_cb_start__ __attribute__((weak)); +extern const uint32_t __os_mempool_cb_end__ __attribute__((weak)); +extern const uint32_t __os_msgqueue_cb_start__ __attribute__((weak)); +extern const uint32_t __os_msgqueue_cb_end__ __attribute__((weak)); +#endif + +//lint -e{9067} "extern array declared without size" +extern const uint32_t * const os_cb_sections[]; + +//lint -esym(714,os_cb_sections) "Referenced by debugger" +//lint -esym(765,os_cb_sections) "Global scope" +const uint32_t * const os_cb_sections[] \ +__USED \ +__attribute__((section(".rodata"))) = +{ + &__os_thread_cb_start__, + &__os_thread_cb_end__, + &__os_timer_cb_start__, + &__os_timer_cb_end__, + &__os_evflags_cb_start__, + &__os_evflags_cb_end__, + &__os_mutex_cb_start__, + &__os_mutex_cb_end__, + &__os_semaphore_cb_start__, + &__os_semaphore_cb_end__, + &__os_mempool_cb_start__, + &__os_mempool_cb_end__, + &__os_msgqueue_cb_start__, + &__os_msgqueue_cb_end__ +}; + + +// OS Initialization +// ================= + +#if defined(__CC_ARM) || \ + (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + +#ifndef __MICROLIB +//lint -esym(714,_platform_post_stackheap_init) "Referenced by C library" +//lint -esym(765,_platform_post_stackheap_init) "Global scope" +extern void _platform_post_stackheap_init (void); +__WEAK void _platform_post_stackheap_init (void) { + (void)osKernelInitialize(); +} +#endif + +#elif defined(__GNUC__) + +extern void software_init_hook (void); +__WEAK void software_init_hook (void) { + (void)osKernelInitialize(); +} + +#elif defined(__ICCARM__) + +extern void $Super$$__iar_data_init3 (void); +void $Sub$$__iar_data_init3 (void) { + $Super$$__iar_data_init3(); + (void)osKernelInitialize(); +} + +#endif + + +// OS Hooks +// ======== + +// RTOS Kernel Pre-Initialization Hook +#if (defined(OS_EVR_INIT) && (OS_EVR_INIT != 0)) +void osRtxKernelPreInit (void); +void osRtxKernelPreInit (void) { + if (osKernelGetState() == osKernelInactive) { + evr_initialize(); + } +} +#endif + + +// C/C++ Standard Library Multithreading Interface +// =============================================== + +#if ( !defined(RTX_NO_MULTITHREAD_CLIB) && \ + ( defined(__CC_ARM) || \ + (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))) && \ + !defined(__MICROLIB)) + +#define LIBSPACE_SIZE 96 + +//lint -esym(714,__user_perthread_libspace,_mutex_*) "Referenced by C library" +//lint -esym(765,__user_perthread_libspace,_mutex_*) "Global scope" +//lint -esym(9003, os_libspace*) "variables 'os_libspace*' defined at module scope" + +// Memory for libspace +static uint32_t os_libspace[OS_THREAD_LIBSPACE_NUM+1][LIBSPACE_SIZE/4] \ +__attribute__((section(".bss.os.libspace"))); + +// Thread IDs for libspace +static osThreadId_t os_libspace_id[OS_THREAD_LIBSPACE_NUM] \ +__attribute__((section(".bss.os.libspace"))); + +// Check if Kernel has been started +static uint32_t os_kernel_is_active (void) { + static uint8_t os_kernel_active = 0U; + + if (os_kernel_active == 0U) { + if (osKernelGetState() > osKernelReady) { + os_kernel_active = 1U; + } + } + return (uint32_t)os_kernel_active; +} + +// Provide libspace for current thread +void *__user_perthread_libspace (void); +void *__user_perthread_libspace (void) { + osThreadId_t id; + uint32_t n; + + if (os_kernel_is_active() != 0U) { + id = osThreadGetId(); + for (n = 0U; n < (uint32_t)OS_THREAD_LIBSPACE_NUM; n++) { + if (os_libspace_id[n] == NULL) { + os_libspace_id[n] = id; + } + if (os_libspace_id[n] == id) { + break; + } + } + if (n == (uint32_t)OS_THREAD_LIBSPACE_NUM) { + (void)osRtxKernelErrorNotify(osRtxErrorClibSpace, id); + } + } else { + n = OS_THREAD_LIBSPACE_NUM; + } + + //lint -e{9087} "cast between pointers to different object types" + return (void *)&os_libspace[n][0]; +} + +// Mutex identifier +typedef void *mutex; + +//lint -save "Function prototypes defined in C library" +//lint -e970 "Use of 'int' outside of a typedef" +//lint -e818 "Pointer 'm' could be declared as pointing to const" + +// Initialize mutex +__USED +int _mutex_initialize(mutex *m); +int _mutex_initialize(mutex *m) { + int result; + + *m = osMutexNew(NULL); + if (*m != NULL) { + result = 1; + } else { + result = 0; + (void)osRtxKernelErrorNotify(osRtxErrorClibMutex, m); + } + return result; +} + +// Acquire mutex +__USED +void _mutex_acquire(mutex *m); +void _mutex_acquire(mutex *m) { + if (os_kernel_is_active() != 0U) { + (void)osMutexAcquire(*m, osWaitForever); + } +} + +// Release mutex +__USED +void _mutex_release(mutex *m); +void _mutex_release(mutex *m) { + if (os_kernel_is_active() != 0U) { + (void)osMutexRelease(*m); + } +} + +// Free mutex +__USED +void _mutex_free(mutex *m); +void _mutex_free(mutex *m) { + (void)osMutexDelete(*m); +} + +//lint -restore + +#endif diff --git a/CMSIS/RTOS2/RTX/Source/rtx_lib.h b/CMSIS/RTOS2/RTX/Source/rtx_lib.h new file mode 100644 index 0000000..242f36f --- /dev/null +++ b/CMSIS/RTOS2/RTX/Source/rtx_lib.h @@ -0,0 +1,224 @@ +/* + * Copyright (c) 2013-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: RTX Library definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_LIB_H_ +#define RTX_LIB_H_ + +#include +#include "rtx_def.h" // RTX Configuration definitions +#include "rtx_core_c.h" // Cortex core definitions +#if ((defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \ + (defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0))) +#include "tz_context.h" // TrustZone Context API +#endif +#include "os_tick.h" // CMSIS OS Tick API +#include "cmsis_os2.h" // CMSIS RTOS API +#include "rtx_os.h" // RTX OS definitions +#include "rtx_evr.h" // RTX Event Recorder definitions + + +// ==== Library defines ==== + +#define os_thread_t osRtxThread_t +#define os_timer_t osRtxTimer_t +#define os_timer_finfo_t osRtxTimerFinfo_t +#define os_event_flags_t osRtxEventFlags_t +#define os_mutex_t osRtxMutex_t +#define os_semaphore_t osRtxSemaphore_t +#define os_mp_info_t osRtxMpInfo_t +#define os_memory_pool_t osRtxMemoryPool_t +#define os_message_t osRtxMessage_t +#define os_message_queue_t osRtxMessageQueue_t +#define os_object_t osRtxObject_t + +// ==== Inline functions ==== + +// Thread ID +__STATIC_INLINE os_thread_t *osRtxThreadId (osThreadId_t thread_id) { + //lint -e{9079} -e{9087} "cast from pointer to void to pointer to object type" [MISRA Note 2] + return ((os_thread_t *)thread_id); +} +// Timer ID +__STATIC_INLINE os_timer_t *osRtxTimerId (osTimerId_t timer_id) { + //lint -e{9079} -e{9087} "cast from pointer to void to pointer to object type" [MISRA Note 2] + return ((os_timer_t *)timer_id); +} +// Event Flags ID +__STATIC_INLINE os_event_flags_t *osRtxEventFlagsId (osEventFlagsId_t ef_id) { + //lint -e{9079} -e{9087} "cast from pointer to void to pointer to object type" [MISRA Note 2] + return ((os_event_flags_t *)ef_id); +} +// Mutex ID +__STATIC_INLINE os_mutex_t *osRtxMutexId (osMutexId_t mutex_id) { + //lint -e{9079} -e{9087} "cast from pointer to void to pointer to object type" [MISRA Note 2] + return ((os_mutex_t *)mutex_id); +} +// Semaphore ID +__STATIC_INLINE os_semaphore_t *osRtxSemaphoreId (osSemaphoreId_t semaphore_id) { + //lint -e{9079} -e{9087} "cast from pointer to void to pointer to object type" [MISRA Note 2] + return ((os_semaphore_t *)semaphore_id); +} +// Memory Pool ID +__STATIC_INLINE os_memory_pool_t *osRtxMemoryPoolId (osMemoryPoolId_t mp_id) { + //lint -e{9079} -e{9087} "cast from pointer to void to pointer to object type" [MISRA Note 2] + return ((os_memory_pool_t *)mp_id); +} +// Message Queue ID +__STATIC_INLINE os_message_queue_t *osRtxMessageQueueId (osMessageQueueId_t mq_id) { + //lint -e{9079} -e{9087} "cast from pointer to void to pointer to object type" [MISRA Note 2] + return ((os_message_queue_t *)mq_id); +} + +// Generic Object +__STATIC_INLINE os_object_t *osRtxObject (void *object) { + //lint -e{9079} -e{9087} "cast from pointer to void to pointer to object type" [MISRA Note 3] + return ((os_object_t *)object); +} + +// Thread Object +__STATIC_INLINE os_thread_t *osRtxThreadObject (os_object_t *object) { + //lint -e{740} -e{826} -e{9087} "cast from pointer to generic object to specific object" [MISRA Note 4] + return ((os_thread_t *)object); +} +// Timer Object +__STATIC_INLINE os_timer_t *osRtxTimerObject (os_object_t *object) { + //lint -e{740} -e{826} -e{9087} "cast from pointer to generic object to specific object" [MISRA Note 4] + return ((os_timer_t *)object); +} +// Event Flags Object +__STATIC_INLINE os_event_flags_t *osRtxEventFlagsObject (os_object_t *object) { + //lint -e{740} -e{826} -e{9087} "cast from pointer to generic object to specific object" [MISRA Note 4] + return ((os_event_flags_t *)object); +} +// Mutex Object +__STATIC_INLINE os_mutex_t *osRtxMutexObject (os_object_t *object) { + //lint -e{740} -e{826} -e{9087} "cast from pointer to generic object to specific object" [MISRA Note 4] + return ((os_mutex_t *)object); +} +// Semaphore Object +__STATIC_INLINE os_semaphore_t *osRtxSemaphoreObject (os_object_t *object) { + //lint -e{740} -e{826} -e{9087} "cast from pointer to generic object to specific object" [MISRA Note 4] + return ((os_semaphore_t *)object); +} +// Memory Pool Object +__STATIC_INLINE os_memory_pool_t *osRtxMemoryPoolObject (os_object_t *object) { + //lint -e{740} -e{826} -e{9087} "cast from pointer to generic object to specific object" [MISRA Note 4] + return ((os_memory_pool_t *)object); +} +// Message Queue Object +__STATIC_INLINE os_message_queue_t *osRtxMessageQueueObject (os_object_t *object) { + //lint -e{740} -e{826} -e{9087} "cast from pointer to generic object to specific object" [MISRA Note 4] + return ((os_message_queue_t *)object); +} +// Message Object +__STATIC_INLINE os_message_t *osRtxMessageObject (os_object_t *object) { + //lint -e{740} -e{826} -e{9087} "cast from pointer to generic object to specific object" [MISRA Note 4] + return ((os_message_t *)object); +} + +// Kernel State +__STATIC_INLINE osKernelState_t osRtxKernelState (void) { + //lint -e{9030} -e{9034} "cast to enum" + return ((osKernelState_t)(osRtxInfo.kernel.state)); +} + +// Thread State +__STATIC_INLINE osThreadState_t osRtxThreadState (const os_thread_t *thread) { + uint8_t state = thread->state & osRtxThreadStateMask; + //lint -e{9030} -e{9034} "cast to enum" + return ((osThreadState_t)state); +} + +// Thread Priority +__STATIC_INLINE osPriority_t osRtxThreadPriority (const os_thread_t *thread) { + //lint -e{9030} -e{9034} "cast to enum" + return ((osPriority_t)thread->priority); +} + +// Kernel Get State +__STATIC_INLINE uint8_t osRtxKernelGetState (void) { + return osRtxInfo.kernel.state; +} + +// Thread Get/Set Running +__STATIC_INLINE os_thread_t *osRtxThreadGetRunning (void) { + return osRtxInfo.thread.run.curr; +} +__STATIC_INLINE void osRtxThreadSetRunning (os_thread_t *thread) { + osRtxInfo.thread.run.curr = thread; +} + + +// ==== Library functions ==== + +// Kernel Library functions +extern void osRtxKernelPreInit (void); + +// Thread Library functions +extern void osRtxThreadListPut (os_object_t *object, os_thread_t *thread); +extern os_thread_t *osRtxThreadListGet (os_object_t *object); +extern void osRtxThreadListSort (os_thread_t *thread); +extern void osRtxThreadListRemove (os_thread_t *thread); +extern void osRtxThreadReadyPut (os_thread_t *thread); +extern void osRtxThreadDelayTick (void); +extern uint32_t *osRtxThreadRegPtr (const os_thread_t *thread); +extern void osRtxThreadSwitch (os_thread_t *thread); +extern void osRtxThreadDispatch (os_thread_t *thread); +extern void osRtxThreadWaitExit (os_thread_t *thread, uint32_t ret_val, bool_t dispatch); +extern bool_t osRtxThreadWaitEnter (uint8_t state, uint32_t timeout); +#ifdef RTX_STACK_CHECK +extern bool_t osRtxThreadStackCheck (const os_thread_t *thread); +#endif +extern bool_t osRtxThreadStartup (void); + +// Timer Library functions +extern int32_t osRtxTimerSetup (void); +extern void osRtxTimerThread (void *argument); + +// Mutex Library functions +extern void osRtxMutexOwnerRelease (os_mutex_t *mutex_list); +extern void osRtxMutexOwnerRestore (const os_mutex_t *mutex, const os_thread_t *thread_wakeup); + +// Memory Heap Library functions +extern uint32_t osRtxMemoryInit (void *mem, uint32_t size); +extern void *osRtxMemoryAlloc(void *mem, uint32_t size, uint32_t type); +extern uint32_t osRtxMemoryFree (void *mem, void *block); + +// Memory Pool Library functions +extern uint32_t osRtxMemoryPoolInit (os_mp_info_t *mp_info, uint32_t block_count, uint32_t block_size, void *block_mem); +extern void *osRtxMemoryPoolAlloc (os_mp_info_t *mp_info); +extern osStatus_t osRtxMemoryPoolFree (os_mp_info_t *mp_info, void *block); + +// Message Queue Library functions +extern int32_t osRtxMessageQueueTimerSetup (void); + +// System Library functions +extern void osRtxTick_Handler (void); +extern void osRtxPendSV_Handler (void); +extern void osRtxPostProcess (os_object_t *object); + + +#endif // RTX_LIB_H_ diff --git a/LA_OPT_NXP_Software_License.txt b/LA_OPT_NXP_Software_License.txt index d534008..1a01b45 100644 --- a/LA_OPT_NXP_Software_License.txt +++ b/LA_OPT_NXP_Software_License.txt @@ -1,2 +1,2 @@ -LA_OPT_NXP_Software_License v39 August 2022  IMPORTANT.  Read the following NXP Software License Agreement ("Agreement") completely. By selecting the "I Accept" button at the end of this page, or by downloading, installing, or using the Licensed Software, you indicate that you accept the terms of the Agreement, and you acknowledge that you have the authority, for yourself or on behalf of your company, to bind your company to these terms. You may then download or install the file. In the event of a conflict between the terms of this Agreement and any license terms and conditions for NXP's proprietary software embedded anywhere in the Licensed Software file, the terms of this Agreement shall control.  If a separate license agreement for the Licensed Software has been signed by you and NXP, then that agreement shall govern your use of the Licensed Software and shall supersede this Agreement. NXP SOFTWARE LICENSE AGREEMENT This is a legal agreement between your employer, of which you are an authorized representative, or, if you have no employer, you as an individual ("you" or "Licensee"), and NXP B.V. ("NXP").  It concerns your rights to use the software provided to you in binary or source code form and any accompanying written materials (the "Licensed Software"). The Licensed Software may include any updates or error corrections or documentation relating to the Licensed Software provided to you by NXP under this Agreement. In consideration for NXP allowing you to access the Licensed Software, you are agreeing to be bound by the terms of this Agreement. If you do not agree to all of the terms of this Agreement, do not download or install the Licensed Software. If you change your mind later, stop using the Licensed Software and delete all copies of the Licensed Software in your possession or control. Any copies of the Licensed Software that you have already distributed, where permitted, and do not destroy will continue to be governed by this Agreement. Your prior use will also continue to be governed by this Agreement. 1.       DEFINITIONS 1.1.         "Affiliate" means, with respect to a party, any corporation or other legal entity that now or hereafter Controls, is Controlled by or is under common Control with such party; where "Control" means the direct or indirect ownership of greater than fifty percent (50%) of the shares or similar interests entitled to vote for the election of directors or other persons performing similar functions. An entity is considered an Affiliate only so long as such Control exists. 1.2 "Authorized System" means either (i) Licensee's hardware product which incorporates an NXP Product or (ii) Licensee's software program which is used exclusively in connection with an NXP Product and with which the Licensed Software will be integrated.       1.3. "Derivative Work" means a work based upon one or more pre-existing works. A work consisting of editorial revisions, annotations, elaborations, or other modifications which, as a whole, represent an original work of authorship, is a Derivative Work.         1.4 "Intellectual Property Rights" means any and all rights under statute, common law or equity in and under copyrights, trade secrets, and patents (including utility models), and analogous rights throughout the world, including any applications for and the right to apply for, any of the foregoing. 1.5 "NXP Product" means a hardware product (e.g. a microprocessor, microcontroller, sensor or digital signal processor) and/or services (e.g. cloud platform services) supplied directly or indirectly from NXP or an NXP Affiliate, unless there is a product specified in the Software Content Register, in which case this definition is limited to such product. 1.6      "Software Content Register" means the documentation which may accompany the Licensed Software which identifies the contents of the Licensed Software, including but not limited to identification of any Third Party Software, if any, and may also contain other related information as whether the license in 2.3 is applicable.  1.7     "Third Party Software" means, any software included in the Licensed Software that is not NXP proprietary software, and is not open source software, and to which different license terms may apply.  2.       LICENSE GRANT.   2.1.         If you are not expressly granted the distribution license in Section 2.3 in the Software Content Register, then you are only granted the rights in Section 2.2 and not in 2.3. If you are expressly granted the distribution license in Section 2.3 in the Software Content Register, then you are granted the rights in both Section 2.2 and 2.3. 2.2. Standard License. Subject to the terms and conditions of this Agreement, NXP grants you a worldwide, personal, non-transferable, non-exclusive, non-sublicensable license, solely for the development of an Authorized System: (a) to use and reproduce the Licensed Software (and its Derivative Works prepared under the license in Section 2.2(b)) solely in combination with a NXP Product; and (b) for Licensed Software provided to you in source code form (human readable), to prepare Derivative Works of the Licensed Software solely for use in combination with a NXP Product. You may not distribute or sublicense the Licensed Software to others under the license granted in this Section 2.2.  You may demonstrate the Licensed Software to your direct customers as part of an Authorized System so long as such demonstration is directly controlled by you and without prior approval by NXP; however, to all other third parties only if NXP has provided its advance, written approval (e.g. email approval) of your demonstrating the Licensed Software to specified third parties or at specified event(s).  You may not leave the Licensed Software with a direct customer or any other third party at any time.  2.3.        Additional Distribution License. If expressly authorized in the Software Content Register, subject to the terms and conditions of this Agreement, NXP grants you a worldwide, personal, non-transferable, non-exclusive, non-sublicensable license solely in connection with your manufacturing and distribution of an Authorized System: (a) to manufacture (or have manufactured), distribute, and market the Licensed Software (and its Derivative Works prepared under the license in 2.2(b)) in object code (machine readable format) only as part of, or embedded within, Authorized Systems and not on a standalone basis solely for use in combination with a NXP Product. Notwithstanding the foregoing, those files marked as .h files ("Header files") may be distributed in source or object code form, but only as part of, or embedded within Authorized Systems; and (b) to copy and distribute as needed, solely in connection with an Authorized System and for use in combination with a NXP Product, non-confidential NXP information provided as part of the Licensed Software for the purpose of maintaining and supporting Authorized Systems with which the Licensed Software is integrated. 2.4 Separate license grants to Third Party Software, or other terms applicable to the Licensed Software if different from those granted in this Section 2, are contained in Appendix A. The Licensed Software may be accompanied by a Software Content Register which will identify that portion of the Licensed Software, if any, that is subject to the different terms in Appendix A.  2.5.         You may use subcontractors to exercise your rights under Section 2.2 and Section 2.3, if any, so long as you have an agreement in place with the subcontractor containing confidentiality restrictions no less stringent than those contained in this Agreement. You will remain liable for your subcontractors' adherence to the terms of this Agreement and for any and all acts and omissions of such subcontractors with respect to this Agreement and the Licensed Software. 3.       LICENSE LIMITATIONS AND RESTRICTIONS.   3.1.         The licenses granted above in Section 2 only extend to NXP Intellectual Property Rights that would be infringed by the unmodified Licensed Software prior to your preparation of any Derivative Work.    3.2.         The Licensed Software is licensed to you, not sold. Title to Licensed Software delivered hereunder remains vested in NXP or NXP's licensor and cannot be assigned or transferred. You are expressly forbidden from selling or otherwise distributing the Licensed Software, or any portion thereof, except as expressly permitted herein. This Agreement does not grant to you any implied rights under any NXP or third party Intellectual Property Rights. 3.3.         You may not translate, reverse engineer, decompile, or disassemble the Licensed Software except to the extent applicable law specifically prohibits such restriction. You must prohibit your subcontractors or customers (if distribution is permitted) from translating, reverse engineering, decompiling, or disassembling the Licensed Software except to the extent applicable law specifically prohibits such restriction. 3.4.         You must reproduce any and all of NXP's (or its third-party licensor's) copyright notices and other proprietary legends on copies of Licensed Software.   3.5.         If you distribute the Licensed Software to the United States Government, then the Licensed Software is "restricted computer software" and is subject to FAR 52.227-19.    3.6.         You grant to NXP a non-exclusive, non-transferable, irrevocable, perpetual, worldwide, royalty-free, sub-licensable license under your Intellectual Property Rights to use without restriction and for any purpose any suggestion, comment or other feedback related to the Licensed Software (including, but not limited to, error corrections and bug fixes). 3.7.         You will not take or fail to take any action that could subject the Licensed Software to an Excluded License. An Excluded License means any license that requires, as a condition of use, modification or distribution of software subject to the Excluded License, that such software or other software combined and/or distributed with the software be (i) disclosed or distributed in source code form; (ii) licensed for the purpose of making Derivative Works; or (iii) redistributable at no charge.  3.8.         You may not publish or distribute reports associated with the use of the Licensed Software to anyone other than NXP. You may advise NXP of any results obtained from your use of the Licensed Software, including any problems or suggested improvements thereof, and NXP retains the right to use such results and related information in any manner it deems appropriate. 4.       OPEN SOURCE.         Open source software included in the Licensed Software is not licensed under the terms of this Agreement but is instead licensed under the terms of the applicable open source license(s), such as the BSD License, Apache License or the GNU Lesser General Public License. Your use of the open source software is subject to the terms of each applicable license. You must agree to the terms of each applicable license, or you cannot use the open source software.   5.       INTELLECTUAL PROPERTY RIGHTS.    Upon request, you must provide NXP the source code of any derivative of the Licensed Software. Unless prohibited by law, the following paragraph shall apply. Your modifications to the Licensed Software, and all intellectual property rights associated with, and title thereto, will be the property of NXP. You agree to assign all, and hereby do assign all rights, title, and interest to any such modifications to the Licensed Software to NXP and agree to provide all assistance reasonably requested by NXP to establish, preserve or enforce such right. Further, you agree to waive all moral rights relating to your modifications to the Licensed Software, including, without limitation, all rights of identification of authorship and all rights of approval, restriction, or limitation on use or subsequent modification. Notwithstanding the foregoing, you will have the license rights granted in Section 2 hereto to any such modifications made by you or your licensees. Otherwise, you agree to grant an irrevocable, worldwide, and perpetual license to NXP to make, have made, use, sell, offer to sell, import, commercialize, sublicense and reproduce your modifications or derivative works to the Licensed Software without any payment to Licensee. You agree to provide all assistance reasonably requested by NXP to establish, preserve or enforce such right. 6.       ESSENTIAL PATENTS.    NXP has no obligation to identify or obtain any license to any Intellectual Property Right of a third-party that may be necessary for use in connection with technology that is incorporated into the Authorized System (whether or not as part of the Licensed Software). 7.       TERM AND TERMINATION.   This Agreement will remain in effect unless terminated as provided in this Section. 7.1.         You may terminate this Agreement immediately upon written notice to NXP at the address provided below. 7.2.         Either party may terminate this Agreement if the other party is in default of any of the terms and conditions of this Agreement, and termination is effective if the defaulting party fails to correct such default within 30 days after written notice thereof by the non-defaulting party to the defaulting party at the address below. 7.3.         Notwithstanding the foregoing, NXP may terminate this Agreement immediately upon written notice if you: breach any of your confidentiality obligations or the license restrictions under this Agreement;  become bankrupt, insolvent, or file a petition for bankruptcy or insolvency; make an assignment for the benefit of its creditors; enter proceedings for winding up or dissolution; are dissolved; or are nationalized or become subject to the expropriation of all or substantially all of your business or assets. 7.4.         Upon termination of this Agreement, all licenses granted under Section 2 will expire. 7.5.         After termination of this Agreement by either party you will destroy all parts of Licensed Software and its Derivative Works (if any) and will provide to NXP a statement certifying the same. 7.6.         Notwithstanding the termination of this Agreement for any reason, the terms of Sections 1 and 3 through 24 will survive.   8.        SUPPORT.  NXP is not obligated to provide any support, upgrades or new releases of the Licensed Software under this Agreement. If you wish, you may contact NXP and report problems and provide suggestions regarding the Licensed Software. NXP has no obligation to respond to such a problem report or suggestion. NXP may make changes to the Licensed Software at any time, without any obligation to notify or provide updated versions of the Licensed Software to you. 9.        NO WARRANTY.  To the maximum extent permitted by law, NXP expressly disclaims any warranty for the Licensed Software. The Licensed Software is provided "AS IS", without warranty of any kind, either express or implied, including without limitation the implied warranties of merchantability, fitness for a particular purpose, or non-infringement. You assume the entire risk arising out of the use or performance of the licensed software, or any systems you design using the licensed software (if any). 10.        INDEMNITY. You agree to fully defend and indemnify NXP from all claims, liabilities, and costs (including reasonable attorney's fees) related to (1) your use (including your subcontractor's or distributee's use, if permitted) of the Licensed Software or (2) your violation of the terms and conditions of this Agreement. 11.        LIMITATION OF LIABILITY.  EXCLUDING LIABILITY FOR A BREACH OF SECTION 2 (LICENSE GRANTS), SECTION 3 (LICENSE LIMITATIONS AND RESTRICTIONS), SECTION 16 (CONFIDENTIAL INFORMATION), OR CLAIMS UNDER SECTION 10 (INDEMNITY), IN NO EVENT WILL EITHER PARTY BE LIABLE, WHETHER IN CONTRACT, TORT, OR OTHERWISE, FOR ANY INCIDENTAL, SPECIAL, INDIRECT, CONSEQUENTIAL OR PUNITIVE DAMAGES, INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR ANY LOSS OF USE, LOSS OF TIME, INCONVENIENCE, COMMERCIAL LOSS, OR LOST PROFITS, SAVINGS, OR REVENUES, TO THE FULL EXTENT SUCH MAY BE DISCLAIMED BY LAW. NXP'S TOTAL LIABILITY FOR ALL COSTS, DAMAGES, CLAIMS, OR LOSSES WHATSOEVER ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT OR PRODUCT(S) SUPPLIED UNDER THIS AGREEMENT IS LIMITED TO THE AGGREGATE AMOUNT PAID BY YOU TO NXP IN CONNECTION WITH THE LICENSED SOFTWARE PROVIDED UNDER THIS AGREEMENT TO WHICH LOSSES OR DAMAGES ARE CLAIMED. 12.        EXPORT COMPLIANCE. Each party shall comply with all applicable export and import control laws and regulations including but not limited to the US Export Administration Regulation (including restrictions on certain military end uses and military end users as specified in Section 15 C.F.R. § 744.21 and prohibited party lists issued by other federal governments), Catch-all regulations and all national and international embargoes. Each party further agrees that it will not knowingly transfer, divert, export or re-export, directly or indirectly, any product, software, including software source code, or technology restricted by such regulations or by other applicable national regulations, received from the other party under this Agreement, or any direct product of such software or technical data to any person, firm, entity, country or destination to which such transfer, diversion, export or re-export is restricted or prohibited, without obtaining prior written authorization from the applicable competent government authorities to the extent required by those laws. 13.   GOVERNMENT CONTRACT COMPLIANCE 13.1.      If you sell Authorized Systems directly to any government or public entity, including U.S., state, local, foreign or international governments or public entities, or indirectly via a prime contractor or subcontractor of such governments or entities, NXP makes no representations, certifications, or warranties whatsoever about compliance with government or public entity acquisition statutes or regulations, including, without limitation, statutes or regulations that may relate to pricing, quality, origin or content. 13.2.      The Licensed Software has been developed at private expense and is a "Commercial Item" as defined in 48 C.F.R. Section 2.101, consisting of "Commercial Computer Software", and/or "Commercial Computer Software Documentation," as such terms are used in 48 C.F.R. Section 12.212 (or 48 C.F.R. Section 227.7202, as applicable) and may only be licensed to or shared with U.S. Government end users in object code form as part of, or embedded within, Authorized Systems. Any agreement pursuant to which you share the Licensed Software will include a provision that reiterates the limitations of this document and requires all sub-agreements to similarly contain such limitations.  14.        CRITICAL APPLICATIONS. In some cases, NXP may promote certain software for use in the development of, or for incorporation into, products or services (a) used in applications requiring fail-safe performance or (b) in which failure could lead to death, personal injury, or severe physical or environmental damage (these products and services are referred to as "Critical Applications"). NXP's goal is to educate customers so that they can design their own end-product solutions to meet applicable functional safety standards and requirements. Licensee makes the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, safety, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. As such, Licensee assumes all risk related to use of the Licensed Software in Critical Applications and NXP SHALL NOT BE LIABLE FOR ANY SUCH USE IN CRITICAL APPLICATIONS BY LICENSEE. Accordingly, Licensee will indemnify and hold NXP harmless from any claims, liabilities, damages and associated costs and expenses (including attorneys' fees) that NXP may incur related to Licensee’s incorporation of the Licensed Software in a Critical Application. 15.        CHOICE OF LAW; VENUE.  This Agreement will be governed by, construed, and enforced in accordance with the laws of The Netherlands, without regard to conflicts of laws principles, will apply to all matters relating to this Agreement or the Licensed Software, and you agree that any litigation will be subject to the exclusive jurisdiction of the courts of Amsterdam, The Netherlands. The United Nations Convention on Contracts for the International Sale of Goods will not apply to this document.  16.        CONFIDENTIAL INFORMATION.  Subject to the license grants and restrictions contained herein, you must treat the Licensed Software as confidential information and you agree to retain the Licensed Software in confidence perpetually. You may not disclose any part of the Licensed Software to anyone other than distributees in accordance with Section 2.3 and employees, or subcontractors in accordance with Section 2.5, who have a need to know of the Licensed Software and who have executed written agreements obligating them to protect such Licensed Software to at least the same degree of confidentiality as in this Agreement. You agree to use the same degree of care, but no less than a reasonable degree of care, with the Licensed Software as you do with your own confidential information. You may disclose Licensed Software to the extent required by a court or under operation of law or order provided that you notify NXP of such requirement prior to disclosure, which you only disclose the minimum of the required information, and that you allow NXP the opportunity to object to such court or other legal body requiring such disclosure. 17.       TRADEMARKS.  You are not authorized to use any NXP trademarks, brand names, or logos. 18.        ENTIRE AGREEMENT.  This Agreement constitutes the entire agreement between you and NXP regarding the subject matter of this Agreement, and supersedes all prior communications, negotiations, understandings, agreements or representations, either written or oral, if any. This Agreement may only be amended in written form, signed by you and NXP. 19.        SEVERABILITY.  If any provision of this Agreement is held for any reason to be invalid or unenforceable, then the remaining provisions of this Agreement will be unimpaired and, unless a modification or replacement of the invalid or unenforceable provision is further held to deprive you or NXP of a material benefit, in which case the Agreement will immediately terminate, the invalid or unenforceable provision will be replaced with a provision that is valid and enforceable and that comes closest to the intention underlying the invalid or unenforceable provision. 20.        NO WAIVER.  The waiver by NXP of any breach of any provision of this Agreement will not operate or be construed as a waiver of any other or a subsequent breach of the same or a different provision. 21.        AUDIT.  You will keep full, clear and accurate records with respect to your compliance with the limited license rights granted under this Agreement for three years following expiration or termination of this Agreement. NXP will have the right, either itself or through an independent certified public accountant to examine and audit, at NXP's expense, not more than once a year, and during normal business hours, all such records that may bear upon your compliance with the limited license rights granted above. You must make prompt adjustment to compensate for any errors and/or omissions disclosed by such examination or audit. 22.        NOTICES.             All notices and communications under this Agreement will be made in writing, and will be effective when received at the following addresses:            NXP:       NXP B.V.                        High Tech Campus 60                          5656 AG Eindhoven                         The Netherlands                     ATTN: Legal Department   You:              The address provided at registration will be used. 23.        RELATIONSHIP OF THE PARTIES.     The parties are independent contractors. Nothing in this Agreement will be construed to create any partnership, joint venture, or similar relationship. Neither party is authorized to bind the other to any obligations with third parties. 24.        SUCCESSION AND ASSIGNMENT.   This Agreement will be binding upon and inure to the benefit of the parties and their permitted successors and assigns.  You may not assign this Agreement, or any part of this Agreement, without the prior written approval of NXP, which approval will not be unreasonably withheld or delayed. NXP may assign this Agreement, or any part of this Agreement, in its sole discretion. 25. PRIVACY. By agreeing to this Agreement and/or utilizing the Licensed Software, Licensee consents to use of certain personal information, including but not limited to name, email address, and location, for the purpose of NXP’s internal analysis regarding future software offerings. NXP’s complete Privacy Statement can be found at: https://www.nxp.com/company/our-company/about-nxp/privacy-statement:PRIVACYPRACTICES.     - APPENDIX A Other License Grants and Restrictions: The Licensed Software may include some or all of the following software, which is either 1) Third Party Software or 2) NXP proprietary software subject to different terms than those in the Agreement. If the Software Content Register that accompanies the Licensed Software identifies any of the following Third Party Software or specific components of the NXP proprietary software, the following terms apply to the extent they deviate from the terms in the Agreement: Airbiquity Inc.: The Airbiquity software may only be used in object code and Licensee may not sublicense the Airbiquity software to any third party. Licensee’s license to use the Airbiquity software expires on June 30, 2023. Amazon: Use of the Amazon software constitutes your acceptance of the terms of the Amazon Program Materials License Agreement (including the AVS Component Schedule, if applicable), located at https://developer.amazon.com/support/legal/pml. All Amazon software is hereby designated "Amazon confidential". With the exception of the binary library of the Amazon Wake Word Engine for “Alexa”, all Amazon software is also hereby designated as “Restricted Program Materials”. Amazon is a third-party beneficiary to this Agreement with respect to the Amazon software. Amazon Web Services, Inc.: AWS is an intended third-party beneficiary to this Agreement with respect to the Greengrass software. If you have an account with AWS that is not in good standing, you may not download, install, use or distribute the Greengrass software. You will comply with all instructions and requirements in any integration documents, guidelines, or other documentation AWS provides. The license to the Greengrass software will immediately terminate without notice if you (a) fail to comply with this Agreement or any other agreement with AWS, (b) fail to make timely payment for any AWS service, (c) fail to implement AWS updates, or (d) bring any action for intellectual property infringement against AWS or any AWS customer utilizing AWS services. Any dispute or claim relating to your use of the Greengrass software will be resolved by binding arbitration, rather than in court, except that you may assert claims in small claims court if your claims qualify. Amazon: AWS Fleetwise software must be used consistent with the terms found here: https://github.com/aws/aws-iot-fleetwise-edge/blob/main/LICENSE. Amphion Semiconductor Ltd.: Distribution of Amphion software must be a part of, or embedded within, Authorized Systems that include an Amphion Video Decoder. Apple MFi Software Development Kit: Use of Apple MFi Software and associated documentation is restricted to current Apple MFi licensees in accordance with the terms of their own valid and in-effect license from Apple. Aquantia Corp.: You may use Aquantia's API binaries solely to flash the API software to an NXP Product which mates with an Aquantia device. Argus Cyber Security: The Argus software may only be used in object code and only for evaluation and demonstration purposes. Atheros: Use of Atheros software is limited to evaluation and demonstration only. Permitted distributions must be similarly limited. Further rights must be obtained directly from Atheros. ATI (AMD): Distribution of ATI software must be a part of, or embedded within, Authorized Systems that include a ATI graphics processor core. Au-Zone Technologies: eIQ Portal, Model Tool, DeepViewRT and ModelRunner are distributed by NXP under license from Au-Zone Technologies.  Your use of the Licensed Software, examples and related documentation is subject to the following: (1)          Use of Software is limited to Authorized System only (2)          In no event may Licensee Sublicense the Software (3)          AU-ZONE TECHNOLOGIES SHALL NOT BE LIABLE FOR USE OF LICENSED SOFTWARE IN CRITICAL APPLICATIONS BY LICENSEE Broadcom Corporation: Your use of Broadcom Corporation software is restricted to Authorized Systems that incorporate a compatible integrated circuit device manufactured or sold by Broadcom. Cadence Design Systems: Use of Cadence audio codec software is limited to distribution only of one copy per single NXP Product. The license granted herein to the Cadence Design Systems HiFi aacPlus Audio Decoder software does not include a license to the AAC family of technologies which you or your customer may need to obtain. Configuration tool outputs may only be distributed by licensees of the relevant Cadence SDK and distribution is limited to distribution of one copy embedded in a single NXP Product. Your use of Cadence NatureDSP Libraries whether in source code or in binary is restricted to NXP SoC based systems or emulation enablement based on NXP SoC. Cirque Corporation: Use of Cirque Corporation technology is limited to evaluation, demonstration, or certification testing only. Permitted distributions must be similarly limited. Further rights, including but not limited to ANY commercial distribution rights, must be obtained directly from Cirque Corporation. Coding Technologies (Dolby Labs): Use of CTS software is limited to evaluation and demonstration only. Permitted distributions must be similarly limited. Further rights must be obtained from Dolby Laboratories. CSR: Use of Cambridge Silicon Radio, Inc. ("CSR") software is limited to evaluation and demonstration only. Permitted distributions must be similarly limited. Further rights must be obtained directly from CSR. Crank: Use of Crank Software Inc. software is limited to evaluation and demonstration only. Permitted distributions must be similarly limited. Further rights must be obtained directly from Crank Software Inc. Cypress Semiconductor Corporation: WWD RTOS source code may only be used in accordance with the Cypress IOT Community License Agreement obtained directly from Cypress Semiconductor Corporation. Elektrobit Automotive GmbH (“EB”): EB software must be used consistent with the EB License Terms and Conditions, Version 1.4 (Dec 2019) found here: https://www.elektrobit.com/legal-notice/ .  Licensee is only granted an evaluation license for the EB software, defined as license to use the EB software internally for own evaluation purposes, limited to three (3) months. Production deployment of the EB software using this license is prohibited. See additionally Section 2.1.1 EB EULA. Embedded Systems Academy GmbH (EmSA): Any use of Micro CANopen Plus is subject to the acceptance of the license conditions described in the LICENSE.INFO file distributed with all example projects and in the documentation and the additional clause described below. Clause 1: Micro CANopen Plus may not be used for any competitive or comparative purpose, including the publication of any form of run time or compile time metric, without the express permission of EmSA. Fenopix Technologies Private Limited: Under no circumstances may the CanvasJS software product be used in any way that would compete with any product from Fenopix.  License to the CanvasJS software will terminate immediately without notice if Licensee fail to comply with any provision of this Agreement. Fraunhofer IIS: Fraunhofer MPEG Audio Decoder (Fraunhofer copyright) - If you are provided MPEG-H decoding functionality, you understand that NXP will provide Fraunhofer your name and contact information. Future Technology Devices International Ltd.: Future Technology Devices International software must be used consistent with the terms found here: http://www.ftdichip.com/Drivers/FTDriverLicenceTerms.htm Global Locate (Broadcom Corporation): Use of Global Locate, Inc. software is limited to evaluation and demonstration only. Permitted distributions must be similarly limited. Further rights must be obtained from Global Locate. LC3plus: the LC3plus Low Complexity Communication Codec Plus (LC3plus) per ETSI TS 103 634 V1.3.1, is subject to ETSI Intellectual Property Rights Policy, See https://portal.etsi.org/directives/45_directives_jun_2022.pdf. For application in an End Product, Fraunhofer communication applies, see https://www.iis.fraunhofer.de/en/ff/amm/communication/lc3.html Microsoft: Except for Microsoft PlayReady software, if the Licensed Software includes software owned by Microsoft Corporation ("Microsoft"), it is subject to the terms of your license with Microsoft (the "Microsoft Underlying Licensed Software") and as such, NXP grants no license to you, beyond evaluation and demonstration in connection with NXP processors, in the Microsoft Underlying Licensed Software. You must separately obtain rights beyond evaluation and demonstration in connection with the Microsoft Underlying Licensed Software from Microsoft. Microsoft does not provide support services for the components provided to you through this Agreement. If you have any questions or require technical assistance, please contact NXP. Microsoft Corporation is a third party beneficiary to this Agreement with the right to enforce the terms of this Agreement. TO THE MAXIMUM EXTENT PERMITTED BY LAW, MICROSOFT AND ITS AFFILIATES DISCLAIM ANY WARRANTIES FOR THE MICROSOFT UNDERLYING LICENSED SOFTWARE. TO THE MAXIMUM EXTENT PERMITTED BY LAW, NEITHER MICROSOFT NOR ITS AFFILIATES WILL BE LIABLE, WHETHER IN CONTRACT, TORT, OR OTHERWISE, FOR ANY DIRECT, INCIDENTAL, SPECIAL, INDIRECT, CONSEQUENTIAL OR PUNITIVE DAMAGES, INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR ANY LOSS OF USE, LOSS OF TIME, INCONVENIENCE, COMMERCIAL LOSS, OR LOST PROFITS, SAVINGS, OR REVENUES, ARISING FROM THE FROM THE USE OF THE MICROSOFT UNDERLYING LICENSED SOFTWARE. With respect to the Microsoft PlayReady software, you will have the license rights granted in Section 2, provided that you may not use the Microsoft PlayReady software unless you have entered into a Microsoft PlayReady Master Agreement and license directly with Microsoft. MindTree: Notwithstanding the terms contained in Section 2.3 (a), if the Licensed Software includes proprietary software of MindTree in source code format, Licensee may make modifications and create derivative works only to the extent necessary for debugging of the Licensed Software. MM SOLUTIONS AD: Use of MM SOLUTIONS AEC (Auto Exposure Control) and AWB (Auto White Balance) software is limited to demonstration, testing, and evaluation only. In no event may Licensee distribute or sublicense the MM SOLUTIONS software. Further rights must be obtained directly from MM SOLUTIONS. MPEG LA: Use of MPEG LA audio or video codec technology is limited to evaluation and demonstration only. Permitted distributions must be similarly limited. Further rights must be obtained directly from MPEG LA. MQX RTOS Code: MQX RTOS source code may not be re-distributed by any NXP Licensee under any circumstance, even by a signed written amendment to this Agreement. NXP Voice Software: VoiceSpot, VoiceSeeker (including AEC), and Conversa may be used for evaluation or demonstration purposes only. Any commercial distribution rights are subject to a separate royalty agreement obtained from NXP. NXP Wireless Charging Library: License to the Software is limited to use in inductive coupling or wireless charging applications Opus: Use of Opus software must be consistent with the terms of the Opus license which can be found at: http://www.opus-codec.org/license/ Oracle JRE (Java): The Oracle JRE must be used consistent with terms found here: http://java.com/license P&E Micro: P&E Software must be used consistent with the terms found here: http://www.pemicro.com/licenses/gdbserver/license_gdb.pdf Pro Design Electronic: Licensee may not modify, create derivative works based on, or copy the Pro Design software, documentation, hardware execution key or the accompanying materials. Licensee shall not use Pro Design's or any of its licensors names, logos or trademarks to market the Authorized System. Only NXP customers and distributors are permitted to further redistribute the Pro Design software and only as part of an Authorized System which contains the Pro Design software. Qualcomm Atheros, Inc.: Notwithstanding anything in this Agreement, Qualcomm Atheros, Inc. Wi-Fi software must be used strictly in accordance with the Qualcomm Atheros, Inc. Technology License Agreement that accompanies such software. Any other use is expressly prohibited. Real Networks - GStreamer Optimized Real Format Client Code implementation or OpenMax Optimized Real Format Client Code: Use of the GStreamer Optimized Real Format Client Code, or OpenMax Optimized Real Format Client code is restricted to applications in the automotive market. Licensee must be a final manufacturer in good standing with a current license with Real Networks for the commercial use and distribution of products containing the GStreamer Optimized Real Format Client Code implementation or OpenMax Optimized Real Format Client Code RivieraWaves SAS (a member of the CEVA, Inc. family of companies): You may not use the RivieraWaves intellectual property licensed under this Agreement if you develop, market, and/or license products similar to such RivieraWaves intellectual property. Such use constitutes a breach of this Agreement. Any such use rights must be obtained directly from RivieraWaves. SanDisk Corporation: If the Licensed Software includes software developed by SanDisk Corporation ("SanDisk"), you must separately obtain the rights to reproduce and distribute this software in source code form from SanDisk. Please follow these easy steps to obtain the license and software: (1) Contact your local SanDisk sales representative to obtain the SanDisk License Agreement. (2) Sign the license agreement. Fax the signed agreement to SanDisk USA marketing department at 408-542-0403. The license will be valid when fully executed by SanDisk. (3) If you have specific questions, please send an email to sales@sandisk.com You may only use the SanDisk Corporation Licensed Software on products compatible with a SanDisk Secure Digital Card. You may not use the SanDisk Corporation Licensed Software on any memory device product. SanDisk retains all rights to any modifications or derivative works to the SanDisk Corporation Licensed Software that you may create. SEGGER Microcontroller - emWin Software: Your use of SEGGER emWin software and components is restricted for development of NXP ARM7, ARM9, Cortex-M0, Cortex-M3, Cortex-M4, Cortex-M33, Cortex-M7, and Cortex-A7 based products only. SEGGER Microcontroller - J-Link/J-Trace Software: Segger software must be used consistent with the terms found here: http://www.segger.com/jlink-software.html Synopsys/BLE Software: Your use of the Synopsys/BLE Software and related documentation is subject to the following: (1) Synopsys is third-party beneficiaries of, and thus may enforce against you, the license restrictions and confidentiality obligations in this agreement with respect to their intellectual property and proprietary information. (2) Your distribution of the Licensed Software shall subject any recipient to a written agreement at least as protective of the Licensed Software as provided in this Agreement. Synopsys/Target Compiler Technologies: Your use of the Synopsys/Target Compiler Technologies Licensed Software and related documentation is subject to the following: (1) Duration of the license for the Licensed Software is limited to 12 months, unless otherwise specified in the license file. (2) The Licensed Software is usable by one user at a time on a single designated computer, unless otherwise agreed by Synopsys. (3) Licensed Software and documentation are to be used only on a designated computer at the designated physical address provided by you on the APEX license form. (4) The Licensed Software is not sub-licensable. T2 Labs / T2 Software: As a condition to the grant of any license under this Agreement, you represent and warrant that you will comply with all licenses, agreements, rules and bylaws of the Bluetooth SIG (Special Interest Group ) applicable to the licensed software and documentation and its use which may affect when and if you may take certain actions under licenses granted hereunder. The license grant under this Agreement is conditional to you being (i) a Bluetooth SIG Associate member until such time as the specifications for the software are made public to Bluetooth SIG members of any level and (ii) thereafter a Bluetooth SIG member of any level. Notwithstanding the terms contained in Section 2.3 (a), if the licensed software includes proprietary software in source code format, you may make modifications and create derivative works only to the extent necessary for improving the performance of the source code with the NXP products or your products and for creating enhancements of such products. You may not further sublicense or otherwise distribute the source code, or any modifications or derivatives thereof as stand-alone products. You will be responsible for qualifying any modifications or derivatives with the Bluetooth SIG and any other qualifying bodies. TARA Systems: Use of TARA Systems GUI technology Embedded Wizard is limited to evaluation and demonstration only. Permitted distributions must be similarly limited. Further rights must be obtained directly from TARA Systems. Texas Instruments: Your use of Texas Instruments Inc. WiLink8 Licensed Software is restricted to NXP SoC based systems that include a compatible connectivity device manufactured by TI. TES Electronic Solutions Germany (TES): TES 3D Surround View software and associated data and documentation may only be used for evaluation purposes and for demonstration to third parties in integrated form on a board package containing an NXP S32V234 device. Licensee may not distribute or sublicense the TES software. Your license to the TES software may be terminated at any time upon notice. Vivante: Distribution of Vivante software must be a part of, or embedded within, Authorized Systems that include a Vivante Graphics Processing Unit. \ No newline at end of file +LA_OPT_NXP_Software_License v45 May 2023  IMPORTANT.  Read the following NXP Software License Agreement (“Agreement”) completely. By selecting the “I Accept” button at the end of this page, or by downloading, installing, or using the Licensed Software, you indicate that you accept the terms of the Agreement, and you acknowledge that you have the authority, for yourself or on behalf of your company, to bind your company to these terms. You may then download or install the file. In the event of a conflict between the terms of this Agreement and any license terms and conditions for NXP’s proprietary software embedded anywhere in the Licensed Software file, the terms of this Agreement shall control.  If a separate license agreement for the Licensed Software has been signed by you and NXP, then that agreement shall govern your use of the Licensed Software and shall supersede this Agreement. NXP SOFTWARE LICENSE AGREEMENT This is a legal agreement between your employer, of which you are an authorized representative, or, if you have no employer, you as an individual (“you” or “Licensee”), and NXP B.V. (“NXP”).  It concerns your rights to use the software provided to you in binary or source code form and any accompanying written materials (the “Licensed Software”). The Licensed Software may include any updates or error corrections or documentation relating to the Licensed Software provided to you by NXP under this Agreement. In consideration for NXP allowing you to access the Licensed Software, you are agreeing to be bound by the terms of this Agreement. If you do not agree to all of the terms of this Agreement, do not download or install the Licensed Software. If you change your mind later, stop using the Licensed Software and delete all copies of the Licensed Software in your possession or control. Any copies of the Licensed Software that you have already distributed, where permitted, and do not destroy will continue to be governed by this Agreement. Your prior use will also continue to be governed by this Agreement. 1.       DEFINITIONS 1.1.         “Affiliate” means, with respect to a party, any corporation or other legal entity that now or hereafter Controls, is Controlled by or is under common Control with such party; where “Control” means the direct or indirect ownership of greater than fifty percent (50%) of the shares or similar interests entitled to vote for the election of directors or other persons performing similar functions. An entity is considered an Affiliate only so long as such Control exists. 1.2 “Authorized System” means either (i) Licensee’s hardware product which incorporates an NXP Product or (ii) Licensee’s software program which is used exclusively in connection with an NXP Product and with which the Licensed Software will be integrated.       1.3. “Derivative Work” means a work based upon one or more pre-existing works. A work consisting of editorial revisions, annotations, elaborations, or other modifications which, as a whole, represent an original work of authorship, is a Derivative Work.         1.4 “Intellectual Property Rights” means any and all rights under statute, common law or equity in and under copyrights, trade secrets, and patents (including utility models), and analogous rights throughout the world, including any applications for and the right to apply for, any of the foregoing. 1.5 “NXP Product” means a hardware product (e.g. a microprocessor, microcontroller, sensor or digital signal processor) and/or services (e.g. cloud platform services) supplied directly or indirectly from NXP or an NXP Affiliate, unless there is a product specified in the Software Content Register, in which case this definition is limited to such product. 1.6      “Software Content Register” means the documentation which may accompany the Licensed Software which identifies the contents of the Licensed Software, including but not limited to identification of any Third Party Software, if any, and may also contain other related information as whether the license in 2.3 is applicable.  1.7     “Third Party Software” means, any software included in the Licensed Software that is not NXP proprietary software, and is not open source software, and to which different license terms may apply.  2.       LICENSE GRANT.   2.1.         If you are not expressly granted the distribution license in Section 2.3 in the Software Content Register, then you are only granted the rights in Section 2.2 and not in 2.3. If you are expressly granted the distribution license in Section 2.3 in the Software Content Register, then you are granted the rights in both Section 2.2 and 2.3. 2.2. Standard License. Subject to the terms and conditions of this Agreement, NXP grants you a worldwide, personal, non-transferable, non-exclusive, non-sublicensable license, solely for the development of an Authorized System: (a) to use and reproduce the Licensed Software (and its Derivative Works prepared under the license in Section 2.2(b)) solely in combination with a NXP Product; and (b) for Licensed Software provided to you in source code form (human readable), to prepare Derivative Works of the Licensed Software solely for use in combination with a NXP Product. You may not distribute or sublicense the Licensed Software to others under the license granted in this Section 2.2.  You may demonstrate the Licensed Software to your direct customers as part of an Authorized System so long as such demonstration is directly controlled by you and without prior approval by NXP; however, to all other third parties only if NXP has provided its advance, written approval (e.g. email approval) of your demonstrating the Licensed Software to specified third parties or at specified event(s).  You may not leave the Licensed Software with a direct customer or any other third party at any time.  2.3.        Additional Distribution License. If expressly authorized in the Software Content Register, subject to the terms and conditions of this Agreement, NXP grants you a worldwide, personal, non-transferable, non-exclusive, non-sublicensable license solely in connection with your manufacturing and distribution of an Authorized System: (a) to manufacture (or have manufactured), distribute, and market the Licensed Software (and its Derivative Works prepared under the license in 2.2(b)) in object code (machine readable format) only as part of, or embedded within, Authorized Systems and not on a standalone basis solely for use in combination with a NXP Product. Notwithstanding the foregoing, those files marked as .h files (“Header files”) may be distributed in source or object code form, but only as part of, or embedded within Authorized Systems; and (b) to copy and distribute as needed, solely in connection with an Authorized System and for use in combination with a NXP Product, non-confidential NXP information provided as part of the Licensed Software for the purpose of maintaining and supporting Authorized Systems with which the Licensed Software is integrated. 2.4 Separate license grants to Third Party Software, or other terms applicable to the Licensed Software if different from those granted in this Section 2, are contained in Appendix A. The Licensed Software may be accompanied by a Software Content Register which will identify that portion of the Licensed Software, if any, that is subject to the different terms in Appendix A.  2.5.         You may use subcontractors to exercise your rights under Section 2.2 and Section 2.3, if any, so long as you have an agreement in place with the subcontractor containing confidentiality restrictions no less stringent than those contained in this Agreement. You will remain liable for your subcontractors’ adherence to the terms of this Agreement and for any and all acts and omissions of such subcontractors with respect to this Agreement and the Licensed Software. 3.       LICENSE LIMITATIONS AND RESTRICTIONS.   3.1.         The licenses granted above in Section 2 only extend to NXP Intellectual Property Rights that would be infringed by the unmodified Licensed Software prior to your preparation of any Derivative Work.    3.2.         The Licensed Software is licensed to you, not sold. Title to Licensed Software delivered hereunder remains vested in NXP or NXP’s licensor and cannot be assigned or transferred. You are expressly forbidden from selling or otherwise distributing the Licensed Software, or any portion thereof, except as expressly permitted herein. This Agreement does not grant to you any implied rights under any NXP or third party Intellectual Property Rights. 3.3.         You may not translate, reverse engineer, decompile, or disassemble the Licensed Software except to the extent applicable law specifically prohibits such restriction. You must prohibit your subcontractors or customers (if distribution is permitted) from translating, reverse engineering, decompiling, or disassembling the Licensed Software except to the extent applicable law specifically prohibits such restriction. 3.4.         You must reproduce any and all of NXP’s (or its third-party licensor’s) copyright notices and other proprietary legends on copies of Licensed Software.   3.5.         If you distribute the Licensed Software to the United States Government, then the Licensed Software is “restricted computer software” and is subject to FAR 52.227-19.    3.6.         You grant to NXP a non-exclusive, non-transferable, irrevocable, perpetual, worldwide, royalty-free, sub-licensable license under your Intellectual Property Rights to use without restriction and for any purpose any suggestion, comment or other feedback related to the Licensed Software (including, but not limited to, error corrections and bug fixes). 3.7.         You will not take or fail to take any action that could subject the Licensed Software to an Excluded License. An Excluded License means any license that requires, as a condition of use, modification or distribution of software subject to the Excluded License, that such software or other software combined and/or distributed with the software be (i) disclosed or distributed in source code form; (ii) licensed for the purpose of making Derivative Works; or (iii) redistributable at no charge.  3.8.         You may not publish or distribute reports associated with the use of the Licensed Software to anyone other than NXP. You may advise NXP of any results obtained from your use of the Licensed Software, including any problems or suggested improvements thereof, and NXP retains the right to use such results and related information in any manner it deems appropriate. 4.       OPEN SOURCE.         Open source software included in the Licensed Software is not licensed under the terms of this Agreement but is instead licensed under the terms of the applicable open source license(s), such as the BSD License, Apache License or the GNU Lesser General Public License. Your use of the open source software is subject to the terms of each applicable license. You must agree to the terms of each applicable license, or you cannot use the open source software.   5.       INTELLECTUAL PROPERTY RIGHTS.    Upon request, you must provide NXP the source code of any derivative of the Licensed Software. Unless prohibited by law, the following paragraph shall apply. Your modifications to the Licensed Software, and all intellectual property rights associated with, and title thereto, will be the property of NXP. You agree to assign all, and hereby do assign all rights, title, and interest to any such modifications to the Licensed Software to NXP and agree to provide all assistance reasonably requested by NXP to establish, preserve or enforce such right. Further, you agree to waive all moral rights relating to your modifications to the Licensed Software, including, without limitation, all rights of identification of authorship and all rights of approval, restriction, or limitation on use or subsequent modification. Notwithstanding the foregoing, you will have the license rights granted in Section 2 hereto to any such modifications made by you or your licensees. Otherwise, you agree to grant an irrevocable, worldwide, and perpetual license to NXP to make, have made, use, sell, offer to sell, import, commercialize, sublicense and reproduce your modifications or derivative works to the Licensed Software without any payment to Licensee. You agree to provide all assistance reasonably requested by NXP to establish, preserve or enforce such right. 6.       ESSENTIAL PATENTS.    NXP has no obligation to identify or obtain any license to any Intellectual Property Right of a third-party that may be necessary for use in connection with technology that is incorporated into the Authorized System (whether or not as part of the Licensed Software). 7.       TERM AND TERMINATION.   This Agreement will remain in effect unless terminated as provided in this Section. 7.1.         You may terminate this Agreement immediately upon written notice to NXP at the address provided below. 7.2.         Either party may terminate this Agreement if the other party is in default of any of the terms and conditions of this Agreement, and termination is effective if the defaulting party fails to correct such default within 30 days after written notice thereof by the non-defaulting party to the defaulting party at the address below. 7.3.         Notwithstanding the foregoing, NXP may terminate this Agreement immediately upon written notice if you: breach any of your confidentiality obligations or the license restrictions under this Agreement;  become bankrupt, insolvent, or file a petition for bankruptcy or insolvency; make an assignment for the benefit of its creditors; enter proceedings for winding up or dissolution; are dissolved; or are nationalized or become subject to the expropriation of all or substantially all of your business or assets. 7.4.         Upon termination of this Agreement, all licenses granted under Section 2 will expire. 7.5.         After termination of this Agreement by either party you will destroy all parts of Licensed Software and its Derivative Works (if any) and will provide to NXP a statement certifying the same. 7.6.         Notwithstanding the termination of this Agreement for any reason, the terms of Sections 1 and 3 through 24 will survive.   8.        SUPPORT.  NXP is not obligated to provide any support, upgrades or new releases of the Licensed Software under this Agreement. If you wish, you may contact NXP and report problems and provide suggestions regarding the Licensed Software. NXP has no obligation to respond to such a problem report or suggestion. NXP may make changes to the Licensed Software at any time, without any obligation to notify or provide updated versions of the Licensed Software to you. 9.        NO WARRANTY.  To the maximum extent permitted by law, NXP expressly disclaims any warranty for the Licensed Software. The Licensed Software is provided “AS IS”, without warranty of any kind, either express or implied, including without limitation the implied warranties of merchantability, fitness for a particular purpose, or non-infringement. You assume the entire risk arising out of the use or performance of the licensed software, or any systems you design using the licensed software (if any). 10.        INDEMNITY. You agree to fully defend and indemnify NXP from all claims, liabilities, and costs (including reasonable attorney’s fees) related to (1) your use (including your subcontractor’s or distributee’s use, if permitted) of the Licensed Software or (2) your violation of the terms and conditions of this Agreement. 11.        LIMITATION OF LIABILITY.  EXCLUDING LIABILITY FOR A BREACH OF SECTION 2 (LICENSE GRANTS), SECTION 3 (LICENSE LIMITATIONS AND RESTRICTIONS), SECTION 16 (CONFIDENTIAL INFORMATION), OR CLAIMS UNDER SECTION 10 (INDEMNITY), IN NO EVENT WILL EITHER PARTY BE LIABLE, WHETHER IN CONTRACT, TORT, OR OTHERWISE, FOR ANY INCIDENTAL, SPECIAL, INDIRECT, CONSEQUENTIAL OR PUNITIVE DAMAGES, INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR ANY LOSS OF USE, LOSS OF TIME, INCONVENIENCE, COMMERCIAL LOSS, OR LOST PROFITS, SAVINGS, OR REVENUES, TO THE FULL EXTENT SUCH MAY BE DISCLAIMED BY LAW. NXP’S TOTAL LIABILITY FOR ALL COSTS, DAMAGES, CLAIMS, OR LOSSES WHATSOEVER ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT OR PRODUCT(S) SUPPLIED UNDER THIS AGREEMENT IS LIMITED TO THE AGGREGATE AMOUNT PAID BY YOU TO NXP IN CONNECTION WITH THE LICENSED SOFTWARE PROVIDED UNDER THIS AGREEMENT TO WHICH LOSSES OR DAMAGES ARE CLAIMED. 12.        EXPORT COMPLIANCE. Each party shall comply with all applicable export and import control laws and regulations including but not limited to the US Export Administration Regulation (including restrictions on certain military end uses and military end users as specified in Section 15 C.F.R. § 744.21 and prohibited party lists issued by other federal governments), Catch-all regulations and all national and international embargoes. Each party further agrees that it will not knowingly transfer, divert, export or re-export, directly or indirectly, any product, software, including software source code, or technology restricted by such regulations or by other applicable national regulations, received from the other party under this Agreement, or any direct product of such software or technical data to any person, firm, entity, country or destination to which such transfer, diversion, export or re-export is restricted or prohibited, without obtaining prior written authorization from the applicable competent government authorities to the extent required by those laws. 13.   GOVERNMENT CONTRACT COMPLIANCE 13.1.      If you sell Authorized Systems directly to any government or public entity, including U.S., state, local, foreign or international governments or public entities, or indirectly via a prime contractor or subcontractor of such governments or entities, NXP makes no representations, certifications, or warranties whatsoever about compliance with government or public entity acquisition statutes or regulations, including, without limitation, statutes or regulations that may relate to pricing, quality, origin or content. 13.2.      The Licensed Software has been developed at private expense and is a “Commercial Item” as defined in 48 C.F.R. Section 2.101, consisting of “Commercial Computer Software”, and/or “Commercial Computer Software Documentation,” as such terms are used in 48 C.F.R. Section 12.212 (or 48 C.F.R. Section 227.7202, as applicable) and may only be licensed to or shared with U.S. Government end users in object code form as part of, or embedded within, Authorized Systems. Any agreement pursuant to which you share the Licensed Software will include a provision that reiterates the limitations of this document and requires all sub-agreements to similarly contain such limitations.  14.        CRITICAL APPLICATIONS. In some cases, NXP may promote certain software for use in the development of, or for incorporation into, products or services (a) used in applications requiring fail-safe performance or (b) in which failure could lead to death, personal injury, or severe physical or environmental damage (these products and services are referred to as “Critical Applications”). NXP’s goal is to educate customers so that they can design their own end-product solutions to meet applicable functional safety standards and requirements. Licensee makes the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, safety, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. As such, Licensee assumes all risk related to use of the Licensed Software in Critical Applications and NXP SHALL NOT BE LIABLE FOR ANY SUCH USE IN CRITICAL APPLICATIONS BY LICENSEE. Accordingly, Licensee will indemnify and hold NXP harmless from any claims, liabilities, damages and associated costs and expenses (including attorneys’ fees) that NXP may incur related to Licensee’s incorporation of the Licensed Software in a Critical Application. 15.        CHOICE OF LAW; VENUE.  This Agreement will be governed by, construed, and enforced in accordance with the laws of The Netherlands, without regard to conflicts of laws principles, will apply to all matters relating to this Agreement or the Licensed Software, and you agree that any litigation will be subject to the exclusive jurisdiction of the courts of Amsterdam, The Netherlands. The United Nations Convention on Contracts for the International Sale of Goods will not apply to this document.  16.        CONFIDENTIAL INFORMATION.  Subject to the license grants and restrictions contained herein, you must treat the Licensed Software as confidential information and you agree to retain the Licensed Software in confidence perpetually. You may not disclose any part of the Licensed Software to anyone other than distributees in accordance with Section 2.3 and employees, or subcontractors in accordance with Section 2.5, who have a need to know of the Licensed Software and who have executed written agreements obligating them to protect such Licensed Software to at least the same degree of confidentiality as in this Agreement. You agree to use the same degree of care, but no less than a reasonable degree of care, with the Licensed Software as you do with your own confidential information. You may disclose Licensed Software to the extent required by a court or under operation of law or order provided that you notify NXP of such requirement prior to disclosure, which you only disclose the minimum of the required information, and that you allow NXP the opportunity to object to such court or other legal body requiring such disclosure. 17.       TRADEMARKS.  You are not authorized to use any NXP trademarks, brand names, or logos. 18.        ENTIRE AGREEMENT.  This Agreement constitutes the entire agreement between you and NXP regarding the subject matter of this Agreement, and supersedes all prior communications, negotiations, understandings, agreements or representations, either written or oral, if any. This Agreement may only be amended in written form, signed by you and NXP. 19.        SEVERABILITY.  If any provision of this Agreement is held for any reason to be invalid or unenforceable, then the remaining provisions of this Agreement will be unimpaired and, unless a modification or replacement of the invalid or unenforceable provision is further held to deprive you or NXP of a material benefit, in which case the Agreement will immediately terminate, the invalid or unenforceable provision will be replaced with a provision that is valid and enforceable and that comes closest to the intention underlying the invalid or unenforceable provision. 20.        NO WAIVER.  The waiver by NXP of any breach of any provision of this Agreement will not operate or be construed as a waiver of any other or a subsequent breach of the same or a different provision. 21.        AUDIT.  You will keep full, clear and accurate records with respect to your compliance with the limited license rights granted under this Agreement for three years following expiration or termination of this Agreement. NXP will have the right, either itself or through an independent certified public accountant to examine and audit, at NXP’s expense, not more than once a year, and during normal business hours, all such records that may bear upon your compliance with the limited license rights granted above. You must make prompt adjustment to compensate for any errors and/or omissions disclosed by such examination or audit. 22.        NOTICES.             All notices and communications under this Agreement will be made in writing, and will be effective when received at the following addresses:  NXP: NXP B.V. High Tech Campus 60 5656 AG Eindhoven The Netherlands ATTN: Legal Department   You: The address provided at registration will be used. 23.        RELATIONSHIP OF THE PARTIES.     The parties are independent contractors. Nothing in this Agreement will be construed to create any partnership, joint venture, or similar relationship. Neither party is authorized to bind the other to any obligations with third parties. 24.        SUCCESSION AND ASSIGNMENT.   This Agreement will be binding upon and inure to the benefit of the parties and their permitted successors and assigns.  You may not assign this Agreement, or any part of this Agreement, without the prior written approval of NXP, which approval will not be unreasonably withheld or delayed. NXP may assign this Agreement, or any part of this Agreement, in its sole discretion. 25. PRIVACY. By agreeing to this Agreement and/or utilizing the Licensed Software, Licensee consents to use of certain personal information, including but not limited to name, email address, and location, for the purpose of NXP’s internal analysis regarding future software offerings. NXP’s complete Privacy Statement can be found at: https://www.nxp.com/company/our-company/about-nxp/privacy-statement:PRIVACYPRACTICES.     + APPENDIX A Other License Grants and Restrictions: The Licensed Software may include some or all of the following software, which is either 1) Third Party Software or 2) NXP proprietary software subject to different terms than those in the Agreement. If the Software Content Register that accompanies the Licensed Software identifies any of the following Third Party Software or specific components of the NXP proprietary software, the following terms apply to the extent they deviate from the terms in the Agreement: Airbiquity Inc.: The Airbiquity software may only be used in object code and Licensee may not sublicense the Airbiquity software to any third party. Licensee’s license to use the Airbiquity software expires on June 30, 2023. Amazon: Use of the Amazon software constitutes your acceptance of the terms of the Amazon Program Materials License Agreement (including the AVS Component Schedule, if applicable), located at https://developer.amazon.com/support/legal/pml. All Amazon software is hereby designated “Amazon confidential”. With the exception of the binary library of the Amazon Wake Word Engine for “Alexa”, all Amazon software is also hereby designated as “Restricted Program Materials”. Amazon is a third-party beneficiary to this Agreement with respect to the Amazon software. Amazon Web Services, Inc.: AWS is an intended third-party beneficiary to this Agreement with respect to the Greengrass software. If you have an account with AWS that is not in good standing, you may not download, install, use or distribute the Greengrass software. You will comply with all instructions and requirements in any integration documents, guidelines, or other documentation AWS provides. The license to the Greengrass software will immediately terminate without notice if you (a) fail to comply with this Agreement or any other agreement with AWS, (b) fail to make timely payment for any AWS service, (c) fail to implement AWS updates, or (d) bring any action for intellectual property infringement against AWS or any AWS customer utilizing AWS services. Any dispute or claim relating to your use of the Greengrass software will be resolved by binding arbitration, rather than in court, except that you may assert claims in small claims court if your claims qualify. Amazon: AWS Fleetwise software must be used consistent with the terms found here: https://github.com/aws/aws-iot-fleetwise-edge/blob/main/LICENSE. Amphion Semiconductor Ltd.: Distribution of Amphion software must be a part of, or embedded within, Authorized Systems that include an Amphion Video Decoder. Apple Mfi Software Development Kit: Use of Apple Mfi Software and associated documentation is restricted to current Apple Mfi licensees in accordance with the terms of their own valid and in-effect license from Apple. Aquantia Corp.: You may use Aquantia’s API binaries solely to flash the API software to an NXP Product which mates with an Aquantia device. Argus Cyber Security: The Argus software may only be used in object code and only for evaluation and demonstration purposes. Atheros: Use of Atheros software is limited to evaluation and demonstration only. Permitted distributions must be similarly limited. Further rights must be obtained directly from Atheros. ATI (AMD): Distribution of ATI software must be a part of, or embedded within, Authorized Systems that include a ATI graphics processor core. Au-Zone Technologies: eIQ Portal, Model Tool, DeepViewRT and ModelRunner are distributed by NXP under license from Au-Zone Technologies.  Your use of the Licensed Software, examples and related documentation is subject to the following: (1)          Use of Software is limited to Authorized System only (2)          In no event may Licensee Sublicense the Software (3)          AU-ZONE TECHNOLOGIES SHALL NOT BE LIABLE FOR USE OF LICENSED SOFTWARE IN CRITICAL APPLICATIONS BY LICENSEE Broadcom Corporation: Your use of Broadcom Corporation software is restricted to Authorized Systems that incorporate a compatible integrated circuit device manufactured or sold by Broadcom. Cadence Design Systems: Use of Cadence audio codec software is limited to distribution only of one copy per single NXP Product. The license granted herein to the Cadence Design Systems HiFi aacPlus Audio Decoder software does not include a license to the AAC family of technologies which you or your customer may need to obtain. Configuration tool outputs may only be distributed by licensees of the relevant Cadence SDK and distribution is limited to distribution of one copy embedded in a single NXP Product. Your use of Cadence NatureDSP Libraries whether in source code or in binary is restricted to NXP SoC based systems or emulation enablement based on NXP SoC. CEVA D.S.P. Ltd. And CEVA Technologies Inc. (“CEVA”): The CEVA-SPF2 linear algebra, CEVA-SPF2 Neural Network Libraries, CEVA-SPF2 Core Libraries, CEVA-SPF2 OpenAMP and CEVA-SPF2 STL licensed modules are owned by CEVA and such materials may only be used in connection with an NXP product containing the S250 or S125 integrated circuits, whether or not the CEVA-SPF2 Core is physically implemented and/or enabled on such NXP product Cirque Corporation: Use of Cirque Corporation technology is limited to evaluation, demonstration, or certification testing only. Permitted distributions must be similarly limited. Further rights, including but not limited to ANY commercial distribution rights, must be obtained directly from Cirque Corporation. Coding Technologies (Dolby Labs): Use of CTS software is limited to evaluation and demonstration only. Permitted distributions must be similarly limited. Further rights must be obtained from Dolby Laboratories. Coremark: Use of the Coremark benchmarking software is subject to the following terms and conditions: https://github.com/eembc/coremark/blob/main/LICENSE.md CSR: Use of Cambridge Silicon Radio, Inc. ("CSR") software is limited to evaluation and demonstration only. Permitted distributions must be similarly limited. Further rights must be obtained directly from CSR. Crank: Use of Crank Software Inc. software is limited to evaluation and demonstration only. Permitted distributions must be similarly limited. Further rights must be obtained directly from Crank Software Inc. Cypress Semiconductor Corporation: WWD RTOS source code may only be used in accordance with the Cypress IOT Community License Agreement obtained directly from Cypress Semiconductor Corporation. Elektrobit Automotive GmbH (“EB”): EB software must be used consistent with the EB License Terms and Conditions, Version 1.4 (Dec 2019) found here: https://www.elektrobit.com/legal-notice/ .  Licensee is only granted an evaluation license for the EB software, defined as license to use the EB software internally for own evaluation purposes, limited to three (3) months. Production deployment of the EB software using this license is prohibited. See additionally Section 2.1.1 EB EULA. Embedded Systems Academy GmbH (EmSA): Any use of Micro CANopen Plus is subject to the acceptance of the license conditions described in the LICENSE.INFO file distributed with all example projects and in the documentation and the additional clause described below. Clause 1: Micro CANopen Plus may not be used for any competitive or comparative purpose, including the publication of any form of run time or compile time metric, without the express permission of EmSA. Fenopix Technologies Private Limited: Under no circumstances may the CanvasJS software product be used in any way that would compete with any product from Fenopix.  License to the CanvasJS software will terminate immediately without notice if Licensee fail to comply with any provision of this Agreement. Fraunhofer IIS: Fraunhofer MPEG Audio Decoder (Fraunhofer copyright) - If you are provided MPEG-H decoding functionality, you understand that NXP will provide Fraunhofer your name and contact information. Future Technology Devices International Ltd.: Future Technology Devices International software must be used consistent with the terms found here: http://www.ftdichip.com/Drivers/FTDriverLicenceTerms.htm Global Locate (Broadcom Corporation): Use of Global Locate, Inc. software is limited to evaluation and demonstration only. Permitted distributions must be similarly limited. Further rights must be obtained from Global Locate. IAR Systems: Use of IAR flashloader or any IAR source code is subject to the terms of the IAR Source License located within the IAR zip package. The IAR Source License applies to linker command files, example projects unless another license is explicitly stated, the cstartup code, low_level_init.c, and some other low-level runtime library files. LC3plus: the LC3plus Low Complexity Communication Codec Plus (LC3plus) per ETSI TS 103 634 V1.3.1, is subject to ETSI Intellectual Property Rights Policy, See https://portal.etsi.org/directives/45_directives_jun_2022.pdf. For application in an End Product, Fraunhofer communication applies, see https://www.iis.fraunhofer.de/en/ff/amm/communication/lc3.html Microsoft: Except for Microsoft PlayReady software, if the Licensed Software includes software owned by Microsoft Corporation ("Microsoft"), it is subject to the terms of your license with Microsoft (the "Microsoft Underlying Licensed Software") and as such, NXP grants no license to you, beyond evaluation and demonstration in connection with NXP processors, in the Microsoft Underlying Licensed Software. You must separately obtain rights beyond evaluation and demonstration in connection with the Microsoft Underlying Licensed Software from Microsoft. Microsoft does not provide support services for the components provided to you through this Agreement. If you have any questions or require technical assistance, please contact NXP. Microsoft Corporation is a third party beneficiary to this Agreement with the right to enforce the terms of this Agreement. TO THE MAXIMUM EXTENT PERMITTED BY LAW, MICROSOFT AND ITS AFFILIATES DISCLAIM ANY WARRANTIES FOR THE MICROSOFT UNDERLYING LICENSED SOFTWARE. TO THE MAXIMUM EXTENT PERMITTED BY LAW, NEITHER MICROSOFT NOR ITS AFFILIATES WILL BE LIABLE, WHETHER IN CONTRACT, TORT, OR OTHERWISE, FOR ANY DIRECT, INCIDENTAL, SPECIAL, INDIRECT, CONSEQUENTIAL OR PUNITIVE DAMAGES, INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR ANY LOSS OF USE, LOSS OF TIME, INCONVENIENCE, COMMERCIAL LOSS, OR LOST PROFITS, SAVINGS, OR REVENUES, ARISING FROM THE FROM THE USE OF THE MICROSOFT UNDERLYING LICENSED SOFTWARE. With respect to the Microsoft PlayReady software, you will have the license rights granted in Section 2, provided that you may not use the Microsoft PlayReady software unless you have entered into a Microsoft PlayReady Master Agreement and license directly with Microsoft. MindTree: Notwithstanding the terms contained in Section 2.3 (a), if the Licensed Software includes proprietary software of MindTree in source code format, Licensee may make modifications and create derivative works only to the extent necessary for debugging of the Licensed Software. MM SOLUTIONS AD: Use of MM SOLUTIONS AEC (Auto Exposure Control) and AWB (Auto White Balance) software is limited to demonstration, testing, and evaluation only. In no event may Licensee distribute or sublicense the MM SOLUTIONS software. Further rights must be obtained directly from MM SOLUTIONS. MPEG LA: Use of MPEG LA audio or video codec technology is limited to evaluation and demonstration only. Permitted distributions must be similarly limited. Further rights must be obtained directly from MPEG LA. MQX RTOS Code: MQX RTOS source code may not be re-distributed by any NXP Licensee under any circumstance, even by a signed written amendment to this Agreement. NXP Voice Software: VoiceSpot, VoiceSeeker (including AEC), and Conversa may be used for evaluation or demonstration purposes only. Any commercial distribution rights are subject to a separate royalty agreement obtained from NXP. NXP Wireless Charging Library: License to the Software is limited to use in inductive coupling or wireless charging applications Opus: Use of Opus software must be consistent with the terms of the Opus license which can be found at: http://www.opus-codec.org/license/ Oracle JRE (Java): The Oracle JRE must be used consistent with terms found here: http://java.com/license P&E Micro: P&E Software must be used consistent with the terms found here: http://www.pemicro.com/licenses/gdbserver/license_gdb.pdf Pro Design Electronic: Licensee may not modify, create derivative works based on, or copy the Pro Design software, documentation, hardware execution key or the accompanying materials. Licensee shall not use Pro Design's or any of its licensors names, logos or trademarks to market the Authorized System. Only NXP customers and distributors are permitted to further redistribute the Pro Design software and only as part of an Authorized System which contains the Pro Design software. Qualcomm Atheros, Inc.: Notwithstanding anything in this Agreement, Qualcomm Atheros, Inc. Wi-Fi software must be used strictly in accordance with the Qualcomm Atheros, Inc. Technology License Agreement that accompanies such software. Any other use is expressly prohibited. Real Networks - GStreamer Optimized Real Format Client Code implementation or OpenMax Optimized Real Format Client Code: Use of the GStreamer Optimized Real Format Client Code, or OpenMax Optimized Real Format Client code is restricted to applications in the automotive market. Licensee must be a final manufacturer in good standing with a current license with Real Networks for the commercial use and distribution of products containing the GStreamer Optimized Real Format Client Code implementation or OpenMax Optimized Real Format Client Code Real-Time Innovations, Inc.: Not withstanding anything in this Agreement, Real-Time Innovations, Inc. software must be used strictly in accordance with Real-Time Innovations, Inc.'s Automotive Software Evaluation License Agreement, available here: https://www.rti.com/hubfs/_Collateral/Services_and_Support/Automotive_Evaluation_SLA_90_dayNXP.pdf .  Any other use is expressly prohibited. RivieraWaves SAS (a member of the CEVA, Inc. family of companies): You may not use the RivieraWaves intellectual property licensed under this Agreement if you develop, market, and/or license products similar to such RivieraWaves intellectual property. Such use constitutes a breach of this Agreement. Any such use rights must be obtained directly from RivieraWaves. SanDisk Corporation: If the Licensed Software includes software developed by SanDisk Corporation ("SanDisk"), you must separately obtain the rights to reproduce and distribute this software in source code form from SanDisk. Please follow these easy steps to obtain the license and software: (1) Contact your local SanDisk sales representative to obtain the SanDisk License Agreement. (2) Sign the license agreement. Fax the signed agreement to SanDisk USA marketing department at 408-542-0403. The license will be valid when fully executed by SanDisk. (3) If you have specific questions, please send an email to sales@sandisk.com You may only use the SanDisk Corporation Licensed Software on products compatible with a SanDisk Secure Digital Card. You may not use the SanDisk Corporation Licensed Software on any memory device product. SanDisk retains all rights to any modifications or derivative works to the SanDisk Corporation Licensed Software that you may create. SEGGER Microcontroller - emWin Software: Your use of SEGGER emWin software and components is restricted for development of NXP ARM7, ARM9, Cortex-M0, Cortex-M3, Cortex-M4, Cortex-M33, Cortex-M7, and Cortex-A7 based products only. SEGGER Microcontroller - J-Link/J-Trace Software: Segger software must be used consistent with the terms found here: http://www.segger.com/jlink-software.html Synopsys/BLE Software: Your use of the Synopsys/BLE Software and related documentation is subject to the following: (1) Synopsys is third-party beneficiaries of, and thus may enforce against you, the license restrictions and confidentiality obligations in this agreement with respect to their intellectual property and proprietary information. (2) Your distribution of the Licensed Software shall subject any recipient to a written agreement at least as protective of the Licensed Software as provided in this Agreement. Synopsys/Target Compiler Technologies: Your use of the Synopsys/Target Compiler Technologies Licensed Software and related documentation is subject to the following: (1) Duration of the license for the Licensed Software is limited to 12 months, unless otherwise specified in the license file. (2) The Licensed Software is usable by one user at a time on a single designated computer, unless otherwise agreed by Synopsys. (3) Licensed Software and documentation are to be used only on a designated computer at the designated physical address provided by you on the APEX license form. (4) The Licensed Software is not sub-licensable. T2 Labs / T2 Software: As a condition to the grant of any license under this Agreement, you represent and warrant that you will comply with all licenses, agreements, rules and bylaws of the Bluetooth SIG (Special Interest Group ) applicable to the licensed software and documentation and its use which may affect when and if you may take certain actions under licenses granted hereunder. The license grant under this Agreement is conditional to you being (i) a Bluetooth SIG Associate member until such time as the specifications for the software are made public to Bluetooth SIG members of any level and (ii) thereafter a Bluetooth SIG member of any level. Notwithstanding the terms contained in Section 2.3 (a), if the licensed software includes proprietary software in source code format, you may make modifications and create derivative works only to the extent necessary for improving the performance of the source code with the NXP products or your products and for creating enhancements of such products. You may not further sublicense or otherwise distribute the source code, or any modifications or derivatives thereof as stand-alone products. You will be responsible for qualifying any modifications or derivatives with the Bluetooth SIG and any other qualifying bodies. TARA Systems: Use of TARA Systems GUI technology Embedded Wizard is limited to evaluation and demonstration only. Permitted distributions must be similarly limited. Further rights must be obtained directly from TARA Systems. Texas Instruments: Your use of Texas Instruments Inc. WiLink8 Licensed Software is restricted to NXP SoC based systems that include a compatible connectivity device manufactured by TI. TES Electronic Solutions Germany (TES): TES 3D Surround View software and associated data and documentation may only be used for evaluation purposes and for demonstration to third parties in integrated form on a board package containing an NXP S32V234 device. Licensee may not distribute or sublicense the TES software. Your license to the TES software may be terminated at any time upon notice. Vivante: Distribution of Vivante software must be a part of, or embedded within, Authorized Systems that include a Vivante Graphics Processing Unit. \ No newline at end of file diff --git a/LPC804_manifest_v3_10.xml b/LPC804_manifest_v3_13.xml similarity index 62% rename from LPC804_manifest_v3_10.xml rename to LPC804_manifest_v3_13.xml index f11aed2..302699f 100644 --- a/LPC804_manifest_v3_10.xml +++ b/LPC804_manifest_v3_13.xml @@ -1,17 +1,13 @@ - - - - - - - - + + + + - + @@ -33,8 +29,8 @@ - - + + @@ -88,239 +84,234 @@ ${load} - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - + - - - + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - + - + - + - + - + - + - + - + - + - + - + - - - + + + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -332,6 +323,10 @@ ${load} + + + + @@ -392,7 +387,7 @@ ${load} - + @@ -408,24 +403,649 @@ ${load} - + - + + + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + + + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + + - + + + + + + + + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + + + + + - - - - - - - - - + - + + + + + - + + + + + + + - + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + + + - + - + - + + + + - + - + - + + + + - + - + - + + + + + + + - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - + - - - - - - - - - - - - + + - - - - - + + + + + - - - - - + + + + + + + + + + + + + + + + + + + - - - - - - - - - - + - - + + - - + + + + + - - + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + @@ -2891,82 +2717,411 @@ ${load} - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + - + - - - + + + + + + + + + + + + + + + + - + - + - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + - + - - - + + + + + + + + + + + + + + + + - + - + - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -2976,14 +3131,82 @@ ${load} - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -2993,14 +3216,14 @@ ${load} - - - + @@ -3010,14 +3233,14 @@ ${load} - - - + @@ -3027,28 +3250,28 @@ ${load} - - - + - - - + @@ -3058,14 +3281,14 @@ ${load} - - - + @@ -3075,14 +3298,14 @@ ${load} - - - + @@ -3092,14 +3315,14 @@ ${load} - - - + @@ -3109,14 +3332,14 @@ ${load} - - - + @@ -3126,31 +3349,14 @@ ${load} - - - - - - - - - - - - - - - + @@ -3160,28 +3366,14 @@ ${load} - - - - - - - - - - - - + @@ -3194,28 +3386,14 @@ ${load} - - - - - - - - - - - - + @@ -3228,28 +3406,14 @@ ${load} - - - - - - - - - - - - + @@ -3259,14 +3423,14 @@ ${load} - - - + @@ -3276,392 +3440,17 @@ ${load} - - - - - - - - - - - - - - - - - - + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/SW-Content-Register.txt b/SW-Content-Register.txt index c99d490..194650f 100644 --- a/SW-Content-Register.txt +++ b/SW-Content-Register.txt @@ -1,6 +1,6 @@ Release Name: MCUXpresso Software Development Kit (SDK) -Release Version: 2.13.0 -Package License: LA_OPT_NXP_Software_License.txt v39 August 2022- Additional Distribution License granted, license in Section 2.3 applies +Release Version: 2.14.0 +Package License: LA_OPT_NXP_Software_License.txt v45 May 2023- Additional Distribution License granted, license in Section 2.3 applies SDK_Peripheral_Driver Name: SDK Peripheral Driver Version: 2.x.x @@ -13,18 +13,6 @@ SDK_Peripheral_Driver Name: SDK Peripheral Driver Location: devices//drivers Origin: NXP (BSD-3-Clause) -SDK_Examples Name: SDK examples - Version: NA - Outgoing License: BSD-3-Clause - License File: COPYING-BSD-3 - Format: source code, binary, project files, linker - files - Description: SDK out of box examples to show how - to use peripheral drivers and integrate - middleware. - Location: boards// - Origin: NXP (BSD-3-Clause) - SDK_Device Name: SDK SoC files Version: NA Outgoing License: BSD-3-Clause @@ -35,20 +23,6 @@ SDK_Device Name: SDK SoC files Location: devices// Origin: NXP (BSD-3-Clause) -cmsis Name: CMSIS - Version: 5.8.0 - Outgoing License: Apache License 2.0 - License File: CMSIS/LICENSE.txt - Format: source code - Description: Vendor-independent hardware - abstraction layer for microcontrollers that are - based on Arm Cortex processors, distributed by - ARM. cores - Location: CMSIS/ - Origin: ARM (Apache-2.0) - - https://github.com/ARM-software/CMSIS_5/releases/t - ag/5.8.0 - SDK_Components Name: SDK components and board peripheral drivers Version: NA Outgoing License: BSD-3-Clause @@ -59,35 +33,37 @@ SDK_Components Name: SDK components and board peripheral drivers Location: components/ Origin: NXP (BSD-3-Clause), ITE (BSD-3-Clause) -rtcesl Name: rtcesl - Version: 4.7 (CM0,CM4,CM7,CM33) + 4.5 (DSC) +CMSIS Name: CMSIS + Version: 5.8.0 + Outgoing License: Apache License 2.0 + License File: CMSIS/LICENSE.txt + Format: source code + Description: Vendor-independent hardware + abstraction layer for microcontrollers that are + based on Arm Cortex processors, distributed by + ARM. cores + Location: CMSIS/ + Origin: NXP (Apache License 2.0) + +osa Name: OSA + Version: 1.0.0 Outgoing License: BSD-3-Clause License File: COPYING-BSD-3 - Format: object code & header files - Description: NXP Real Time Control Embedded - Software Library. - Location: middleware/rtcesl + Format: source code + Description: NXP USB stack. This is a version of + the USB stack that has been integrated with the + MCUXpresso SDK. Origin: NXP (BSD-3-Clause) + Location: components/osa -safety_iec60730b Name: safety iec60730b - Version: 4.2 - Outgoing License: LA_OPT_NXP_Software_License.txt - v39 August 2022 - Additional distribution license - granted - License in Section 2.3 applies - License File: LA_OPT_NXP_Software_License.txt - Format: source code & object code & header files - Description: Safety IEC60730b Example - Location: middleware/safety_iec60730b - Origin: NXP - -srecord Name: SRecord 1.64 For Windows - Version: 1.64 - Outgoing License: GPL-3.0 - License File: - tool/srecord/srecord-1.64.zip/srecord-1.64/LICENSE - Format: source code & binary - Description: Utility for manipulating EPROM load - files, is used for postbuild CRC calculation. - Location: tools/srecord - Origin: Peter Miller - Url: http://srecord.sourceforge.net/index.html +SDK_Examples Name: SDK examples + Version: NA + Outgoing License: BSD-3-Clause + License File: COPYING-BSD-3 + Format: source code, binary, project files, linker + files + Description: SDK out of box examples to show how + to use peripheral drivers and integrate + middleware. + Location: boards// + Origin: NXP (BSD-3-Clause) diff --git a/boards/lpcxpresso804/demo_apps/hello_world/armgcc/CMakeLists.txt b/boards/lpcxpresso804/demo_apps/hello_world/armgcc/CMakeLists.txt index e525cbe..b7f8d6d 100644 --- a/boards/lpcxpresso804/demo_apps/hello_world/armgcc/CMakeLists.txt +++ b/boards/lpcxpresso804/demo_apps/hello_world/armgcc/CMakeLists.txt @@ -3,8 +3,16 @@ SET(CMAKE_SYSTEM_NAME Generic) CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) # THE VERSION NUMBER -SET (Tutorial_VERSION_MAJOR 1) -SET (Tutorial_VERSION_MINOR 0) +SET (MCUXPRESSO_CMAKE_FORMAT_MAJOR_VERSION 2) +SET (MCUXPRESSO_CMAKE_FORMAT_MINOR_VERSION 0) + +include(ide_overrides.cmake OPTIONAL) + +if(CMAKE_SCRIPT_MODE_FILE) + message("${MCUXPRESSO_CMAKE_FORMAT_MAJOR_VERSION}") + return() +endif() + # ENABLE ASM ENABLE_LANGUAGE(ASM) @@ -34,6 +42,8 @@ endif() include(${ProjDirPath}/flags.cmake) +include(${ProjDirPath}/config.cmake) + add_executable(${MCUX_SDK_PROJECT_NAME} "${ProjDirPath}/../hello_world.c" "${ProjDirPath}/../pin_mux.c" @@ -44,60 +54,12 @@ add_executable(${MCUX_SDK_PROJECT_NAME} "${ProjDirPath}/../clock_config.h" ) -target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE ${ProjDirPath}/.. ) -set(CMAKE_MODULE_PATH - ${SdkRootDirPath}/devices/LPC804/drivers - ${SdkRootDirPath}/devices/LPC804 - ${SdkRootDirPath}/components/uart - ${SdkRootDirPath}/devices/LPC804/utilities/debug_console_lite - ${SdkRootDirPath}/devices/LPC804/utilities - ${SdkRootDirPath}/CMSIS/Core/Include -) - -# include modules -include(driver_common_LPC804) - -include(driver_clock_LPC804) - -include(driver_power_no_lib_LPC804) - -include(driver_reset_LPC804) - -include(device_LPC804_CMSIS_LPC804) - -include(component_miniusart_adapter_LPC804) - -include(device_LPC804_startup_LPC804) - -include(driver_lpc_miniusart_LPC804) - -include(utility_assert_lite_LPC804) - -include(utility_debug_console_lite_LPC804) - -include(driver_lpc_iocon_lite_LPC804) - -include(driver_swm_LPC804) - -include(driver_lpc_gpio_LPC804) - -include(driver_syscon_LPC804) - -include(driver_rom_api_LPC804) - -include(CMSIS_Include_core_cm_LPC804) - -include(utilities_misc_utilities_LPC804) - -include(device_LPC804_system_LPC804) - -include(driver_swm_connections_LPC804) - -include(driver_syscon_connections_LPC804) +include(${SdkRootDirPath}/devices/LPC804/all_lib_device.cmake) IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES) SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys") @@ -109,4 +71,5 @@ target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBR TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) +set_target_properties(${MCUX_SDK_PROJECT_NAME} PROPERTIES ADDITIONAL_CLEAN_FILES "output.map") diff --git a/boards/lpcxpresso804/demo_apps/hello_world/armgcc/config.cmake b/boards/lpcxpresso804/demo_apps/hello_world/armgcc/config.cmake new file mode 100755 index 0000000..a9e8ddf --- /dev/null +++ b/boards/lpcxpresso804/demo_apps/hello_world/armgcc/config.cmake @@ -0,0 +1,34 @@ +# config to select component, the format is CONFIG_USE_${component} +# Please refer to cmake files below to get available components: +# ${SdkRootDirPath}/devices/LPC804/all_lib_device.cmake + +set(CONFIG_COMPILER gcc) +set(CONFIG_TOOLCHAIN armgcc) +set(CONFIG_USE_COMPONENT_CONFIGURATION false) +set(CONFIG_USE_driver_common true) +set(CONFIG_USE_driver_clock true) +set(CONFIG_USE_driver_power_no_lib true) +set(CONFIG_USE_driver_reset true) +set(CONFIG_USE_device_LPC804_CMSIS true) +set(CONFIG_USE_component_miniusart_adapter true) +set(CONFIG_USE_device_LPC804_startup true) +set(CONFIG_USE_driver_lpc_miniusart true) +set(CONFIG_USE_utility_assert_lite true) +set(CONFIG_USE_utility_debug_console_lite true) +set(CONFIG_USE_driver_lpc_iocon_lite true) +set(CONFIG_USE_driver_swm true) +set(CONFIG_USE_driver_lpc_gpio true) +set(CONFIG_USE_driver_syscon true) +set(CONFIG_USE_driver_rom_api true) +set(CONFIG_USE_utilities_misc_utilities true) +set(CONFIG_USE_CMSIS_Include_core_cm true) +set(CONFIG_USE_device_LPC804_system true) +set(CONFIG_USE_driver_swm_connections true) +set(CONFIG_USE_driver_syscon_connections true) +set(CONFIG_CORE cm0p) +set(CONFIG_DEVICE LPC804) +set(CONFIG_BOARD lpcxpresso804) +set(CONFIG_KIT lpcxpresso804) +set(CONFIG_DEVICE_ID LPC804) +set(CONFIG_FPU NO_FPU) +set(CONFIG_DSP NO_DSP) diff --git a/boards/lpcxpresso804/demo_apps/hello_world/hello_world.bin b/boards/lpcxpresso804/demo_apps/hello_world/hello_world.bin index b14f460..db25e6b 100755 Binary files a/boards/lpcxpresso804/demo_apps/hello_world/hello_world.bin and b/boards/lpcxpresso804/demo_apps/hello_world/hello_world.bin differ diff --git a/boards/lpcxpresso804/demo_apps/hello_world/hello_world_v3_10.xml b/boards/lpcxpresso804/demo_apps/hello_world/hello_world_v3_13.xml similarity index 93% rename from boards/lpcxpresso804/demo_apps/hello_world/hello_world_v3_10.xml rename to boards/lpcxpresso804/demo_apps/hello_world/hello_world_v3_13.xml index 2f9ffef..5678dd4 100644 --- a/boards/lpcxpresso804/demo_apps/hello_world/hello_world_v3_10.xml +++ b/boards/lpcxpresso804/demo_apps/hello_world/hello_world_v3_13.xml @@ -16,8 +16,8 @@ - + @@ -27,7 +27,7 @@ - + @@ -62,6 +62,9 @@ + @@ -89,11 +92,15 @@ + + + + @@ -104,7 +111,7 @@ -