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MCUXpresso_LPC804/devices/LPC804/LPC804.xml

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<?xml version="1.0" encoding="UTF-8"?>
<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
<vendor>nxp.com</vendor>
<name>LPC804</name>
<version>1.0</version>
<description>LPC804M101JDH20,LPC804M101JDH24,LPC804M101JHI33,LPC804M111JDH24,LPC804UK</description>
<licenseText>
Copyright 2016-2020 NXP
All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
</licenseText>
<cpu>
<name>CM0PLUS</name>
<revision>r0p0</revision>
<endian>little</endian>
<mpuPresent>false</mpuPresent>
<fpuPresent>false</fpuPresent>
<vtorPresent>true</vtorPresent>
<nvicPrioBits>2</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
<addressUnitBits>8</addressUnitBits>
<width>32</width>
<peripherals>
<peripheral>
<name>WWDT</name>
<description>LPC80X Windowed Watchdog Timer (WWDT)</description>
<groupName>WWDT</groupName>
<baseAddress>0x40000000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1C</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>WDT</name>
<value>12</value>
</interrupt>
<registers>
<register>
<name>MOD</name>
<description>Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer.</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>WDEN</name>
<description>Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the watchdog timer will run permanently.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>STOP</name>
<description>Stop. The watchdog timer is stopped.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RUN</name>
<description>Run. The watchdog timer is running.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WDRESET</name>
<description>Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INTERRUPT</name>
<description>Interrupt. A watchdog time-out will not cause a chip reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RESET</name>
<description>Reset. A watchdog time-out will cause a chip reset.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WDTOF</name>
<description>Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a chip reset if WDRESET = 1.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WDINT</name>
<description>Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the WARNINT value is equal to the value of the TV register. This can occur if the value of WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WDPROTECT</name>
<description>Watchdog update mode. This bit can be set once by software and is only cleared by a reset.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>FLEXIBLE</name>
<description>Flexible. The watchdog time-out value (TC) can be changed at any time.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>THRESHOLD</name>
<description>Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOCK</name>
<description>Once this bit is set to one and a watchdog feed is performed, disabling or powering down the watchdog oscillator is prevented by hardware. This bit can be set once by software and is only cleared by any reset.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TC</name>
<description>Watchdog timer constant register. This 24-bit register determines the time-out value.</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFFFFFF</resetMask>
<fields>
<field>
<name>COUNT</name>
<description>Watchdog time-out value.</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>FEED</name>
<description>Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC.</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>FEED</name>
<description>Feed value should be 0xAA followed by 0x55.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>TV</name>
<description>Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer.</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFFFFFF</resetMask>
<fields>
<field>
<name>COUNT</name>
<description>Counter timer value.</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>WARNINT</name>
<description>Watchdog Warning Interrupt compare value.</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x3FF</resetMask>
<fields>
<field>
<name>WARNINT</name>
<description>Watchdog warning interrupt compare value.</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WINDOW</name>
<description>Watchdog Window compare value.</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFF</resetValue>
<resetMask>0xFFFFFF</resetMask>
<fields>
<field>
<name>WINDOW</name>
<description>Watchdog window value.</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>MRT0</name>
<description>LPC80X Multi-Rate Timer (MRT)</description>
<groupName>MRT</groupName>
<baseAddress>0x40004000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xFC</size>
<usage>registers</usage>
</addressBlock>
<registers>
<cluster>
<dim>4</dim>
<dimIncrement>0x10</dimIncrement>
<name>CHANNEL[%s]</name>
<description>no description available</description>
<addressOffset>0</addressOffset>
<register>
<name>INTVAL</name>
<description>MRT Time interval value register. This value is loaded into the TIMER register.</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x80FFFFFF</resetMask>
<fields>
<field>
<name>IVALUE</name>
<description>Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval.</description>
<bitOffset>0</bitOffset>
<bitWidth>31</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LOAD</name>
<description>Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_FORCE_LOAD</name>
<description>No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FORCE_LOAD</name>
<description>Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TIMER</name>
<description>MRT Timer register. This register reads the value of the down-counter.</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0xFFFFFF</resetValue>
<resetMask>0xFFFFFF</resetMask>
<fields>
<field>
<name>VALUE</name>
<description>Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF).</description>
<bitOffset>0</bitOffset>
<bitWidth>31</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CTRL</name>
<description>MRT Control register. This register controls the MRT modes.</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x7</resetMask>
<fields>
<field>
<name>INTEN</name>
<description>Enable the TIMERn interrupt.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. TIMERn interrupt is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. TIMERn interrupt is enabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects timer mode.</description>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>REPEAT_INTERRUPT_MODE</name>
<description>Repeat interrupt mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ONE_SHOT_INTERRUPT_MODE</name>
<description>One-shot interrupt mode.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>ONE_SHOT_STALL_MODE</name>
<description>One-shot stall mode.</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>STAT</name>
<description>MRT Status register.</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>INTFLAG</name>
<description>Monitors the interrupt flag.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_PENDING_INTERRUPT</name>
<description>No pending interrupt. Writing a zero is equivalent to no operation.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PENDING_INTERRUPT</name>
<description>Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RUN</name>
<description>Indicates the state of TIMERn. This bit is read-only.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>IDLE_STATE</name>
<description>Idle state. TIMERn is stopped.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RUNNING</name>
<description>Running. TIMERn is running.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</cluster>
<register>
<name>MODCFG</name>
<description>Module Configuration register. This register provides information about this particular MRT instance.</description>
<addressOffset>0xF0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1F4</resetValue>
<resetMask>0x1FF</resetMask>
<fields>
<field>
<name>NOC</name>
<description>Identifies the number of channels in this MRT.(4 channels on this device.)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NOB</name>
<description>Identifies the number of timer bits in this MRT. (31 bits wide on this device.)</description>
<bitOffset>4</bitOffset>
<bitWidth>5</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>IDLE_CH</name>
<description>Idle channel register. This register returns the number of the first idle channel.</description>
<addressOffset>0xF4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xF0</resetMask>
<fields>
<field>
<name>CHAN</name>
<description>Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is positioned such that it can be used as an offset from the MRT base address in order to access the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See text above for more details.</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>IRQ_FLAG</name>
<description>Global interrupt flag register</description>
<addressOffset>0xF8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>GFLAG0</name>
<description>Monitors the interrupt flag of TIMER0.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_PENDING_INTERRUPT</name>
<description>No pending interrupt. Writing a zero is equivalent to no operation.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PENDING_INTERRUPT</name>
<description>Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GFLAG1</name>
<description>Monitors the interrupt flag of TIMER1. See description of channel 0.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>WKT</name>
<description>LPC80X Wake Up Timer(WKT)</description>
<groupName>WKT</groupName>
<baseAddress>0x40008000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x10</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>WKT</name>
<value>15</value>
</interrupt>
<registers>
<register>
<name>CTRL</name>
<description>Self wake-up timer control register.</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xF</resetMask>
<fields>
<field>
<name>CLKSEL</name>
<description>Select the self wake-up timer clock source. Remark: This bit only has an effect if the SEL_EXTCLK bit is not set.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DIVIDED_IRC_CLOCK</name>
<description>Divided IRC clock. This clock runs at 750 kHz and provides time-out periods of up to approximately 95 minutes in 1.33 us increments. Remark: This clock is not available in not available in Deep-sleep, power-down, deep power-down modes. Do not select this option if the timer is to be used to wake up from one of these modes.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_POWER_CLOCK</name>
<description>This is the (nominally) 10 kHz clock and provides time-out periods of up to approximately 119 hours in 100 us increments. The accuracy of this clock is limited to +/- 40 % over temperature and processing. Remark: This clock is available in all power modes. Prior to use, the low-power oscillator must be enabled. The oscillator must also be set to remain active in Deep power-down if needed.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ALARMFLAG</name>
<description>Wake-up or alarm timer flag.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_TIME_OUT</name>
<description>No time-out. The self wake-up timer has not timed out. Writing a 0 to has no effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>TIME_OUT</name>
<description>Time-out. The self wake-up timer has timed out. This flag generates an interrupt request which can wake up the part from any reduced power mode including Deep power-down if the clock source is the low power oscillator. Writing a 1 clears this status bit.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLEARCTR</name>
<description>Clears the self wake-up timer.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_EFFECT</name>
<description>No effect. Reading this bit always returns 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR_THE_COUNTER</name>
<description>Clear the counter. Counting is halted until a new count value is loaded.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SEL_EXTCLK</name>
<description>Select external or internal clock source for the self wake-up timer. The internal clock source is selected by the CLKSEL bit in this register if SET_EXTCLK is set to internal.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INTERNAL</name>
<description>Internal. The clock source is the internal clock selected by the CLKSEL bit.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EXTERNAL</name>
<description>External. The self wake-up timer uses the external WKTCLKIN pin.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>COUNT</name>
<description>Counter register.</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>VALUE</name>
<description>A write to this register pre-loads start count value into the timer and starts the count-down sequence. A read reflects the current value of the timer.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SWM0</name>
<description>LPC804 SWM</description>
<groupName>SWM</groupName>
<baseAddress>0x4000C000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1C4</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PINASSIGN0</name>
<description>Pin assign register 0. Assign movable functions U0_TXD, U0_RXD, U0_RTS, U0_CTS.</description>
<alternateGroup>PINASSIGN_PINASSIGN_DATA</alternateGroup>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>U0_TXD_O</name>
<description>U0_TXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>U0_RXD_I</name>
<description>U0_RXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>U0_RTS_O</name>
<description>U0_RTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>U0_CTS_I</name>
<description>U0_CTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PINASSIGN_DATA0</name>
<description>Pin assign register</description>
<alternateGroup>PINASSIGN_PINASSIGN_DATA</alternateGroup>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>T0_MAT3</name>
<description>T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>T0_CAP0</name>
<description>T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>T0_CAP1</name>
<description>T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>T0_CAP2</name>
<description>T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PINASSIGN1</name>
<description>Pin assign register 1. Assign movable functions U0_SCLK, U1_TXD, U1_RXD, U1_SCLK.</description>
<alternateGroup>PINASSIGN_PINASSIGN_DATA</alternateGroup>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>U0_SCLK_IO</name>
<description>U0_SCLK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>U1_TXD_O</name>
<description>U1_TXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>U1_RXD_I</name>
<description>U1_RXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>U1_SCLK_IO</name>
<description>U1_SCLK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PINASSIGN_DATA1</name>
<description>Pin assign register</description>
<alternateGroup>PINASSIGN_PINASSIGN_DATA</alternateGroup>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>T0_MAT3</name>
<description>T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>T0_CAP0</name>
<description>T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>T0_CAP1</name>
<description>T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>T0_CAP2</name>
<description>T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PINASSIGN2</name>
<description>Pin assign register 2. Assign movable functions SPI0_SCK, SPI0_MOSI,SPI0_MISO,SPI0_SSEL0.</description>
<alternateGroup>PINASSIGN_PINASSIGN_DATA</alternateGroup>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SPI0_SCK_IO</name>
<description>SPI0_SCK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SPI0_MOSI_IO</name>
<description>SPI0_MOSI function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SPI0_MISO_IO</name>
<description>SPI0_MISO function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SPI0_SSEL0_IO</name>
<description>SPI0_SSEL0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PINASSIGN_DATA2</name>
<description>Pin assign register</description>
<alternateGroup>PINASSIGN_PINASSIGN_DATA</alternateGroup>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>T0_MAT3</name>
<description>T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>T0_CAP0</name>
<description>T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>T0_CAP1</name>
<description>T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>T0_CAP2</name>
<description>T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PINASSIGN3</name>
<description>Pin assign register 3. Assign movable function SPI0_SSEL1, T0_CAP0, T0_CAP1, T0_CAP2.</description>
<alternateGroup>PINASSIGN_PINASSIGN_DATA</alternateGroup>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SPI0_SSEL1_IO</name>
<description>SPI0_SSEL1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>T0_CAP0</name>
<description>T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>T0_CAP1</name>
<description>T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>T0_CAP2</name>
<description>T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PINASSIGN_DATA3</name>
<description>Pin assign register</description>
<alternateGroup>PINASSIGN_PINASSIGN_DATA</alternateGroup>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>T0_MAT3</name>
<description>T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>T0_CAP0</name>
<description>T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>T0_CAP1</name>
<description>T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>T0_CAP2</name>
<description>T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PINASSIGN4</name>
<description>Pin assign register 4. Assign movable functions T0_MAT0, T0_MAT1,T0_MAT2,T0_MAT3.</description>
<alternateGroup>PINASSIGN_PINASSIGN_DATA</alternateGroup>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>T0_MAT0</name>
<description>T0_MAT0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>T0_MAT1</name>
<description>T0_MAT1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>T0_MAT2</name>
<description>T0_MAT2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>T0_MAT3</name>
<description>T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PINASSIGN_DATA4</name>
<description>Pin assign register</description>
<alternateGroup>PINASSIGN_PINASSIGN_DATA</alternateGroup>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>T0_MAT3</name>
<description>T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>T0_CAP0</name>
<description>T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>T0_CAP1</name>
<description>T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>T0_CAP2</name>
<description>T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PINASSIGN5</name>
<description>Pin assign register 5. Assign movable functions I2C0_SDA, I2C0_SCL, COMP0_OUT, CLKOUT</description>
<alternateGroup>PINASSIGN_PINASSIGN_DATA</alternateGroup>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>I2C0_SDA_IO</name>
<description>I2C0_SDA function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>I2C0_SCL_IO</name>
<description>I2C0_SCL function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>COMP0_OUT_O</name>
<description>COMP0_OUT function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CLKOUT_O</name>
<description>CLKOUT function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PINASSIGN_DATA5</name>
<description>Pin assign register</description>
<alternateGroup>PINASSIGN_PINASSIGN_DATA</alternateGroup>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>T0_MAT3</name>
<description>T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>T0_CAP0</name>
<description>T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>T0_CAP1</name>
<description>T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>T0_CAP2</name>
<description>T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PINASSIGN6</name>
<description>Pin assign register 6. Assign movable functions GPIO_INT_BMAT, LVLSHFT_IN0, LVLSHFT_IN1, LVLSHFT_OUT0.</description>
<alternateGroup>PINASSIGN_PINASSIGN_DATA</alternateGroup>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPIO_INT_BMAT_O</name>
<description>GPIO_INT_BMAT function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LVLSHFT_IN0</name>
<description>LVLSHFT_IN0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LVLSHFT_IN1</name>
<description>LVLSHFT_IN1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LVLSHFT_OUT0</name>
<description>LVLSHFT_OUT0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PINASSIGN_DATA6</name>
<description>Pin assign register</description>
<alternateGroup>PINASSIGN_PINASSIGN_DATA</alternateGroup>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>T0_MAT3</name>
<description>T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>T0_CAP0</name>
<description>T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>T0_CAP1</name>
<description>T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>T0_CAP2</name>
<description>T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PINASSIGN7</name>
<description>Pin assign register 7. Assign movable functions LVLSHFT_OUT1, I2C1_SDA, I2C1_SCL, PLU_CLKIN.</description>
<alternateGroup>PINASSIGN_PINASSIGN_DATA</alternateGroup>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LVLSHFT_OUT1</name>
<description>LVLSHFT_OUT1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>I2C1_SDA_IO</name>
<description>I2C1_SDA function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>I2C1_SCL_IO</name>
<description>I2C1_SCL function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PLU_CLKIN_IN</name>
<description>PLU_CLKIN function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PINASSIGN_DATA7</name>
<description>Pin assign register</description>
<alternateGroup>PINASSIGN_PINASSIGN_DATA</alternateGroup>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>T0_MAT3</name>
<description>T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>T0_CAP0</name>
<description>T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>T0_CAP1</name>
<description>T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>T0_CAP2</name>
<description>T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PINASSIGN8</name>
<description>Pin assign register 8. Assign movable functions CAPT_X0, CAPT_X1, CAPT_X2, CAPT_X3.</description>
<alternateGroup>PINASSIGN_PINASSIGN_DATA</alternateGroup>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CAPT_X0_O</name>
<description>CAPT_X0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CAPT_X1_O</name>
<description>CAPT_X1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CAPT_X2_O</name>
<description>CAPT_X2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CAPT_X3_O</name>
<description>CAPT_X3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PINASSIGN_DATA8</name>
<description>Pin assign register</description>
<alternateGroup>PINASSIGN_PINASSIGN_DATA</alternateGroup>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>T0_MAT3</name>
<description>T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>T0_CAP0</name>
<description>T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>T0_CAP1</name>
<description>T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>T0_CAP2</name>
<description>T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PINASSIGN9</name>
<description>Pin assign register 9. Assign movable functions CAPT_X4, CAPT_YL, CAPT_YH.</description>
<alternateGroup>PINASSIGN_PINASSIGN_DATA</alternateGroup>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFF</resetValue>
<resetMask>0xFFFFFF</resetMask>
<fields>
<field>
<name>CAPT_X4_O</name>
<description>CAPT_X4 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CAPT_YL_O</name>
<description>CAPT_YL function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CAPT_YH_O</name>
<description>CAPT_YH_O function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PINASSIGN_DATA9</name>
<description>Pin assign register</description>
<alternateGroup>PINASSIGN_PINASSIGN_DATA</alternateGroup>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>T0_MAT3</name>
<description>T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>T0_CAP0</name>
<description>T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>T0_CAP1</name>
<description>T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>T0_CAP2</name>
<description>T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_30 (= 0x1E).</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PINASSIGNFIXED0</name>
<description>Pin assign to fixed bits register 0. Pin assign to fixed bits register 0. Assign movable functions PLU_INPUT0 to PLU_INPUT5 and PLU_OUT0 to PLU_INPUT7.</description>
<addressOffset>0x180</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFF</resetValue>
<resetMask>0xFFFFFFF</resetMask>
<fields>
<field>
<name>PLU_INPUT0</name>
<description>PLU_INPUT0 function assignment.</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Assign_PIO0_00</name>
<description>Assign to PIO0_00.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Assign_PIO0_08</name>
<description>Assign to PIO0_08.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>Assign_PIO0_17</name>
<description>Assign to PIO0_17.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>None</name>
<description>None.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLU_INPUT1</name>
<description>PLU_INPUT1 function assignment</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Assign_PIO0_01</name>
<description>Assign to PIO0_01.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Assign_PIO0_09</name>
<description>Assign to PIO0_09.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>Assign_PIO0_18</name>
<description>Assign to PIO0_18.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>None</name>
<description>None.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLU_INPUT2</name>
<description>PLU_INPUT2 function assignment.</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Assign_PIO0_02</name>
<description>Assign to PIO0_02.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Assign_PIO0_10</name>
<description>Assign to PIO0_10.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>Assign_PIO0_19</name>
<description>Assign to PIO0_19.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>None</name>
<description>None.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLU_INPUT3</name>
<description>PLU_INPUT3 function assignment.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Assign_PIO0_03</name>
<description>Assign to PIO0_03.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Assign_PIO0_11</name>
<description>Assign to PIO0_11.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>Assign_PIO0_20</name>
<description>Assign to PIO0_20.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>None</name>
<description>None.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLU_INPUT4</name>
<description>PLU_INPUT4 function assignment.</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Assign_PIO0_04</name>
<description>Assign to PIO0_04.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Assign_PIO0_12</name>
<description>Assign to PIO0_12.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>Assign_PIO0_21</name>
<description>Assign to PIO0_21.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>None</name>
<description>None.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLU_INPUT5</name>
<description>PLU_INPUT5 function assignment.</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Assign_PIO0_05</name>
<description>Assign to PIO0_05.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Assign_PIO0_13</name>
<description>Assign to PIO0_13.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>Assign_PIO0_22</name>
<description>Assign to PIO0_22.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>None</name>
<description>None.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLU_OUT0</name>
<description>PLU_OUT0 function assignment.</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Assign_PIO0_07</name>
<description>Assign to PIO0_07.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Assign_PIO0_14</name>
<description>Assign to PIO0_14.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>Assign_PIO0_23</name>
<description>Assign to PIO0_23.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>None</name>
<description>None.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLU_OUT1</name>
<description>PLU_OUT1 function assignment.</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Assign_PIO0_08</name>
<description>Assign to PIO0_08.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Assign_PIO0_15</name>
<description>Assign to PIO0_15.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>Assign_PIO0_24</name>
<description>Assign to PIO0_24.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>None</name>
<description>None.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLU_OUT2</name>
<description>PLU_OUT2 function assignment.</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Assign_PIO0_09</name>
<description>Assign to PIO0_09.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Assign_PIO0_16</name>
<description>Assign to PIO0_16.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>Assign_PIO0_25</name>
<description>Assign to PIO0_25.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>None</name>
<description>None.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLU_OUT3</name>
<description>PLU_OUT3 function assignment.</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Assign_PIO0_10</name>
<description>Assign to PIO0_10.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Assign_PIO0_17</name>
<description>Assign to PIO0_17.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>Assign_PIO0_26</name>
<description>Assign to PIO0_26.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>None</name>
<description>None.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLU_OUT4</name>
<description>PLU_OUT4 function assignment.</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Assign_PIO0_11</name>
<description>Assign to PIO0_11.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Assign_PIO0_18</name>
<description>Assign to PIO0_18.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>Assign_PIO0_27</name>
<description>Assign to PIO0_27.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>None</name>
<description>None.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLU_OUT5</name>
<description>PLU_OUT5 function assignment.</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Assign_PIO0_12</name>
<description>Assign to PIO0_12.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Assign_PIO0_19</name>
<description>Assign to PIO0_19.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>Assign_PIO0_28</name>
<description>Assign to PIO0_28.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>None</name>
<description>None.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLU_OUT6</name>
<description>PLU_OUT6 function assignment.</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Assign_PIO0_13</name>
<description>Assign to PIO0_13.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Assign_PIO0_20</name>
<description>Assign to PIO0_20.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>Assign_PIO0_29</name>
<description>Assign to PIO0_29.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>None</name>
<description>None.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLU_OUT7</name>
<description>PLU_OUT7 function assignment.</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Assign_PIO0_14</name>
<description>Assign to PIO0_14.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Assign_PIO0_21</name>
<description>Assign to PIO0_21.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>Assign_PIO0_30</name>
<description>Assign to PIO0_30.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>None</name>
<description>None.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PINENABLE0</name>
<description>Pin enable register 0. Enables fixed-pin functions ACMP_I1, ACMP_I2, ACMP_I3,ACMP_I4, SWCLK, SWDIO, RESETN, CLKIN,WKCLK_IN, VDDCMP, ADC_0 - ADC_11,ACMP_I5,DACOUT0.</description>
<addressOffset>0x1C0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFF8F</resetValue>
<resetMask>0xFFFFFF</resetMask>
<fields>
<field>
<name>ACMP_I1</name>
<description>ACMP_I1 function select.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>ACMP_I1 enabled on pin PIO0_00.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>ACMP_I1 disabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACMP_I2</name>
<description>ACMP_I2 function select.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ACMP_I2_0</name>
<description>ACMP_I2 enabled on pin PIO0_1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACMP_I2_1</name>
<description>ACMP_I2 disabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACMP_I3</name>
<description>ACMP_I3 function select.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>ACMP_I3 enabled on pin PIO0_14.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>ACMP_I3 disabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACMP_I4</name>
<description>ACMP_I4 function select.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>ACMP_I4 enabled on pin PIO0_16.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>ACMP_I4 disabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWCLK</name>
<description>SWCLK function select.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>SWCLK enabled on pin PIO0_3.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>SWCLK disabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWDIO</name>
<description>SWDIO function select.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>SWDIO enabled on pin PIO0_2.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>SWDIO disabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESETN</name>
<description>RESETN function select.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>RESETN enabled on pin PIO0_5.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>RESETN disabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKIN</name>
<description>CLKIN function select.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>CLKIN enabled on pin PIO0_1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>CLKIN disabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKCLKIN</name>
<description>WKCLK_IN function select.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>WKCLK_IN enabled on pin PIO0_11.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>WKCLK_IN disabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VDDCMP</name>
<description>VDDCMP function select.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>VDDCMP enabled on pin PIO0_6.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>VDDCMP disabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC_0</name>
<description>ADC_0 function select.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>ADC_0 enabled on pin PIO0_1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>ADC_0 disabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC_1</name>
<description>ADC_1 function select.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>ADC_1 enabled on pin PIO0_7.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>ADC_1 disabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC_2</name>
<description>ADC_2 function select.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>ADC_2 enabled on pin PIO0_14.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>ADC_2 disabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC_3</name>
<description>ADC_3 function select.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>ADC_3 enabled on pin PIO0_16.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>ADC_3 disabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC_4</name>
<description>ADC_4 function select.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>ADC_4 enabled on pin PIO0_9.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>ADC_4 disabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC_5</name>
<description>ADC_5 function select.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>ADC_5 enabled on pin PIO0_8.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>ADC_5 disabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC_6</name>
<description>ADC_6 function select.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>ADC_6 enabled on pin PIO0_11.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>ADC_6 disabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC_7</name>
<description>ADC_7 function select.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>ADC_7 enabled on pin PIO0_10.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>ADC_7 disabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC_8</name>
<description>ADC_8 function select.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>ADC_8 enabled on pin PIO0_15.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>ADC_8 disabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC_9</name>
<description>ADC_9 function select.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>ADC_9 enabled on pin PIO0_17.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>ADC_9 disabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC_10</name>
<description>ADC_10 function select.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>ADC_10 enabled on pin PIO0_13.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>ADC_10 disabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC_11</name>
<description>ADC_11 function select.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>ADC_11 enabled on pin PIO0_4.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>ADC_11 disabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACMP_I5</name>
<description>ACMP_I5 function select.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>ACMP_I5 enabled on pin PIO0_21.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>ACMP_I5 disabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DACOUT0</name>
<description>DACOUT0 function select.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>DACOUT0 enabled on pin PIO0_19.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>DACOUT0 disabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DAC0</name>
<description>LPC80X 10-bit DAC controller (DAC)</description>
<groupName>DAC</groupName>
<baseAddress>0x40014000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xC</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>DAC0</name>
<value>2</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<description>D/A Converter Register. This register contains the digital value to be converted to analog and a power control bit.</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1FFC0</resetMask>
<fields>
<field>
<name>VALUE</name>
<description>After the selected settling time after this field is written with a new VALUE, the voltage on the DAC_OUT pin (with respect to VSSA) is VALUE (VREFP - VREFN)/1024 + VREFN.</description>
<bitOffset>6</bitOffset>
<bitWidth>10</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BIAS</name>
<description>The settling time of the DAC</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>BIAS_0</name>
<description>The settling time of the DAC is 1 us max, and the maximum current is 700 uA. This allows a maximum update rate of 1 MHz.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>BIAS_1</name>
<description>The settling time of the DAC is 2.5 us and the maximum current is 350 uA. This allows a maximum update rate of 400 kHz.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CTRL</name>
<description>DAC Control register. This register controls DMA and timer operation.</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x7</resetMask>
<fields>
<field>
<name>INT_CPU_REQ</name>
<description>Interrupt request to CPU. This interrupt request is handled by the CPU.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear on any write to the CR register.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Set by hardware when the timer times out.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBLBUF_ENA</name>
<description>dacr double buffer</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>DACR double-buffering is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CNT_ENA</name>
<description>time-out counter operation</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Time-out counter operation is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Time-out counter operation is enabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CNTVAL</name>
<description>DAC Counter Value register. This register contains the reload value for the DAC DMA/Interrupt timer.</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>VALUE</name>
<description>16-bit reload value for the DAC interrupt/DMA timer.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>ADC</name>
<description>LPC80X 12-bit ADC controller (ADC)</description>
<groupName>ADC</groupName>
<baseAddress>0x4001C000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x6C</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>ADC_SEQA</name>
<value>16</value>
</interrupt>
<interrupt>
<name>ADC_SEQB</name>
<value>17</value>
</interrupt>
<interrupt>
<name>ADC_THCMP</name>
<value>18</value>
</interrupt>
<interrupt>
<name>ADC_OVR</name>
<value>19</value>
</interrupt>
<registers>
<register>
<name>CTRL</name>
<description>ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls.</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x4FF</resetMask>
<fields>
<field>
<name>CLKDIV</name>
<description>In synchronous mode only, the system clock is divided by this value plus one to produce the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically, software should program the smallest value in this field that yields this maximum clock rate or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. This field is ignored in the asynchronous operating mode.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LPWRMODE</name>
<description>The low-power ADC mode</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>LPWRMODE_0</name>
<description>The low-power ADC mode is disabled. The analog circuitry remains activated even when no conversions are requested.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LPWRMODE_1</name>
<description>The low-power ADC mode is enabled. The analog circuitry is automatically powered-down when no conversions are taking place. When any (hardware or software) triggering event is detected, the analog circuitry is enabled. After the required start-up time, the requested conversion will be launched. Once the conversion completes, the analog-circuitry will again be powered-down provided no further conversions are pending. Using this mode can save an appreciable amount of current (approximately 2.5 mA) when conversions are required relatively infrequently. The penalty for using this mode is an approximately FIFTEEN ADC CLOCK delay (30 clocks in 10-bit mode), based on the frequency specified in the CLKDIV field, from the time the trigger event occurs until sampling of the A/D input commences. Note: This mode will NOT power-up the A/D if the ADC_ENA bit is low.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>A,B</dimIndex>
<name>SEQ_CTRL%s</name>
<description>ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n.</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFDFC7FFF</resetMask>
<fields>
<field>
<name>CHANNELS</name>
<description>Selects which one or more of the ADC channels will be sampled and converted when this sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 and so forth. When this conversion sequence is triggered, either by a hardware trigger or via software command, ADC conversions will be performed on each enabled channel, in sequence, beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31) is LOW. It is allowed to change this field and set bit 31 in the same write.</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TRIGGER</name>
<description>Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field. See Table 476. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TRIGPOL</name>
<description>Select the polarity of the selected input trigger for this conversion sequence. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NEGATIVE_EDGE</name>
<description>Negative edge. A negative edge launches the conversion sequence on the selected trigger input.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>POSITIVE_EDGE</name>
<description>Positive edge. A positive edge launches the conversion sequence on the selected trigger input.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYNCBYPASS</name>
<description>Setting this bit allows the hardware trigger input to bypass synchronization flip-flop stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0): Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLE_TRIGGER_SYNCH</name>
<description>Enable trigger synchronization. The hardware trigger bypass is not enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>BYPASS_TRIGGER_SYNCH</name>
<description>Bypass trigger synchronization. The hardware trigger bypass is enabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TSAMP</name>
<description>Sample Time The default sample period (TSAMP = &quot;00000&quot;) at the beginning of each new conversion is 6.5 ADC clock periods. Depending on a variety of factors including ADC clock rate, output impedance of the analog source driver, ADC resolution, and the selection of channels, the sample time may need to be increased. The value programmed into the TSAMP fields dictates the number of additional ADC clock cycles (beyond 6.5) that the sample period will be extended by. Note that any additional clocks of sample time inserted will add directly to the overall number of clocks required for a conversion, effectively reducing the overall conversion throughput rate.</description>
<bitOffset>20</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>START</name>
<description>Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a conversion sequence. It will consequently always read back as a zero.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BURST</name>
<description>Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions can be halted by clearing this bit. The sequence currently in progress will be completed before conversions are terminated. Note that a new sequence could begin just before BURST is cleared.</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SINGLESTEP</name>
<description>When this bit is set, a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels comprising a sequence have been converted, a subsequent trigger will repeat the sequence beginning with the first enabled channel. Interrupt generation will still occur either after each individual conversion or at the end of the entire sequence, depending on the state of the MODE bit.</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LOWPRIO</name>
<description>Set priority for sequence A.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>LOW_PRIORITY</name>
<description>Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_PRIORITY</name>
<description>High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion currently in progress will be terminated. The A sequence that was interrupted will automatically resume after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the conversion sequence will resume from that point.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQA_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which overrun conditions contribute to an overrun interrupt as described below.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>END_OF_CONVERSION</name>
<description>End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger if enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>END_OF_SEQUENCE</name>
<description>End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun interrupt/DMA trigger since it is assumed this register may not be utilized in this mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SEQ_ENA</name>
<description>Sequence Enable. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. Sequence n is enabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>A,B</dimIndex>
<name>SEQ_GDAT%s</name>
<description>ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n.</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFC0FFFF0</resetMask>
<fields>
<field>
<name>RESULT</name>
<description>This field contains the 12-bit ADC conversion result from the most recent conversion performed under conversion sequence associated with this register. The result is a binary fraction representing the voltage on the currently-selected input channel as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this result has not yet been read.</description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
<access>read-only</access>
</field>
<field>
<name>THCMPRANGE</name>
<description>Indicates whether the result of the last conversion performed was above, below or within the range established by the designated threshold comparison registers (THRn_LOW and THRn_HIGH).</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
<field>
<name>THCMPCROSS</name>
<description>Indicates whether the result of the last conversion performed represented a crossing of the threshold level established by the designated LOW threshold comparison register (THRn_LOW) and, if so, in what direction the crossing occurred.</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CHN</name>
<description>These bits contain the channel from which the RESULT bits were converted (e.g. 0000 identifies channel 0, 0001 channel 1, etc.).</description>
<bitOffset>26</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>OVERRUN</name>
<description>This bit is set if a new conversion result is loaded into the RESULT field before a previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set to '0' (and if the overrun interrupt is enabled).</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DATAVALID</name>
<description>This bit is set to '1' at the end of each conversion when a new result is loaded into the RESULT field. It is cleared whenever this register is read. This bit will cause a conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that sequence is set to 0 (and if the interrupt is enabled).</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>12</dim>
<dimIncrement>0x4</dimIncrement>
<name>DAT[%s]</name>
<description>ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFC0FFFF0</resetMask>
<fields>
<field>
<name>RESULT</name>
<description>This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.</description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
<access>read-only</access>
</field>
<field>
<name>THCMPRANGE</name>
<description>Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
<field>
<name>THCMPCROSS</name>
<description>Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CHANNEL</name>
<description>This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)</description>
<bitOffset>26</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>OVERRUN</name>
<description>This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DATAVALID</name>
<description>This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>THR0_LOW</name>
<description>ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0.</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFF0</resetMask>
<fields>
<field>
<name>THRLOW</name>
<description>Low threshold value against which ADC results will be compared</description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>THR1_LOW</name>
<description>ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1.</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFF0</resetMask>
<fields>
<field>
<name>THRLOW</name>
<description>Low threshold value against which ADC results will be compared</description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>THR0_HIGH</name>
<description>ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0.</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFF0</resetMask>
<fields>
<field>
<name>THRHIGH</name>
<description>High threshold value against which ADC results will be compared</description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>THR1_HIGH</name>
<description>ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1.</description>
<addressOffset>0x5C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFF0</resetMask>
<fields>
<field>
<name>THRHIGH</name>
<description>High threshold value against which ADC results will be compared</description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CHAN_THRSEL</name>
<description>ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFF</resetMask>
<fields>
<field>
<name>CH0_THRSEL</name>
<description>Threshold select for channel 0.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>THRESHOLD0</name>
<description>Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>THRESHOLD1</name>
<description>Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1_THRSEL</name>
<description>Threshold select for channel 1. See description for channel 0.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CH2_THRSEL</name>
<description>Threshold select for channel 2. See description for channel 0.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CH3_THRSEL</name>
<description>Threshold select for channel 3. See description for channel 0.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CH4_THRSEL</name>
<description>Threshold select for channel 4. See description for channel 0.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CH5_THRSEL</name>
<description>Threshold select for channel 5. See description for channel 0.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CH6_THRSEL</name>
<description>Threshold select for channel 6. See description for channel 0.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CH7_THRSEL</name>
<description>Threshold select for channel 7. See description for channel 0.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CH8_THRSEL</name>
<description>Threshold select for channel 8. See description for channel 0.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CH9_THRSEL</name>
<description>Threshold select for channel 9. See description for channel 0.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CH10_THRSEL</name>
<description>Threshold select for channel 10. See description for channel 0.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CH11_THRSEL</name>
<description>Threshold select for channel 11. See description for channel 0.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTEN</name>
<description>ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated.</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x7FFFFFF</resetMask>
<fields>
<field>
<name>SEQA_INTEN</name>
<description>Sequence A interrupt enable.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The sequence A interrupt/DMA trigger is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of conversions, depending on the MODE bit in the SEQA_CTRL register.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SEQB_INTEN</name>
<description>Sequence B interrupt enable.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The sequence B interrupt/DMA trigger is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of conversions, depending on the MODE bit in the SEQB_CTRL register.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OVR_INTEN</name>
<description>Overrun interrupt enable.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The overrun interrupt is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular sequence is 0, then an overrun in the global data register for that sequence will also cause this interrupt/DMA trigger to be asserted.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADCMPINTEN0</name>
<description>Threshold comparison interrupt enable for channel 0.</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OUTSIDE_THRESHOLD</name>
<description>Outside threshold.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CROSSING_THRESHOLD</name>
<description>Crossing threshold.</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADCMPINTEN1</name>
<description>Channel 1 threshold comparison interrupt enable. See description for channel 0.</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ADCMPINTEN2</name>
<description>Channel 2 threshold comparison interrupt enable. See description for channel 0.</description>
<bitOffset>7</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ADCMPINTEN3</name>
<description>Channel 3 threshold comparison interrupt enable. See description for channel 0.</description>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ADCMPINTEN4</name>
<description>Channel 4 threshold comparison interrupt enable. See description for channel 0.</description>
<bitOffset>11</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ADCMPINTEN5</name>
<description>Channel 5 threshold comparison interrupt enable. See description for channel 0.</description>
<bitOffset>13</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ADCMPINTEN6</name>
<description>Channel 6 threshold comparison interrupt enable. See description for channel 0.</description>
<bitOffset>15</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ADCMPINTEN7</name>
<description>Channel 7 threshold comparison interrupt enable. See description for channel 0.</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ADCMPINTEN8</name>
<description>Channel 8 threshold comparison interrupt enable. See description for channel 0.</description>
<bitOffset>19</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ADCMPINTEN9</name>
<description>Channel 9 threshold comparison interrupt enable. See description for channel 0.</description>
<bitOffset>21</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ADCMPINTEN10</name>
<description>Channel 10 threshold comparison interrupt enable. See description for channel 0.</description>
<bitOffset>23</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ADCMPINTEN11</name>
<description>Channel 21 threshold comparison interrupt enable. See description for channel 0.</description>
<bitOffset>25</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>FLAGS</name>
<description>ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers).</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xF3FFFFFF</resetMask>
<fields>
<field>
<name>THCMP0</name>
<description>Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>THCMP1</name>
<description>Threshold comparison event on Channel 1. See description for channel 0.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>THCMP2</name>
<description>Threshold comparison event on Channel 2. See description for channel 0.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>THCMP3</name>
<description>Threshold comparison event on Channel 3. See description for channel 0.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>THCMP4</name>
<description>Threshold comparison event on Channel 4. See description for channel 0.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>THCMP5</name>
<description>Threshold comparison event on Channel 5. See description for channel 0.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>THCMP6</name>
<description>Threshold comparison event on Channel 6. See description for channel 0.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>THCMP7</name>
<description>Threshold comparison event on Channel 7. See description for channel 0.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>THCMP8</name>
<description>Threshold comparison event on Channel 8. See description for channel 0.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>THCMP9</name>
<description>Threshold comparison event on Channel 9. See description for channel 0.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>THCMP10</name>
<description>Threshold comparison event on Channel 10. See description for channel 0.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>THCMP11</name>
<description>Threshold comparison event on Channel 11. See description for channel 0.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>OVERRUN0</name>
<description>Mirrors the OVERRRUN status flag from the result register for ADC channel 0</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>OVERRUN1</name>
<description>Mirrors the OVERRRUN status flag from the result register for ADC channel 1</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>OVERRUN2</name>
<description>Mirrors the OVERRRUN status flag from the result register for ADC channel 2</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>OVERRUN3</name>
<description>Mirrors the OVERRRUN status flag from the result register for ADC channel 3</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>OVERRUN4</name>
<description>Mirrors the OVERRRUN status flag from the result register for ADC channel 4</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>OVERRUN5</name>
<description>Mirrors the OVERRRUN status flag from the result register for ADC channel 5</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>OVERRUN6</name>
<description>Mirrors the OVERRRUN status flag from the result register for ADC channel 6</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>OVERRUN7</name>
<description>Mirrors the OVERRRUN status flag from the result register for ADC channel 7</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>OVERRUN8</name>
<description>Mirrors the OVERRRUN status flag from the result register for ADC channel 8</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>OVERRUN9</name>
<description>Mirrors the OVERRRUN status flag from the result register for ADC channel 9</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>OVERRUN10</name>
<description>Mirrors the OVERRRUN status flag from the result register for ADC channel 10</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>OVERRUN11</name>
<description>Mirrors the OVERRRUN status flag from the result register for ADC channel 11</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SEQA_OVR</name>
<description>Mirrors the global OVERRUN status flag in the SEQA_GDAT register</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SEQB_OVR</name>
<description>Mirrors the global OVERRUN status flag in the SEQB_GDAT register</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SEQA_INT</name>
<description>Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which is set at the end of every ADC conversion performed as part of sequence A. It will be cleared automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register is 1, this flag will be set upon completion of an entire A sequence. In this case it must be cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN register.</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SEQB_INT</name>
<description>Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which is set at the end of every ADC conversion performed as part of sequence B. It will be cleared automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register is 1, this flag will be set upon completion of an entire B sequence. In this case it must be cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN register.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>THCMP_INT</name>
<description>Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in the lower bits of this register are set to 1 (due to an enabled out-of-range or threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be individually enabled in the INTEN register to cause this interrupt. This bit will be cleared when all of the individual threshold flags are cleared via writing 1s to those bits.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>OVR_INT</name>
<description>Overrun Interrupt flag. Any overrun bit in any of the individual channel data registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all of the individual overrun bits have been cleared via reading the corresponding data registers.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PMU</name>
<description>LPC80X PMU</description>
<groupName>PMU</groupName>
<baseAddress>0x40020000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x28</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PCON</name>
<description>Power control register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x90F</resetMask>
<fields>
<field>
<name>PM</name>
<description>Power mode</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DEFAULT</name>
<description>Default. The part is in active or sleep mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DEEP_SLEEP_MODE</name>
<description>Deep-sleep mode. ARM WFI will enter Deep-sleep mode.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>POWER_DOWN_MODE</name>
<description>Power-down mode. ARM WFI will enter Power-down mode.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>DEEP_POWER_DOWN_MODE</name>
<description>Deep power-down mode. ARM WFI will enter Deep-power down mode (ARM Cortex-M0+ core powered-down).</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NODPD</name>
<description>A 1 in this bit prevents entry to Deep power-down mode when 0x3 is written to the PM field above, the SLEEPDEEP bit is set, and a WFI is executed. This bit is cleared only by power-on reset, so writing a one to this bit locks the part in a mode in which Deep power-down mode is blocked.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SLEEPFLAG</name>
<description>Sleep mode flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ACTIVE_MODE</name>
<description>Active mode. Read: No power-down mode entered. Part is in Active mode. Write: No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_POWER_MODE</name>
<description>Low power mode. Read: Sleep, Deep-sleep or Power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DPDFLAG</name>
<description>Deep power-down flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_DEEP_POWER_DOWN</name>
<description>Not Deep power-down. Read: Deep power-down mode not entered. Write: No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DEEP_POWER_DOWN</name>
<description>Deep power-down. Read: Deep power-down mode entered. Write: Clear the Deep power-down flag.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>5</dim>
<dimIncrement>0x4</dimIncrement>
<name>GPREG[%s]</name>
<description>General purpose register N</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPDATA</name>
<description>Data retained during Deep power-down mode.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WUSRCREG</name>
<description>Pin wake-up source register</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WUSRCREG</name>
<description>Pin wake-up source</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WUENAREG</name>
<description>Pin wake-up enable register</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WUENAREG</name>
<description>Pin wake-up enable</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>ACOMP</name>
<description>LPC80X analog comparator</description>
<groupName>ACOMP</groupName>
<baseAddress>0x40024000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x8</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CTRL</name>
<description>Comparator control register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x6C03F58</resetMask>
<fields>
<field>
<name>EDGESEL</name>
<description>This field controls which edges on the comparator output set the COMPEDGE bit (bit 23 below):</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>FALLING_EDGES</name>
<description>Falling edges</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RISING_EDGES</name>
<description>Rising edges</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>BOTH_EDGES0</name>
<description>Both edges</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>BOTH_EDGES1</name>
<description>Both edges</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COMPSA</name>
<description>Comparator output control</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>COMPSA_0</name>
<description>Comparator output is used directly.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>COMPSA_1</name>
<description>Comparator output is synchronized to the bus clock for output to other modules.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COMP_VP_SEL</name>
<description>Selects positive voltage input</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>VOLTAGE_LADDER_OUTPUT</name>
<description>VOLTAGE_LADDER_OUTPUT</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACMP_I1</name>
<description>ACMP_I1</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>ACMP_I2</name>
<description>ACMP_I2</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>ACMP_I3</name>
<description>ACMP_I3</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>ACMP_I4</name>
<description>ACMP_I4</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>ACMP_I5</name>
<description>ACMP_I5</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>BAND_GAP</name>
<description>Band gap. Internal reference voltage.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>DACOUT0</name>
<description>DAC0 output</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COMP_VM_SEL</name>
<description>Selects negative voltage input</description>
<bitOffset>11</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>VOLTAGE_LADDER_OUTPUT</name>
<description>VOLTAGE_LADDER_OUTPUT</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACMP_I1</name>
<description>ACMP_I1</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>ACMP_I2</name>
<description>ACMP_I2</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>ACMP_I3</name>
<description>ACMP_I3</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>ACMP_I4</name>
<description>ACMP_I4</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>ACMP_I5</name>
<description>ACMP_I5</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>BAND_GAP</name>
<description>Band gap. Internal reference voltage.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>DACOUT0</name>
<description>DAC0 output</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EDGECLR</name>
<description>Interrupt clear bit. To clear the COMPEDGE bit and thus negate the interrupt request, toggle the EDGECLR bit by first writing a 1 and then a 0.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>COMPSTAT</name>
<description>Comparator status. This bit reflects the state of the comparator output.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>COMPEDGE</name>
<description>Comparator edge-detect status.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INTENA</name>
<description>Must be set to generate interrupts.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HYS</name>
<description>Controls the hysteresis of the comparator. When the comparator is outputting a certain state, this is the difference between the selected signals, in the opposite direction from the state being output, that will switch the output.</description>
<bitOffset>25</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>HYS_0</name>
<description>None (the output will switch as the voltages cross)</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HYS_1</name>
<description>5 mv</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>HYS_2</name>
<description>10 mv</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>HYS_3</name>
<description>20 mv</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>LAD</name>
<description>Voltage ladder register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LADEN</name>
<description>Voltage ladder enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LADSEL</name>
<description>Voltage ladder value. The reference voltage Vref depends on the LADREF bit below. 00000 = VSS 00001 = 1 x Vref/31 00010 = 2 x Vref/31 ... 11111 = Vref</description>
<bitOffset>1</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LADREF</name>
<description>Selects the reference voltage Vref for the voltage ladder.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>LADREF_0</name>
<description>Supply pin VDD</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LADREF_1</name>
<description>VDDCMP pin</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PLU</name>
<description>LPC80X Programmable Logic Unit (PLU)</description>
<groupName>PLU</groupName>
<baseAddress>0x40028000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xC20</size>
<usage>registers</usage>
</addressBlock>
<registers>
<cluster>
<dim>26</dim>
<dimIncrement>0x20</dimIncrement>
<name>LUT[%s]</name>
<description>no description available</description>
<addressOffset>0</addressOffset>
<register>
<dim>5</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2,3,4</dimIndex>
<name>LUT_INP_MUX%s</name>
<description>LUTLUTn input INPx MUX</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>LUTn_INPx</name>
<description>Selects the input source to be connected to LUT0 input0. For each LUT, the slot associated with the output from LUTn itself is tied low.</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>plu_inputs0</name>
<description>The PLU primary inputs 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>plu_inputs1</name>
<description>The PLU primary inputs 1.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>plu_inputs2</name>
<description>The PLU primary inputs 2.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>plu_inputs3</name>
<description>The PLU primary inputs 3.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>plu_inputs4</name>
<description>The PLU primary inputs 4.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>plu_inputs5</name>
<description>The PLU primary inputs 5.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>lut_outputs0</name>
<description>The output of LUT0.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>lut_outputs1</name>
<description>The output of LUT1.</description>
<value>0x7</value>
</enumeratedValue>
<enumeratedValue>
<name>lut_outputs2</name>
<description>The output of LUT2.</description>
<value>0x8</value>
</enumeratedValue>
<enumeratedValue>
<name>lut_outputs3</name>
<description>The output of LUT3.</description>
<value>0x9</value>
</enumeratedValue>
<enumeratedValue>
<name>lut_outputs4</name>
<description>The output of LUT4.</description>
<value>0xA</value>
</enumeratedValue>
<enumeratedValue>
<name>lut_outputs5</name>
<description>The output of LUT5.</description>
<value>0xB</value>
</enumeratedValue>
<enumeratedValue>
<name>lut_outputs6</name>
<description>The output of LUT6.</description>
<value>0xC</value>
</enumeratedValue>
<enumeratedValue>
<name>lut_outputs7</name>
<description>The output of LUT7.</description>
<value>0xD</value>
</enumeratedValue>
<enumeratedValue>
<name>lut_outputs8</name>
<description>The output of LUT8.</description>
<value>0xE</value>
</enumeratedValue>
<enumeratedValue>
<name>lut_outputs9</name>
<description>The output of LUT9.</description>
<value>0xF</value>
</enumeratedValue>
<enumeratedValue>
<name>lut_outputs10</name>
<description>The output of LUT10.</description>
<value>0x10</value>
</enumeratedValue>
<enumeratedValue>
<name>lut_outputs11</name>
<description>The output of LUT11.</description>
<value>0x11</value>
</enumeratedValue>
<enumeratedValue>
<name>lut_outputs12</name>
<description>The output of LUT12.</description>
<value>0x12</value>
</enumeratedValue>
<enumeratedValue>
<name>lut_outputs13</name>
<description>The output of LUT13.</description>
<value>0x13</value>
</enumeratedValue>
<enumeratedValue>
<name>lut_outputs14</name>
<description>The output of LUT14.</description>
<value>0x14</value>
</enumeratedValue>
<enumeratedValue>
<name>lut_outputs15</name>
<description>The output of LUT15.</description>
<value>0x15</value>
</enumeratedValue>
<enumeratedValue>
<name>lut_outputs16</name>
<description>The output of LUT16.</description>
<value>0x16</value>
</enumeratedValue>
<enumeratedValue>
<name>lut_outputs17</name>
<description>The output of LUT17.</description>
<value>0x17</value>
</enumeratedValue>
<enumeratedValue>
<name>lut_outputs18</name>
<description>The output of LUT18.</description>
<value>0x18</value>
</enumeratedValue>
<enumeratedValue>
<name>lut_outputs19</name>
<description>The output of LUT19.</description>
<value>0x19</value>
</enumeratedValue>
<enumeratedValue>
<name>lut_outputs20</name>
<description>The output of LUT20.</description>
<value>0x1A</value>
</enumeratedValue>
<enumeratedValue>
<name>lut_outputs21</name>
<description>The output of LUT21.</description>
<value>0x1B</value>
</enumeratedValue>
<enumeratedValue>
<name>lut_outputs22</name>
<description>The output of LUT22.</description>
<value>0x1C</value>
</enumeratedValue>
<enumeratedValue>
<name>lut_outputs23</name>
<description>The output of LUT23.</description>
<value>0x1D</value>
</enumeratedValue>
<enumeratedValue>
<name>lut_outputs24</name>
<description>The output of LUT24.</description>
<value>0x1E</value>
</enumeratedValue>
<enumeratedValue>
<name>lut_outputs25</name>
<description>The output of LUT25.</description>
<value>0x1F</value>
</enumeratedValue>
<enumeratedValue>
<name>state0</name>
<description>state(0).</description>
<value>0x20</value>
</enumeratedValue>
<enumeratedValue>
<name>state1</name>
<description>state(1).</description>
<value>0x21</value>
</enumeratedValue>
<enumeratedValue>
<name>state2</name>
<description>state(2).</description>
<value>0x22</value>
</enumeratedValue>
<enumeratedValue>
<name>state3</name>
<description>state(3).</description>
<value>0x23</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</cluster>
<register>
<dim>26</dim>
<dimIncrement>0x4</dimIncrement>
<name>LUT_TRUTH[%s]</name>
<description>Specifies the Truth Table contents for LUTLUTn</description>
<addressOffset>0x800</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LUTn_TRUTH</name>
<description>Specifies the Truth Table contents for LUT0..</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OUTPUTS</name>
<description>Provides the current state of the 8 designated PLU Outputs.</description>
<addressOffset>0x900</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>OUTPUT_STATE</name>
<description>Provides the current state of the 8 designated PLU Outputs..</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>0x4</dimIncrement>
<name>OUTPUT_MUX[%s]</name>
<description>Selects the source to be connected to PLU Output OUTPUT_n</description>
<addressOffset>0xC00</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>OUTPUTn</name>
<description>Selects the source to be connected to PLU Output 0.</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>plu_output0</name>
<description>The PLU output 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>plu_output1</name>
<description>The PLU output 1.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>plu_output2</name>
<description>The PLU output 2.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>plu_output3</name>
<description>The PLU output 3.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>plu_output4</name>
<description>The PLU output 4.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>plu_output5</name>
<description>The PLU output 5.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>plu_output6</name>
<description>The PLU output 6.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>plu_output7</name>
<description>The PLU output 7.</description>
<value>0x7</value>
</enumeratedValue>
<enumeratedValue>
<name>plu_output8</name>
<description>The PLU output 8.</description>
<value>0x8</value>
</enumeratedValue>
<enumeratedValue>
<name>plu_output9</name>
<description>The PLU output 9.</description>
<value>0x9</value>
</enumeratedValue>
<enumeratedValue>
<name>plu_output10</name>
<description>The PLU output 10.</description>
<value>0xA</value>
</enumeratedValue>
<enumeratedValue>
<name>plu_output11</name>
<description>The PLU output 11.</description>
<value>0xB</value>
</enumeratedValue>
<enumeratedValue>
<name>plu_output12</name>
<description>The PLU output 12.</description>
<value>0xC</value>
</enumeratedValue>
<enumeratedValue>
<name>plu_output13</name>
<description>The PLU output 13.</description>
<value>0xD</value>
</enumeratedValue>
<enumeratedValue>
<name>plu_output14</name>
<description>The PLU output 14.</description>
<value>0xE</value>
</enumeratedValue>
<enumeratedValue>
<name>plu_output15</name>
<description>The PLU output 15.</description>
<value>0xF</value>
</enumeratedValue>
<enumeratedValue>
<name>plu_output16</name>
<description>The PLU output 16.</description>
<value>0x10</value>
</enumeratedValue>
<enumeratedValue>
<name>plu_output17</name>
<description>The PLU output 17.</description>
<value>0x11</value>
</enumeratedValue>
<enumeratedValue>
<name>plu_output18</name>
<description>The PLU output 18.</description>
<value>0x12</value>
</enumeratedValue>
<enumeratedValue>
<name>plu_output19</name>
<description>The PLU output 19.</description>
<value>0x13</value>
</enumeratedValue>
<enumeratedValue>
<name>plu_output20</name>
<description>The PLU output 20.</description>
<value>0x14</value>
</enumeratedValue>
<enumeratedValue>
<name>plu_output21</name>
<description>The PLU output 21.</description>
<value>0x15</value>
</enumeratedValue>
<enumeratedValue>
<name>plu_output22</name>
<description>The PLU output 22.</description>
<value>0x16</value>
</enumeratedValue>
<enumeratedValue>
<name>plu_output23</name>
<description>The PLU output 23.</description>
<value>0x17</value>
</enumeratedValue>
<enumeratedValue>
<name>plu_output24</name>
<description>The PLU output 24.</description>
<value>0x18</value>
</enumeratedValue>
<enumeratedValue>
<name>plu_output25</name>
<description>The PLU output 25.</description>
<value>0x19</value>
</enumeratedValue>
<enumeratedValue>
<name>state0</name>
<description>state(0).</description>
<value>0x1A</value>
</enumeratedValue>
<enumeratedValue>
<name>state1</name>
<description>state(1).</description>
<value>0x1B</value>
</enumeratedValue>
<enumeratedValue>
<name>state2</name>
<description>state(2).</description>
<value>0x1C</value>
</enumeratedValue>
<enumeratedValue>
<name>state3</name>
<description>state(3).</description>
<value>0x1D</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CTIMER0</name>
<description>LPC80X Standard counter/timer</description>
<groupName>CTIMER</groupName>
<baseAddress>0x40038000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x88</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>CTIMER0</name>
<value>23</value>
</interrupt>
<registers>
<register>
<name>IR</name>
<description>Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending.</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xEF</resetMask>
<fields>
<field>
<name>MR0INT</name>
<description>Interrupt flag for match channel 0.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MR1INT</name>
<description>Interrupt flag for match channel 1.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MR2INT</name>
<description>Interrupt flag for match channel 2.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MR3INT</name>
<description>Interrupt flag for match channel 3.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CR0INT</name>
<description>Interrupt flag for capture channel 0 event.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CR1INT</name>
<description>Interrupt flag for capture channel 1 event.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CR2INT</name>
<description>Interrupt flag for capture channel 2 event.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TCR</name>
<description>Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>CEN</name>
<description>Counter enable.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.The counters are disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The Timer Counter and Prescale Counter are enabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CRST</name>
<description>Counter reset.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. Do nothing.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of the APB bus clock. The counters remain reset until TCR[1] is returned to zero.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TC</name>
<description>Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR.</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TCVAL</name>
<description>Timer counter value.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PR</name>
<description>Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC.</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PRVAL</name>
<description>Prescale counter value.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PC</name>
<description>Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PCVAL</name>
<description>Prescale counter value.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MCR</name>
<description>Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xF000FFF</resetMask>
<fields>
<field>
<name>MR0I</name>
<description>Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 = disabled. 1 = enabled.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MR0R</name>
<description>Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MR0S</name>
<description>Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MR1I</name>
<description>Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 = disabled. 1 = enabled. 0 = disabled. 1 = enabled.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MR1R</name>
<description>Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MR1S</name>
<description>Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MR2I</name>
<description>Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MR2R</name>
<description>Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MR2S</name>
<description>Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MR3I</name>
<description>Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MR3R</name>
<description>Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MR3S</name>
<description>Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MR0RL</name>
<description>Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MR1RL</name>
<description>Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MR2RL</name>
<description>Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MR3RL</name>
<description>Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled.</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x4</dimIncrement>
<name>MR[%s]</name>
<description>Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MATCH</name>
<description>Timer counter match value.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CCR</name>
<description>Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1FF</resetMask>
<fields>
<field>
<name>CAP0RE</name>
<description>Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CAP0FE</name>
<description>Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CAP0I</name>
<description>Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CAP1RE</name>
<description>Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CAP1FE</name>
<description>Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CAP1I</name>
<description>Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CAP2RE</name>
<description>Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CAP2FE</name>
<description>Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CAP2I</name>
<description>Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>3</dim>
<dimIncrement>0x4</dimIncrement>
<name>CR[%s]</name>
<description>Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CAP</name>
<description>Timer counter capture value.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>EMR</name>
<description>External Match Register. The EMR controls the match function and the external match pins.</description>
<addressOffset>0x3C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFF</resetMask>
<fields>
<field>
<name>EM0</name>
<description>External Match 0. This bit reflects the state of output MAT0, whether or not this output is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EM1</name>
<description>External Match 1. This bit reflects the state of output MAT1, whether or not this output is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EM2</name>
<description>External Match 2. This bit reflects the state of output MAT2, whether or not this output is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EM3</name>
<description>External Match 3. This bit reflects the state of output MAT3, whether or not this output is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EMC0</name>
<description>External Match Control 0. Determines the functionality of External Match 0.</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DO_NOTHING</name>
<description>Do Nothing.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE</name>
<description>Toggle. Toggle the corresponding External Match bit/output.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EMC1</name>
<description>External Match Control 1. Determines the functionality of External Match 1.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DO_NOTHING</name>
<description>Do Nothing.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE</name>
<description>Toggle. Toggle the corresponding External Match bit/output.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EMC2</name>
<description>External Match Control 2. Determines the functionality of External Match 2.</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DO_NOTHING</name>
<description>Do Nothing.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE</name>
<description>Toggle. Toggle the corresponding External Match bit/output.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EMC3</name>
<description>External Match Control 3. Determines the functionality of External Match 3.</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DO_NOTHING</name>
<description>Do Nothing.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE</name>
<description>Toggle. Toggle the corresponding External Match bit/output.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CTCR</name>
<description>Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>CTMODE</name>
<description>Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>TIMER</name>
<description>Timer Mode. Incremented every rising APB bus clock edge.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>COUNTER_RISING_EDGE</name>
<description>Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>COUNTER_FALLING_EDGE</name>
<description>Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>COUNTER_DUAL_EDGE</name>
<description>Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CINSEL</name>
<description>Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>CHANNEL_0</name>
<description>Channel 0. CAPn.0 for CTIMERn</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CHANNEL_1</name>
<description>Channel 1. CAPn.1 for CTIMERn</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CHANNEL_2</name>
<description>Channel 2. CAPn.2 for CTIMERn</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CHANNEL_3</name>
<description>Channel 3. CAPn.3 for CTIMERn</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ENCC</name>
<description>Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SELCC</name>
<description>Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved.</description>
<bitOffset>5</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>CHANNEL_0_RISING</name>
<description>Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CHANNEL_0_FALLING</name>
<description>Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CHANNEL_1_RISING</name>
<description>Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CHANNEL_1_FALLING</name>
<description>Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set).</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>CHANNEL_2_RISING</name>
<description>Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set).</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>CHANNEL_2_FALLING</name>
<description>Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set).</description>
<value>0x5</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PWMC</name>
<description>PWM Control Register. The PWMCON enables PWM mode for the external match pins.</description>
<addressOffset>0x74</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xF</resetMask>
<fields>
<field>
<name>PWMEN0</name>
<description>PWM mode enable for channel0.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>MATCH</name>
<description>Match. CTIMERn_MAT0 is controlled by EM0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PWM</name>
<description>PWM. PWM mode is enabled for CTIMERn_MAT0.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PWMEN1</name>
<description>PWM mode enable for channel1.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>MATCH</name>
<description>Match. CTIMERn_MAT01 is controlled by EM1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PWM</name>
<description>PWM. PWM mode is enabled for CTIMERn_MAT1.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PWMEN2</name>
<description>PWM mode enable for channel2.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>MATCH</name>
<description>Match. CTIMERn_MAT2 is controlled by EM2.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PWM</name>
<description>PWM. PWM mode is enabled for CTIMERn_MAT2.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PWMEN3</name>
<description>PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>MATCH</name>
<description>Match. CTIMERn_MAT3 is controlled by EM3.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PWM</name>
<description>PWM. PWM mode is enabled for CT132Bn_MAT3.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x4</dimIncrement>
<name>MSR[%s]</name>
<description>Match Shadow Register . If enabled, the Match Register will be automatically reloaded with the contents of this register whenever the TC is reset to zero.</description>
<addressOffset>0x78</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MATCH_Shadow</name>
<description>Timer counter match value.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>IOCON</name>
<description>LPC804 I/O pin configuration (IOCON)</description>
<groupName>IOCON</groupName>
<baseAddress>0x40044000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x78</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PIO0_17</name>
<description>Digital I/O control for pins PIO0_17</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xB0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN</name>
<description>Pull-down. Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP</name>
<description>Pull-up. Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER</name>
<description>Repeater. Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERTED</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PIO0_13</name>
<description>Digital I/O control for pins PIO0_13</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xB0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN</name>
<description>Pull-down. Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP</name>
<description>Pull-up. Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER</name>
<description>Repeater. Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERTED</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PIO0_12</name>
<description>Digital I/O control for pins PIO0_12</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xB0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN</name>
<description>Pull-down. Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP</name>
<description>Pull-up. Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER</name>
<description>Repeater. Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERTED</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PIO0_5</name>
<description>Digital I/O control for pins PIO0_5</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xB0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN</name>
<description>Pull-down. Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP</name>
<description>Pull-up. Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER</name>
<description>Repeater. Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERTED</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PIO0_4</name>
<description>Digital I/O control for pins PIO0_4</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xB0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN</name>
<description>Pull-down. Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP</name>
<description>Pull-up. Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER</name>
<description>Repeater. Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERTED</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PIO0_3</name>
<description>Digital I/O control for pins PIO0_3</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xB0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN</name>
<description>Pull-down. Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP</name>
<description>Pull-up. Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER</name>
<description>Repeater. Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERTED</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PIO0_2</name>
<description>Digital I/O control for pins PIO0_2</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xB0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN</name>
<description>Pull-down. Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP</name>
<description>Pull-up. Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER</name>
<description>Repeater. Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERTED</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PIO0_11</name>
<description>Digital I/O control for pins PIO0_11</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xB0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN</name>
<description>Pull-down. Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP</name>
<description>Pull-up. Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER</name>
<description>Repeater. Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERTED</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PIO0_10</name>
<description>Digital I/O control for pins PIO0_10</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xB0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN</name>
<description>Pull-down. Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP</name>
<description>Pull-up. Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER</name>
<description>Repeater. Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERTED</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PIO0_16</name>
<description>Digital I/O control for pins PIO0_16</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xB0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN</name>
<description>Pull-down. Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP</name>
<description>Pull-up. Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER</name>
<description>Repeater. Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERTED</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PIO0_15</name>
<description>Digital I/O control for pins PIO0_15</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xB0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN</name>
<description>Pull-down. Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP</name>
<description>Pull-up. Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER</name>
<description>Repeater. Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERTED</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PIO0_1</name>
<description>Digital I/O control for pins PIO0_1</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xB0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN</name>
<description>Pull-down. Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP</name>
<description>Pull-up. Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER</name>
<description>Repeater. Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERTED</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PIO0_21</name>
<description>Digital I/O control for pins PIO0_21</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xB0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN</name>
<description>Pull-down. Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP</name>
<description>Pull-up. Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER</name>
<description>Repeater. Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERTED</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PIO0_9</name>
<description>Digital I/O control for pins PIO0_9</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xB0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN</name>
<description>Pull-down. Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP</name>
<description>Pull-up. Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER</name>
<description>Repeater. Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERTED</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PIO0_8</name>
<description>Digital I/O control for pins PIO0_8</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xB0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN</name>
<description>Pull-down. Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP</name>
<description>Pull-up. Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER</name>
<description>Repeater. Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERTED</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PIO0_7</name>
<description>Digital I/O control for pins PIO0_7</description>
<addressOffset>0x3C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xB0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN</name>
<description>Pull-down. Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP</name>
<description>Pull-up. Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER</name>
<description>Repeater. Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERTED</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PIO0_29</name>
<description>Digital I/O control for pins PIO0_29</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xB0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN</name>
<description>Pull-down. Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP</name>
<description>Pull-up. Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER</name>
<description>Repeater. Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERTED</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PIO0_0</name>
<description>Digital I/O control for pins PIO0_0</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xB0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN</name>
<description>Pull-down. Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP</name>
<description>Pull-up. Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER</name>
<description>Repeater. Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERTED</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PIO0_14</name>
<description>Digital I/O control for pins PIO0_14</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xB0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN</name>
<description>Pull-down. Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP</name>
<description>Pull-up. Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER</name>
<description>Repeater. Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERTED</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PIO0_28</name>
<description>Digital I/O control for pins PIO0_28</description>
<addressOffset>0x4C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xB0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN</name>
<description>Pull-down. Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP</name>
<description>Pull-up. Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER</name>
<description>Repeater. Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERTED</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PIO0_27</name>
<description>Digital I/O control for pins PIO0_27</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xB0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN</name>
<description>Pull-down. Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP</name>
<description>Pull-up. Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER</name>
<description>Repeater. Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERTED</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PIO0_26</name>
<description>Digital I/O control for pins PIO0_26</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xB0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN</name>
<description>Pull-down. Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP</name>
<description>Pull-up. Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER</name>
<description>Repeater. Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERTED</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PIO0_20</name>
<description>Digital I/O control for pins PIO0_20</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xB0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN</name>
<description>Pull-down. Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP</name>
<description>Pull-up. Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER</name>
<description>Repeater. Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERTED</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PIO0_30</name>
<description>Digital I/O control for pins PIO0_30</description>
<addressOffset>0x5C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xB0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN</name>
<description>Pull-down. Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP</name>
<description>Pull-up. Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER</name>
<description>Repeater. Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERTED</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PIO0_19</name>
<description>Digital I/O control for pins PIO0_19</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xB0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN</name>
<description>Pull-down. Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP</name>
<description>Pull-up. Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER</name>
<description>Repeater. Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERTED</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DACMODE</name>
<description>DAC mode enable.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PIO0_25</name>
<description>Digital I/O control for pins PIO0_25</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xB0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN</name>
<description>Pull-down. Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP</name>
<description>Pull-up. Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER</name>
<description>Repeater. Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERTED</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PIO0_24</name>
<description>Digital I/O control for pins PIO0_24</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xB0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN</name>
<description>Pull-down. Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP</name>
<description>Pull-up. Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER</name>
<description>Repeater. Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERTED</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PIO0_23</name>
<description>Digital I/O control for pins PIO0_23</description>
<addressOffset>0x6C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xB0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN</name>
<description>Pull-down. Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP</name>
<description>Pull-up. Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER</name>
<description>Repeater. Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERTED</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PIO0_22</name>
<description>Digital I/O control for pins PIO0_22</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xB0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN</name>
<description>Pull-down. Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP</name>
<description>Pull-up. Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER</name>
<description>Repeater. Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERTED</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PIO0_18</name>
<description>Digital I/O control for pins PIO0_18</description>
<addressOffset>0x74</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xB0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN</name>
<description>Pull-down. Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP</name>
<description>Pull-up. Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER</name>
<description>Repeater. Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERTED</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SYSCON</name>
<description>LPC80X System configuration (SYSCON)</description>
<groupName>SYSCON</groupName>
<baseAddress>0x40048000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x3FC</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SYSMEMREMAP</name>
<description>System Remap register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x2</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>MAP</name>
<description>System memory remap. Value 0x2 is reserved.</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>BOOT_LOADER_MODE</name>
<description>Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>USER_RAM_MODE</name>
<description>User RAM Mode. Interrupt vectors are re-mapped to Static RAM.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>USER_FLASH_MODE</name>
<description>User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash.</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SYSRSTSTAT</name>
<description>System reset status register.</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x17</resetMask>
<fields>
<field>
<name>POR_BOD</name>
<description>POR and BOD reset status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EXTRST</name>
<description>Status of the external RESET pin</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>EXTRST_0</name>
<description>no description available</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WDT</name>
<description>Status of the Watchdog reset.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SYSRST</name>
<description>Status of the software system reset.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MAINCLKSEL</name>
<description>Main clock source select register</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>SEL</name>
<description>Clock source for main clock.</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>FRO</name>
<description>FRO.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EXT_CLK</name>
<description>External clock.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>WDTOSC</name>
<description>Low power oscillator.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>FRO_DIV</name>
<description>FRO_DIV.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MAINCLKUEN</name>
<description>Main clock source update enable register.</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>ENA</name>
<description>Enable main clock source update</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_CHANGE</name>
<description>no change</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>UPDATED</name>
<description>update clock source</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SYSAHBCLKDIV</name>
<description>System clock divider register</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DIV</name>
<description>System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CAPTCLKSEL</name>
<description>Capacitive Touch clock source select.</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x7</resetValue>
<resetMask>0x7</resetMask>
<fields>
<field>
<name>SEL</name>
<description>Peripheral clock source.</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>FRO</name>
<description>FRO</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Main_clock</name>
<description>Main clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>FRO_DIV</name>
<description>FRO_DIV = FRO/2</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>Low_power_oscillator</name>
<description>Low power oscillator</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>SEL_7</name>
<description>None</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ADCCLKSEL</name>
<description>ADC clock source select register</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>SEL</name>
<description>Clock source for ADC clock</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>FRO</name>
<description>FRO</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>External_clock</name>
<description>External clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SEL_3</name>
<description>None</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ADCCLKDIV</name>
<description>ADC clock divider register</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DIV</name>
<description>ADC clock divider values 0: ADC clock disabled. 1: Divide by 1. to 255: Divide by 255.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>LPOSCCLKEN</name>
<description>WDT and Wake Timer clock enable control.</description>
<addressOffset>0x7C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>WDT</name>
<description>Enables clock for WDT</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Disable</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enable</name>
<description>Enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKT</name>
<description>Enables clock for Wake Timer</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Disable</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enable</name>
<description>Enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SYSAHBCLKCTRL0</name>
<description>System clock group 0 control register</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1F</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SYS</name>
<description>Enables the clock for the AHB, the APB bridge, the Cortex-M0+ core clocks, SYSCON, and the PMU. This bit is read only and always reads as 1.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ROM</name>
<description>Enables clock for ROM.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RAM0</name>
<description>Enables clock for SRAM0</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLASH</name>
<description>Enables clock for flash.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C0</name>
<description>Enables clock for I2C0.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIO0</name>
<description>Enables clock for GPIO0 port registers.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWM</name>
<description>Enables clock for switch matrix.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKT</name>
<description>Enables clock for self-wake-up timer.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MRT</name>
<description>Enables clock for multi-rate timer.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI0</name>
<description>Enables clock for SPI0.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CRC</name>
<description>Enables clock for CRC.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART0</name>
<description>Enables clock for UART0.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART1</name>
<description>Enables clock for UART1.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WWDT</name>
<description>Enables clock for WWDT.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IOCON</name>
<description>Enables clock for IOCON.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACMP</name>
<description>Enables clock for analog comparator.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C1</name>
<description>Enables clock for I2C1.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC</name>
<description>Enables clock for ADC.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CTIMER</name>
<description>Enables clock for CTIMER.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DAC</name>
<description>Enables clock for DAC.</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIO_INT</name>
<description>Enable clock for GPIO pin interrupt registers</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SYSAHBCLKCTRL1</name>
<description>System clock group 1 control register</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CAPT</name>
<description>Enables the clock for Capacitive Touch.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PLU</name>
<description>Enables clock for PLU.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PRESETCTRL0</name>
<description>Peripheral reset group 0 control register</description>
<addressOffset>0x88</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FLASH_RST_N</name>
<description>flash controller reset control</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ASSERT</name>
<description>Assert the flash controller reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear the flash controller reset.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C0_RST_N</name>
<description>I2C0 reset control</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ASSERT</name>
<description>Assert the I2C0 reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear the I2C0 reset.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIO0_RST_N</name>
<description>GPIO0 reset control</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ASSERT</name>
<description>Assert the GPIO0 reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear the GPIO0 reset.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWM_RST_N</name>
<description>SWM reset control</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ASSERT</name>
<description>Assert the SWM reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear the SWM reset.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKT_RST_N</name>
<description>Self-wake-up timer (WKT) reset control</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ASSERT</name>
<description>Assert the WKT reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear the WKT reset.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MRT_RST_N</name>
<description>Multi-rate timer (MRT) reset control</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ASSERT</name>
<description>Assert the MRT reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear the MRT reset.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI0_RST_N</name>
<description>SPI0 reset control</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ASSERT</name>
<description>Assert the SPI0 reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear the SPI0 reset.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CRC_RST_N</name>
<description>CRC engine reset control</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ASSERT</name>
<description>Assert the CRC reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear the CRC reset.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART0_RST_N</name>
<description>UART0 reset control</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ASSERT</name>
<description>Assert the UART0 reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ClEAR</name>
<description>Clear the UART0 reset.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART1_RST_N</name>
<description>UART1 reset control</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ASSERT</name>
<description>Assert the UART1 reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear the UART1 reset.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IOCON_RST_N</name>
<description>IOCON reset control</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ASSERT</name>
<description>Assert the IOCON reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear the IOCON reset.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACMP_RST_N</name>
<description>Analog comparator reset control</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ASSERT</name>
<description>Assert the analog comparator reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear the analog comparator reset.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C1_RST_N</name>
<description>I2C1 reset control.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ASSERT</name>
<description>Assert the I2C1 reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear the I2C1 reset.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC_RST_N</name>
<description>ADC reset control</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ASSERT</name>
<description>Assert the ADC reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear the ADC reset.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CTIMER0_RST_N</name>
<description>CTIMER reset control</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ASSERT</name>
<description>Assert the CTIMER reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear the CTIMER reset.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DAC0_RST_N</name>
<description>DAC0 reset control.</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ASSERT</name>
<description>Assert the DAC0 reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear the DAC0 reset.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOINT_RST_N</name>
<description>GPIOINT reset control</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ASSERT</name>
<description>Assert the GPIOINT reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear the GPIOINT reset.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PRESETCTRL1</name>
<description>Peripheral reset group 1 control register</description>
<addressOffset>0x8C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x3F</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>CAPT_RST_N</name>
<description>Capacitive Touch reset control.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ASSERT</name>
<description>Assert Capacitive Touch reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear Capacitive Touch reset.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FRG0_RST_N</name>
<description>Fractional baud rate generator 0 reset control</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ASSERT</name>
<description>Assert the FRG0 reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear the FRG0 reset.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLU_RST_N</name>
<description>PLU reset control.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ASSERT</name>
<description>Assert PLU reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear PLU reset.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>UART0CLKSEL</name>
<description>Function clock source select for UART0.</description>
<addressOffset>0x90</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x7</resetValue>
<resetMask>0x7</resetMask>
<fields>
<field>
<name>SEL</name>
<description>Peripheral clock source</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>FRO</name>
<description>FRO</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MAIN_CLK</name>
<description>main clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>FRO0CLK</name>
<description>Frg0clk</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>NONE</name>
<description>none</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>FRO_DIV</name>
<description>FRO_DIV</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>NONE1</name>
<description>none</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>NONE2</name>
<description>none</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>NONE3</name>
<description>none</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>UART1CLKSEL</name>
<description>Function clock source select for UART1.</description>
<addressOffset>0x94</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x7</resetValue>
<resetMask>0x7</resetMask>
<fields>
<field>
<name>SEL</name>
<description>Peripheral clock source</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>FRO</name>
<description>FRO</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MAIN_CLK</name>
<description>main clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>FRO0CLK</name>
<description>Frg0clk</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>NONE</name>
<description>none</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>FRO_DIV</name>
<description>FRO_DIV</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>NONE1</name>
<description>none</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>NONE2</name>
<description>none</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>NONE3</name>
<description>none</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>I2C0CLKSEL</name>
<description>Function clock source select for I2C0.</description>
<addressOffset>0xA4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x7</resetValue>
<resetMask>0x7</resetMask>
<fields>
<field>
<name>SEL</name>
<description>Peripheral clock source</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>FRO</name>
<description>FRO</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MAIN_CLK</name>
<description>main clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>FRO0CLK</name>
<description>Frg0clk</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>NONE</name>
<description>none</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>FRO_DIV</name>
<description>FRO_DIV</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>NONE1</name>
<description>none</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>NONE2</name>
<description>none</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>NONE3</name>
<description>none</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>I2C1CLKSEL</name>
<description>Function clock source select for I2C1.</description>
<addressOffset>0xA8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x7</resetValue>
<resetMask>0x7</resetMask>
<fields>
<field>
<name>SEL</name>
<description>Peripheral clock source</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>FRO</name>
<description>FRO</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MAIN_CLK</name>
<description>main clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>FRO0CLK</name>
<description>Frg0clk</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>NONE</name>
<description>none</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>FRO_DIV</name>
<description>FRO_DIV</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>NONE1</name>
<description>none</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>NONE2</name>
<description>none</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>NONE3</name>
<description>none</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SPI0CLKSEL</name>
<description>Function clock source select for SPI0.</description>
<addressOffset>0xB4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x7</resetValue>
<resetMask>0x7</resetMask>
<fields>
<field>
<name>SEL</name>
<description>Peripheral clock source</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>FRO</name>
<description>FRO</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MAIN_CLK</name>
<description>main clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>FRO0CLK</name>
<description>Frg0clk</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>NONE</name>
<description>none</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>FRO_DIV</name>
<description>FRO_DIV</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>NONE1</name>
<description>none</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>NONE2</name>
<description>none</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>NONE3</name>
<description>none</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FRG0DIV</name>
<description>fractional generator divider value register</description>
<addressOffset>0xD0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DIV</name>
<description>Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>FRG0MULT</name>
<description>fractional generator multiplier value register</description>
<addressOffset>0xD4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MULT</name>
<description>Numerator of the fractional divider. MULT is equal to the programmed value.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>FRG0CLKSEL</name>
<description>FRG clock source select register</description>
<addressOffset>0xD8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>SEL</name>
<description>Clock source for frgN_src clock</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>FRO</name>
<description>FRO</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MAIN_CLK</name>
<description>main clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>NONE</name>
<description>None</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CLKOUTSEL</name>
<description>CLKOUT clock source select register</description>
<addressOffset>0xF0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SEL</name>
<description>CLKOUT clock source</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>FRO</name>
<description>FRO</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MAIN_CLK</name>
<description>main clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>EXT_CLK</name>
<description>external clock</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>Low_power_oscillator</name>
<description>Low power oscillator</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>SEL_7</name>
<description>None</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CLKOUTDIV</name>
<description>CLKOUT clock divider registers</description>
<addressOffset>0xF4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DIV</name>
<description>CLKOUT clock divider values 0: Disable CLKOUT clock divider. 1: Divide by 1. to 255: Divide by 255.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PIOPORACP</name>
<description>POR captured PIO0 status 0</description>
<addressOffset>0x100</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>PIOSTAT</name>
<description>State of PIO0_0 to PIO0_5 and PIO0_7 to PIO0_17 at power-on reset</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>BODCTRL</name>
<description>BOD control register</description>
<addressOffset>0x150</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x10</resetValue>
<resetMask>0x1F</resetMask>
<fields>
<field>
<name>BODRSTLEV</name>
<description>BOD reset level</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>LEVEL_1</name>
<description>Level 1</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>LEVEL_2</name>
<description>Level 2</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>LEVEL_3</name>
<description>Level 3</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BODINTVAL</name>
<description>BOD interrupt level</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>LEVEL_1</name>
<description>Level 1</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>LEVEL_2</name>
<description>Level 2</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>LEVEL_3</name>
<description>Level 3</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BODRSTENA</name>
<description>BOD reset enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable reset function.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable reset function.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SYSTCKCAL</name>
<description>System tick timer calibration register</description>
<addressOffset>0x154</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x3FFFFFF</resetMask>
<fields>
<field>
<name>CAL</name>
<description>System tick timer calibration value.</description>
<bitOffset>0</bitOffset>
<bitWidth>26</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>IRQLATENCY</name>
<description>IRQ latency register</description>
<addressOffset>0x170</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x10</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>LATENCY</name>
<description>8-bit latency value.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>NMISRC</name>
<description>NMI source selection register</description>
<addressOffset>0x174</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x8000001F</resetMask>
<fields>
<field>
<name>IRQN</name>
<description>The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) if bit 31 is 1</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>NMIEN</name>
<description>Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>0x4</dimIncrement>
<name>PINTSEL[%s]</name>
<description>Pin interrupt select registers N</description>
<addressOffset>0x178</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>INTPIN</name>
<description>Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_5 correspond to numbers 0 to 5. PIO0_7 to PIO0_30 correspond to numbers 7 to 30.)</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>STARTERP0</name>
<description>Start logic 0 pin wake-up enable register 0</description>
<addressOffset>0x204</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PINT0</name>
<description>GPIO pin interrupt 0 wake-up</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PINT1</name>
<description>GPIO pin interrupt 1 wake-up</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PINT2</name>
<description>GPIO pin interrupt 2 wake-up</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PINT3</name>
<description>GPIO pin interrupt 3 wake-up</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PINT4</name>
<description>GPIO pin interrupt 4 wake-up</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PINT5</name>
<description>GPIO pin interrupt 5 wake-up</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PINT6</name>
<description>GPIO pin interrupt 6 wake-up</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PINT7</name>
<description>GPIO pin interrupt 7 wake-up</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>STARTERP1</name>
<description>Start logic 0 pin wake-up enable register 1</description>
<addressOffset>0x214</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xB9D9</resetMask>
<fields>
<field>
<name>SPI0</name>
<description>SPI0 interrupt wake-up</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART0</name>
<description>USART0 interrupt wake-up. Configure USART in synchronous slave mode.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART1</name>
<description>USART1 interrupt wake-up. Configure USART in synchronous slave mode.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLU</name>
<description>PLU interrupt wake-up.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C1</name>
<description>I2C1 interrupt wake-up.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C0</name>
<description>I2C0 interrupt wake-up.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CAPT</name>
<description>CAPT interrupt wake-up.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WWDT</name>
<description>WWDT interrupt wake-up</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BOD</name>
<description>BOD interrupt wake-up</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WKT</name>
<description>Self-wake-up timer interrupt wake-up</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDSLEEPCFG</name>
<description>Deep-sleep configuration register</description>
<addressOffset>0x230</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFF</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>BOD_PD</name>
<description>BOD power-down control for Deep-sleep and Power-down mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>POWERED</name>
<description>powered</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>powered down</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPOSC_PD</name>
<description>Low power oscillator power-down control for deep-sleep and power-down mode. Changing this bit to powered-down has no effect when the LOCK bit in the WWDT MOD register is set. In this case, the low power oscillator is always running.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDAWAKECFG</name>
<description>Wake-up configuration register</description>
<addressOffset>0x234</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xA050</resetValue>
<resetMask>0xA05F</resetMask>
<fields>
<field>
<name>FROOUT_PD</name>
<description>FRO oscillator output wake-up configuration</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>POWERED</name>
<description>powered</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>powered down</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FRO_PD</name>
<description>FRO oscillator power-down wake-up configuration</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>POWERED</name>
<description>powered</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>powered down</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLASH_PD</name>
<description>Flash wake-up configuration</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>POWERED</name>
<description>powered</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>powered down</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BOD_PD</name>
<description>BOD wake-up configuration</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>POWERED</name>
<description>powered</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>powered down</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC_PD</name>
<description>ADC wake-up configuration</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>POWERED</name>
<description>powered</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>powered down</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPOSC_PD</name>
<description>Low power oscillator wake-up configuration. Changing this bit to powered-down has no effect when the LOCK bit in the WWDT MOD register is set. In this case, the low power oscillator is always running.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DAC</name>
<description>DAC0 wake-up configuration.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACMP</name>
<description>Analog comparator wake-up configuration</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDRUNCFG</name>
<description>Power configuration register</description>
<addressOffset>0x238</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xA078</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FROOUT_PD</name>
<description>FRO oscillator output wake-up configuration</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>POWERED</name>
<description>powered</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>powered down</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FRO_PD</name>
<description>FRO oscillator power-down wake-up configuration</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>POWERED</name>
<description>powered</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>powered down</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLASH_PD</name>
<description>Flash wake-up configuration</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>POWERED</name>
<description>powered</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>powered down</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BOD_PD</name>
<description>BOD wake-up configuration</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>POWERED</name>
<description>powered</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>powered down</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC_PD</name>
<description>ADC wake-up configuration</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>POWERED</name>
<description>powered</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>powered down</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPOSC_PD</name>
<description>Low power oscillator power down. Changing this bit to powered-down has no effect when the LOCK bit in the WWDT MOD register is set. In this case, the low power oscillator is always running.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DAC0</name>
<description>DAC0 wake-up configuration.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACMP</name>
<description>Analog comparator wake-up configuration</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DEVICE_ID</name>
<description>Device ID register</description>
<addressOffset>0x3F8</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>DEVICEID</name>
<description>Used to read the part identification number.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>I2C0</name>
<description>LPC80X I2C-bus interfaces</description>
<groupName>I2C</groupName>
<headerStructName>I2C</headerStructName>
<baseAddress>0x40050000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x84</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>I2C0</name>
<value>8</value>
</interrupt>
<registers>
<register>
<name>CFG</name>
<description>Configuration for shared functions.</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1F</resetMask>
<fields>
<field>
<name>MSTEN</name>
<description>Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The I2C Master function is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The I2C Master function is enabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLVEN</name>
<description>Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The I2C slave function is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The I2C slave function is enabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MONEN</name>
<description>Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The I2C Monitor function is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The I2C Monitor function is enabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIMEOUTEN</name>
<description>I2C bus Time-out Enable. When disabled, the time-out function is internally reset.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. Time-out function is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MONCLKSTR</name>
<description>Monitor function Clock Stretching.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>STAT</name>
<description>Status register for Master, Slave, and Monitor functions.</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x801</resetValue>
<resetMask>0x30FFF5F</resetMask>
<fields>
<field>
<name>MSTPENDING</name>
<description>Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>IN_PROGRESS</name>
<description>In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PENDING</name>
<description>Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSTSTATE</name>
<description>Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses.</description>
<bitOffset>1</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>IDLE</name>
<description>Idle. The Master function is available to be used for a new transaction.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RECEIVE_READY</name>
<description>Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>TRANSMIT_READY</name>
<description>Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>NACK_ADDRESS</name>
<description>NACK Address. Slave NACKed address.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>NACK_DATA</name>
<description>NACK Data. Slave NACKed transmitted data.</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSTARBLOSS</name>
<description>Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_LOSS</name>
<description>No Arbitration Loss has occurred.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ARBITRATION_LOSS</name>
<description>Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSTSTSTPERR</name>
<description>Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_ERROR</name>
<description>No Start/Stop Error has occurred.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ERROR</name>
<description>The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLVPENDING</name>
<description>Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>IN_PROGRESS</name>
<description>In progress. The Slave function does not currently need service.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PENDING</name>
<description>Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLVSTATE</name>
<description>Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes.</description>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>SLAVE_ADDRESS</name>
<description>Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SLAVE_RECEIVE</name>
<description>Slave receive. Received data is available (Slave Receiver mode).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SLAVE_TRANSMIT</name>
<description>Slave transmit. Data can be transmitted (Slave Transmitter mode).</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLVNOTSTR</name>
<description>Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>STRETCHING</name>
<description>Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NOT_STRETCHING</name>
<description>Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLVIDX</name>
<description>Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here.</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>ADDRESS0</name>
<description>Address 0. Slave address 0 was matched.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ADDRESS1</name>
<description>Address 1. Slave address 1 was matched.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>ADDRESS2</name>
<description>Address 2. Slave address 2 was matched.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>ADDRESS3</name>
<description>Address 3. Slave address 3 was matched.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLVSEL</name>
<description>Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SELECTED</name>
<description>Not selected. The Slave function is not currently selected.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SELECTED</name>
<description>Selected. The Slave function is currently selected.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLVDESEL</name>
<description>Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_DESELECTED</name>
<description>Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DESELECTED</name>
<description>Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MONRDY</name>
<description>Monitor Ready. This flag is cleared when the MONRXDAT register is read.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_DATA</name>
<description>No data. The Monitor function does not currently have data available.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DATA_WAITING</name>
<description>Data waiting. The Monitor function has data waiting to be read.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MONOV</name>
<description>Monitor Overflow flag.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_OVERRUN</name>
<description>No overrun. Monitor data has not overrun.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OVERRUN</name>
<description>Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MONACTIVE</name>
<description>Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>Inactive. The Monitor function considers the I2C bus to be inactive.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACTIVE</name>
<description>Active. The Monitor function considers the I2C bus to be active.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MONIDLE</name>
<description>Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_IDLE</name>
<description>Not idle. The I2C bus is not idle, or this flag has been cleared by software.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>IDLE</name>
<description>Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EVENTTIMEOUT</name>
<description>Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_TIMEOUT</name>
<description>No time-out. I2C bus events have not caused a time-out.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EVEN_TIMEOUT</name>
<description>Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SCLTIMEOUT</name>
<description>SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_TIMEOUT</name>
<description>No time-out. SCL low time has not caused a time-out.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMEOUT</name>
<description>Time-out. SCL low time has caused a time-out.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>INTENSET</name>
<description>Interrupt Enable Set and read register.</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x30B8951</resetMask>
<fields>
<field>
<name>MSTPENDINGEN</name>
<description>Master Pending interrupt Enable.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The MstPending interrupt is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The MstPending interrupt is enabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSTARBLOSSEN</name>
<description>Master Arbitration Loss interrupt Enable.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The MstArbLoss interrupt is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The MstArbLoss interrupt is enabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSTSTSTPERREN</name>
<description>Master Start/Stop Error interrupt Enable.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The MstStStpErr interrupt is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The MstStStpErr interrupt is enabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLVPENDINGEN</name>
<description>Slave Pending interrupt Enable.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The SlvPending interrupt is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The SlvPending interrupt is enabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLVNOTSTREN</name>
<description>Slave Not Stretching interrupt Enable.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The SlvNotStr interrupt is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The SlvNotStr interrupt is enabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLVDESELEN</name>
<description>Slave Deselect interrupt Enable.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The SlvDeSel interrupt is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The SlvDeSel interrupt is enabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MONRDYEN</name>
<description>Monitor data Ready interrupt Enable.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The MonRdy interrupt is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The MonRdy interrupt is enabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MONOVEN</name>
<description>Monitor Overrun interrupt Enable.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The MonOv interrupt is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The MonOv interrupt is enabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MONIDLEEN</name>
<description>Monitor Idle interrupt Enable.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The MonIdle interrupt is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The MonIdle interrupt is enabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EVENTTIMEOUTEN</name>
<description>Event time-out interrupt Enable.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The Event time-out interrupt is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The Event time-out interrupt is enabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SCLTIMEOUTEN</name>
<description>SCL time-out interrupt Enable.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The SCL time-out interrupt is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The SCL time-out interrupt is enabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>INTENCLR</name>
<description>Interrupt Enable Clear register.</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>MSTPENDINGCLR</name>
<description>Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>MSTARBLOSSCLR</name>
<description>Master Arbitration Loss interrupt clear.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>MSTSTSTPERRCLR</name>
<description>Master Start/Stop Error interrupt clear.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SLVPENDINGCLR</name>
<description>Slave Pending interrupt clear.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SLVNOTSTRCLR</name>
<description>Slave Not Stretching interrupt clear.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SLVDESELCLR</name>
<description>Slave Deselect interrupt clear.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>MONRDYCLR</name>
<description>Monitor data Ready interrupt clear.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>MONOVCLR</name>
<description>Monitor Overrun interrupt clear.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>MONIDLECLR</name>
<description>Monitor Idle interrupt clear.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>EVENTTIMEOUTCLR</name>
<description>Event time-out interrupt clear.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SCLTIMEOUTCLR</name>
<description>SCL time-out interrupt clear.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>TIMEOUT</name>
<description>Time-out value register.</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFF</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>TOMIN</name>
<description>Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks.</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TO</name>
<description>Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock.</description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLKDIV</name>
<description>Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function.</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>DIVVAL</name>
<description>This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is divided by 65,536 before use.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTSTAT</name>
<description>Interrupt Status register for Master, Slave, and Monitor functions.</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x801</resetValue>
<resetMask>0x30B1951</resetMask>
<fields>
<field>
<name>MSTPENDING</name>
<description>Master Pending.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>MSTARBLOSS</name>
<description>Master Arbitration Loss flag.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>MSTSTSTPERR</name>
<description>Master Start/Stop Error flag.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SLVPENDING</name>
<description>Slave Pending.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SLVNOTSTR</name>
<description>Slave Not Stretching status.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SLVDESEL</name>
<description>Slave Deselected flag.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>MONRDY</name>
<description>Monitor Ready.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>MONOV</name>
<description>Monitor Overflow flag.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>MONIDLE</name>
<description>Monitor Idle flag.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EVENTTIMEOUT</name>
<description>Event time-out Interrupt flag.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SCLTIMEOUT</name>
<description>SCL time-out Interrupt flag.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>MSTCTL</name>
<description>Master control register.</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x7</resetMask>
<fields>
<field>
<name>MSTCONTINUE</name>
<description>Master Continue.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_EFFECT</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Continue</name>
<description>Informs the Master function to continue to the next operation.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSTSTART</name>
<description>Master Start control.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_EFFECT</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>START</name>
<description>Start. A Start will be generated on the I2C bus at the next allowed time.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSTSTOP</name>
<description>Master Stop control.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_EFFECT</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>STOP</name>
<description>Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MSTTIME</name>
<description>Master timing configuration.</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x77</resetValue>
<resetMask>0x77</resetMask>
<fields>
<field>
<name>MSTSCLLOW</name>
<description>Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW.</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>CLOCKS_2</name>
<description>2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLOCKS_3</name>
<description>3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLOCKS_4</name>
<description>4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CLOCKS_5</name>
<description>5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>CLOCKS_6</name>
<description>6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>CLOCKS_7</name>
<description>7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>CLOCKS_8</name>
<description>8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>CLOCKS_9</name>
<description>9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSTSCLHIGH</name>
<description>Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH.</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>CLOCKS_2</name>
<description>2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLOCKS_3</name>
<description>3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLOCKS_4</name>
<description>4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CLOCKS_5</name>
<description>5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>CLOCKS_6</name>
<description>6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>CLOCKS_7</name>
<description>7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>CLOCKS_8</name>
<description>8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>CLOCKS_9</name>
<description>9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MSTDAT</name>
<description>Combined Master receiver and transmitter data register.</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SLVCTL</name>
<description>Slave control register.</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>SLVCONTINUE</name>
<description>Slave Continue.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_EFFECT</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Continue</name>
<description>Informs the Slave function to continue to the next operation.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLVNACK</name>
<description>Slave NACK.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_EFFECT</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NACK</name>
<description>NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SLVDAT</name>
<description>Combined Slave receiver and transmitter data register.</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x4</dimIncrement>
<name>SLVADR[%s]</name>
<description>Slave address register.</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SADISABLE</name>
<description>Slave Address n Disable.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. Slave Address n is enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Ignored Slave Address n is ignored.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLVADR</name>
<description>Slave Address. Seven bit slave address that is compared to received addresses if enabled.</description>
<bitOffset>1</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SLVQUAL0</name>
<description>Slave Qualification for address 0.</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>QUALMODE0</name>
<description>Qualify mode for slave address 0.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>MASK</name>
<description>Mask. The SLVQUAL0 field is used as a logical mask for matching address 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EXTEND</name>
<description>Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLVQUAL0</name>
<description>Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] &lt;= received address &lt;= SLVQUAL0[7:1]).</description>
<bitOffset>1</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MONRXDAT</name>
<description>Monitor receiver data register.</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x7FF</resetMask>
<fields>
<field>
<name>MONRXDAT</name>
<description>Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>MONSTART</name>
<description>Monitor Received Start.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_START_DETECTED</name>
<description>No start detected. The Monitor function has not detected a Start event on the I2C bus.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>START_DETECTED</name>
<description>Start detected. The Monitor function has detected a Start event on the I2C bus.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MONRESTART</name>
<description>Monitor Received Repeated Start.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_DETECTED</name>
<description>No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DETECTED</name>
<description>Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MONNACK</name>
<description>Monitor Received NACK.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>ACKNOWLEDGED</name>
<description>Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NOT_ACKNOWLEDGED</name>
<description>Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="I2C0">
<name>I2C1</name>
<description>LPC80X I2C-bus interfaces</description>
<groupName>I2C</groupName>
<baseAddress>0x40054000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x84</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>I2C1</name>
<value>7</value>
</interrupt>
</peripheral>
<peripheral>
<name>SPI0</name>
<description>LPC80X Serial Peripheral Interfaces (SPI)</description>
<groupName>SPI</groupName>
<baseAddress>0x40058000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x2C</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>SPI0</name>
<value>0</value>
</interrupt>
<registers>
<register>
<name>CFG</name>
<description>SPI Configuration register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x3BD</resetMask>
<fields>
<field>
<name>ENABLE</name>
<description>SPI enable.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The SPI is disabled and the internal state machine and counters are reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The SPI is enabled for operation.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MASTER</name>
<description>Master mode select.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>SLAVE_MODE</name>
<description>Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MASTER_MODE</name>
<description>Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LSBF</name>
<description>LSB First mode enable.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>STANDARD</name>
<description>Standard. Data is transmitted and received in standard MSB first order.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>REVERSE</name>
<description>Reverse. Data is transmitted and received in reverse order (LSB first).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPHA</name>
<description>Clock Phase select.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>CHANGE</name>
<description>Change. The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CAPTURE</name>
<description>Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPOL</name>
<description>Clock Polarity select.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>Low. The rest state of the clock (between transfers) is low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>High. The rest state of the clock (between transfers) is high.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOOP</name>
<description>Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPOL0</name>
<description>SSEL0 Polarity select.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>Low. The SSEL0 pin is active low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>High. The SSEL0 pin is active high.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPOL1</name>
<description>SSEL1 Polarity select.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>Low. The SSEL1 pin is active low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>High. The SSEL1 pin is active high.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DLY</name>
<description>SPI Delay register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>PRE_DELAY</name>
<description>Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted.</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>POST_DELAY</name>
<description>Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted.</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FRAME_DELAY</name>
<description>If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted.</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TRANSFER_DELAY</name>
<description>Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times.</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>STAT</name>
<description>SPI Status. Some status flags can be cleared by writing a 1 to that bit position</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x102</resetValue>
<resetMask>0x1FF</resetMask>
<fields>
<field>
<name>RXRDY</name>
<description>Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TXRDY</name>
<description>Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT or TXDATCTL until the data is moved to the transmit shift register.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RXOV</name>
<description>Receiver Overrun interrupt flag. This flag applies only to slave mode (Master = 0). This flag is set when the beginning of a received character is detected while the receiver buffer is still in use. If this occurs, the receiver buffer contents are preserved, and the incoming data is lost. Data received by the SPI should be considered undefined if RxOv is set.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>TXUR</name>
<description>Transmitter Underrun interrupt flag. This flag applies only to slave mode (Master = 0). In this case, the transmitter must begin sending new data on the next input clock if the transmitter is idle. If that data is not available in the transmitter holding register at that point, there is no data to transmit and the TXUR flag is set. Data transmitted by the SPI should be considered undefined if TXUR is set.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SSA</name>
<description>Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SSD</name>
<description>Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>STALLED</name>
<description>Stalled status flag. This indicates whether the SPI is currently in a stall condition.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ENDTRANSFER</name>
<description>End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MSTIDLE</name>
<description>Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>INTENSET</name>
<description>SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>RXRDYEN</name>
<description>Determines whether an interrupt occurs when receiver data is available.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>RXRDYEN_0</name>
<description>No interrupt will be generated when receiver data is available.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RXRDYEN_1</name>
<description>An interrupt will be generated when receiver data is available in the RXDAT register.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXRDYEN</name>
<description>Determines whether an interrupt occurs when the transmitter holding register is available.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>TXRDYEN_0</name>
<description>No interrupt will be generated when the transmitter holding register is available.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>TXRDYEN_1</name>
<description>An interrupt will be generated when data may be written to TXDAT.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXOVEN</name>
<description>Determines whether an interrupt occurs when a receiver overrun occurs. This happens in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use. The interface prevents receiver overrun in Master mode by not allowing a new transmission to begin when a receiver overrun would otherwise occur.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>RXOVEN_0</name>
<description>No interrupt will be generated when a receiver overrun occurs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RXOVEN_1</name>
<description>An interrupt will be generated if a receiver overrun occurs.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXUREN</name>
<description>Determines whether an interrupt occurs when a transmitter underrun occurs. This happens in slave mode when there is a need to transmit data when none is available.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>TXUREN_0</name>
<description>No interrupt will be generated when the transmitter underruns.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>TXUREN_1</name>
<description>An interrupt will be generated if the transmitter underruns.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SSAEN</name>
<description>Determines whether an interrupt occurs when the Slave Select is asserted.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>SSAEN_0</name>
<description>No interrupt will be generated when any Slave Select transitions from deasserted to asserted.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SSAEN_1</name>
<description>An interrupt will be generated when any Slave Select transitions from deasserted to asserted.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SSDEN</name>
<description>Determines whether an interrupt occurs when the Slave Select is deasserted.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>SSDEN_0</name>
<description>No interrupt will be generated when all asserted Slave Selects transition to deasserted.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SSDEN_1</name>
<description>An interrupt will be generated when all asserted Slave Selects transition to deasserted.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSTIDLEEN</name>
<description>Determines whether an interrupt occurs when the MSTIDLE enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>MSTIDLEEN_0</name>
<description>No interrupt will be generated when MSTIDLE enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MSTIDLEEN_1</name>
<description>An interrupt will be generated when MSTIDLE enabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>INTENCLR</name>
<description>SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared.</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>RXRDYEN</name>
<description>Writing 1 clears the corresponding bits in the INTENSET register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>TXRDYEN</name>
<description>Writing 1 clears the corresponding bits in the INTENSET register.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>RXOVEN</name>
<description>Writing 1 clears the corresponding bits in the INTENSET register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>TXUREN</name>
<description>Writing 1 clears the corresponding bits in the INTENSET register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SSAEN</name>
<description>Writing 1 clears the corresponding bits in the INTENSET register.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SSDEN</name>
<description>Writing 1 clears the corresponding bits in the INTENSET register.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>MSTIDLE</name>
<description>Writing 1 clears the corresponding bits in the INTENSET register.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>RXDAT</name>
<description>SPI Receive Data</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>RXDAT</name>
<description>Receiver Data. This contains the next piece of received data. The number of bits that are used depends on the LEN setting in TXCTL / TXDATCTL.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RXSSEL0_N</name>
<description>Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RXSSEL1_N</name>
<description>Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RXSSEL2_N</name>
<description>Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RXSSEL3_N</name>
<description>Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SOT</name>
<description>Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the transfer length is greater than 16 bit.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>TXDATCTL</name>
<description>SPI Transmit Data with Control</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xF73FFFF</resetMask>
<fields>
<field>
<name>TXDAT</name>
<description>Transmit Data. This field provides from 1 to 16 bits of data to be transmitted.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXSSEL0_N</name>
<description>Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL0 pin is configured by bits in the CFG register.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>TXSSEL0_N_0</name>
<description>SSEL0 asserted.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>TXSSEL0_N_1</name>
<description>SSEL0 not asserted.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXSSEL1_N</name>
<description>Transmit Slave Select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL1 pin is configured by bits in the CFG register.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>TXSSEL1_N_0</name>
<description>SSEL1 asserted.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>TXSSEL1_N_1</name>
<description>SSEL1 not asserted.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EOT</name>
<description>End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain so for at least the time specified by the Transfer_delay value in the DLY register.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>SSEL_deasserted</name>
<description>This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SSEL_not_deasserted</name>
<description>This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EOF</name>
<description>End of Frame. Between frames, a delay may be inserted, as defined by the FRAME_DELAY value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for frame lengths greater than 16 bits.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Data_not_EOF</name>
<description>This piece of data transmitted is not treated as the end of a frame.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Data_EOF</name>
<description>This piece of data is treated as the end of a frame, causing the FRAME_DELAY time to be inserted before subsequent data is transmitted.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXIGNORE</name>
<description>Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver.Setting this bit simplifies the transmit process and can be used with the DMA.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Read_received_data</name>
<description>Received data must be read in order to allow transmission to progress. In slave mode, an overrun error will occur if received data is not read before new data is received.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Ignore_received_data</name>
<description>Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LEN</name>
<description>Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data transfer is 1 bit in length. 0x1 = Data transfer is 2 bits in length. 0x2 = Data transfer is 3 bits in length. ... 0xF = Data transfer is 16 bits in length.</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>LEN_0</name>
<description>no description available</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LEN_1</name>
<description>Data transfer is 1 bit in length.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>LEN_2</name>
<description>Data transfer is 2 bit in length.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>LEN_3</name>
<description>Data transfer is 3 bit in length.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>LEN_4</name>
<description>Data transfer is 4 bit in length.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>LEN_5</name>
<description>Data transfer is 5 bit in length.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>LEN_6</name>
<description>Data transfer is 6 bit in length.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>LEN_7</name>
<description>Data transfer is 7 bit in length.</description>
<value>0x7</value>
</enumeratedValue>
<enumeratedValue>
<name>LEN_8</name>
<description>Data transfer is 8 bit in length.</description>
<value>0x8</value>
</enumeratedValue>
<enumeratedValue>
<name>LEN_9</name>
<description>Data transfer is 9 bit in length.</description>
<value>0x9</value>
</enumeratedValue>
<enumeratedValue>
<name>LEN_10</name>
<description>Data transfer is 10 bit in length.</description>
<value>0xA</value>
</enumeratedValue>
<enumeratedValue>
<name>LEN_11</name>
<description>Data transfer is 11 bit in length.</description>
<value>0xB</value>
</enumeratedValue>
<enumeratedValue>
<name>LEN_12</name>
<description>Data transfer is 12 bit in length.</description>
<value>0xC</value>
</enumeratedValue>
<enumeratedValue>
<name>LEN_13</name>
<description>Data transfer is 13 bit in length.</description>
<value>0xD</value>
</enumeratedValue>
<enumeratedValue>
<name>LEN_14</name>
<description>Data transfer is 14 bit in length.</description>
<value>0xE</value>
</enumeratedValue>
<enumeratedValue>
<name>LEN_15</name>
<description>Data transfer is 15 bit in length.</description>
<value>0xF</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TXDAT</name>
<description>SPI Transmit Data.</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Transmit Data. This field provides from 4 to 16 bits of data to be transmitted.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TXCTL</name>
<description>SPI Transmit Control</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xF730000</resetMask>
<fields>
<field>
<name>TXSSEL0_N</name>
<description>Transmit Slave Select 0.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXSSEL1_N</name>
<description>Transmit Slave Select 1.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EOT</name>
<description>End of Transfer.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EOF</name>
<description>End of Frame.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RXIGNORE</name>
<description>Receive Ignore.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LEN</name>
<description>Data transfer Length.</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DIV</name>
<description>SPI clock Divider</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>DIVVAL</name>
<description>Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTSTAT</name>
<description>SPI Interrupt Status</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x2</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>RXRDY</name>
<description>Receiver Ready flag.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TXRDY</name>
<description>Transmitter Ready flag.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RXOV</name>
<description>Receiver Overrun interrupt flag.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TXUR</name>
<description>Transmitter Underrun interrupt flag.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SSA</name>
<description>Slave Select Assert.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SSD</name>
<description>Slave Select Deassert.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>MSTIDLE</name>
<description>Master Idle status flag.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CAPT</name>
<description>LPC84x Capacitive Touch</description>
<groupName>CAPT</groupName>
<baseAddress>0x40060000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>CMP_CAPT</name>
<value>11</value>
</interrupt>
<registers>
<register>
<name>CTRL</name>
<description>Configuration and control to setup the functional clock, the rules, and the pin selections and rules.</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFBF3F</resetMask>
<fields>
<field>
<name>POLLMODE</name>
<description>Mode of operation. May only change from 0 to another value. So, if 2 or 3, must be changed to 0 1st. Any attempt to go from non-0 to non-0 will result in 0 anyway.</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NONE</name>
<description>None, inactive. Poll and time counters are turned off. Writing this will reset state and stop any collection in progress. Note: this has no effect on STATUS - those must be cleared manually.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>POLL_NOW</name>
<description>Poll now - forces a manual poll to be started immediately, using XPINSEL X pin(s) to activate in the integration loop (all pins set together). Self clears - clear is not indication it is done (see STATUS).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>NORMAL</name>
<description>Normal polling using poll delay from POLL_TCNT register. This will start with the poll delay (which can be 0).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_POWER_MODE</name>
<description>The CAPT block will operate in low-power mode. This means it will use GPIO as input, use combination touch measurements, and assume it is to wake the system. This will use the POLL_TCNT poll delay, and start with the delay.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TYPE</name>
<description>Selects type of Touch arrangement to use and so how to handle XPINSEL bits</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>TYPE_0</name>
<description>Normal - all X elements are treated as normal, such as buttons and sliders.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>TYPE_1</name>
<description>3x3 grid using NXP Complementary measurements. The 1st 9 Xs are assumed to be the 3x3 grid. After that would be normal X elements. This will also allow 3x1 and 3x2 Note: Only possible if XMAX in STATUS is &gt;=8</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>TYPE_2</name>
<description>5 Sensors interleaved to act as 3x3 touch area using NXP Complementary measurements. 1st 5 Xs used for this, all remaining are treated as normal. Note that if 16 X pins allowed, the 16th will not be usable when TYPE=1. (use TYPE=0 and select 1 smaller than 15 ( and any others from 1 smaller than 5 on up in XPINSEL).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TYPE_3</name>
<description>9 Sensors interleaved to act as 5x5 touch area using NXP Complementary measurements. 1st 9 Xs used for this, all remaining are treated as normal. Note: Only possible if XMAX in STATUS is &gt;=8</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRIGGER</name>
<description>This selects what is being used as the trigger</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>USES_YH_GPIO</name>
<description>Uses YH GPIO. This is not normally used except in Low-power mode. But, it can be used with POLLNOW to baseline that measurement.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACMP</name>
<description>ACMP (if fitted). This assumes the ACMP state is fed in asynchronously and it will sample.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WAIT</name>
<description>If 0, the block will continue its X based measurements, even if the TOUCH register has not been read (and so could OVERRUN). If 1, it will wait until read when a touch (TOUCH's ISTOUCH bit is set) before starting the next. This should not normally be needed.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FDIV</name>
<description>Functional clock divider, or 0 if no divide. The term &quot;clocks&quot; in this spec then refer to divided clocks. For a 12MHz input (e.g. FRO 12MHz), this would normally be set to generate a 4MHz output (so, 2). For a 1MHz input, it should be 0. Note for internal use: this does not produce a 50/50 duty cycle when non even divide.</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>FDIV_0</name>
<description>No divide</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FDIV_1</name>
<description>/2</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>FDIV_2</name>
<description>/3</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>FDIV_3</name>
<description>/4</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>FDIV_4</name>
<description>/5</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>FDIV_5</name>
<description>/6</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>FDIV_7</name>
<description>/(FDIV+1)</description>
<value>0x7</value>
</enumeratedValue>
<enumeratedValue>
<name>FDIV_8</name>
<description>/(FDIV+1)</description>
<value>0x8</value>
</enumeratedValue>
<enumeratedValue>
<name>FDIV_9</name>
<description>/(FDIV+1)</description>
<value>0x9</value>
</enumeratedValue>
<enumeratedValue>
<name>FDIV_10</name>
<description>/(FDIV+1)</description>
<value>0xA</value>
</enumeratedValue>
<enumeratedValue>
<name>FDIV_11</name>
<description>/(FDIV+1)</description>
<value>0xB</value>
</enumeratedValue>
<enumeratedValue>
<name>FDIV_12</name>
<description>/(FDIV+1)</description>
<value>0xC</value>
</enumeratedValue>
<enumeratedValue>
<name>FDIV_13</name>
<description>/(FDIV+1)</description>
<value>0xD</value>
</enumeratedValue>
<enumeratedValue>
<name>FDIV_14</name>
<description>/(FDIV+1)</description>
<value>0xE</value>
</enumeratedValue>
<enumeratedValue>
<name>FDIV_15</name>
<description>/(FDIV+1)</description>
<value>0xF</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>XPINUSE</name>
<description>Controls how X pins selected in XPINSEL are used when not active in the current polling round.</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NORMAL_MDOE</name>
<description>Normal mode. Each inactive X pin is Hi-Z.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>GROUND_MDOE</name>
<description>Ground mode. Each inactive X pin is Low</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INCHANGE</name>
<description>If 1, do not attempt to write to this register again. This means the last change has not been propagated. This can only happen after changing POLLMODE and DMA. Worse case time would be based on divided FCLK.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>XPINSEL</name>
<description>Selects which of the X pins are to be used within the allowed pins - see XMAX in STATUS. The X pins are mapped via the IOCON (as are the YH and YL pins) to physical pads. So, this only selects which are to be used as the X half of the touch element. Note: when polling, these are &quot;walked&quot; (active) one at a time. When using POLLNOW, the 1 or more selected are used at the same time. Likewise, when in low-power mode, they are used at the same time (or small groups). X pads not selected by XPINSEL are kept at High-Z if they are connected to a pad. This allows using controlled sets for touch detection based on context.</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<description>Status from triggers and time-outs including if in a poll now. Some are used for interrupts.</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x80000</resetValue>
<resetMask>0xF011F</resetMask>
<fields>
<field>
<name>YESTOUCH</name>
<description>Is 1 if a touch has been detected, including a wakeup from low-power mode.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
</field>
<field>
<name>NOTOUCH</name>
<description>Is 1 if a no-touch has been detected (ie. completed an integration cycle and found no-touch). This is not set when in low-power mode.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
</field>
<field>
<name>POLLDONE</name>
<description>Is 1 if a poll or POLLNOW is complete.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
</field>
<field>
<name>TIMEOUT</name>
<description>Is 1 if an integration cycle ended with a timeout (should not happen).</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
</field>
<field>
<name>OVERUN</name>
<description>Is 1 if new data was collected before application read out previous ISTOUCH. No-touch (ISTOUCH==0) data will be silently overrun. Is not possible if WAIT=1.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
</field>
<field>
<name>BUSY</name>
<description>In a poll now.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>XMAX</name>
<description>Indicates the maximum number of X pins allowed 0-relative. So, 15 means there are pins 0 to 15, or 16 total X pins. INTERNAL note: this may be setup to be written by ROM boot.</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>POLL_TCNT</name>
<description>This sets up the polling counter and measurement counter rules.</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x8FFFFFFF</resetMask>
<fields>
<field>
<name>TCNT</name>
<description>Sets the threshold between touch and no-touch count. If not used, then the block will treat all events as touch or no-touch, depending whether at max or min. This is in terms of divided FCLK. If the comparator triggers it is no-touch; if bigger than TCNT counts, it is a touch event.</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TOUT</name>
<description>Time-out count expressed as 1 is smaller than TOUT, allowing for up to 12 bits. Must be less than 13. So, for example, 1 is smaller than 12=4096 counts; if TOUT=12, then if 4096 counts occur without a trigger, it is a time-out. This should be set to be large enough above TCNT to prevent timeout invalidly.</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>POLL</name>
<description>Poll counter in (internal) 12-bit counter wraparounds (loosely 1msec), so related to divided FCLK. This expresses time delay between measurement cycles (ie. after one set of X measurements, time before starting next). This count is used to delay before the next set of measurements. Measuring too often wastes power and does not add value since movement of fingers is relatively slow. For low power mode, this must allow for the clock being used (e.g. a 1MHz osc) so 12 bit count will be potentially much longer. That means, lowering the count to get the reasonable delay period.</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MDELAY</name>
<description>If not 0, this selects the number of divided FCLKs to wait after entry of measurement mode before deciding if has triggered. This gives the ACMP time to react to the transferred charge. It is used as 1+(1 smaller than MDELAY), , so between 2 and 8 ticks of the divided FCLK added during the measurement.</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RDELAY</name>
<description>If not 0, this is the number of divided FCLKs to hold in Step 0 'Reset' state (draining capacitance). It is used as (1 is smaller than RDELAY), so between 2 and 8 ticks of the divided FCLK added to the 'Reset' state.</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCHLOW_ER</name>
<description>Specifies whether a touched sensor triggers at a lower or higher count than an untouched sensor. TOUCHLOWER = 0: Trigger at count &gt; TCNT is a touch. Trigger at count lower than or equal to TCNT is a no-touch. TOUCHLOWER = 1: Trigger at count lower than or equal to TCNT is a touch. Trigger at count &gt; TCNT is a no-touch.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTENSET</name>
<description>Interrupt enable</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1F</resetMask>
<fields>
<field>
<name>YESTOUCH</name>
<description>Is 1 if a touch detected should interrupt. This includes wake from low-power mode.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
</field>
<field>
<name>NOTOUCH</name>
<description>Is 1 if a no-touch detected should interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
</field>
<field>
<name>POLLDONE</name>
<description>Is 1 if a poll or POLLNOW completing should interrupt</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
</field>
<field>
<name>TIMEOUT</name>
<description>Is 1 if an integration cycle ending with timeout should interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
</field>
<field>
<name>OVERUN</name>
<description>Is 1 if an overrun should interrupt.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
</field>
</fields>
</register>
<register>
<name>INTENCLR</name>
<description>Interrupt enable clear</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1F</resetMask>
<fields>
<field>
<name>YESTOUCH</name>
<description>clear the touch interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
</field>
<field>
<name>NOTOUCH</name>
<description>clear the no-touch interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
</field>
<field>
<name>POLLDONE</name>
<description>clear the poll or POLLNOW completing interrupt</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
</field>
<field>
<name>TIMEOUT</name>
<description>clear the timeout interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
</field>
<field>
<name>OVERUN</name>
<description>clear the overrun interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
</field>
</fields>
</register>
<register>
<name>INTSTAT</name>
<description>Interrupt status (mask of STATUS and INTEN)</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1F</resetMask>
<fields>
<field>
<name>YESTOUCH</name>
<description>the status of touch interrrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NOTOUCH</name>
<description>the status of no-touch interrrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>POLLDONE</name>
<description>the status of poll or pollnow completing interrupt</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TIMEOUT</name>
<description>the status of timeout interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>OVERUN</name>
<description>the status of overrun interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>TOUCH</name>
<description>Last touch event (touch or no-touch) in context.</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x80F3FFFF</resetMask>
<fields>
<field>
<name>COUNT</name>
<description>Count value reached at trigger. If timeout, will be (1 bigger than TOUT)-1; e.g. if TOUT=12, then 0xFFF.</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
<access>read-only</access>
</field>
<field>
<name>XVAL</name>
<description>Is the X that triggered this, or lowest X if more than one.</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ISTOUCH</name>
<description>1 if is Touch (by count) or 0 if is no-touch.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ISTO</name>
<description>1 if is Timeout.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SEQ</name>
<description>Sequence number - rolling counter of polls. Changes after all selected Xs per poll (so, 0 for 1st set of Xs, then 1 for next set, etc).</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CHANGE</name>
<description>If 1, the rest of the register is 0 because the data is changing. This will only happen for 1 cycle and would never happen if using interrupts to read, unless took so long as to overrun.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>ID</name>
<description>Block ID.</description>
<addressOffset>0xFFC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0xE1000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>APERTURE</name>
<description>Aperture: encoded as (aperture size/4K) -1, so 0x00 is a 4 K aperture.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>MINOR_REV</name>
<description>Minor revision of module implementation, starting at 0. Software compatibility is expected between minor revisions.</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>MAJOR_REV</name>
<description>Major revision of module implementation, starting at 0. There may not be software compatibility between major revisions.</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ID</name>
<description>Unique module identifier for this IP block.</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>USART0</name>
<description>LPC80X USARTs</description>
<groupName>USART</groupName>
<headerStructName>USART</headerStructName>
<baseAddress>0x40064000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x30</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>USART0</name>
<value>3</value>
</interrupt>
<registers>
<register>
<name>CFG</name>
<description>USART Configuration register. Basic USART configuration settings that typically are not changed during operation.</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFCDA7D</resetMask>
<fields>
<field>
<name>ENABLE</name>
<description>USART Enable.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The USART is enabled for operation.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DATALEN</name>
<description>Selects the data size for the USART.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>BIT_7</name>
<description>7 bit Data length.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>BIT_8</name>
<description>8 bit Data length.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>BIT_9</name>
<description>9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register.</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PARITYSEL</name>
<description>Selects what type of parity is used by the USART.</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_PARITY</name>
<description>No parity.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EVEN_PARITY</name>
<description>Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>ODD_PARITY</name>
<description>Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STOPLEN</name>
<description>Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>BIT_1</name>
<description>1 stop bit.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>BITS_2</name>
<description>2 stop bits. This setting should only be used for asynchronous communication.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CTSEN</name>
<description>CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>No flow control. The transmitter does not receive any automatic flow control signal.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYNCEN</name>
<description>Selects synchronous or asynchronous operation.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ASYNCHRONOUS_MODE</name>
<description>Asynchronous mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SYNCHRONOUS_MODE</name>
<description>Synchronous mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKPOL</name>
<description>Selects the clock polarity and sampling edge of received data in synchronous mode.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>FALLING_EDGE</name>
<description>Falling edge. Un_RXD is sampled on the falling edge of SCLK.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RISING_EDGE</name>
<description>Rising edge. Un_RXD is sampled on the rising edge of SCLK.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYNCMST</name>
<description>Synchronous mode Master select.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>SLAVE</name>
<description>Slave. When synchronous mode is enabled, the USART is a slave.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MASTER</name>
<description>Master. When synchronous mode is enabled, the USART is a master.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOOP</name>
<description>Selects data loopback mode.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NORMAL</name>
<description>Normal operation.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOOPBACK</name>
<description>Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OETA</name>
<description>Output Enable Turnaround time enable for RS-485 operation.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AUTOADDR</name>
<description>Automatic Address matching enable.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OESEL</name>
<description>Output Enable Select.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>STANDARD</name>
<description>Standard. The RTS signal is used as the standard flow control function.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RS_485</name>
<description>RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OEPOL</name>
<description>Output Enable Polarity.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>Low. If selected by OESEL, the output enable is active low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>High. If selected by OESEL, the output enable is active high.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXPOL</name>
<description>Receive data polarity.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>STANDARD</name>
<description>Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERTED</name>
<description>Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXPOL</name>
<description>Transmit data polarity.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>STANDARD</name>
<description>Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERTED</name>
<description>Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CTL</name>
<description>USART Control register. USART control settings that are more likely to change during operation.</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x10346</resetMask>
<fields>
<field>
<name>TXBRKEN</name>
<description>Break Enable.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NORMAL</name>
<description>Normal operation.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CONTINOUS</name>
<description>Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADDRDET</name>
<description>Enable address detect mode.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. The USART presents all incoming data.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXDIS</name>
<description>Transmit Disable.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Not disabled. USART transmitter is not disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CC</name>
<description>Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>CLOCK_ON_CHARACTER</name>
<description>Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CONTINOUS_CLOCK</name>
<description>Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLRCCONRX</name>
<description>Clear Continuous Clock.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_EFFECT</name>
<description>No effect. No effect on the CC bit.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>AUTO_CLEAR</name>
<description>Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AUTOBAUD</name>
<description>Autobaud enable.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. USART is in normal operating mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>STAT</name>
<description>USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xE</resetValue>
<resetMask>0x1FD7F</resetMask>
<fields>
<field>
<name>RXRDY</name>
<description>Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RXIDLE</name>
<description>Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TXRDY</name>
<description>Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TXIDLE</name>
<description>Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CTS</name>
<description>This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DELTACTS</name>
<description>This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>TXDISSTAT</name>
<description>Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CTL register (TXDIS = 1).</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>OVERRUNINT</name>
<description>Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>RXBRK</name>
<description>Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DELTARXBRK</name>
<description>This bit is set when a change in the state of receiver break detection occurs.Cleared by software.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>START</name>
<description>This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>FRAMERRINT</name>
<description>Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>PARITYERRINT</name>
<description>Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>RXNOISEINT</name>
<description>Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>ABERR</name>
<description>Autobaud Error. An autobaud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an autobaud time-out.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>INTENSET</name>
<description>Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1F96D</resetMask>
<fields>
<field>
<name>RXRDYEN</name>
<description>When 1, enables an interrupt when there is a received character available to be read from the RXDAT register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXRDYEN</name>
<description>When 1, enables an interrupt when the TXDAT register is available to take another character to transmit.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXIDLEEN</name>
<description>When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1).</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DELTACTSEN</name>
<description>When 1, enables an interrupt when there is a change in the state of the CTS input.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXDISEN</name>
<description>When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>OVERRUNEN</name>
<description>When 1, enables an interrupt when an overrun error occurred.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DELTARXBRKEN</name>
<description>When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted).</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>STARTEN</name>
<description>When 1, enables an interrupt when a received start bit has been detected.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FRAMERREN</name>
<description>When 1, enables an interrupt when a framing error has been detected.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PARITYERREN</name>
<description>When 1, enables an interrupt when a parity error has been detected.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RXNOISEEN</name>
<description>When 1, enables an interrupt when noise is detected.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ABERREN</name>
<description>When 1, enables an interrupt when an autobaud error occurs.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTENCLR</name>
<description>Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>RXRDYCLR</name>
<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>TXRDYCLR</name>
<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>TXIDLECLR</name>
<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>DELTACTSCLR</name>
<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>TXDISINTCLR</name>
<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>OVERRUNCLR</name>
<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>DELTARXBRKCLR</name>
<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>STARTCLR</name>
<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>FRAMERRCLR</name>
<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>PARITYERRCLR</name>
<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>RXNOISECLR</name>
<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>ABERRCLR</name>
<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>RXDAT</name>
<description>Receiver Data register. Contains the last character received.</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>RXDAT</name>
<description>The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings.</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RXDATSTAT</name>
<description>Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together.</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>RXDAT</name>
<description>The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings.</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
<access>read-only</access>
</field>
<field>
<name>FRAMERR</name>
<description>Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PARITYERR</name>
<description>Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RXNOISE</name>
<description>Received Noise flag.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>TXDAT</name>
<description>Transmit Data register. Data to be transmitted is written here.</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1FF</resetMask>
<fields>
<field>
<name>TXDAT</name>
<description>Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0.</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>BRG</name>
<description>Baud Rate Generator register. 16-bit integer baud rate divisor value.</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>BRGVAL</name>
<description>This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTSTAT</name>
<description>Interrupt status register. Reflects interrupts that are currently enabled.</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0x1F96D</resetMask>
<fields>
<field>
<name>RXRDY</name>
<description>Receiver Ready flag.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TXRDY</name>
<description>Transmitter Ready flag.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TXIDLE</name>
<description>Transmitter idle status.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DELTACTS</name>
<description>This bit is set when a change in the state of the CTS input is detected.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TXDISINT</name>
<description>Transmitter Disabled Interrupt flag.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>OVERRUNINT</name>
<description>Overrun Error interrupt flag.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DELTARXBRK</name>
<description>This bit is set when a change in the state of receiver break detection occurs.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>START</name>
<description>This bit is set when a start is detected on the receiver input.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>FRAMERRINT</name>
<description>Framing Error interrupt flag.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PARITYERRINT</name>
<description>Parity Error interrupt flag.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RXNOISEINT</name>
<description>Received Noise interrupt flag.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ABERR</name>
<description>Autobaud Error flag.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>OSR</name>
<description>Oversample selection register for asynchronous communication.</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xF</resetValue>
<resetMask>0xF</resetMask>
<fields>
<field>
<name>OSRVAL</name>
<description>Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit.</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ADDR</name>
<description>Address register for automatic address matching.</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ADDRESS</name>
<description>8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1).</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="USART0">
<name>USART1</name>
<description>LPC80X USARTs</description>
<groupName>USART</groupName>
<baseAddress>0x40068000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x30</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>USART1</name>
<value>4</value>
</interrupt>
</peripheral>
<peripheral>
<name>CRC</name>
<description>LPC80X CRC engine</description>
<groupName>CRC</groupName>
<baseAddress>0x50000000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xC</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>MODE</name>
<description>CRC mode register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>CRC_POLY</name>
<description>CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BIT_RVS_WR</name>
<description>Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CMPL_WR</name>
<description>Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BIT_RVS_SUM</name>
<description>CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CMPL_SUM</name>
<description>CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SEED</name>
<description>CRC seed register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CRC_SEED</name>
<description>A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1's complement pre-processes. A write access to this register will overrule the CRC calculation in progresses.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SUM</name>
<description>CRC checksum register</description>
<alternateGroup>SUM_WR_DATA</alternateGroup>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0xFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CRC_SUM</name>
<description>The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>WR_DATA</name>
<description>CRC data register</description>
<alternateGroup>SUM_WR_DATA</alternateGroup>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>CRC_WR_DATA</name>
<description>Data written to this register will be taken to perform CRC calculation with selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>GPIO</name>
<description>LPC80X General Purpose I/O (GPIO)</description>
<groupName>GPIO</groupName>
<baseAddress>0xA0000000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x2484</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>B0_0</name>
<description>Byte pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>PBYTE</name>
<description>Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>B0_1</name>
<description>Byte pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>PBYTE</name>
<description>Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>B0_2</name>
<description>Byte pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>PBYTE</name>
<description>Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>B0_3</name>
<description>Byte pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>PBYTE</name>
<description>Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>B0_4</name>
<description>Byte pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>PBYTE</name>
<description>Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>B0_5</name>
<description>Byte pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>PBYTE</name>
<description>Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>B0_6</name>
<description>Byte pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x6</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>PBYTE</name>
<description>Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>B0_7</name>
<description>Byte pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x7</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>PBYTE</name>
<description>Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>B0_8</name>
<description>Byte pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x8</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>PBYTE</name>
<description>Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>B0_9</name>
<description>Byte pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x9</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>PBYTE</name>
<description>Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>B0_10</name>
<description>Byte pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0xA</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>PBYTE</name>
<description>Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>B0_11</name>
<description>Byte pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0xB</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>PBYTE</name>
<description>Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>B0_12</name>
<description>Byte pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0xC</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>PBYTE</name>
<description>Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>B0_13</name>
<description>Byte pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0xD</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>PBYTE</name>
<description>Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>B0_14</name>
<description>Byte pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0xE</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>PBYTE</name>
<description>Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>B0_15</name>
<description>Byte pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0xF</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>PBYTE</name>
<description>Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>B0_16</name>
<description>Byte pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x10</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>PBYTE</name>
<description>Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>B0_17</name>
<description>Byte pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x11</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>PBYTE</name>
<description>Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>B0_18</name>
<description>Byte pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x12</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>PBYTE</name>
<description>Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>B0_19</name>
<description>Byte pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x13</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>PBYTE</name>
<description>Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>B0_20</name>
<description>Byte pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x14</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>PBYTE</name>
<description>Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>B0_21</name>
<description>Byte pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x15</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>PBYTE</name>
<description>Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>B0_22</name>
<description>Byte pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x16</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>PBYTE</name>
<description>Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>B0_23</name>
<description>Byte pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x17</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>PBYTE</name>
<description>Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>B0_24</name>
<description>Byte pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x18</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>PBYTE</name>
<description>Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>B0_25</name>
<description>Byte pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x19</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>PBYTE</name>
<description>Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>B0_26</name>
<description>Byte pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x1A</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>PBYTE</name>
<description>Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>B0_27</name>
<description>Byte pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x1B</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>PBYTE</name>
<description>Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>B0_28</name>
<description>Byte pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x1C</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>PBYTE</name>
<description>Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>B0_29</name>
<description>Byte pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x1D</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>PBYTE</name>
<description>Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>B0_30</name>
<description>Byte pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x1E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>PBYTE</name>
<description>Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>W0_0</name>
<description>Word pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x1000</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWORD</name>
<description>Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>W0_1</name>
<description>Word pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x1004</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWORD</name>
<description>Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>W0_2</name>
<description>Word pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x1008</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWORD</name>
<description>Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>W0_3</name>
<description>Word pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x100C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWORD</name>
<description>Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>W0_4</name>
<description>Word pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x1010</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWORD</name>
<description>Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>W0_5</name>
<description>Word pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x1014</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWORD</name>
<description>Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>W0_6</name>
<description>Word pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x1018</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWORD</name>
<description>Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>W0_7</name>
<description>Word pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x101C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWORD</name>
<description>Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>W0_8</name>
<description>Word pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x1020</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWORD</name>
<description>Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>W0_9</name>
<description>Word pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x1024</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWORD</name>
<description>Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>W0_10</name>
<description>Word pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x1028</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWORD</name>
<description>Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>W0_11</name>
<description>Word pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x102C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWORD</name>
<description>Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>W0_12</name>
<description>Word pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x1030</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWORD</name>
<description>Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>W0_13</name>
<description>Word pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x1034</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWORD</name>
<description>Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>W0_14</name>
<description>Word pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x1038</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWORD</name>
<description>Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>W0_15</name>
<description>Word pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x103C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWORD</name>
<description>Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>W0_16</name>
<description>Word pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x1040</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWORD</name>
<description>Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>W0_17</name>
<description>Word pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x1044</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWORD</name>
<description>Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>W0_18</name>
<description>Word pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x1048</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWORD</name>
<description>Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>W0_19</name>
<description>Word pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x104C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWORD</name>
<description>Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>W0_20</name>
<description>Word pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x1050</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWORD</name>
<description>Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>W0_21</name>
<description>Word pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x1054</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWORD</name>
<description>Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>W0_22</name>
<description>Word pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x1058</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWORD</name>
<description>Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>W0_23</name>
<description>Word pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x105C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWORD</name>
<description>Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>W0_24</name>
<description>Word pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x1060</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWORD</name>
<description>Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>W0_25</name>
<description>Word pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x1064</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWORD</name>
<description>Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>W0_26</name>
<description>Word pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x1068</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWORD</name>
<description>Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>W0_27</name>
<description>Word pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x106C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWORD</name>
<description>Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>W0_28</name>
<description>Word pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x1070</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWORD</name>
<description>Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>W0_29</name>
<description>Word pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x1074</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWORD</name>
<description>Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>W0_30</name>
<description>Word pin registers for all port 0 and 1 GPIO pins</description>
<addressOffset>0x1078</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWORD</name>
<description>Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DIR0</name>
<description>Direction registers</description>
<addressOffset>0x2000</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIRP</name>
<description>Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output.</description>
<bitOffset>0</bitOffset>
<bitWidth>31</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MASK0</name>
<description>Mask register</description>
<addressOffset>0x2080</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MASKP</name>
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitOffset>0</bitOffset>
<bitWidth>31</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PIN0</name>
<description>Port pin register</description>
<addressOffset>0x2100</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PORT</name>
<description>Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitOffset>0</bitOffset>
<bitWidth>31</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MPIN0</name>
<description>Masked port register</description>
<addressOffset>0x2180</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MPORTP</name>
<description>Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitOffset>0</bitOffset>
<bitWidth>31</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SET0</name>
<description>Write: Set register for port Read: output bits for port</description>
<addressOffset>0x2200</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SETP</name>
<description>Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitOffset>0</bitOffset>
<bitWidth>31</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLR0</name>
<description>Clear port</description>
<addressOffset>0x2280</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>CLRP</name>
<description>Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit.</description>
<bitOffset>0</bitOffset>
<bitWidth>31</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>NOT0</name>
<description>Toggle port</description>
<addressOffset>0x2300</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>NOTP</name>
<description>Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit.</description>
<bitOffset>0</bitOffset>
<bitWidth>31</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>DIRSET0</name>
<description>Set pin direction bits for port</description>
<addressOffset>0x2380</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>DIRSETP</name>
<description>Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Set direction bit.</description>
<bitOffset>0</bitOffset>
<bitWidth>31</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>DIRCLR0</name>
<description>Clear pin direction bits for port</description>
<addressOffset>0x2400</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>DIRCLRP</name>
<description>Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit.</description>
<bitOffset>0</bitOffset>
<bitWidth>31</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>DIRNOT0</name>
<description>Toggle pin direction bits for port</description>
<addressOffset>0x2480</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>DIRNOTP</name>
<description>Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle direction bit.</description>
<bitOffset>0</bitOffset>
<bitWidth>31</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PINT</name>
<description>LPC80X Pin interrupt and pattern match (PINT)</description>
<groupName>PINT</groupName>
<baseAddress>0xA0004000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x34</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PIN_INT0</name>
<value>24</value>
</interrupt>
<interrupt>
<name>PIN_INT1</name>
<value>25</value>
</interrupt>
<interrupt>
<name>PIN_INT2</name>
<value>26</value>
</interrupt>
<interrupt>
<name>PIN_INT3</name>
<value>27</value>
</interrupt>
<interrupt>
<name>PIN_INT4</name>
<value>28</value>
</interrupt>
<interrupt>
<name>PIN_INT5</name>
<value>29</value>
</interrupt>
<interrupt>
<name>PIN_INT6</name>
<value>30</value>
</interrupt>
<interrupt>
<name>PIN_INT7</name>
<value>31</value>
</interrupt>
<registers>
<register>
<name>ISEL</name>
<description>Pin Interrupt Mode register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PMODE</name>
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>IENR</name>
<description>Pin interrupt level or rising edge interrupt enable register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ENRL</name>
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIENR</name>
<description>Pin interrupt level or rising edge interrupt set register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>SETENRL</name>
<description>Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>CIENR</name>
<description>Pin interrupt level (rising edge interrupt) clear register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>CENRL</name>
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>IENF</name>
<description>Pin interrupt active level or falling edge interrupt enable register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ENAF</name>
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIENF</name>
<description>Pin interrupt active level or falling edge interrupt set register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>SETENAF</name>
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>CIENF</name>
<description>Pin interrupt active level or falling edge interrupt clear register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>CENAF</name>
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>RISE</name>
<description>Pin interrupt rising edge register</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RDET</name>
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>FALL</name>
<description>Pin interrupt falling edge register</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>FDET</name>
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>IST</name>
<description>Pin interrupt status register</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PSTAT</name>
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register).</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PMCTRL</name>
<description>Pattern match interrupt control register</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF000003</resetMask>
<fields>
<field>
<name>SEL_PMATCH</name>
<description>Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>PIN_INTERRUPT</name>
<description>Pin interrupt. Interrupts are driven in response to the standard pin interrupt function.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PATTERN_MATCH</name>
<description>Pattern match. Interrupts are driven in response to pattern matches.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ENA_RXEV</name>
<description>Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. RXEV output to the CPU is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. RXEV output to the CPU is enabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PMAT</name>
<description>This field displays the current state of pattern matches. A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs.</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PMSRC</name>
<description>Pattern match interrupt bit-slice source register</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFF00</resetMask>
<fields>
<field>
<name>SRC0</name>
<description>Selects the input source for bit slice 0</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INPUT0</name>
<description>Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT1</name>
<description>Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT2</name>
<description>Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT3</name>
<description>Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT4</name>
<description>Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT5</name>
<description>Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT6</name>
<description>Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT7</name>
<description>Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRC1</name>
<description>Selects the input source for bit slice 1</description>
<bitOffset>11</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INPUT0</name>
<description>Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT1</name>
<description>Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT2</name>
<description>Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT3</name>
<description>Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT4</name>
<description>Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT5</name>
<description>Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT6</name>
<description>Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT7</name>
<description>Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRC2</name>
<description>Selects the input source for bit slice 2</description>
<bitOffset>14</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INPUT0</name>
<description>Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT1</name>
<description>Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT2</name>
<description>Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT3</name>
<description>Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT4</name>
<description>Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT5</name>
<description>Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT6</name>
<description>Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT7</name>
<description>Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRC3</name>
<description>Selects the input source for bit slice 3</description>
<bitOffset>17</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INPUT0</name>
<description>Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT1</name>
<description>Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT2</name>
<description>Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT3</name>
<description>Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT4</name>
<description>Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT5</name>
<description>Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT6</name>
<description>Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT7</name>
<description>Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRC4</name>
<description>Selects the input source for bit slice 4</description>
<bitOffset>20</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INPUT0</name>
<description>Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT1</name>
<description>Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT2</name>
<description>Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT3</name>
<description>Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT4</name>
<description>Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT5</name>
<description>Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT6</name>
<description>Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT7</name>
<description>Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRC5</name>
<description>Selects the input source for bit slice 5</description>
<bitOffset>23</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INPUT0</name>
<description>Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT1</name>
<description>Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT2</name>
<description>Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT3</name>
<description>Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT4</name>
<description>Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT5</name>
<description>Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT6</name>
<description>Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT7</name>
<description>Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRC6</name>
<description>Selects the input source for bit slice 6</description>
<bitOffset>26</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INPUT0</name>
<description>Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT1</name>
<description>Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT2</name>
<description>Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT3</name>
<description>Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT4</name>
<description>Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT5</name>
<description>Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT6</name>
<description>Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT7</name>
<description>Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRC7</name>
<description>Selects the input source for bit slice 7</description>
<bitOffset>29</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INPUT0</name>
<description>Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT1</name>
<description>Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT2</name>
<description>Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT3</name>
<description>Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT4</name>
<description>Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT5</name>
<description>Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT6</name>
<description>Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT7</name>
<description>Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PMCFG</name>
<description>Pattern match interrupt bit slice configuration register</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFF7F</resetMask>
<fields>
<field>
<name>PROD_ENDPTS0</name>
<description>Determines whether slice 0 is an endpoint.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_EFFECT</name>
<description>No effect. Slice 0 is not an endpoint.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENDPOINT</name>
<description>endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PROD_ENDPTS1</name>
<description>Determines whether slice 1 is an endpoint.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_EFFECT</name>
<description>No effect. Slice 1 is not an endpoint.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENDPOINT</name>
<description>endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PROD_ENDPTS2</name>
<description>Determines whether slice 2 is an endpoint.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_EFFECT</name>
<description>No effect. Slice 2 is not an endpoint.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENDPOINT</name>
<description>endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PROD_ENDPTS3</name>
<description>Determines whether slice 3 is an endpoint.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_EFFECT</name>
<description>No effect. Slice 3 is not an endpoint.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENDPOINT</name>
<description>endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PROD_ENDPTS4</name>
<description>Determines whether slice 4 is an endpoint.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_EFFECT</name>
<description>No effect. Slice 4 is not an endpoint.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENDPOINT</name>
<description>endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PROD_ENDPTS5</name>
<description>Determines whether slice 5 is an endpoint.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_EFFECT</name>
<description>No effect. Slice 5 is not an endpoint.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENDPOINT</name>
<description>endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PROD_ENDPTS6</name>
<description>Determines whether slice 6 is an endpoint.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_EFFECT</name>
<description>No effect. Slice 6 is not an endpoint.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENDPOINT</name>
<description>endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CFG0</name>
<description>Specifies the match contribution condition for bit slice 0.</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>CONSTANT_HIGH</name>
<description>Constant HIGH. This bit slice always contributes to a product term match.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_EDGE</name>
<description>Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_FALLING_EDGE</name>
<description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_FALLING_EDGE</name>
<description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_LEVEL</name>
<description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_LEVEL</name>
<description>Low level. Match occurs when there is a low level on the specified input.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>CONSTANT_ZERO</name>
<description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>EVENT</name>
<description>Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CFG1</name>
<description>Specifies the match contribution condition for bit slice 1.</description>
<bitOffset>11</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>CONSTANT_HIGH</name>
<description>Constant HIGH. This bit slice always contributes to a product term match.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_EDGE</name>
<description>Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_FALLING_EDGE</name>
<description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_FALLING_EDGE</name>
<description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_LEVEL</name>
<description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_LEVEL</name>
<description>Low level. Match occurs when there is a low level on the specified input.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>CONSTANT_ZERO</name>
<description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>EVENT</name>
<description>Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CFG2</name>
<description>Specifies the match contribution condition for bit slice 2.</description>
<bitOffset>14</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>CONSTANT_HIGH</name>
<description>Constant HIGH. This bit slice always contributes to a product term match.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_EDGE</name>
<description>Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_FALLING_EDGE</name>
<description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_FALLING_EDGE</name>
<description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_LEVEL</name>
<description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_LEVEL</name>
<description>Low level. Match occurs when there is a low level on the specified input.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>CONSTANT_ZERO</name>
<description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>EVENT</name>
<description>Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CFG3</name>
<description>Specifies the match contribution condition for bit slice 3.</description>
<bitOffset>17</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>CONSTANT_HIGH</name>
<description>Constant HIGH. This bit slice always contributes to a product term match.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_EDGE</name>
<description>Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_FALLING_EDGE</name>
<description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_FALLING_EDGE</name>
<description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_LEVEL</name>
<description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_LEVEL</name>
<description>Low level. Match occurs when there is a low level on the specified input.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>CONSTANT_ZERO</name>
<description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>EVENT</name>
<description>Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CFG4</name>
<description>Specifies the match contribution condition for bit slice 4.</description>
<bitOffset>20</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>CONSTANT_HIGH</name>
<description>Constant HIGH. This bit slice always contributes to a product term match.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_EDGE</name>
<description>Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_FALLING_EDGE</name>
<description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_FALLING_EDGE</name>
<description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_LEVEL</name>
<description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_LEVEL</name>
<description>Low level. Match occurs when there is a low level on the specified input.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>CONSTANT_ZERO</name>
<description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>EVENT</name>
<description>Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CFG5</name>
<description>Specifies the match contribution condition for bit slice 5.</description>
<bitOffset>23</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>CONSTANT_HIGH</name>
<description>Constant HIGH. This bit slice always contributes to a product term match.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_EDGE</name>
<description>Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_FALLING_EDGE</name>
<description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_FALLING_EDGE</name>
<description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_LEVEL</name>
<description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_LEVEL</name>
<description>Low level. Match occurs when there is a low level on the specified input.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>CONSTANT_ZERO</name>
<description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>EVENT</name>
<description>Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CFG6</name>
<description>Specifies the match contribution condition for bit slice 6.</description>
<bitOffset>26</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>CONSTANT_HIGH</name>
<description>Constant HIGH. This bit slice always contributes to a product term match.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_EDGE</name>
<description>Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_FALLING_EDGE</name>
<description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_FALLING_EDGE</name>
<description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_LEVEL</name>
<description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_LEVEL</name>
<description>Low level. Match occurs when there is a low level on the specified input.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>CONSTANT_ZERO</name>
<description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>EVENT</name>
<description>Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CFG7</name>
<description>Specifies the match contribution condition for bit slice 7.</description>
<bitOffset>29</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>CONSTANT_HIGH</name>
<description>Constant HIGH. This bit slice always contributes to a product term match.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_EDGE</name>
<description>Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_FALLING_EDGE</name>
<description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>STICKY_RISING_FALLING_EDGE</name>
<description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_LEVEL</name>
<description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_LEVEL</name>
<description>Low level. Match occurs when there is a low level on the specified input.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>CONSTANT_ZERO</name>
<description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>EVENT</name>
<description>Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
</peripherals>
</device>
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