258 lines
9.2 KiB
C
258 lines
9.2 KiB
C
/*
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** ###################################################################
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** Version: rev. 1.0, 2018-01-09
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** Build: b220714
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**
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** Abstract:
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** Chip specific module features.
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**
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** Copyright 2016 Freescale Semiconductor, Inc.
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** Copyright 2016-2022 NXP
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** All rights reserved.
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**
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** SPDX-License-Identifier: BSD-3-Clause
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**
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** http: www.nxp.com
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** mail: support@nxp.com
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**
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** Revisions:
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** - rev. 1.0 (2018-01-09)
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** Initial version.
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**
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** ###################################################################
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*/
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#ifndef _LPC804_FEATURES_H_
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#define _LPC804_FEATURES_H_
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/* SOC module features */
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#if defined(CPU_LPC804M101JDH20) || defined(CPU_LPC804UK)
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/* @brief ACOMP availability on the SoC. */
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#define FSL_FEATURE_SOC_ACOMP_COUNT (1)
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/* @brief ADC availability on the SoC. */
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#define FSL_FEATURE_SOC_ADC_COUNT (1)
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/* @brief CAPT availability on the SoC. */
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#define FSL_FEATURE_SOC_CAPT_COUNT (1)
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/* @brief CRC availability on the SoC. */
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#define FSL_FEATURE_SOC_CRC_COUNT (1)
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/* @brief CTIMER availability on the SoC. */
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#define FSL_FEATURE_SOC_CTIMER_COUNT (1)
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/* @brief GPIO availability on the SoC. */
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#define FSL_FEATURE_SOC_GPIO_COUNT (1)
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/* @brief I2C availability on the SoC. */
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#define FSL_FEATURE_SOC_I2C_COUNT (2)
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/* @brief IOCON availability on the SoC. */
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#define FSL_FEATURE_SOC_IOCON_COUNT (1)
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/* @brief MRT availability on the SoC. */
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#define FSL_FEATURE_SOC_MRT_COUNT (1)
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/* @brief PINT availability on the SoC. */
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#define FSL_FEATURE_SOC_PINT_COUNT (1)
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/* @brief PMU availability on the SoC. */
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#define FSL_FEATURE_SOC_PMU_COUNT (1)
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/* @brief SPI availability on the SoC. */
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#define FSL_FEATURE_SOC_SPI_COUNT (1)
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/* @brief SWM availability on the SoC. */
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#define FSL_FEATURE_SOC_SWM_COUNT (1)
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/* @brief SYSCON availability on the SoC. */
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#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
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/* @brief USART availability on the SoC. */
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#define FSL_FEATURE_SOC_USART_COUNT (2)
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/* @brief WWDT availability on the SoC. */
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#define FSL_FEATURE_SOC_WWDT_COUNT (1)
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#elif defined(CPU_LPC804M101JDH24) || defined(CPU_LPC804M101JHI33) || defined(CPU_LPC804M111JDH24)
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/* @brief ACOMP availability on the SoC. */
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#define FSL_FEATURE_SOC_ACOMP_COUNT (1)
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/* @brief ADC availability on the SoC. */
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#define FSL_FEATURE_SOC_ADC_COUNT (1)
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/* @brief CAPT availability on the SoC. */
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#define FSL_FEATURE_SOC_CAPT_COUNT (1)
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/* @brief CRC availability on the SoC. */
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#define FSL_FEATURE_SOC_CRC_COUNT (1)
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/* @brief CTIMER availability on the SoC. */
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#define FSL_FEATURE_SOC_CTIMER_COUNT (1)
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/* @brief DAC availability on the SoC. */
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#define FSL_FEATURE_SOC_DAC_COUNT (1)
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/* @brief GPIO availability on the SoC. */
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#define FSL_FEATURE_SOC_GPIO_COUNT (1)
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/* @brief I2C availability on the SoC. */
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#define FSL_FEATURE_SOC_I2C_COUNT (2)
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/* @brief IOCON availability on the SoC. */
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#define FSL_FEATURE_SOC_IOCON_COUNT (1)
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/* @brief MRT availability on the SoC. */
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#define FSL_FEATURE_SOC_MRT_COUNT (1)
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/* @brief PINT availability on the SoC. */
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#define FSL_FEATURE_SOC_PINT_COUNT (1)
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/* @brief PMU availability on the SoC. */
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#define FSL_FEATURE_SOC_PMU_COUNT (1)
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/* @brief SPI availability on the SoC. */
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#define FSL_FEATURE_SOC_SPI_COUNT (1)
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/* @brief SWM availability on the SoC. */
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#define FSL_FEATURE_SOC_SWM_COUNT (1)
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/* @brief SYSCON availability on the SoC. */
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#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
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/* @brief USART availability on the SoC. */
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#define FSL_FEATURE_SOC_USART_COUNT (2)
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/* @brief WWDT availability on the SoC. */
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#define FSL_FEATURE_SOC_WWDT_COUNT (1)
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#endif
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/* ACOMP module features */
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/* @brief Has INTENA bitfile in CTRL reigster. */
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#define FSL_FEATURE_ACOMP_HAS_CTRL_INTENA (1)
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/* ADC module features */
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/* @brief Do not has input select (register INSEL). */
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#define FSL_FEATURE_ADC_HAS_NO_INSEL (1)
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/* @brief Has ASYNMODE bitfile in CTRL reigster. */
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#define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (0)
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/* @brief Has ASYNMODE bitfile in CTRL reigster. */
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#define FSL_FEATURE_ADC_HAS_CTRL_RESOL (0)
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/* @brief Has ASYNMODE bitfile in CTRL reigster. */
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#define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (0)
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/* @brief Has ASYNMODE bitfile in CTRL reigster. */
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#define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (0)
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/* @brief Has ASYNMODE bitfile in CTRL reigster. */
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#define FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE (1)
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/* @brief Has ASYNMODE bitfile in CTRL reigster. */
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#define FSL_FEATURE_ADC_HAS_CTRL_CALMODE (0)
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/* @brief Has startup register. */
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#define FSL_FEATURE_ADC_HAS_STARTUP_REG (0)
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/* @brief Has ADC Trim register */
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#define FSL_FEATURE_ADC_HAS_TRIM_REG (0)
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/* @brief Has Calibration register. */
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#define FSL_FEATURE_ADC_HAS_CALIB_REG (0)
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/* @brief Has no Calibration function. */
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#define FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC (1)
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/* CAPT module features */
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/* @brief Has DMA bitfile in CTRL reigster. */
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#define FSL_FEATURE_CAPT_HAS_CTRL_DMA (0)
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/* CLOCK module features */
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/* @brief GPIOINT clock source. */
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#define FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE (1)
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/* CTIMER module features */
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/* @brief CTIMER has no capture channel. */
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#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0)
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/* @brief CTIMER has no capture 2 interrupt. */
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#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0)
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/* @brief CTIMER capture 3 interrupt. */
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#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (0)
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/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */
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#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0)
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/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */
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#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (0)
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/* @brief Writing a zero asserts the CTIMER reset. */
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#define FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET (1)
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/* @brief CTIMER Has register MSR */
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#define FSL_FEATURE_CTIMER_HAS_MSR (1)
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/* DAC module features */
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#if defined(CPU_LPC804M101JDH24) || defined(CPU_LPC804M101JHI33) || defined(CPU_LPC804M111JDH24)
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/* No feature definitions */
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#endif /* defined(CPU_LPC804M101JDH24) || defined(CPU_LPC804M101JHI33) || defined(CPU_LPC804M111JDH24) */
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/* IOCON module features */
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/* No feature definitions */
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/* MRT module features */
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/* @brief number of channels. */
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#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4)
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/* @brief Has no MULTITASK bitfile in MODCFG reigster. */
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#define FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK (1)
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/* @brief Has no INUSE bitfile in STAT reigster. */
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#define FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE (1)
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/* @brief Writing a zero asserts the MRT reset. */
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#define FSL_FEATURE_MRT_WRITE_ZERO_ASSERT_RESET (1)
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/* NVIC module features */
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/* @brief Number of connected outputs. */
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#define FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER (1)
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/* PINT module features */
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/* @brief Number of connected outputs */
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#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8)
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/* PLU module features */
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/* No feature definitions */
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/* SPI module features */
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/* @brief Has SPOL0 bitfile in CFG reigster. */
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#define FSL_FEATURE_SPI_HAS_SSEL0 (1)
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/* @brief Has SPOL1 bitfile in CFG reigster. */
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#define FSL_FEATURE_SPI_HAS_SSEL1 (1)
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/* @brief Has SPOL2 bitfile in CFG reigster. */
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#define FSL_FEATURE_SPI_HAS_SSEL2 (0)
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/* @brief Has SPOL3 bitfile in CFG reigster. */
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#define FSL_FEATURE_SPI_HAS_SSEL3 (0)
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/* SWM module features */
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/* @brief Has SWM PINENABLE0 ACMP I3. */
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#define FSL_FEATURE_SWM_HAS_PINENABLE0_ACMP_I3 (1)
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/* @brief Has SWM PINENABLE0 ACMP I4. */
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#define FSL_FEATURE_SWM_HAS_PINENABLE0_ACMP_I4 (1)
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/* @brief Has SWM PINENABLE0 ACMP I5. */
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#define FSL_FEATURE_SWM_HAS_PINENABLE0_ACMP_I5 (1)
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/* @brief Has PINASSIGNFIXED0 register. */
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#define FSL_FEATURE_SWM_HAS_PINASSIGNFIXED0_REGISTER (1)
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/* SYSCON module features */
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/* @brief Pointer to ROM IAP entry functions */
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#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x0F001FF1)
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/* @brief IAP Reinvoke ISP command parameter is pointer */
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#define FSL_FEATURE_SYSCON_IAP_REINVOKE_ISP_PARAM_POINTER (0)
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/* @brief Flash page size in bytes */
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#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (64)
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/* @brief Flash sector size in bytes */
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#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (1024)
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/* @brief Flash size in bytes */
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#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (32640)
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/* @brief IAP has Flash read & write function */
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#define FSL_FEATURE_IAP_HAS_FLASH_FUNCTION (1)
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/* @brief Starter register discontinuous. */
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#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1)
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/* @brief Has PINTSEL register. */
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#define FSL_FEATURE_SYSCON_HAS_PINT_SEL_REGISTER (1)
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/* @brief Has fixed reference clock for flash controller */
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#define FSL_FEATURE_SYSCON_HAS_FLASH_REFERENCE_CLOCK (1)
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/* USART module features */
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/* @brief Has OSR (register OSR). */
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#define FSL_FEATURE_USART_HAS_OSR_REGISTER (1)
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/* @brief Has TXIDLEEN bitfile in INTENSET reigster. */
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#define FSL_FEATURE_USART_HAS_INTENSET_TXIDLEEN (1)
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/* @brief Has ABERREN bitfile in INTENSET reigster. */
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#define FSL_FEATURE_USART_HAS_ABERR_CHECK (1)
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/* WKT module features */
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/* @brief Has SEL_EXTCLK bitfile in CTRL reigster. */
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#define FSL_FEATURE_WKT_HAS_CTRL_SEL_EXTCLK (1)
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/* WWDT module features */
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/* @brief Has LPOSC as clock source. */
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#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (1)
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/* @brief Has no RESET register. */
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#define FSL_FEATURE_WWDT_HAS_NO_RESET (1)
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#endif /* _LPC804_FEATURES_H_ */
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