1130 lines
30 KiB
C
1130 lines
30 KiB
C
/*
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* Copyright (c) 2013-2021 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* -----------------------------------------------------------------------------
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*
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* Project: CMSIS-RTOS RTX
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* Title: Cortex-A Core definitions
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*
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* -----------------------------------------------------------------------------
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*/
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#ifndef RTX_CORE_CA_H_
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#define RTX_CORE_CA_H_
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#ifndef RTX_CORE_C_H_
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#ifndef RTE_COMPONENTS_H
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#include "RTE_Components.h"
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#endif
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#include CMSIS_device_header
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#endif
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#include <stdbool.h>
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typedef bool bool_t;
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#ifndef FALSE
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#define FALSE ((bool_t)0)
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#endif
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#ifndef TRUE
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#define TRUE ((bool_t)1)
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#endif
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#define DOMAIN_NS 0
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#define EXCLUSIVE_ACCESS 1
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#define OS_TICK_HANDLER osRtxTick_Handler
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// CPSR bit definitions
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#define CPSR_T_BIT 0x20U
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#define CPSR_I_BIT 0x80U
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#define CPSR_F_BIT 0x40U
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// CPSR mode bitmasks
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#define CPSR_MODE_USER 0x10U
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#define CPSR_MODE_SYSTEM 0x1FU
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/// xPSR_Initialization Value
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/// \param[in] privileged true=privileged, false=unprivileged
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/// \param[in] thumb true=Thumb, false=Arm
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/// \return xPSR Init Value
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__STATIC_INLINE uint32_t xPSR_InitVal (bool_t privileged, bool_t thumb) {
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uint32_t psr;
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if (privileged) {
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if (thumb) {
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psr = CPSR_MODE_SYSTEM | CPSR_T_BIT;
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} else {
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psr = CPSR_MODE_SYSTEM;
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}
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} else {
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if (thumb) {
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psr = CPSR_MODE_USER | CPSR_T_BIT;
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} else {
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psr = CPSR_MODE_USER;
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}
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}
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return psr;
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}
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// Stack Frame:
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// - VFP-D32: D16-31, D0-D15, FPSCR, Reserved, R4-R11, R0-R3, R12, LR, PC, CPSR
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// - VFP-D16: D0-D15, FPSCR, Reserved, R4-R11, R0-R3, R12, LR, PC, CPSR
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// - Basic: R4-R11, R0-R3, R12, LR, PC, CPSR
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/// Stack Frame Initialization Value
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#define STACK_FRAME_INIT_VAL 0x00U
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/// Stack Offset of Register R0
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/// \param[in] stack_frame Stack Frame
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/// \return R0 Offset
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__STATIC_INLINE uint32_t StackOffsetR0 (uint8_t stack_frame) {
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uint32_t offset;
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if ((stack_frame & 0x04U) != 0U) {
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offset = (32U*8U) + (2U*4U) + (8U*4U);
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} else if ((stack_frame & 0x02U) != 0U) {
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offset = (16U*8U) + (2U*4U) + (8U*4U);
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} else {
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offset = (8U*4U);
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}
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return offset;
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}
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// ==== Emulated Cortex-M functions ====
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/// Get xPSR Register - emulate M profile: SP_usr - (8*4)
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/// \return xPSR Register value
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#if defined(__CC_ARM)
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#pragma push
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#pragma arm
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static __asm uint32_t __get_PSP (void) {
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sub sp, sp, #4
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stm sp, {sp}^
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pop {r0}
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sub r0, r0, #32
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bx lr
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}
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#pragma pop
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#else
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#ifdef __ICCARM__
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__arm
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#else
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__attribute__((target("arm")))
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#endif
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__STATIC_INLINE uint32_t __get_PSP (void) {
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register uint32_t ret;
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__ASM volatile (
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"sub sp,sp,#4\n\t"
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"stm sp,{sp}^\n\t"
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"pop {%[ret]}\n\t"
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"sub %[ret],%[ret],#32\n\t"
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: [ret] "=&l" (ret)
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:
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: "memory"
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);
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return ret;
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}
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#endif
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/// Set Control Register - not needed for A profile
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/// \param[in] control Control Register value to set
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__STATIC_INLINE void __set_CONTROL(uint32_t control) {
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(void)control;
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}
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// ==== Core functions ====
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/// Check if running Privileged
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/// \return true=privileged, false=unprivileged
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__STATIC_INLINE bool_t IsPrivileged (void) {
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return (__get_mode() != CPSR_MODE_USER);
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}
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/// Check if in Exception
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/// \return true=exception, false=thread
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__STATIC_INLINE bool_t IsException (void) {
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return ((__get_mode() != CPSR_MODE_USER) && (__get_mode() != CPSR_MODE_SYSTEM));
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}
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/// Check if IRQ is Masked
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/// \return true=masked, false=not masked
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__STATIC_INLINE bool_t IsIrqMasked (void) {
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return FALSE;
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}
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// ==== Core Peripherals functions ====
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extern uint8_t IRQ_PendSV;
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/// Setup SVC and PendSV System Service Calls (not needed on Cortex-A)
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__STATIC_INLINE void SVC_Setup (void) {
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}
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/// Get Pending SV (Service Call) Flag
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/// \return Pending SV Flag
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__STATIC_INLINE uint8_t GetPendSV (void) {
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return (IRQ_PendSV);
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}
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/// Clear Pending SV (Service Call) Flag
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__STATIC_INLINE void ClrPendSV (void) {
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IRQ_PendSV = 0U;
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}
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/// Set Pending SV (Service Call) Flag
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__STATIC_INLINE void SetPendSV (void) {
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IRQ_PendSV = 1U;
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}
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// ==== Service Calls definitions ====
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#if defined(__CC_ARM)
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#define __SVC_INDIRECT(n) __svc_indirect(n)
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#define SVC0_0N(f,t) \
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__SVC_INDIRECT(0) t svc##f (t(*)()); \
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__attribute__((always_inline)) \
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__STATIC_INLINE t __svc##f (void) { \
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svc##f(svcRtx##f); \
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}
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#define SVC0_0(f,t) \
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__SVC_INDIRECT(0) t svc##f (t(*)()); \
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__attribute__((always_inline)) \
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__STATIC_INLINE t __svc##f (void) { \
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return svc##f(svcRtx##f); \
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}
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#define SVC0_1N(f,t,t1) \
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__SVC_INDIRECT(0) t svc##f (t(*)(t1),t1); \
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__attribute__((always_inline)) \
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__STATIC_INLINE t __svc##f (t1 a1) { \
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svc##f(svcRtx##f,a1); \
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}
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#define SVC0_1(f,t,t1) \
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__SVC_INDIRECT(0) t svc##f (t(*)(t1),t1); \
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__attribute__((always_inline)) \
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__STATIC_INLINE t __svc##f (t1 a1) { \
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return svc##f(svcRtx##f,a1); \
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}
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#define SVC0_2(f,t,t1,t2) \
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__SVC_INDIRECT(0) t svc##f (t(*)(t1,t2),t1,t2); \
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__attribute__((always_inline)) \
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__STATIC_INLINE t __svc##f (t1 a1, t2 a2) { \
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return svc##f(svcRtx##f,a1,a2); \
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}
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#define SVC0_3(f,t,t1,t2,t3) \
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__SVC_INDIRECT(0) t svc##f (t(*)(t1,t2,t3),t1,t2,t3); \
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__attribute__((always_inline)) \
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__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) { \
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return svc##f(svcRtx##f,a1,a2,a3); \
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}
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#define SVC0_4(f,t,t1,t2,t3,t4) \
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__SVC_INDIRECT(0) t svc##f (t(*)(t1,t2,t3,t4),t1,t2,t3,t4); \
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__attribute__((always_inline)) \
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__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) { \
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return svc##f(svcRtx##f,a1,a2,a3,a4); \
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}
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#elif defined(__ICCARM__)
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#define SVC_ArgF(f) \
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__asm( \
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"mov r12,%0\n" \
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:: "r"(&f): "r12" \
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);
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#define STRINGIFY(a) #a
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#define __SVC_INDIRECT(n) _Pragma(STRINGIFY(swi_number = n)) __swi
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#define SVC0_0N(f,t) \
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__SVC_INDIRECT(0) t svc##f (); \
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__attribute__((always_inline)) \
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__STATIC_INLINE t __svc##f (void) { \
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SVC_ArgF(svcRtx##f); \
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svc##f(); \
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}
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#define SVC0_0(f,t) \
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__SVC_INDIRECT(0) t svc##f (); \
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__attribute__((always_inline)) \
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__STATIC_INLINE t __svc##f (void) { \
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SVC_ArgF(svcRtx##f); \
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return svc##f(); \
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}
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#define SVC0_1N(f,t,t1) \
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__SVC_INDIRECT(0) t svc##f (t1 a1); \
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__attribute__((always_inline)) \
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__STATIC_INLINE t __svc##f (t1 a1) { \
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SVC_ArgF(svcRtx##f); \
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svc##f(a1); \
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}
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#define SVC0_1(f,t,t1) \
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__SVC_INDIRECT(0) t svc##f (t1 a1); \
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__attribute__((always_inline)) \
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__STATIC_INLINE t __svc##f (t1 a1) { \
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SVC_ArgF(svcRtx##f); \
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return svc##f(a1); \
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}
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#define SVC0_2(f,t,t1,t2) \
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__SVC_INDIRECT(0) t svc##f (t1 a1, t2 a2); \
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__attribute__((always_inline)) \
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__STATIC_INLINE t __svc##f (t1 a1, t2 a2) { \
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SVC_ArgF(svcRtx##f); \
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return svc##f(a1,a2); \
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}
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#define SVC0_3(f,t,t1,t2,t3) \
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__SVC_INDIRECT(0) t svc##f (t1 a1, t2 a2, t3 a3); \
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__attribute__((always_inline)) \
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__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) { \
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SVC_ArgF(svcRtx##f); \
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return svc##f(a1,a2,a3); \
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}
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#define SVC0_4(f,t,t1,t2,t3,t4) \
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__SVC_INDIRECT(0) t svc##f (t1 a1, t2 a2, t3 a3, t4 a4); \
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__attribute__((always_inline)) \
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__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) { \
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SVC_ArgF(svcRtx##f); \
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return svc##f(a1,a2,a3,a4); \
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}
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#else // !(defined(__CC_ARM) || defined(__ICCARM__))
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#define SVC_RegF "r12"
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#define SVC_ArgN(n) \
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register uint32_t __r##n __ASM("r"#n)
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#define SVC_ArgR(n,a) \
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register uint32_t __r##n __ASM("r"#n) = (uint32_t)a
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#define SVC_ArgF(f) \
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register uint32_t __rf __ASM(SVC_RegF) = (uint32_t)f
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#define SVC_In0 "r"(__rf)
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#define SVC_In1 "r"(__rf),"r"(__r0)
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#define SVC_In2 "r"(__rf),"r"(__r0),"r"(__r1)
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#define SVC_In3 "r"(__rf),"r"(__r0),"r"(__r1),"r"(__r2)
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#define SVC_In4 "r"(__rf),"r"(__r0),"r"(__r1),"r"(__r2),"r"(__r3)
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#define SVC_Out0
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#define SVC_Out1 "=r"(__r0)
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#define SVC_CL0
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#define SVC_CL1 "r1"
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#define SVC_CL2 "r0","r1"
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#define SVC_Call0(in, out, cl) \
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__ASM volatile ("svc 0" : out : in : cl)
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#define SVC0_0N(f,t) \
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__attribute__((always_inline)) \
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__STATIC_INLINE t __svc##f (void) { \
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SVC_ArgF(svcRtx##f); \
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SVC_Call0(SVC_In0, SVC_Out0, SVC_CL2); \
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}
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#define SVC0_0(f,t) \
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__attribute__((always_inline)) \
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__STATIC_INLINE t __svc##f (void) { \
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SVC_ArgN(0); \
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SVC_ArgF(svcRtx##f); \
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SVC_Call0(SVC_In0, SVC_Out1, SVC_CL1); \
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return (t) __r0; \
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}
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#define SVC0_1N(f,t,t1) \
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__attribute__((always_inline)) \
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__STATIC_INLINE t __svc##f (t1 a1) { \
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SVC_ArgR(0,a1); \
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SVC_ArgF(svcRtx##f); \
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SVC_Call0(SVC_In1, SVC_Out0, SVC_CL1); \
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}
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#define SVC0_1(f,t,t1) \
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__attribute__((always_inline)) \
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__STATIC_INLINE t __svc##f (t1 a1) { \
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SVC_ArgR(0,a1); \
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SVC_ArgF(svcRtx##f); \
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SVC_Call0(SVC_In1, SVC_Out1, SVC_CL1); \
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return (t) __r0; \
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}
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#define SVC0_2(f,t,t1,t2) \
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__attribute__((always_inline)) \
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__STATIC_INLINE t __svc##f (t1 a1, t2 a2) { \
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SVC_ArgR(0,a1); \
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SVC_ArgR(1,a2); \
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SVC_ArgF(svcRtx##f); \
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SVC_Call0(SVC_In2, SVC_Out1, SVC_CL0); \
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return (t) __r0; \
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}
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#define SVC0_3(f,t,t1,t2,t3) \
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__attribute__((always_inline)) \
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__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) { \
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SVC_ArgR(0,a1); \
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SVC_ArgR(1,a2); \
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SVC_ArgR(2,a3); \
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SVC_ArgF(svcRtx##f); \
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SVC_Call0(SVC_In3, SVC_Out1, SVC_CL0); \
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return (t) __r0; \
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}
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#define SVC0_4(f,t,t1,t2,t3,t4) \
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__attribute__((always_inline)) \
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__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) { \
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SVC_ArgR(0,a1); \
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SVC_ArgR(1,a2); \
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SVC_ArgR(2,a3); \
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SVC_ArgR(3,a4); \
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SVC_ArgF(svcRtx##f); \
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SVC_Call0(SVC_In4, SVC_Out1, SVC_CL0); \
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return (t) __r0; \
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}
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#endif
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// ==== Exclusive Access Operation ====
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#if (EXCLUSIVE_ACCESS == 1)
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/// Atomic Access Operation: Write (8-bit)
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/// \param[in] mem Memory address
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/// \param[in] val Value to write
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/// \return Previous value
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#if defined(__CC_ARM)
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static __asm uint8_t atomic_wr8 (uint8_t *mem, uint8_t val) {
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mov r2,r0
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1
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ldrexb r0,[r2]
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strexb r3,r1,[r2]
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cmp r3,#0
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bne %B1
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bx lr
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}
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#else
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__STATIC_INLINE uint8_t atomic_wr8 (uint8_t *mem, uint8_t val) {
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#ifdef __ICCARM__
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#pragma diag_suppress=Pe550
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#endif
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register uint32_t res;
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#ifdef __ICCARM__
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#pragma diag_default=Pe550
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#endif
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register uint8_t ret;
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__ASM volatile (
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#ifndef __ICCARM__
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".syntax unified\n\t"
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#endif
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"1:\n\t"
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"ldrexb %[ret],[%[mem]]\n\t"
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"strexb %[res],%[val],[%[mem]]\n\t"
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"cmp %[res],#0\n\t"
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"bne 1b\n\t"
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: [ret] "=&l" (ret),
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[res] "=&l" (res)
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: [mem] "l" (mem),
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[val] "l" (val)
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: "memory"
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);
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return ret;
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}
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#endif
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/// Atomic Access Operation: Set bits (32-bit)
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/// \param[in] mem Memory address
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/// \param[in] bits Bit mask
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|
/// \return New value
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|
#if defined(__CC_ARM)
|
|
static __asm uint32_t atomic_set32 (uint32_t *mem, uint32_t bits) {
|
|
mov r2,r0
|
|
1
|
|
ldrex r0,[r2]
|
|
orr r0,r0,r1
|
|
strex r3,r0,[r2]
|
|
cmp r3,#0
|
|
bne %B1
|
|
bx lr
|
|
}
|
|
#else
|
|
__STATIC_INLINE uint32_t atomic_set32 (uint32_t *mem, uint32_t bits) {
|
|
#ifdef __ICCARM__
|
|
#pragma diag_suppress=Pe550
|
|
#endif
|
|
register uint32_t val, res;
|
|
#ifdef __ICCARM__
|
|
#pragma diag_default=Pe550
|
|
#endif
|
|
register uint32_t ret;
|
|
|
|
__ASM volatile (
|
|
#ifndef __ICCARM__
|
|
".syntax unified\n\t"
|
|
#endif
|
|
"1:\n\t"
|
|
"ldrex %[val],[%[mem]]\n\t"
|
|
"orr %[ret],%[val],%[bits]\n\t"
|
|
"strex %[res],%[ret],[%[mem]]\n\t"
|
|
"cmp %[res],#0\n\t"
|
|
"bne 1b\n"
|
|
: [ret] "=&l" (ret),
|
|
[val] "=&l" (val),
|
|
[res] "=&l" (res)
|
|
: [mem] "l" (mem),
|
|
[bits] "l" (bits)
|
|
: "memory"
|
|
);
|
|
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
/// Atomic Access Operation: Clear bits (32-bit)
|
|
/// \param[in] mem Memory address
|
|
/// \param[in] bits Bit mask
|
|
/// \return Previous value
|
|
#if defined(__CC_ARM)
|
|
static __asm uint32_t atomic_clr32 (uint32_t *mem, uint32_t bits) {
|
|
push {r4,lr}
|
|
mov r2,r0
|
|
1
|
|
ldrex r0,[r2]
|
|
bic r4,r0,r1
|
|
strex r3,r4,[r2]
|
|
cmp r3,#0
|
|
bne %B1
|
|
pop {r4,pc}
|
|
}
|
|
#else
|
|
__STATIC_INLINE uint32_t atomic_clr32 (uint32_t *mem, uint32_t bits) {
|
|
#ifdef __ICCARM__
|
|
#pragma diag_suppress=Pe550
|
|
#endif
|
|
register uint32_t val, res;
|
|
#ifdef __ICCARM__
|
|
#pragma diag_default=Pe550
|
|
#endif
|
|
register uint32_t ret;
|
|
|
|
__ASM volatile (
|
|
#ifndef __ICCARM__
|
|
".syntax unified\n\t"
|
|
#endif
|
|
"1:\n\t"
|
|
"ldrex %[ret],[%[mem]]\n\t"
|
|
"bic %[val],%[ret],%[bits]\n\t"
|
|
"strex %[res],%[val],[%[mem]]\n\t"
|
|
"cmp %[res],#0\n\t"
|
|
"bne 1b\n"
|
|
: [ret] "=&l" (ret),
|
|
[val] "=&l" (val),
|
|
[res] "=&l" (res)
|
|
: [mem] "l" (mem),
|
|
[bits] "l" (bits)
|
|
: "memory"
|
|
);
|
|
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
/// Atomic Access Operation: Check if all specified bits (32-bit) are active and clear them
|
|
/// \param[in] mem Memory address
|
|
/// \param[in] bits Bit mask
|
|
/// \return Active bits before clearing or 0 if not active
|
|
#if defined(__CC_ARM)
|
|
static __asm uint32_t atomic_chk32_all (uint32_t *mem, uint32_t bits) {
|
|
push {r4,lr}
|
|
mov r2,r0
|
|
1
|
|
ldrex r0,[r2]
|
|
and r4,r0,r1
|
|
cmp r4,r1
|
|
beq %F2
|
|
clrex
|
|
movs r0,#0
|
|
pop {r4,pc}
|
|
2
|
|
bic r4,r0,r1
|
|
strex r3,r4,[r2]
|
|
cmp r3,#0
|
|
bne %B1
|
|
pop {r4,pc}
|
|
}
|
|
#else
|
|
__STATIC_INLINE uint32_t atomic_chk32_all (uint32_t *mem, uint32_t bits) {
|
|
#ifdef __ICCARM__
|
|
#pragma diag_suppress=Pe550
|
|
#endif
|
|
register uint32_t val, res;
|
|
#ifdef __ICCARM__
|
|
#pragma diag_default=Pe550
|
|
#endif
|
|
register uint32_t ret;
|
|
|
|
__ASM volatile (
|
|
#ifndef __ICCARM__
|
|
".syntax unified\n\t"
|
|
#endif
|
|
"1:\n\t"
|
|
"ldrex %[ret],[%[mem]]\n\t"
|
|
"and %[val],%[ret],%[bits]\n\t"
|
|
"cmp %[val],%[bits]\n\t"
|
|
"beq 2f\n\t"
|
|
"clrex\n\t"
|
|
"movs %[ret],#0\n\t"
|
|
"b 3f\n"
|
|
"2:\n\t"
|
|
"bic %[val],%[ret],%[bits]\n\t"
|
|
"strex %[res],%[val],[%[mem]]\n\t"
|
|
"cmp %[res],#0\n\t"
|
|
"bne 1b\n"
|
|
"3:"
|
|
: [ret] "=&l" (ret),
|
|
[val] "=&l" (val),
|
|
[res] "=&l" (res)
|
|
: [mem] "l" (mem),
|
|
[bits] "l" (bits)
|
|
: "cc", "memory"
|
|
);
|
|
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
/// Atomic Access Operation: Check if any specified bits (32-bit) are active and clear them
|
|
/// \param[in] mem Memory address
|
|
/// \param[in] bits Bit mask
|
|
/// \return Active bits before clearing or 0 if not active
|
|
#if defined(__CC_ARM)
|
|
static __asm uint32_t atomic_chk32_any (uint32_t *mem, uint32_t bits) {
|
|
push {r4,lr}
|
|
mov r2,r0
|
|
1
|
|
ldrex r0,[r2]
|
|
tst r0,r1
|
|
bne %F2
|
|
clrex
|
|
movs r0,#0
|
|
pop {r4,pc}
|
|
2
|
|
bic r4,r0,r1
|
|
strex r3,r4,[r2]
|
|
cmp r3,#0
|
|
bne %B1
|
|
pop {r4,pc}
|
|
}
|
|
#else
|
|
__STATIC_INLINE uint32_t atomic_chk32_any (uint32_t *mem, uint32_t bits) {
|
|
#ifdef __ICCARM__
|
|
#pragma diag_suppress=Pe550
|
|
#endif
|
|
register uint32_t val, res;
|
|
#ifdef __ICCARM__
|
|
#pragma diag_default=Pe550
|
|
#endif
|
|
register uint32_t ret;
|
|
|
|
__ASM volatile (
|
|
#ifndef __ICCARM__
|
|
".syntax unified\n\t"
|
|
#endif
|
|
"1:\n\t"
|
|
"ldrex %[ret],[%[mem]]\n\t"
|
|
"tst %[ret],%[bits]\n\t"
|
|
"bne 2f\n\t"
|
|
"clrex\n\t"
|
|
"movs %[ret],#0\n\t"
|
|
"b 3f\n"
|
|
"2:\n\t"
|
|
"bic %[val],%[ret],%[bits]\n\t"
|
|
"strex %[res],%[val],[%[mem]]\n\t"
|
|
"cmp %[res],#0\n\t"
|
|
"bne 1b\n"
|
|
"3:"
|
|
: [ret] "=&l" (ret),
|
|
[val] "=&l" (val),
|
|
[res] "=&l" (res)
|
|
: [mem] "l" (mem),
|
|
[bits] "l" (bits)
|
|
: "cc", "memory"
|
|
);
|
|
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
/// Atomic Access Operation: Increment (32-bit)
|
|
/// \param[in] mem Memory address
|
|
/// \return Previous value
|
|
#if defined(__CC_ARM)
|
|
static __asm uint32_t atomic_inc32 (uint32_t *mem) {
|
|
mov r2,r0
|
|
1
|
|
ldrex r0,[r2]
|
|
adds r1,r0,#1
|
|
strex r3,r1,[r2]
|
|
cmp r3,#0
|
|
bne %B1
|
|
bx lr
|
|
}
|
|
#else
|
|
__STATIC_INLINE uint32_t atomic_inc32 (uint32_t *mem) {
|
|
#ifdef __ICCARM__
|
|
#pragma diag_suppress=Pe550
|
|
#endif
|
|
register uint32_t val, res;
|
|
#ifdef __ICCARM__
|
|
#pragma diag_default=Pe550
|
|
#endif
|
|
register uint32_t ret;
|
|
|
|
__ASM volatile (
|
|
#ifndef __ICCARM__
|
|
".syntax unified\n\t"
|
|
#endif
|
|
"1:\n\t"
|
|
"ldrex %[ret],[%[mem]]\n\t"
|
|
"adds %[val],%[ret],#1\n\t"
|
|
"strex %[res],%[val],[%[mem]]\n\t"
|
|
"cmp %[res],#0\n\t"
|
|
"bne 1b\n"
|
|
: [ret] "=&l" (ret),
|
|
[val] "=&l" (val),
|
|
[res] "=&l" (res)
|
|
: [mem] "l" (mem)
|
|
: "cc", "memory"
|
|
);
|
|
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
/// Atomic Access Operation: Increment (16-bit) if Less Than
|
|
/// \param[in] mem Memory address
|
|
/// \param[in] max Maximum value
|
|
/// \return Previous value
|
|
#if defined(__CC_ARM)
|
|
static __asm uint16_t atomic_inc16_lt (uint16_t *mem, uint16_t max) {
|
|
push {r4,lr}
|
|
mov r2,r0
|
|
1
|
|
ldrexh r0,[r2]
|
|
cmp r1,r0
|
|
bhi %F2
|
|
clrex
|
|
pop {r4,pc}
|
|
2
|
|
adds r4,r0,#1
|
|
strexh r3,r4,[r2]
|
|
cmp r3,#0
|
|
bne %B1
|
|
pop {r4,pc}
|
|
}
|
|
#else
|
|
__STATIC_INLINE uint16_t atomic_inc16_lt (uint16_t *mem, uint16_t max) {
|
|
#ifdef __ICCARM__
|
|
#pragma diag_suppress=Pe550
|
|
#endif
|
|
register uint32_t val, res;
|
|
#ifdef __ICCARM__
|
|
#pragma diag_default=Pe550
|
|
#endif
|
|
register uint16_t ret;
|
|
|
|
__ASM volatile (
|
|
#ifndef __ICCARM__
|
|
".syntax unified\n\t"
|
|
#endif
|
|
"1:\n\t"
|
|
"ldrexh %[ret],[%[mem]]\n\t"
|
|
"cmp %[max],%[ret]\n\t"
|
|
"bhi 2f\n\t"
|
|
"clrex\n\t"
|
|
"b 3f\n"
|
|
"2:\n\t"
|
|
"adds %[val],%[ret],#1\n\t"
|
|
"strexh %[res],%[val],[%[mem]]\n\t"
|
|
"cmp %[res],#0\n\t"
|
|
"bne 1b\n"
|
|
"3:"
|
|
: [ret] "=&l" (ret),
|
|
[val] "=&l" (val),
|
|
[res] "=&l" (res)
|
|
: [mem] "l" (mem),
|
|
[max] "l" (max)
|
|
: "cc", "memory"
|
|
);
|
|
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
/// Atomic Access Operation: Increment (16-bit) and clear on Limit
|
|
/// \param[in] mem Memory address
|
|
/// \param[in] max Maximum value
|
|
/// \return Previous value
|
|
#if defined(__CC_ARM)
|
|
static __asm uint16_t atomic_inc16_lim (uint16_t *mem, uint16_t lim) {
|
|
push {r4,lr}
|
|
mov r2,r0
|
|
1
|
|
ldrexh r0,[r2]
|
|
adds r4,r0,#1
|
|
cmp r1,r4
|
|
bhi %F2
|
|
movs r4,#0
|
|
2
|
|
strexh r3,r4,[r2]
|
|
cmp r3,#0
|
|
bne %B1
|
|
pop {r4,pc}
|
|
}
|
|
#else
|
|
__STATIC_INLINE uint16_t atomic_inc16_lim (uint16_t *mem, uint16_t lim) {
|
|
#ifdef __ICCARM__
|
|
#pragma diag_suppress=Pe550
|
|
#endif
|
|
register uint32_t val, res;
|
|
#ifdef __ICCARM__
|
|
#pragma diag_default=Pe550
|
|
#endif
|
|
register uint16_t ret;
|
|
|
|
__ASM volatile (
|
|
#ifndef __ICCARM__
|
|
".syntax unified\n\t"
|
|
#endif
|
|
"1:\n\t"
|
|
"ldrexh %[ret],[%[mem]]\n\t"
|
|
"adds %[val],%[ret],#1\n\t"
|
|
"cmp %[lim],%[val]\n\t"
|
|
"bhi 2f\n\t"
|
|
"movs %[val],#0\n"
|
|
"2:\n\t"
|
|
"strexh %[res],%[val],[%[mem]]\n\t"
|
|
"cmp %[res],#0\n\t"
|
|
"bne 1b\n"
|
|
: [ret] "=&l" (ret),
|
|
[val] "=&l" (val),
|
|
[res] "=&l" (res)
|
|
: [mem] "l" (mem),
|
|
[lim] "l" (lim)
|
|
: "cc", "memory"
|
|
);
|
|
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
/// Atomic Access Operation: Decrement (32-bit)
|
|
/// \param[in] mem Memory address
|
|
/// \return Previous value
|
|
#if defined(__CC_ARM)
|
|
static __asm uint32_t atomic_dec32 (uint32_t *mem) {
|
|
mov r2,r0
|
|
1
|
|
ldrex r0,[r2]
|
|
subs r1,r0,#1
|
|
strex r3,r1,[r2]
|
|
cmp r3,#0
|
|
bne %B1
|
|
bx lr
|
|
}
|
|
#else
|
|
__STATIC_INLINE uint32_t atomic_dec32 (uint32_t *mem) {
|
|
#ifdef __ICCARM__
|
|
#pragma diag_suppress=Pe550
|
|
#endif
|
|
register uint32_t val, res;
|
|
#ifdef __ICCARM__
|
|
#pragma diag_default=Pe550
|
|
#endif
|
|
register uint32_t ret;
|
|
|
|
__ASM volatile (
|
|
#ifndef __ICCARM__
|
|
".syntax unified\n\t"
|
|
#endif
|
|
"1:\n\t"
|
|
"ldrex %[ret],[%[mem]]\n\t"
|
|
"subs %[val],%[ret],#1\n\t"
|
|
"strex %[res],%[val],[%[mem]]\n\t"
|
|
"cmp %[res],#0\n\t"
|
|
"bne 1b\n"
|
|
: [ret] "=&l" (ret),
|
|
[val] "=&l" (val),
|
|
[res] "=&l" (res)
|
|
: [mem] "l" (mem)
|
|
: "cc", "memory"
|
|
);
|
|
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
/// Atomic Access Operation: Decrement (32-bit) if Not Zero
|
|
/// \param[in] mem Memory address
|
|
/// \return Previous value
|
|
#if defined(__CC_ARM)
|
|
static __asm uint32_t atomic_dec32_nz (uint32_t *mem) {
|
|
mov r2,r0
|
|
1
|
|
ldrex r0,[r2]
|
|
cmp r0,#0
|
|
bne %F2
|
|
clrex
|
|
bx lr
|
|
2
|
|
subs r1,r0,#1
|
|
strex r3,r1,[r2]
|
|
cmp r3,#0
|
|
bne %B1
|
|
bx lr
|
|
}
|
|
#else
|
|
__STATIC_INLINE uint32_t atomic_dec32_nz (uint32_t *mem) {
|
|
#ifdef __ICCARM__
|
|
#pragma diag_suppress=Pe550
|
|
#endif
|
|
register uint32_t val, res;
|
|
#ifdef __ICCARM__
|
|
#pragma diag_default=Pe550
|
|
#endif
|
|
register uint32_t ret;
|
|
|
|
__ASM volatile (
|
|
#ifndef __ICCARM__
|
|
".syntax unified\n\t"
|
|
#endif
|
|
"1:\n\t"
|
|
"ldrex %[ret],[%[mem]]\n\t"
|
|
"cmp %[ret],#0\n\t"
|
|
"bne 2f\n"
|
|
"clrex\n\t"
|
|
"b 3f\n"
|
|
"2:\n\t"
|
|
"subs %[val],%[ret],#1\n\t"
|
|
"strex %[res],%[val],[%[mem]]\n\t"
|
|
"cmp %[res],#0\n\t"
|
|
"bne 1b\n"
|
|
"3:"
|
|
: [ret] "=&l" (ret),
|
|
[val] "=&l" (val),
|
|
[res] "=&l" (res)
|
|
: [mem] "l" (mem)
|
|
: "cc", "memory"
|
|
);
|
|
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
/// Atomic Access Operation: Decrement (16-bit) if Not Zero
|
|
/// \param[in] mem Memory address
|
|
/// \return Previous value
|
|
#if defined(__CC_ARM)
|
|
static __asm uint16_t atomic_dec16_nz (uint16_t *mem) {
|
|
mov r2,r0
|
|
1
|
|
ldrexh r0,[r2]
|
|
cmp r0,#0
|
|
bne %F2
|
|
clrex
|
|
bx lr
|
|
2
|
|
subs r1,r0,#1
|
|
strexh r3,r1,[r2]
|
|
cmp r3,#0
|
|
bne %B1
|
|
bx lr
|
|
}
|
|
#else
|
|
__STATIC_INLINE uint16_t atomic_dec16_nz (uint16_t *mem) {
|
|
#ifdef __ICCARM__
|
|
#pragma diag_suppress=Pe550
|
|
#endif
|
|
register uint32_t val, res;
|
|
#ifdef __ICCARM__
|
|
#pragma diag_default=Pe550
|
|
#endif
|
|
register uint16_t ret;
|
|
|
|
__ASM volatile (
|
|
#ifndef __ICCARM__
|
|
".syntax unified\n\t"
|
|
#endif
|
|
"1:\n\t"
|
|
"ldrexh %[ret],[%[mem]]\n\t"
|
|
"cmp %[ret],#0\n\t"
|
|
"bne 2f\n\t"
|
|
"clrex\n\t"
|
|
"b 3f\n"
|
|
"2:\n\t"
|
|
"subs %[val],%[ret],#1\n\t"
|
|
"strexh %[res],%[val],[%[mem]]\n\t"
|
|
"cmp %[res],#0\n\t"
|
|
"bne 1b\n"
|
|
"3:"
|
|
: [ret] "=&l" (ret),
|
|
[val] "=&l" (val),
|
|
[res] "=&l" (res)
|
|
: [mem] "l" (mem)
|
|
: "cc", "memory"
|
|
);
|
|
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
/// Atomic Access Operation: Link Get
|
|
/// \param[in] root Root address
|
|
/// \return Link
|
|
#if defined(__CC_ARM)
|
|
static __asm void *atomic_link_get (void **root) {
|
|
mov r2,r0
|
|
1
|
|
ldrex r0,[r2]
|
|
cmp r0,#0
|
|
bne %F2
|
|
clrex
|
|
bx lr
|
|
2
|
|
ldr r1,[r0]
|
|
strex r3,r1,[r2]
|
|
cmp r3,#0
|
|
bne %B1
|
|
bx lr
|
|
}
|
|
#else
|
|
__STATIC_INLINE void *atomic_link_get (void **root) {
|
|
#ifdef __ICCARM__
|
|
#pragma diag_suppress=Pe550
|
|
#endif
|
|
register uint32_t val, res;
|
|
#ifdef __ICCARM__
|
|
#pragma diag_default=Pe550
|
|
#endif
|
|
register void *ret;
|
|
|
|
__ASM volatile (
|
|
#ifndef __ICCARM__
|
|
".syntax unified\n\t"
|
|
#endif
|
|
"1:\n\t"
|
|
"ldrex %[ret],[%[root]]\n\t"
|
|
"cmp %[ret],#0\n\t"
|
|
"bne 2f\n\t"
|
|
"clrex\n\t"
|
|
"b 3f\n"
|
|
"2:\n\t"
|
|
"ldr %[val],[%[ret]]\n\t"
|
|
"strex %[res],%[val],[%[root]]\n\t"
|
|
"cmp %[res],#0\n\t"
|
|
"bne 1b\n"
|
|
"3:"
|
|
: [ret] "=&l" (ret),
|
|
[val] "=&l" (val),
|
|
[res] "=&l" (res)
|
|
: [root] "l" (root)
|
|
: "cc", "memory"
|
|
);
|
|
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
/// Atomic Access Operation: Link Put
|
|
/// \param[in] root Root address
|
|
/// \param[in] lnk Link
|
|
#if defined(__CC_ARM)
|
|
static __asm void atomic_link_put (void **root, void *link) {
|
|
1
|
|
ldr r2,[r0]
|
|
str r2,[r1]
|
|
dmb
|
|
ldrex r2,[r0]
|
|
ldr r3,[r1]
|
|
cmp r3,r2
|
|
bne %B1
|
|
strex r3,r1,[r0]
|
|
cmp r3,#0
|
|
bne %B1
|
|
bx lr
|
|
}
|
|
#else
|
|
__STATIC_INLINE void atomic_link_put (void **root, void *link) {
|
|
#ifdef __ICCARM__
|
|
#pragma diag_suppress=Pe550
|
|
#endif
|
|
register uint32_t val1, val2, res;
|
|
#ifdef __ICCARM__
|
|
#pragma diag_default=Pe550
|
|
#endif
|
|
|
|
__ASM volatile (
|
|
#ifndef __ICCARM__
|
|
".syntax unified\n\t"
|
|
#endif
|
|
"1:\n\t"
|
|
"ldr %[val1],[%[root]]\n\t"
|
|
"str %[val1],[%[link]]\n\t"
|
|
"dmb\n\t"
|
|
"ldrex %[val1],[%[root]]\n\t"
|
|
"ldr %[val2],[%[link]]\n\t"
|
|
"cmp %[val2],%[val1]\n\t"
|
|
"bne 1b\n\t"
|
|
"strex %[res],%[link],[%[root]]\n\t"
|
|
"cmp %[res],#0\n\t"
|
|
"bne 1b\n"
|
|
: [val1] "=&l" (val1),
|
|
[val2] "=&l" (val2),
|
|
[res] "=&l" (res)
|
|
: [root] "l" (root),
|
|
[link] "l" (link)
|
|
: "cc", "memory"
|
|
);
|
|
}
|
|
#endif
|
|
|
|
#endif // (EXCLUSIVE_ACCESS == 1)
|
|
|
|
|
|
#endif // RTX_CORE_CA_H_
|