235 lines
6.8 KiB
C
235 lines
6.8 KiB
C
/*
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* Copyright 2021 NXP.
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "project_setup_lpcxpresso804.h"
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#include "clock_config.h"
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#include "pin_mux.h"
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#include "fsl_usart.h"
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#if FMSTR_SERIAL_ENABLE
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#include "freemaster.h"
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#include "freemaster_serial_usart.h"
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#endif
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#include "board.h"
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/*******************************************************************************
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* Code
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******************************************************************************/
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/*!
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* @brief Watchdog configuration function
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*
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* Enables the watchdog. Also in Wait and Stop mode. Updates are allowed
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*
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* @param wd_setup_value //watchdog setup value for timeout
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*
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* @return None
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*/
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void WatchdogEnable(uint32_t wd_setup_value)
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{
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SYSCON->SYSAHBCLKCTRL0 |= SYSCON_SYSAHBCLKCTRL0_WWDT_MASK; /*Enable clock to WWDT*/
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SYSCON->PDRUNCFG &= ~(SYSCON_PDRUNCFG_LPOSC_PD_MASK);
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WWDT->TC = WWDT_TC_COUNT(wd_setup_value); /*500mS refresh value */
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WWDT->MOD = (WWDT_MOD_LOCK(0)) | WWDT_MOD_WDEN(1) | (WWDT_MOD_WDRESET(1));
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WWDT->WINDOW = 0xFFFFFF; /* Disable Window mode */
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WWDT->WARNINT = 0;
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WWDT->FEED = 0xAA; /*Start WDOG */
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WWDT->FEED = 0x55;
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}
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/*!
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* @brief Watchdog disabling function
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*
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* @param None
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*
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* @return None
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*/
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void WatchdogDisable(void)
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{
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/* WDOG is disabled on LPC after reset by default */
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}
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/*!
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* @brief Initialization of Systick timer
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*
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* This function configures the Systick as a source of interrupt
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*
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* @param reloadValue - defines the period of counter refresh
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*
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* @return None
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*/
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void SystickInit(uint32_t reloadValue)
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{
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SysTick->VAL = 0;
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SysTick->LOAD = reloadValue;
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SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_TICKINT_Msk;
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}
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/* Second timer for CLOCK test */
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void ReferenceTimerInit(void)
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{
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SYSCON->SYSAHBCLKCTRL0 |= SYSCON_SYSAHBCLKCTRL0_WKT_MASK; /* Enable Clock to WKT regiter */
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SYSCON->PRESETCTRL0 &= ~(SYSCON_PRESETCTRL0_WKT_RST_N_MASK); // Reset the WKT
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SYSCON->PRESETCTRL0 |= (SYSCON_PRESETCTRL0_WKT_RST_N_MASK);
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SYSCON->PDRUNCFG &= ~(SYSCON_PDRUNCFG_LPOSC_PD_MASK);
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SYSCON->LPOSCCLKEN |= 0x2; /*Enable clock for WKT */
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WKT->CTRL = 0x1; /*Set LPO osc as clokc for WKT */
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WKT->COUNT = START_VALUE; /* Set start value for Decreasin of Counter */
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}
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/*!
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* @brief Setup of clock
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*
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* @param void
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*
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* @return None
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*
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*
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*/
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void ClockInit(void)
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{
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BOARD_BootClockFRO30M();
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/*Enable clock to IOCONN and SWM*/
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SYSCON->SYSAHBCLKCTRL0 |= (SYSCON_SYSAHBCLKCTRL0_SWM(1) | SYSCON_SYSAHBCLKCTRL0_IOCON(1));
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}
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/*!
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* @brief Initialization of CTIMER
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*
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* This function initializes the CTIMER. CTIMER is used for After reset WDog test.
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*
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* @param void
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*
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* @return None
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*/
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void CTIMERInit(void)
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{
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SYSCON->SYSAHBCLKCTRL0 |= SYSCON_SYSAHBCLKCTRL0_CTIMER_MASK; // Enable clock
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CTIMER0->CTCR = 0; /* Give DEFAULT state, Timer mode selected */
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CTIMER0->MCR = 0; /* Default state*/
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CTIMER0->CCR = 0; /* Default state*/
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CTIMER0->EMR = 0; /* Default state*/
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CTIMER0->PWMC = 0; /* Default state*/
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CTIMER0->PR = 0; /* Every APB bus clock */
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}
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/*!
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* @brief Sets port direction and mux
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*
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* @param
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*
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* @return None
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*/
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void PortInit(uint8_t *pByte,
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uint32_t *pDir,
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uint32_t *pIocon,
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uint32_t pinDir,
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uint32_t pinNum,
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uint32_t pull,
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uint32_t clock_enable_shift)
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{
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/* Enable clock to GPIO module */
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SYSCON->SYSAHBCLKCTRL0 |= (1 << clock_enable_shift);
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*pIocon &= ~(IOCON_PIO_MODE_MASK); /*Clear PULL setting*/
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*pIocon |= IOCON_PIO_MODE(pull); /*Set pullup*/
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if (pinDir == PIN_DIRECTION_OUT)
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{
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*pDir |= (1 << pinNum); /* PINx = 1 = output */
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}
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else if (pinDir == PIN_DIRECTION_IN)
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{
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*pDir &= ~(1 << pinNum); /* PINx = 0 = input */
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}
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}
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/*!
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* @brief Initialization of ADC0
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*
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* 8 MHz System Oscillator Bus Clock is the source clock.
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* single-ended 12-bit conversion
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*
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* @param void
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*
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* @return None
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*/
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#define FRO_CLK 30000000
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void AdcInit(void)
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{
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// uint8_t clkdiv = 0;
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uint32_t temp;
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// Step 1. Power up and reset the ADC, and enable clocks to peripheral
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SYSCON->PDRUNCFG &= ~(SYSCON_PDRUNCFG_ADC_PD_MASK);
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SYSCON->PRESETCTRL0 &= ~(SYSCON_PRESETCTRL0_ADC_RST_N_MASK);
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SYSCON->PRESETCTRL0 |= (SYSCON_PRESETCTRL0_ADC_RST_N_MASK);
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SYSCON->SYSAHBCLKCTRL0 |= (SYSCON_SYSAHBCLKCTRL0_ADC_MASK); /* Enable Clock to ADC */
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SYSCON->ADCCLKDIV = 1; // Enable clock, and divide-by-1 at this clock divider
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SYSCON->ADCCLKSEL = 0; // Use fro_clk as source for ADC async clock
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temp = ADC->CTRL;
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// Step 2. Perform a self-calibration
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// Choose a CLKDIV divider value that yields about 500 KHz.
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// clkdiv = (FRO_CLK / 500000) - 1;
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ADC->CTRL = temp; /*REstroe ADC setting*/
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ADC->CTRL |= 0x1; /*Clock Divider 2*/
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ADC->SEQ_CTRL[0] |= ADC_SEQ_CTRL_TRIGPOL_MASK; // polarity of triger
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// TODO Some macro for easy edit?
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SWM0->PINENABLE0 &= ~(SWM_PINENABLE0_ADC_0_MASK | SWM_PINENABLE0_ADC_3_MASK | SWM_PINENABLE0_ADC_7_MASK);
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}
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/* Configure UART0 for "brate" baud
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*
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**********************************************************/
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void SerialInit(void)
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{
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usart_config_t config;
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/* Select the main clock as source clock of USART0 (debug console) */
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CLOCK_Select(BOARD_DEBUG_USART_CLK_ATTACH);
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/* Board initialization */
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BOARD_InitPins();
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/*
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* usartConfig->baudRate_Bps = UART_BAUD_RATE;
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* usartConfig->parityMode = kUSART_ParityDisabled;
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* usartConfig->stopBitCount = kUSART_OneStopBit;
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* usartConfig->bitCountPerChar = kUSART_8BitsPerChar;
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* usartConfig->loopback = false;
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* usartConfig->enableTx = false;
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* usartConfig->enableRx = false;
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*/
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USART_GetDefaultConfig(&config);
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/* Override the Default configuration to satisfy FreeMASTER needs */
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config.baudRate_Bps = UART_BAUD_RATE;
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config.enableTx = false;
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config.enableRx = false;
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USART_Init((USART_Type *)BOARD_DEBUG_USART_BASEADDR, &config, BOARD_DEBUG_USART_CLK_FREQ);
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#if FMSTR_SERIAL_ENABLE
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/* Register communication module used by FreeMASTER driver. */
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FMSTR_SerialSetBaseAddress((USART_Type *)BOARD_DEBUG_USART_BASEADDR);
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#if FMSTR_SHORT_INTR || FMSTR_LONG_INTR
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/* Enable UART interrupts. */
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EnableIRQ(BOARD_UART_IRQ);
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EnableGlobalIRQ(0);
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#endif
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#endif // FMSTR_SERIAL_ENABLE
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}
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