/*******************************************************************************
*
 * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc.
 * Copyright 2016-2021 NXP
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *
 * o Redistributions of source code must retain the above copyright notice, this list
 *   of conditions and the following disclaimer.
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 *   list of conditions and the following disclaimer in the documentation and/or
 *   other materials provided with the distribution.
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 *   contributors may be used to endorse or promote products derived from this
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* 
*
****************************************************************************//*!
*
* @brief  MLIB_MMDVSQ.h
* 
*******************************************************************************/
#ifndef _MLIB_MMDVSQ_H_
#define _MLIB_MMDVSQ_H_

#if defined(__cplusplus)
extern "C" {
#endif

/******************************************************************************
* Includes
******************************************************************************/   
#include "mlib_types.h"

/*******************************************************************************
* Macros
*******************************************************************************/    
/* Base address of Memory-Mapped Divide and Square Root peripheral module(MMDVSQ) */ 
#define RTCESL_MMDVSQ_BASE_PTR 0xF0004000U

/* MMDVSQ registers definitions
*  Absolute      Register name                        Width      Access Reset value
*  address (hex)                                      (in bits)
*  F000_4000     Dividend Register (MMDVSQ_DEND)      32         R/W    Undefined
*  F000_4004     Divisor Register (MMDVSQ_DSOR)       32         R/W    Undefined
*  F000_4008     Control/Status Register (MMDVSQ_CSR) 32         R/W    Some bits undefined
*  F000_400C     Result Register (MMDVSQ_RES)         32         R/W    Undefined
*  F000_4010     Radicand Register (MMDVSQ_RCND)      32         W      Undefined    */
    
#define RTCESL_MMDVSQ_DEND  *(volatile unsigned int*)(RTCESL_MMDVSQ_BASE_PTR + 0x0U)
#define RTCESL_MMDVSQ_DSOR  *(volatile unsigned int*)(RTCESL_MMDVSQ_BASE_PTR + 0x4U)
#define RTCESL_MMDVSQ_CSR   *(volatile unsigned int*)(RTCESL_MMDVSQ_BASE_PTR + 0x8U)
#define RTCESL_MMDVSQ_RES   *(volatile unsigned int*)(RTCESL_MMDVSQ_BASE_PTR + 0xCU)
#define RTCESL_MMDVSQ_RCND  *(volatile unsigned int*)(RTCESL_MMDVSQ_BASE_PTR + 0x10U)

/*******************************************************************************
* Variables
*******************************************************************************/    
/* Global variable which store actual MMDVSQ state to avoid register 
   rewriting during interrupt service routine handling */  
extern volatile uint16_t gu16CntMmdvsq;  

#if defined(__cplusplus)
}
#endif

#endif /* _MLIB_MMDVSQ_H_ */  


