![]() |
MCUXpresso SDK API Reference Manual
Rev 2.11.0
NXP Semiconductors
|
The MCUXpresso SDK provides APIs for MCUXpresso SDK devices' clock operation.
The clock driver supports:
The MCUXpresso SDK provides a peripheral clock driver for the SYSCON module of MCUXpresso SDK devices.
Clock driver provides these functions:
SYSCON clock module provides clocks, such as MCLKCLK, ADCCLK, DMICCLK, MCGFLLCLK, FXCOMCLK, WDTOSC, RTCOSC, USBCLK, and SYSPLL. The functions CLOCK_EnableClock() and CLOCK_DisableClock() enables and disables the various clocks. CLOCK_SetupFROClocking() initializes the FRO to 12 MHz, 48 MHz, or 96 MHz frequency. CLOCK_SetupPLLData(), CLOCK_SetupSystemPLLPrec(), and CLOCK_SetPLLFreq() functions are used to setup the PLL. The SYSCON clock driver provides functions to get the frequency of these clocks, such as CLOCK_GetFreq(), CLOCK_GetFro12MFreq(), CLOCK_GetExtClkFreq(), CLOCK_GetWdtOscFreq(), CLOCK_GetFroHfFreq(), CLOCK_GetPllOutFreq(), CLOCK_GetOsc32KFreq(), CLOCK_GetCoreSysClkFreq(), CLOCK_GetI2SMClkFreq(), CLOCK_GetFlexCommClkFreq, and CLOCK_GetAsyncApbClkFreq.
The SYSCON clock driver provides the function to configure the clock selected. The function CLOCK_AttachClk() is implemented for this. The function selects the clock source for a particular peripheral like MAINCLK, DMIC, FLEXCOMM, USB, ADC, and PLL.
The SYSCON clock module provides the function to setup the peripheral clock dividers. The function CLOCK_SetClkDiv() configures the CLKDIV registers for various periperals like USB, DMIC, I2S, SYSTICK, AHB, ADC, and also CLKOUT and TRACE functions.
The SYSCON clock driver provides the function CLOCK_SetFLASHAccessCyclesForFreq() that configures FLASHCFG register with a selected FLASHTIM value.
POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on so that we can switch to its 12MHz mode temporarily
Files | |
file | fsl_clock.h |
Data Structures | |
struct | clock_sys_pll_t |
PLL configuration structure. More... | |
Macros | |
#define | CLOCK_FRO_SETTING_API_ROM_ADDRESS (0x0F0026F5U) |
FRO clock setting API address in ROM. More... | |
#define | CLOCK_FAIM_BASE (0x50010000U) |
FAIM base address. | |
#define | ADC_CLOCKS |
Clock ip name array for ADC. More... | |
#define | ACMP_CLOCKS |
Clock ip name array for ACMP. More... | |
#define | DAC_CLOCKS |
Clock ip name array for DAC. More... | |
#define | SWM_CLOCKS |
Clock ip name array for SWM. More... | |
#define | ROM_CLOCKS |
Clock ip name array for ROM. More... | |
#define | SRAM_CLOCKS |
Clock ip name array for SRAM. More... | |
#define | IOCON_CLOCKS |
Clock ip name array for IOCON. More... | |
#define | GPIO_CLOCKS |
Clock ip name array for GPIO. More... | |
#define | GPIO_INT_CLOCKS |
Clock ip name array for GPIO_INT. More... | |
#define | DMA_CLOCKS |
Clock ip name array for DMA. More... | |
#define | CRC_CLOCKS |
Clock ip name array for CRC. More... | |
#define | WWDT_CLOCKS |
Clock ip name array for WWDT. More... | |
#define | SCT_CLOCKS |
Clock ip name array for SCT0. More... | |
#define | I2C_CLOCKS |
Clock ip name array for I2C. More... | |
#define | USART_CLOCKS |
Clock ip name array for I2C. More... | |
#define | SPI_CLOCKS |
Clock ip name array for SPI. More... | |
#define | CAPT_CLOCKS |
Clock ip name array for CAPT. More... | |
#define | CTIMER_CLOCKS |
Clock ip name array for CTIMER. More... | |
#define | MTB_CLOCKS |
Clock ip name array for MTB. More... | |
#define | MRT_CLOCKS |
Clock ip name array for MRT. More... | |
#define | WKT_CLOCKS |
Clock ip name array for WKT. More... | |
#define | CLK_GATE_DEFINE(reg, bit) ((((reg)&0xFFU) << 8U) | ((bit)&0xFFU)) |
Internal used Clock definition only. More... | |
Enumerations | |
enum | clock_ip_name_t { kCLOCK_IpInvalid = 0U, kCLOCK_Rom = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 1U), kCLOCK_Ram0_1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 2U), kCLOCK_I2c0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 5U), kCLOCK_Gpio0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 6U), kCLOCK_Swm = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 7U), kCLOCK_Sct = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 8U), kCLOCK_Wkt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 9U), kCLOCK_Mrt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 10U), kCLOCK_Spi0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 11U), kCLOCK_Spi1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 12U), kCLOCK_Crc = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 13U), kCLOCK_Uart0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 14U), kCLOCK_Uart1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 15U), kCLOCK_Uart2 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 16U), kCLOCK_Wwdt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 17U), kCLOCK_Iocon = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 18U), kCLOCK_Acmp = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 19U), kCLOCK_Gpio1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 20U), kCLOCK_I2c1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 21U), kCLOCK_I2c2 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 22U), kCLOCK_I2c3 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 23U), kCLOCK_Adc = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 24U), kCLOCK_Ctimer0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 25U), kCLOCK_Mtb = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 26U), kCLOCK_Dac0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 27U), kCLOCK_GpioInt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 28U), kCLOCK_Dma = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 29U), kCLOCK_Uart3 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 30U), kCLOCK_Uart4 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 31U), kCLOCK_Capt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL1, 0U), kCLOCK_Dac1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL1, 1U) } |
Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. More... | |
enum | clock_name_t { kCLOCK_CoreSysClk, kCLOCK_MainClk, kCLOCK_Fro, kCLOCK_FroDiv, kCLOCK_ExtClk, kCLOCK_PllOut, kCLOCK_WdtOsc, kCLOCK_Frg0, kCLOCK_Frg1 } |
Clock name used to get clock frequency. More... | |
enum | clock_select_t { kCAPT_Clk_From_Fro = CLK_MUX_DEFINE(CAPTCLKSEL, 0U), kCAPT_Clk_From_MainClk = CLK_MUX_DEFINE(CAPTCLKSEL, 1U), kCAPT_Clk_From_SysPll = CLK_MUX_DEFINE(CAPTCLKSEL, 2U), kCAPT_Clk_From_Fro_Div = CLK_MUX_DEFINE(CAPTCLKSEL, 3U), kCAPT_Clk_From_WdtOsc = CLK_MUX_DEFINE(CAPTCLKSEL, 4U), kADC_Clk_From_Fro = CLK_MUX_DEFINE(ADCCLKSEL, 0U), kADC_Clk_From_SysPll = CLK_MUX_DEFINE(ADCCLKSEL, 1U), kSCT_Clk_From_Fro = CLK_MUX_DEFINE(SCTCLKSEL, 0U), kSCT_Clk_From_MainClk = CLK_MUX_DEFINE(SCTCLKSEL, 1U), kSCT_Clk_From_SysPll = CLK_MUX_DEFINE(SCTCLKSEL, 2U), kEXT_Clk_From_SysOsc = CLK_MUX_DEFINE(EXTCLKSEL, 0U), kEXT_Clk_From_ClkIn = CLK_MUX_DEFINE(EXTCLKSEL, 1U), kUART0_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[0U], 0U), kUART0_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[0U], 1U), kUART0_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[0U], 2U), kUART0_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[0U], 3U), kUART0_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[0U], 4U), kUART1_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[1U], 0U), kUART1_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[1U], 1U), kUART1_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[1U], 2U), kUART1_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[1U], 3U), kUART1_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[1U], 4U), kUART2_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[2U], 0U), kUART2_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[2U], 1U), kUART2_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[2U], 2U), kUART2_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[2U], 3U), kUART2_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[2U], 4U), kUART3_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[3U], 0U), kUART3_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[3U], 1U), kUART3_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[3U], 2U), kUART3_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[3U], 3U), kUART3_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[3U], 4U), kUART4_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[4U], 0U), kUART4_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[4U], 1U), kUART4_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[4U], 2U), kUART4_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[4U], 3U), kUART4_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[4U], 4U), kI2C0_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[5U], 0U), kI2C0_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[5U], 1U), kI2C0_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[5U], 2U), kI2C0_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[5U], 3U), kI2C0_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[5U], 4U), kI2C1_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[6U], 0U), kI2C1_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[6U], 1U), kI2C1_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[6U], 2U), kI2C1_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[6U], 3U), kI2C1_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[6U], 4U), kI2C2_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[7U], 0U), kI2C2_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[7U], 1U), kI2C2_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[7U], 2U), kI2C2_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[7U], 3U), kI2C2_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[7U], 4U), kI2C3_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[8U], 0U), kI2C3_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[8U], 1U), kI2C3_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[8U], 2U), kI2C3_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[8U], 3U), kI2C3_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[8U], 4U), kSPI0_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[9U], 0U), kSPI0_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[9U], 1U), kSPI0_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[9U], 2U), kSPI0_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[9U], 3U), kSPI0_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[9U], 4U), kSPI1_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[10U], 0U), kSPI1_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[10U], 1U), kSPI1_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[10U], 2U), kSPI1_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[10U], 3U), kSPI1_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[10U], 4U), kFRG0_Clk_From_Fro = CLK_MUX_DEFINE(FRG[0U].FRGCLKSEL, 0U), kFRG0_Clk_From_MainClk = CLK_MUX_DEFINE(FRG[0U].FRGCLKSEL, 1U), kFRG0_Clk_From_SysPll = CLK_MUX_DEFINE(FRG[0U].FRGCLKSEL, 2U), kFRG1_Clk_From_Fro = CLK_MUX_DEFINE(FRG[1U].FRGCLKSEL, 0U), kFRG1_Clk_From_MainClk = CLK_MUX_DEFINE(FRG[1U].FRGCLKSEL, 1U), kFRG1_Clk_From_SysPll = CLK_MUX_DEFINE(FRG[1U].FRGCLKSEL, 2U), kCLKOUT_From_Fro = CLK_MUX_DEFINE(CLKOUTSEL, 0U), kCLKOUT_From_MainClk = CLK_MUX_DEFINE(CLKOUTSEL, 1U), kCLKOUT_From_SysPll = CLK_MUX_DEFINE(CLKOUTSEL, 2U), kCLKOUT_From_ExtClk = CLK_MUX_DEFINE(CLKOUTSEL, 3U), kCLKOUT_From_WdtOsc = CLK_MUX_DEFINE(CLKOUTSEL, 4U) } |
Clock Mux Switches CLK_MUX_DEFINE(reg, mux) reg is used to define the mux register mux is used to define the mux value. More... | |
enum | clock_divider_t { kCLOCK_DivAdcClk = CLK_DIV_DEFINE(ADCCLKDIV), kCLOCK_DivSctClk = CLK_DIV_DEFINE(SCTCLKDIV), kCLOCK_DivClkOut = CLK_DIV_DEFINE(CLKOUTDIV), kCLOCK_IOCONCLKDiv6 = CLK_DIV_DEFINE(IOCONCLKDIV6), kCLOCK_IOCONCLKDiv5 = CLK_DIV_DEFINE(IOCONCLKDIV5), kCLOCK_IOCONCLKDiv4 = CLK_DIV_DEFINE(IOCONCLKDIV4), kCLOCK_IOCONCLKDiv3 = CLK_DIV_DEFINE(IOCONCLKDIV3), kCLOCK_IOCONCLKDiv2 = CLK_DIV_DEFINE(IOCONCLKDIV2), kCLOCK_IOCONCLKDiv1 = CLK_DIV_DEFINE(IOCONCLKDIV1), kCLOCK_IOCONCLKDiv0 = CLK_DIV_DEFINE(IOCONCLKDIV0) } |
Clock divider. More... | |
enum | clock_wdt_analog_freq_t { kCLOCK_WdtAnaFreq0HZ = CLK_WDT_OSC_DEFINE(0U, 0U), kCLOCK_WdtAnaFreq600KHZ = CLK_WDT_OSC_DEFINE(600000U, 1U), kCLOCK_WdtAnaFreq1050KHZ = CLK_WDT_OSC_DEFINE(1050000U, 2u), kCLOCK_WdtAnaFreq1400KHZ = CLK_WDT_OSC_DEFINE(1400000U, 3U), kCLOCK_WdtAnaFreq1750KHZ = CLK_WDT_OSC_DEFINE(1750000U, 4U), kCLOCK_WdtAnaFreq2100KHZ = CLK_WDT_OSC_DEFINE(2100000U, 5U), kCLOCK_WdtAnaFreq2400KHZ = CLK_WDT_OSC_DEFINE(2400000U, 6U), kCLOCK_WdtAnaFreq2700KHZ = CLK_WDT_OSC_DEFINE(2700000U, 7U), kCLOCK_WdtAnaFreq3000KHZ = CLK_WDT_OSC_DEFINE(3000000U, 8U), kCLOCK_WdtAnaFreq3250KHZ = CLK_WDT_OSC_DEFINE(3250000U, 9U), kCLOCK_WdtAnaFreq3500KHZ = CLK_WDT_OSC_DEFINE(3500000U, 10U), kCLOCK_WdtAnaFreq3750KHZ = CLK_WDT_OSC_DEFINE(3750000U, 11U), kCLOCK_WdtAnaFreq4000KHZ = CLK_WDT_OSC_DEFINE(4000000U, 12U), kCLOCK_WdtAnaFreq4200KHZ = CLK_WDT_OSC_DEFINE(4200000U, 13U), kCLOCK_WdtAnaFreq4400KHZ = CLK_WDT_OSC_DEFINE(4400000U, 14U), kCLOCK_WdtAnaFreq4600KHZ = CLK_WDT_OSC_DEFINE(4600000U, 15U) } |
watch dog analog output frequency More... | |
enum | clock_fro_src_t { kCLOCK_FroSrcLpwrBootValue = 0U, kCLOCK_FroSrcFroOsc = 1U << SYSCON_FROOSCCTRL_FRO_DIRECT_SHIFT } |
fro output frequency source definition More... | |
enum | clock_fro_osc_freq_t { kCLOCK_FroOscOut18M = 18000U, kCLOCK_FroOscOut24M = 24000U, kCLOCK_FroOscOut30M = 30000U } |
fro oscillator output frequency value definition More... | |
enum | clock_sys_pll_src { kCLOCK_SysPllSrcFRO = 0U, kCLOCK_SysPllSrcExtClk = 1U, kCLOCK_SysPllSrcWdtOsc = 2U, kCLOCK_SysPllSrcFroDiv = 3U } |
PLL clock definition. More... | |
enum | clock_main_clk_src_t { kCLOCK_MainClkSrcFro = CLK_MAIN_CLK_MUX_DEFINE(0U, 0U), kCLOCK_MainClkSrcExtClk = CLK_MAIN_CLK_MUX_DEFINE(1U, 0U), kCLOCK_MainClkSrcWdtOsc = CLK_MAIN_CLK_MUX_DEFINE(2U, 0U), kCLOCK_MainClkSrcFroDiv = CLK_MAIN_CLK_MUX_DEFINE(3U, 0U), kCLOCK_MainClkSrcSysPll = CLK_MAIN_CLK_MUX_DEFINE(0U, 1U) } |
Main clock source definition. More... | |
Variables | |
volatile uint32_t | g_Wdt_Osc_Freq |
watchdog oscilltor clock frequency. More... | |
volatile uint32_t | g_Ext_Clk_Freq |
external clock frequency. More... | |
Driver version | |
#define | FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 3)) |
CLOCK driver version 2.3.3. More... | |
Clock gate, mux, and divider. | |
static void | CLOCK_EnableClock (clock_ip_name_t clk) |
static void | CLOCK_DisableClock (clock_ip_name_t clk) |
static void | CLOCK_Select (clock_select_t sel) |
static void | CLOCK_SetClkDivider (clock_divider_t name, uint32_t value) |
static uint32_t | CLOCK_GetClkDivider (clock_divider_t name) |
static void | CLOCK_SetCoreSysClkDiv (uint32_t value) |
void | CLOCK_SetMainClkSrc (clock_main_clk_src_t src) |
Set main clock reference source. More... | |
void | CLOCK_SetFroOutClkSrc (clock_fro_src_t src) |
Set FRO clock source. More... | |
static void | CLOCK_SetFRGClkMul (uint32_t *base, uint32_t mul) |
Get frequency | |
uint32_t | CLOCK_GetFRG0ClkFreq (void) |
Return Frequency of FRG0 Clock. More... | |
uint32_t | CLOCK_GetFRG1ClkFreq (void) |
Return Frequency of FRG1 Clock. More... | |
uint32_t | CLOCK_GetMainClkFreq (void) |
Return Frequency of Main Clock. More... | |
uint32_t | CLOCK_GetFroFreq (void) |
Return Frequency of FRO. More... | |
static uint32_t | CLOCK_GetCoreSysClkFreq (void) |
Return Frequency of core. More... | |
uint32_t | CLOCK_GetClockOutClkFreq (void) |
Return Frequency of ClockOut. More... | |
uint32_t | CLOCK_GetUart0ClkFreq (void) |
Get UART0 frequency. More... | |
uint32_t | CLOCK_GetUart1ClkFreq (void) |
Get UART1 frequency. More... | |
uint32_t | CLOCK_GetUart2ClkFreq (void) |
Get UART2 frequency. More... | |
uint32_t | CLOCK_GetUart3ClkFreq (void) |
Get UART3 frequency. More... | |
uint32_t | CLOCK_GetUart4ClkFreq (void) |
Get UART4 frequency. More... | |
uint32_t | CLOCK_GetFreq (clock_name_t clockName) |
Return Frequency of selected clock. More... | |
uint32_t | CLOCK_GetSystemPLLInClockRate (void) |
Return System PLL input clock rate. More... | |
static uint32_t | CLOCK_GetSystemPLLFreq (void) |
Return Frequency of System PLL. More... | |
static uint32_t | CLOCK_GetWdtOscFreq (void) |
Get watch dog OSC frequency. More... | |
static uint32_t | CLOCK_GetExtClkFreq (void) |
Get external clock frequency. More... | |
PLL operations | |
void | CLOCK_InitSystemPll (const clock_sys_pll_t *config) |
System PLL initialize. More... | |
static void | CLOCK_DenitSystemPll (void) |
System PLL Deinitialize. More... | |
Fractional clock operations | |
bool | CLOCK_SetFRG0ClkFreq (uint32_t freq) |
Set FRG0 output frequency. More... | |
bool | CLOCK_SetFRG1ClkFreq (uint32_t freq) |
Set FRG1 output frequency. More... | |
External/internal oscillator clock operations | |
void | CLOCK_InitExtClkin (uint32_t clkInFreq) |
Init external CLK IN, select the CLKIN as the external clock source. More... | |
void | CLOCK_InitSysOsc (uint32_t oscFreq) |
Init SYS OSC. More... | |
void | CLOCK_InitXtalin (uint32_t xtalInFreq) |
XTALIN init function system oscillator is bypassed, sys_osc_clk is fed driectly from the XTALIN. More... | |
static void | CLOCK_DeinitSysOsc (void) |
Deinit SYS OSC. | |
void | CLOCK_InitWdtOsc (clock_wdt_analog_freq_t wdtOscFreq, uint32_t wdtOscDiv) |
Init watch dog OSC Any setting of the FREQSEL bits will yield a Fclkana value within 40% of the listed frequency value. More... | |
static void | CLOCK_DeinitWdtOsc (void) |
Deinit watch dog OSC. | |
static void | CLOCK_SetFroOscFreq (clock_fro_osc_freq_t freq) |
Set FRO oscillator output frequency. More... | |
struct clock_sys_pll_t |
Data Fields | |
uint32_t | targetFreq |
System pll fclk output frequency, the output frequency should be lower than 100MHZ. | |
clock_sys_pll_src | src |
System pll clock source. | |
#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 3)) |
#define CLOCK_FRO_SETTING_API_ROM_ADDRESS (0x0F0026F5U) |
#define ADC_CLOCKS |
#define ACMP_CLOCKS |
#define DAC_CLOCKS |
#define SWM_CLOCKS |
#define ROM_CLOCKS |
#define SRAM_CLOCKS |
#define IOCON_CLOCKS |
#define GPIO_CLOCKS |
#define GPIO_INT_CLOCKS |
#define DMA_CLOCKS |
#define CRC_CLOCKS |
#define WWDT_CLOCKS |
#define SCT_CLOCKS |
#define I2C_CLOCKS |
#define USART_CLOCKS |
#define SPI_CLOCKS |
#define CAPT_CLOCKS |
#define CTIMER_CLOCKS |
#define MTB_CLOCKS |
#define MRT_CLOCKS |
#define WKT_CLOCKS |
#define CLK_GATE_DEFINE | ( | reg, | |
bit | |||
) | ((((reg)&0xFFU) << 8U) | ((bit)&0xFFU)) |
enum clock_ip_name_t |
enum clock_name_t |
enum clock_select_t |
enum clock_divider_t |
enum clock_fro_src_t |
enum clock_fro_osc_freq_t |
enum clock_sys_pll_src |
enum clock_main_clk_src_t |
void CLOCK_SetMainClkSrc | ( | clock_main_clk_src_t | src | ) |
src | Refer to clock_main_clk_src_t to set the main clock source. |
void CLOCK_SetFroOutClkSrc | ( | clock_fro_src_t | src | ) |
src | Please refer to _clock_fro_src definition. |
uint32_t CLOCK_GetFRG0ClkFreq | ( | void | ) |
uint32_t CLOCK_GetFRG1ClkFreq | ( | void | ) |
uint32_t CLOCK_GetMainClkFreq | ( | void | ) |
uint32_t CLOCK_GetFroFreq | ( | void | ) |
|
inlinestatic |
uint32_t CLOCK_GetClockOutClkFreq | ( | void | ) |
uint32_t CLOCK_GetUart0ClkFreq | ( | void | ) |
UART0 | frequency value. |
uint32_t CLOCK_GetUart1ClkFreq | ( | void | ) |
UART1 | frequency value. |
uint32_t CLOCK_GetUart2ClkFreq | ( | void | ) |
UART2 | frequency value. |
uint32_t CLOCK_GetUart3ClkFreq | ( | void | ) |
UART3 | frequency value. |
uint32_t CLOCK_GetUart4ClkFreq | ( | void | ) |
UART4 | frequency value. |
uint32_t CLOCK_GetFreq | ( | clock_name_t | clockName | ) |
uint32_t CLOCK_GetSystemPLLInClockRate | ( | void | ) |
|
inlinestatic |
|
inlinestatic |
watch | dog OSC frequency value. |
|
inlinestatic |
external | clock frequency value. |
void CLOCK_InitSystemPll | ( | const clock_sys_pll_t * | config | ) |
config | System PLL configurations. |
|
inlinestatic |
bool CLOCK_SetFRG0ClkFreq | ( | uint32_t | freq | ) |
freq | Target output frequency, freq < input and (input / freq) < 2 should be satisfy. |
true | - successfully, false - input argument is invalid. |
bool CLOCK_SetFRG1ClkFreq | ( | uint32_t | freq | ) |
freq | Target output frequency, freq < input and (input / freq) < 2 should be satisfy. |
true | - successfully, false - input argument is invalid. |
void CLOCK_InitExtClkin | ( | uint32_t | clkInFreq | ) |
clkInFreq | external clock in frequency. |
void CLOCK_InitSysOsc | ( | uint32_t | oscFreq | ) |
oscFreq | oscillator frequency value. |
void CLOCK_InitXtalin | ( | uint32_t | xtalInFreq | ) |
xtalInFreq | XTALIN frequency value |
void CLOCK_InitWdtOsc | ( | clock_wdt_analog_freq_t | wdtOscFreq, |
uint32_t | wdtOscDiv | ||
) |
The watchdog oscillator is the clock source with the lowest power consumption. If accurate timing is required, use the FRO or system oscillator. The frequency of the watchdog oscillator is undefined after reset. The watchdog oscillator frequency must be programmed by writing to the WDTOSCCTRL register before using the watchdog oscillator. Watchdog osc output frequency = wdtOscFreq / wdtOscDiv, should in range 9.3KHZ to 2.3MHZ.
wdtOscFreq | watch dog analog part output frequency, reference _wdt_analog_output_freq. |
wdtOscDiv | watch dog analog part output frequency divider, shoule be a value >= 2U and multiple of 2 |
|
inlinestatic |
Initialize the FRO clock to given frequency (18, 24 or 30 MHz).
freq | Please refer to clock_fro_osc_freq_t definition, frequency must be one of 18000, 24000 or 30000 KHz. |
volatile uint32_t g_Wdt_Osc_Freq |
This variable is used to store the watchdog oscillator frequency which is set by CLOCK_InitWdtOsc, and it is returned by CLOCK_GetWdtOscFreq.
volatile uint32_t g_Ext_Clk_Freq |
This variable is used to store the external clock frequency which is include external oscillator clock and external clk in clock frequency value, it is set by CLOCK_InitExtClkin when CLK IN is used as external clock or by CLOCK_InitSysOsc when external oscillator is used as external clock ,and it is returned by CLOCK_GetExtClkFreq.