175 lines
5.5 KiB
C
175 lines
5.5 KiB
C
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/*
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* Copyright 2017-2019 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_dac.h"
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#include "fsl_clock.h"
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.lpc_dac"
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#endif
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/* Array of GPIO peripheral base address. */
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static DAC_Type *const s_dacBases[] = DAC_BASE_PTRS;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Array of GPIO clock name. */
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static const clock_ip_name_t s_dacClocks[] = DAC_CLOCKS;
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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#if !(defined(FSL_FEATURE_DAC_HAS_NO_RESET) && FSL_FEATURE_DAC_HAS_NO_RESET)
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static const reset_ip_name_t s_dacResets[] = DAC_RSTS_N;
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#endif
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Gets the DAC instance according to the DAC base.
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*
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* @param base DAC peripheral base pointer.
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* @retval DAC instance.
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*/
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static uint32_t DAC_GetInstance(DAC_Type *base);
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/*******************************************************************************
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* Code
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******************************************************************************/
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static uint32_t DAC_GetInstance(DAC_Type *base)
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{
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uint32_t instance;
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ARRAY_SIZE(s_dacBases); instance++)
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{
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if (s_dacBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ARRAY_SIZE(s_dacBases));
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return instance;
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}
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/*!
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* brief Initialize the DAC module.
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*
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* param base DAC peripheral base address.
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* param config The pointer to configuration structure. Please refer to "dac_config_t" structure.
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*/
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void DAC_Init(DAC_Type *base, const dac_config_t *config)
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{
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assert(config != NULL);
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Enable clock. */
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CLOCK_EnableClock(s_dacClocks[DAC_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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#if !(defined(FSL_FEATURE_DAC_HAS_NO_RESET) && FSL_FEATURE_DAC_HAS_NO_RESET)
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/* Reset the DAC module */
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RESET_PeripheralReset(s_dacResets[DAC_GetInstance(base)]);
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#endif
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base->CR &= ~DAC_CR_BIAS_MASK;
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base->CR |= DAC_CR_BIAS(config->settlingTime);
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}
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/*!
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* brief De-Initialize the DAC module.
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*
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* param base DAC peripheral base address.
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*/
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void DAC_Deinit(DAC_Type *base)
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{
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Disable the clock. */
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CLOCK_DisableClock(s_dacClocks[DAC_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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/*!
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* brief Initializes the DAC user configuration structure.
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*
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* This function initializes the user configuration structure to a default value. The default values are as follows.
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* code
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* config->settlingTime = kDAC_SettlingTimeIs1us;
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* endcode
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* param config Pointer to the configuration structure. See "dac_config_t".
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*/
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void DAC_GetDefaultConfig(dac_config_t *config)
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{
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assert(config != NULL);
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/* Initializes the configure structure to zero. */
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(void)memset(config, 0, sizeof(*config));
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config->settlingTime = kDAC_SettlingTimeIs1us;
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}
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/*!
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* brief Enable/Diable double-buffering feature. Notice: Disabling the double-buffering feature will disable counter
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* opreation.
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* If double-buffering feature is disabled, any writes to the CR address will go directly to the CR register.
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* If double-buffering feature is enabled, any write to the CR register will only load the pre-buffer,
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* which shares its register address with the CR register. The CR itself will be loaded from the pre-buffer
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* whenever the counter reaches zero and the DMA request is set.
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*
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* param base DAC peripheral base address.
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* param enable Enable or disable the feature.
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*/
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void DAC_EnableDoubleBuffering(DAC_Type *base, bool enable)
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{
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if (enable)
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{
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base->CTRL |= DAC_CTRL_DBLBUF_ENA_MASK;
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base->CTRL |= DAC_CTRL_CNT_ENA_MASK;
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}
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else
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{
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base->CTRL &= ~DAC_CTRL_DBLBUF_ENA_MASK;
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base->CTRL &= ~DAC_CTRL_CNT_ENA_MASK;
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}
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}
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/*!
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* brief Write DAC output value into CR register or pre-buffer. The DAC output voltage is VALUE*((VREFP)/1024).
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*
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* param base DAC peripheral base address.
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* param value Setting the value for items in the buffer. 10-bits are available.
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*/
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void DAC_SetBufferValue(DAC_Type *base, uint32_t value)
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{
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assert(value < 1024U);
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base->CR = (base->CR & ~DAC_CR_VALUE_MASK) | DAC_CR_VALUE(value);
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}
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/*!
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* brief Write DAC counter value into CNTVAL register.
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* When the counter is enabled bit, the 16-bit counter will begin counting down, at the rate selected by PCLK,
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* from the value programmed into the DACCNTVAL register. The counter is decremented Each time the counter
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* reaches zero, the counter will be reloaded by the value of DACCNTVAL and the DMA request bit INT_DMA_REQ will be set
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* in hardware.
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*
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* param base DAC peripheral basic address.
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* param value Setting the value for items in the counter. 16-bits are available.
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*/
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void DAC_SetCounterValue(DAC_Type *base, uint32_t value)
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{
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assert(value < 65536U);
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base->CNTVAL &= ~DAC_CNTVAL_VALUE_MASK;
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base->CNTVAL |= DAC_CNTVAL_VALUE(value);
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}
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