NXP Semiconductors NXP LPC845 LPC 1.6 LPC845 NXP Microcontroller Copyright 2016-2020 NXP\n All rights reserved.\n SPDX-License-Identifier: BSD-3-Clause CM0PLUS r0p0 little false false true 2 false 8 32 WWDT LPC84x Windowed Watchdog Timer (WWDT) 0x40000000 0 0x1C registers WDT 12 MOD Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. 0 32 read-write 0 0x3F WDEN Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the watchdog timer will run permanently. 0 1 read-write 0 Stop. The watchdog timer is stopped. #0 1 Run. The watchdog timer is running. #1 WDRESET Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. 1 1 read-write 0 Interrupt. A watchdog time-out will not cause a chip reset. #0 1 Reset. A watchdog time-out will cause a chip reset. #1 WDTOF Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a chip reset if WDRESET = 1. 2 1 read-write WDINT Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the WARNINT value is equal to the value of the TV register. This can occur if the value of WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0. 3 1 read-write WDPROTECT Watchdog update mode. This bit can be set once by software and is only cleared by a reset. 4 1 read-write 0 Flexible. The watchdog time-out value (TC) can be changed at any time. #0 1 Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. #1 LOCK Once this bit is set to one and a watchdog feed is performed, disabling or powering down the watchdog oscillator is prevented by hardware. This bit can be set once by software and is only cleared by any reset. 5 1 read-write TC Watchdog timer constant register. This 24-bit register determines the time-out value. 0x4 32 read-write 0xFF 0xFFFFFF COUNT Watchdog time-out value. 0 24 read-write FEED Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. 0x8 32 write-only 0 0 FEED Feed value should be 0xAA followed by 0x55. 0 8 write-only TV Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. 0xC 32 read-only 0xFF 0xFFFFFF COUNT Counter timer value. 0 24 read-only WARNINT Watchdog Warning Interrupt compare value. 0x14 32 read-write 0 0x3FF WARNINT Watchdog warning interrupt compare value. 0 10 read-write WINDOW Watchdog Window compare value. 0x18 32 read-write 0xFFFFFF 0xFFFFFF WINDOW Watchdog window value. 0 24 read-write MRT0 LPC84x Multi-Rate Timer (MRT) 0x40004000 0 0xFC registers MRT0 10 INTVAL0 MRT Time interval value register. This value is loaded into the TIMER register. 0 32 read-write 0 0xFFFFFFFF IVALUE Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval. 0 31 read-write LOAD Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0. 31 1 read-write 0 No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected. #0 1 Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running. #1 TIMER0 MRT Timer register. This register reads the value of the down-counter. 0x4 32 read-only 0xFFFFFF 0x7FFFFFFF VALUE Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF). 0 31 read-only CTRL0 MRT Control register. This register controls the MRT modes. 0x8 32 read-write 0 0x7 INTEN Enable the TIMERn interrupt. 0 1 read-write 0 Disabled. TIMERn interrupt is disabled. #0 1 Enabled. TIMERn interrupt is enabled. #1 MODE Selects timer mode. 1 2 read-write 00 Repeat interrupt mode. #00 01 One-shot interrupt mode. #01 10 One-shot stall mode. #10 STAT0 MRT Status register. 0xC 32 read-write 0 0x3 INTFLAG Monitors the interrupt flag. 0 1 read-write 0 No pending interrupt. Writing a zero is equivalent to no operation. #0 1 Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. #1 RUN Indicates the state of TIMERn. This bit is read-only. 1 1 read-write 0 Idle state. TIMERn is stopped. #0 1 Running. TIMERn is running. #1 INTVAL1 MRT Time interval value register. This value is loaded into the TIMER register. 0x10 32 read-write 0 0xFFFFFFFF IVALUE Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval. 0 31 read-write LOAD Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0. 31 1 read-write 0 No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected. #0 1 Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running. #1 TIMER1 MRT Timer register. This register reads the value of the down-counter. 0x14 32 read-only 0xFFFFFF 0x7FFFFFFF VALUE Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF). 0 31 read-only CTRL1 MRT Control register. This register controls the MRT modes. 0x18 32 read-write 0 0x7 INTEN Enable the TIMERn interrupt. 0 1 read-write 0 Disabled. TIMERn interrupt is disabled. #0 1 Enabled. TIMERn interrupt is enabled. #1 MODE Selects timer mode. 1 2 read-write 00 Repeat interrupt mode. #00 01 One-shot interrupt mode. #01 10 One-shot stall mode. #10 STAT1 MRT Status register. 0x1C 32 read-write 0 0x3 INTFLAG Monitors the interrupt flag. 0 1 read-write 0 No pending interrupt. Writing a zero is equivalent to no operation. #0 1 Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. #1 RUN Indicates the state of TIMERn. This bit is read-only. 1 1 read-write 0 Idle state. TIMERn is stopped. #0 1 Running. TIMERn is running. #1 INTVAL2 MRT Time interval value register. This value is loaded into the TIMER register. 0x20 32 read-write 0 0xFFFFFFFF IVALUE Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval. 0 31 read-write LOAD Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0. 31 1 read-write 0 No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected. #0 1 Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running. #1 TIMER2 MRT Timer register. This register reads the value of the down-counter. 0x24 32 read-only 0xFFFFFF 0x7FFFFFFF VALUE Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF). 0 31 read-only CTRL2 MRT Control register. This register controls the MRT modes. 0x28 32 read-write 0 0x7 INTEN Enable the TIMERn interrupt. 0 1 read-write 0 Disabled. TIMERn interrupt is disabled. #0 1 Enabled. TIMERn interrupt is enabled. #1 MODE Selects timer mode. 1 2 read-write 00 Repeat interrupt mode. #00 01 One-shot interrupt mode. #01 10 One-shot stall mode. #10 STAT2 MRT Status register. 0x2C 32 read-write 0 0x3 INTFLAG Monitors the interrupt flag. 0 1 read-write 0 No pending interrupt. Writing a zero is equivalent to no operation. #0 1 Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. #1 RUN Indicates the state of TIMERn. This bit is read-only. 1 1 read-write 0 Idle state. TIMERn is stopped. #0 1 Running. TIMERn is running. #1 INTVAL3 MRT Time interval value register. This value is loaded into the TIMER register. 0x30 32 read-write 0 0xFFFFFFFF IVALUE Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval. 0 31 read-write LOAD Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0. 31 1 read-write 0 No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected. #0 1 Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running. #1 TIMER3 MRT Timer register. This register reads the value of the down-counter. 0x34 32 read-only 0xFFFFFF 0x7FFFFFFF VALUE Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF). 0 31 read-only CTRL3 MRT Control register. This register controls the MRT modes. 0x38 32 read-write 0 0x7 INTEN Enable the TIMERn interrupt. 0 1 read-write 0 Disabled. TIMERn interrupt is disabled. #0 1 Enabled. TIMERn interrupt is enabled. #1 MODE Selects timer mode. 1 2 read-write 00 Repeat interrupt mode. #00 01 One-shot interrupt mode. #01 10 One-shot stall mode. #10 STAT3 MRT Status register. 0x3C 32 read-write 0 0x3 INTFLAG Monitors the interrupt flag. 0 1 read-write 0 No pending interrupt. Writing a zero is equivalent to no operation. #0 1 Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. #1 RUN Indicates the state of TIMERn. This bit is read-only. 1 1 read-write 0 Idle state. TIMERn is stopped. #0 1 Running. TIMERn is running. #1 IDLE_CH Idle channel register. This register returns the number of the first idle channel. 0xF4 32 read-only 0 0xF0 CHAN Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is positioned such that it can be used as an offset from the MRT base address in order to access the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See text above for more details. 4 4 read-only IRQ_FLAG Global interrupt flag register 0xF8 32 read-write 0 0xF GFLAG0 Monitors the interrupt flag of TIMER0. 0 1 read-write 0 No pending interrupt. Writing a zero is equivalent to no operation. #0 1 Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. #1 GFLAG1 Monitors the interrupt flag of TIMER1. See description of channel 0. 1 1 read-write GFLAG2 Monitors the interrupt flag of TIMER2. See description of channel 0. 2 1 read-write GFLAG3 Monitors the interrupt flag of TIMER3. See description of channel 0. 3 1 read-write WKT LPC84x Wake Up Timer(WKT) 0x40008000 0 0x10 registers WKT 15 CTRL Self wake-up timer control register. 0 32 read-write 0 0xF CLKSEL Select the self wake-up timer clock source. Remark: This bit only has an effect if the SEL_EXTCLK bit is not set. 0 1 read-write 0 Divided FRO clock. This clock runs at 750 kHz and provides time-out periods of up to approximately 95 minutes in 1.33 us increments. Remark: This clock is not available in not available in Deep-sleep, power-down, deep power-down modes. Do not select this option if the timer is to be used to wake up from one of these modes. #0 1 This is the (nominally) 10 kHz clock and provides time-out periods of up to approximately 119 hours in 100 us increments. The accuracy of this clock is limited to +/- 40 % over temperature and processing. Remark: This clock is available in all power modes. Prior to use, the low-power oscillator must be enabled. The oscillator must also be set to remain active in Deep power-down if needed. #1 ALARMFLAG Wake-up or alarm timer flag. 1 1 read-write 0 No time-out. The self wake-up timer has not timed out. Writing a 0 to has no effect. #0 1 Time-out. The self wake-up timer has timed out. This flag generates an interrupt request which can wake up the part from any reduced power mode including Deep power-down if the clock source is the low power oscillator. Writing a 1 clears this status bit. #1 CLEARCTR Clears the self wake-up timer. 2 1 read-write 0 No effect. Reading this bit always returns 0. #0 1 Clear the counter. Counting is halted until a new count value is loaded. #1 SEL_EXTCLK Select external or internal clock source for the self wake-up timer. The internal clock source is selected by the CLKSEL bit in this register if SET_EXTCLK is set to internal. 3 1 read-write 0 Internal. The clock source is the internal clock selected by the CLKSEL bit. #0 1 External. The self wake-up timer uses the external WKTCLKIN pin. #1 COUNT Counter register. 0xC 32 read-write 0 0 VALUE A write to this register pre-loads start count value into the timer and starts the count-down sequence. A read reflects the current value of the timer. 0 32 read-write SWM0 LPC84x SWM 0x4000C000 0 0x1C8 registers PINASSIGN0 Pin assign register 0. Assign movable functions U0_TXD, U0_RXD, U0_RTS, U0_CTS. SWM0 0 32 read-write 0xFFFFFFFF 0xFFFFFFFF U0_TXD_O U0_TXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35) . 0 8 read-write U0_RXD_I U0_RXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 8 8 read-write U0_RTS_O U0_RTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 16 8 read-write U0_CTS_I U0_CTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 24 8 read-write PINASSIGN_DATA0 Pin assign register SWM0 0 32 read-write 0xFFFFFFFF 0xFFFFFFFF DATA0 T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 0 8 read-write DATA1 T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 8 8 read-write DATA2 T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 16 8 read-write DATA3 T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 24 8 read-write PINASSIGN1 Pin assign register 1. Assign movable functions U0_SCLK, U1_TXD, U1_RXD, U1_RTS. SWM0 0x4 32 read-write 0xFFFFFFFF 0xFFFFFFFF U0_SCLK_IO U0_SCLK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 0 8 read-write U1_TXD_O U1_TXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 8 8 read-write U1_RXD_I U1_RXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 16 8 read-write U1_RTS_O U1_RTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 24 8 read-write PINASSIGN_DATA1 Pin assign register SWM0 0x4 32 read-write 0xFFFFFFFF 0xFFFFFFFF DATA0 T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 0 8 read-write DATA1 T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 8 8 read-write DATA2 T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 16 8 read-write DATA3 T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 24 8 read-write PINASSIGN2 Pin assign register 2. Assign movable functions U1_CTS, U1_SCLK, U2_TXD, U2_RXD. SWM0 0x8 32 read-write 0xFFFFFFFF 0xFFFFFFFF U1_CTS_I U1_CTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 0 8 read-write U1_SCLK_IO U1_SCLK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 8 8 read-write U2_TXD_O U2_TXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 16 8 read-write U2_RXD_I U2_RXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 24 8 read-write PINASSIGN_DATA2 Pin assign register SWM0 0x8 32 read-write 0xFFFFFFFF 0xFFFFFFFF DATA0 T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 0 8 read-write DATA1 T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 8 8 read-write DATA2 T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 16 8 read-write DATA3 T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 24 8 read-write PINASSIGN3 Pin assign register 3. Assign movable function U2_RTS, U2_CTS, U2_SCLK, SPI0_SCK. SWM0 0xC 32 read-write 0xFFFFFFFF 0xFFFFFFFF U2_RTS_O U2_RTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 0 8 read-write U2_CTS_I U2_CTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 8 8 read-write U2_SCLK_IO U2_SCLK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 16 8 read-write SPI0_SCK_IO SPI0_SCK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 24 8 read-write PINASSIGN_DATA3 Pin assign register SWM0 0xC 32 read-write 0xFFFFFFFF 0xFFFFFFFF DATA0 T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 0 8 read-write DATA1 T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 8 8 read-write DATA2 T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 16 8 read-write DATA3 T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 24 8 read-write PINASSIGN4 Pin assign register 4. Assign movable functions SPI0_MOSI, SPI0_MISO, SPI0_SSEL0, SPI0_SSEL1. SWM0 0x10 32 read-write 0xFFFFFFFF 0xFFFFFFFF SPI0_MOSI_IO SPI0_MOSI function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 0 8 read-write SPI0_MISO_IO SPI0_MISIO function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 8 8 read-write SPI0_SSEL0_IO SPI0_SSEL0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 16 8 read-write SPI0_SSEL1_IO SPI0_SSEL1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 24 8 read-write PINASSIGN_DATA4 Pin assign register SWM0 0x10 32 read-write 0xFFFFFFFF 0xFFFFFFFF DATA0 T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 0 8 read-write DATA1 T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 8 8 read-write DATA2 T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 16 8 read-write DATA3 T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 24 8 read-write PINASSIGN5 Pin assign register 5. Assign movable functions SPI0_SSEL2, SPI0_SSEL3, SPI1_SCK, SPI1_MOSI SWM0 0x14 32 read-write 0xFFFFFFFF 0xFFFFFFFF SPI0_SSEL2_IO SPI0_SSEL2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 0 8 read-write SPI0_SSEL3_IO SPI0_SSEL3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 8 8 read-write SPI1_SCK_IO SPI1_SCK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 16 8 read-write SPI1_MOSI_IO SPI1_MOSI function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 24 8 read-write PINASSIGN_DATA5 Pin assign register SWM0 0x14 32 read-write 0xFFFFFFFF 0xFFFFFFFF DATA0 T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 0 8 read-write DATA1 T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 8 8 read-write DATA2 T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 16 8 read-write DATA3 T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 24 8 read-write PINASSIGN6 Pin assign register 6. Assign movable functions SPI1_MISO, SPI1_SSEL0, SPI1_SSEL1, SCT0_IN0. SWM0 0x18 32 read-write 0xFFFFFFFF 0xFFFFFFFF SPI1_MISO_IO SPI1_MISO function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 0 8 read-write SPI1_SSEL0_IO SPI1_SSEL0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 8 8 read-write SPI1_SSEL1_IO SPI1_SSEL1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 16 8 read-write SCT0_GPIO_IN_A_I SCT0_GPIO_IN_A function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 24 8 read-write PINASSIGN_DATA6 Pin assign register SWM0 0x18 32 read-write 0xFFFFFFFF 0xFFFFFFFF DATA0 T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 0 8 read-write DATA1 T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 8 8 read-write DATA2 T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 16 8 read-write DATA3 T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 24 8 read-write PINASSIGN7 Pin assign register 7. Assign movable functions SCT_IN1, SCT_IN2, SCT_IN3, SCT_OUT0. SWM0 0x1C 32 read-write 0xFFFFFFFF 0xFFFFFFFF SCT0_GPIO_IN_B_I SCT0_GPIO_IN_B function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 0 8 read-write SCT0_GPIO_IN_C_I SCT0_GPIO_IN_C function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 8 8 read-write SCT0_GPIO_IN_D_I SCT0_GPIO_IN_D function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 16 8 read-write SCT_OUT0_O SCT_OUT0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 24 8 read-write PINASSIGN_DATA7 Pin assign register SWM0 0x1C 32 read-write 0xFFFFFFFF 0xFFFFFFFF DATA0 T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 0 8 read-write DATA1 T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 8 8 read-write DATA2 T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 16 8 read-write DATA3 T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 24 8 read-write PINASSIGN8 Pin assign register 8. Assign movable functions SCT_OUT1, SCT_OUT2, SCT_OUT3, SCT_OUT4. SWM0 0x20 32 read-write 0xFFFFFFFF 0xFFFFFFFF SCT_OUT1_O SCT_OUT1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 0 8 read-write SCT_OUT2_O SCT_OUT2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 8 8 read-write SCT_OUT3_O SCT_OUT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 16 8 read-write SCT_OUT4_O SCT_OUT4 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 24 8 read-write PINASSIGN_DATA8 Pin assign register SWM0 0x20 32 read-write 0xFFFFFFFF 0xFFFFFFFF DATA0 T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 0 8 read-write DATA1 T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 8 8 read-write DATA2 T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 16 8 read-write DATA3 T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 24 8 read-write PINASSIGN9 Pin assign register 9. Assign movable functions SCT_OUT5, SCT_OUT6, I2C1_SDA, I2C1_SCL. SWM0 0x24 32 read-write 0xFFFFFFFF 0xFFFFFFFF SCT_OUT5_O SCT_OUT5 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 0 8 read-write SCT_OUT6_O SCT_OUT6 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 8 8 read-write I2C1_SDA_IO I2C1_SDA function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 16 8 read-write I2C1_SCL_IO I2C1_SCL function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 24 8 read-write PINASSIGN_DATA9 Pin assign register SWM0 0x24 32 read-write 0xFFFFFFFF 0xFFFFFFFF DATA0 T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 0 8 read-write DATA1 T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 8 8 read-write DATA2 T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 16 8 read-write DATA3 T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 24 8 read-write PINASSIGN10 Pin assign register 10. Assign movable functions I2C2_SDA, I2C2_SCL, I2C3_SDA, I2C3_SCL. SWM0 0x28 32 read-write 0xFFFFFFFF 0xFFFFFFFF I2C2_SDA_IO I2C1_SDA function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 0 8 read-write I2C2_SCL_IO I2C1_SCL function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 8 8 read-write I2C3_SDA_IO I2C3_SDA function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 16 8 read-write I2C3_SCL_IO I2C3_SCL function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 24 8 read-write PINASSIGN_DATA10 Pin assign register SWM0 0x28 32 read-write 0xFFFFFFFF 0xFFFFFFFF DATA0 T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 0 8 read-write DATA1 T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 8 8 read-write DATA2 T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 16 8 read-write DATA3 T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 24 8 read-write PINASSIGN11 Pin assign register 11. Assign movable functions COMP0_OUT, CLKOUT, GPIOINT_BMATCH, UART3_TXD SWM0 0x2C 32 read-write 0xFFFFFFFF 0xFFFFFFFF COMP0_OUT_O COMP0_OUT function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 0 8 read-write CLKOUT_O CLKOUT function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 8 8 read-write GPIO_INT_BMAT_O GPIO_INT_BMAT function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 16 8 read-write UART3_TXD UART3_TXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 24 8 read-write PINASSIGN_DATA11 Pin assign register SWM0 0x2C 32 read-write 0xFFFFFFFF 0xFFFFFFFF DATA0 T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 0 8 read-write DATA1 T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 8 8 read-write DATA2 T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 16 8 read-write DATA3 T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 24 8 read-write PINASSIGN12 Pin assign register 12. Assign movable functions UART3_RXD, UART3_SCLK, UART4_TXD, UART4_RXD. SWM0 0x30 32 read-write 0xFFFFFFFF 0xFFFFFFFF UART3_RXD UART3_RXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 0 8 read-write UART3_SCLK UART3_SCLK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 8 8 read-write UART4_TXD UART4_TXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 16 8 read-write UART4_RXD UART4_TXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 24 8 read-write PINASSIGN_DATA12 Pin assign register SWM0 0x30 32 read-write 0xFFFFFFFF 0xFFFFFFFF DATA0 T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 0 8 read-write DATA1 T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 8 8 read-write DATA2 T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 16 8 read-write DATA3 T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 24 8 read-write PINASSIGN13 Pin assign register 13. Assign movable functions UART4_SCLK, T0_MAT0, T0_MAT1, T0_MAT2. SWM0 0x34 32 read-write 0xFFFFFFFF 0xFFFFFFFF UART4_SCLK UART4_SCLK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 0 8 read-write T0_MAT0 T0_MAT0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 8 8 read-write T0_MAT1 T0_MAT1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 16 8 read-write T0_MAT2 T0_MAT2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 24 8 read-write PINASSIGN_DATA13 Pin assign register SWM0 0x34 32 read-write 0xFFFFFFFF 0xFFFFFFFF DATA0 T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 0 8 read-write DATA1 T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 8 8 read-write DATA2 T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 16 8 read-write DATA3 T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 24 8 read-write PINASSIGN14 Pin assign register 14. Assign movable functions T0_MAT3, T0_CAP0, T0_CAP1, T0_CAP2. SWM0 0x38 32 read-write 0xFFFFFFFF 0xFFFFFFFF T0_MAT3 T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 0 8 read-write T0_CAP0 T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 8 8 read-write T0_CAP1 T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 16 8 read-write T0_CAP2 T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 24 8 read-write PINASSIGN_DATA14 Pin assign register SWM0 0x38 32 read-write 0xFFFFFFFF 0xFFFFFFFF DATA0 T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 0 8 read-write DATA1 T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 8 8 read-write DATA2 T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 16 8 read-write DATA3 T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35). 24 8 read-write PINENABLE0 Pin enable register 0. Enables fixed-pin functions ACMP_I0, ACMP_I1, SWCLK, SWDIO, XTALIN, XTALOUT, RESET, CLKIN, VDDCMP and so on. 0x1C0 32 read-write 0xFFFFFD9F 0xFFFFFFFF ACMP_I1 ACMP_I1 function select. 0 1 read-write 0 ACMP_I1 enabled on pin PIO0_00. #0 1 ACMP_I1 disabled. #1 ACMP_I2 ACMP_I2 function select. 1 1 read-write 0 ACMP_I2 enabled on pin PIO0_1. #0 1 ACMP_I2 disabled. #1 ACMP_I3 ACMP_I3 function select. 2 1 read-write 0 ACMP_I3 enabled on pin PIO0_14. #0 1 ACMP_I3 disabled. #1 ACMP_I4 ACMP_I4 function select. 3 1 read-write 0 ACMP_I4 enabled on pin PIO0_23. #0 1 ACMP_I4 disabled. #1 ACMP_I5 ACMP_I5 function select. 4 1 read-write 0 ACMP_I5 enabled on pin PIO0_30. #0 1 ACMP_I5 disabled. #1 SWCLK SWCLK function select. 5 1 read-write 0 SWCLK enabled on pin PIO0_3. #0 1 SWCLK disabled. #1 SWDIO SWDIO function select. 6 1 read-write 0 SWDIO enabled on pin PIO0_2. #0 1 SWDIO disabled. #1 XTALIN XTALIN function select. 7 1 read-write 0 XTALIN enabled on pin PIO0_8. #0 1 XTALIN disabled. #1 XTALOUT XTALOUT function select. 8 1 read-write 0 XTALOUT enabled on pin PIO0_9. #0 1 XTALOUT disabled. #1 RESETN RESETN function select. 9 1 read-write 0 RESETN enabled on pin PIO0_5. #0 1 RESETN disabled. #1 CLKIN CLKIN function select. 10 1 read-write 0 CLKIN enabled on pin PIO0_1. #0 1 CLKIN disabled. #1 VDDCMP VDDCMP function select. 11 1 read-write 0 VDDCMP enabled on pin PIO0_6. #0 1 VDDCMP disabled. #1 I2C0_SDA I2C0_SDA function select. 12 1 read-write 0 I2C0_SDA enabled on pin PIO0_11. #0 1 I2C0_SDA disabled. #1 I2C0_SCL I2C0_SCL function select. 13 1 read-write 0 I2C0_SCL enabled on pin PIO0_10. #0 1 I2C0_SCL disabled. #1 ADC_0 ADC_0 function select. 14 1 read-write 0 ADC_0 enabled on pin PIO0_7. #0 1 ADC_0 disabled. #1 ADC_1 ADC_1 function select. 15 1 read-write 0 ADC_1 enabled on pin PIO0_6. #0 1 ADC_1 disabled. #1 ADC_2 ADC_2 function select. 16 1 read-write 0 ADC_2 enabled on pin PIO0_14. #0 1 ADC_2 disabled. #1 ADC_3 ADC_3 function select. 17 1 read-write 0 ADC_3 enabled on pin PIO0_23. #0 1 ADC_3 disabled. #1 ADC_4 ADC_4 function select. 18 1 read-write 0 ADC_4 enabled on pin PIO0_22. #0 1 ADC_4 disabled. #1 ADC_5 ADC_5 function select. 19 1 read-write 0 ADC_5 enabled on pin PIO0_21. #0 1 ADC_5 disabled. #1 ADC_6 ADC_6 function select. 20 1 read-write 0 ADC_6 enabled on pin PIO0_20. #0 1 ADC_6 disabled. #1 ADC_7 ADC_7 function select. 21 1 read-write 0 ADC_7 enabled on pin PIO0_19. #0 1 ADC_7 disabled. #1 ADC_8 ADC_8 function select. 22 1 read-write 0 ADC_8 enabled on pin PIO0_18. #0 1 ADC_8 disabled. #1 ADC_9 ADC_9 function select. 23 1 read-write 0 ADC_9 enabled on pin PIO0_17. #0 1 ADC_9 disabled. #1 ADC_10 ADC_10 function select. 24 1 read-write 0 ADC_10 enabled on pin PIO0_13. #0 1 ADC_10 disabled. #1 ADC_11 ADC_11 function select. 25 1 read-write 0 ADC_11 enabled on pin PIO0_4. #0 1 ADC_11 disabled. #1 DACOUT0 DACOUT0 function select. 26 1 read-write 0 DACOUT0 enabled on pin PIO0_17. #0 1 DACOUT0 disabled. #1 DACOUT1 DACOUT1 function select. 27 1 read-write 0 DACOUT1 enabled on pin PIO0_29. #0 1 DACOUT1 disabled. #1 CAPT_X0 CAPT_X0 function select. 28 1 read-write 0 CAPT_X0 enabled on pin PIO0_31. #0 1 CAPT_X0 disabled. #1 CAPT_X1 CAPT_X1 function select. 29 1 read-write 0 CAPT_X1 enabled on pin PIO1_0. #0 1 CAPT_X1 disabled. #1 CAPT_X2 CAPT_X2 function select. 30 1 read-write 0 CAPT_X2 enabled on pin PIO1_1. #0 1 CAPT_X2 disabled. #1 CAPT_X3 CAPT_X3 function select. 31 1 read-write 0 CAPT_X3 enabled on pin PIO1_2. #0 1 CAPT_X3 disabled. #1 PINENABLE1 Pin enable register 1. Enables fixed-pin functions CAPT_X4, CAPT_X5, CAPT_X6, CAPT_X7, CAPT_X8, CAPT_X4, CAPT_YL and CAPT_YH. 0x1C4 32 read-write 0x1F 0x7F CAPT_X4 CAPT_X4 function select. 0 1 read-write 0 CAPT_X4 enabled on pin PIO1_3. #0 1 CAPT_X4 disabled. #1 CAPT_X5 CAPT_X5 function select. 1 1 read-write 0 CAPT_X5 enabled on pin PIO1_4. #0 1 CAPT_X5 disabled. #1 CAPT_X6 CAPT_X6 function select. 2 1 read-write 0 CAPT_X6 enabled on pin PIO1_5. #0 1 CAPT_X6 disabled. #1 CAPT_X7 CAPT_X7 function select. 3 1 read-write 0 CAPT_X7 enabled on pin PIO1_6. #0 1 CAPT_X7 disabled. #1 CAPT_X8 CAPT_X8 function select. 4 1 read-write 0 CAPT_X8 enabled on pin PIO1_7. #0 1 CAPT_X8 disabled. #1 CAPT_YL CAPT_YL function select. 5 1 read-write 0 CAPT_YL enabled on pin PIO1_8. #0 1 CAPT_YL disabled. #1 CAPT_YH CAPT_YH function select. 6 1 read-write 0 CAPT_YH enabled on pin PIO1_9. #0 1 CAPT_YH disabled. #1 DAC0 LPC84x 10-bit DAC controller (DAC) DAC 0x40014000 0 0xC registers DAC0 2 CR D/A Converter Register. This register contains the digital value to be converted to analog and a power control bit. 0 32 read-write 0 0x1FFC0 VALUE After the selected settling time after this field is written with a new VALUE, the voltage on the DAC_OUT pin (with respect to VSSA) is VALUE (VREFP - VREFN)/1024 + VREFN. 6 10 read-write BIAS The settling time of the DAC 16 1 read-write 0 The settling time of the DAC is 1 us max, and the maximum current is 700 uA. This allows a maximum update rate of 1 MHz. #0 1 The settling time of the DAC is 2.5 us and the maximum current is 350 uA. This allows a maximum update rate of 400 kHz. #1 CTRL DAC Control register. This register controls DMA and timer operation. 0x4 32 read-write 0 0xF INT_DMA_REQ DMA request 0 1 read-write 0 This bit is cleared on any write to the DACR register. #0 1 This bit is set by hardware when the timer times out. #1 DBLBUF_ENA dacr double buffer 1 1 read-write 0 DACR double-buffering is disabled. #0 1 When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter. #1 CNT_ENA time-out counter operation 2 1 read-write 0 Time-out counter operation is disabled. #0 1 Time-out counter operation is enabled. #1 DMA_ENA DMA access 3 1 read-write 0 DMA access is disabled. #0 1 DMA Burst Request Input 7 is enabled for the DAC #1 CNTVAL DAC Counter Value register. This register contains the reload value for the DAC DMA/Interrupt timer. 0x8 32 read-write 0 0xFFFF VALUE 16-bit reload value for the DAC interrupt/DMA timer. 0 16 read-write DAC1 LPC84x 10-bit DAC controller (DAC) DAC 0x40018000 0 0xC registers PIN_INT5_DAC1 29 CR D/A Converter Register. This register contains the digital value to be converted to analog and a power control bit. 0 32 read-write 0 0x1FFC0 VALUE After the selected settling time after this field is written with a new VALUE, the voltage on the DAC_OUT pin (with respect to VSSA) is VALUE (VREFP - VREFN)/1024 + VREFN. 6 10 read-write BIAS The settling time of the DAC 16 1 read-write 0 The settling time of the DAC is 1 us max, and the maximum current is 700 uA. This allows a maximum update rate of 1 MHz. #0 1 The settling time of the DAC is 2.5 us and the maximum current is 350 uA. This allows a maximum update rate of 400 kHz. #1 CTRL DAC Control register. This register controls DMA and timer operation. 0x4 32 read-write 0 0xF INT_DMA_REQ DMA request 0 1 read-write 0 This bit is cleared on any write to the DACR register. #0 1 This bit is set by hardware when the timer times out. #1 DBLBUF_ENA dacr double buffer 1 1 read-write 0 DACR double-buffering is disabled. #0 1 When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter. #1 CNT_ENA time-out counter operation 2 1 read-write 0 Time-out counter operation is disabled. #0 1 Time-out counter operation is enabled. #1 DMA_ENA DMA access 3 1 read-write 0 DMA access is disabled. #0 1 DMA Burst Request Input 7 is enabled for the DAC #1 CNTVAL DAC Counter Value register. This register contains the reload value for the DAC DMA/Interrupt timer. 0x8 32 read-write 0 0xFFFF VALUE 16-bit reload value for the DAC interrupt/DMA timer. 0 16 read-write ADC0 LPC84x 12-bit ADC controller (ADC) 0x4001C000 0 0x70 registers ADC0_SEQA 16 ADC0_SEQB 17 ADC0_THCMP 18 ADC0_OVR 19 CTRL ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. 0 32 read-write 0 0x400005FF CLKDIV In synchronous mode only, the system clock is divided by this value plus one to produce the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically, software should program the smallest value in this field that yields this maximum clock rate or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. This field is ignored in the asynchronous operating mode. 0 8 read-write ASYNMODE Select clock mode. 8 1 read-write 0 Synchronous mode. The ADC clock is derived from the system clock based on the divide value selected in the CLKDIV field. The ADC clock will be started in a controlled fashion in response to a trigger to eliminate any uncertainty in the launching of an ADC conversion in response to any synchronous (on-chip) trigger. In Synchronous mode with the SYNCBYPASS bit (in a sequence control register) set, sampling of the ADC input and start of conversion will initiate 2 system clocks after the leading edge of a (synchronous) trigger pulse. #0 1 Asynchronous mode. The ADC clock is based on the output of the ADC clock divider ADCCLKSEL in the SYSCON block. #1 LPWRMODE The low-power ADC mode 10 1 read-write 0 The low-power ADC mode is disabled. The analog circuitry remains activated even when no conversions are requested. #0 1 The low-power ADC mode is enabled. The analog circuitry is automatically powered-down when no conversions are taking place. When any (hardware or software) triggering event is detected, the analog circuitry is enabled. After the required start-up time, the requested conversion will be launched. Once the conversion completes, the analog-circuitry will again be powered-down provided no further conversions are pending. Using this mode can save an appreciable amount of current (approximately 2.5 mA) when conversions are required relatively infrequently. The penalty for using this mode is an approximately FIFTEEN ADC CLOCK delay (30 clocks in 10-bit mode), based on the frequency specified in the CLKDIV field, from the time the trigger event occurs until sampling of the A/D input commences. Note: This mode will NOT power-up the A/D if the ADC_ENA bit is low. #1 CALMODE Writing a '1' to this bit will initiate a sef-calibration cycle. This bit will be automatically cleared by hardware after the calibration cycle is complete. Note: Other bits of this register may be written to concurrently with setting this bit, however once this bit has been set no further writes to this register are permitted unitl the full calibration cycle has ended. 30 1 read-write SEQ_CTRLA ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. 0x8 32 read-write 0 0xFC0FFFFF CHANNELS Selects which one or more of the ADC channels will be sampled and converted when this sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 and so forth. When this conversion sequence is triggered, either by a hardware trigger or via software command, ADC conversions will be performed on each enabled channel, in sequence, beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31) is LOW. It is allowed to change this field and set bit 31 in the same write. 0 12 read-write TRIGGER Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field. See Table 476. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write. 12 3 read-write TRIGPOL Select the polarity of the selected input trigger for this conversion sequence. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write. 18 1 read-write 0 Negative edge. A negative edge launches the conversion sequence on the selected trigger input. #0 1 Positive edge. A positive edge launches the conversion sequence on the selected trigger input. #1 SYNCBYPASS Setting this bit allows the hardware trigger input to bypass synchronization flip-flop stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0): Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period. 19 1 read-write 0 Enable trigger synchronization. The hardware trigger bypass is not enabled. #0 1 Bypass trigger synchronization. The hardware trigger bypass is enabled. #1 START Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a conversion sequence. It will consequently always read back as a zero. 26 1 read-write BURST Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions can be halted by clearing this bit. The sequence currently in progress will be completed before conversions are terminated. Note that a new sequence could begin just before BURST is cleared. 27 1 read-write SINGLESTEP When this bit is set, a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels comprising a sequence have been converted, a subsequent trigger will repeat the sequence beginning with the first enabled channel. Interrupt generation will still occur either after each individual conversion or at the end of the entire sequence, depending on the state of the MODE bit. 28 1 read-write LOWPRIO Set priority for sequence A. 29 1 read-write 0 Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost. #0 1 High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion currently in progress will be terminated. The A sequence that was interrupted will automatically resume after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the conversion sequence will resume from that point. #1 MODE Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQA_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which overrun conditions contribute to an overrun interrupt as described below. 30 1 read-write 0 End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger if enabled. #0 1 End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun interrupt/DMA trigger since it is assumed this register may not be utilized in this mode. #1 SEQ_ENA Sequence Enable. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled. 31 1 read-write 0 Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel. #0 1 Enabled. Sequence n is enabled. #1 SEQ_CTRLB ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. 0xC 32 read-write 0 0xFC0FFFFF CHANNELS Selects which one or more of the ADC channels will be sampled and converted when this sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 and so forth. When this conversion sequence is triggered, either by a hardware trigger or via software command, ADC conversions will be performed on each enabled channel, in sequence, beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31) is LOW. It is allowed to change this field and set bit 31 in the same write. 0 12 read-write TRIGGER Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field. See Table 476. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write. 12 3 read-write TRIGPOL Select the polarity of the selected input trigger for this conversion sequence. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write. 18 1 read-write 0 Negative edge. A negative edge launches the conversion sequence on the selected trigger input. #0 1 Positive edge. A positive edge launches the conversion sequence on the selected trigger input. #1 SYNCBYPASS Setting this bit allows the hardware trigger input to bypass synchronization flip-flop stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0): Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period. 19 1 read-write 0 Enable trigger synchronization. The hardware trigger bypass is not enabled. #0 1 Bypass trigger synchronization. The hardware trigger bypass is enabled. #1 START Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a conversion sequence. It will consequently always read back as a zero. 26 1 read-write BURST Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions can be halted by clearing this bit. The sequence currently in progress will be completed before conversions are terminated. Note that a new sequence could begin just before BURST is cleared. 27 1 read-write SINGLESTEP When this bit is set, a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels comprising a sequence have been converted, a subsequent trigger will repeat the sequence beginning with the first enabled channel. Interrupt generation will still occur either after each individual conversion or at the end of the entire sequence, depending on the state of the MODE bit. 28 1 read-write LOWPRIO Set priority for sequence A. 29 1 read-write 0 Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost. #0 1 High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion currently in progress will be terminated. The A sequence that was interrupted will automatically resume after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the conversion sequence will resume from that point. #1 MODE Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQA_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which overrun conditions contribute to an overrun interrupt as described below. 30 1 read-write 0 End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger if enabled. #0 1 End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun interrupt/DMA trigger since it is assumed this register may not be utilized in this mode. #1 SEQ_ENA Sequence Enable. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled. 31 1 read-write 0 Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel. #0 1 Enabled. Sequence n is enabled. #1 SEQ_GDATA ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. 0x10 32 read-only 0 0xFC0FFFF0 RESULT This field contains the 12-bit ADC conversion result from the most recent conversion performed under conversion sequence associated with this register. The result is a binary fraction representing the voltage on the currently-selected input channel as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this result has not yet been read. 4 12 read-only THCMPRANGE Indicates whether the result of the last conversion performed was above, below or within the range established by the designated threshold comparison registers (THRn_LOW and THRn_HIGH). 16 2 read-only THCMPCROSS Indicates whether the result of the last conversion performed represented a crossing of the threshold level established by the designated LOW threshold comparison register (THRn_LOW) and, if so, in what direction the crossing occurred. 18 2 read-only CHN These bits contain the channel from which the RESULT bits were converted (e.g. 0000 identifies channel 0, 0001 channel 1, etc.). 26 4 read-only OVERRUN This bit is set if a new conversion result is loaded into the RESULT field before a previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set to '0' (and if the overrun interrupt is enabled). 30 1 read-only DATAVALID This bit is set to '1' at the end of each conversion when a new result is loaded into the RESULT field. It is cleared whenever this register is read. This bit will cause a conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that sequence is set to 0 (and if the interrupt is enabled). 31 1 read-only SEQ_GDATB ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. 0x14 32 read-only 0 0xFC0FFFF0 RESULT This field contains the 12-bit ADC conversion result from the most recent conversion performed under conversion sequence associated with this register. The result is a binary fraction representing the voltage on the currently-selected input channel as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this result has not yet been read. 4 12 read-only THCMPRANGE Indicates whether the result of the last conversion performed was above, below or within the range established by the designated threshold comparison registers (THRn_LOW and THRn_HIGH). 16 2 read-only THCMPCROSS Indicates whether the result of the last conversion performed represented a crossing of the threshold level established by the designated LOW threshold comparison register (THRn_LOW) and, if so, in what direction the crossing occurred. 18 2 read-only CHN These bits contain the channel from which the RESULT bits were converted (e.g. 0000 identifies channel 0, 0001 channel 1, etc.). 26 4 read-only OVERRUN This bit is set if a new conversion result is loaded into the RESULT field before a previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set to '0' (and if the overrun interrupt is enabled). 30 1 read-only DATAVALID This bit is set to '1' at the end of each conversion when a new result is loaded into the RESULT field. It is cleared whenever this register is read. This bit will cause a conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that sequence is set to 0 (and if the interrupt is enabled). 31 1 read-only DAT0 ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N. 0x20 32 read-only 0 0xFC0FFFF0 RESULT This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. 4 12 read-only THCMPRANGE Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved. 16 2 read-only THCMPCROSS Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold. 18 2 read-only CHANNEL This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc) 26 4 read-only OVERRUN This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. 30 1 read-only DATAVALID This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. 31 1 read-only DAT1 ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N. 0x24 32 read-only 0 0xFC0FFFF0 RESULT This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. 4 12 read-only THCMPRANGE Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved. 16 2 read-only THCMPCROSS Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold. 18 2 read-only CHANNEL This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc) 26 4 read-only OVERRUN This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. 30 1 read-only DATAVALID This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. 31 1 read-only DAT2 ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N. 0x28 32 read-only 0 0xFC0FFFF0 RESULT This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. 4 12 read-only THCMPRANGE Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved. 16 2 read-only THCMPCROSS Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold. 18 2 read-only CHANNEL This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc) 26 4 read-only OVERRUN This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. 30 1 read-only DATAVALID This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. 31 1 read-only DAT3 ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N. 0x2C 32 read-only 0 0xFC0FFFF0 RESULT This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. 4 12 read-only THCMPRANGE Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved. 16 2 read-only THCMPCROSS Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold. 18 2 read-only CHANNEL This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc) 26 4 read-only OVERRUN This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. 30 1 read-only DATAVALID This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. 31 1 read-only DAT4 ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N. 0x30 32 read-only 0 0xFC0FFFF0 RESULT This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. 4 12 read-only THCMPRANGE Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved. 16 2 read-only THCMPCROSS Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold. 18 2 read-only CHANNEL This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc) 26 4 read-only OVERRUN This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. 30 1 read-only DATAVALID This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. 31 1 read-only DAT5 ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N. 0x34 32 read-only 0 0xFC0FFFF0 RESULT This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. 4 12 read-only THCMPRANGE Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved. 16 2 read-only THCMPCROSS Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold. 18 2 read-only CHANNEL This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc) 26 4 read-only OVERRUN This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. 30 1 read-only DATAVALID This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. 31 1 read-only DAT6 ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N. 0x38 32 read-only 0 0xFC0FFFF0 RESULT This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. 4 12 read-only THCMPRANGE Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved. 16 2 read-only THCMPCROSS Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold. 18 2 read-only CHANNEL This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc) 26 4 read-only OVERRUN This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. 30 1 read-only DATAVALID This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. 31 1 read-only DAT7 ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N. 0x3C 32 read-only 0 0xFC0FFFF0 RESULT This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. 4 12 read-only THCMPRANGE Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved. 16 2 read-only THCMPCROSS Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold. 18 2 read-only CHANNEL This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc) 26 4 read-only OVERRUN This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. 30 1 read-only DATAVALID This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. 31 1 read-only DAT8 ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N. 0x40 32 read-only 0 0xFC0FFFF0 RESULT This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. 4 12 read-only THCMPRANGE Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved. 16 2 read-only THCMPCROSS Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold. 18 2 read-only CHANNEL This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc) 26 4 read-only OVERRUN This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. 30 1 read-only DATAVALID This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. 31 1 read-only DAT9 ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N. 0x44 32 read-only 0 0xFC0FFFF0 RESULT This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. 4 12 read-only THCMPRANGE Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved. 16 2 read-only THCMPCROSS Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold. 18 2 read-only CHANNEL This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc) 26 4 read-only OVERRUN This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. 30 1 read-only DATAVALID This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. 31 1 read-only DAT10 ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N. 0x48 32 read-only 0 0xFC0FFFF0 RESULT This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. 4 12 read-only THCMPRANGE Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved. 16 2 read-only THCMPCROSS Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold. 18 2 read-only CHANNEL This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc) 26 4 read-only OVERRUN This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. 30 1 read-only DATAVALID This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. 31 1 read-only DAT11 ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N. 0x4C 32 read-only 0 0xFC0FFFF0 RESULT This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. 4 12 read-only THCMPRANGE Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved. 16 2 read-only THCMPCROSS Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold. 18 2 read-only CHANNEL This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc) 26 4 read-only OVERRUN This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. 30 1 read-only DATAVALID This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. 31 1 read-only THR0_LOW ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. 0x50 32 read-write 0 0xFFF0 THRLOW Low threshold value against which ADC results will be compared 4 12 read-write THR1_LOW ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. 0x54 32 read-write 0 0xFFF0 THRLOW Low threshold value against which ADC results will be compared 4 12 read-write THR0_HIGH ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. 0x58 32 read-write 0 0xFFF0 THRHIGH High threshold value against which ADC results will be compared 4 12 read-write THR1_HIGH ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. 0x5C 32 read-write 0 0xFFF0 THRHIGH High threshold value against which ADC results will be compared 4 12 read-write CHAN_THRSEL ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel 0x60 32 read-write 0 0xFFF CH0_THRSEL Threshold select for channel 0. 0 1 read-write 0 Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers. #0 1 Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers. #1 CH1_THRSEL Threshold select for channel 1. See description for channel 0. 1 1 read-write CH2_THRSEL Threshold select for channel 2. See description for channel 0. 2 1 read-write CH3_THRSEL Threshold select for channel 3. See description for channel 0. 3 1 read-write CH4_THRSEL Threshold select for channel 4. See description for channel 0. 4 1 read-write CH5_THRSEL Threshold select for channel 5. See description for channel 0. 5 1 read-write CH6_THRSEL Threshold select for channel 6. See description for channel 0. 6 1 read-write CH7_THRSEL Threshold select for channel 7. See description for channel 0. 7 1 read-write CH8_THRSEL Threshold select for channel 8. See description for channel 0. 8 1 read-write CH9_THRSEL Threshold select for channel 9. See description for channel 0. 9 1 read-write CH10_THRSEL Threshold select for channel 10. See description for channel 0. 10 1 read-write CH11_THRSEL Threshold select for channel 11. See description for channel 0. 11 1 read-write INTEN ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. 0x64 32 read-write 0 0x7FFFFFF SEQA_INTEN Sequence A interrupt enable. 0 1 read-write 0 Disabled. The sequence A interrupt/DMA trigger is disabled. #0 1 Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of conversions, depending on the MODE bit in the SEQA_CTRL register. #1 SEQB_INTEN Sequence B interrupt enable. 1 1 read-write 0 Disabled. The sequence B interrupt/DMA trigger is disabled. #0 1 Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of conversions, depending on the MODE bit in the SEQB_CTRL register. #1 OVR_INTEN Overrun interrupt enable. 2 1 read-write 0 Disabled. The overrun interrupt is disabled. #0 1 Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular sequence is 0, then an overrun in the global data register for that sequence will also cause this interrupt/DMA trigger to be asserted. #1 ADCMPINTEN0 Threshold comparison interrupt enable for channel 0. 3 2 read-write 00 Disabled. #00 01 Outside threshold. #01 10 Crossing threshold. #10 ADCMPINTEN1 Channel 1 threshold comparison interrupt enable. See description for channel 0. 5 2 read-write ADCMPINTEN2 Channel 2 threshold comparison interrupt enable. See description for channel 0. 7 2 read-write ADCMPINTEN3 Channel 3 threshold comparison interrupt enable. See description for channel 0. 9 2 read-write ADCMPINTEN4 Channel 4 threshold comparison interrupt enable. See description for channel 0. 11 2 read-write ADCMPINTEN5 Channel 5 threshold comparison interrupt enable. See description for channel 0. 13 2 read-write ADCMPINTEN6 Channel 6 threshold comparison interrupt enable. See description for channel 0. 15 2 read-write ADCMPINTEN7 Channel 7 threshold comparison interrupt enable. See description for channel 0. 17 2 read-write ADCMPINTEN8 Channel 8 threshold comparison interrupt enable. See description for channel 0. 19 2 read-write ADCMPINTEN9 Channel 9 threshold comparison interrupt enable. See description for channel 0. 21 2 read-write ADCMPINTEN10 Channel 10 threshold comparison interrupt enable. See description for channel 0. 23 2 read-write ADCMPINTEN11 Channel 21 threshold comparison interrupt enable. See description for channel 0. 25 2 read-write FLAGS ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). 0x68 32 read-write 0 0xF3FFFFFF THCMP0 Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1. 0 1 read-write THCMP1 Threshold comparison event on Channel 1. See description for channel 0. 1 1 read-write THCMP2 Threshold comparison event on Channel 2. See description for channel 0. 2 1 read-write THCMP3 Threshold comparison event on Channel 3. See description for channel 0. 3 1 read-write THCMP4 Threshold comparison event on Channel 4. See description for channel 0. 4 1 read-write THCMP5 Threshold comparison event on Channel 5. See description for channel 0. 5 1 read-write THCMP6 Threshold comparison event on Channel 6. See description for channel 0. 6 1 read-write THCMP7 Threshold comparison event on Channel 7. See description for channel 0. 7 1 read-write THCMP8 Threshold comparison event on Channel 8. See description for channel 0. 8 1 read-write THCMP9 Threshold comparison event on Channel 9. See description for channel 0. 9 1 read-write THCMP10 Threshold comparison event on Channel 10. See description for channel 0. 10 1 read-write THCMP11 Threshold comparison event on Channel 11. See description for channel 0. 11 1 read-write OVERRUN0 Mirrors the OVERRRUN status flag from the result register for ADC channel 0 12 1 read-only OVERRUN1 Mirrors the OVERRRUN status flag from the result register for ADC channel 1 13 1 read-only OVERRUN2 Mirrors the OVERRRUN status flag from the result register for ADC channel 2 14 1 read-only OVERRUN3 Mirrors the OVERRRUN status flag from the result register for ADC channel 3 15 1 read-only OVERRUN4 Mirrors the OVERRRUN status flag from the result register for ADC channel 4 16 1 read-only OVERRUN5 Mirrors the OVERRRUN status flag from the result register for ADC channel 5 17 1 read-only OVERRUN6 Mirrors the OVERRRUN status flag from the result register for ADC channel 6 18 1 read-only OVERRUN7 Mirrors the OVERRRUN status flag from the result register for ADC channel 7 19 1 read-only OVERRUN8 Mirrors the OVERRRUN status flag from the result register for ADC channel 8 20 1 read-only OVERRUN9 Mirrors the OVERRRUN status flag from the result register for ADC channel 9 21 1 read-only OVERRUN10 Mirrors the OVERRRUN status flag from the result register for ADC channel 10 22 1 read-only OVERRUN11 Mirrors the OVERRRUN status flag from the result register for ADC channel 11 23 1 read-only SEQA_OVR Mirrors the global OVERRUN status flag in the SEQA_GDAT register 24 1 read-only SEQB_OVR Mirrors the global OVERRUN status flag in the SEQB_GDAT register 25 1 read-only SEQA_INT Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which is set at the end of every ADC conversion performed as part of sequence A. It will be cleared automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register is 1, this flag will be set upon completion of an entire A sequence. In this case it must be cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN register. 28 1 read-only SEQB_INT Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which is set at the end of every ADC conversion performed as part of sequence B. It will be cleared automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register is 1, this flag will be set upon completion of an entire B sequence. In this case it must be cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN register. 29 1 read-only THCMP_INT Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in the lower bits of this register are set to 1 (due to an enabled out-of-range or threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be individually enabled in the INTEN register to cause this interrupt. This bit will be cleared when all of the individual threshold flags are cleared via writing 1s to those bits. 30 1 read-only OVR_INT Overrun Interrupt flag. Any overrun bit in any of the individual channel data registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all of the individual overrun bits have been cleared via reading the corresponding data registers. 31 1 read-only TRM ADC Startup register. 0x6C 32 read-write 0 0x20 VRANGE 1.8V to 3.6V Vdd range: This bit MUST be set to '1' if operation below 2.7V is to be used. Failure to set this bit will result in invalid ADC results. Note: This bit will not be spec'd on parts that do not support operation below 2.7V 5 1 read-write PMU LPC84x PMU 0x40020000 0 0x18 registers PCON Power control register 0 32 read-write 0 0x90F PM Power mode 0 3 read-write 00 Default. The part is in active or sleep mode. #000 01 Deep-sleep mode. ARM WFI will enter Deep-sleep mode. #001 10 Power-down mode. ARM WFI will enter Power-down mode. #010 11 Deep power-down mode. ARM WFI will enter Deep-power down mode (ARM Cortex-M0+ core powered-down). #011 NODPD A 1 in this bit prevents entry to Deep power-down mode when 0x3 is written to the PM field above, the SLEEPDEEP bit is set, and a WFI is executed. This bit is cleared only by power-on reset, so writing a one to this bit locks the part in a mode in which Deep power-down mode is blocked. 3 1 read-write SLEEPFLAG Sleep mode flag 8 1 read-write 0 Active mode. Read: No power-down mode entered. Part is in Active mode. Write: No effect. #0 1 Low power mode. Read: Sleep, Deep-sleep or Power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0. #1 DPDFLAG Deep power-down flag 11 1 read-write 0 Not Deep power-down. Read: Deep power-down mode not entered. Write: No effect. #0 1 Deep power-down. Read: Deep power-down mode entered. Write: Clear the Deep power-down flag. #1 GPREG0 General purpose register N 0x4 32 read-write 0 0xFFFFFFFF GPDATA Data retained during Deep power-down mode. 0 32 read-write GPREG1 General purpose register N 0x8 32 read-write 0 0xFFFFFFFF GPDATA Data retained during Deep power-down mode. 0 32 read-write GPREG2 General purpose register N 0xC 32 read-write 0 0xFFFFFFFF GPDATA Data retained during Deep power-down mode. 0 32 read-write GPREG3 General purpose register N 0x10 32 read-write 0 0xFFFFFFFF GPDATA Data retained during Deep power-down mode. 0 32 read-write DPDCTRL Deep power-down control register. Also includes bits for general purpose storage. 0x14 32 read-write 0 0xFFFFFFFF WAKEUPHYS WAKEUP pin hysteresis enable 0 1 read-write 0 Disabled. Hysteresis for WAKEUP pin disabled. #0 1 Enabled. Hysteresis for WAKEUP pin enabled. #1 WAKEPAD_DISABLE WAKEUP pin disable. Setting this bit disables the wake-up pin, so it can be used for other purposes. Remark: Never set this bit if you intend to use a pin to wake up the part from Deep power-down mode. You can only disable the wake-up pin if the self wake-up timer is enabled and configured. Remark: Setting this bit is not necessary if Deep power-down mode is not used. 1 1 read-write 0 Enabled. The wake-up function is enabled on pin PIO0_4. #0 1 Disabled. Setting this bit disables the wake-up function on pin PIO0_4. #1 LPOSCEN Enable the low-power oscillator for use with the 10 kHz self wake-up timer clock. You must set this bit if the CLKSEL bit in the self wake-up timer CTRL bit is set. Do not enable the low-power oscillator if the self wake-up timer is clocked by the divided IRC or the external clock input. 2 1 read-write 0 Disabled. #0 1 Enabled. #1 LPOSCDPDEN causes the low-power oscillator to remain running during Deep power-down mode provided that bit 2 in this register is set as well. You must set this bit for the self wake-up timer to be able to wake up the part from Deep power-down mode. Remark: Do not set this bit unless you use the self wake-up timer with the low-power oscillator clock source to wake up from Deep power-down mode. 3 1 read-write 0 Disabled. #0 1 Enabled. #1 WAKEUPCLKHYS External clock input for the self wake-up timer WKTCLKIN hysteresis enable. 4 1 read-write 0 Disabled. Hysteresis for WAKEUP clock pin disabled. #0 1 Enabled. Hysteresis for WAKEUP clock pin enabled. #1 WAKECLKPAD_DISABLE Disable the external clock input for the self-wake-up timer. Setting this bit enables the self-wake-up timer clock pin WKTCLKLIN. To minimize power consumption, especially in deep power-down mode, disable this clock input when not using the external clock option for the self-wake-up timer. 5 1 read-write 0 Disabled. Setting this bit disables external clock input on pin PIO0_28. #0 1 Enabled. The external clock input for the self wake-up timer is enabled on pin PIO0_28. #1 RESETHYS RESET pin hysteresis enable. 6 1 read-write 0 Disabled. Hysteresis for RESET pin disabled. #0 1 Enabled. Hysteresis for RESET pin enabled. #1 RESET_DISABLE RESET pin disable. Setting this bit disables the reset wake-up function, so the pin can be used for other purposes. Remark: Setting this bit is not necessary if deep power-down mode is not used. 7 1 read-write 0 Enabled. The reset wake-up function is enabled on pin PIO0_5. #0 1 Disabled. Setting this bit disables the wake-up function on pin PIO0_5. #1 GPDATA Data retained during Deep power-down mode. 8 24 read-write ACOMP LPC84x analog comparator 0x40024000 0 0x8 registers CMP_CAPT 11 CTRL Comparator control register 0 32 read-write 0 0x6C03F58 EDGESEL This field controls which edges on the comparator output set the COMPEDGE bit (bit 23 below): 3 2 read-write 00 Falling edges #00 01 Rising edges #01 10 Both edges #10 11 Both edges #11 COMPSA Comparator output control 6 1 read-write 0 Comparator output is used directly. #0 1 Comparator output is synchronized to the bus clock for output to other modules. #1 COMP_VP_SEL Selects positive voltage input 8 3 read-write 000 VOLTAGE_LADDER_OUTPUT #000 001 ACMP_I1 #001 010 ACMP_I2 #010 011 ACMP_I3 #011 100 ACMP_I4 #100 101 ACMP_I5 #101 110 Band gap. Internal reference voltage. #110 111 DAC0 output #111 COMP_VM_SEL Selects negative voltage input 11 3 read-write 000 VOLTAGE_LADDER_OUTPUT #000 001 ACMP_I1 #001 010 ACMP_I2 #010 011 ACMP_I3 #011 100 ACMP_I4 #100 101 ACMP_I5 #101 110 Band gap. Internal reference voltage. #110 111 DAC0 output #111 EDGECLR Interrupt clear bit. To clear the COMPEDGE bit and thus negate the interrupt request, toggle the EDGECLR bit by first writing a 1 and then a 0. 20 1 read-write COMPSTAT Comparator status. This bit reflects the state of the comparator output. 21 1 read-write COMPEDGE Comparator edge-detect status. 23 1 read-write INTENA Must be set to generate interrupts. 24 1 read-write HYS Controls the hysteresis of the comparator. When the comparator is outputting a certain state, this is the difference between the selected signals, in the opposite direction from the state being output, that will switch the output. 25 2 read-write 00 None (the output will switch as the voltages cross) #00 01 5 mv #01 10 10 mv #10 11 20 mv #11 LAD Voltage ladder register 0x4 32 read-write 0 0xFFFFFFFF LADEN Voltage ladder enable 0 1 read-write LADSEL Voltage ladder value. The reference voltage Vref depends on the LADREF bit below. 00000 = VSS 00001 = 1 x Vref/31 00010 = 2 x Vref/31 ... 11111 = Vref 1 5 read-write LADREF Selects the reference voltage Vref for the voltage ladder. 6 1 read-write 0 Supply pin VDD #0 1 VDDCMP pin #1 INPUTMUX LPC84x Input multiplexing (INPUT MUX) 0x4002C000 0 0xA4 registers DMA_INMUX_INMUX0 DMA output trigger selection to become DMA trigger 0 32 read-write 0x1F 0x1F INP DMA trigger output number (decimal value) for DMA channel n (n = 0 to 24). 0 5 read-write DMA_INMUX_INMUX1 DMA output trigger selection to become DMA trigger 0x4 32 read-write 0x1F 0x1F INP DMA trigger output number (decimal value) for DMA channel n (n = 0 to 24). 0 5 read-write SCT_INMUX0 input select register for SCT 0x20 32 read-write 0xF 0xF INP_N Input mux register for SCT input n (n = 0 to 3). 0 = sct input 0 1=sct input 1 2= sct input 2 3= sct gpio input 3 4= adc_thcmp_irq 5 = comparator out 6 = timer ct32b0 match2 7=gpio_int_bmatch 8=arm_txev 9=debug_halted 0 4 read-write SCT_INMUX1 input select register for SCT 0x24 32 read-write 0xF 0xF INP_N Input mux register for SCT input n (n = 0 to 3). 0 = sct input 0 1=sct input 1 2= sct input 2 3= sct gpio input 3 4= adc_thcmp_irq 5 = comparator out 6 = timer ct32b0 match2 7=gpio_int_bmatch 8=arm_txev 9=debug_halted 0 4 read-write SCT_INMUX2 input select register for SCT 0x28 32 read-write 0xF 0xF INP_N Input mux register for SCT input n (n = 0 to 3). 0 = sct input 0 1=sct input 1 2= sct input 2 3= sct gpio input 3 4= adc_thcmp_irq 5 = comparator out 6 = timer ct32b0 match2 7=gpio_int_bmatch 8=arm_txev 9=debug_halted 0 4 read-write SCT_INMUX3 input select register for SCT 0x2C 32 read-write 0xF 0xF INP_N Input mux register for SCT input n (n = 0 to 3). 0 = sct input 0 1=sct input 1 2= sct input 2 3= sct gpio input 3 4= adc_thcmp_irq 5 = comparator out 6 = timer ct32b0 match2 7=gpio_int_bmatch 8=arm_txev 9=debug_halted 0 4 read-write DMA_ITRIG_INMUX0 Trigger select register for DMA channel 0x40 32 read-write 0xF 0xF INP Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1 0 4 read-write DMA_ITRIG_INMUX1 Trigger select register for DMA channel 0x44 32 read-write 0xF 0xF INP Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1 0 4 read-write DMA_ITRIG_INMUX2 Trigger select register for DMA channel 0x48 32 read-write 0xF 0xF INP Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1 0 4 read-write DMA_ITRIG_INMUX3 Trigger select register for DMA channel 0x4C 32 read-write 0xF 0xF INP Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1 0 4 read-write DMA_ITRIG_INMUX4 Trigger select register for DMA channel 0x50 32 read-write 0xF 0xF INP Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1 0 4 read-write DMA_ITRIG_INMUX5 Trigger select register for DMA channel 0x54 32 read-write 0xF 0xF INP Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1 0 4 read-write DMA_ITRIG_INMUX6 Trigger select register for DMA channel 0x58 32 read-write 0xF 0xF INP Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1 0 4 read-write DMA_ITRIG_INMUX7 Trigger select register for DMA channel 0x5C 32 read-write 0xF 0xF INP Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1 0 4 read-write DMA_ITRIG_INMUX8 Trigger select register for DMA channel 0x60 32 read-write 0xF 0xF INP Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1 0 4 read-write DMA_ITRIG_INMUX9 Trigger select register for DMA channel 0x64 32 read-write 0xF 0xF INP Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1 0 4 read-write DMA_ITRIG_INMUX10 Trigger select register for DMA channel 0x68 32 read-write 0xF 0xF INP Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1 0 4 read-write DMA_ITRIG_INMUX11 Trigger select register for DMA channel 0x6C 32 read-write 0xF 0xF INP Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1 0 4 read-write DMA_ITRIG_INMUX12 Trigger select register for DMA channel 0x70 32 read-write 0xF 0xF INP Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1 0 4 read-write DMA_ITRIG_INMUX13 Trigger select register for DMA channel 0x74 32 read-write 0xF 0xF INP Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1 0 4 read-write DMA_ITRIG_INMUX14 Trigger select register for DMA channel 0x78 32 read-write 0xF 0xF INP Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1 0 4 read-write DMA_ITRIG_INMUX15 Trigger select register for DMA channel 0x7C 32 read-write 0xF 0xF INP Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1 0 4 read-write DMA_ITRIG_INMUX16 Trigger select register for DMA channel 0x80 32 read-write 0xF 0xF INP Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1 0 4 read-write DMA_ITRIG_INMUX17 Trigger select register for DMA channel 0x84 32 read-write 0xF 0xF INP Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1 0 4 read-write DMA_ITRIG_INMUX18 Trigger select register for DMA channel 0x88 32 read-write 0xF 0xF INP Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1 0 4 read-write DMA_ITRIG_INMUX19 Trigger select register for DMA channel 0x8C 32 read-write 0xF 0xF INP Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1 0 4 read-write DMA_ITRIG_INMUX20 Trigger select register for DMA channel 0x90 32 read-write 0xF 0xF INP Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1 0 4 read-write DMA_ITRIG_INMUX21 Trigger select register for DMA channel 0x94 32 read-write 0xF 0xF INP Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1 0 4 read-write DMA_ITRIG_INMUX22 Trigger select register for DMA channel 0x98 32 read-write 0xF 0xF INP Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1 0 4 read-write DMA_ITRIG_INMUX23 Trigger select register for DMA channel 0x9C 32 read-write 0xF 0xF INP Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1 0 4 read-write DMA_ITRIG_INMUX24 Trigger select register for DMA channel 0xA0 32 read-write 0xF 0xF INP Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1 0 4 read-write I2C2 LPC84x I2C-bus interfaces I2C 0x40030000 0 0x84 registers I2C2 21 CFG Configuration for shared functions. 0 32 read-write 0 0x3F MSTEN Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset. 0 1 read-write 0 Disabled. The I2C Master function is disabled. #0 1 Enabled. The I2C Master function is enabled. #1 SLVEN Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset. 1 1 read-write 0 Disabled. The I2C slave function is disabled. #0 1 Enabled. The I2C slave function is enabled. #1 MONEN Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset. 2 1 read-write 0 Disabled. The I2C Monitor function is disabled. #0 1 Enabled. The I2C Monitor function is enabled. #1 TIMEOUTEN I2C bus Time-out Enable. When disabled, the time-out function is internally reset. 3 1 read-write 0 Disabled. Time-out function is disabled. #0 1 Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system. #1 MONCLKSTR Monitor function Clock Stretching. 4 1 read-write 0 Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical. #0 1 Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function. #1 STAT Status register for Master, Slave, and Monitor functions. 0x4 32 read-write 0x801 0x30FFF5F MSTPENDING Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt. 0 1 read-only 0 In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. #0 1 Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit. #1 MSTSTATE Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses. 1 3 read-only 000 Idle. The Master function is available to be used for a new transaction. #000 001 Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. #001 010 Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. #010 011 NACK Address. Slave NACKed address. #011 100 NACK Data. Slave NACKed transmitted data. #100 MSTARBLOSS Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. 4 1 read-write 0 No Arbitration Loss has occurred. #0 1 Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. #1 MSTSTSTPERR Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. 6 1 read-write 0 No Start/Stop Error has occurred. #0 1 The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled. #1 SLVPENDING Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched. 8 1 read-only 0 In progress. The Slave function does not currently need service. #0 1 Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. #1 SLVSTATE Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes. 9 2 read-only 00 Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. #00 01 Slave receive. Received data is available (Slave Receiver mode). #01 10 Slave transmit. Data can be transmitted (Slave Transmitter mode). #10 SLVNOTSTR Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time. 11 1 read-only 0 Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. #0 1 Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time. #1 SLVIDX Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here. 12 2 read-only 00 Address 0. Slave address 0 was matched. #00 01 Address 1. Slave address 1 was matched. #01 10 Address 2. Slave address 2 was matched. #10 11 Address 3. Slave address 3 was matched. #11 SLVSEL Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data. 14 1 read-only 0 Not selected. The Slave function is not currently selected. #0 1 Selected. The Slave function is currently selected. #1 SLVDESEL Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit. 15 1 read-write 0 Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag. #0 1 Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. #1 MONRDY Monitor Ready. This flag is cleared when the MONRXDAT register is read. 16 1 read-only 0 No data. The Monitor function does not currently have data available. #0 1 Data waiting. The Monitor function has data waiting to be read. #1 MONOV Monitor Overflow flag. 17 1 read-write 0 No overrun. Monitor data has not overrun. #0 1 Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. #1 MONACTIVE Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop. 18 1 read-only 0 Inactive. The Monitor function considers the I2C bus to be inactive. #0 1 Active. The Monitor function considers the I2C bus to be active. #1 MONIDLE Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit. 19 1 read-write 0 Not idle. The I2C bus is not idle, or this flag has been cleared by software. #0 1 Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. #1 EVENTTIMEOUT Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle. 24 1 read-write 0 No time-out. I2C bus events have not caused a time-out. #0 1 Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. #1 SCLTIMEOUT SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. 25 1 read-write 0 No time-out. SCL low time has not caused a time-out. #0 1 Time-out. SCL low time has caused a time-out. #1 INTENSET Interrupt Enable Set and read register. 0x8 32 read-write 0 0x30B8951 MSTPENDINGEN Master Pending interrupt Enable. 0 1 read-write 0 Disabled. The MstPending interrupt is disabled. #0 1 Enabled. The MstPending interrupt is enabled. #1 MSTARBLOSSEN Master Arbitration Loss interrupt Enable. 4 1 read-write 0 Disabled. The MstArbLoss interrupt is disabled. #0 1 Enabled. The MstArbLoss interrupt is enabled. #1 MSTSTSTPERREN Master Start/Stop Error interrupt Enable. 6 1 read-write 0 Disabled. The MstStStpErr interrupt is disabled. #0 1 Enabled. The MstStStpErr interrupt is enabled. #1 SLVPENDINGEN Slave Pending interrupt Enable. 8 1 read-write 0 Disabled. The SlvPending interrupt is disabled. #0 1 Enabled. The SlvPending interrupt is enabled. #1 SLVNOTSTREN Slave Not Stretching interrupt Enable. 11 1 read-write 0 Disabled. The SlvNotStr interrupt is disabled. #0 1 Enabled. The SlvNotStr interrupt is enabled. #1 SLVDESELEN Slave Deselect interrupt Enable. 15 1 read-write 0 Disabled. The SlvDeSel interrupt is disabled. #0 1 Enabled. The SlvDeSel interrupt is enabled. #1 MONRDYEN Monitor data Ready interrupt Enable. 16 1 read-write 0 Disabled. The MonRdy interrupt is disabled. #0 1 Enabled. The MonRdy interrupt is enabled. #1 MONOVEN Monitor Overrun interrupt Enable. 17 1 read-write 0 Disabled. The MonOv interrupt is disabled. #0 1 Enabled. The MonOv interrupt is enabled. #1 MONIDLEEN Monitor Idle interrupt Enable. 19 1 read-write 0 Disabled. The MonIdle interrupt is disabled. #0 1 Enabled. The MonIdle interrupt is enabled. #1 EVENTTIMEOUTEN Event time-out interrupt Enable. 24 1 read-write 0 Disabled. The Event time-out interrupt is disabled. #0 1 Enabled. The Event time-out interrupt is enabled. #1 SCLTIMEOUTEN SCL time-out interrupt Enable. 25 1 read-write 0 Disabled. The SCL time-out interrupt is disabled. #0 1 Enabled. The SCL time-out interrupt is enabled. #1 INTENCLR Interrupt Enable Clear register. 0xC 32 write-only 0 0 MSTPENDINGCLR Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented. 0 1 write-only MSTARBLOSSCLR Master Arbitration Loss interrupt clear. 4 1 write-only MSTSTSTPERRCLR Master Start/Stop Error interrupt clear. 6 1 write-only SLVPENDINGCLR Slave Pending interrupt clear. 8 1 write-only SLVNOTSTRCLR Slave Not Stretching interrupt clear. 11 1 write-only SLVDESELCLR Slave Deselect interrupt clear. 15 1 write-only MONRDYCLR Monitor data Ready interrupt clear. 16 1 write-only MONOVCLR Monitor Overrun interrupt clear. 17 1 write-only MONIDLECLR Monitor Idle interrupt clear. 19 1 write-only EVENTTIMEOUTCLR Event time-out interrupt clear. 24 1 write-only SCLTIMEOUTCLR SCL time-out interrupt clear. 25 1 write-only TIMEOUT Time-out value register. 0x10 32 read-write 0xFFFF 0xFFFF TOMIN Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks. 0 4 read-write TO Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock. 4 12 read-write CLKDIV Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. 0x14 32 read-write 0 0xFFFF DIVVAL This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is divided by 65,536 before use. 0 16 read-write INTSTAT Interrupt Status register for Master, Slave, and Monitor functions. 0x18 32 read-only 0x801 0x30FFF5F MSTPENDING Master Pending. 0 1 read-only MSTARBLOSS Master Arbitration Loss flag. 4 1 read-only MSTSTSTPERR Master Start/Stop Error flag. 6 1 read-only SLVPENDING Slave Pending. 8 1 read-only SLVNOTSTR Slave Not Stretching status. 11 1 read-only SLVDESEL Slave Deselected flag. 15 1 read-only MONRDY Monitor Ready. 16 1 read-only MONOV Monitor Overflow flag. 17 1 read-only MONIDLE Monitor Idle flag. 19 1 read-only EVENTTIMEOUT Event time-out Interrupt flag. 24 1 read-only SCLTIMEOUT SCL time-out Interrupt flag. 25 1 read-only MSTCTL Master control register. 0x20 32 read-write 0 0xF MSTCONTINUE Master Continue. 0 1 read-write 0 No effect. #0 1 Informs the Master function to continue to the next operation. #1 MSTSTART Master Start control. 1 1 read-write 0 No effect. #0 1 Start. A Start will be generated on the I2C bus at the next allowed time. #1 MSTSTOP Master Stop control. 2 1 read-write 0 No effect. #0 1 Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode). #1 MSTDMA Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write. 3 1 read-write 0 Disable. No DMA requests are generated for master operation. #0 1 Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. #1 MSTTIME Master timing configuration. 0x24 32 read-write 0x77 0x77 MSTSCLLOW Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW. 0 3 read-write 000 2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. #000 001 3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. #001 010 4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. #010 011 5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. #011 100 6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. #100 101 7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. #101 110 8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. #110 111 9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. #111 MSTSCLHIGH Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. 4 3 read-write 000 2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. #000 001 3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . #001 010 4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. #010 011 5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. #011 100 6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. #100 101 7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. #101 110 8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. #110 111 9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. #111 MSTDAT Combined Master receiver and transmitter data register. 0x28 32 read-write 0 0xFF DATA Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function. 0 8 read-write SLVCTL Slave control register. 0x40 32 read-write 0 0xB SLVCONTINUE Slave Continue. 0 1 read-write 0 No effect. #0 1 Informs the Slave function to continue to the next operation. #1 SLVNACK Slave NACK. 1 1 read-write 0 No effect. #0 1 NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). #1 SLVDMA Slave DMA enable. 3 1 read-write 0 Disabled. No DMA requests are issued for Slave mode operation. #0 1 Enabled. DMA requests are issued for I2C slave data transmission and reception. #1 SLVDAT Combined Slave receiver and transmitter data register. 0x44 32 read-write 0 0xFF DATA Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function. 0 8 read-write SLVADR0 Slave address register. 0x48 32 read-write 0x1 0xFF SADISABLE Slave Address n Disable. 0 1 read-write 0 Enabled. Slave Address n is enabled. #0 1 Ignored Slave Address n is ignored. #1 SLVADR Slave Address. Seven bit slave address that is compared to received addresses if enabled. 1 7 read-write SLVADR1 Slave address register. 0x4C 32 read-write 0x1 0xFF SADISABLE Slave Address n Disable. 0 1 read-write 0 Enabled. Slave Address n is enabled. #0 1 Ignored Slave Address n is ignored. #1 SLVADR Slave Address. Seven bit slave address that is compared to received addresses if enabled. 1 7 read-write SLVADR2 Slave address register. 0x50 32 read-write 0x1 0xFF SADISABLE Slave Address n Disable. 0 1 read-write 0 Enabled. Slave Address n is enabled. #0 1 Ignored Slave Address n is ignored. #1 SLVADR Slave Address. Seven bit slave address that is compared to received addresses if enabled. 1 7 read-write SLVADR3 Slave address register. 0x54 32 read-write 0x1 0xFF SADISABLE Slave Address n Disable. 0 1 read-write 0 Enabled. Slave Address n is enabled. #0 1 Ignored Slave Address n is ignored. #1 SLVADR Slave Address. Seven bit slave address that is compared to received addresses if enabled. 1 7 read-write SLVQUAL0 Slave Qualification for address 0. 0x58 32 read-write 0 0xFF QUALMODE0 Qualify mode for slave address 0. 0 1 read-write 0 Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. #0 1 Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. #1 SLVQUAL0 Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]). 1 7 read-write MONRXDAT Monitor receiver data register. 0x80 32 read-only 0 0x7FF MONRXDAT Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins. 0 8 read-only MONSTART Monitor Received Start. 8 1 read-only 0 No start detected. The Monitor function has not detected a Start event on the I2C bus. #0 1 Start detected. The Monitor function has detected a Start event on the I2C bus. #1 MONRESTART Monitor Received Repeated Start. 9 1 read-only 0 No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. #0 1 Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. #1 MONNACK Monitor Received NACK. 10 1 read-only 0 Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver. #0 1 Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver. #1 I2C3 LPC84x I2C-bus interfaces I2C 0x40034000 0 0x84 registers I2C3 22 CFG Configuration for shared functions. 0 32 read-write 0 0x3F MSTEN Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset. 0 1 read-write 0 Disabled. The I2C Master function is disabled. #0 1 Enabled. The I2C Master function is enabled. #1 SLVEN Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset. 1 1 read-write 0 Disabled. The I2C slave function is disabled. #0 1 Enabled. The I2C slave function is enabled. #1 MONEN Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset. 2 1 read-write 0 Disabled. The I2C Monitor function is disabled. #0 1 Enabled. The I2C Monitor function is enabled. #1 TIMEOUTEN I2C bus Time-out Enable. When disabled, the time-out function is internally reset. 3 1 read-write 0 Disabled. Time-out function is disabled. #0 1 Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system. #1 MONCLKSTR Monitor function Clock Stretching. 4 1 read-write 0 Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical. #0 1 Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function. #1 STAT Status register for Master, Slave, and Monitor functions. 0x4 32 read-write 0x801 0x30FFF5F MSTPENDING Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt. 0 1 read-only 0 In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. #0 1 Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit. #1 MSTSTATE Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses. 1 3 read-only 000 Idle. The Master function is available to be used for a new transaction. #000 001 Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. #001 010 Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. #010 011 NACK Address. Slave NACKed address. #011 100 NACK Data. Slave NACKed transmitted data. #100 MSTARBLOSS Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. 4 1 read-write 0 No Arbitration Loss has occurred. #0 1 Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. #1 MSTSTSTPERR Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. 6 1 read-write 0 No Start/Stop Error has occurred. #0 1 The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled. #1 SLVPENDING Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched. 8 1 read-only 0 In progress. The Slave function does not currently need service. #0 1 Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. #1 SLVSTATE Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes. 9 2 read-only 00 Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. #00 01 Slave receive. Received data is available (Slave Receiver mode). #01 10 Slave transmit. Data can be transmitted (Slave Transmitter mode). #10 SLVNOTSTR Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time. 11 1 read-only 0 Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. #0 1 Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time. #1 SLVIDX Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here. 12 2 read-only 00 Address 0. Slave address 0 was matched. #00 01 Address 1. Slave address 1 was matched. #01 10 Address 2. Slave address 2 was matched. #10 11 Address 3. Slave address 3 was matched. #11 SLVSEL Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data. 14 1 read-only 0 Not selected. The Slave function is not currently selected. #0 1 Selected. The Slave function is currently selected. #1 SLVDESEL Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit. 15 1 read-write 0 Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag. #0 1 Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. #1 MONRDY Monitor Ready. This flag is cleared when the MONRXDAT register is read. 16 1 read-only 0 No data. The Monitor function does not currently have data available. #0 1 Data waiting. The Monitor function has data waiting to be read. #1 MONOV Monitor Overflow flag. 17 1 read-write 0 No overrun. Monitor data has not overrun. #0 1 Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. #1 MONACTIVE Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop. 18 1 read-only 0 Inactive. The Monitor function considers the I2C bus to be inactive. #0 1 Active. The Monitor function considers the I2C bus to be active. #1 MONIDLE Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit. 19 1 read-write 0 Not idle. The I2C bus is not idle, or this flag has been cleared by software. #0 1 Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. #1 EVENTTIMEOUT Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle. 24 1 read-write 0 No time-out. I2C bus events have not caused a time-out. #0 1 Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. #1 SCLTIMEOUT SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. 25 1 read-write 0 No time-out. SCL low time has not caused a time-out. #0 1 Time-out. SCL low time has caused a time-out. #1 INTENSET Interrupt Enable Set and read register. 0x8 32 read-write 0 0x30B8951 MSTPENDINGEN Master Pending interrupt Enable. 0 1 read-write 0 Disabled. The MstPending interrupt is disabled. #0 1 Enabled. The MstPending interrupt is enabled. #1 MSTARBLOSSEN Master Arbitration Loss interrupt Enable. 4 1 read-write 0 Disabled. The MstArbLoss interrupt is disabled. #0 1 Enabled. The MstArbLoss interrupt is enabled. #1 MSTSTSTPERREN Master Start/Stop Error interrupt Enable. 6 1 read-write 0 Disabled. The MstStStpErr interrupt is disabled. #0 1 Enabled. The MstStStpErr interrupt is enabled. #1 SLVPENDINGEN Slave Pending interrupt Enable. 8 1 read-write 0 Disabled. The SlvPending interrupt is disabled. #0 1 Enabled. The SlvPending interrupt is enabled. #1 SLVNOTSTREN Slave Not Stretching interrupt Enable. 11 1 read-write 0 Disabled. The SlvNotStr interrupt is disabled. #0 1 Enabled. The SlvNotStr interrupt is enabled. #1 SLVDESELEN Slave Deselect interrupt Enable. 15 1 read-write 0 Disabled. The SlvDeSel interrupt is disabled. #0 1 Enabled. The SlvDeSel interrupt is enabled. #1 MONRDYEN Monitor data Ready interrupt Enable. 16 1 read-write 0 Disabled. The MonRdy interrupt is disabled. #0 1 Enabled. The MonRdy interrupt is enabled. #1 MONOVEN Monitor Overrun interrupt Enable. 17 1 read-write 0 Disabled. The MonOv interrupt is disabled. #0 1 Enabled. The MonOv interrupt is enabled. #1 MONIDLEEN Monitor Idle interrupt Enable. 19 1 read-write 0 Disabled. The MonIdle interrupt is disabled. #0 1 Enabled. The MonIdle interrupt is enabled. #1 EVENTTIMEOUTEN Event time-out interrupt Enable. 24 1 read-write 0 Disabled. The Event time-out interrupt is disabled. #0 1 Enabled. The Event time-out interrupt is enabled. #1 SCLTIMEOUTEN SCL time-out interrupt Enable. 25 1 read-write 0 Disabled. The SCL time-out interrupt is disabled. #0 1 Enabled. The SCL time-out interrupt is enabled. #1 INTENCLR Interrupt Enable Clear register. 0xC 32 write-only 0 0 MSTPENDINGCLR Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented. 0 1 write-only MSTARBLOSSCLR Master Arbitration Loss interrupt clear. 4 1 write-only MSTSTSTPERRCLR Master Start/Stop Error interrupt clear. 6 1 write-only SLVPENDINGCLR Slave Pending interrupt clear. 8 1 write-only SLVNOTSTRCLR Slave Not Stretching interrupt clear. 11 1 write-only SLVDESELCLR Slave Deselect interrupt clear. 15 1 write-only MONRDYCLR Monitor data Ready interrupt clear. 16 1 write-only MONOVCLR Monitor Overrun interrupt clear. 17 1 write-only MONIDLECLR Monitor Idle interrupt clear. 19 1 write-only EVENTTIMEOUTCLR Event time-out interrupt clear. 24 1 write-only SCLTIMEOUTCLR SCL time-out interrupt clear. 25 1 write-only TIMEOUT Time-out value register. 0x10 32 read-write 0xFFFF 0xFFFF TOMIN Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks. 0 4 read-write TO Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock. 4 12 read-write CLKDIV Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. 0x14 32 read-write 0 0xFFFF DIVVAL This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is divided by 65,536 before use. 0 16 read-write INTSTAT Interrupt Status register for Master, Slave, and Monitor functions. 0x18 32 read-only 0x801 0x30FFF5F MSTPENDING Master Pending. 0 1 read-only MSTARBLOSS Master Arbitration Loss flag. 4 1 read-only MSTSTSTPERR Master Start/Stop Error flag. 6 1 read-only SLVPENDING Slave Pending. 8 1 read-only SLVNOTSTR Slave Not Stretching status. 11 1 read-only SLVDESEL Slave Deselected flag. 15 1 read-only MONRDY Monitor Ready. 16 1 read-only MONOV Monitor Overflow flag. 17 1 read-only MONIDLE Monitor Idle flag. 19 1 read-only EVENTTIMEOUT Event time-out Interrupt flag. 24 1 read-only SCLTIMEOUT SCL time-out Interrupt flag. 25 1 read-only MSTCTL Master control register. 0x20 32 read-write 0 0xF MSTCONTINUE Master Continue. 0 1 read-write 0 No effect. #0 1 Informs the Master function to continue to the next operation. #1 MSTSTART Master Start control. 1 1 read-write 0 No effect. #0 1 Start. A Start will be generated on the I2C bus at the next allowed time. #1 MSTSTOP Master Stop control. 2 1 read-write 0 No effect. #0 1 Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode). #1 MSTDMA Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write. 3 1 read-write 0 Disable. No DMA requests are generated for master operation. #0 1 Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. #1 MSTTIME Master timing configuration. 0x24 32 read-write 0x77 0x77 MSTSCLLOW Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW. 0 3 read-write 000 2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. #000 001 3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. #001 010 4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. #010 011 5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. #011 100 6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. #100 101 7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. #101 110 8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. #110 111 9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. #111 MSTSCLHIGH Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. 4 3 read-write 000 2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. #000 001 3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . #001 010 4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. #010 011 5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. #011 100 6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. #100 101 7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. #101 110 8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. #110 111 9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. #111 MSTDAT Combined Master receiver and transmitter data register. 0x28 32 read-write 0 0xFF DATA Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function. 0 8 read-write SLVCTL Slave control register. 0x40 32 read-write 0 0xB SLVCONTINUE Slave Continue. 0 1 read-write 0 No effect. #0 1 Informs the Slave function to continue to the next operation. #1 SLVNACK Slave NACK. 1 1 read-write 0 No effect. #0 1 NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). #1 SLVDMA Slave DMA enable. 3 1 read-write 0 Disabled. No DMA requests are issued for Slave mode operation. #0 1 Enabled. DMA requests are issued for I2C slave data transmission and reception. #1 SLVDAT Combined Slave receiver and transmitter data register. 0x44 32 read-write 0 0xFF DATA Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function. 0 8 read-write SLVADR0 Slave address register. 0x48 32 read-write 0x1 0xFF SADISABLE Slave Address n Disable. 0 1 read-write 0 Enabled. Slave Address n is enabled. #0 1 Ignored Slave Address n is ignored. #1 SLVADR Slave Address. Seven bit slave address that is compared to received addresses if enabled. 1 7 read-write SLVADR1 Slave address register. 0x4C 32 read-write 0x1 0xFF SADISABLE Slave Address n Disable. 0 1 read-write 0 Enabled. Slave Address n is enabled. #0 1 Ignored Slave Address n is ignored. #1 SLVADR Slave Address. Seven bit slave address that is compared to received addresses if enabled. 1 7 read-write SLVADR2 Slave address register. 0x50 32 read-write 0x1 0xFF SADISABLE Slave Address n Disable. 0 1 read-write 0 Enabled. Slave Address n is enabled. #0 1 Ignored Slave Address n is ignored. #1 SLVADR Slave Address. Seven bit slave address that is compared to received addresses if enabled. 1 7 read-write SLVADR3 Slave address register. 0x54 32 read-write 0x1 0xFF SADISABLE Slave Address n Disable. 0 1 read-write 0 Enabled. Slave Address n is enabled. #0 1 Ignored Slave Address n is ignored. #1 SLVADR Slave Address. Seven bit slave address that is compared to received addresses if enabled. 1 7 read-write SLVQUAL0 Slave Qualification for address 0. 0x58 32 read-write 0 0xFF QUALMODE0 Qualify mode for slave address 0. 0 1 read-write 0 Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. #0 1 Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. #1 SLVQUAL0 Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]). 1 7 read-write MONRXDAT Monitor receiver data register. 0x80 32 read-only 0 0x7FF MONRXDAT Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins. 0 8 read-only MONSTART Monitor Received Start. 8 1 read-only 0 No start detected. The Monitor function has not detected a Start event on the I2C bus. #0 1 Start detected. The Monitor function has detected a Start event on the I2C bus. #1 MONRESTART Monitor Received Repeated Start. 9 1 read-only 0 No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. #0 1 Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. #1 MONNACK Monitor Received NACK. 10 1 read-only 0 Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver. #0 1 Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver. #1 I2C0 LPC84x I2C-bus interfaces I2C 0x40050000 0 0x84 registers I2C0 8 CFG Configuration for shared functions. 0 32 read-write 0 0x3F MSTEN Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset. 0 1 read-write 0 Disabled. The I2C Master function is disabled. #0 1 Enabled. The I2C Master function is enabled. #1 SLVEN Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset. 1 1 read-write 0 Disabled. The I2C slave function is disabled. #0 1 Enabled. The I2C slave function is enabled. #1 MONEN Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset. 2 1 read-write 0 Disabled. The I2C Monitor function is disabled. #0 1 Enabled. The I2C Monitor function is enabled. #1 TIMEOUTEN I2C bus Time-out Enable. When disabled, the time-out function is internally reset. 3 1 read-write 0 Disabled. Time-out function is disabled. #0 1 Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system. #1 MONCLKSTR Monitor function Clock Stretching. 4 1 read-write 0 Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical. #0 1 Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function. #1 STAT Status register for Master, Slave, and Monitor functions. 0x4 32 read-write 0x801 0x30FFF5F MSTPENDING Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt. 0 1 read-only 0 In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. #0 1 Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit. #1 MSTSTATE Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses. 1 3 read-only 000 Idle. The Master function is available to be used for a new transaction. #000 001 Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. #001 010 Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. #010 011 NACK Address. Slave NACKed address. #011 100 NACK Data. Slave NACKed transmitted data. #100 MSTARBLOSS Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. 4 1 read-write 0 No Arbitration Loss has occurred. #0 1 Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. #1 MSTSTSTPERR Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. 6 1 read-write 0 No Start/Stop Error has occurred. #0 1 The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled. #1 SLVPENDING Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched. 8 1 read-only 0 In progress. The Slave function does not currently need service. #0 1 Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. #1 SLVSTATE Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes. 9 2 read-only 00 Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. #00 01 Slave receive. Received data is available (Slave Receiver mode). #01 10 Slave transmit. Data can be transmitted (Slave Transmitter mode). #10 SLVNOTSTR Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time. 11 1 read-only 0 Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. #0 1 Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time. #1 SLVIDX Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here. 12 2 read-only 00 Address 0. Slave address 0 was matched. #00 01 Address 1. Slave address 1 was matched. #01 10 Address 2. Slave address 2 was matched. #10 11 Address 3. Slave address 3 was matched. #11 SLVSEL Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data. 14 1 read-only 0 Not selected. The Slave function is not currently selected. #0 1 Selected. The Slave function is currently selected. #1 SLVDESEL Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit. 15 1 read-write 0 Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag. #0 1 Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. #1 MONRDY Monitor Ready. This flag is cleared when the MONRXDAT register is read. 16 1 read-only 0 No data. The Monitor function does not currently have data available. #0 1 Data waiting. The Monitor function has data waiting to be read. #1 MONOV Monitor Overflow flag. 17 1 read-write 0 No overrun. Monitor data has not overrun. #0 1 Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. #1 MONACTIVE Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop. 18 1 read-only 0 Inactive. The Monitor function considers the I2C bus to be inactive. #0 1 Active. The Monitor function considers the I2C bus to be active. #1 MONIDLE Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit. 19 1 read-write 0 Not idle. The I2C bus is not idle, or this flag has been cleared by software. #0 1 Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. #1 EVENTTIMEOUT Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle. 24 1 read-write 0 No time-out. I2C bus events have not caused a time-out. #0 1 Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. #1 SCLTIMEOUT SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. 25 1 read-write 0 No time-out. SCL low time has not caused a time-out. #0 1 Time-out. SCL low time has caused a time-out. #1 INTENSET Interrupt Enable Set and read register. 0x8 32 read-write 0 0x30B8951 MSTPENDINGEN Master Pending interrupt Enable. 0 1 read-write 0 Disabled. The MstPending interrupt is disabled. #0 1 Enabled. The MstPending interrupt is enabled. #1 MSTARBLOSSEN Master Arbitration Loss interrupt Enable. 4 1 read-write 0 Disabled. The MstArbLoss interrupt is disabled. #0 1 Enabled. The MstArbLoss interrupt is enabled. #1 MSTSTSTPERREN Master Start/Stop Error interrupt Enable. 6 1 read-write 0 Disabled. The MstStStpErr interrupt is disabled. #0 1 Enabled. The MstStStpErr interrupt is enabled. #1 SLVPENDINGEN Slave Pending interrupt Enable. 8 1 read-write 0 Disabled. The SlvPending interrupt is disabled. #0 1 Enabled. The SlvPending interrupt is enabled. #1 SLVNOTSTREN Slave Not Stretching interrupt Enable. 11 1 read-write 0 Disabled. The SlvNotStr interrupt is disabled. #0 1 Enabled. The SlvNotStr interrupt is enabled. #1 SLVDESELEN Slave Deselect interrupt Enable. 15 1 read-write 0 Disabled. The SlvDeSel interrupt is disabled. #0 1 Enabled. The SlvDeSel interrupt is enabled. #1 MONRDYEN Monitor data Ready interrupt Enable. 16 1 read-write 0 Disabled. The MonRdy interrupt is disabled. #0 1 Enabled. The MonRdy interrupt is enabled. #1 MONOVEN Monitor Overrun interrupt Enable. 17 1 read-write 0 Disabled. The MonOv interrupt is disabled. #0 1 Enabled. The MonOv interrupt is enabled. #1 MONIDLEEN Monitor Idle interrupt Enable. 19 1 read-write 0 Disabled. The MonIdle interrupt is disabled. #0 1 Enabled. The MonIdle interrupt is enabled. #1 EVENTTIMEOUTEN Event time-out interrupt Enable. 24 1 read-write 0 Disabled. The Event time-out interrupt is disabled. #0 1 Enabled. The Event time-out interrupt is enabled. #1 SCLTIMEOUTEN SCL time-out interrupt Enable. 25 1 read-write 0 Disabled. The SCL time-out interrupt is disabled. #0 1 Enabled. The SCL time-out interrupt is enabled. #1 INTENCLR Interrupt Enable Clear register. 0xC 32 write-only 0 0 MSTPENDINGCLR Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented. 0 1 write-only MSTARBLOSSCLR Master Arbitration Loss interrupt clear. 4 1 write-only MSTSTSTPERRCLR Master Start/Stop Error interrupt clear. 6 1 write-only SLVPENDINGCLR Slave Pending interrupt clear. 8 1 write-only SLVNOTSTRCLR Slave Not Stretching interrupt clear. 11 1 write-only SLVDESELCLR Slave Deselect interrupt clear. 15 1 write-only MONRDYCLR Monitor data Ready interrupt clear. 16 1 write-only MONOVCLR Monitor Overrun interrupt clear. 17 1 write-only MONIDLECLR Monitor Idle interrupt clear. 19 1 write-only EVENTTIMEOUTCLR Event time-out interrupt clear. 24 1 write-only SCLTIMEOUTCLR SCL time-out interrupt clear. 25 1 write-only TIMEOUT Time-out value register. 0x10 32 read-write 0xFFFF 0xFFFF TOMIN Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks. 0 4 read-write TO Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock. 4 12 read-write CLKDIV Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. 0x14 32 read-write 0 0xFFFF DIVVAL This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is divided by 65,536 before use. 0 16 read-write INTSTAT Interrupt Status register for Master, Slave, and Monitor functions. 0x18 32 read-only 0x801 0x30FFF5F MSTPENDING Master Pending. 0 1 read-only MSTARBLOSS Master Arbitration Loss flag. 4 1 read-only MSTSTSTPERR Master Start/Stop Error flag. 6 1 read-only SLVPENDING Slave Pending. 8 1 read-only SLVNOTSTR Slave Not Stretching status. 11 1 read-only SLVDESEL Slave Deselected flag. 15 1 read-only MONRDY Monitor Ready. 16 1 read-only MONOV Monitor Overflow flag. 17 1 read-only MONIDLE Monitor Idle flag. 19 1 read-only EVENTTIMEOUT Event time-out Interrupt flag. 24 1 read-only SCLTIMEOUT SCL time-out Interrupt flag. 25 1 read-only MSTCTL Master control register. 0x20 32 read-write 0 0xF MSTCONTINUE Master Continue. 0 1 read-write 0 No effect. #0 1 Informs the Master function to continue to the next operation. #1 MSTSTART Master Start control. 1 1 read-write 0 No effect. #0 1 Start. A Start will be generated on the I2C bus at the next allowed time. #1 MSTSTOP Master Stop control. 2 1 read-write 0 No effect. #0 1 Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode). #1 MSTDMA Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write. 3 1 read-write 0 Disable. No DMA requests are generated for master operation. #0 1 Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. #1 MSTTIME Master timing configuration. 0x24 32 read-write 0x77 0x77 MSTSCLLOW Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW. 0 3 read-write 000 2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. #000 001 3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. #001 010 4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. #010 011 5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. #011 100 6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. #100 101 7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. #101 110 8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. #110 111 9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. #111 MSTSCLHIGH Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. 4 3 read-write 000 2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. #000 001 3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . #001 010 4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. #010 011 5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. #011 100 6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. #100 101 7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. #101 110 8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. #110 111 9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. #111 MSTDAT Combined Master receiver and transmitter data register. 0x28 32 read-write 0 0xFF DATA Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function. 0 8 read-write SLVCTL Slave control register. 0x40 32 read-write 0 0xB SLVCONTINUE Slave Continue. 0 1 read-write 0 No effect. #0 1 Informs the Slave function to continue to the next operation. #1 SLVNACK Slave NACK. 1 1 read-write 0 No effect. #0 1 NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). #1 SLVDMA Slave DMA enable. 3 1 read-write 0 Disabled. No DMA requests are issued for Slave mode operation. #0 1 Enabled. DMA requests are issued for I2C slave data transmission and reception. #1 SLVDAT Combined Slave receiver and transmitter data register. 0x44 32 read-write 0 0xFF DATA Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function. 0 8 read-write SLVADR0 Slave address register. 0x48 32 read-write 0x1 0xFF SADISABLE Slave Address n Disable. 0 1 read-write 0 Enabled. Slave Address n is enabled. #0 1 Ignored Slave Address n is ignored. #1 SLVADR Slave Address. Seven bit slave address that is compared to received addresses if enabled. 1 7 read-write SLVADR1 Slave address register. 0x4C 32 read-write 0x1 0xFF SADISABLE Slave Address n Disable. 0 1 read-write 0 Enabled. Slave Address n is enabled. #0 1 Ignored Slave Address n is ignored. #1 SLVADR Slave Address. Seven bit slave address that is compared to received addresses if enabled. 1 7 read-write SLVADR2 Slave address register. 0x50 32 read-write 0x1 0xFF SADISABLE Slave Address n Disable. 0 1 read-write 0 Enabled. Slave Address n is enabled. #0 1 Ignored Slave Address n is ignored. #1 SLVADR Slave Address. Seven bit slave address that is compared to received addresses if enabled. 1 7 read-write SLVADR3 Slave address register. 0x54 32 read-write 0x1 0xFF SADISABLE Slave Address n Disable. 0 1 read-write 0 Enabled. Slave Address n is enabled. #0 1 Ignored Slave Address n is ignored. #1 SLVADR Slave Address. Seven bit slave address that is compared to received addresses if enabled. 1 7 read-write SLVQUAL0 Slave Qualification for address 0. 0x58 32 read-write 0 0xFF QUALMODE0 Qualify mode for slave address 0. 0 1 read-write 0 Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. #0 1 Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. #1 SLVQUAL0 Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]). 1 7 read-write MONRXDAT Monitor receiver data register. 0x80 32 read-only 0 0x7FF MONRXDAT Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins. 0 8 read-only MONSTART Monitor Received Start. 8 1 read-only 0 No start detected. The Monitor function has not detected a Start event on the I2C bus. #0 1 Start detected. The Monitor function has detected a Start event on the I2C bus. #1 MONRESTART Monitor Received Repeated Start. 9 1 read-only 0 No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. #0 1 Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. #1 MONNACK Monitor Received NACK. 10 1 read-only 0 Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver. #0 1 Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver. #1 I2C1 LPC84x I2C-bus interfaces I2C 0x40054000 0 0x84 registers I2C1 7 CFG Configuration for shared functions. 0 32 read-write 0 0x3F MSTEN Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset. 0 1 read-write 0 Disabled. The I2C Master function is disabled. #0 1 Enabled. The I2C Master function is enabled. #1 SLVEN Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset. 1 1 read-write 0 Disabled. The I2C slave function is disabled. #0 1 Enabled. The I2C slave function is enabled. #1 MONEN Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset. 2 1 read-write 0 Disabled. The I2C Monitor function is disabled. #0 1 Enabled. The I2C Monitor function is enabled. #1 TIMEOUTEN I2C bus Time-out Enable. When disabled, the time-out function is internally reset. 3 1 read-write 0 Disabled. Time-out function is disabled. #0 1 Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system. #1 MONCLKSTR Monitor function Clock Stretching. 4 1 read-write 0 Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical. #0 1 Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function. #1 STAT Status register for Master, Slave, and Monitor functions. 0x4 32 read-write 0x801 0x30FFF5F MSTPENDING Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt. 0 1 read-only 0 In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. #0 1 Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit. #1 MSTSTATE Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses. 1 3 read-only 000 Idle. The Master function is available to be used for a new transaction. #000 001 Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. #001 010 Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. #010 011 NACK Address. Slave NACKed address. #011 100 NACK Data. Slave NACKed transmitted data. #100 MSTARBLOSS Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. 4 1 read-write 0 No Arbitration Loss has occurred. #0 1 Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. #1 MSTSTSTPERR Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. 6 1 read-write 0 No Start/Stop Error has occurred. #0 1 The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled. #1 SLVPENDING Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched. 8 1 read-only 0 In progress. The Slave function does not currently need service. #0 1 Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. #1 SLVSTATE Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes. 9 2 read-only 00 Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. #00 01 Slave receive. Received data is available (Slave Receiver mode). #01 10 Slave transmit. Data can be transmitted (Slave Transmitter mode). #10 SLVNOTSTR Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time. 11 1 read-only 0 Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. #0 1 Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time. #1 SLVIDX Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here. 12 2 read-only 00 Address 0. Slave address 0 was matched. #00 01 Address 1. Slave address 1 was matched. #01 10 Address 2. Slave address 2 was matched. #10 11 Address 3. Slave address 3 was matched. #11 SLVSEL Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data. 14 1 read-only 0 Not selected. The Slave function is not currently selected. #0 1 Selected. The Slave function is currently selected. #1 SLVDESEL Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit. 15 1 read-write 0 Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag. #0 1 Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. #1 MONRDY Monitor Ready. This flag is cleared when the MONRXDAT register is read. 16 1 read-only 0 No data. The Monitor function does not currently have data available. #0 1 Data waiting. The Monitor function has data waiting to be read. #1 MONOV Monitor Overflow flag. 17 1 read-write 0 No overrun. Monitor data has not overrun. #0 1 Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. #1 MONACTIVE Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop. 18 1 read-only 0 Inactive. The Monitor function considers the I2C bus to be inactive. #0 1 Active. The Monitor function considers the I2C bus to be active. #1 MONIDLE Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit. 19 1 read-write 0 Not idle. The I2C bus is not idle, or this flag has been cleared by software. #0 1 Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. #1 EVENTTIMEOUT Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle. 24 1 read-write 0 No time-out. I2C bus events have not caused a time-out. #0 1 Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. #1 SCLTIMEOUT SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. 25 1 read-write 0 No time-out. SCL low time has not caused a time-out. #0 1 Time-out. SCL low time has caused a time-out. #1 INTENSET Interrupt Enable Set and read register. 0x8 32 read-write 0 0x30B8951 MSTPENDINGEN Master Pending interrupt Enable. 0 1 read-write 0 Disabled. The MstPending interrupt is disabled. #0 1 Enabled. The MstPending interrupt is enabled. #1 MSTARBLOSSEN Master Arbitration Loss interrupt Enable. 4 1 read-write 0 Disabled. The MstArbLoss interrupt is disabled. #0 1 Enabled. The MstArbLoss interrupt is enabled. #1 MSTSTSTPERREN Master Start/Stop Error interrupt Enable. 6 1 read-write 0 Disabled. The MstStStpErr interrupt is disabled. #0 1 Enabled. The MstStStpErr interrupt is enabled. #1 SLVPENDINGEN Slave Pending interrupt Enable. 8 1 read-write 0 Disabled. The SlvPending interrupt is disabled. #0 1 Enabled. The SlvPending interrupt is enabled. #1 SLVNOTSTREN Slave Not Stretching interrupt Enable. 11 1 read-write 0 Disabled. The SlvNotStr interrupt is disabled. #0 1 Enabled. The SlvNotStr interrupt is enabled. #1 SLVDESELEN Slave Deselect interrupt Enable. 15 1 read-write 0 Disabled. The SlvDeSel interrupt is disabled. #0 1 Enabled. The SlvDeSel interrupt is enabled. #1 MONRDYEN Monitor data Ready interrupt Enable. 16 1 read-write 0 Disabled. The MonRdy interrupt is disabled. #0 1 Enabled. The MonRdy interrupt is enabled. #1 MONOVEN Monitor Overrun interrupt Enable. 17 1 read-write 0 Disabled. The MonOv interrupt is disabled. #0 1 Enabled. The MonOv interrupt is enabled. #1 MONIDLEEN Monitor Idle interrupt Enable. 19 1 read-write 0 Disabled. The MonIdle interrupt is disabled. #0 1 Enabled. The MonIdle interrupt is enabled. #1 EVENTTIMEOUTEN Event time-out interrupt Enable. 24 1 read-write 0 Disabled. The Event time-out interrupt is disabled. #0 1 Enabled. The Event time-out interrupt is enabled. #1 SCLTIMEOUTEN SCL time-out interrupt Enable. 25 1 read-write 0 Disabled. The SCL time-out interrupt is disabled. #0 1 Enabled. The SCL time-out interrupt is enabled. #1 INTENCLR Interrupt Enable Clear register. 0xC 32 write-only 0 0 MSTPENDINGCLR Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented. 0 1 write-only MSTARBLOSSCLR Master Arbitration Loss interrupt clear. 4 1 write-only MSTSTSTPERRCLR Master Start/Stop Error interrupt clear. 6 1 write-only SLVPENDINGCLR Slave Pending interrupt clear. 8 1 write-only SLVNOTSTRCLR Slave Not Stretching interrupt clear. 11 1 write-only SLVDESELCLR Slave Deselect interrupt clear. 15 1 write-only MONRDYCLR Monitor data Ready interrupt clear. 16 1 write-only MONOVCLR Monitor Overrun interrupt clear. 17 1 write-only MONIDLECLR Monitor Idle interrupt clear. 19 1 write-only EVENTTIMEOUTCLR Event time-out interrupt clear. 24 1 write-only SCLTIMEOUTCLR SCL time-out interrupt clear. 25 1 write-only TIMEOUT Time-out value register. 0x10 32 read-write 0xFFFF 0xFFFF TOMIN Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks. 0 4 read-write TO Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock. 4 12 read-write CLKDIV Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. 0x14 32 read-write 0 0xFFFF DIVVAL This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is divided by 65,536 before use. 0 16 read-write INTSTAT Interrupt Status register for Master, Slave, and Monitor functions. 0x18 32 read-only 0x801 0x30FFF5F MSTPENDING Master Pending. 0 1 read-only MSTARBLOSS Master Arbitration Loss flag. 4 1 read-only MSTSTSTPERR Master Start/Stop Error flag. 6 1 read-only SLVPENDING Slave Pending. 8 1 read-only SLVNOTSTR Slave Not Stretching status. 11 1 read-only SLVDESEL Slave Deselected flag. 15 1 read-only MONRDY Monitor Ready. 16 1 read-only MONOV Monitor Overflow flag. 17 1 read-only MONIDLE Monitor Idle flag. 19 1 read-only EVENTTIMEOUT Event time-out Interrupt flag. 24 1 read-only SCLTIMEOUT SCL time-out Interrupt flag. 25 1 read-only MSTCTL Master control register. 0x20 32 read-write 0 0xF MSTCONTINUE Master Continue. 0 1 read-write 0 No effect. #0 1 Informs the Master function to continue to the next operation. #1 MSTSTART Master Start control. 1 1 read-write 0 No effect. #0 1 Start. A Start will be generated on the I2C bus at the next allowed time. #1 MSTSTOP Master Stop control. 2 1 read-write 0 No effect. #0 1 Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode). #1 MSTDMA Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write. 3 1 read-write 0 Disable. No DMA requests are generated for master operation. #0 1 Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. #1 MSTTIME Master timing configuration. 0x24 32 read-write 0x77 0x77 MSTSCLLOW Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW. 0 3 read-write 000 2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. #000 001 3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. #001 010 4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. #010 011 5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. #011 100 6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. #100 101 7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. #101 110 8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. #110 111 9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. #111 MSTSCLHIGH Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. 4 3 read-write 000 2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. #000 001 3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . #001 010 4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. #010 011 5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. #011 100 6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. #100 101 7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. #101 110 8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. #110 111 9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. #111 MSTDAT Combined Master receiver and transmitter data register. 0x28 32 read-write 0 0xFF DATA Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function. 0 8 read-write SLVCTL Slave control register. 0x40 32 read-write 0 0xB SLVCONTINUE Slave Continue. 0 1 read-write 0 No effect. #0 1 Informs the Slave function to continue to the next operation. #1 SLVNACK Slave NACK. 1 1 read-write 0 No effect. #0 1 NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). #1 SLVDMA Slave DMA enable. 3 1 read-write 0 Disabled. No DMA requests are issued for Slave mode operation. #0 1 Enabled. DMA requests are issued for I2C slave data transmission and reception. #1 SLVDAT Combined Slave receiver and transmitter data register. 0x44 32 read-write 0 0xFF DATA Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function. 0 8 read-write SLVADR0 Slave address register. 0x48 32 read-write 0x1 0xFF SADISABLE Slave Address n Disable. 0 1 read-write 0 Enabled. Slave Address n is enabled. #0 1 Ignored Slave Address n is ignored. #1 SLVADR Slave Address. Seven bit slave address that is compared to received addresses if enabled. 1 7 read-write SLVADR1 Slave address register. 0x4C 32 read-write 0x1 0xFF SADISABLE Slave Address n Disable. 0 1 read-write 0 Enabled. Slave Address n is enabled. #0 1 Ignored Slave Address n is ignored. #1 SLVADR Slave Address. Seven bit slave address that is compared to received addresses if enabled. 1 7 read-write SLVADR2 Slave address register. 0x50 32 read-write 0x1 0xFF SADISABLE Slave Address n Disable. 0 1 read-write 0 Enabled. Slave Address n is enabled. #0 1 Ignored Slave Address n is ignored. #1 SLVADR Slave Address. Seven bit slave address that is compared to received addresses if enabled. 1 7 read-write SLVADR3 Slave address register. 0x54 32 read-write 0x1 0xFF SADISABLE Slave Address n Disable. 0 1 read-write 0 Enabled. Slave Address n is enabled. #0 1 Ignored Slave Address n is ignored. #1 SLVADR Slave Address. Seven bit slave address that is compared to received addresses if enabled. 1 7 read-write SLVQUAL0 Slave Qualification for address 0. 0x58 32 read-write 0 0xFF QUALMODE0 Qualify mode for slave address 0. 0 1 read-write 0 Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. #0 1 Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. #1 SLVQUAL0 Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]). 1 7 read-write MONRXDAT Monitor receiver data register. 0x80 32 read-only 0 0x7FF MONRXDAT Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins. 0 8 read-only MONSTART Monitor Received Start. 8 1 read-only 0 No start detected. The Monitor function has not detected a Start event on the I2C bus. #0 1 Start detected. The Monitor function has detected a Start event on the I2C bus. #1 MONRESTART Monitor Received Repeated Start. 9 1 read-only 0 No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. #0 1 Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. #1 MONNACK Monitor Received NACK. 10 1 read-only 0 Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver. #0 1 Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver. #1 CTIMER0 LPC184 Standard counter/timer 0x40038000 0 0x88 registers CTIMER0 23 IR Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. 0 32 read-write 0 0xFF MR0INT Interrupt flag for match channel 0. 0 1 read-write MR1INT Interrupt flag for match channel 1. 1 1 read-write MR2INT Interrupt flag for match channel 2. 2 1 read-write MR3INT Interrupt flag for match channel 3. 3 1 read-write CR0INT Interrupt flag for capture channel 0 event. 4 1 read-write CR1INT Interrupt flag for capture channel 1 event. 5 1 read-write CR2INT Interrupt flag for capture channel 2 event. 6 1 read-write CR3INT Interrupt flag for capture channel 3 event. 7 1 read-write TCR Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. 0x4 32 read-write 0 0x3 CEN Counter enable. 0 1 read-write 0 Disabled.The counters are disabled. #0 1 Enabled. The Timer Counter and Prescale Counter are enabled. #1 CRST Counter reset. 1 1 read-write 0 Disabled. Do nothing. #0 1 Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of the APB bus clock. The counters remain reset until TCR[1] is returned to zero. #1 TC Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR. 0x8 32 read-write 0 0xFFFFFFFF TCVAL Timer counter value. 0 32 read-write PR Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC. 0xC 32 read-write 0 0xFFFFFFFF PRVAL Prescale counter value. 0 32 read-write PC Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. 0x10 32 read-write 0 0xFFFFFFFF PCVAL Prescale counter value. 0 32 read-write MCR Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. 0x14 32 read-write 0 0xF000FFF MR0I Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 = disabled. 1 = enabled. 0 1 read-write MR0R Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled. 1 1 read-write MR0S Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled. 2 1 read-write MR1I Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 = disabled. 1 = enabled. 0 = disabled. 1 = enabled. 3 1 read-write MR1R Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled. 4 1 read-write MR1S Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled. 5 1 read-write MR2I Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled. 6 1 read-write MR2R Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled. 7 1 read-write MR2S Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled. 8 1 read-write MR3I Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled. 9 1 read-write MR3R Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled. 10 1 read-write MR3S Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled. 11 1 read-write MR0RL Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled. 24 1 read-write MR1RL Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled. 25 1 read-write MR2RL Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled. 26 1 read-write MR3RL Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled. 27 1 read-write MR0 Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. 0x18 32 read-write 0 0xFFFFFFFF MATCH Timer counter match value. 0 32 read-write MR1 Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. 0x1C 32 read-write 0 0xFFFFFFFF MATCH Timer counter match value. 0 32 read-write MR2 Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. 0x20 32 read-write 0 0xFFFFFFFF MATCH Timer counter match value. 0 32 read-write MR3 Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. 0x24 32 read-write 0 0xFFFFFFFF MATCH Timer counter match value. 0 32 read-write CCR Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. 0x28 32 read-write 0 0xFFF CAP0RE Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. 0 1 read-write CAP0FE Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. 1 1 read-write CAP0I Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt. 2 1 read-write CAP1RE Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. 3 1 read-write CAP1FE Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. 4 1 read-write CAP1I Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt. 5 1 read-write CAP2RE Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. 6 1 read-write CAP2FE Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. 7 1 read-write CAP2I Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt. 8 1 read-write CAP3RE Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. 9 1 read-write CAP3FE Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. 10 1 read-write CAP3I Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt. 11 1 read-write CR0 Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. 0x2C 32 read-only 0 0xFFFFFFFF CAP Timer counter capture value. 0 32 read-only CR1 Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. 0x30 32 read-only 0 0xFFFFFFFF CAP Timer counter capture value. 0 32 read-only CR2 Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. 0x34 32 read-only 0 0xFFFFFFFF CAP Timer counter capture value. 0 32 read-only CR3 Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. 0x38 32 read-only 0 0xFFFFFFFF CAP Timer counter capture value. 0 32 read-only EMR External Match Register. The EMR controls the match function and the external match pins. 0x3C 32 read-write 0 0xFFF EM0 External Match 0. This bit reflects the state of output MAT0, whether or not this output is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. 0 1 read-write EM1 External Match 1. This bit reflects the state of output MAT1, whether or not this output is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. 1 1 read-write EM2 External Match 2. This bit reflects the state of output MAT2, whether or not this output is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. 2 1 read-write EM3 External Match 3. This bit reflects the state of output MAT3, whether or not this output is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. 3 1 read-write EMC0 External Match Control 0. Determines the functionality of External Match 0. 4 2 read-write 00 Do Nothing. #00 01 Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out). #01 10 Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out). #10 11 Toggle. Toggle the corresponding External Match bit/output. #11 EMC1 External Match Control 1. Determines the functionality of External Match 1. 6 2 read-write 00 Do Nothing. #00 01 Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out). #01 10 Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out). #10 11 Toggle. Toggle the corresponding External Match bit/output. #11 EMC2 External Match Control 2. Determines the functionality of External Match 2. 8 2 read-write 00 Do Nothing. #00 01 Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out). #01 10 Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out). #10 11 Toggle. Toggle the corresponding External Match bit/output. #11 EMC3 External Match Control 3. Determines the functionality of External Match 3. 10 2 read-write 00 Do Nothing. #00 01 Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out). #01 10 Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out). #10 11 Toggle. Toggle the corresponding External Match bit/output. #11 CTCR Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. 0x70 32 read-write 0 0xFF CTMODE Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. 0 2 read-write 00 Timer Mode. Incremented every rising APB bus clock edge. #00 01 Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. #01 10 Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. #10 11 Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. #11 CINSEL Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. 2 2 read-write 00 Channel 0. CAPn.0 for CTIMERn #00 01 Channel 1. CAPn.1 for CTIMERn #01 10 Channel 2. CAPn.2 for CTIMERn #10 11 Channel 3. CAPn.3 for CTIMERn #11 ENCC Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs. 4 1 read-write SELCC Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved. 5 3 read-write 000 Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set). #000 001 Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set). #001 010 Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set). #010 011 Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set). #011 100 Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). #100 101 Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). #101 110 Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). #110 111 Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). #111 PWMC PWM Control Register. The PWMCON enables PWM mode for the external match pins. 0x74 32 read-write 0 0xF PWMEN0 PWM mode enable for channel0. 0 1 read-write 0 Match. CTIMERn_MAT0 is controlled by EM0. #0 1 PWM. PWM mode is enabled for CTIMERn_MAT0. #1 PWMEN1 PWM mode enable for channel1. 1 1 read-write 0 Match. CTIMERn_MAT01 is controlled by EM1. #0 1 PWM. PWM mode is enabled for CTIMERn_MAT1. #1 PWMEN2 PWM mode enable for channel2. 2 1 read-write 0 Match. CTIMERn_MAT2 is controlled by EM2. #0 1 PWM. PWM mode is enabled for CTIMERn_MAT2. #1 PWMEN3 PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. 3 1 read-write 0 Match. CTIMERn_MAT3 is controlled by EM3. #0 1 PWM. PWM mode is enabled for CT132Bn_MAT3. #1 MSR0 Match Shadow Register . If enabled, the Match Register will be automatically reloaded with the contents of this register whenever the TC is reset to zero. 0x78 32 read-write 0 0xFFFFFFFF MATCH_SHADOW Timer counter match value. 0 32 read-write MSR1 Match Shadow Register . If enabled, the Match Register will be automatically reloaded with the contents of this register whenever the TC is reset to zero. 0x7C 32 read-write 0 0xFFFFFFFF MATCH_SHADOW Timer counter match value. 0 32 read-write MSR2 Match Shadow Register . If enabled, the Match Register will be automatically reloaded with the contents of this register whenever the TC is reset to zero. 0x80 32 read-write 0 0xFFFFFFFF MATCH_SHADOW Timer counter match value. 0 32 read-write MSR3 Match Shadow Register . If enabled, the Match Register will be automatically reloaded with the contents of this register whenever the TC is reset to zero. 0x84 32 read-write 0 0xFFFFFFFF MATCH_SHADOW Timer counter match value. 0 32 read-write FLASH_CTRL LPC84x NVMC flash controller 0x40040000 0x10 0xFDC registers FLASH 14 FLASHCFG Flash configuration register 0x10 32 read-write 0x2 0x3 FLASHTIM Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access. 0 2 read-write 00 1 system clock flash access time. #00 01 2 system clock flash access time. #01 10 3 system clock flash access time. #10 FMSSTART Flash signature start address register 0x20 32 read-write 0 0x1FFFF START Signature generation start address (corresponds to AHB byte address bits[18:2]). 0 17 read-write FMSSTOP Flash signaure stop address register 0x24 32 read-write 0 0x8001FFFF STOPA Stop address for signature generation (the word specified by STOP is included in the address range). The address is in units of memory words, not bytes. 0 17 read-write STRTBIST When this bit is written to 1, signature generation starts. At the end of signature generation, this bit is automatically cleared. 31 1 read-write FMSW0 Flash signature generation result register returns the flash signature produced by the embedded signature generator.. 0x2C 32 read-only 0 0 SIG 32-bit signature. 0 32 read-only FMSTAT Flash signature generation status bit 0xFE0 32 read-only 0 0xFFFFFFFF SIG_DONE This status bit is set at the end of signature computation 1 1 read-only FMSTATCLR Clear FLASH signature generation status bit 0xFE8 32 write-only 0 0xFFFFFFFF SIG_DONE_CLR When the bit is written to 1, the SIGNATURE_DONE bit is cleared. 1 1 write-only IOCON LPC84x I/O pin configuration (IOCON) 0x40044000 0 0xE0 registers PIO0_17 Digital I/O control for pins PIO0_17 0 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 DACMODE DAC mode enable. 16 1 read-write 0 Disable. #0 1 Enable. #1 PIO0_13 Digital I/O control for pins PIO0_13 0x4 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO0_12 Digital I/O control for pins PIO0_12 0x8 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO0_5 Digital I/O control for pins PIO0_5 0xC 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO0_4 Digital I/O control for pins PIO0_4 0x10 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO0_3 Digital I/O control for pins PIO0_3 0x14 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO0_2 Digital I/O control for pins PIO0_2 0x18 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO0_11 Digital I/O control for pins PIO0_11 0x1C 32 read-write 0x80 0xFBFF INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 I2CMODE Selects I2C mode. 8 2 read-write 00 Standard mode/ Fast-mode I2C. #00 01 Standard GPIO functionality. Requires external pull-up for GPIO output function. #01 10 Fast-mode Plus I2C #10 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO0_10 Digital I/O control for pins PIO0_10 0x20 32 read-write 0x80 0xFBFF INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 I2CMODE Selects I2C mode. 8 2 read-write 00 Standard mode/ Fast-mode I2C. #00 01 Standard GPIO functionality. Requires external pull-up for GPIO output function. #01 10 Fast-mode Plus I2C #10 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO0_16 Digital I/O control for pins PIO0_16 0x24 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO0_15 Digital I/O control for pins PIO0_15 0x28 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO0_1 Digital I/O control for pins PIO0_1 0x2C 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO0_9 Digital I/O control for pins PIO0_9 0x34 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO0_8 Digital I/O control for pins PIO0_8 0x38 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO0_7 Digital I/O control for pins PIO0_7 0x3C 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO0_6 Digital I/O control for pins PIO0_6 0x40 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO0_0 Digital I/O control for pins PIO0_0 0x44 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO0_14 Digital I/O control for pins PIO0_14 0x48 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO0_28 Digital I/O control for pins PIO0_28 0x50 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO0_27 Digital I/O control for pins PIO0_27 0x54 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO0_26 Digital I/O control for pins PIO0_26 0x58 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO0_25 Digital I/O control for pins PIO0_25 0x5C 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO0_24 Digital I/O control for pins PIO0_24 0x60 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO0_23 Digital I/O control for pins PIO0_23 0x64 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO0_22 Digital I/O control for pins PIO0_22 0x68 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO0_21 Digital I/O control for pins PIO0_21 0x6C 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO0_20 Digital I/O control for pins PIO0_20 0x70 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO0_19 Digital I/O control for pins PIO0_19 0x74 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO0_18 Digital I/O control for pins PIO0_18 0x78 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO1_8 Digital I/O control for pins PIO1_8 0x7C 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO1_9 Digital I/O control for pins PIO1_9 0x80 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO1_12 Digital I/O control for pins PIO1_12 0x84 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO1_13 Digital I/O control for pins PIO1_13 0x88 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO0_31 Digital I/O control for pins PIO0_31 0x8C 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO1_0 Digital I/O control for pins PIO1_0 0x90 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO1_1 Digital I/O control for pins PIO1_1 0x94 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO1_2 Digital I/O control for pins PIO1_2 0x98 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO1_14 Digital I/O control for pins PIO1_14 0x9C 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO1_15 Digital I/O control for pins PIO1_15 0xA0 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO1_3 Digital I/O control for pins PIO1_3 0xA4 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO1_4 Digital I/O control for pins PIO1_4 0xA8 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO1_5 Digital I/O control for pins PIO1_5 0xAC 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO1_16 Digital I/O control for pins PIO1_16 0xB0 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO1_17 Digital I/O control for pins PIO1_17 0xB4 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO1_6 Digital I/O control for pins PIO1_6 0xB8 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO1_18 Digital I/O control for pins PIO1_18 0xBC 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO1_19 Digital I/O control for pins PIO1_19 0xC0 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO1_7 Digital I/O control for pins PIO1_7 0xC4 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO0_29 Digital I/O control for pins PIO0_29 0xC8 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO0_30 Digital I/O control for pins PIO0_30 0xCC 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO1_20 Digital I/O control for pins PIO1_20 0xD0 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO1_21 Digital I/O control for pins PIO1_21 0xD4 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO1_11 Digital I/O control for pins PIO1_11 0xD8 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 PIO1_10 Digital I/O control for pins PIO1_10 0xDC 32 read-write 0xB0 0xFFFFFFFF MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 2 read-write 00 Inactive. Inactive (no pull-down/pull-up resistor enabled). #00 01 Pull-down. Pull-down resistor enabled. #01 10 Pull-up. Pull-up resistor enabled. #10 11 Repeater. Repeater mode. #11 HYS Hysteresis. 5 1 read-write 0 Disable #0 1 Enable #1 INV Invert input 6 1 read-write 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). #0 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). #1 OD Open-drain mode. 10 1 read-write 0 Disable. #0 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. #1 S_MODE Digital filter sample mode. 11 2 read-write 00 Bypass input filter. #00 01 1 clock cycle. Input pulses shorter than one filter clock are rejected. #01 10 2 clock cycles. Input pulses shorter than two filter clocks are rejected. #10 11 3 clock cycles. Input pulses shorter than three filter clocks are rejected. #11 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 13 3 read-write 000 IOCONCLKDIV0 #000 001 IOCONCLKDIV1 #001 010 IOCONCLKDIV2 #010 011 IOCONCLKDIV3 #011 100 IOCONCLKDIV4 #100 101 IOCONCLKDIV5 #101 110 IOCONCLKDIV6 #110 SYSCON LPC84x System configuration (SYSCON) 0x40048000 0 0x3FC registers BOD 13 SYSMEMREMAP System Remap register 0 32 read-write 0x2 0x3 MAP System memory remap. Value 0x3 is reserved. 0 2 read-write 00 Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM. #00 01 User RAM Mode. Interrupt vectors are re-mapped to Static RAM. #01 10 User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash. #10 SYSPLLCTRL PLL control 0x8 32 read-write 0 0x7F MSEL Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32 0 5 read-write PSEL Post divider ratio P. The division ratio is 2 x P. 5 2 read-write 00 P = 1 #00 01 P = 2 #01 10 P = 4 #10 11 P = 8 #11 SYSPLLSTAT PLL status 0xC 32 read-only 0 0x1 LOCK PLL0 lock indicator 0 1 read-only SYSOSCCTRL system oscillator control 0x20 32 read-write 0 0xFFFFFFFF BYPASS oscillator (Xtal) Test Mode input (Active High) 0 1 read-write FREQRANGE oscillator low / high transconductance selection input (Active High) 1-20MHz '0' : 15-50MHz '1' 1 1 read-write WDTOSCCTRL Watchdog oscillator control 0x24 32 read-write 0 0xFFFFFFFF DIVSEL Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64 0 5 read-write FREQSEL Frequency select. Selects the frequency of the oscillator. 0x00 = invalid setting when watchdog oscillator is running 0x1 = 0.6 MHz 0x2 = 1.05 MHz 0x3 = 1.4 MHz 0x4 = 1.75 MHz 0x5 = 2.1 MHz 0x6 = 2.4 MHz 0x7 = 2.7 MHz 0x8 = 3.0 MHz 0x9 = 3.25 MHz 0xA = 3.5 MHz 0xB = 3.75 MHz 0xC = 4.0 MHz 0xD = 4.2 MHz 0xE = 4.4 MHz 0xF = 4.6 MHz 5 4 read-write FROOSCCTRL FRO oscillator control 0x28 32 read-write 0 0xFFFFFFFF FRO_DIRECT fro direct clock select 17 1 read-write 0 fro clock is divider by 2 or 16,depend on FAIM slow boot value #0 1 fro clock is direct from FRO oscillator #1 FRODIRECTCLKUEN FRO direct clock source update enable register 0x30 32 read-write 0 0x1 ENA Enable fro clock source update 0 1 read-write 0 no change #0 1 update clock source #1 SYSRSTSTAT System reset status register 0x38 32 read-write 0 0x1F POR POR reset status 0 1 read-write 0 No POR detected #0 1 POR detected. Writing a one clears this reset. #1 EXTRST Status of the external RESET pin. External reset status. 1 1 read-write 0 No reset event detected. #0 1 Reset detected. Writing a one clears this reset. #1 WDT Status of the Watchdog reset 2 1 read-write 0 No WDT reset detected #0 1 WDT reset detected. Writing a one clears this reset. #1 BOD Status of the Brown-out detect reset 3 1 read-write 0 No BOD reset detected #0 1 BOD reset detected. Writing a one clears this reset. #1 SYSRST Status of the software system reset 4 1 read-write 0 No System reset detected #0 1 System reset detected. Writing a one clears this reset. #1 SYSPLLCLKSEL System PLL clock source select register 0x40 32 read-write 0 0x3 SEL System PLL clock source 0 2 read-write 00 FRO #00 01 External clock #01 10 Watchdog oscillator #10 11 FRO DIV #11 SYSPLLCLKUEN System PLL clock source update enable register 0x44 32 read-write 0 0x1 ENA Enable system PLL clock source update 0 1 read-write 0 no change #0 1 update clock source #1 MAINCLKPLLSEL Main clock source select register 0x48 32 read-write 0 0x3 SEL System PLL clock source 0 2 read-write 00 main_clk_pre_pll #00 01 sys pll #01 10 none #10 11 none #11 MAINCLKPLLUEN Main clock source update enable register 0x4C 32 read-write 0 0x1 ENA Enable main clock source update 0 1 read-write 0 no change #0 1 update clock source #1 MAINCLKSEL Main clock source select register 0x50 32 read-write 0 0x3 SEL System PLL clock source 0 2 read-write 00 FRO #00 01 External clock #01 10 Watchdog oscillator #10 11 FRO_DIV #11 MAINCLKUEN Main clock source update enable register 0x54 32 read-write 0 0x1 ENA Enable main clock source update 0 1 read-write 0 no change #0 1 update clock source #1 SYSAHBCLKDIV System clock divider register 0x58 32 read-write 0x1 0xFF DIV System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255. 0 8 read-write CAPTCLKSEL CAPT clock source select register 0x60 32 read-write 0x7 0x7 SEL Clock source for CAPT clock 0 3 read-write 000 FRO #000 001 main clock #001 010 sys pll #010 011 FRO_DIV #011 100 Watchdog oscillator #100 101 None #101 110 None #110 111 None #111 ADCCLKSEL ADC clock source select register 0x64 32 read-write 0 0x3 SEL Clock source for ADC clock 0 2 read-write 00 FRO #00 01 sys pll #01 10 none #10 11 none #11 ADCCLKDIV ADC clock divider register 0x68 32 read-write 0 0xFF DIV ADC clock divider values 0: ADC clock disabled. 1: Divide by 1. to 255: Divide by 255. 0 8 read-write SCTCLKSEL SCT clock source select register 0x6C 32 read-write 0 0x3 SEL Clock source for SCT clock 0 2 read-write 00 FRO #00 01 main clock #01 10 sys pll #10 11 none #11 SCTCLKDIV SCT clock divider register 0x70 32 read-write 0 0xFF DIV SCT clock divider values 0: SCT clock disabled. 1: Divide by 1. to 255: Divide by 255. 0 8 read-write EXTCLKSEL external clock source select register 0x74 32 read-write 0 0x1 SEL Clock source for external clock 0 1 read-write 0 System oscillator #0 1 Clk_in #1 SYSAHBCLKCTRL0 System clock group 0 control register 0x80 32 read-write 0x17 0xFFFFFFFF SYS Enables the clock for the AHB, the APB bridge, the Cortex-M0+ core clocks, SYSCON, and the PMU. This bit is read only and always reads as 1. 0 1 read-write ROM Enables clock for ROM. 1 1 read-write 0 disable #0 1 enable #1 RAM0_1 Enables clock for SRAM0 and SRAM1. 2 1 read-write 0 disable #0 1 enable #1 FLASH Enables clock for flash. 4 1 read-write 0 disable #0 1 enable #1 I2C0 Enables clock for I2C0. 5 1 read-write 0 disable #0 1 enable #1 GPIO0 Enables clock for GPIO0 port registers. 6 1 read-write 0 disable #0 1 enable #1 SWM Enables clock for switch matrix. 7 1 read-write 0 disable #0 1 enable #1 SCT Enables clock for state configurable timer SCTimer/PWM. 8 1 read-write 0 disable #0 1 enable #1 WKT Enables clock for self-wake-up timer. 9 1 read-write 0 disable #0 1 enable #1 MRT Enables clock for multi-rate timer. 10 1 read-write 0 disable #0 1 enable #1 SPI0 Enables clock for SPI0. 11 1 read-write 0 disable #0 1 enable #1 SPI1 Enables clock for SPI1. 12 1 read-write 0 disable #0 1 enable #1 CRC Enables clock for CRC. 13 1 read-write 0 disable #0 1 enable #1 UART0 Enables clock for UART0. 14 1 read-write 0 disable #0 1 enable #1 UART1 Enables clock for UART1. 15 1 read-write 0 disable #0 1 enable #1 UART2 Enables clock for UART2. 16 1 read-write 0 disable #0 1 enable #1 WWDT Enables clock for WWDT. 17 1 read-write 0 disable #0 1 enable #1 IOCON Enables clock for IOCON. 18 1 read-write 0 disable #0 1 enable #1 ACMP Enables clock for analog comparator. 19 1 read-write 0 disable #0 1 enable #1 GPIO1 Enables clock for GPIO1 port registers. 20 1 read-write 0 disable #0 1 enable #1 I2C1 Enables clock for I2C1. 21 1 read-write 0 disable #0 1 enable #1 I2C2 Enables clock for I2C2. 22 1 read-write 0 disable #0 1 enable #1 I2C3 Enables clock for I2C3. 23 1 read-write 0 disable #0 1 enable #1 ADC Enables clock for ADC. 24 1 read-write 0 disable #0 1 enable #1 CTIMER Enables clock for CTIMER. 25 1 read-write 0 disable #0 1 enable #1 MTB Enables clock to micro-trace buffer control registers. Turn on this clock when using the micro-trace buffer for debug purposes. 26 1 read-write 0 disable #0 1 enable #1 DAC0 Enables clock for DAC0. 27 1 read-write 0 disable #0 1 enable #1 GPIO_INT Enable clock for GPIO pin interrupt registers 28 1 read-write 0 disable #0 1 enable #1 DMA Enables clock for DMA. 29 1 read-write 0 disable #0 1 enable #1 UART3 Enables clock for UART3. 30 1 read-write 0 disable #0 1 enable #1 UART4 Enables clock for UART4. 31 1 read-write 0 disable #0 1 enable #1 SYSAHBCLKCTRL1 System clock group 1 control register 0x84 32 read-write 0 0x3 CAPT Enables clock for CAPT. 0 1 read-write 0 disable #0 1 enable #1 DAC1 Enables clock for DAC1. 1 1 read-write 0 disable #0 1 enable #1 PRESETCTRL0 Peripheral reset group 0 control register 0x88 32 read-write 0xFBFDFFF0 0xFBFDFFF0 FLASH_RST_N flash controller reset control 4 1 read-write 0 Assert the flash controller reset. #0 1 Clear the flash controller reset. #1 I2C0_RST_N I2C0 reset control 5 1 read-write 0 Assert the I2C0 reset. #0 1 Clear the I2C0 reset. #1 GPIO0_RST_N GPIO0 reset control 6 1 read-write 0 Assert the GPIO0 reset. #0 1 Clear the GPIO0 reset. #1 SWM_RST_N SWM reset control 7 1 read-write 0 Assert the SWM reset. #0 1 Clear the SWM reset. #1 SCT_RST_N SCT reset control 8 1 read-write 0 Assert the SCT reset. #0 1 Clear the SCT reset. #1 WKT_RST_N Self-wake-up timer (WKT) reset control 9 1 read-write 0 Assert the WKT reset. #0 1 Clear the WKT reset. #1 MRT_RST_N Multi-rate timer (MRT) reset control 10 1 read-write 0 Assert the MRT reset. #0 1 Clear the MRT reset. #1 SPI0_RST_N SPI0 reset control 11 1 read-write 0 Assert the SPI0 reset. #0 1 Clear the SPI0 reset. #1 SPI1_RST_N SPI1 reset control 12 1 read-write 0 Assert the SPI1 reset. #0 1 Clear the SPI1 reset. #1 CRC_RST_N CRC engine reset control 13 1 read-write 0 Assert the CRC reset. #0 1 Clear the CRC reset. #1 UART0_RST_N UART0 reset control 14 1 read-write 0 Assert the UART0 reset. #0 1 Clear the UART0 reset. #1 UART1_RST_N UART1 reset control 15 1 read-write 0 Assert the UART1 reset. #0 1 Clear the UART1 reset. #1 UART2_RST_N UART2 reset control 16 1 read-write 0 Assert the UART2 reset. #0 1 Clear the UART2 reset. #1 IOCON_RST_N IOCON reset control 18 1 read-write 0 Assert the IOCON reset. #0 1 Clear the IOCON reset. #1 ACMP_RST_N Analog comparator reset control 19 1 read-write 0 Assert the analog comparator reset. #0 1 Clear the analog comparator reset. #1 GPIO1_RST_N GPIO1 reset control 20 1 read-write 0 Assert the GPIO1 reset. #0 1 Clear the GPIO1 reset. #1 I2C1_RST_N I2C1 reset control 21 1 read-write 0 Assert the I2C1 reset. #0 1 Clear the I2C1 reset. #1 I2C2_RST_N I2C2 reset control 22 1 read-write 0 Assert the I2C2 reset. #0 1 Clear the I2C2 reset. #1 I2C3_RST_N I2C3 reset control 23 1 read-write 0 Assert the I2C3 reset. #0 1 Clear the I2C3 reset. #1 ADC_RST_N ADC reset control 24 1 read-write 0 Assert the ADC reset. #0 1 Clear the ADC reset. #1 CTIMER_RST_N CTIMER reset control 25 1 read-write 0 Assert the CTIMER reset. #0 1 Clear the CTIMER reset. #1 DAC0_RST_N DAC0 reset control 27 1 read-write 0 Assert the DAC0 reset. #0 1 Clear the DAC0 reset. #1 GPIOINT_RST_N GPIOINT reset control 28 1 read-write 0 Assert the GPIOINT reset. #0 1 Clear the GPIOINT reset. #1 DMA_RST_N DMA reset control 29 1 read-write 0 Assert the DMA reset. #0 1 Clear the DMA reset. #1 UART3_RST_N UART3 reset control 30 1 read-write 0 Assert the UART3 reset. #0 1 Clear the UART3 reset. #1 UART4_RST_N UART4 reset control 31 1 read-write 0 Assert the UART4 reset. #0 1 Clear the UART4 reset. #1 PRESETCTRL1 Peripheral reset group 1 control register 0x8C 32 read-write 0x1F 0x1F CAPT_RST_N Capacitive touch reset control 0 1 read-write 0 Assert the capacitive touch reset. #0 1 Clear the capacitive touch reset. #1 DAC1_RST_N DAC1 reset control 1 1 read-write 0 Assert the DAC1 reset. #0 1 Clear the DAC1 reset. #1 FRG0_RST_N Fractional baud rate generator 0 reset control 3 1 read-write 0 Assert the FRG0 reset. #0 1 Clear the FRG0 reset. #1 FRG1_RST_N Fractional baud rate generator 1 reset control 4 1 read-write 0 Assert the FRG1 reset. #0 1 Clear the FRG1 reset. #1 FCLK0SEL peripheral clock source select register. FCLK0SEL~FCLK4SEL are for UART0~UART4 clock source select register. FCLK5SEL~FCLK8SEL are for I2C0~I2C3 clock source select register. FCLK9SEL~FCLK10SEL are for SPI0~SPI1 clock source select register. 0x90 32 read-write 0x7 0x7 SEL Peripheral clock source 0 3 read-write 000 FRO #000 001 main clock #001 010 Frg0clk #010 011 Frg1clk #011 100 FRO_DIV #100 101 none #101 110 none #110 111 none #111 FCLK1SEL peripheral clock source select register. FCLK0SEL~FCLK4SEL are for UART0~UART4 clock source select register. FCLK5SEL~FCLK8SEL are for I2C0~I2C3 clock source select register. FCLK9SEL~FCLK10SEL are for SPI0~SPI1 clock source select register. 0x94 32 read-write 0x7 0x7 SEL Peripheral clock source 0 3 read-write 000 FRO #000 001 main clock #001 010 Frg0clk #010 011 Frg1clk #011 100 FRO_DIV #100 101 none #101 110 none #110 111 none #111 FCLK2SEL peripheral clock source select register. FCLK0SEL~FCLK4SEL are for UART0~UART4 clock source select register. FCLK5SEL~FCLK8SEL are for I2C0~I2C3 clock source select register. FCLK9SEL~FCLK10SEL are for SPI0~SPI1 clock source select register. 0x98 32 read-write 0x7 0x7 SEL Peripheral clock source 0 3 read-write 000 FRO #000 001 main clock #001 010 Frg0clk #010 011 Frg1clk #011 100 FRO_DIV #100 101 none #101 110 none #110 111 none #111 FCLK3SEL peripheral clock source select register. FCLK0SEL~FCLK4SEL are for UART0~UART4 clock source select register. FCLK5SEL~FCLK8SEL are for I2C0~I2C3 clock source select register. FCLK9SEL~FCLK10SEL are for SPI0~SPI1 clock source select register. 0x9C 32 read-write 0x7 0x7 SEL Peripheral clock source 0 3 read-write 000 FRO #000 001 main clock #001 010 Frg0clk #010 011 Frg1clk #011 100 FRO_DIV #100 101 none #101 110 none #110 111 none #111 FCLK4SEL peripheral clock source select register. FCLK0SEL~FCLK4SEL are for UART0~UART4 clock source select register. FCLK5SEL~FCLK8SEL are for I2C0~I2C3 clock source select register. FCLK9SEL~FCLK10SEL are for SPI0~SPI1 clock source select register. 0xA0 32 read-write 0x7 0x7 SEL Peripheral clock source 0 3 read-write 000 FRO #000 001 main clock #001 010 Frg0clk #010 011 Frg1clk #011 100 FRO_DIV #100 101 none #101 110 none #110 111 none #111 FCLK5SEL peripheral clock source select register. FCLK0SEL~FCLK4SEL are for UART0~UART4 clock source select register. FCLK5SEL~FCLK8SEL are for I2C0~I2C3 clock source select register. FCLK9SEL~FCLK10SEL are for SPI0~SPI1 clock source select register. 0xA4 32 read-write 0x7 0x7 SEL Peripheral clock source 0 3 read-write 000 FRO #000 001 main clock #001 010 Frg0clk #010 011 Frg1clk #011 100 FRO_DIV #100 101 none #101 110 none #110 111 none #111 FCLK6SEL peripheral clock source select register. FCLK0SEL~FCLK4SEL are for UART0~UART4 clock source select register. FCLK5SEL~FCLK8SEL are for I2C0~I2C3 clock source select register. FCLK9SEL~FCLK10SEL are for SPI0~SPI1 clock source select register. 0xA8 32 read-write 0x7 0x7 SEL Peripheral clock source 0 3 read-write 000 FRO #000 001 main clock #001 010 Frg0clk #010 011 Frg1clk #011 100 FRO_DIV #100 101 none #101 110 none #110 111 none #111 FCLK7SEL peripheral clock source select register. FCLK0SEL~FCLK4SEL are for UART0~UART4 clock source select register. FCLK5SEL~FCLK8SEL are for I2C0~I2C3 clock source select register. FCLK9SEL~FCLK10SEL are for SPI0~SPI1 clock source select register. 0xAC 32 read-write 0x7 0x7 SEL Peripheral clock source 0 3 read-write 000 FRO #000 001 main clock #001 010 Frg0clk #010 011 Frg1clk #011 100 FRO_DIV #100 101 none #101 110 none #110 111 none #111 FCLK8SEL peripheral clock source select register. FCLK0SEL~FCLK4SEL are for UART0~UART4 clock source select register. FCLK5SEL~FCLK8SEL are for I2C0~I2C3 clock source select register. FCLK9SEL~FCLK10SEL are for SPI0~SPI1 clock source select register. 0xB0 32 read-write 0x7 0x7 SEL Peripheral clock source 0 3 read-write 000 FRO #000 001 main clock #001 010 Frg0clk #010 011 Frg1clk #011 100 FRO_DIV #100 101 none #101 110 none #110 111 none #111 FCLK9SEL peripheral clock source select register. FCLK0SEL~FCLK4SEL are for UART0~UART4 clock source select register. FCLK5SEL~FCLK8SEL are for I2C0~I2C3 clock source select register. FCLK9SEL~FCLK10SEL are for SPI0~SPI1 clock source select register. 0xB4 32 read-write 0x7 0x7 SEL Peripheral clock source 0 3 read-write 000 FRO #000 001 main clock #001 010 Frg0clk #010 011 Frg1clk #011 100 FRO_DIV #100 101 none #101 110 none #110 111 none #111 FCLK10SEL peripheral clock source select register. FCLK0SEL~FCLK4SEL are for UART0~UART4 clock source select register. FCLK5SEL~FCLK8SEL are for I2C0~I2C3 clock source select register. FCLK9SEL~FCLK10SEL are for SPI0~SPI1 clock source select register. 0xB8 32 read-write 0x7 0x7 SEL Peripheral clock source 0 3 read-write 000 FRO #000 001 main clock #001 010 Frg0clk #010 011 Frg1clk #011 100 FRO_DIV #100 101 none #101 110 none #110 111 none #111 FRG0DIV fractional generator N divider value register 0xD0 32 read-write 0 0xFF DIV Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator. 0 8 read-write FRG0MULT fractional generator N multiplier value register 0xD4 32 read-write 0 0xFF MULT Numerator of the fractional divider. MULT is equal to the programmed value. 0 8 read-write FRG0CLKSEL FRG N clock source select register 0xD8 32 read-write 0 0x3 SEL Clock source for frgN_src clock 0 2 read-write 00 FRO #00 01 main clock #01 10 sys pll #10 11 None #11 FRG1DIV fractional generator N divider value register 0xE0 32 read-write 0 0xFF DIV Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator. 0 8 read-write FRG1MULT fractional generator N multiplier value register 0xE4 32 read-write 0 0xFF MULT Numerator of the fractional divider. MULT is equal to the programmed value. 0 8 read-write FRG1CLKSEL FRG N clock source select register 0xE8 32 read-write 0 0x3 SEL Clock source for frgN_src clock 0 2 read-write 00 FRO #00 01 main clock #01 10 sys pll #10 11 None #11 CLKOUTSEL CLKOUT clock source select register 0xF0 32 read-write 0 0xFFFFFFFF SEL CLKOUT clock source 0 3 read-write 000 FRO #000 001 main clock #001 010 sys pll #010 011 external clock #011 100 Watchdog oscillator #100 101 None #101 110 None #110 111 None #111 CLKOUTDIV CLKOUT clock divider registers 0xF4 32 read-write 0 0xFF DIV CLKOUT clock divider values 0: Disable CLKOUT clock divider. 1: Divide by 1. to 255: Divide by 255. 0 8 read-write EXTTRACECMD External trace buffer command register 0xFC 32 read-write 0 0x3 START Trace start command. Writing a one to this bit sets the TSTART signal to the MTB to HIGH and starts tracing if the TSTARTEN bit in the MTB master register is set to one as well. 0 1 read-write STOP Trace stop command. Writing a one to this bit sets the TSTOP signal in the MTB to HIGH and stops tracing if the TSTOPEN bit in the MTB master register is set to one as well. 1 1 read-write PIOPORCAP0 POR captured PIO N status register(PIO0 has 32 PIOs, PIO1 has 22 PIOs) 0x100 32 read-only 0 0 PIOSTAT State of PION_31 through PION_0 at power-on reset 0 32 read-only PIOPORCAP1 POR captured PIO N status register(PIO0 has 32 PIOs, PIO1 has 22 PIOs) 0x104 32 read-only 0 0 PIOSTAT State of PION_31 through PION_0 at power-on reset 0 32 read-only IOCONCLKDIV6 Peripheral clock 6 to the IOCON block for programmable glitch filter 0x134 32 read-write 0 0xFFFFFFFF DIV IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255. 0 8 read-write IOCONCLKDIV5 Peripheral clock 6 to the IOCON block for programmable glitch filter 0x138 32 read-write 0 0xFFFFFFFF DIV IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255. 0 8 read-write IOCONCLKDIV4 Peripheral clock 4 to the IOCON block for programmable glitch filter 0x13C 32 read-write 0 0xFFFFFFFF DIV IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255. 0 8 read-write IOCONCLKDIV3 Peripheral clock 3 to the IOCON block for programmable glitch filter 0x140 32 read-write 0 0xFFFFFFFF DIV IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255. 0 8 read-write IOCONCLKDIV2 Peripheral clock 2 to the IOCON block for programmable glitch filter 0x144 32 read-write 0 0xFFFFFFFF DIV IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255. 0 8 read-write IOCONCLKDIV1 Peripheral clock 1 to the IOCON block for programmable glitch filter 0x148 32 read-write 0 0xFFFFFFFF DIV IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255. 0 8 read-write IOCONCLKDIV0 Peripheral clock 0 to the IOCON block for programmable glitch filter 0x14C 32 read-write 0 0xFFFFFFFF DIV IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255. 0 8 read-write BODCTRL BOD control register 0x150 32 read-write 0 0x1F BODRSTLEV BOD reset level 0 2 read-write 01 Level 1 #01 10 Level 2 #10 11 Level 3 #11 BODINTVAL BOD interrupt level 2 2 read-write 01 Level 1 #01 10 Level 2 #10 11 Level 3 #11 BODRSTENA BOD reset enable 4 1 read-write 0 Disable reset function. #0 1 Enable reset function. #1 SYSTCKCAL System tick timer calibration register 0x154 32 read-write 0 0x3FFFFFF CAL System tick timer calibration value. 0 26 read-write IRQLATENCY IRQ latency register 0x170 32 read-write 0x10 0xFF LATENCY 8-bit latency value. 0 8 read-write NMISRC NMI source selection register 0x174 32 read-write 0 0x8000001F IRQN The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) if bit 31 is 1 0 5 read-write NMIEN Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0. 31 1 read-write PINTSEL0 Pin interrupt select registers N 0x178 32 read-write 0 0x3F INTPIN Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_31correspond to numbers 0 to 31 and PIO1_0 to PIO1_31 correspond to numbers 32 to 63). 0 6 read-write PINTSEL1 Pin interrupt select registers N 0x17C 32 read-write 0 0x3F INTPIN Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_31correspond to numbers 0 to 31 and PIO1_0 to PIO1_31 correspond to numbers 32 to 63). 0 6 read-write PINTSEL2 Pin interrupt select registers N 0x180 32 read-write 0 0x3F INTPIN Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_31correspond to numbers 0 to 31 and PIO1_0 to PIO1_31 correspond to numbers 32 to 63). 0 6 read-write PINTSEL3 Pin interrupt select registers N 0x184 32 read-write 0 0x3F INTPIN Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_31correspond to numbers 0 to 31 and PIO1_0 to PIO1_31 correspond to numbers 32 to 63). 0 6 read-write PINTSEL4 Pin interrupt select registers N 0x188 32 read-write 0 0x3F INTPIN Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_31correspond to numbers 0 to 31 and PIO1_0 to PIO1_31 correspond to numbers 32 to 63). 0 6 read-write PINTSEL5 Pin interrupt select registers N 0x18C 32 read-write 0 0x3F INTPIN Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_31correspond to numbers 0 to 31 and PIO1_0 to PIO1_31 correspond to numbers 32 to 63). 0 6 read-write PINTSEL6 Pin interrupt select registers N 0x190 32 read-write 0 0x3F INTPIN Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_31correspond to numbers 0 to 31 and PIO1_0 to PIO1_31 correspond to numbers 32 to 63). 0 6 read-write PINTSEL7 Pin interrupt select registers N 0x194 32 read-write 0 0x3F INTPIN Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_31correspond to numbers 0 to 31 and PIO1_0 to PIO1_31 correspond to numbers 32 to 63). 0 6 read-write STARTERP0 Start logic 0 pin wake-up enable register 0 0x204 32 read-write 0 0xFF PINT0 GPIO pin interrupt 0 wake-up 0 1 read-write 0 Disabled #0 1 Enabled #1 PINT1 GPIO pin interrupt 1 wake-up 1 1 read-write 0 Disabled #0 1 Enabled #1 PINT2 GPIO pin interrupt 2 wake-up 2 1 read-write 0 Disabled #0 1 Enabled #1 PINT3 GPIO pin interrupt 3 wake-up 3 1 read-write 0 Disabled #0 1 Enabled #1 PINT4 GPIO pin interrupt 4 wake-up 4 1 read-write 0 Disabled #0 1 Enabled #1 PINT5 GPIO pin interrupt 5 wake-up 5 1 read-write 0 Disabled #0 1 Enabled #1 PINT6 GPIO pin interrupt 6 wake-up 6 1 read-write 0 Disabled #0 1 Enabled #1 PINT7 GPIO pin interrupt 7 wake-up 7 1 read-write 0 Disabled #0 1 Enabled #1 STARTERP1 Start logic 0 pin wake-up enable register 1 0x214 32 read-write 0 0xFF SPI0 SPI0 interrupt wake-up 0 1 read-write 0 Disabled #0 1 Enabled #1 SPI1 SPI1 interrupt wake-up 1 1 read-write 0 Disabled #0 1 Enabled #1 USART0 USART0 interrupt wake-up. Configure USART in synchronous slave mode. 3 1 read-write 0 Disabled #0 1 Enabled #1 USART1 USART1 interrupt wake-up. Configure USART in synchronous slave mode. 4 1 read-write 0 Disabled #0 1 Enabled #1 USART2 USART2 interrupt wake-up. Configure USART in synchronous slave mode. 5 1 read-write 0 Disabled #0 1 Enabled #1 I2C1 I2C1 interrupt wake-up. 7 1 read-write 0 Disabled #0 1 Enabled #1 I2C0 I2C0 interrupt wake-up. 8 1 read-write 0 Disabled #0 1 Enabled #1 Cap_Touch Cap Touch interrupt wake-up. 11 1 read-write 0 Disabled #0 1 Enabled #1 WWDT WWDT interrupt wake-up 12 1 read-write 0 Disabled #0 1 Enabled #1 BOD BOD interrupt wake-up 13 1 read-write 0 Disabled #0 1 Enabled #1 WKT Self-wake-up timer interrupt wake-up 15 1 read-write 0 Disabled #0 1 Enabled #1 I2C2 I2C2 interrupt wake-up 21 1 read-write 0 Disabled #0 1 Enabled #1 I2C3 I2C3 interrupt wake-up 22 1 read-write 0 Disabled #0 1 Enabled #1 UART3 UART3 interrupt wake-up 30 1 read-write 0 Disabled #0 1 Enabled #1 UART4 UART4 interrupt wake-up 31 1 read-write 0 Disabled #0 1 Enabled #1 PDSLEEPCFG Deep-sleep configuration register 0x230 32 read-write 0xFFFF 0xFFFF BOD_PD BOD power-down control for Deep-sleep and Power-down mode 3 1 read-write 0 powered #0 1 powered down #1 WDTOSC_PD Watchdog oscillator power-down control for Deep-sleep and Power-down mode. Changing this bit to powered-down has no effect when the LOCK bit in the WWDT MOD register is set. In this case, the watchdog oscillator is always running. 6 1 read-write 0 Disabled #0 1 Enabled #1 PDAWAKECFG Wake-up configuration register 0x234 32 read-write 0xEDF8 0xFFFF FROOUT_PD FRO oscillator output wake-up configuration 0 1 read-write 0 powered #0 1 powered down #1 FRO_PD FRO oscillator power-down wake-up configuration 1 1 read-write 0 powered #0 1 powered down #1 FLASH_PD Flash wake-up configuration 2 1 read-write 0 powered #0 1 powered down #1 BOD_PD BOD wake-up configuration 3 1 read-write 0 powered #0 1 powered down #1 ADC_PD ADC wake-up configuration 4 1 read-write 0 powered #0 1 powered down #1 SYSOSC_PD Crystal oscillator wake-up configuration 5 1 read-write 0 powered #0 1 powered down #1 WDTOSC_PD Watchdog oscillator wake-up configuration. Changing this bit to powered-down has no effect when the LOCK bit in the WWDT MOD register is set. In this case, the watchdog oscillator is always running 6 1 read-write 0 Disabled #0 1 Enabled #1 SYSPLL_PD System PLL wake-up configuration 7 1 read-write 0 Disabled #0 1 Enabled #1 VREF2_PD VREF2 wake-up configuration 10 1 read-write 0 Disabled #0 1 Enabled #1 DAC0 DAC0 wake-up configuration 13 1 read-write 0 Disabled #0 1 Enabled #1 DAC1 DAC1 wake-up configuration 14 1 read-write 0 Disabled #0 1 Enabled #1 ACMP Analog comparator wake-up configuration 15 1 read-write 0 Disabled #0 1 Enabled #1 PDRUNCFG Power configuration register 0x238 32 read-write 0xEDF8 0xFFFFFFFF FROOUT_PD FRO oscillator output wake-up configuration 0 1 read-write 0 powered #0 1 powered down #1 FRO_PD FRO oscillator power-down wake-up configuration 1 1 read-write 0 powered #0 1 powered down #1 FLASH_PD Flash wake-up configuration 2 1 read-write 0 powered #0 1 powered down #1 BOD_PD BOD wake-up configuration 3 1 read-write 0 powered #0 1 powered down #1 ADC_PD ADC wake-up configuration 4 1 read-write 0 powered #0 1 powered down #1 SYSOSC_PD Crystal oscillator wake-up configuration 5 1 read-write 0 powered #0 1 powered down #1 WDTOSC_PD Watchdog oscillator wake-up configuration. Changing this bit to powered-down has no effect when the LOCK bit in the WWDT MOD register is set. In this case, the watchdog oscillator is always running 6 1 read-write 0 Disabled #0 1 Enabled #1 SYSPLL_PD System PLL wake-up configuration 7 1 read-write 0 Disabled #0 1 Enabled #1 DAC0 DAC0 wake-up configuration 13 1 read-write 0 Disabled #0 1 Enabled #1 DAC1 DAC1 wake-up configuration 14 1 read-write 0 Disabled #0 1 Enabled #1 ACMP Analog comparator wake-up configuration 15 1 read-write 0 Disabled #0 1 Enabled #1 DEVICE_ID Part ID register 0x3F8 32 read-only 0 0xFFFFFFFF DEVICEID Part ID 0 32 read-only SPI0 LPC84x Serial Peripheral Interfaces (SPI) SPI 0x40058000 0 0x2C registers SPI0 0 CFG SPI Configuration register 0 32 read-write 0 0xFBD ENABLE SPI enable. 0 1 read-write 0 Disabled. The SPI is disabled and the internal state machine and counters are reset. #0 1 Enabled. The SPI is enabled for operation. #1 MASTER Master mode select. 2 1 read-write 0 Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. #0 1 Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. #1 LSBF LSB First mode enable. 3 1 read-write 0 Standard. Data is transmitted and received in standard MSB first order. #0 1 Reverse. Data is transmitted and received in reverse order (LSB first). #1 CPHA Clock Phase select. 4 1 read-write 0 Change. The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge. #0 1 Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge. #1 CPOL Clock Polarity select. 5 1 read-write 0 Low. The rest state of the clock (between transfers) is low. #0 1 High. The rest state of the clock (between transfers) is high. #1 LOOP Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing. 7 1 read-write 0 Disabled. #0 1 Enabled. #1 SPOL0 SSEL0 Polarity select. 8 1 read-write 0 Low. The SSEL0 pin is active low. #0 1 High. The SSEL0 pin is active high. #1 SPOL1 SSEL1 Polarity select. 9 1 read-write 0 Low. The SSEL1 pin is active low. #0 1 High. The SSEL1 pin is active high. #1 SPOL2 SSEL2 Polarity select. 10 1 read-write 0 Low. The SSEL2 pin is active low. #0 1 High. The SSEL2 pin is active high. #1 SPOL3 SSEL3 Polarity select. 11 1 read-write 0 Low. The SSEL3 pin is active low. #0 1 High. The SSEL3 pin is active high. #1 DLY SPI Delay register 0x4 32 read-write 0 0xFFFF PRE_DELAY Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. 0 4 read-write POST_DELAY Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. 4 4 read-write FRAME_DELAY If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. 8 4 read-write TRANSFER_DELAY Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times. 12 4 read-write STAT SPI Status. Some status flags can be cleared by writing a 1 to that bit position 0x8 32 read-write 0x102 0x1FF RXRDY Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT register. 0 1 read-only TXRDY Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT or TXDATCTL until the data is moved to the transmit shift register. 1 1 read-only RXOV Receiver Overrun interrupt flag. This flag applies only to slave mode (Master = 0). This flag is set when the beginning of a received character is detected while the receiver buffer is still in use. If this occurs, the receiver buffer contents are preserved, and the incoming data is lost. Data received by the SPI should be considered undefined if RxOv is set. 2 1 write-only TXUR Transmitter Underrun interrupt flag. This flag applies only to slave mode (Master = 0). In this case, the transmitter must begin sending new data on the next input clock if the transmitter is idle. If that data is not available in the transmitter holding register at that point, there is no data to transmit and the TXUR flag is set. Data transmitted by the SPI should be considered undefined if TXUR is set. 3 1 write-only SSA Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software. 4 1 write-only SSD Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software. 5 1 write-only STALLED Stalled status flag. This indicates whether the SPI is currently in a stall condition. 6 1 read-only ENDTRANSFER End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted. 7 1 read-write MSTIDLE Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data. 8 1 read-only INTENSET SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. 0xC 32 read-write 0 0x13F RXRDYEN Determines whether an interrupt occurs when receiver data is available. 0 1 read-write 0 No interrupt will be generated when receiver data is available. #0 1 An interrupt will be generated when receiver data is available in the RXDAT register. #1 TXRDYEN Determines whether an interrupt occurs when the transmitter holding register is available. 1 1 read-write 0 No interrupt will be generated when the transmitter holding register is available. #0 1 An interrupt will be generated when data may be written to TXDAT. #1 RXOVEN Determines whether an interrupt occurs when a receiver overrun occurs. This happens in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use. The interface prevents receiver overrun in Master mode by not allowing a new transmission to begin when a receiver overrun would otherwise occur. 2 1 read-write 0 No interrupt will be generated when a receiver overrun occurs. #0 1 An interrupt will be generated if a receiver overrun occurs. #1 TXUREN Determines whether an interrupt occurs when a transmitter underrun occurs. This happens in slave mode when there is a need to transmit data when none is available. 3 1 read-write 0 No interrupt will be generated when the transmitter underruns. #0 1 An interrupt will be generated if the transmitter underruns. #1 SSAEN Determines whether an interrupt occurs when the Slave Select is asserted. 4 1 read-write 0 No interrupt will be generated when any Slave Select transitions from deasserted to asserted. #0 1 An interrupt will be generated when any Slave Select transitions from deasserted to asserted. #1 SSDEN Determines whether an interrupt occurs when the Slave Select is deasserted. 5 1 read-write 0 No interrupt will be generated when all asserted Slave Selects transition to deasserted. #0 1 An interrupt will be generated when all asserted Slave Selects transition to deasserted. #1 INTENCLR SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. 0x10 32 write-only 0 0 RXRDYEN Writing 1 clears the corresponding bits in the INTENSET register. 0 1 write-only TXRDYEN Writing 1 clears the corresponding bits in the INTENSET register. 1 1 write-only RXOVEN Writing 1 clears the corresponding bits in the INTENSET register. 2 1 write-only TXUREN Writing 1 clears the corresponding bits in the INTENSET register. 3 1 write-only SSAEN Writing 1 clears the corresponding bits in the INTENSET register. 4 1 write-only SSDEN Writing 1 clears the corresponding bits in the INTENSET register. 5 1 write-only RXDAT SPI Receive Data 0x14 32 read-only 0 0 RXDAT Receiver Data. This contains the next piece of received data. The number of bits that are used depends on the LEN setting in TXCTL / TXDATCTL. 0 16 read-only RXSSEL0_N Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. 16 1 read-only RXSSEL1_N Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. 17 1 read-only RXSSEL2_N Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. 18 1 read-only RXSSEL3_N Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. 19 1 read-only SOT Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the transfer length is greater than 16 bit. 20 1 read-only TXDATCTL SPI Transmit Data with Control 0x18 32 read-write 0 0xF7FFFFF TXDAT Transmit Data. This field provides from 1 to 16 bits of data to be transmitted. 0 16 read-write TXSSEL0_N Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL0 pin is configured by bits in the CFG register. 16 1 read-write 0 SSEL0 asserted. #0 1 SSEL0 not asserted. #1 TXSSEL1_N Transmit Slave Select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL1 pin is configured by bits in the CFG register. 17 1 read-write 0 SSEL1 asserted. #0 1 SSEL1 not asserted. #1 TXSSEL2_N Transmit Slave Select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL2 pin is configured by bits in the CFG register. 18 1 read-write 0 SSEL2 asserted. #0 1 SSEL2 not asserted. #1 TXSSEL3_N Transmit Slave Select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL3 pin is configured by bits in the CFG register. 19 1 read-write 0 SSEL3 asserted. #0 1 SSEL3 not asserted. #1 EOT End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain so for at least the time specified by the Transfer_delay value in the DLY register. 20 1 read-write 0 This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. #0 1 This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. #1 EOF End of Frame. Between frames, a delay may be inserted, as defined by the FRAME_DELAY value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for frame lengths greater than 16 bits. 21 1 read-write 0 This piece of data transmitted is not treated as the end of a frame. #0 1 This piece of data is treated as the end of a frame, causing the FRAME_DELAY time to be inserted before subsequent data is transmitted. #1 RXIGNORE Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver.Setting this bit simplifies the transmit process and can be used with the DMA. 22 1 read-write 0 Received data must be read in order to allow transmission to progress. In slave mode, an overrun error will occur if received data is not read before new data is received. #0 1 Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated. #1 LEN Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data transfer is 1 bit in length. 0x1 = Data transfer is 2 bits in length. 0x2 = Data transfer is 3 bits in length. ... 0xF = Data transfer is 16 bits in length. 24 4 read-write 0001 Data transfer is 1 bit in length. #0001 0010 Data transfer is 2 bit in length. #0010 0011 Data transfer is 3 bit in length. #0011 0100 Data transfer is 4 bit in length. #0100 0101 Data transfer is 5 bit in length. #0101 0110 Data transfer is 6 bit in length. #0110 0111 Data transfer is 7 bit in length. #0111 1000 Data transfer is 8 bit in length. #1000 1001 Data transfer is 9 bit in length. #1001 1010 Data transfer is 10 bit in length. #1010 1011 Data transfer is 11 bit in length. #1011 1100 Data transfer is 12 bit in length. #1100 1101 Data transfer is 13 bit in length. #1101 1110 Data transfer is 14 bit in length. #1110 1111 Data transfer is 15 bit in length. #1111 TXDAT SPI Transmit Data. 0x1C 32 read-write 0 0xFFFF DATA Transmit Data. This field provides from 4 to 16 bits of data to be transmitted. 0 16 read-write TXCTL SPI Transmit Control 0x20 32 read-write 0 0xF7F0000 TXSSEL0_N Transmit Slave Select 0. 16 1 read-write TXSSEL1_N Transmit Slave Select 1. 17 1 read-write TXSSEL2_N Transmit Slave Select 2. 18 1 read-write TXSSEL3_N Transmit Slave Select 3. 19 1 read-write EOT End of Transfer. 20 1 read-write EOF End of Frame. 21 1 read-write RXIGNORE Receive Ignore. 22 1 read-write LEN Data transfer Length. 24 4 read-write DIV SPI clock Divider 0x24 32 read-write 0 0xFFFF DIVVAL Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536. 0 16 read-write INTSTAT SPI Interrupt Status 0x28 32 read-write 0x2 0x1FF RXRDY Receiver Ready flag. 0 1 read-only TXRDY Transmitter Ready flag. 1 1 read-only RXOV Receiver Overrun interrupt flag. 2 1 read-only TXUR Transmitter Underrun interrupt flag. 3 1 read-only SSA Slave Select Assert. 4 1 read-only SSD Slave Select Deassert. 5 1 read-only MSTIDLE Master Idle status flag. 8 1 read-only SPI1 LPC84x Serial Peripheral Interfaces (SPI) SPI 0x4005C000 0 0x2C registers SPI1 1 CFG SPI Configuration register 0 32 read-write 0 0xFBD ENABLE SPI enable. 0 1 read-write 0 Disabled. The SPI is disabled and the internal state machine and counters are reset. #0 1 Enabled. The SPI is enabled for operation. #1 MASTER Master mode select. 2 1 read-write 0 Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. #0 1 Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. #1 LSBF LSB First mode enable. 3 1 read-write 0 Standard. Data is transmitted and received in standard MSB first order. #0 1 Reverse. Data is transmitted and received in reverse order (LSB first). #1 CPHA Clock Phase select. 4 1 read-write 0 Change. The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge. #0 1 Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge. #1 CPOL Clock Polarity select. 5 1 read-write 0 Low. The rest state of the clock (between transfers) is low. #0 1 High. The rest state of the clock (between transfers) is high. #1 LOOP Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing. 7 1 read-write 0 Disabled. #0 1 Enabled. #1 SPOL0 SSEL0 Polarity select. 8 1 read-write 0 Low. The SSEL0 pin is active low. #0 1 High. The SSEL0 pin is active high. #1 SPOL1 SSEL1 Polarity select. 9 1 read-write 0 Low. The SSEL1 pin is active low. #0 1 High. The SSEL1 pin is active high. #1 SPOL2 SSEL2 Polarity select. 10 1 read-write 0 Low. The SSEL2 pin is active low. #0 1 High. The SSEL2 pin is active high. #1 SPOL3 SSEL3 Polarity select. 11 1 read-write 0 Low. The SSEL3 pin is active low. #0 1 High. The SSEL3 pin is active high. #1 DLY SPI Delay register 0x4 32 read-write 0 0xFFFF PRE_DELAY Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. 0 4 read-write POST_DELAY Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. 4 4 read-write FRAME_DELAY If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. 8 4 read-write TRANSFER_DELAY Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times. 12 4 read-write STAT SPI Status. Some status flags can be cleared by writing a 1 to that bit position 0x8 32 read-write 0x102 0x1FF RXRDY Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT register. 0 1 read-only TXRDY Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT or TXDATCTL until the data is moved to the transmit shift register. 1 1 read-only RXOV Receiver Overrun interrupt flag. This flag applies only to slave mode (Master = 0). This flag is set when the beginning of a received character is detected while the receiver buffer is still in use. If this occurs, the receiver buffer contents are preserved, and the incoming data is lost. Data received by the SPI should be considered undefined if RxOv is set. 2 1 write-only TXUR Transmitter Underrun interrupt flag. This flag applies only to slave mode (Master = 0). In this case, the transmitter must begin sending new data on the next input clock if the transmitter is idle. If that data is not available in the transmitter holding register at that point, there is no data to transmit and the TXUR flag is set. Data transmitted by the SPI should be considered undefined if TXUR is set. 3 1 write-only SSA Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software. 4 1 write-only SSD Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software. 5 1 write-only STALLED Stalled status flag. This indicates whether the SPI is currently in a stall condition. 6 1 read-only ENDTRANSFER End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted. 7 1 read-write MSTIDLE Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data. 8 1 read-only INTENSET SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. 0xC 32 read-write 0 0x13F RXRDYEN Determines whether an interrupt occurs when receiver data is available. 0 1 read-write 0 No interrupt will be generated when receiver data is available. #0 1 An interrupt will be generated when receiver data is available in the RXDAT register. #1 TXRDYEN Determines whether an interrupt occurs when the transmitter holding register is available. 1 1 read-write 0 No interrupt will be generated when the transmitter holding register is available. #0 1 An interrupt will be generated when data may be written to TXDAT. #1 RXOVEN Determines whether an interrupt occurs when a receiver overrun occurs. This happens in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use. The interface prevents receiver overrun in Master mode by not allowing a new transmission to begin when a receiver overrun would otherwise occur. 2 1 read-write 0 No interrupt will be generated when a receiver overrun occurs. #0 1 An interrupt will be generated if a receiver overrun occurs. #1 TXUREN Determines whether an interrupt occurs when a transmitter underrun occurs. This happens in slave mode when there is a need to transmit data when none is available. 3 1 read-write 0 No interrupt will be generated when the transmitter underruns. #0 1 An interrupt will be generated if the transmitter underruns. #1 SSAEN Determines whether an interrupt occurs when the Slave Select is asserted. 4 1 read-write 0 No interrupt will be generated when any Slave Select transitions from deasserted to asserted. #0 1 An interrupt will be generated when any Slave Select transitions from deasserted to asserted. #1 SSDEN Determines whether an interrupt occurs when the Slave Select is deasserted. 5 1 read-write 0 No interrupt will be generated when all asserted Slave Selects transition to deasserted. #0 1 An interrupt will be generated when all asserted Slave Selects transition to deasserted. #1 INTENCLR SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. 0x10 32 write-only 0 0 RXRDYEN Writing 1 clears the corresponding bits in the INTENSET register. 0 1 write-only TXRDYEN Writing 1 clears the corresponding bits in the INTENSET register. 1 1 write-only RXOVEN Writing 1 clears the corresponding bits in the INTENSET register. 2 1 write-only TXUREN Writing 1 clears the corresponding bits in the INTENSET register. 3 1 write-only SSAEN Writing 1 clears the corresponding bits in the INTENSET register. 4 1 write-only SSDEN Writing 1 clears the corresponding bits in the INTENSET register. 5 1 write-only RXDAT SPI Receive Data 0x14 32 read-only 0 0 RXDAT Receiver Data. This contains the next piece of received data. The number of bits that are used depends on the LEN setting in TXCTL / TXDATCTL. 0 16 read-only RXSSEL0_N Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. 16 1 read-only RXSSEL1_N Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. 17 1 read-only RXSSEL2_N Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. 18 1 read-only RXSSEL3_N Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. 19 1 read-only SOT Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the transfer length is greater than 16 bit. 20 1 read-only TXDATCTL SPI Transmit Data with Control 0x18 32 read-write 0 0xF7FFFFF TXDAT Transmit Data. This field provides from 1 to 16 bits of data to be transmitted. 0 16 read-write TXSSEL0_N Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL0 pin is configured by bits in the CFG register. 16 1 read-write 0 SSEL0 asserted. #0 1 SSEL0 not asserted. #1 TXSSEL1_N Transmit Slave Select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL1 pin is configured by bits in the CFG register. 17 1 read-write 0 SSEL1 asserted. #0 1 SSEL1 not asserted. #1 TXSSEL2_N Transmit Slave Select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL2 pin is configured by bits in the CFG register. 18 1 read-write 0 SSEL2 asserted. #0 1 SSEL2 not asserted. #1 TXSSEL3_N Transmit Slave Select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL3 pin is configured by bits in the CFG register. 19 1 read-write 0 SSEL3 asserted. #0 1 SSEL3 not asserted. #1 EOT End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain so for at least the time specified by the Transfer_delay value in the DLY register. 20 1 read-write 0 This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. #0 1 This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. #1 EOF End of Frame. Between frames, a delay may be inserted, as defined by the FRAME_DELAY value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for frame lengths greater than 16 bits. 21 1 read-write 0 This piece of data transmitted is not treated as the end of a frame. #0 1 This piece of data is treated as the end of a frame, causing the FRAME_DELAY time to be inserted before subsequent data is transmitted. #1 RXIGNORE Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver.Setting this bit simplifies the transmit process and can be used with the DMA. 22 1 read-write 0 Received data must be read in order to allow transmission to progress. In slave mode, an overrun error will occur if received data is not read before new data is received. #0 1 Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated. #1 LEN Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data transfer is 1 bit in length. 0x1 = Data transfer is 2 bits in length. 0x2 = Data transfer is 3 bits in length. ... 0xF = Data transfer is 16 bits in length. 24 4 read-write 0001 Data transfer is 1 bit in length. #0001 0010 Data transfer is 2 bit in length. #0010 0011 Data transfer is 3 bit in length. #0011 0100 Data transfer is 4 bit in length. #0100 0101 Data transfer is 5 bit in length. #0101 0110 Data transfer is 6 bit in length. #0110 0111 Data transfer is 7 bit in length. #0111 1000 Data transfer is 8 bit in length. #1000 1001 Data transfer is 9 bit in length. #1001 1010 Data transfer is 10 bit in length. #1010 1011 Data transfer is 11 bit in length. #1011 1100 Data transfer is 12 bit in length. #1100 1101 Data transfer is 13 bit in length. #1101 1110 Data transfer is 14 bit in length. #1110 1111 Data transfer is 15 bit in length. #1111 TXDAT SPI Transmit Data. 0x1C 32 read-write 0 0xFFFF DATA Transmit Data. This field provides from 4 to 16 bits of data to be transmitted. 0 16 read-write TXCTL SPI Transmit Control 0x20 32 read-write 0 0xF7F0000 TXSSEL0_N Transmit Slave Select 0. 16 1 read-write TXSSEL1_N Transmit Slave Select 1. 17 1 read-write TXSSEL2_N Transmit Slave Select 2. 18 1 read-write TXSSEL3_N Transmit Slave Select 3. 19 1 read-write EOT End of Transfer. 20 1 read-write EOF End of Frame. 21 1 read-write RXIGNORE Receive Ignore. 22 1 read-write LEN Data transfer Length. 24 4 read-write DIV SPI clock Divider 0x24 32 read-write 0 0xFFFF DIVVAL Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536. 0 16 read-write INTSTAT SPI Interrupt Status 0x28 32 read-write 0x2 0x1FF RXRDY Receiver Ready flag. 0 1 read-only TXRDY Transmitter Ready flag. 1 1 read-only RXOV Receiver Overrun interrupt flag. 2 1 read-only TXUR Transmitter Underrun interrupt flag. 3 1 read-only SSA Slave Select Assert. 4 1 read-only SSD Slave Select Deassert. 5 1 read-only MSTIDLE Master Idle status flag. 8 1 read-only CAPT LPC84x Capacitive Touch 0x40060000 0 0x1000 registers CMP_CAPT 11 CTRL Configuration and control to setup the functional clock, the rules, and the pin selections and rules. 0 32 read-write 0 0xFFFFBFFF POLLMODE Mode of operation. May only change from 0 to another value. So, if 2 or 3, must be changed to 0 1st. Any attempt to go from non-0 to non-0 will result in 0 anyway. 0 2 read-write 00 None, inactive. Poll and time counters are turned off. Writing this will reset state and stop any collection in progress. Note: this has no effect on STATUS - those must be cleared manually. #00 01 Poll now - forces a manual poll to be started immediately, using XPINSEL X pin(s) to activate in the integration loop (all pins set together). Self clears - clear is not indication it is done (see STATUS). #01 10 Normal polling using poll delay from POLL_TCNT register. This will start with the poll delay (which can be 0). #10 11 The CAPT block will operate in low-power mode. This means it will use GPIO as input, use combination touch measurements, and assume it is to wake the system. This will use the POLL_TCNT poll delay, and start with the delay. #11 TYPE Selects type of Touch arrangement to use and so how to handle XPINSEL bits 2 2 read-write 00 Normal - all X elements are treated as normal, such as buttons and sliders. #00 01 3x3 grid using NXP Complementary measurements. The 1st 9 Xs are assumed to be the 3x3 grid. After that would be normal X elements. This will also allow 3x1 and 3x2 Note: Only possible if XMAX in STATUS is >=8 #01 10 5 Sensors interleaved to act as 3x3 touch area using NXP Complementary measurements. 1st 5 Xs used for this, all remaining are treated as normal. Note that if 16 X pins allowed, the 16th will not be usable when TYPE=1. (use TYPE=0 and select 1 smaller than 15 ( and any others from 1 smaller than 5 on up in XPINSEL). #10 11 9 Sensors interleaved to act as 5x5 touch area using NXP Complementary measurements. 1st 9 Xs used for this, all remaining are treated as normal. Note: Only possible if XMAX in STATUS is >=8 #11 TRIGGER This selects what is being used as the trigger 4 1 read-write 0 Uses YH GPIO. This is not normally used except in Low-power mode. But, it can be used with POLLNOW to baseline that measurement. #0 1 ACMP (if fitted). This assumes the ACMP state is fed in asynchronously and it will sample. #1 WAIT If 0, the block will continue its X based measurements, even if the TOUCH register has not been read (and so could OVERRUN). If 1, it will wait until read when a touch (TOUCH's ISTOUCH bit is set) before starting the next. This should not normally be needed. 5 1 read-write DMA If not 0, will use the DMA to read out touch events from TOUCH register. The values are shown below. This may be changed while active. 6 2 read-write 00 No DMA. Application will use ISRs to read out data #00 01 Trigger DMA on Touch events #01 10 Trigger DMA on both Touch and No-Touch events #10 11 Trigger DMA on both plus Timeout. #11 FDIV Functional clock divider, or 0 if no divide. The term "clocks" in this spec then refer to divided clocks. For a 12MHz input (e.g. FRO 12MHz), this would normally be set to generate a 4MHz output (so, 2). For a 1MHz input, it should be 0. Note for internal use: this does not produce a 50/50 duty cycle when non even divide. 8 4 read-write 0000 No divide #0000 0001 /2 #0001 0010 /3 #0010 0011 /4 #0011 0100 /5 #0100 0101 /6 #0101 0111 /(FDIV+1) #0111 1000 /(FDIV+1) #1000 1001 /(FDIV+1) #1001 1010 /(FDIV+1) #1010 1011 /(FDIV+1) #1011 1100 /(FDIV+1) #1100 1101 /(FDIV+1) #1101 1110 /(FDIV+1) #1110 1111 /(FDIV+1) #1111 XPINUSE Controls how X pins selected in XPINSEL are used when not active in the current polling round. 12 2 read-write 0 Normal mode. Each inactive X pin is Hi-Z. #00 1 Ground mode. Each inactive X pin is Low #01 INCHANGE If 1, do not attempt to write to this register again. This means the last change has not been propagated. This can only happen after changing POLLMODE and DMA. Worse case time would be based on divided FCLK. 15 1 read-only XPINSEL Selects which of the X pins are to be used within the allowed pins - see XMAX in STATUS. The X pins are mapped via the IOCON (as are the YH and YL pins) to physical pads. So, this only selects which are to be used as the X half of the touch element. Note: when polling, these are "walked" (active) one at a time. When using POLLNOW, the 1 or more selected are used at the same time. Likewise, when in low-power mode, they are used at the same time (or small groups). X pads not selected by XPINSEL are kept at High-Z if they are connected to a pad. This allows using controlled sets for touch detection based on context. 16 16 read-write STATUS Status from triggers and time-outs including if in a poll now. Some are used for interrupts. 0x4 32 read-write 0x80000 0xF011F YESTOUCH Is 1 if a touch has been detected, including a wakeup from low-power mode. 0 1 read-write NOTOUCH Is 1 if a no-touch has been detected (ie. completed an integration cycle and found no-touch). This is not set when in low-power mode. 1 1 read-write POLLDONE Is 1 if a poll or POLLNOW is complete. 2 1 read-write TIMEOUT Is 1 if an integration cycle ended with a timeout (should not happen). 3 1 read-write OVERUN Is 1 if new data was collected before application read out previous ISTOUCH. No-touch (ISTOUCH==0) data will be silently overrun. Is not possible if WAIT=1. 4 1 read-write BUSY In a poll now. 8 1 read-only XMAX Indicates the maximum number of X pins allowed 0-relative. So, 15 means there are pins 0 to 15, or 16 total X pins. INTERNAL note: this may be setup to be written by ROM boot. 16 4 read-only POLL_TCNT This sets up the polling counter and measurement counter rules. 0x8 32 read-write 0 0x8FFFFFFF TCNT Sets the threshold between touch and no-touch count. If not used, then the block will treat all events as touch or no-touch, depending whether at max or min. This is in terms of divided FCLK. If the comparator triggers it is no-touch; if bigger than TCNT counts, it is a touch event. 0 12 read-write TOUT Time-out count expressed as 1 is smaller than TOUT, allowing for up to 12 bits. Must be less than 13. So, for example, 1 is smaller than 12=4096 counts; if TOUT=12, then if 4096 counts occur without a trigger, it is a time-out. This should be set to be large enough above TCNT to prevent timeout invalidly. 12 4 read-write POLL Poll counter in (internal) 12-bit counter wraparounds (loosely 1msec), so related to divided FCLK. This expresses time delay between measurement cycles (ie. after one set of X measurements, time before starting next). This count is used to delay before the next set of measurements. Measuring too often wastes power and does not add value since movement of fingers is relatively slow. For low power mode, this must allow for the clock being used (e.g. a 1MHz osc) so 12 bit count will be potentially much longer. That means, lowering the count to get the reasonable delay period. 16 8 read-write MDELAY If not 0, this selects the number of divided FCLKs to wait after entry of measurement mode before deciding if has triggered. This gives the ACMP time to react to the transferred charge. It is used as 1+(1 smaller than MDELAY), , so between 2 and 8 ticks of the divided FCLK added during the measurement. 24 2 read-write RDELAY If not 0, this is the number of divided FCLKs to hold in Step 0 'Reset' state (draining capacitance). It is used as (1 is smaller than RDELAY), so between 2 and 8 ticks of the divided FCLK added to the 'Reset' state. 26 2 read-write TCHLOW_ER If 1, then the touch/no-touch boundary of TCNT is reversed. In a floating system (most common), the no-touch case triggers at a lower count vs. touch; this is due to touch drawing off charge. In a grounded system, the reverse is true and the touch adds to the charge and so touch is a lower count. In a system which can switch between grounded and non-grounded, the SW will check for all of the Xs looking like they have been touched and reverse the setting of this bit. This should only be changed between polls. 31 1 read-write INTENSET Interrupt enable 0x10 32 read-write 0 0x1F YESTOUCH Is 1 if a touch detected should interrupt. This includes wake from low-power mode. 0 1 read-write NOTOUCH Is 1 if a no-touch detected should interrupt 1 1 read-write POLLDONE Is 1 if a poll or POLLNOW completing should interrupt 2 1 read-write TIMEOUT Is 1 if an integration cycle ending with timeout should interrupt 3 1 read-write OVERUN Is 1 if an overrun should interrupt. 4 1 read-write INTENCLR Interrupt enable clear 0x14 32 read-write 0 0x1F YESTOUCH clear the touch interrupt 0 1 read-write NOTOUCH clear the no-touch interrupt 1 1 read-write POLLDONE clear the poll or POLLNOW completing interrupt 2 1 read-write TIMEOUT clear the timeout interrupt 3 1 read-write OVERUN clear the overrun interrupt 4 1 read-write INTSTAT Interrupt status (mask of STATUS and INTEN) 0x18 32 read-write 0 0x1F YESTOUCH the status of touch interrrupt 0 1 read-only NOTOUCH the status of no-touch interrrupt 1 1 read-only POLLDONE the status of poll or pollnow completing interrupt 2 1 read-only TIMEOUT the status of timeout interrupt 3 1 read-only OVERUN the status of overrun interrupt 4 1 read-only TOUCH Last touch event (touch or no-touch) in context. 0x20 32 read-write 0 0x80F3FFFF COUNT Count value reached at trigger. If timeout, will be (1 bigger than TOUT)-1; e.g. if TOUT=12, then 0xFFF. 0 12 read-only XVAL Is the X that triggered this, or lowest X if more than one. 12 4 read-only ISTOUCH 1 if is Touch (by count) or 0 if is no-touch. 16 1 read-only ISTO 1 if is Timeout. 17 1 read-only SEQ Sequence number - rolling counter of polls. Changes after all selected Xs per poll (so, 0 for 1st set of Xs, then 1 for next set, etc). 20 4 read-only CHANGE If 1, the rest of the register is 0 because the data is changing. This will only happen for 1 cycle and would never happen if using interrupts to read, unless took so long as to overrun. 31 1 read-only ID Block ID 0xFFC 32 read-only 0xE1000000 0xFFFFFFFF APERTURE Aperture: encoded as (aperture size/4K) -1, so 0x00 is a 4 K aperture. 0 8 read-only MINOR_REV Minor revision of module implementation, starting at 0. Software compatibility is expected between minor revisions. 8 4 read-only MAJOR_REV Major revision of module implementation, starting at 0. There may not be software compatibility between major revisions. 12 4 read-only ID 1 if is Timeout. 16 16 read-only USART0 LPC84x USARTs USART 0x40064000 0 0x30 registers USART0 3 CFG USART Configuration register. Basic USART configuration settings that typically are not changed during operation. 0 32 read-write 0 0xFDDBFD ENABLE USART Enable. 0 1 read-write 0 Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available. #0 1 Enabled. The USART is enabled for operation. #1 DATALEN Selects the data size for the USART. 2 2 read-write 00 7 bit Data length. #00 01 8 bit Data length. #01 10 9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register. #10 PARITYSEL Selects what type of parity is used by the USART. 4 2 read-write 00 No parity. #00 10 Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even. #10 11 Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd. #11 STOPLEN Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. 6 1 read-write 0 1 stop bit. #0 1 2 stop bits. This setting should only be used for asynchronous communication. #1 CTSEN CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled. 9 1 read-write 0 No flow control. The transmitter does not receive any automatic flow control signal. #0 1 Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. #1 SYNCEN Selects synchronous or asynchronous operation. 11 1 read-write 0 Asynchronous mode. #0 1 Synchronous mode. #1 CLKPOL Selects the clock polarity and sampling edge of received data in synchronous mode. 12 1 read-write 0 Falling edge. Un_RXD is sampled on the falling edge of SCLK. #0 1 Rising edge. Un_RXD is sampled on the rising edge of SCLK. #1 SYNCMST Synchronous mode Master select. 14 1 read-write 0 Slave. When synchronous mode is enabled, the USART is a slave. #0 1 Master. When synchronous mode is enabled, the USART is a master. #1 LOOP Selects data loopback mode. 15 1 read-write 0 Normal operation. #0 1 Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. #1 OETA Output Enable Turnaround time enable for RS-485 operation. 18 1 read-write 0 Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission. #0 1 Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted. #1 AUTOADDR Automatic Address matching enable. 19 1 read-write 0 Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address). #0 1 Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match. #1 OESEL Output Enable Select. 20 1 read-write 0 Standard. The RTS signal is used as the standard flow control function. #0 1 RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. #1 OEPOL Output Enable Polarity. 21 1 read-write 0 Low. If selected by OESEL, the output enable is active low. #0 1 High. If selected by OESEL, the output enable is active high. #1 RXPOL Receive data polarity. 22 1 read-write 0 Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. #0 1 Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. #1 TXPOL Transmit data polarity. 23 1 read-write 0 Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. #0 1 Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. #1 CTL USART Control register. USART control settings that are more likely to change during operation. 0x4 32 read-write 0 0x10346 TXBRKEN Break Enable. 1 1 read-write 0 Normal operation. #0 1 Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. #1 ADDRDET Enable address detect mode. 2 1 read-write 0 Disabled. The USART presents all incoming data. #0 1 Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally. #1 TXDIS Transmit Disable. 6 1 read-write 0 Not disabled. USART transmitter is not disabled. #0 1 Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control. #1 CC Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. 8 1 read-write 0 Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received. #0 1 Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD). #1 CLRCCONRX Clear Continuous Clock. 9 1 read-write 0 No effect. No effect on the CC bit. #0 1 Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. #1 AUTOBAUD Autobaud enable. 16 1 read-write 0 Disabled. USART is in normal operating mode. #0 1 Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR. #1 STAT USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. 0x8 32 read-write 0xE 0x1FD7F RXRDY Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers. 0 1 read-only RXIDLE Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data. 1 1 read-only TXRDY Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift register. 2 1 read-only TXIDLE Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data. 3 1 read-only CTS This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled. 4 1 read-only DELTACTS This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software. 5 1 read-write TXDISSTAT Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CTL register (TXDIS = 1). 6 1 read-only OVERRUNINT Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost. 8 1 read-write RXBRK Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high. 10 1 read-only DELTARXBRK This bit is set when a change in the state of receiver break detection occurs.Cleared by software. 11 1 read-write START This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software. 12 1 read-write FRAMERRINT Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. 13 1 read-write PARITYERRINT Parity Error interrupt flag. This flag is set when a parity error is detected in a received character. 14 1 read-write RXNOISEINT Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception. 15 1 read-write ABERR Autobaud Error. An autobaud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an autobaud time-out. 16 1 read-write INTENSET Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. 0xC 32 read-write 0 0x1F96D RXRDYEN When 1, enables an interrupt when there is a received character available to be read from the RXDAT register. 0 1 read-write TXRDYEN When 1, enables an interrupt when the TXDAT register is available to take another character to transmit. 2 1 read-write TXIDLEEN When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1). 3 1 read-write DELTACTSEN When 1, enables an interrupt when there is a change in the state of the CTS input. 5 1 read-write TXDISEN When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details. 6 1 read-write OVERRUNEN When 1, enables an interrupt when an overrun error occurred. 8 1 read-write DELTARXBRKEN When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted). 11 1 read-write STARTEN When 1, enables an interrupt when a received start bit has been detected. 12 1 read-write FRAMERREN When 1, enables an interrupt when a framing error has been detected. 13 1 read-write PARITYERREN When 1, enables an interrupt when a parity error has been detected. 14 1 read-write RXNOISEEN When 1, enables an interrupt when noise is detected. 15 1 read-write ABERREN When 1, enables an interrupt when an autobaud error occurs. 16 1 read-write INTENCLR Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. 0x10 32 write-only 0 0 RXRDYCLR Writing 1 clears the corresponding bit in the INTENSET register. 0 1 write-only TXRDYCLR Writing 1 clears the corresponding bit in the INTENSET register. 2 1 write-only TXIDLECLR Writing 1 clears the corresponding bit in the INTENSET register. 3 1 write-only DELTACTSCLR Writing 1 clears the corresponding bit in the INTENSET register. 5 1 write-only TXDISINTCLR Writing 1 clears the corresponding bit in the INTENSET register. 6 1 write-only OVERRUNCLR Writing 1 clears the corresponding bit in the INTENSET register. 8 1 write-only DELTARXBRKCLR Writing 1 clears the corresponding bit in the INTENSET register. 11 1 write-only STARTCLR Writing 1 clears the corresponding bit in the INTENSET register. 12 1 write-only FRAMERRCLR Writing 1 clears the corresponding bit in the INTENSET register. 13 1 write-only PARITYERRCLR Writing 1 clears the corresponding bit in the INTENSET register. 14 1 write-only RXNOISECLR Writing 1 clears the corresponding bit in the INTENSET register. 15 1 write-only ABERRCLR Writing 1 clears the corresponding bit in the INTENSET register. 16 1 write-only RXDAT Receiver Data register. Contains the last character received. 0x14 32 read-only 0 0 RXDAT The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings. 0 9 read-only RXDATSTAT Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together. 0x18 32 read-only 0 0 RXDAT The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings. 0 9 read-only FRAMERR Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. 13 1 read-only PARITYERR Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character. 14 1 read-only RXNOISE Received Noise flag. 15 1 read-only TXDAT Transmit Data register. Data to be transmitted is written here. 0x1C 32 read-write 0 0x1FF TXDAT Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0. 0 9 read-write BRG Baud Rate Generator register. 16-bit integer baud rate divisor value. 0x20 32 read-write 0 0xFFFF BRGVAL This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function. 0 16 read-write INTSTAT Interrupt status register. Reflects interrupts that are currently enabled. 0x24 32 read-write 0xC 0x1F96D RXRDY Receiver Ready flag. 0 1 read-only TXRDY Transmitter Ready flag. 2 1 read-only TXIDLE Transmitter idle status. 3 1 read-only DELTACTS This bit is set when a change in the state of the CTS input is detected. 5 1 read-only TXDISINT Transmitter Disabled Interrupt flag. 6 1 read-only OVERRUNINT Overrun Error interrupt flag. 8 1 read-only DELTARXBRK This bit is set when a change in the state of receiver break detection occurs. 11 1 read-only START This bit is set when a start is detected on the receiver input. 12 1 read-only FRAMERRINT Framing Error interrupt flag. 13 1 read-only PARITYERRINT Parity Error interrupt flag. 14 1 read-only RXNOISEINT Received Noise interrupt flag. 15 1 read-only ABERR Autobaud Error flag. 16 1 read-only OSR Oversample selection register for asynchronous communication. 0x28 32 read-write 0xF 0xF OSRVAL Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit. 0 4 read-write ADDR Address register for automatic address matching. 0x2C 32 read-write 0 0xFF ADDRESS 8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1). 0 8 read-write USART1 LPC84x USARTs USART 0x40068000 0 0x30 registers USART1 4 CFG USART Configuration register. Basic USART configuration settings that typically are not changed during operation. 0 32 read-write 0 0xFDDBFD ENABLE USART Enable. 0 1 read-write 0 Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available. #0 1 Enabled. The USART is enabled for operation. #1 DATALEN Selects the data size for the USART. 2 2 read-write 00 7 bit Data length. #00 01 8 bit Data length. #01 10 9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register. #10 PARITYSEL Selects what type of parity is used by the USART. 4 2 read-write 00 No parity. #00 10 Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even. #10 11 Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd. #11 STOPLEN Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. 6 1 read-write 0 1 stop bit. #0 1 2 stop bits. This setting should only be used for asynchronous communication. #1 CTSEN CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled. 9 1 read-write 0 No flow control. The transmitter does not receive any automatic flow control signal. #0 1 Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. #1 SYNCEN Selects synchronous or asynchronous operation. 11 1 read-write 0 Asynchronous mode. #0 1 Synchronous mode. #1 CLKPOL Selects the clock polarity and sampling edge of received data in synchronous mode. 12 1 read-write 0 Falling edge. Un_RXD is sampled on the falling edge of SCLK. #0 1 Rising edge. Un_RXD is sampled on the rising edge of SCLK. #1 SYNCMST Synchronous mode Master select. 14 1 read-write 0 Slave. When synchronous mode is enabled, the USART is a slave. #0 1 Master. When synchronous mode is enabled, the USART is a master. #1 LOOP Selects data loopback mode. 15 1 read-write 0 Normal operation. #0 1 Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. #1 OETA Output Enable Turnaround time enable for RS-485 operation. 18 1 read-write 0 Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission. #0 1 Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted. #1 AUTOADDR Automatic Address matching enable. 19 1 read-write 0 Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address). #0 1 Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match. #1 OESEL Output Enable Select. 20 1 read-write 0 Standard. The RTS signal is used as the standard flow control function. #0 1 RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. #1 OEPOL Output Enable Polarity. 21 1 read-write 0 Low. If selected by OESEL, the output enable is active low. #0 1 High. If selected by OESEL, the output enable is active high. #1 RXPOL Receive data polarity. 22 1 read-write 0 Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. #0 1 Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. #1 TXPOL Transmit data polarity. 23 1 read-write 0 Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. #0 1 Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. #1 CTL USART Control register. USART control settings that are more likely to change during operation. 0x4 32 read-write 0 0x10346 TXBRKEN Break Enable. 1 1 read-write 0 Normal operation. #0 1 Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. #1 ADDRDET Enable address detect mode. 2 1 read-write 0 Disabled. The USART presents all incoming data. #0 1 Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally. #1 TXDIS Transmit Disable. 6 1 read-write 0 Not disabled. USART transmitter is not disabled. #0 1 Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control. #1 CC Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. 8 1 read-write 0 Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received. #0 1 Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD). #1 CLRCCONRX Clear Continuous Clock. 9 1 read-write 0 No effect. No effect on the CC bit. #0 1 Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. #1 AUTOBAUD Autobaud enable. 16 1 read-write 0 Disabled. USART is in normal operating mode. #0 1 Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR. #1 STAT USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. 0x8 32 read-write 0xE 0x1FD7F RXRDY Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers. 0 1 read-only RXIDLE Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data. 1 1 read-only TXRDY Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift register. 2 1 read-only TXIDLE Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data. 3 1 read-only CTS This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled. 4 1 read-only DELTACTS This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software. 5 1 read-write TXDISSTAT Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CTL register (TXDIS = 1). 6 1 read-only OVERRUNINT Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost. 8 1 read-write RXBRK Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high. 10 1 read-only DELTARXBRK This bit is set when a change in the state of receiver break detection occurs.Cleared by software. 11 1 read-write START This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software. 12 1 read-write FRAMERRINT Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. 13 1 read-write PARITYERRINT Parity Error interrupt flag. This flag is set when a parity error is detected in a received character. 14 1 read-write RXNOISEINT Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception. 15 1 read-write ABERR Autobaud Error. An autobaud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an autobaud time-out. 16 1 read-write INTENSET Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. 0xC 32 read-write 0 0x1F96D RXRDYEN When 1, enables an interrupt when there is a received character available to be read from the RXDAT register. 0 1 read-write TXRDYEN When 1, enables an interrupt when the TXDAT register is available to take another character to transmit. 2 1 read-write TXIDLEEN When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1). 3 1 read-write DELTACTSEN When 1, enables an interrupt when there is a change in the state of the CTS input. 5 1 read-write TXDISEN When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details. 6 1 read-write OVERRUNEN When 1, enables an interrupt when an overrun error occurred. 8 1 read-write DELTARXBRKEN When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted). 11 1 read-write STARTEN When 1, enables an interrupt when a received start bit has been detected. 12 1 read-write FRAMERREN When 1, enables an interrupt when a framing error has been detected. 13 1 read-write PARITYERREN When 1, enables an interrupt when a parity error has been detected. 14 1 read-write RXNOISEEN When 1, enables an interrupt when noise is detected. 15 1 read-write ABERREN When 1, enables an interrupt when an autobaud error occurs. 16 1 read-write INTENCLR Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. 0x10 32 write-only 0 0 RXRDYCLR Writing 1 clears the corresponding bit in the INTENSET register. 0 1 write-only TXRDYCLR Writing 1 clears the corresponding bit in the INTENSET register. 2 1 write-only TXIDLECLR Writing 1 clears the corresponding bit in the INTENSET register. 3 1 write-only DELTACTSCLR Writing 1 clears the corresponding bit in the INTENSET register. 5 1 write-only TXDISINTCLR Writing 1 clears the corresponding bit in the INTENSET register. 6 1 write-only OVERRUNCLR Writing 1 clears the corresponding bit in the INTENSET register. 8 1 write-only DELTARXBRKCLR Writing 1 clears the corresponding bit in the INTENSET register. 11 1 write-only STARTCLR Writing 1 clears the corresponding bit in the INTENSET register. 12 1 write-only FRAMERRCLR Writing 1 clears the corresponding bit in the INTENSET register. 13 1 write-only PARITYERRCLR Writing 1 clears the corresponding bit in the INTENSET register. 14 1 write-only RXNOISECLR Writing 1 clears the corresponding bit in the INTENSET register. 15 1 write-only ABERRCLR Writing 1 clears the corresponding bit in the INTENSET register. 16 1 write-only RXDAT Receiver Data register. Contains the last character received. 0x14 32 read-only 0 0 RXDAT The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings. 0 9 read-only RXDATSTAT Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together. 0x18 32 read-only 0 0 RXDAT The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings. 0 9 read-only FRAMERR Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. 13 1 read-only PARITYERR Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character. 14 1 read-only RXNOISE Received Noise flag. 15 1 read-only TXDAT Transmit Data register. Data to be transmitted is written here. 0x1C 32 read-write 0 0x1FF TXDAT Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0. 0 9 read-write BRG Baud Rate Generator register. 16-bit integer baud rate divisor value. 0x20 32 read-write 0 0xFFFF BRGVAL This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function. 0 16 read-write INTSTAT Interrupt status register. Reflects interrupts that are currently enabled. 0x24 32 read-write 0xC 0x1F96D RXRDY Receiver Ready flag. 0 1 read-only TXRDY Transmitter Ready flag. 2 1 read-only TXIDLE Transmitter idle status. 3 1 read-only DELTACTS This bit is set when a change in the state of the CTS input is detected. 5 1 read-only TXDISINT Transmitter Disabled Interrupt flag. 6 1 read-only OVERRUNINT Overrun Error interrupt flag. 8 1 read-only DELTARXBRK This bit is set when a change in the state of receiver break detection occurs. 11 1 read-only START This bit is set when a start is detected on the receiver input. 12 1 read-only FRAMERRINT Framing Error interrupt flag. 13 1 read-only PARITYERRINT Parity Error interrupt flag. 14 1 read-only RXNOISEINT Received Noise interrupt flag. 15 1 read-only ABERR Autobaud Error flag. 16 1 read-only OSR Oversample selection register for asynchronous communication. 0x28 32 read-write 0xF 0xF OSRVAL Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit. 0 4 read-write ADDR Address register for automatic address matching. 0x2C 32 read-write 0 0xFF ADDRESS 8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1). 0 8 read-write USART2 LPC84x USARTs USART 0x4006C000 0 0x30 registers USART2 5 CFG USART Configuration register. Basic USART configuration settings that typically are not changed during operation. 0 32 read-write 0 0xFDDBFD ENABLE USART Enable. 0 1 read-write 0 Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available. #0 1 Enabled. The USART is enabled for operation. #1 DATALEN Selects the data size for the USART. 2 2 read-write 00 7 bit Data length. #00 01 8 bit Data length. #01 10 9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register. #10 PARITYSEL Selects what type of parity is used by the USART. 4 2 read-write 00 No parity. #00 10 Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even. #10 11 Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd. #11 STOPLEN Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. 6 1 read-write 0 1 stop bit. #0 1 2 stop bits. This setting should only be used for asynchronous communication. #1 CTSEN CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled. 9 1 read-write 0 No flow control. The transmitter does not receive any automatic flow control signal. #0 1 Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. #1 SYNCEN Selects synchronous or asynchronous operation. 11 1 read-write 0 Asynchronous mode. #0 1 Synchronous mode. #1 CLKPOL Selects the clock polarity and sampling edge of received data in synchronous mode. 12 1 read-write 0 Falling edge. Un_RXD is sampled on the falling edge of SCLK. #0 1 Rising edge. Un_RXD is sampled on the rising edge of SCLK. #1 SYNCMST Synchronous mode Master select. 14 1 read-write 0 Slave. When synchronous mode is enabled, the USART is a slave. #0 1 Master. When synchronous mode is enabled, the USART is a master. #1 LOOP Selects data loopback mode. 15 1 read-write 0 Normal operation. #0 1 Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. #1 OETA Output Enable Turnaround time enable for RS-485 operation. 18 1 read-write 0 Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission. #0 1 Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted. #1 AUTOADDR Automatic Address matching enable. 19 1 read-write 0 Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address). #0 1 Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match. #1 OESEL Output Enable Select. 20 1 read-write 0 Standard. The RTS signal is used as the standard flow control function. #0 1 RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. #1 OEPOL Output Enable Polarity. 21 1 read-write 0 Low. If selected by OESEL, the output enable is active low. #0 1 High. If selected by OESEL, the output enable is active high. #1 RXPOL Receive data polarity. 22 1 read-write 0 Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. #0 1 Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. #1 TXPOL Transmit data polarity. 23 1 read-write 0 Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. #0 1 Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. #1 CTL USART Control register. USART control settings that are more likely to change during operation. 0x4 32 read-write 0 0x10346 TXBRKEN Break Enable. 1 1 read-write 0 Normal operation. #0 1 Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. #1 ADDRDET Enable address detect mode. 2 1 read-write 0 Disabled. The USART presents all incoming data. #0 1 Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally. #1 TXDIS Transmit Disable. 6 1 read-write 0 Not disabled. USART transmitter is not disabled. #0 1 Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control. #1 CC Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. 8 1 read-write 0 Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received. #0 1 Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD). #1 CLRCCONRX Clear Continuous Clock. 9 1 read-write 0 No effect. No effect on the CC bit. #0 1 Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. #1 AUTOBAUD Autobaud enable. 16 1 read-write 0 Disabled. USART is in normal operating mode. #0 1 Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR. #1 STAT USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. 0x8 32 read-write 0xE 0x1FD7F RXRDY Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers. 0 1 read-only RXIDLE Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data. 1 1 read-only TXRDY Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift register. 2 1 read-only TXIDLE Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data. 3 1 read-only CTS This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled. 4 1 read-only DELTACTS This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software. 5 1 read-write TXDISSTAT Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CTL register (TXDIS = 1). 6 1 read-only OVERRUNINT Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost. 8 1 read-write RXBRK Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high. 10 1 read-only DELTARXBRK This bit is set when a change in the state of receiver break detection occurs.Cleared by software. 11 1 read-write START This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software. 12 1 read-write FRAMERRINT Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. 13 1 read-write PARITYERRINT Parity Error interrupt flag. This flag is set when a parity error is detected in a received character. 14 1 read-write RXNOISEINT Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception. 15 1 read-write ABERR Autobaud Error. An autobaud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an autobaud time-out. 16 1 read-write INTENSET Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. 0xC 32 read-write 0 0x1F96D RXRDYEN When 1, enables an interrupt when there is a received character available to be read from the RXDAT register. 0 1 read-write TXRDYEN When 1, enables an interrupt when the TXDAT register is available to take another character to transmit. 2 1 read-write TXIDLEEN When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1). 3 1 read-write DELTACTSEN When 1, enables an interrupt when there is a change in the state of the CTS input. 5 1 read-write TXDISEN When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details. 6 1 read-write OVERRUNEN When 1, enables an interrupt when an overrun error occurred. 8 1 read-write DELTARXBRKEN When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted). 11 1 read-write STARTEN When 1, enables an interrupt when a received start bit has been detected. 12 1 read-write FRAMERREN When 1, enables an interrupt when a framing error has been detected. 13 1 read-write PARITYERREN When 1, enables an interrupt when a parity error has been detected. 14 1 read-write RXNOISEEN When 1, enables an interrupt when noise is detected. 15 1 read-write ABERREN When 1, enables an interrupt when an autobaud error occurs. 16 1 read-write INTENCLR Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. 0x10 32 write-only 0 0 RXRDYCLR Writing 1 clears the corresponding bit in the INTENSET register. 0 1 write-only TXRDYCLR Writing 1 clears the corresponding bit in the INTENSET register. 2 1 write-only TXIDLECLR Writing 1 clears the corresponding bit in the INTENSET register. 3 1 write-only DELTACTSCLR Writing 1 clears the corresponding bit in the INTENSET register. 5 1 write-only TXDISINTCLR Writing 1 clears the corresponding bit in the INTENSET register. 6 1 write-only OVERRUNCLR Writing 1 clears the corresponding bit in the INTENSET register. 8 1 write-only DELTARXBRKCLR Writing 1 clears the corresponding bit in the INTENSET register. 11 1 write-only STARTCLR Writing 1 clears the corresponding bit in the INTENSET register. 12 1 write-only FRAMERRCLR Writing 1 clears the corresponding bit in the INTENSET register. 13 1 write-only PARITYERRCLR Writing 1 clears the corresponding bit in the INTENSET register. 14 1 write-only RXNOISECLR Writing 1 clears the corresponding bit in the INTENSET register. 15 1 write-only ABERRCLR Writing 1 clears the corresponding bit in the INTENSET register. 16 1 write-only RXDAT Receiver Data register. Contains the last character received. 0x14 32 read-only 0 0 RXDAT The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings. 0 9 read-only RXDATSTAT Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together. 0x18 32 read-only 0 0 RXDAT The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings. 0 9 read-only FRAMERR Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. 13 1 read-only PARITYERR Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character. 14 1 read-only RXNOISE Received Noise flag. 15 1 read-only TXDAT Transmit Data register. Data to be transmitted is written here. 0x1C 32 read-write 0 0x1FF TXDAT Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0. 0 9 read-write BRG Baud Rate Generator register. 16-bit integer baud rate divisor value. 0x20 32 read-write 0 0xFFFF BRGVAL This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function. 0 16 read-write INTSTAT Interrupt status register. Reflects interrupts that are currently enabled. 0x24 32 read-write 0xC 0x1F96D RXRDY Receiver Ready flag. 0 1 read-only TXRDY Transmitter Ready flag. 2 1 read-only TXIDLE Transmitter idle status. 3 1 read-only DELTACTS This bit is set when a change in the state of the CTS input is detected. 5 1 read-only TXDISINT Transmitter Disabled Interrupt flag. 6 1 read-only OVERRUNINT Overrun Error interrupt flag. 8 1 read-only DELTARXBRK This bit is set when a change in the state of receiver break detection occurs. 11 1 read-only START This bit is set when a start is detected on the receiver input. 12 1 read-only FRAMERRINT Framing Error interrupt flag. 13 1 read-only PARITYERRINT Parity Error interrupt flag. 14 1 read-only RXNOISEINT Received Noise interrupt flag. 15 1 read-only ABERR Autobaud Error flag. 16 1 read-only OSR Oversample selection register for asynchronous communication. 0x28 32 read-write 0xF 0xF OSRVAL Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit. 0 4 read-write ADDR Address register for automatic address matching. 0x2C 32 read-write 0 0xFF ADDRESS 8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1). 0 8 read-write USART3 LPC84x USARTs USART 0x40070000 0 0x30 registers PIN_INT6_USART3 30 CFG USART Configuration register. Basic USART configuration settings that typically are not changed during operation. 0 32 read-write 0 0xFDDBFD ENABLE USART Enable. 0 1 read-write 0 Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available. #0 1 Enabled. The USART is enabled for operation. #1 DATALEN Selects the data size for the USART. 2 2 read-write 00 7 bit Data length. #00 01 8 bit Data length. #01 10 9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register. #10 PARITYSEL Selects what type of parity is used by the USART. 4 2 read-write 00 No parity. #00 10 Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even. #10 11 Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd. #11 STOPLEN Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. 6 1 read-write 0 1 stop bit. #0 1 2 stop bits. This setting should only be used for asynchronous communication. #1 CTSEN CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled. 9 1 read-write 0 No flow control. The transmitter does not receive any automatic flow control signal. #0 1 Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. #1 SYNCEN Selects synchronous or asynchronous operation. 11 1 read-write 0 Asynchronous mode. #0 1 Synchronous mode. #1 CLKPOL Selects the clock polarity and sampling edge of received data in synchronous mode. 12 1 read-write 0 Falling edge. Un_RXD is sampled on the falling edge of SCLK. #0 1 Rising edge. Un_RXD is sampled on the rising edge of SCLK. #1 SYNCMST Synchronous mode Master select. 14 1 read-write 0 Slave. When synchronous mode is enabled, the USART is a slave. #0 1 Master. When synchronous mode is enabled, the USART is a master. #1 LOOP Selects data loopback mode. 15 1 read-write 0 Normal operation. #0 1 Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. #1 OETA Output Enable Turnaround time enable for RS-485 operation. 18 1 read-write 0 Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission. #0 1 Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted. #1 AUTOADDR Automatic Address matching enable. 19 1 read-write 0 Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address). #0 1 Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match. #1 OESEL Output Enable Select. 20 1 read-write 0 Standard. The RTS signal is used as the standard flow control function. #0 1 RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. #1 OEPOL Output Enable Polarity. 21 1 read-write 0 Low. If selected by OESEL, the output enable is active low. #0 1 High. If selected by OESEL, the output enable is active high. #1 RXPOL Receive data polarity. 22 1 read-write 0 Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. #0 1 Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. #1 TXPOL Transmit data polarity. 23 1 read-write 0 Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. #0 1 Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. #1 CTL USART Control register. USART control settings that are more likely to change during operation. 0x4 32 read-write 0 0x10346 TXBRKEN Break Enable. 1 1 read-write 0 Normal operation. #0 1 Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. #1 ADDRDET Enable address detect mode. 2 1 read-write 0 Disabled. The USART presents all incoming data. #0 1 Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally. #1 TXDIS Transmit Disable. 6 1 read-write 0 Not disabled. USART transmitter is not disabled. #0 1 Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control. #1 CC Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. 8 1 read-write 0 Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received. #0 1 Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD). #1 CLRCCONRX Clear Continuous Clock. 9 1 read-write 0 No effect. No effect on the CC bit. #0 1 Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. #1 AUTOBAUD Autobaud enable. 16 1 read-write 0 Disabled. USART is in normal operating mode. #0 1 Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR. #1 STAT USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. 0x8 32 read-write 0xE 0x1FD7F RXRDY Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers. 0 1 read-only RXIDLE Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data. 1 1 read-only TXRDY Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift register. 2 1 read-only TXIDLE Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data. 3 1 read-only CTS This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled. 4 1 read-only DELTACTS This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software. 5 1 read-write TXDISSTAT Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CTL register (TXDIS = 1). 6 1 read-only OVERRUNINT Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost. 8 1 read-write RXBRK Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high. 10 1 read-only DELTARXBRK This bit is set when a change in the state of receiver break detection occurs.Cleared by software. 11 1 read-write START This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software. 12 1 read-write FRAMERRINT Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. 13 1 read-write PARITYERRINT Parity Error interrupt flag. This flag is set when a parity error is detected in a received character. 14 1 read-write RXNOISEINT Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception. 15 1 read-write ABERR Autobaud Error. An autobaud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an autobaud time-out. 16 1 read-write INTENSET Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. 0xC 32 read-write 0 0x1F96D RXRDYEN When 1, enables an interrupt when there is a received character available to be read from the RXDAT register. 0 1 read-write TXRDYEN When 1, enables an interrupt when the TXDAT register is available to take another character to transmit. 2 1 read-write TXIDLEEN When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1). 3 1 read-write DELTACTSEN When 1, enables an interrupt when there is a change in the state of the CTS input. 5 1 read-write TXDISEN When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details. 6 1 read-write OVERRUNEN When 1, enables an interrupt when an overrun error occurred. 8 1 read-write DELTARXBRKEN When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted). 11 1 read-write STARTEN When 1, enables an interrupt when a received start bit has been detected. 12 1 read-write FRAMERREN When 1, enables an interrupt when a framing error has been detected. 13 1 read-write PARITYERREN When 1, enables an interrupt when a parity error has been detected. 14 1 read-write RXNOISEEN When 1, enables an interrupt when noise is detected. 15 1 read-write ABERREN When 1, enables an interrupt when an autobaud error occurs. 16 1 read-write INTENCLR Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. 0x10 32 write-only 0 0 RXRDYCLR Writing 1 clears the corresponding bit in the INTENSET register. 0 1 write-only TXRDYCLR Writing 1 clears the corresponding bit in the INTENSET register. 2 1 write-only TXIDLECLR Writing 1 clears the corresponding bit in the INTENSET register. 3 1 write-only DELTACTSCLR Writing 1 clears the corresponding bit in the INTENSET register. 5 1 write-only TXDISINTCLR Writing 1 clears the corresponding bit in the INTENSET register. 6 1 write-only OVERRUNCLR Writing 1 clears the corresponding bit in the INTENSET register. 8 1 write-only DELTARXBRKCLR Writing 1 clears the corresponding bit in the INTENSET register. 11 1 write-only STARTCLR Writing 1 clears the corresponding bit in the INTENSET register. 12 1 write-only FRAMERRCLR Writing 1 clears the corresponding bit in the INTENSET register. 13 1 write-only PARITYERRCLR Writing 1 clears the corresponding bit in the INTENSET register. 14 1 write-only RXNOISECLR Writing 1 clears the corresponding bit in the INTENSET register. 15 1 write-only ABERRCLR Writing 1 clears the corresponding bit in the INTENSET register. 16 1 write-only RXDAT Receiver Data register. Contains the last character received. 0x14 32 read-only 0 0 RXDAT The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings. 0 9 read-only RXDATSTAT Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together. 0x18 32 read-only 0 0 RXDAT The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings. 0 9 read-only FRAMERR Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. 13 1 read-only PARITYERR Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character. 14 1 read-only RXNOISE Received Noise flag. 15 1 read-only TXDAT Transmit Data register. Data to be transmitted is written here. 0x1C 32 read-write 0 0x1FF TXDAT Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0. 0 9 read-write BRG Baud Rate Generator register. 16-bit integer baud rate divisor value. 0x20 32 read-write 0 0xFFFF BRGVAL This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function. 0 16 read-write INTSTAT Interrupt status register. Reflects interrupts that are currently enabled. 0x24 32 read-write 0xC 0x1F96D RXRDY Receiver Ready flag. 0 1 read-only TXRDY Transmitter Ready flag. 2 1 read-only TXIDLE Transmitter idle status. 3 1 read-only DELTACTS This bit is set when a change in the state of the CTS input is detected. 5 1 read-only TXDISINT Transmitter Disabled Interrupt flag. 6 1 read-only OVERRUNINT Overrun Error interrupt flag. 8 1 read-only DELTARXBRK This bit is set when a change in the state of receiver break detection occurs. 11 1 read-only START This bit is set when a start is detected on the receiver input. 12 1 read-only FRAMERRINT Framing Error interrupt flag. 13 1 read-only PARITYERRINT Parity Error interrupt flag. 14 1 read-only RXNOISEINT Received Noise interrupt flag. 15 1 read-only ABERR Autobaud Error flag. 16 1 read-only OSR Oversample selection register for asynchronous communication. 0x28 32 read-write 0xF 0xF OSRVAL Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit. 0 4 read-write ADDR Address register for automatic address matching. 0x2C 32 read-write 0 0xFF ADDRESS 8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1). 0 8 read-write USART4 LPC84x USARTs USART 0x40074000 0 0x30 registers PIN_INT7_USART4 31 CFG USART Configuration register. Basic USART configuration settings that typically are not changed during operation. 0 32 read-write 0 0xFDDBFD ENABLE USART Enable. 0 1 read-write 0 Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available. #0 1 Enabled. The USART is enabled for operation. #1 DATALEN Selects the data size for the USART. 2 2 read-write 00 7 bit Data length. #00 01 8 bit Data length. #01 10 9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register. #10 PARITYSEL Selects what type of parity is used by the USART. 4 2 read-write 00 No parity. #00 10 Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even. #10 11 Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd. #11 STOPLEN Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. 6 1 read-write 0 1 stop bit. #0 1 2 stop bits. This setting should only be used for asynchronous communication. #1 CTSEN CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled. 9 1 read-write 0 No flow control. The transmitter does not receive any automatic flow control signal. #0 1 Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. #1 SYNCEN Selects synchronous or asynchronous operation. 11 1 read-write 0 Asynchronous mode. #0 1 Synchronous mode. #1 CLKPOL Selects the clock polarity and sampling edge of received data in synchronous mode. 12 1 read-write 0 Falling edge. Un_RXD is sampled on the falling edge of SCLK. #0 1 Rising edge. Un_RXD is sampled on the rising edge of SCLK. #1 SYNCMST Synchronous mode Master select. 14 1 read-write 0 Slave. When synchronous mode is enabled, the USART is a slave. #0 1 Master. When synchronous mode is enabled, the USART is a master. #1 LOOP Selects data loopback mode. 15 1 read-write 0 Normal operation. #0 1 Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. #1 OETA Output Enable Turnaround time enable for RS-485 operation. 18 1 read-write 0 Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission. #0 1 Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted. #1 AUTOADDR Automatic Address matching enable. 19 1 read-write 0 Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address). #0 1 Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match. #1 OESEL Output Enable Select. 20 1 read-write 0 Standard. The RTS signal is used as the standard flow control function. #0 1 RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. #1 OEPOL Output Enable Polarity. 21 1 read-write 0 Low. If selected by OESEL, the output enable is active low. #0 1 High. If selected by OESEL, the output enable is active high. #1 RXPOL Receive data polarity. 22 1 read-write 0 Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. #0 1 Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. #1 TXPOL Transmit data polarity. 23 1 read-write 0 Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. #0 1 Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. #1 CTL USART Control register. USART control settings that are more likely to change during operation. 0x4 32 read-write 0 0x10346 TXBRKEN Break Enable. 1 1 read-write 0 Normal operation. #0 1 Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. #1 ADDRDET Enable address detect mode. 2 1 read-write 0 Disabled. The USART presents all incoming data. #0 1 Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally. #1 TXDIS Transmit Disable. 6 1 read-write 0 Not disabled. USART transmitter is not disabled. #0 1 Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control. #1 CC Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. 8 1 read-write 0 Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received. #0 1 Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD). #1 CLRCCONRX Clear Continuous Clock. 9 1 read-write 0 No effect. No effect on the CC bit. #0 1 Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. #1 AUTOBAUD Autobaud enable. 16 1 read-write 0 Disabled. USART is in normal operating mode. #0 1 Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR. #1 STAT USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. 0x8 32 read-write 0xE 0x1FD7F RXRDY Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers. 0 1 read-only RXIDLE Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data. 1 1 read-only TXRDY Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift register. 2 1 read-only TXIDLE Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data. 3 1 read-only CTS This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled. 4 1 read-only DELTACTS This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software. 5 1 read-write TXDISSTAT Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CTL register (TXDIS = 1). 6 1 read-only OVERRUNINT Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost. 8 1 read-write RXBRK Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high. 10 1 read-only DELTARXBRK This bit is set when a change in the state of receiver break detection occurs.Cleared by software. 11 1 read-write START This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software. 12 1 read-write FRAMERRINT Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. 13 1 read-write PARITYERRINT Parity Error interrupt flag. This flag is set when a parity error is detected in a received character. 14 1 read-write RXNOISEINT Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception. 15 1 read-write ABERR Autobaud Error. An autobaud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an autobaud time-out. 16 1 read-write INTENSET Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. 0xC 32 read-write 0 0x1F96D RXRDYEN When 1, enables an interrupt when there is a received character available to be read from the RXDAT register. 0 1 read-write TXRDYEN When 1, enables an interrupt when the TXDAT register is available to take another character to transmit. 2 1 read-write TXIDLEEN When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1). 3 1 read-write DELTACTSEN When 1, enables an interrupt when there is a change in the state of the CTS input. 5 1 read-write TXDISEN When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details. 6 1 read-write OVERRUNEN When 1, enables an interrupt when an overrun error occurred. 8 1 read-write DELTARXBRKEN When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted). 11 1 read-write STARTEN When 1, enables an interrupt when a received start bit has been detected. 12 1 read-write FRAMERREN When 1, enables an interrupt when a framing error has been detected. 13 1 read-write PARITYERREN When 1, enables an interrupt when a parity error has been detected. 14 1 read-write RXNOISEEN When 1, enables an interrupt when noise is detected. 15 1 read-write ABERREN When 1, enables an interrupt when an autobaud error occurs. 16 1 read-write INTENCLR Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. 0x10 32 write-only 0 0 RXRDYCLR Writing 1 clears the corresponding bit in the INTENSET register. 0 1 write-only TXRDYCLR Writing 1 clears the corresponding bit in the INTENSET register. 2 1 write-only TXIDLECLR Writing 1 clears the corresponding bit in the INTENSET register. 3 1 write-only DELTACTSCLR Writing 1 clears the corresponding bit in the INTENSET register. 5 1 write-only TXDISINTCLR Writing 1 clears the corresponding bit in the INTENSET register. 6 1 write-only OVERRUNCLR Writing 1 clears the corresponding bit in the INTENSET register. 8 1 write-only DELTARXBRKCLR Writing 1 clears the corresponding bit in the INTENSET register. 11 1 write-only STARTCLR Writing 1 clears the corresponding bit in the INTENSET register. 12 1 write-only FRAMERRCLR Writing 1 clears the corresponding bit in the INTENSET register. 13 1 write-only PARITYERRCLR Writing 1 clears the corresponding bit in the INTENSET register. 14 1 write-only RXNOISECLR Writing 1 clears the corresponding bit in the INTENSET register. 15 1 write-only ABERRCLR Writing 1 clears the corresponding bit in the INTENSET register. 16 1 write-only RXDAT Receiver Data register. Contains the last character received. 0x14 32 read-only 0 0 RXDAT The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings. 0 9 read-only RXDATSTAT Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together. 0x18 32 read-only 0 0 RXDAT The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings. 0 9 read-only FRAMERR Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. 13 1 read-only PARITYERR Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character. 14 1 read-only RXNOISE Received Noise flag. 15 1 read-only TXDAT Transmit Data register. Data to be transmitted is written here. 0x1C 32 read-write 0 0x1FF TXDAT Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0. 0 9 read-write BRG Baud Rate Generator register. 16-bit integer baud rate divisor value. 0x20 32 read-write 0 0xFFFF BRGVAL This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function. 0 16 read-write INTSTAT Interrupt status register. Reflects interrupts that are currently enabled. 0x24 32 read-write 0xC 0x1F96D RXRDY Receiver Ready flag. 0 1 read-only TXRDY Transmitter Ready flag. 2 1 read-only TXIDLE Transmitter idle status. 3 1 read-only DELTACTS This bit is set when a change in the state of the CTS input is detected. 5 1 read-only TXDISINT Transmitter Disabled Interrupt flag. 6 1 read-only OVERRUNINT Overrun Error interrupt flag. 8 1 read-only DELTARXBRK This bit is set when a change in the state of receiver break detection occurs. 11 1 read-only START This bit is set when a start is detected on the receiver input. 12 1 read-only FRAMERRINT Framing Error interrupt flag. 13 1 read-only PARITYERRINT Parity Error interrupt flag. 14 1 read-only RXNOISEINT Received Noise interrupt flag. 15 1 read-only ABERR Autobaud Error flag. 16 1 read-only OSR Oversample selection register for asynchronous communication. 0x28 32 read-write 0xF 0xF OSRVAL Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit. 0 4 read-write ADDR Address register for automatic address matching. 0x2C 32 read-write 0 0xFF ADDRESS 8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1). 0 8 read-write CRC LPC5411x CRC engine 0x50000000 0 0xC registers MODE CRC mode register 0 32 read-write 0 0x3F CRC_POLY CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial 0 2 read-write BIT_RVS_WR Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte) 2 1 read-write CMPL_WR Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA 3 1 read-write BIT_RVS_SUM CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM 4 1 read-write CMPL_SUM CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM 5 1 read-write SEED CRC seed register 0x4 32 read-write 0xFFFF 0xFFFFFFFF CRC_SEED A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1's complement pre-processes. A write access to this register will overrule the CRC calculation in progresses. 0 32 read-write SUM CRC checksum register CRC 0x8 32 read-only 0xFFFF 0xFFFFFFFF CRC_SUM The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes. 0 32 read-only WR_DATA CRC data register CRC 0x8 32 write-only 0 0 CRC_WR_DATA Data written to this register will be taken to perform CRC calculation with selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions. 0 32 write-only SCT0 LPC84x SCTimer/PWM (SCT) 0x50004000 0 0x538 registers SCT0 9 CONFIG SCT configuration register 0 32 read-write 0x1E00 0x61FFF UNIFY SCT operation 0 1 read-write 0 The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H. #0 1 The SCT operates as a unified 32-bit counter. #1 CLKMODE SCT clock mode 1 2 read-write 00 System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers. #00 01 Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the high-performance, sampled-clock mode. #01 10 SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode. #10 11 Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system clock. The input clock rate must be at least half the system clock rate and can be the same or faster than the system clock. #11 CKSEL SCT clock select. The specific functionality of the designated input/edge is dependent on the CLKMODE bit selection in this register. 3 4 read-write 000 Rising edges on input 0. #0000 001 Falling edges on input 0. #0001 010 Rising edges on input 1. #0010 011 Falling edges on input 1. #0011 100 Rising edges on input 2. #0100 101 Falling edges on input 2. #0101 110 Rising edges on input 3. #0110 111 Falling edges on input 3. #0111 NORELOAD_L A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. 7 1 read-write NORELOAD_H A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. 8 1 read-write INSYNC Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is known to already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. It does not apply to the clock input specified in the CKSEL field. 9 4 read-write AUTOLIMIT_L A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. 17 1 read-write AUTOLIMIT_H A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. 18 1 read-write CTRL SCT control register 0x4 32 read-write 0x40004 0x1FFF1FFF DOWN_L This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0. 0 1 read-write STOP_L When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events related to the counter can occur. If a designated start event occurs, this bit is cleared and counting resumes. 1 1 read-write HALT_L When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, only software can clear this bit to restore counter operation. This bit is set on reset. 2 1 read-write CLRCTR_L Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. 3 1 read-write BIDIR_L L or unified counter direction select 4 1 read-write 0 Up. The counter counts up to a limit condition, then is cleared to zero. #0 1 Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. #1 PRE_L Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. 5 8 read-write DOWN_H This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0. 16 1 read-write STOP_H When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes. 17 1 read-write HALT_H When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit can only be cleared by software to restore counter operation. This bit is set on reset. 18 1 read-write CLRCTR_H Writing a 1 to this bit clears the H counter. This bit always reads as 0. 19 1 read-write BIDIR_H Direction select 20 1 read-write 0 The H counter counts up to its limit condition, then is cleared to zero. #0 1 The H counter counts up to its limit, then counts down to a limit condition or to 0. #1 PRE_H Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. 21 8 read-write LIMIT SCT limit event select register 0x8 32 read-write 0 0xFFFFFFFF LIMMSK_L If bit n is one, event n is used as a counter limit for the L or unified counter (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 0 8 read-write LIMMSK_H If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. 16 8 read-write HALT SCT halt event select register 0xC 32 read-write 0 0xFFFFFFFF HALTMSK_L If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 0 8 read-write HALTMSK_H If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. 16 8 read-write STOP SCT stop event select register 0x10 32 read-write 0 0xFFFFFFFF STOPMSK_L If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 0 8 read-write STOPMSK_H If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. 16 8 read-write START SCT start event select register 0x14 32 read-write 0 0xFFFFFFFF STARTMSK_L If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 0 8 read-write STARTMSK_H If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. 16 8 read-write COUNT SCT counter register 0x40 32 read-write 0 0xFFFFFFFF CTR_L When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter. 0 16 read-write CTR_H When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter. 16 16 read-write STATE SCT state register 0x44 32 read-write 0 0x1F001F STATE_L State variable. 0 5 read-write STATE_H State variable. 16 5 read-write INPUT SCT input register 0x48 32 read-write 0 0xFFFFFFFF AIN0 Input 0 state. Input 0 state on the last SCT clock edge. 0 1 read-only AIN1 Input 1 state. Input 1 state on the last SCT clock edge. 1 1 read-only AIN2 Input 2 state. Input 2 state on the last SCT clock edge. 2 1 read-only AIN3 Input 3 state. Input 3 state on the last SCT clock edge. 3 1 read-only AIN4 Input 4 state. Input 4 state on the last SCT clock edge. 4 1 read-only SIN0 Input 0 state. Input 0 state following the synchronization specified by INSYNC. 16 1 read-only SIN1 Input 1 state. Input 1 state following the synchronization specified by INSYNC. 17 1 read-only SIN2 Input 2 state. Input 2 state following the synchronization specified by INSYNC. 18 1 read-only SIN3 Input 3 state. Input 3 state following the synchronization specified by INSYNC. 19 1 read-only SIN4 Input 4 state. Input 4 state following the synchronization specified by INSYNC. 20 1 read-only REGMODE SCT match/capture mode register 0x4C 32 read-write 0 0xFFFFFFFF REGMOD_L Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match register. 1 = register operates as capture register. 0 8 read-write REGMOD_H Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match registers. 1 = register operates as capture registers. 16 8 read-write OUTPUT SCT output register 0x50 32 read-write 0 0xFFFF OUT Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT. 0 7 read-write OUTPUTDIRCTRL SCT output counter direction control register 0x54 32 read-write 0 0xFFFFFFFF SETCLR0 Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. 0 2 read-write 00 Set and clear do not depend on the direction of any counter. #00 01 Set and clear are reversed when counter L or the unified counter is counting down. #01 10 Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. #10 SETCLR1 Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. 2 2 read-write 00 Set and clear do not depend on the direction of any counter. #00 01 Set and clear are reversed when counter L or the unified counter is counting down. #01 10 Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. #10 SETCLR2 Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. 4 2 read-write 00 Set and clear do not depend on the direction of any counter. #00 01 Set and clear are reversed when counter L or the unified counter is counting down. #01 10 Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. #10 SETCLR3 Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. 6 2 read-write 00 Set and clear do not depend on the direction of any counter. #00 01 Set and clear are reversed when counter L or the unified counter is counting down. #01 10 Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. #10 SETCLR4 Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. 8 2 read-write 00 Set and clear do not depend on the direction of any counter. #00 01 Set and clear are reversed when counter L or the unified counter is counting down. #01 10 Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. #10 SETCLR5 Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. 10 2 read-write 00 Set and clear do not depend on the direction of any counter. #00 01 Set and clear are reversed when counter L or the unified counter is counting down. #01 10 Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. #10 SETCLR6 Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value. 12 2 read-write 00 Set and clear do not depend on the direction of any counter. #00 01 Set and clear are reversed when counter L or the unified counter is counting down. #01 10 Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. #10 RES SCT conflict resolution register 0x58 32 read-write 0 0xFFFFFFFF O0RES Effect of simultaneous set and clear on output 0. 0 2 read-write 00 No change. #00 01 Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register). #01 10 Clear output (or set based on the SETCLR0 field). #10 11 Toggle output. #11 O1RES Effect of simultaneous set and clear on output 1. 2 2 read-write 00 No change. #00 01 Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register). #01 10 Clear output (or set based on the SETCLR1 field). #10 11 Toggle output. #11 O2RES Effect of simultaneous set and clear on output 2. 4 2 read-write 00 No change. #00 01 Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register). #01 10 Clear output n (or set based on the SETCLR2 field). #10 11 Toggle output. #11 O3RES Effect of simultaneous set and clear on output 3. 6 2 read-write 00 No change. #00 01 Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register). #01 10 Clear output (or set based on the SETCLR3 field). #10 11 Toggle output. #11 O4RES Effect of simultaneous set and clear on output 4. 8 2 read-write 00 No change. #00 01 Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register). #01 10 Clear output (or set based on the SETCLR4 field). #10 11 Toggle output. #11 O5RES Effect of simultaneous set and clear on output 5. 10 2 read-write 00 No change. #00 01 Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register). #01 10 Clear output (or set based on the SETCLR5 field). #10 11 Toggle output. #11 O6RES Effect of simultaneous set and clear on output 6. 12 2 read-write 00 No change. #00 01 Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register). #01 10 Clear output (or set based on the SETCLR6 field). #10 11 Toggle output. #11 DMAREQ0 SCT DMA request 0 register 0x5C 32 read-write 0 0xC000FFFF DEV_0 If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 0 6 read-write DRL0 A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers. 30 1 read-write DRQ0 This read-only bit indicates the state of DMA Request 0. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup. 31 1 read-write DMAREQ1 SCT DMA request 1 register 0x60 32 read-write 0 0xC000FFFF DEV_1 If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 0 6 read-write DRL1 A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers. 30 1 read-write DRQ1 This read-only bit indicates the state of DMA Request 1. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup. 31 1 read-write EVEN SCT event interrupt enable register 0xF0 32 read-write 0 0xFFFF IEN The SCT requests an interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 0 8 read-write EVFLAG SCT event flag register 0xF4 32 read-write 0 0xFFFF FLAG Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 0 8 read-write CONEN SCT conflict interrupt enable register 0xF8 32 read-write 0 0xFFFF NCEN The SCT requests an interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT. 0 6 read-write CONFLAG SCT conflict flag register 0xFC 32 read-write 0 0xC000FFFF NCFLAG Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT. 0 6 read-write BUSERRL The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful. 30 1 read-write BUSERRH The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted. 31 1 read-write CAP0 SCT capture register of capture channel SCT0 0x100 32 read-write 0 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. 0 16 read-write CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. 16 16 read-write MATCH0 SCT match value register of match channels SCT0 0x100 32 read-write 0 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. 0 16 read-write MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. 16 16 read-write CAP1 SCT capture register of capture channel SCT0 0x104 32 read-write 0 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. 0 16 read-write CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. 16 16 read-write MATCH1 SCT match value register of match channels SCT0 0x104 32 read-write 0 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. 0 16 read-write MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. 16 16 read-write CAP2 SCT capture register of capture channel SCT0 0x108 32 read-write 0 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. 0 16 read-write CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. 16 16 read-write MATCH2 SCT match value register of match channels SCT0 0x108 32 read-write 0 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. 0 16 read-write MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. 16 16 read-write CAP3 SCT capture register of capture channel SCT0 0x10C 32 read-write 0 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. 0 16 read-write CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. 16 16 read-write MATCH3 SCT match value register of match channels SCT0 0x10C 32 read-write 0 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. 0 16 read-write MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. 16 16 read-write CAP4 SCT capture register of capture channel SCT0 0x110 32 read-write 0 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. 0 16 read-write CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. 16 16 read-write MATCH4 SCT match value register of match channels SCT0 0x110 32 read-write 0 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. 0 16 read-write MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. 16 16 read-write CAP5 SCT capture register of capture channel SCT0 0x114 32 read-write 0 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. 0 16 read-write CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. 16 16 read-write MATCH5 SCT match value register of match channels SCT0 0x114 32 read-write 0 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. 0 16 read-write MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. 16 16 read-write CAP6 SCT capture register of capture channel SCT0 0x118 32 read-write 0 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. 0 16 read-write CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. 16 16 read-write MATCH6 SCT match value register of match channels SCT0 0x118 32 read-write 0 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. 0 16 read-write MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. 16 16 read-write CAP7 SCT capture register of capture channel SCT0 0x11C 32 read-write 0 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. 0 16 read-write CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. 16 16 read-write MATCH7 SCT match value register of match channels SCT0 0x11C 32 read-write 0 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. 0 16 read-write MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. 16 16 read-write CAPCTRL0 SCT capture control register SCT0 0x200 32 read-write 0 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 8 read-write CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 16 8 read-write MATCHREL0 SCT match reload value register SCT0 0x200 32 read-write 0 0xFFFFFFFF RELOADn_L When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 16 read-write RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. 16 16 read-write CAPCTRL1 SCT capture control register SCT0 0x204 32 read-write 0 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 8 read-write CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 16 8 read-write MATCHREL1 SCT match reload value register SCT0 0x204 32 read-write 0 0xFFFFFFFF RELOADn_L When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 16 read-write RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. 16 16 read-write CAPCTRL2 SCT capture control register SCT0 0x208 32 read-write 0 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 8 read-write CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 16 8 read-write MATCHREL2 SCT match reload value register SCT0 0x208 32 read-write 0 0xFFFFFFFF RELOADn_L When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 16 read-write RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. 16 16 read-write CAPCTRL3 SCT capture control register SCT0 0x20C 32 read-write 0 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 8 read-write CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 16 8 read-write MATCHREL3 SCT match reload value register SCT0 0x20C 32 read-write 0 0xFFFFFFFF RELOADn_L When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 16 read-write RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. 16 16 read-write CAPCTRL4 SCT capture control register SCT0 0x210 32 read-write 0 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 8 read-write CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 16 8 read-write MATCHREL4 SCT match reload value register SCT0 0x210 32 read-write 0 0xFFFFFFFF RELOADn_L When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 16 read-write RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. 16 16 read-write CAPCTRL5 SCT capture control register SCT0 0x214 32 read-write 0 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 8 read-write CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 16 8 read-write MATCHREL5 SCT match reload value register SCT0 0x214 32 read-write 0 0xFFFFFFFF RELOADn_L When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 16 read-write RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. 16 16 read-write CAPCTRL6 SCT capture control register SCT0 0x218 32 read-write 0 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 8 read-write CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 16 8 read-write MATCHREL6 SCT match reload value register SCT0 0x218 32 read-write 0 0xFFFFFFFF RELOADn_L When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 16 read-write RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. 16 16 read-write CAPCTRL7 SCT capture control register SCT0 0x21C 32 read-write 0 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 8 read-write CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 16 8 read-write MATCHREL7 SCT match reload value register SCT0 0x21C 32 read-write 0 0xFFFFFFFF RELOADn_L When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 16 read-write RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. 16 16 read-write EV0_STATE SCT event state register 0 0x300 32 read-write 0 0xFFFF STATEMSKn If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT. 0 8 read-write EV0_CTRL SCT event control register 0 0x304 32 read-write 0 0x7FFFFF MATCHSEL Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running. 0 4 read-write HEVENT Select L/H counter. Do not set this bit if UNIFY = 1. 4 1 read-write 0 Selects the L state and the L match register selected by MATCHSEL. #0 1 Selects the H state and the H match register selected by MATCHSEL. #1 OUTSEL Input/output select 5 1 read-write 0 Selects the inputs selected by IOSEL. #0 1 Selects the outputs selected by IOSEL. #1 IOSEL Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event. 6 4 read-write IOCOND Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period . 10 2 read-write 00 LOW #00 01 Rise #01 10 Fall #10 11 HIGH #11 COMBMODE Selects how the specified match and I/O condition are used and combined. 12 2 read-write 00 OR. The event occurs when either the specified match or I/O condition occurs. #00 01 MATCH. Uses the specified match only. #01 10 IO. Uses the specified I/O condition only. #10 11 AND. The event occurs when the specified match and I/O condition occur simultaneously. #11 STATELD This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state. 14 1 read-write 0 STATEV value is added into STATE (the carry-out is ignored). #0 1 STATEV value is loaded into STATE. #1 STATEV This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value. 15 5 read-write MATCHMEM If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value. 20 1 read-write DIRECTION Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. 21 2 read-write 00 Direction independent. This event is triggered regardless of the count direction. #00 01 Counting up. This event is triggered only during up-counting when BIDIR = 1. #01 10 Counting down. This event is triggered only during down-counting when BIDIR = 1. #10 EV1_STATE SCT event state register 0 0x308 32 read-write 0 0xFFFF STATEMSKn If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT. 0 8 read-write EV1_CTRL SCT event control register 0 0x30C 32 read-write 0 0x7FFFFF MATCHSEL Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running. 0 4 read-write HEVENT Select L/H counter. Do not set this bit if UNIFY = 1. 4 1 read-write 0 Selects the L state and the L match register selected by MATCHSEL. #0 1 Selects the H state and the H match register selected by MATCHSEL. #1 OUTSEL Input/output select 5 1 read-write 0 Selects the inputs selected by IOSEL. #0 1 Selects the outputs selected by IOSEL. #1 IOSEL Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event. 6 4 read-write IOCOND Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period . 10 2 read-write 00 LOW #00 01 Rise #01 10 Fall #10 11 HIGH #11 COMBMODE Selects how the specified match and I/O condition are used and combined. 12 2 read-write 00 OR. The event occurs when either the specified match or I/O condition occurs. #00 01 MATCH. Uses the specified match only. #01 10 IO. Uses the specified I/O condition only. #10 11 AND. The event occurs when the specified match and I/O condition occur simultaneously. #11 STATELD This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state. 14 1 read-write 0 STATEV value is added into STATE (the carry-out is ignored). #0 1 STATEV value is loaded into STATE. #1 STATEV This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value. 15 5 read-write MATCHMEM If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value. 20 1 read-write DIRECTION Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. 21 2 read-write 00 Direction independent. This event is triggered regardless of the count direction. #00 01 Counting up. This event is triggered only during up-counting when BIDIR = 1. #01 10 Counting down. This event is triggered only during down-counting when BIDIR = 1. #10 EV2_STATE SCT event state register 0 0x310 32 read-write 0 0xFFFF STATEMSKn If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT. 0 8 read-write EV2_CTRL SCT event control register 0 0x314 32 read-write 0 0x7FFFFF MATCHSEL Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running. 0 4 read-write HEVENT Select L/H counter. Do not set this bit if UNIFY = 1. 4 1 read-write 0 Selects the L state and the L match register selected by MATCHSEL. #0 1 Selects the H state and the H match register selected by MATCHSEL. #1 OUTSEL Input/output select 5 1 read-write 0 Selects the inputs selected by IOSEL. #0 1 Selects the outputs selected by IOSEL. #1 IOSEL Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event. 6 4 read-write IOCOND Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period . 10 2 read-write 00 LOW #00 01 Rise #01 10 Fall #10 11 HIGH #11 COMBMODE Selects how the specified match and I/O condition are used and combined. 12 2 read-write 00 OR. The event occurs when either the specified match or I/O condition occurs. #00 01 MATCH. Uses the specified match only. #01 10 IO. Uses the specified I/O condition only. #10 11 AND. The event occurs when the specified match and I/O condition occur simultaneously. #11 STATELD This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state. 14 1 read-write 0 STATEV value is added into STATE (the carry-out is ignored). #0 1 STATEV value is loaded into STATE. #1 STATEV This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value. 15 5 read-write MATCHMEM If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value. 20 1 read-write DIRECTION Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. 21 2 read-write 00 Direction independent. This event is triggered regardless of the count direction. #00 01 Counting up. This event is triggered only during up-counting when BIDIR = 1. #01 10 Counting down. This event is triggered only during down-counting when BIDIR = 1. #10 EV3_STATE SCT event state register 0 0x318 32 read-write 0 0xFFFF STATEMSKn If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT. 0 8 read-write EV3_CTRL SCT event control register 0 0x31C 32 read-write 0 0x7FFFFF MATCHSEL Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running. 0 4 read-write HEVENT Select L/H counter. Do not set this bit if UNIFY = 1. 4 1 read-write 0 Selects the L state and the L match register selected by MATCHSEL. #0 1 Selects the H state and the H match register selected by MATCHSEL. #1 OUTSEL Input/output select 5 1 read-write 0 Selects the inputs selected by IOSEL. #0 1 Selects the outputs selected by IOSEL. #1 IOSEL Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event. 6 4 read-write IOCOND Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period . 10 2 read-write 00 LOW #00 01 Rise #01 10 Fall #10 11 HIGH #11 COMBMODE Selects how the specified match and I/O condition are used and combined. 12 2 read-write 00 OR. The event occurs when either the specified match or I/O condition occurs. #00 01 MATCH. Uses the specified match only. #01 10 IO. Uses the specified I/O condition only. #10 11 AND. The event occurs when the specified match and I/O condition occur simultaneously. #11 STATELD This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state. 14 1 read-write 0 STATEV value is added into STATE (the carry-out is ignored). #0 1 STATEV value is loaded into STATE. #1 STATEV This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value. 15 5 read-write MATCHMEM If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value. 20 1 read-write DIRECTION Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. 21 2 read-write 00 Direction independent. This event is triggered regardless of the count direction. #00 01 Counting up. This event is triggered only during up-counting when BIDIR = 1. #01 10 Counting down. This event is triggered only during down-counting when BIDIR = 1. #10 EV4_STATE SCT event state register 0 0x320 32 read-write 0 0xFFFF STATEMSKn If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT. 0 8 read-write EV4_CTRL SCT event control register 0 0x324 32 read-write 0 0x7FFFFF MATCHSEL Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running. 0 4 read-write HEVENT Select L/H counter. Do not set this bit if UNIFY = 1. 4 1 read-write 0 Selects the L state and the L match register selected by MATCHSEL. #0 1 Selects the H state and the H match register selected by MATCHSEL. #1 OUTSEL Input/output select 5 1 read-write 0 Selects the inputs selected by IOSEL. #0 1 Selects the outputs selected by IOSEL. #1 IOSEL Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event. 6 4 read-write IOCOND Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period . 10 2 read-write 00 LOW #00 01 Rise #01 10 Fall #10 11 HIGH #11 COMBMODE Selects how the specified match and I/O condition are used and combined. 12 2 read-write 00 OR. The event occurs when either the specified match or I/O condition occurs. #00 01 MATCH. Uses the specified match only. #01 10 IO. Uses the specified I/O condition only. #10 11 AND. The event occurs when the specified match and I/O condition occur simultaneously. #11 STATELD This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state. 14 1 read-write 0 STATEV value is added into STATE (the carry-out is ignored). #0 1 STATEV value is loaded into STATE. #1 STATEV This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value. 15 5 read-write MATCHMEM If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value. 20 1 read-write DIRECTION Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. 21 2 read-write 00 Direction independent. This event is triggered regardless of the count direction. #00 01 Counting up. This event is triggered only during up-counting when BIDIR = 1. #01 10 Counting down. This event is triggered only during down-counting when BIDIR = 1. #10 EV5_STATE SCT event state register 0 0x328 32 read-write 0 0xFFFF STATEMSKn If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT. 0 8 read-write EV5_CTRL SCT event control register 0 0x32C 32 read-write 0 0x7FFFFF MATCHSEL Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running. 0 4 read-write HEVENT Select L/H counter. Do not set this bit if UNIFY = 1. 4 1 read-write 0 Selects the L state and the L match register selected by MATCHSEL. #0 1 Selects the H state and the H match register selected by MATCHSEL. #1 OUTSEL Input/output select 5 1 read-write 0 Selects the inputs selected by IOSEL. #0 1 Selects the outputs selected by IOSEL. #1 IOSEL Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event. 6 4 read-write IOCOND Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period . 10 2 read-write 00 LOW #00 01 Rise #01 10 Fall #10 11 HIGH #11 COMBMODE Selects how the specified match and I/O condition are used and combined. 12 2 read-write 00 OR. The event occurs when either the specified match or I/O condition occurs. #00 01 MATCH. Uses the specified match only. #01 10 IO. Uses the specified I/O condition only. #10 11 AND. The event occurs when the specified match and I/O condition occur simultaneously. #11 STATELD This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state. 14 1 read-write 0 STATEV value is added into STATE (the carry-out is ignored). #0 1 STATEV value is loaded into STATE. #1 STATEV This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value. 15 5 read-write MATCHMEM If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value. 20 1 read-write DIRECTION Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. 21 2 read-write 00 Direction independent. This event is triggered regardless of the count direction. #00 01 Counting up. This event is triggered only during up-counting when BIDIR = 1. #01 10 Counting down. This event is triggered only during down-counting when BIDIR = 1. #10 EV6_STATE SCT event state register 0 0x330 32 read-write 0 0xFFFF STATEMSKn If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT. 0 8 read-write EV6_CTRL SCT event control register 0 0x334 32 read-write 0 0x7FFFFF MATCHSEL Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running. 0 4 read-write HEVENT Select L/H counter. Do not set this bit if UNIFY = 1. 4 1 read-write 0 Selects the L state and the L match register selected by MATCHSEL. #0 1 Selects the H state and the H match register selected by MATCHSEL. #1 OUTSEL Input/output select 5 1 read-write 0 Selects the inputs selected by IOSEL. #0 1 Selects the outputs selected by IOSEL. #1 IOSEL Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event. 6 4 read-write IOCOND Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period . 10 2 read-write 00 LOW #00 01 Rise #01 10 Fall #10 11 HIGH #11 COMBMODE Selects how the specified match and I/O condition are used and combined. 12 2 read-write 00 OR. The event occurs when either the specified match or I/O condition occurs. #00 01 MATCH. Uses the specified match only. #01 10 IO. Uses the specified I/O condition only. #10 11 AND. The event occurs when the specified match and I/O condition occur simultaneously. #11 STATELD This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state. 14 1 read-write 0 STATEV value is added into STATE (the carry-out is ignored). #0 1 STATEV value is loaded into STATE. #1 STATEV This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value. 15 5 read-write MATCHMEM If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value. 20 1 read-write DIRECTION Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. 21 2 read-write 00 Direction independent. This event is triggered regardless of the count direction. #00 01 Counting up. This event is triggered only during up-counting when BIDIR = 1. #01 10 Counting down. This event is triggered only during down-counting when BIDIR = 1. #10 EV7_STATE SCT event state register 0 0x338 32 read-write 0 0xFFFF STATEMSKn If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT. 0 8 read-write EV7_CTRL SCT event control register 0 0x33C 32 read-write 0 0x7FFFFF MATCHSEL Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running. 0 4 read-write HEVENT Select L/H counter. Do not set this bit if UNIFY = 1. 4 1 read-write 0 Selects the L state and the L match register selected by MATCHSEL. #0 1 Selects the H state and the H match register selected by MATCHSEL. #1 OUTSEL Input/output select 5 1 read-write 0 Selects the inputs selected by IOSEL. #0 1 Selects the outputs selected by IOSEL. #1 IOSEL Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event. 6 4 read-write IOCOND Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period . 10 2 read-write 00 LOW #00 01 Rise #01 10 Fall #10 11 HIGH #11 COMBMODE Selects how the specified match and I/O condition are used and combined. 12 2 read-write 00 OR. The event occurs when either the specified match or I/O condition occurs. #00 01 MATCH. Uses the specified match only. #01 10 IO. Uses the specified I/O condition only. #10 11 AND. The event occurs when the specified match and I/O condition occur simultaneously. #11 STATELD This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state. 14 1 read-write 0 STATEV value is added into STATE (the carry-out is ignored). #0 1 STATEV value is loaded into STATE. #1 STATEV This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value. 15 5 read-write MATCHMEM If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value. 20 1 read-write DIRECTION Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. 21 2 read-write 00 Direction independent. This event is triggered regardless of the count direction. #00 01 Counting up. This event is triggered only during up-counting when BIDIR = 1. #01 10 Counting down. This event is triggered only during down-counting when BIDIR = 1. #10 OUT0_SET SCT output 0 set register 0x500 32 read-write 0 0xFFFF SET A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register. 0 8 read-write OUT0_CLR SCT output 0 clear register 0x504 32 read-write 0 0xFFFF CLR A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register. 0 8 read-write OUT1_SET SCT output 0 set register 0x508 32 read-write 0 0xFFFF SET A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register. 0 8 read-write OUT1_CLR SCT output 0 clear register 0x50C 32 read-write 0 0xFFFF CLR A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register. 0 8 read-write OUT2_SET SCT output 0 set register 0x510 32 read-write 0 0xFFFF SET A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register. 0 8 read-write OUT2_CLR SCT output 0 clear register 0x514 32 read-write 0 0xFFFF CLR A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register. 0 8 read-write OUT3_SET SCT output 0 set register 0x518 32 read-write 0 0xFFFF SET A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register. 0 8 read-write OUT3_CLR SCT output 0 clear register 0x51C 32 read-write 0 0xFFFF CLR A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register. 0 8 read-write OUT4_SET SCT output 0 set register 0x520 32 read-write 0 0xFFFF SET A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register. 0 8 read-write OUT4_CLR SCT output 0 clear register 0x524 32 read-write 0 0xFFFF CLR A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register. 0 8 read-write OUT5_SET SCT output 0 set register 0x528 32 read-write 0 0xFFFF SET A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register. 0 8 read-write OUT5_CLR SCT output 0 clear register 0x52C 32 read-write 0 0xFFFF CLR A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register. 0 8 read-write OUT6_SET SCT output 0 set register 0x530 32 read-write 0 0xFFFF SET A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register. 0 8 read-write OUT6_CLR SCT output 0 clear register 0x534 32 read-write 0 0xFFFF CLR A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register. 0 8 read-write DMA0 LPC84x DMA controller 0x50008000 0 0x58C registers DMA0 20 CTRL DMA control. 0 32 read-write 0 0x1 ENABLE DMA controller master enable. 0 1 read-write 0 Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when disabled, but does not prevent re-triggering when the DMA controller is re-enabled. #0 1 Enabled. The DMA controller is enabled. #1 INTSTAT Interrupt status. 0x4 32 read-only 0 0x6 ACTIVEINT Summarizes whether any enabled interrupts (other than error interrupts) are pending. 1 1 read-only 0 Not pending. No enabled interrupts are pending. #0 1 Pending. At least one enabled interrupt is pending. #1 ACTIVEERRINT Summarizes whether any error interrupts are pending. 2 1 read-only 0 Not pending. No error interrupts are pending. #0 1 Pending. At least one error interrupt is pending. #1 SRAMBASE SRAM address of the channel configuration table. 0x8 32 read-write 0 0xFFFFFE00 OFFSET Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the table must begin on a 512 byte boundary. 9 23 read-write ENABLESET0 Channel Enable read and Set for all DMA channels. 0x20 32 read-write 0 0x3FFFFFF ENA Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled. 0 25 read-write ENABLECLR0 Channel Enable Clear for all DMA channels. 0x28 32 write-only 0 0 CLR Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 25 write-only ACTIVE0 Channel Active status for all DMA channels. 0x30 32 read-only 0 0xFFFFFFFF ACT Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active. 0 25 read-only BUSY0 Channel Busy status for all DMA channels. 0x38 32 read-only 0 0xFFFFFFFF BSY Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy. 0 25 read-only ERRINT0 Error Interrupt status for all DMA channels. 0x40 32 read-write 0 0xFFFFFFFF ERR Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is not active. 1 = error interrupt is active. 0 25 read-write INTENSET0 Interrupt Enable read and Set for all DMA channels. 0x48 32 read-write 0 0xFFFFFFFF INTEN Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled. 0 25 read-write INTENCLR0 Interrupt Enable Clear for all DMA channels. 0x50 32 write-only 0 0 CLR Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 25 write-only INTA0 Interrupt A status for all DMA channels. 0x58 32 read-write 0 0xFFFFFFFF IA Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active. 0 25 read-write INTB0 Interrupt B status for all DMA channels. 0x60 32 read-write 0 0xFFFFFFFF IB Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active. 0 25 read-write SETVALID0 Set ValidPending control bits for all DMA channels. 0x68 32 write-only 0 0 SV SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n 0 32 write-only SETTRIG0 Set Trigger control bits for all DMA channels. 0x70 32 write-only 0 0 TRIG Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the TRIG bit for DMA channel n. 0 32 write-only ABORT0 Channel Abort control for all DMA channels. 0x78 32 write-only 0 0 ABORTCTRL Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n. 0 32 write-only CFG0 Configuration register for DMA channel . 0x400 32 read-write 0 0x7CF73 PERIPHREQEN Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. 0 1 read-write 0 Disabled. Peripheral DMA requests are disabled. #0 1 Enabled. Peripheral DMA requests are enabled. #1 HWTRIGEN Hardware Triggering Enable for this channel. 1 1 read-write 0 Disabled. Hardware triggering is not used. #0 1 Enabled. Use hardware triggering. #1 TRIGPOL Trigger Polarity. Selects the polarity of a hardware trigger for this channel. 4 1 read-write 0 Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. #0 1 Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. #1 TRIGTYPE Trigger Type. Selects hardware trigger as edge triggered or level triggered. 5 1 read-write 0 Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. #0 1 Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. #1 TRIGBURST Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. 6 1 read-write 0 Single transfer. Hardware trigger causes a single transfer. #0 1 Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. #1 BURSTPOWER Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size. 8 4 read-write SRCBURSTWRAP Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. 14 1 read-write 0 Disabled. Source burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Source burst wrapping is enabled for this DMA channel. #1 DSTBURSTWRAP Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. 15 1 read-write 0 Disabled. Destination burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Destination burst wrapping is enabled for this DMA channel. #1 CHPRIORITY Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority. 16 3 read-write CTLSTAT0 Control and status register for DMA channel . 0x404 32 read-only 0 0x5 VALIDPENDING Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. 0 1 read-only 0 No effect. No effect on DMA operation. #0 1 Valid pending. #1 TRIG Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. 2 1 read-only 0 Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. #0 1 Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. #1 XFERCFG0 Transfer configuration register for DMA channel . 0x408 32 read-write 0 0x3FFF33F CFGVALID Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. 0 1 read-write 0 Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. #0 1 Valid. The current channel descriptor is considered valid. #1 RELOAD Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. 1 1 read-write 0 Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. #0 1 Enabled. Reload the channels' control structure when the current descriptor is exhausted. #1 SWTRIG Software Trigger. 2 1 read-write 0 Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. #0 1 Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. #1 CLRTRIG Clear Trigger. 3 1 read-write 0 Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. #0 1 Cleared. The trigger is cleared when this descriptor is exhausted #1 SETINTA Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 4 1 read-write 0 No effect. #0 1 Set. The INTA flag for this channel will be set when the current descriptor is exhausted. #1 SETINTB Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 5 1 read-write 0 No effect. #0 1 Set. The INTB flag for this channel will be set when the current descriptor is exhausted. #1 WIDTH Transfer width used for this DMA channel. 8 2 read-write 00 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). #00 01 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). #01 10 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). #10 11 Reserved. Reserved setting, do not use. #11 SRCINC Determines whether the source address is incremented for each DMA transfer. 12 2 read-write 00 No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. #00 01 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. #01 10 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. #11 DSTINC Determines whether the destination address is incremented for each DMA transfer. 14 2 read-write 00 No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. #00 01 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. #01 10 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. #11 XFERCOUNT Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed. 16 10 read-write CFG1 Configuration register for DMA channel . 0x410 32 read-write 0 0x7CF73 PERIPHREQEN Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. 0 1 read-write 0 Disabled. Peripheral DMA requests are disabled. #0 1 Enabled. Peripheral DMA requests are enabled. #1 HWTRIGEN Hardware Triggering Enable for this channel. 1 1 read-write 0 Disabled. Hardware triggering is not used. #0 1 Enabled. Use hardware triggering. #1 TRIGPOL Trigger Polarity. Selects the polarity of a hardware trigger for this channel. 4 1 read-write 0 Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. #0 1 Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. #1 TRIGTYPE Trigger Type. Selects hardware trigger as edge triggered or level triggered. 5 1 read-write 0 Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. #0 1 Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. #1 TRIGBURST Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. 6 1 read-write 0 Single transfer. Hardware trigger causes a single transfer. #0 1 Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. #1 BURSTPOWER Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size. 8 4 read-write SRCBURSTWRAP Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. 14 1 read-write 0 Disabled. Source burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Source burst wrapping is enabled for this DMA channel. #1 DSTBURSTWRAP Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. 15 1 read-write 0 Disabled. Destination burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Destination burst wrapping is enabled for this DMA channel. #1 CHPRIORITY Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority. 16 3 read-write CTLSTAT1 Control and status register for DMA channel . 0x414 32 read-only 0 0x5 VALIDPENDING Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. 0 1 read-only 0 No effect. No effect on DMA operation. #0 1 Valid pending. #1 TRIG Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. 2 1 read-only 0 Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. #0 1 Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. #1 XFERCFG1 Transfer configuration register for DMA channel . 0x418 32 read-write 0 0x3FFF33F CFGVALID Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. 0 1 read-write 0 Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. #0 1 Valid. The current channel descriptor is considered valid. #1 RELOAD Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. 1 1 read-write 0 Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. #0 1 Enabled. Reload the channels' control structure when the current descriptor is exhausted. #1 SWTRIG Software Trigger. 2 1 read-write 0 Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. #0 1 Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. #1 CLRTRIG Clear Trigger. 3 1 read-write 0 Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. #0 1 Cleared. The trigger is cleared when this descriptor is exhausted #1 SETINTA Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 4 1 read-write 0 No effect. #0 1 Set. The INTA flag for this channel will be set when the current descriptor is exhausted. #1 SETINTB Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 5 1 read-write 0 No effect. #0 1 Set. The INTB flag for this channel will be set when the current descriptor is exhausted. #1 WIDTH Transfer width used for this DMA channel. 8 2 read-write 00 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). #00 01 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). #01 10 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). #10 11 Reserved. Reserved setting, do not use. #11 SRCINC Determines whether the source address is incremented for each DMA transfer. 12 2 read-write 00 No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. #00 01 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. #01 10 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. #11 DSTINC Determines whether the destination address is incremented for each DMA transfer. 14 2 read-write 00 No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. #00 01 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. #01 10 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. #11 XFERCOUNT Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed. 16 10 read-write CFG2 Configuration register for DMA channel . 0x420 32 read-write 0 0x7CF73 PERIPHREQEN Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. 0 1 read-write 0 Disabled. Peripheral DMA requests are disabled. #0 1 Enabled. Peripheral DMA requests are enabled. #1 HWTRIGEN Hardware Triggering Enable for this channel. 1 1 read-write 0 Disabled. Hardware triggering is not used. #0 1 Enabled. Use hardware triggering. #1 TRIGPOL Trigger Polarity. Selects the polarity of a hardware trigger for this channel. 4 1 read-write 0 Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. #0 1 Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. #1 TRIGTYPE Trigger Type. Selects hardware trigger as edge triggered or level triggered. 5 1 read-write 0 Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. #0 1 Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. #1 TRIGBURST Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. 6 1 read-write 0 Single transfer. Hardware trigger causes a single transfer. #0 1 Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. #1 BURSTPOWER Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size. 8 4 read-write SRCBURSTWRAP Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. 14 1 read-write 0 Disabled. Source burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Source burst wrapping is enabled for this DMA channel. #1 DSTBURSTWRAP Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. 15 1 read-write 0 Disabled. Destination burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Destination burst wrapping is enabled for this DMA channel. #1 CHPRIORITY Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority. 16 3 read-write CTLSTAT2 Control and status register for DMA channel . 0x424 32 read-only 0 0x5 VALIDPENDING Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. 0 1 read-only 0 No effect. No effect on DMA operation. #0 1 Valid pending. #1 TRIG Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. 2 1 read-only 0 Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. #0 1 Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. #1 XFERCFG2 Transfer configuration register for DMA channel . 0x428 32 read-write 0 0x3FFF33F CFGVALID Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. 0 1 read-write 0 Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. #0 1 Valid. The current channel descriptor is considered valid. #1 RELOAD Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. 1 1 read-write 0 Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. #0 1 Enabled. Reload the channels' control structure when the current descriptor is exhausted. #1 SWTRIG Software Trigger. 2 1 read-write 0 Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. #0 1 Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. #1 CLRTRIG Clear Trigger. 3 1 read-write 0 Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. #0 1 Cleared. The trigger is cleared when this descriptor is exhausted #1 SETINTA Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 4 1 read-write 0 No effect. #0 1 Set. The INTA flag for this channel will be set when the current descriptor is exhausted. #1 SETINTB Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 5 1 read-write 0 No effect. #0 1 Set. The INTB flag for this channel will be set when the current descriptor is exhausted. #1 WIDTH Transfer width used for this DMA channel. 8 2 read-write 00 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). #00 01 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). #01 10 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). #10 11 Reserved. Reserved setting, do not use. #11 SRCINC Determines whether the source address is incremented for each DMA transfer. 12 2 read-write 00 No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. #00 01 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. #01 10 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. #11 DSTINC Determines whether the destination address is incremented for each DMA transfer. 14 2 read-write 00 No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. #00 01 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. #01 10 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. #11 XFERCOUNT Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed. 16 10 read-write CFG3 Configuration register for DMA channel . 0x430 32 read-write 0 0x7CF73 PERIPHREQEN Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. 0 1 read-write 0 Disabled. Peripheral DMA requests are disabled. #0 1 Enabled. Peripheral DMA requests are enabled. #1 HWTRIGEN Hardware Triggering Enable for this channel. 1 1 read-write 0 Disabled. Hardware triggering is not used. #0 1 Enabled. Use hardware triggering. #1 TRIGPOL Trigger Polarity. Selects the polarity of a hardware trigger for this channel. 4 1 read-write 0 Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. #0 1 Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. #1 TRIGTYPE Trigger Type. Selects hardware trigger as edge triggered or level triggered. 5 1 read-write 0 Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. #0 1 Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. #1 TRIGBURST Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. 6 1 read-write 0 Single transfer. Hardware trigger causes a single transfer. #0 1 Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. #1 BURSTPOWER Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size. 8 4 read-write SRCBURSTWRAP Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. 14 1 read-write 0 Disabled. Source burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Source burst wrapping is enabled for this DMA channel. #1 DSTBURSTWRAP Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. 15 1 read-write 0 Disabled. Destination burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Destination burst wrapping is enabled for this DMA channel. #1 CHPRIORITY Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority. 16 3 read-write CTLSTAT3 Control and status register for DMA channel . 0x434 32 read-only 0 0x5 VALIDPENDING Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. 0 1 read-only 0 No effect. No effect on DMA operation. #0 1 Valid pending. #1 TRIG Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. 2 1 read-only 0 Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. #0 1 Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. #1 XFERCFG3 Transfer configuration register for DMA channel . 0x438 32 read-write 0 0x3FFF33F CFGVALID Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. 0 1 read-write 0 Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. #0 1 Valid. The current channel descriptor is considered valid. #1 RELOAD Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. 1 1 read-write 0 Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. #0 1 Enabled. Reload the channels' control structure when the current descriptor is exhausted. #1 SWTRIG Software Trigger. 2 1 read-write 0 Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. #0 1 Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. #1 CLRTRIG Clear Trigger. 3 1 read-write 0 Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. #0 1 Cleared. The trigger is cleared when this descriptor is exhausted #1 SETINTA Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 4 1 read-write 0 No effect. #0 1 Set. The INTA flag for this channel will be set when the current descriptor is exhausted. #1 SETINTB Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 5 1 read-write 0 No effect. #0 1 Set. The INTB flag for this channel will be set when the current descriptor is exhausted. #1 WIDTH Transfer width used for this DMA channel. 8 2 read-write 00 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). #00 01 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). #01 10 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). #10 11 Reserved. Reserved setting, do not use. #11 SRCINC Determines whether the source address is incremented for each DMA transfer. 12 2 read-write 00 No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. #00 01 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. #01 10 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. #11 DSTINC Determines whether the destination address is incremented for each DMA transfer. 14 2 read-write 00 No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. #00 01 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. #01 10 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. #11 XFERCOUNT Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed. 16 10 read-write CFG4 Configuration register for DMA channel . 0x440 32 read-write 0 0x7CF73 PERIPHREQEN Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. 0 1 read-write 0 Disabled. Peripheral DMA requests are disabled. #0 1 Enabled. Peripheral DMA requests are enabled. #1 HWTRIGEN Hardware Triggering Enable for this channel. 1 1 read-write 0 Disabled. Hardware triggering is not used. #0 1 Enabled. Use hardware triggering. #1 TRIGPOL Trigger Polarity. Selects the polarity of a hardware trigger for this channel. 4 1 read-write 0 Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. #0 1 Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. #1 TRIGTYPE Trigger Type. Selects hardware trigger as edge triggered or level triggered. 5 1 read-write 0 Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. #0 1 Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. #1 TRIGBURST Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. 6 1 read-write 0 Single transfer. Hardware trigger causes a single transfer. #0 1 Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. #1 BURSTPOWER Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size. 8 4 read-write SRCBURSTWRAP Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. 14 1 read-write 0 Disabled. Source burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Source burst wrapping is enabled for this DMA channel. #1 DSTBURSTWRAP Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. 15 1 read-write 0 Disabled. Destination burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Destination burst wrapping is enabled for this DMA channel. #1 CHPRIORITY Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority. 16 3 read-write CTLSTAT4 Control and status register for DMA channel . 0x444 32 read-only 0 0x5 VALIDPENDING Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. 0 1 read-only 0 No effect. No effect on DMA operation. #0 1 Valid pending. #1 TRIG Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. 2 1 read-only 0 Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. #0 1 Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. #1 XFERCFG4 Transfer configuration register for DMA channel . 0x448 32 read-write 0 0x3FFF33F CFGVALID Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. 0 1 read-write 0 Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. #0 1 Valid. The current channel descriptor is considered valid. #1 RELOAD Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. 1 1 read-write 0 Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. #0 1 Enabled. Reload the channels' control structure when the current descriptor is exhausted. #1 SWTRIG Software Trigger. 2 1 read-write 0 Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. #0 1 Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. #1 CLRTRIG Clear Trigger. 3 1 read-write 0 Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. #0 1 Cleared. The trigger is cleared when this descriptor is exhausted #1 SETINTA Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 4 1 read-write 0 No effect. #0 1 Set. The INTA flag for this channel will be set when the current descriptor is exhausted. #1 SETINTB Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 5 1 read-write 0 No effect. #0 1 Set. The INTB flag for this channel will be set when the current descriptor is exhausted. #1 WIDTH Transfer width used for this DMA channel. 8 2 read-write 00 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). #00 01 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). #01 10 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). #10 11 Reserved. Reserved setting, do not use. #11 SRCINC Determines whether the source address is incremented for each DMA transfer. 12 2 read-write 00 No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. #00 01 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. #01 10 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. #11 DSTINC Determines whether the destination address is incremented for each DMA transfer. 14 2 read-write 00 No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. #00 01 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. #01 10 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. #11 XFERCOUNT Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed. 16 10 read-write CFG5 Configuration register for DMA channel . 0x450 32 read-write 0 0x7CF73 PERIPHREQEN Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. 0 1 read-write 0 Disabled. Peripheral DMA requests are disabled. #0 1 Enabled. Peripheral DMA requests are enabled. #1 HWTRIGEN Hardware Triggering Enable for this channel. 1 1 read-write 0 Disabled. Hardware triggering is not used. #0 1 Enabled. Use hardware triggering. #1 TRIGPOL Trigger Polarity. Selects the polarity of a hardware trigger for this channel. 4 1 read-write 0 Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. #0 1 Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. #1 TRIGTYPE Trigger Type. Selects hardware trigger as edge triggered or level triggered. 5 1 read-write 0 Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. #0 1 Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. #1 TRIGBURST Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. 6 1 read-write 0 Single transfer. Hardware trigger causes a single transfer. #0 1 Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. #1 BURSTPOWER Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size. 8 4 read-write SRCBURSTWRAP Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. 14 1 read-write 0 Disabled. Source burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Source burst wrapping is enabled for this DMA channel. #1 DSTBURSTWRAP Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. 15 1 read-write 0 Disabled. Destination burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Destination burst wrapping is enabled for this DMA channel. #1 CHPRIORITY Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority. 16 3 read-write CTLSTAT5 Control and status register for DMA channel . 0x454 32 read-only 0 0x5 VALIDPENDING Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. 0 1 read-only 0 No effect. No effect on DMA operation. #0 1 Valid pending. #1 TRIG Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. 2 1 read-only 0 Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. #0 1 Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. #1 XFERCFG5 Transfer configuration register for DMA channel . 0x458 32 read-write 0 0x3FFF33F CFGVALID Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. 0 1 read-write 0 Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. #0 1 Valid. The current channel descriptor is considered valid. #1 RELOAD Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. 1 1 read-write 0 Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. #0 1 Enabled. Reload the channels' control structure when the current descriptor is exhausted. #1 SWTRIG Software Trigger. 2 1 read-write 0 Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. #0 1 Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. #1 CLRTRIG Clear Trigger. 3 1 read-write 0 Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. #0 1 Cleared. The trigger is cleared when this descriptor is exhausted #1 SETINTA Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 4 1 read-write 0 No effect. #0 1 Set. The INTA flag for this channel will be set when the current descriptor is exhausted. #1 SETINTB Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 5 1 read-write 0 No effect. #0 1 Set. The INTB flag for this channel will be set when the current descriptor is exhausted. #1 WIDTH Transfer width used for this DMA channel. 8 2 read-write 00 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). #00 01 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). #01 10 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). #10 11 Reserved. Reserved setting, do not use. #11 SRCINC Determines whether the source address is incremented for each DMA transfer. 12 2 read-write 00 No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. #00 01 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. #01 10 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. #11 DSTINC Determines whether the destination address is incremented for each DMA transfer. 14 2 read-write 00 No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. #00 01 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. #01 10 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. #11 XFERCOUNT Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed. 16 10 read-write CFG6 Configuration register for DMA channel . 0x460 32 read-write 0 0x7CF73 PERIPHREQEN Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. 0 1 read-write 0 Disabled. Peripheral DMA requests are disabled. #0 1 Enabled. Peripheral DMA requests are enabled. #1 HWTRIGEN Hardware Triggering Enable for this channel. 1 1 read-write 0 Disabled. Hardware triggering is not used. #0 1 Enabled. Use hardware triggering. #1 TRIGPOL Trigger Polarity. Selects the polarity of a hardware trigger for this channel. 4 1 read-write 0 Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. #0 1 Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. #1 TRIGTYPE Trigger Type. Selects hardware trigger as edge triggered or level triggered. 5 1 read-write 0 Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. #0 1 Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. #1 TRIGBURST Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. 6 1 read-write 0 Single transfer. Hardware trigger causes a single transfer. #0 1 Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. #1 BURSTPOWER Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size. 8 4 read-write SRCBURSTWRAP Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. 14 1 read-write 0 Disabled. Source burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Source burst wrapping is enabled for this DMA channel. #1 DSTBURSTWRAP Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. 15 1 read-write 0 Disabled. Destination burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Destination burst wrapping is enabled for this DMA channel. #1 CHPRIORITY Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority. 16 3 read-write CTLSTAT6 Control and status register for DMA channel . 0x464 32 read-only 0 0x5 VALIDPENDING Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. 0 1 read-only 0 No effect. No effect on DMA operation. #0 1 Valid pending. #1 TRIG Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. 2 1 read-only 0 Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. #0 1 Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. #1 XFERCFG6 Transfer configuration register for DMA channel . 0x468 32 read-write 0 0x3FFF33F CFGVALID Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. 0 1 read-write 0 Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. #0 1 Valid. The current channel descriptor is considered valid. #1 RELOAD Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. 1 1 read-write 0 Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. #0 1 Enabled. Reload the channels' control structure when the current descriptor is exhausted. #1 SWTRIG Software Trigger. 2 1 read-write 0 Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. #0 1 Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. #1 CLRTRIG Clear Trigger. 3 1 read-write 0 Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. #0 1 Cleared. The trigger is cleared when this descriptor is exhausted #1 SETINTA Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 4 1 read-write 0 No effect. #0 1 Set. The INTA flag for this channel will be set when the current descriptor is exhausted. #1 SETINTB Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 5 1 read-write 0 No effect. #0 1 Set. The INTB flag for this channel will be set when the current descriptor is exhausted. #1 WIDTH Transfer width used for this DMA channel. 8 2 read-write 00 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). #00 01 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). #01 10 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). #10 11 Reserved. Reserved setting, do not use. #11 SRCINC Determines whether the source address is incremented for each DMA transfer. 12 2 read-write 00 No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. #00 01 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. #01 10 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. #11 DSTINC Determines whether the destination address is incremented for each DMA transfer. 14 2 read-write 00 No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. #00 01 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. #01 10 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. #11 XFERCOUNT Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed. 16 10 read-write CFG7 Configuration register for DMA channel . 0x470 32 read-write 0 0x7CF73 PERIPHREQEN Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. 0 1 read-write 0 Disabled. Peripheral DMA requests are disabled. #0 1 Enabled. Peripheral DMA requests are enabled. #1 HWTRIGEN Hardware Triggering Enable for this channel. 1 1 read-write 0 Disabled. Hardware triggering is not used. #0 1 Enabled. Use hardware triggering. #1 TRIGPOL Trigger Polarity. Selects the polarity of a hardware trigger for this channel. 4 1 read-write 0 Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. #0 1 Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. #1 TRIGTYPE Trigger Type. Selects hardware trigger as edge triggered or level triggered. 5 1 read-write 0 Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. #0 1 Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. #1 TRIGBURST Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. 6 1 read-write 0 Single transfer. Hardware trigger causes a single transfer. #0 1 Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. #1 BURSTPOWER Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size. 8 4 read-write SRCBURSTWRAP Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. 14 1 read-write 0 Disabled. Source burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Source burst wrapping is enabled for this DMA channel. #1 DSTBURSTWRAP Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. 15 1 read-write 0 Disabled. Destination burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Destination burst wrapping is enabled for this DMA channel. #1 CHPRIORITY Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority. 16 3 read-write CTLSTAT7 Control and status register for DMA channel . 0x474 32 read-only 0 0x5 VALIDPENDING Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. 0 1 read-only 0 No effect. No effect on DMA operation. #0 1 Valid pending. #1 TRIG Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. 2 1 read-only 0 Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. #0 1 Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. #1 XFERCFG7 Transfer configuration register for DMA channel . 0x478 32 read-write 0 0x3FFF33F CFGVALID Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. 0 1 read-write 0 Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. #0 1 Valid. The current channel descriptor is considered valid. #1 RELOAD Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. 1 1 read-write 0 Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. #0 1 Enabled. Reload the channels' control structure when the current descriptor is exhausted. #1 SWTRIG Software Trigger. 2 1 read-write 0 Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. #0 1 Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. #1 CLRTRIG Clear Trigger. 3 1 read-write 0 Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. #0 1 Cleared. The trigger is cleared when this descriptor is exhausted #1 SETINTA Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 4 1 read-write 0 No effect. #0 1 Set. The INTA flag for this channel will be set when the current descriptor is exhausted. #1 SETINTB Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 5 1 read-write 0 No effect. #0 1 Set. The INTB flag for this channel will be set when the current descriptor is exhausted. #1 WIDTH Transfer width used for this DMA channel. 8 2 read-write 00 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). #00 01 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). #01 10 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). #10 11 Reserved. Reserved setting, do not use. #11 SRCINC Determines whether the source address is incremented for each DMA transfer. 12 2 read-write 00 No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. #00 01 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. #01 10 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. #11 DSTINC Determines whether the destination address is incremented for each DMA transfer. 14 2 read-write 00 No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. #00 01 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. #01 10 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. #11 XFERCOUNT Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed. 16 10 read-write CFG8 Configuration register for DMA channel . 0x480 32 read-write 0 0x7CF73 PERIPHREQEN Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. 0 1 read-write 0 Disabled. Peripheral DMA requests are disabled. #0 1 Enabled. Peripheral DMA requests are enabled. #1 HWTRIGEN Hardware Triggering Enable for this channel. 1 1 read-write 0 Disabled. Hardware triggering is not used. #0 1 Enabled. Use hardware triggering. #1 TRIGPOL Trigger Polarity. Selects the polarity of a hardware trigger for this channel. 4 1 read-write 0 Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. #0 1 Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. #1 TRIGTYPE Trigger Type. Selects hardware trigger as edge triggered or level triggered. 5 1 read-write 0 Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. #0 1 Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. #1 TRIGBURST Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. 6 1 read-write 0 Single transfer. Hardware trigger causes a single transfer. #0 1 Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. #1 BURSTPOWER Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size. 8 4 read-write SRCBURSTWRAP Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. 14 1 read-write 0 Disabled. Source burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Source burst wrapping is enabled for this DMA channel. #1 DSTBURSTWRAP Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. 15 1 read-write 0 Disabled. Destination burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Destination burst wrapping is enabled for this DMA channel. #1 CHPRIORITY Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority. 16 3 read-write CTLSTAT8 Control and status register for DMA channel . 0x484 32 read-only 0 0x5 VALIDPENDING Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. 0 1 read-only 0 No effect. No effect on DMA operation. #0 1 Valid pending. #1 TRIG Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. 2 1 read-only 0 Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. #0 1 Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. #1 XFERCFG8 Transfer configuration register for DMA channel . 0x488 32 read-write 0 0x3FFF33F CFGVALID Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. 0 1 read-write 0 Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. #0 1 Valid. The current channel descriptor is considered valid. #1 RELOAD Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. 1 1 read-write 0 Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. #0 1 Enabled. Reload the channels' control structure when the current descriptor is exhausted. #1 SWTRIG Software Trigger. 2 1 read-write 0 Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. #0 1 Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. #1 CLRTRIG Clear Trigger. 3 1 read-write 0 Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. #0 1 Cleared. The trigger is cleared when this descriptor is exhausted #1 SETINTA Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 4 1 read-write 0 No effect. #0 1 Set. The INTA flag for this channel will be set when the current descriptor is exhausted. #1 SETINTB Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 5 1 read-write 0 No effect. #0 1 Set. The INTB flag for this channel will be set when the current descriptor is exhausted. #1 WIDTH Transfer width used for this DMA channel. 8 2 read-write 00 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). #00 01 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). #01 10 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). #10 11 Reserved. Reserved setting, do not use. #11 SRCINC Determines whether the source address is incremented for each DMA transfer. 12 2 read-write 00 No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. #00 01 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. #01 10 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. #11 DSTINC Determines whether the destination address is incremented for each DMA transfer. 14 2 read-write 00 No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. #00 01 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. #01 10 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. #11 XFERCOUNT Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed. 16 10 read-write CFG9 Configuration register for DMA channel . 0x490 32 read-write 0 0x7CF73 PERIPHREQEN Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. 0 1 read-write 0 Disabled. Peripheral DMA requests are disabled. #0 1 Enabled. Peripheral DMA requests are enabled. #1 HWTRIGEN Hardware Triggering Enable for this channel. 1 1 read-write 0 Disabled. Hardware triggering is not used. #0 1 Enabled. Use hardware triggering. #1 TRIGPOL Trigger Polarity. Selects the polarity of a hardware trigger for this channel. 4 1 read-write 0 Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. #0 1 Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. #1 TRIGTYPE Trigger Type. Selects hardware trigger as edge triggered or level triggered. 5 1 read-write 0 Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. #0 1 Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. #1 TRIGBURST Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. 6 1 read-write 0 Single transfer. Hardware trigger causes a single transfer. #0 1 Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. #1 BURSTPOWER Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size. 8 4 read-write SRCBURSTWRAP Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. 14 1 read-write 0 Disabled. Source burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Source burst wrapping is enabled for this DMA channel. #1 DSTBURSTWRAP Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. 15 1 read-write 0 Disabled. Destination burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Destination burst wrapping is enabled for this DMA channel. #1 CHPRIORITY Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority. 16 3 read-write CTLSTAT9 Control and status register for DMA channel . 0x494 32 read-only 0 0x5 VALIDPENDING Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. 0 1 read-only 0 No effect. No effect on DMA operation. #0 1 Valid pending. #1 TRIG Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. 2 1 read-only 0 Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. #0 1 Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. #1 XFERCFG9 Transfer configuration register for DMA channel . 0x498 32 read-write 0 0x3FFF33F CFGVALID Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. 0 1 read-write 0 Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. #0 1 Valid. The current channel descriptor is considered valid. #1 RELOAD Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. 1 1 read-write 0 Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. #0 1 Enabled. Reload the channels' control structure when the current descriptor is exhausted. #1 SWTRIG Software Trigger. 2 1 read-write 0 Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. #0 1 Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. #1 CLRTRIG Clear Trigger. 3 1 read-write 0 Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. #0 1 Cleared. The trigger is cleared when this descriptor is exhausted #1 SETINTA Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 4 1 read-write 0 No effect. #0 1 Set. The INTA flag for this channel will be set when the current descriptor is exhausted. #1 SETINTB Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 5 1 read-write 0 No effect. #0 1 Set. The INTB flag for this channel will be set when the current descriptor is exhausted. #1 WIDTH Transfer width used for this DMA channel. 8 2 read-write 00 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). #00 01 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). #01 10 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). #10 11 Reserved. Reserved setting, do not use. #11 SRCINC Determines whether the source address is incremented for each DMA transfer. 12 2 read-write 00 No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. #00 01 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. #01 10 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. #11 DSTINC Determines whether the destination address is incremented for each DMA transfer. 14 2 read-write 00 No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. #00 01 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. #01 10 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. #11 XFERCOUNT Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed. 16 10 read-write CFG10 Configuration register for DMA channel . 0x4A0 32 read-write 0 0x7CF73 PERIPHREQEN Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. 0 1 read-write 0 Disabled. Peripheral DMA requests are disabled. #0 1 Enabled. Peripheral DMA requests are enabled. #1 HWTRIGEN Hardware Triggering Enable for this channel. 1 1 read-write 0 Disabled. Hardware triggering is not used. #0 1 Enabled. Use hardware triggering. #1 TRIGPOL Trigger Polarity. Selects the polarity of a hardware trigger for this channel. 4 1 read-write 0 Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. #0 1 Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. #1 TRIGTYPE Trigger Type. Selects hardware trigger as edge triggered or level triggered. 5 1 read-write 0 Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. #0 1 Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. #1 TRIGBURST Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. 6 1 read-write 0 Single transfer. Hardware trigger causes a single transfer. #0 1 Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. #1 BURSTPOWER Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size. 8 4 read-write SRCBURSTWRAP Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. 14 1 read-write 0 Disabled. Source burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Source burst wrapping is enabled for this DMA channel. #1 DSTBURSTWRAP Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. 15 1 read-write 0 Disabled. Destination burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Destination burst wrapping is enabled for this DMA channel. #1 CHPRIORITY Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority. 16 3 read-write CTLSTAT10 Control and status register for DMA channel . 0x4A4 32 read-only 0 0x5 VALIDPENDING Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. 0 1 read-only 0 No effect. No effect on DMA operation. #0 1 Valid pending. #1 TRIG Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. 2 1 read-only 0 Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. #0 1 Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. #1 XFERCFG10 Transfer configuration register for DMA channel . 0x4A8 32 read-write 0 0x3FFF33F CFGVALID Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. 0 1 read-write 0 Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. #0 1 Valid. The current channel descriptor is considered valid. #1 RELOAD Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. 1 1 read-write 0 Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. #0 1 Enabled. Reload the channels' control structure when the current descriptor is exhausted. #1 SWTRIG Software Trigger. 2 1 read-write 0 Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. #0 1 Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. #1 CLRTRIG Clear Trigger. 3 1 read-write 0 Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. #0 1 Cleared. The trigger is cleared when this descriptor is exhausted #1 SETINTA Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 4 1 read-write 0 No effect. #0 1 Set. The INTA flag for this channel will be set when the current descriptor is exhausted. #1 SETINTB Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 5 1 read-write 0 No effect. #0 1 Set. The INTB flag for this channel will be set when the current descriptor is exhausted. #1 WIDTH Transfer width used for this DMA channel. 8 2 read-write 00 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). #00 01 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). #01 10 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). #10 11 Reserved. Reserved setting, do not use. #11 SRCINC Determines whether the source address is incremented for each DMA transfer. 12 2 read-write 00 No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. #00 01 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. #01 10 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. #11 DSTINC Determines whether the destination address is incremented for each DMA transfer. 14 2 read-write 00 No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. #00 01 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. #01 10 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. #11 XFERCOUNT Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed. 16 10 read-write CFG11 Configuration register for DMA channel . 0x4B0 32 read-write 0 0x7CF73 PERIPHREQEN Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. 0 1 read-write 0 Disabled. Peripheral DMA requests are disabled. #0 1 Enabled. Peripheral DMA requests are enabled. #1 HWTRIGEN Hardware Triggering Enable for this channel. 1 1 read-write 0 Disabled. Hardware triggering is not used. #0 1 Enabled. Use hardware triggering. #1 TRIGPOL Trigger Polarity. Selects the polarity of a hardware trigger for this channel. 4 1 read-write 0 Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. #0 1 Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. #1 TRIGTYPE Trigger Type. Selects hardware trigger as edge triggered or level triggered. 5 1 read-write 0 Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. #0 1 Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. #1 TRIGBURST Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. 6 1 read-write 0 Single transfer. Hardware trigger causes a single transfer. #0 1 Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. #1 BURSTPOWER Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size. 8 4 read-write SRCBURSTWRAP Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. 14 1 read-write 0 Disabled. Source burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Source burst wrapping is enabled for this DMA channel. #1 DSTBURSTWRAP Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. 15 1 read-write 0 Disabled. Destination burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Destination burst wrapping is enabled for this DMA channel. #1 CHPRIORITY Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority. 16 3 read-write CTLSTAT11 Control and status register for DMA channel . 0x4B4 32 read-only 0 0x5 VALIDPENDING Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. 0 1 read-only 0 No effect. No effect on DMA operation. #0 1 Valid pending. #1 TRIG Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. 2 1 read-only 0 Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. #0 1 Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. #1 XFERCFG11 Transfer configuration register for DMA channel . 0x4B8 32 read-write 0 0x3FFF33F CFGVALID Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. 0 1 read-write 0 Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. #0 1 Valid. The current channel descriptor is considered valid. #1 RELOAD Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. 1 1 read-write 0 Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. #0 1 Enabled. Reload the channels' control structure when the current descriptor is exhausted. #1 SWTRIG Software Trigger. 2 1 read-write 0 Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. #0 1 Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. #1 CLRTRIG Clear Trigger. 3 1 read-write 0 Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. #0 1 Cleared. The trigger is cleared when this descriptor is exhausted #1 SETINTA Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 4 1 read-write 0 No effect. #0 1 Set. The INTA flag for this channel will be set when the current descriptor is exhausted. #1 SETINTB Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 5 1 read-write 0 No effect. #0 1 Set. The INTB flag for this channel will be set when the current descriptor is exhausted. #1 WIDTH Transfer width used for this DMA channel. 8 2 read-write 00 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). #00 01 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). #01 10 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). #10 11 Reserved. Reserved setting, do not use. #11 SRCINC Determines whether the source address is incremented for each DMA transfer. 12 2 read-write 00 No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. #00 01 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. #01 10 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. #11 DSTINC Determines whether the destination address is incremented for each DMA transfer. 14 2 read-write 00 No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. #00 01 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. #01 10 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. #11 XFERCOUNT Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed. 16 10 read-write CFG12 Configuration register for DMA channel . 0x4C0 32 read-write 0 0x7CF73 PERIPHREQEN Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. 0 1 read-write 0 Disabled. Peripheral DMA requests are disabled. #0 1 Enabled. Peripheral DMA requests are enabled. #1 HWTRIGEN Hardware Triggering Enable for this channel. 1 1 read-write 0 Disabled. Hardware triggering is not used. #0 1 Enabled. Use hardware triggering. #1 TRIGPOL Trigger Polarity. Selects the polarity of a hardware trigger for this channel. 4 1 read-write 0 Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. #0 1 Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. #1 TRIGTYPE Trigger Type. Selects hardware trigger as edge triggered or level triggered. 5 1 read-write 0 Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. #0 1 Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. #1 TRIGBURST Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. 6 1 read-write 0 Single transfer. Hardware trigger causes a single transfer. #0 1 Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. #1 BURSTPOWER Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size. 8 4 read-write SRCBURSTWRAP Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. 14 1 read-write 0 Disabled. Source burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Source burst wrapping is enabled for this DMA channel. #1 DSTBURSTWRAP Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. 15 1 read-write 0 Disabled. Destination burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Destination burst wrapping is enabled for this DMA channel. #1 CHPRIORITY Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority. 16 3 read-write CTLSTAT12 Control and status register for DMA channel . 0x4C4 32 read-only 0 0x5 VALIDPENDING Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. 0 1 read-only 0 No effect. No effect on DMA operation. #0 1 Valid pending. #1 TRIG Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. 2 1 read-only 0 Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. #0 1 Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. #1 XFERCFG12 Transfer configuration register for DMA channel . 0x4C8 32 read-write 0 0x3FFF33F CFGVALID Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. 0 1 read-write 0 Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. #0 1 Valid. The current channel descriptor is considered valid. #1 RELOAD Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. 1 1 read-write 0 Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. #0 1 Enabled. Reload the channels' control structure when the current descriptor is exhausted. #1 SWTRIG Software Trigger. 2 1 read-write 0 Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. #0 1 Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. #1 CLRTRIG Clear Trigger. 3 1 read-write 0 Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. #0 1 Cleared. The trigger is cleared when this descriptor is exhausted #1 SETINTA Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 4 1 read-write 0 No effect. #0 1 Set. The INTA flag for this channel will be set when the current descriptor is exhausted. #1 SETINTB Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 5 1 read-write 0 No effect. #0 1 Set. The INTB flag for this channel will be set when the current descriptor is exhausted. #1 WIDTH Transfer width used for this DMA channel. 8 2 read-write 00 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). #00 01 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). #01 10 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). #10 11 Reserved. Reserved setting, do not use. #11 SRCINC Determines whether the source address is incremented for each DMA transfer. 12 2 read-write 00 No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. #00 01 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. #01 10 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. #11 DSTINC Determines whether the destination address is incremented for each DMA transfer. 14 2 read-write 00 No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. #00 01 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. #01 10 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. #11 XFERCOUNT Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed. 16 10 read-write CFG13 Configuration register for DMA channel . 0x4D0 32 read-write 0 0x7CF73 PERIPHREQEN Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. 0 1 read-write 0 Disabled. Peripheral DMA requests are disabled. #0 1 Enabled. Peripheral DMA requests are enabled. #1 HWTRIGEN Hardware Triggering Enable for this channel. 1 1 read-write 0 Disabled. Hardware triggering is not used. #0 1 Enabled. Use hardware triggering. #1 TRIGPOL Trigger Polarity. Selects the polarity of a hardware trigger for this channel. 4 1 read-write 0 Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. #0 1 Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. #1 TRIGTYPE Trigger Type. Selects hardware trigger as edge triggered or level triggered. 5 1 read-write 0 Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. #0 1 Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. #1 TRIGBURST Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. 6 1 read-write 0 Single transfer. Hardware trigger causes a single transfer. #0 1 Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. #1 BURSTPOWER Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size. 8 4 read-write SRCBURSTWRAP Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. 14 1 read-write 0 Disabled. Source burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Source burst wrapping is enabled for this DMA channel. #1 DSTBURSTWRAP Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. 15 1 read-write 0 Disabled. Destination burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Destination burst wrapping is enabled for this DMA channel. #1 CHPRIORITY Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority. 16 3 read-write CTLSTAT13 Control and status register for DMA channel . 0x4D4 32 read-only 0 0x5 VALIDPENDING Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. 0 1 read-only 0 No effect. No effect on DMA operation. #0 1 Valid pending. #1 TRIG Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. 2 1 read-only 0 Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. #0 1 Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. #1 XFERCFG13 Transfer configuration register for DMA channel . 0x4D8 32 read-write 0 0x3FFF33F CFGVALID Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. 0 1 read-write 0 Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. #0 1 Valid. The current channel descriptor is considered valid. #1 RELOAD Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. 1 1 read-write 0 Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. #0 1 Enabled. Reload the channels' control structure when the current descriptor is exhausted. #1 SWTRIG Software Trigger. 2 1 read-write 0 Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. #0 1 Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. #1 CLRTRIG Clear Trigger. 3 1 read-write 0 Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. #0 1 Cleared. The trigger is cleared when this descriptor is exhausted #1 SETINTA Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 4 1 read-write 0 No effect. #0 1 Set. The INTA flag for this channel will be set when the current descriptor is exhausted. #1 SETINTB Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 5 1 read-write 0 No effect. #0 1 Set. The INTB flag for this channel will be set when the current descriptor is exhausted. #1 WIDTH Transfer width used for this DMA channel. 8 2 read-write 00 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). #00 01 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). #01 10 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). #10 11 Reserved. Reserved setting, do not use. #11 SRCINC Determines whether the source address is incremented for each DMA transfer. 12 2 read-write 00 No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. #00 01 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. #01 10 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. #11 DSTINC Determines whether the destination address is incremented for each DMA transfer. 14 2 read-write 00 No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. #00 01 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. #01 10 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. #11 XFERCOUNT Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed. 16 10 read-write CFG14 Configuration register for DMA channel . 0x4E0 32 read-write 0 0x7CF73 PERIPHREQEN Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. 0 1 read-write 0 Disabled. Peripheral DMA requests are disabled. #0 1 Enabled. Peripheral DMA requests are enabled. #1 HWTRIGEN Hardware Triggering Enable for this channel. 1 1 read-write 0 Disabled. Hardware triggering is not used. #0 1 Enabled. Use hardware triggering. #1 TRIGPOL Trigger Polarity. Selects the polarity of a hardware trigger for this channel. 4 1 read-write 0 Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. #0 1 Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. #1 TRIGTYPE Trigger Type. Selects hardware trigger as edge triggered or level triggered. 5 1 read-write 0 Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. #0 1 Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. #1 TRIGBURST Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. 6 1 read-write 0 Single transfer. Hardware trigger causes a single transfer. #0 1 Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. #1 BURSTPOWER Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size. 8 4 read-write SRCBURSTWRAP Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. 14 1 read-write 0 Disabled. Source burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Source burst wrapping is enabled for this DMA channel. #1 DSTBURSTWRAP Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. 15 1 read-write 0 Disabled. Destination burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Destination burst wrapping is enabled for this DMA channel. #1 CHPRIORITY Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority. 16 3 read-write CTLSTAT14 Control and status register for DMA channel . 0x4E4 32 read-only 0 0x5 VALIDPENDING Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. 0 1 read-only 0 No effect. No effect on DMA operation. #0 1 Valid pending. #1 TRIG Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. 2 1 read-only 0 Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. #0 1 Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. #1 XFERCFG14 Transfer configuration register for DMA channel . 0x4E8 32 read-write 0 0x3FFF33F CFGVALID Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. 0 1 read-write 0 Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. #0 1 Valid. The current channel descriptor is considered valid. #1 RELOAD Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. 1 1 read-write 0 Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. #0 1 Enabled. Reload the channels' control structure when the current descriptor is exhausted. #1 SWTRIG Software Trigger. 2 1 read-write 0 Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. #0 1 Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. #1 CLRTRIG Clear Trigger. 3 1 read-write 0 Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. #0 1 Cleared. The trigger is cleared when this descriptor is exhausted #1 SETINTA Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 4 1 read-write 0 No effect. #0 1 Set. The INTA flag for this channel will be set when the current descriptor is exhausted. #1 SETINTB Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 5 1 read-write 0 No effect. #0 1 Set. The INTB flag for this channel will be set when the current descriptor is exhausted. #1 WIDTH Transfer width used for this DMA channel. 8 2 read-write 00 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). #00 01 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). #01 10 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). #10 11 Reserved. Reserved setting, do not use. #11 SRCINC Determines whether the source address is incremented for each DMA transfer. 12 2 read-write 00 No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. #00 01 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. #01 10 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. #11 DSTINC Determines whether the destination address is incremented for each DMA transfer. 14 2 read-write 00 No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. #00 01 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. #01 10 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. #11 XFERCOUNT Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed. 16 10 read-write CFG15 Configuration register for DMA channel . 0x4F0 32 read-write 0 0x7CF73 PERIPHREQEN Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. 0 1 read-write 0 Disabled. Peripheral DMA requests are disabled. #0 1 Enabled. Peripheral DMA requests are enabled. #1 HWTRIGEN Hardware Triggering Enable for this channel. 1 1 read-write 0 Disabled. Hardware triggering is not used. #0 1 Enabled. Use hardware triggering. #1 TRIGPOL Trigger Polarity. Selects the polarity of a hardware trigger for this channel. 4 1 read-write 0 Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. #0 1 Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. #1 TRIGTYPE Trigger Type. Selects hardware trigger as edge triggered or level triggered. 5 1 read-write 0 Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. #0 1 Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. #1 TRIGBURST Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. 6 1 read-write 0 Single transfer. Hardware trigger causes a single transfer. #0 1 Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. #1 BURSTPOWER Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size. 8 4 read-write SRCBURSTWRAP Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. 14 1 read-write 0 Disabled. Source burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Source burst wrapping is enabled for this DMA channel. #1 DSTBURSTWRAP Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. 15 1 read-write 0 Disabled. Destination burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Destination burst wrapping is enabled for this DMA channel. #1 CHPRIORITY Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority. 16 3 read-write CTLSTAT15 Control and status register for DMA channel . 0x4F4 32 read-only 0 0x5 VALIDPENDING Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. 0 1 read-only 0 No effect. No effect on DMA operation. #0 1 Valid pending. #1 TRIG Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. 2 1 read-only 0 Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. #0 1 Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. #1 XFERCFG15 Transfer configuration register for DMA channel . 0x4F8 32 read-write 0 0x3FFF33F CFGVALID Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. 0 1 read-write 0 Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. #0 1 Valid. The current channel descriptor is considered valid. #1 RELOAD Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. 1 1 read-write 0 Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. #0 1 Enabled. Reload the channels' control structure when the current descriptor is exhausted. #1 SWTRIG Software Trigger. 2 1 read-write 0 Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. #0 1 Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. #1 CLRTRIG Clear Trigger. 3 1 read-write 0 Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. #0 1 Cleared. The trigger is cleared when this descriptor is exhausted #1 SETINTA Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 4 1 read-write 0 No effect. #0 1 Set. The INTA flag for this channel will be set when the current descriptor is exhausted. #1 SETINTB Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 5 1 read-write 0 No effect. #0 1 Set. The INTB flag for this channel will be set when the current descriptor is exhausted. #1 WIDTH Transfer width used for this DMA channel. 8 2 read-write 00 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). #00 01 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). #01 10 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). #10 11 Reserved. Reserved setting, do not use. #11 SRCINC Determines whether the source address is incremented for each DMA transfer. 12 2 read-write 00 No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. #00 01 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. #01 10 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. #11 DSTINC Determines whether the destination address is incremented for each DMA transfer. 14 2 read-write 00 No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. #00 01 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. #01 10 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. #11 XFERCOUNT Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed. 16 10 read-write CFG16 Configuration register for DMA channel . 0x500 32 read-write 0 0x7CF73 PERIPHREQEN Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. 0 1 read-write 0 Disabled. Peripheral DMA requests are disabled. #0 1 Enabled. Peripheral DMA requests are enabled. #1 HWTRIGEN Hardware Triggering Enable for this channel. 1 1 read-write 0 Disabled. Hardware triggering is not used. #0 1 Enabled. Use hardware triggering. #1 TRIGPOL Trigger Polarity. Selects the polarity of a hardware trigger for this channel. 4 1 read-write 0 Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. #0 1 Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. #1 TRIGTYPE Trigger Type. Selects hardware trigger as edge triggered or level triggered. 5 1 read-write 0 Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. #0 1 Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. #1 TRIGBURST Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. 6 1 read-write 0 Single transfer. Hardware trigger causes a single transfer. #0 1 Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. #1 BURSTPOWER Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size. 8 4 read-write SRCBURSTWRAP Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. 14 1 read-write 0 Disabled. Source burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Source burst wrapping is enabled for this DMA channel. #1 DSTBURSTWRAP Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. 15 1 read-write 0 Disabled. Destination burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Destination burst wrapping is enabled for this DMA channel. #1 CHPRIORITY Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority. 16 3 read-write CTLSTAT16 Control and status register for DMA channel . 0x504 32 read-only 0 0x5 VALIDPENDING Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. 0 1 read-only 0 No effect. No effect on DMA operation. #0 1 Valid pending. #1 TRIG Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. 2 1 read-only 0 Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. #0 1 Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. #1 XFERCFG16 Transfer configuration register for DMA channel . 0x508 32 read-write 0 0x3FFF33F CFGVALID Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. 0 1 read-write 0 Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. #0 1 Valid. The current channel descriptor is considered valid. #1 RELOAD Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. 1 1 read-write 0 Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. #0 1 Enabled. Reload the channels' control structure when the current descriptor is exhausted. #1 SWTRIG Software Trigger. 2 1 read-write 0 Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. #0 1 Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. #1 CLRTRIG Clear Trigger. 3 1 read-write 0 Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. #0 1 Cleared. The trigger is cleared when this descriptor is exhausted #1 SETINTA Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 4 1 read-write 0 No effect. #0 1 Set. The INTA flag for this channel will be set when the current descriptor is exhausted. #1 SETINTB Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 5 1 read-write 0 No effect. #0 1 Set. The INTB flag for this channel will be set when the current descriptor is exhausted. #1 WIDTH Transfer width used for this DMA channel. 8 2 read-write 00 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). #00 01 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). #01 10 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). #10 11 Reserved. Reserved setting, do not use. #11 SRCINC Determines whether the source address is incremented for each DMA transfer. 12 2 read-write 00 No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. #00 01 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. #01 10 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. #11 DSTINC Determines whether the destination address is incremented for each DMA transfer. 14 2 read-write 00 No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. #00 01 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. #01 10 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. #11 XFERCOUNT Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed. 16 10 read-write CFG17 Configuration register for DMA channel . 0x510 32 read-write 0 0x7CF73 PERIPHREQEN Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. 0 1 read-write 0 Disabled. Peripheral DMA requests are disabled. #0 1 Enabled. Peripheral DMA requests are enabled. #1 HWTRIGEN Hardware Triggering Enable for this channel. 1 1 read-write 0 Disabled. Hardware triggering is not used. #0 1 Enabled. Use hardware triggering. #1 TRIGPOL Trigger Polarity. Selects the polarity of a hardware trigger for this channel. 4 1 read-write 0 Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. #0 1 Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. #1 TRIGTYPE Trigger Type. Selects hardware trigger as edge triggered or level triggered. 5 1 read-write 0 Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. #0 1 Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. #1 TRIGBURST Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. 6 1 read-write 0 Single transfer. Hardware trigger causes a single transfer. #0 1 Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. #1 BURSTPOWER Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size. 8 4 read-write SRCBURSTWRAP Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. 14 1 read-write 0 Disabled. Source burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Source burst wrapping is enabled for this DMA channel. #1 DSTBURSTWRAP Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. 15 1 read-write 0 Disabled. Destination burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Destination burst wrapping is enabled for this DMA channel. #1 CHPRIORITY Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority. 16 3 read-write CTLSTAT17 Control and status register for DMA channel . 0x514 32 read-only 0 0x5 VALIDPENDING Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. 0 1 read-only 0 No effect. No effect on DMA operation. #0 1 Valid pending. #1 TRIG Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. 2 1 read-only 0 Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. #0 1 Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. #1 XFERCFG17 Transfer configuration register for DMA channel . 0x518 32 read-write 0 0x3FFF33F CFGVALID Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. 0 1 read-write 0 Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. #0 1 Valid. The current channel descriptor is considered valid. #1 RELOAD Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. 1 1 read-write 0 Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. #0 1 Enabled. Reload the channels' control structure when the current descriptor is exhausted. #1 SWTRIG Software Trigger. 2 1 read-write 0 Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. #0 1 Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. #1 CLRTRIG Clear Trigger. 3 1 read-write 0 Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. #0 1 Cleared. The trigger is cleared when this descriptor is exhausted #1 SETINTA Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 4 1 read-write 0 No effect. #0 1 Set. The INTA flag for this channel will be set when the current descriptor is exhausted. #1 SETINTB Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 5 1 read-write 0 No effect. #0 1 Set. The INTB flag for this channel will be set when the current descriptor is exhausted. #1 WIDTH Transfer width used for this DMA channel. 8 2 read-write 00 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). #00 01 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). #01 10 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). #10 11 Reserved. Reserved setting, do not use. #11 SRCINC Determines whether the source address is incremented for each DMA transfer. 12 2 read-write 00 No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. #00 01 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. #01 10 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. #11 DSTINC Determines whether the destination address is incremented for each DMA transfer. 14 2 read-write 00 No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. #00 01 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. #01 10 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. #11 XFERCOUNT Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed. 16 10 read-write CFG18 Configuration register for DMA channel . 0x520 32 read-write 0 0x7CF73 PERIPHREQEN Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. 0 1 read-write 0 Disabled. Peripheral DMA requests are disabled. #0 1 Enabled. Peripheral DMA requests are enabled. #1 HWTRIGEN Hardware Triggering Enable for this channel. 1 1 read-write 0 Disabled. Hardware triggering is not used. #0 1 Enabled. Use hardware triggering. #1 TRIGPOL Trigger Polarity. Selects the polarity of a hardware trigger for this channel. 4 1 read-write 0 Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. #0 1 Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. #1 TRIGTYPE Trigger Type. Selects hardware trigger as edge triggered or level triggered. 5 1 read-write 0 Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. #0 1 Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. #1 TRIGBURST Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. 6 1 read-write 0 Single transfer. Hardware trigger causes a single transfer. #0 1 Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. #1 BURSTPOWER Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size. 8 4 read-write SRCBURSTWRAP Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. 14 1 read-write 0 Disabled. Source burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Source burst wrapping is enabled for this DMA channel. #1 DSTBURSTWRAP Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. 15 1 read-write 0 Disabled. Destination burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Destination burst wrapping is enabled for this DMA channel. #1 CHPRIORITY Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority. 16 3 read-write CTLSTAT18 Control and status register for DMA channel . 0x524 32 read-only 0 0x5 VALIDPENDING Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. 0 1 read-only 0 No effect. No effect on DMA operation. #0 1 Valid pending. #1 TRIG Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. 2 1 read-only 0 Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. #0 1 Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. #1 XFERCFG18 Transfer configuration register for DMA channel . 0x528 32 read-write 0 0x3FFF33F CFGVALID Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. 0 1 read-write 0 Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. #0 1 Valid. The current channel descriptor is considered valid. #1 RELOAD Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. 1 1 read-write 0 Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. #0 1 Enabled. Reload the channels' control structure when the current descriptor is exhausted. #1 SWTRIG Software Trigger. 2 1 read-write 0 Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. #0 1 Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. #1 CLRTRIG Clear Trigger. 3 1 read-write 0 Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. #0 1 Cleared. The trigger is cleared when this descriptor is exhausted #1 SETINTA Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 4 1 read-write 0 No effect. #0 1 Set. The INTA flag for this channel will be set when the current descriptor is exhausted. #1 SETINTB Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 5 1 read-write 0 No effect. #0 1 Set. The INTB flag for this channel will be set when the current descriptor is exhausted. #1 WIDTH Transfer width used for this DMA channel. 8 2 read-write 00 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). #00 01 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). #01 10 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). #10 11 Reserved. Reserved setting, do not use. #11 SRCINC Determines whether the source address is incremented for each DMA transfer. 12 2 read-write 00 No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. #00 01 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. #01 10 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. #11 DSTINC Determines whether the destination address is incremented for each DMA transfer. 14 2 read-write 00 No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. #00 01 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. #01 10 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. #11 XFERCOUNT Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed. 16 10 read-write CFG19 Configuration register for DMA channel . 0x530 32 read-write 0 0x7CF73 PERIPHREQEN Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. 0 1 read-write 0 Disabled. Peripheral DMA requests are disabled. #0 1 Enabled. Peripheral DMA requests are enabled. #1 HWTRIGEN Hardware Triggering Enable for this channel. 1 1 read-write 0 Disabled. Hardware triggering is not used. #0 1 Enabled. Use hardware triggering. #1 TRIGPOL Trigger Polarity. Selects the polarity of a hardware trigger for this channel. 4 1 read-write 0 Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. #0 1 Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. #1 TRIGTYPE Trigger Type. Selects hardware trigger as edge triggered or level triggered. 5 1 read-write 0 Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. #0 1 Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. #1 TRIGBURST Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. 6 1 read-write 0 Single transfer. Hardware trigger causes a single transfer. #0 1 Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. #1 BURSTPOWER Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size. 8 4 read-write SRCBURSTWRAP Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. 14 1 read-write 0 Disabled. Source burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Source burst wrapping is enabled for this DMA channel. #1 DSTBURSTWRAP Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. 15 1 read-write 0 Disabled. Destination burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Destination burst wrapping is enabled for this DMA channel. #1 CHPRIORITY Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority. 16 3 read-write CTLSTAT19 Control and status register for DMA channel . 0x534 32 read-only 0 0x5 VALIDPENDING Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. 0 1 read-only 0 No effect. No effect on DMA operation. #0 1 Valid pending. #1 TRIG Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. 2 1 read-only 0 Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. #0 1 Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. #1 XFERCFG19 Transfer configuration register for DMA channel . 0x538 32 read-write 0 0x3FFF33F CFGVALID Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. 0 1 read-write 0 Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. #0 1 Valid. The current channel descriptor is considered valid. #1 RELOAD Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. 1 1 read-write 0 Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. #0 1 Enabled. Reload the channels' control structure when the current descriptor is exhausted. #1 SWTRIG Software Trigger. 2 1 read-write 0 Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. #0 1 Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. #1 CLRTRIG Clear Trigger. 3 1 read-write 0 Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. #0 1 Cleared. The trigger is cleared when this descriptor is exhausted #1 SETINTA Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 4 1 read-write 0 No effect. #0 1 Set. The INTA flag for this channel will be set when the current descriptor is exhausted. #1 SETINTB Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 5 1 read-write 0 No effect. #0 1 Set. The INTB flag for this channel will be set when the current descriptor is exhausted. #1 WIDTH Transfer width used for this DMA channel. 8 2 read-write 00 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). #00 01 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). #01 10 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). #10 11 Reserved. Reserved setting, do not use. #11 SRCINC Determines whether the source address is incremented for each DMA transfer. 12 2 read-write 00 No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. #00 01 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. #01 10 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. #11 DSTINC Determines whether the destination address is incremented for each DMA transfer. 14 2 read-write 00 No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. #00 01 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. #01 10 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. #11 XFERCOUNT Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed. 16 10 read-write CFG20 Configuration register for DMA channel . 0x540 32 read-write 0 0x7CF73 PERIPHREQEN Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. 0 1 read-write 0 Disabled. Peripheral DMA requests are disabled. #0 1 Enabled. Peripheral DMA requests are enabled. #1 HWTRIGEN Hardware Triggering Enable for this channel. 1 1 read-write 0 Disabled. Hardware triggering is not used. #0 1 Enabled. Use hardware triggering. #1 TRIGPOL Trigger Polarity. Selects the polarity of a hardware trigger for this channel. 4 1 read-write 0 Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. #0 1 Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. #1 TRIGTYPE Trigger Type. Selects hardware trigger as edge triggered or level triggered. 5 1 read-write 0 Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. #0 1 Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. #1 TRIGBURST Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. 6 1 read-write 0 Single transfer. Hardware trigger causes a single transfer. #0 1 Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. #1 BURSTPOWER Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size. 8 4 read-write SRCBURSTWRAP Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. 14 1 read-write 0 Disabled. Source burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Source burst wrapping is enabled for this DMA channel. #1 DSTBURSTWRAP Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. 15 1 read-write 0 Disabled. Destination burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Destination burst wrapping is enabled for this DMA channel. #1 CHPRIORITY Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority. 16 3 read-write CTLSTAT20 Control and status register for DMA channel . 0x544 32 read-only 0 0x5 VALIDPENDING Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. 0 1 read-only 0 No effect. No effect on DMA operation. #0 1 Valid pending. #1 TRIG Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. 2 1 read-only 0 Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. #0 1 Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. #1 XFERCFG20 Transfer configuration register for DMA channel . 0x548 32 read-write 0 0x3FFF33F CFGVALID Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. 0 1 read-write 0 Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. #0 1 Valid. The current channel descriptor is considered valid. #1 RELOAD Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. 1 1 read-write 0 Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. #0 1 Enabled. Reload the channels' control structure when the current descriptor is exhausted. #1 SWTRIG Software Trigger. 2 1 read-write 0 Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. #0 1 Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. #1 CLRTRIG Clear Trigger. 3 1 read-write 0 Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. #0 1 Cleared. The trigger is cleared when this descriptor is exhausted #1 SETINTA Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 4 1 read-write 0 No effect. #0 1 Set. The INTA flag for this channel will be set when the current descriptor is exhausted. #1 SETINTB Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 5 1 read-write 0 No effect. #0 1 Set. The INTB flag for this channel will be set when the current descriptor is exhausted. #1 WIDTH Transfer width used for this DMA channel. 8 2 read-write 00 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). #00 01 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). #01 10 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). #10 11 Reserved. Reserved setting, do not use. #11 SRCINC Determines whether the source address is incremented for each DMA transfer. 12 2 read-write 00 No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. #00 01 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. #01 10 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. #11 DSTINC Determines whether the destination address is incremented for each DMA transfer. 14 2 read-write 00 No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. #00 01 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. #01 10 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. #11 XFERCOUNT Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed. 16 10 read-write CFG21 Configuration register for DMA channel . 0x550 32 read-write 0 0x7CF73 PERIPHREQEN Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. 0 1 read-write 0 Disabled. Peripheral DMA requests are disabled. #0 1 Enabled. Peripheral DMA requests are enabled. #1 HWTRIGEN Hardware Triggering Enable for this channel. 1 1 read-write 0 Disabled. Hardware triggering is not used. #0 1 Enabled. Use hardware triggering. #1 TRIGPOL Trigger Polarity. Selects the polarity of a hardware trigger for this channel. 4 1 read-write 0 Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. #0 1 Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. #1 TRIGTYPE Trigger Type. Selects hardware trigger as edge triggered or level triggered. 5 1 read-write 0 Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. #0 1 Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. #1 TRIGBURST Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. 6 1 read-write 0 Single transfer. Hardware trigger causes a single transfer. #0 1 Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. #1 BURSTPOWER Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size. 8 4 read-write SRCBURSTWRAP Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. 14 1 read-write 0 Disabled. Source burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Source burst wrapping is enabled for this DMA channel. #1 DSTBURSTWRAP Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. 15 1 read-write 0 Disabled. Destination burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Destination burst wrapping is enabled for this DMA channel. #1 CHPRIORITY Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority. 16 3 read-write CTLSTAT21 Control and status register for DMA channel . 0x554 32 read-only 0 0x5 VALIDPENDING Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. 0 1 read-only 0 No effect. No effect on DMA operation. #0 1 Valid pending. #1 TRIG Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. 2 1 read-only 0 Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. #0 1 Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. #1 XFERCFG21 Transfer configuration register for DMA channel . 0x558 32 read-write 0 0x3FFF33F CFGVALID Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. 0 1 read-write 0 Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. #0 1 Valid. The current channel descriptor is considered valid. #1 RELOAD Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. 1 1 read-write 0 Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. #0 1 Enabled. Reload the channels' control structure when the current descriptor is exhausted. #1 SWTRIG Software Trigger. 2 1 read-write 0 Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. #0 1 Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. #1 CLRTRIG Clear Trigger. 3 1 read-write 0 Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. #0 1 Cleared. The trigger is cleared when this descriptor is exhausted #1 SETINTA Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 4 1 read-write 0 No effect. #0 1 Set. The INTA flag for this channel will be set when the current descriptor is exhausted. #1 SETINTB Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 5 1 read-write 0 No effect. #0 1 Set. The INTB flag for this channel will be set when the current descriptor is exhausted. #1 WIDTH Transfer width used for this DMA channel. 8 2 read-write 00 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). #00 01 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). #01 10 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). #10 11 Reserved. Reserved setting, do not use. #11 SRCINC Determines whether the source address is incremented for each DMA transfer. 12 2 read-write 00 No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. #00 01 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. #01 10 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. #11 DSTINC Determines whether the destination address is incremented for each DMA transfer. 14 2 read-write 00 No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. #00 01 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. #01 10 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. #11 XFERCOUNT Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed. 16 10 read-write CFG22 Configuration register for DMA channel . 0x560 32 read-write 0 0x7CF73 PERIPHREQEN Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. 0 1 read-write 0 Disabled. Peripheral DMA requests are disabled. #0 1 Enabled. Peripheral DMA requests are enabled. #1 HWTRIGEN Hardware Triggering Enable for this channel. 1 1 read-write 0 Disabled. Hardware triggering is not used. #0 1 Enabled. Use hardware triggering. #1 TRIGPOL Trigger Polarity. Selects the polarity of a hardware trigger for this channel. 4 1 read-write 0 Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. #0 1 Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. #1 TRIGTYPE Trigger Type. Selects hardware trigger as edge triggered or level triggered. 5 1 read-write 0 Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. #0 1 Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. #1 TRIGBURST Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. 6 1 read-write 0 Single transfer. Hardware trigger causes a single transfer. #0 1 Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. #1 BURSTPOWER Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size. 8 4 read-write SRCBURSTWRAP Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. 14 1 read-write 0 Disabled. Source burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Source burst wrapping is enabled for this DMA channel. #1 DSTBURSTWRAP Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. 15 1 read-write 0 Disabled. Destination burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Destination burst wrapping is enabled for this DMA channel. #1 CHPRIORITY Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority. 16 3 read-write CTLSTAT22 Control and status register for DMA channel . 0x564 32 read-only 0 0x5 VALIDPENDING Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. 0 1 read-only 0 No effect. No effect on DMA operation. #0 1 Valid pending. #1 TRIG Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. 2 1 read-only 0 Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. #0 1 Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. #1 XFERCFG22 Transfer configuration register for DMA channel . 0x568 32 read-write 0 0x3FFF33F CFGVALID Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. 0 1 read-write 0 Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. #0 1 Valid. The current channel descriptor is considered valid. #1 RELOAD Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. 1 1 read-write 0 Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. #0 1 Enabled. Reload the channels' control structure when the current descriptor is exhausted. #1 SWTRIG Software Trigger. 2 1 read-write 0 Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. #0 1 Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. #1 CLRTRIG Clear Trigger. 3 1 read-write 0 Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. #0 1 Cleared. The trigger is cleared when this descriptor is exhausted #1 SETINTA Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 4 1 read-write 0 No effect. #0 1 Set. The INTA flag for this channel will be set when the current descriptor is exhausted. #1 SETINTB Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 5 1 read-write 0 No effect. #0 1 Set. The INTB flag for this channel will be set when the current descriptor is exhausted. #1 WIDTH Transfer width used for this DMA channel. 8 2 read-write 00 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). #00 01 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). #01 10 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). #10 11 Reserved. Reserved setting, do not use. #11 SRCINC Determines whether the source address is incremented for each DMA transfer. 12 2 read-write 00 No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. #00 01 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. #01 10 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. #11 DSTINC Determines whether the destination address is incremented for each DMA transfer. 14 2 read-write 00 No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. #00 01 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. #01 10 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. #11 XFERCOUNT Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed. 16 10 read-write CFG23 Configuration register for DMA channel . 0x570 32 read-write 0 0x7CF73 PERIPHREQEN Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. 0 1 read-write 0 Disabled. Peripheral DMA requests are disabled. #0 1 Enabled. Peripheral DMA requests are enabled. #1 HWTRIGEN Hardware Triggering Enable for this channel. 1 1 read-write 0 Disabled. Hardware triggering is not used. #0 1 Enabled. Use hardware triggering. #1 TRIGPOL Trigger Polarity. Selects the polarity of a hardware trigger for this channel. 4 1 read-write 0 Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. #0 1 Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. #1 TRIGTYPE Trigger Type. Selects hardware trigger as edge triggered or level triggered. 5 1 read-write 0 Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. #0 1 Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. #1 TRIGBURST Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. 6 1 read-write 0 Single transfer. Hardware trigger causes a single transfer. #0 1 Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. #1 BURSTPOWER Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size. 8 4 read-write SRCBURSTWRAP Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. 14 1 read-write 0 Disabled. Source burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Source burst wrapping is enabled for this DMA channel. #1 DSTBURSTWRAP Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. 15 1 read-write 0 Disabled. Destination burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Destination burst wrapping is enabled for this DMA channel. #1 CHPRIORITY Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority. 16 3 read-write CTLSTAT23 Control and status register for DMA channel . 0x574 32 read-only 0 0x5 VALIDPENDING Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. 0 1 read-only 0 No effect. No effect on DMA operation. #0 1 Valid pending. #1 TRIG Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. 2 1 read-only 0 Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. #0 1 Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. #1 XFERCFG23 Transfer configuration register for DMA channel . 0x578 32 read-write 0 0x3FFF33F CFGVALID Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. 0 1 read-write 0 Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. #0 1 Valid. The current channel descriptor is considered valid. #1 RELOAD Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. 1 1 read-write 0 Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. #0 1 Enabled. Reload the channels' control structure when the current descriptor is exhausted. #1 SWTRIG Software Trigger. 2 1 read-write 0 Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. #0 1 Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. #1 CLRTRIG Clear Trigger. 3 1 read-write 0 Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. #0 1 Cleared. The trigger is cleared when this descriptor is exhausted #1 SETINTA Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 4 1 read-write 0 No effect. #0 1 Set. The INTA flag for this channel will be set when the current descriptor is exhausted. #1 SETINTB Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 5 1 read-write 0 No effect. #0 1 Set. The INTB flag for this channel will be set when the current descriptor is exhausted. #1 WIDTH Transfer width used for this DMA channel. 8 2 read-write 00 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). #00 01 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). #01 10 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). #10 11 Reserved. Reserved setting, do not use. #11 SRCINC Determines whether the source address is incremented for each DMA transfer. 12 2 read-write 00 No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. #00 01 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. #01 10 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. #11 DSTINC Determines whether the destination address is incremented for each DMA transfer. 14 2 read-write 00 No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. #00 01 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. #01 10 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. #11 XFERCOUNT Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed. 16 10 read-write CFG24 Configuration register for DMA channel . 0x580 32 read-write 0 0x7CF73 PERIPHREQEN Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. 0 1 read-write 0 Disabled. Peripheral DMA requests are disabled. #0 1 Enabled. Peripheral DMA requests are enabled. #1 HWTRIGEN Hardware Triggering Enable for this channel. 1 1 read-write 0 Disabled. Hardware triggering is not used. #0 1 Enabled. Use hardware triggering. #1 TRIGPOL Trigger Polarity. Selects the polarity of a hardware trigger for this channel. 4 1 read-write 0 Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. #0 1 Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. #1 TRIGTYPE Trigger Type. Selects hardware trigger as edge triggered or level triggered. 5 1 read-write 0 Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. #0 1 Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. #1 TRIGBURST Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. 6 1 read-write 0 Single transfer. Hardware trigger causes a single transfer. #0 1 Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. #1 BURSTPOWER Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size. 8 4 read-write SRCBURSTWRAP Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. 14 1 read-write 0 Disabled. Source burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Source burst wrapping is enabled for this DMA channel. #1 DSTBURSTWRAP Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. 15 1 read-write 0 Disabled. Destination burst wrapping is not enabled for this DMA channel. #0 1 Enabled. Destination burst wrapping is enabled for this DMA channel. #1 CHPRIORITY Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority. 16 3 read-write CTLSTAT24 Control and status register for DMA channel . 0x584 32 read-only 0 0x5 VALIDPENDING Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. 0 1 read-only 0 No effect. No effect on DMA operation. #0 1 Valid pending. #1 TRIG Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. 2 1 read-only 0 Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. #0 1 Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. #1 XFERCFG24 Transfer configuration register for DMA channel . 0x588 32 read-write 0 0x3FFF33F CFGVALID Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. 0 1 read-write 0 Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. #0 1 Valid. The current channel descriptor is considered valid. #1 RELOAD Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. 1 1 read-write 0 Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. #0 1 Enabled. Reload the channels' control structure when the current descriptor is exhausted. #1 SWTRIG Software Trigger. 2 1 read-write 0 Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. #0 1 Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. #1 CLRTRIG Clear Trigger. 3 1 read-write 0 Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. #0 1 Cleared. The trigger is cleared when this descriptor is exhausted #1 SETINTA Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 4 1 read-write 0 No effect. #0 1 Set. The INTA flag for this channel will be set when the current descriptor is exhausted. #1 SETINTB Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 5 1 read-write 0 No effect. #0 1 Set. The INTB flag for this channel will be set when the current descriptor is exhausted. #1 WIDTH Transfer width used for this DMA channel. 8 2 read-write 00 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). #00 01 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). #01 10 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). #10 11 Reserved. Reserved setting, do not use. #11 SRCINC Determines whether the source address is incremented for each DMA transfer. 12 2 read-write 00 No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. #00 01 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. #01 10 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. #11 DSTINC Determines whether the destination address is incremented for each DMA transfer. 14 2 read-write 00 No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. #00 01 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. #01 10 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. #10 11 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. #11 XFERCOUNT Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed. 16 10 read-write MTB_SFR LPC84x Micro Trace Buffer 0x5000C000 0 0x10 registers POSITION POSITION Register 0 32 read-write 0 0 WRAP This bit is set to 1 automatically when the POINTER value wraps as determined by the MASTER.MASK field in the MASTER Trace Control Register. 2 1 read-write POINTER Trace packet location pointer. Because a packet consists of two words, the POINTER field is the location of the first word of a packet. This field contains bits [31:3] of the address, in the SRAM, where the next trace packet will be written. The field points to an unused location and is automatically incremented. A debug agent can calculate the system address, on the AHB-Lite bus, of the SRAM location pointed to by the POSITION register using the following equation: system address = BASE + ((P + (2AWIDTH - (BASE MOD 2AWIDTH))) MOD 2AWIDTH). Where P = POSITION AND 0xFFFF_FFF8. Where BASE is the BASE register value 3 29 read-write MASTER MASTER Register 0x4 32 read-write 0x80 0x800003E0 MASK This value determines the maximum size of the trace buffer in SRAM. It specifies the most-significant bit of the POSITION.POINTER field that can be updated by automatic increment. If the trace tries to advance past this power of two, the POSITION.WRAP bit is set to 1, the POSITION.POINTER[MASK:0] bits are set to zero, and the POSITION.POINTER[AWIDTH-4:MASK+1] bits remain unchanged. This field causes the trace packet information to be stored in a circular buffer of size 2(MASK+4) bytes, that can be positioned in memory at multiples of this size. Valid values of this field are zero to AWIDTH-4. Values greater than the maximum have the same effect as the maximum. 0 5 read-write TSTARTEN Trace start input enable. If this bit is 1 and the TSTART signal is HIGH, then the EN bit is set to 1. Tracing continues until a stop condition occurs. 5 1 read-write TSTOPEN Trace stop input enable. If this bit is 1 and the TSTOP signal is HIGH, then the EN bit is set to 0. If a trace packet is being written to memory, the write is completed before tracing is stopped. 6 1 read-write SFRWPRIV Special Function Register Write Privilege bit. If this bit is 0, then User or Privileged AHB-Lite read and write accesses to the Special Function Registers are permitted. If this bit is 1, then only Privileged write accesses are permitted and User write accesses are ignored. The HPROT[1] signal determines if an access is User or Privileged. 7 1 read-write RAMPRIV SRAM Privilege bit. If this bit is 0, then User or Privileged AHB-Lite read and write accesses to the SRAM are permitted. If this bit is 1, then only Privileged AHB-Lite read and write accesses to the SRAM are permitted and User accesses are RAZ/WI. The HPROT[1] signal determines if an access is User or Privileged. 8 1 read-write HALTREQ Halt request bit. This bit is connected to the halt request signal of the trace logic, EDBGRQ. When HALTREQ is set to 1, EDBGRQ is asserted if DBGEN is also HIGH. The HALTREQ bit can be automatically set to 1 using the FLOW.WATERMARK field. 9 1 read-write EN Main trace enable bit. When this bit is 1 trace data is written into the SRAM memory location addressed by POSITION.POINTER. The POSITION.POINTER value auto increments after the trace data packet is written. The EN bit can be automatically set to 0 using the FLOW.WATERMARK field and the FLOW.AUTOSTOP bit. The EN bit is automatically set to 1 if the TSTARTEN bit is 1 and the TSTART signal is HIGH. The EN bit is automatically set to 0 if TSTOPEN bit is 1 and the TSTOP signal is HIGH. 31 1 read-write FLOW FLOW Register 0x8 32 read-write 0 0x3 AUTOSTOP If this bit is 1 and WATERMARK is equal to POSITION.POINTER, then the MASTER.EN bit is automatically set to 0. This stops tracing. 0 1 read-write AUTOHALT If this bit is 1 and WATERMARK is equal to POSITION.POINTER, then the MASTER.HALTREQ bit is automatically set to 1. If the DBGEN signal is HIGH, the MTB asserts this halt request to the Cortex-M0+ processor by asserting the EDBGRQ signal. 1 1 read-write WATERMARK WATERMARK value. This field contains an address in the same format as the POSITION.POINTER field. When the POSITION.POINTER matches the WATERMARK field value, actions defined by the AUTOHALT and AUTOSTOP bits are performed. 3 29 read-write BASE Indicates where the SRAM is located in the processor memory map. This register is provided to enable auto discovery of the MTB SRAM location, by a debug agent. 0xC 32 read-only 0 0 BASE The value provided is the value of the SRAMBASEADDR[31:0] signal. 0 32 read-only GPIO LPC84x General Purpose I/O (GPIO) 0xA0000000 0 0x2488 registers B0_0 Byte pin registers for all port 0 and 1 GPIO pins 0 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_1 Byte pin registers for all port 0 and 1 GPIO pins 0x1 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_2 Byte pin registers for all port 0 and 1 GPIO pins 0x2 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_3 Byte pin registers for all port 0 and 1 GPIO pins 0x3 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_4 Byte pin registers for all port 0 and 1 GPIO pins 0x4 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_5 Byte pin registers for all port 0 and 1 GPIO pins 0x5 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_6 Byte pin registers for all port 0 and 1 GPIO pins 0x6 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_7 Byte pin registers for all port 0 and 1 GPIO pins 0x7 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_8 Byte pin registers for all port 0 and 1 GPIO pins 0x8 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_9 Byte pin registers for all port 0 and 1 GPIO pins 0x9 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_10 Byte pin registers for all port 0 and 1 GPIO pins 0xA 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_11 Byte pin registers for all port 0 and 1 GPIO pins 0xB 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_12 Byte pin registers for all port 0 and 1 GPIO pins 0xC 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_13 Byte pin registers for all port 0 and 1 GPIO pins 0xD 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_14 Byte pin registers for all port 0 and 1 GPIO pins 0xE 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_15 Byte pin registers for all port 0 and 1 GPIO pins 0xF 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_16 Byte pin registers for all port 0 and 1 GPIO pins 0x10 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_17 Byte pin registers for all port 0 and 1 GPIO pins 0x11 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_18 Byte pin registers for all port 0 and 1 GPIO pins 0x12 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_19 Byte pin registers for all port 0 and 1 GPIO pins 0x13 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_20 Byte pin registers for all port 0 and 1 GPIO pins 0x14 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_21 Byte pin registers for all port 0 and 1 GPIO pins 0x15 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_22 Byte pin registers for all port 0 and 1 GPIO pins 0x16 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_23 Byte pin registers for all port 0 and 1 GPIO pins 0x17 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_24 Byte pin registers for all port 0 and 1 GPIO pins 0x18 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_25 Byte pin registers for all port 0 and 1 GPIO pins 0x19 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_26 Byte pin registers for all port 0 and 1 GPIO pins 0x1A 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_27 Byte pin registers for all port 0 and 1 GPIO pins 0x1B 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_28 Byte pin registers for all port 0 and 1 GPIO pins 0x1C 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_29 Byte pin registers for all port 0 and 1 GPIO pins 0x1D 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_30 Byte pin registers for all port 0 and 1 GPIO pins 0x1E 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_31 Byte pin registers for all port 0 and 1 GPIO pins 0x1F 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B1_0 Byte pin registers for all port 0 and 1 GPIO pins 0x20 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B1_1 Byte pin registers for all port 0 and 1 GPIO pins 0x21 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B1_2 Byte pin registers for all port 0 and 1 GPIO pins 0x22 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B1_3 Byte pin registers for all port 0 and 1 GPIO pins 0x23 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B1_4 Byte pin registers for all port 0 and 1 GPIO pins 0x24 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B1_5 Byte pin registers for all port 0 and 1 GPIO pins 0x25 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B1_6 Byte pin registers for all port 0 and 1 GPIO pins 0x26 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B1_7 Byte pin registers for all port 0 and 1 GPIO pins 0x27 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B1_8 Byte pin registers for all port 0 and 1 GPIO pins 0x28 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B1_9 Byte pin registers for all port 0 and 1 GPIO pins 0x29 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B1_10 Byte pin registers for all port 0 and 1 GPIO pins 0x2A 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B1_11 Byte pin registers for all port 0 and 1 GPIO pins 0x2B 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B1_12 Byte pin registers for all port 0 and 1 GPIO pins 0x2C 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B1_13 Byte pin registers for all port 0 and 1 GPIO pins 0x2D 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B1_14 Byte pin registers for all port 0 and 1 GPIO pins 0x2E 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B1_15 Byte pin registers for all port 0 and 1 GPIO pins 0x2F 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B1_16 Byte pin registers for all port 0 and 1 GPIO pins 0x30 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B1_17 Byte pin registers for all port 0 and 1 GPIO pins 0x31 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B1_18 Byte pin registers for all port 0 and 1 GPIO pins 0x32 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B1_19 Byte pin registers for all port 0 and 1 GPIO pins 0x33 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B1_20 Byte pin registers for all port 0 and 1 GPIO pins 0x34 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B1_21 Byte pin registers for all port 0 and 1 GPIO pins 0x35 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B1_22 Byte pin registers for all port 0 and 1 GPIO pins 0x36 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B1_23 Byte pin registers for all port 0 and 1 GPIO pins 0x37 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B1_24 Byte pin registers for all port 0 and 1 GPIO pins 0x38 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B1_25 Byte pin registers for all port 0 and 1 GPIO pins 0x39 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B1_26 Byte pin registers for all port 0 and 1 GPIO pins 0x3A 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B1_27 Byte pin registers for all port 0 and 1 GPIO pins 0x3B 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B1_28 Byte pin registers for all port 0 and 1 GPIO pins 0x3C 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B1_29 Byte pin registers for all port 0 and 1 GPIO pins 0x3D 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B1_30 Byte pin registers for all port 0 and 1 GPIO pins 0x3E 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B1_31 Byte pin registers for all port 0 and 1 GPIO pins 0x3F 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write W0_0 Word pin registers for all port 0 and 1 GPIO pins 0x1000 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_1 Word pin registers for all port 0 and 1 GPIO pins 0x1004 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_2 Word pin registers for all port 0 and 1 GPIO pins 0x1008 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_3 Word pin registers for all port 0 and 1 GPIO pins 0x100C 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_4 Word pin registers for all port 0 and 1 GPIO pins 0x1010 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_5 Word pin registers for all port 0 and 1 GPIO pins 0x1014 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_6 Word pin registers for all port 0 and 1 GPIO pins 0x1018 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_7 Word pin registers for all port 0 and 1 GPIO pins 0x101C 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_8 Word pin registers for all port 0 and 1 GPIO pins 0x1020 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_9 Word pin registers for all port 0 and 1 GPIO pins 0x1024 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_10 Word pin registers for all port 0 and 1 GPIO pins 0x1028 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_11 Word pin registers for all port 0 and 1 GPIO pins 0x102C 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_12 Word pin registers for all port 0 and 1 GPIO pins 0x1030 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_13 Word pin registers for all port 0 and 1 GPIO pins 0x1034 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_14 Word pin registers for all port 0 and 1 GPIO pins 0x1038 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_15 Word pin registers for all port 0 and 1 GPIO pins 0x103C 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_16 Word pin registers for all port 0 and 1 GPIO pins 0x1040 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_17 Word pin registers for all port 0 and 1 GPIO pins 0x1044 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_18 Word pin registers for all port 0 and 1 GPIO pins 0x1048 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_19 Word pin registers for all port 0 and 1 GPIO pins 0x104C 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_20 Word pin registers for all port 0 and 1 GPIO pins 0x1050 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_21 Word pin registers for all port 0 and 1 GPIO pins 0x1054 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_22 Word pin registers for all port 0 and 1 GPIO pins 0x1058 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_23 Word pin registers for all port 0 and 1 GPIO pins 0x105C 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_24 Word pin registers for all port 0 and 1 GPIO pins 0x1060 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_25 Word pin registers for all port 0 and 1 GPIO pins 0x1064 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_26 Word pin registers for all port 0 and 1 GPIO pins 0x1068 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_27 Word pin registers for all port 0 and 1 GPIO pins 0x106C 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_28 Word pin registers for all port 0 and 1 GPIO pins 0x1070 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_29 Word pin registers for all port 0 and 1 GPIO pins 0x1074 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_30 Word pin registers for all port 0 and 1 GPIO pins 0x1078 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_31 Word pin registers for all port 0 and 1 GPIO pins 0x107C 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W1_0 Word pin registers for all port 0 and 1 GPIO pins 0x1080 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W1_1 Word pin registers for all port 0 and 1 GPIO pins 0x1084 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W1_2 Word pin registers for all port 0 and 1 GPIO pins 0x1088 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W1_3 Word pin registers for all port 0 and 1 GPIO pins 0x108C 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W1_4 Word pin registers for all port 0 and 1 GPIO pins 0x1090 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W1_5 Word pin registers for all port 0 and 1 GPIO pins 0x1094 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W1_6 Word pin registers for all port 0 and 1 GPIO pins 0x1098 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W1_7 Word pin registers for all port 0 and 1 GPIO pins 0x109C 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W1_8 Word pin registers for all port 0 and 1 GPIO pins 0x10A0 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W1_9 Word pin registers for all port 0 and 1 GPIO pins 0x10A4 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W1_10 Word pin registers for all port 0 and 1 GPIO pins 0x10A8 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W1_11 Word pin registers for all port 0 and 1 GPIO pins 0x10AC 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W1_12 Word pin registers for all port 0 and 1 GPIO pins 0x10B0 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W1_13 Word pin registers for all port 0 and 1 GPIO pins 0x10B4 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W1_14 Word pin registers for all port 0 and 1 GPIO pins 0x10B8 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W1_15 Word pin registers for all port 0 and 1 GPIO pins 0x10BC 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W1_16 Word pin registers for all port 0 and 1 GPIO pins 0x10C0 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W1_17 Word pin registers for all port 0 and 1 GPIO pins 0x10C4 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W1_18 Word pin registers for all port 0 and 1 GPIO pins 0x10C8 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W1_19 Word pin registers for all port 0 and 1 GPIO pins 0x10CC 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W1_20 Word pin registers for all port 0 and 1 GPIO pins 0x10D0 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W1_21 Word pin registers for all port 0 and 1 GPIO pins 0x10D4 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W1_22 Word pin registers for all port 0 and 1 GPIO pins 0x10D8 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W1_23 Word pin registers for all port 0 and 1 GPIO pins 0x10DC 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W1_24 Word pin registers for all port 0 and 1 GPIO pins 0x10E0 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W1_25 Word pin registers for all port 0 and 1 GPIO pins 0x10E4 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W1_26 Word pin registers for all port 0 and 1 GPIO pins 0x10E8 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W1_27 Word pin registers for all port 0 and 1 GPIO pins 0x10EC 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W1_28 Word pin registers for all port 0 and 1 GPIO pins 0x10F0 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W1_29 Word pin registers for all port 0 and 1 GPIO pins 0x10F4 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W1_30 Word pin registers for all port 0 and 1 GPIO pins 0x10F8 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W1_31 Word pin registers for all port 0 and 1 GPIO pins 0x10FC 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write DIR0 Direction registers 0x2000 32 read-write 0 0xFFFFFFFF DIRP Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output. 0 32 read-write DIR1 Direction registers 0x2004 32 read-write 0 0xFFFFFFFF DIRP Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output. 0 32 read-write MASK0 Mask register 0x2080 32 read-write 0 0xFFFFFFFF MASKP Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. 0 32 read-write MASK1 Mask register 0x2084 32 read-write 0 0xFFFFFFFF MASKP Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. 0 32 read-write PIN0 Port pin register 0x2100 32 read-write 0 0xFFFFFFFF PORT Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. 0 32 read-write PIN1 Port pin register 0x2104 32 read-write 0 0xFFFFFFFF PORT Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. 0 32 read-write MPIN0 Masked port register 0x2180 32 read-write 0 0xFFFFFFFF MPORTP Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. 0 32 read-write MPIN1 Masked port register 0x2184 32 read-write 0 0xFFFFFFFF MPORTP Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. 0 32 read-write SET0 Write: Set register for port Read: output bits for port 0x2200 32 read-write 0 0xFFFFFFFF SETP Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. 0 32 read-write SET1 Write: Set register for port Read: output bits for port 0x2204 32 read-write 0 0xFFFFFFFF SETP Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. 0 32 read-write CLR0 Clear port 0x2280 32 write-only 0 0 CLRP Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit. 0 32 write-only CLR1 Clear port 0x2284 32 write-only 0 0 CLRP Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit. 0 32 write-only NOT0 Toggle port 0x2300 32 write-only 0 0 NOTP Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit. 0 32 write-only NOT1 Toggle port 0x2304 32 write-only 0 0 NOTP Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit. 0 32 write-only DIRSET0 Set pin direction bits for port 0x2380 32 write-only 0 0 DIRSETP Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Set direction bit. 0 29 write-only DIRSET1 Set pin direction bits for port 0x2384 32 write-only 0 0 DIRSETP Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Set direction bit. 0 29 write-only DIRCLR0 Clear pin direction bits for port 0x2400 32 write-only 0 0 DIRCLRP Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit. 0 29 write-only DIRCLR1 Clear pin direction bits for port 0x2404 32 write-only 0 0 DIRCLRP Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit. 0 29 write-only DIRNOT0 Toggle pin direction bits for port 0x2480 32 write-only 0 0 DIRNOTP Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle direction bit. 0 29 write-only DIRNOT1 Toggle pin direction bits for port 0x2484 32 write-only 0 0 DIRNOTP Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle direction bit. 0 29 write-only PINT LPC84x Pin interrupt and pattern match (PINT) 0xA0004000 0 0x34 registers PIN_INT0 24 PIN_INT1 25 PIN_INT2 26 PIN_INT3 27 PIN_INT4 28 PIN_INT5_DAC1 29 PIN_INT6_USART3 30 PIN_INT7_USART4 31 ISEL Pin Interrupt Mode register 0 32 read-write 0 0xFF PMODE Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive 0 8 read-write IENR Pin interrupt level or rising edge interrupt enable register 0x4 32 read-write 0 0xFF ENRL Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. 0 8 read-write SIENR Pin interrupt level or rising edge interrupt set register 0x8 32 write-only 0 0 SETENRL Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. 0 8 write-only CIENR Pin interrupt level (rising edge interrupt) clear register 0xC 32 write-only 0 0 CENRL Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. 0 8 write-only IENF Pin interrupt active level or falling edge interrupt enable register 0x10 32 read-write 0 0xFF ENAF Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. 0 8 read-write SIENF Pin interrupt active level or falling edge interrupt set register 0x14 32 write-only 0 0 SETENAF Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. 0 8 write-only CIENF Pin interrupt active level or falling edge interrupt clear register 0x18 32 write-only 0 0 CENAF Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. 0 8 write-only RISE Pin interrupt rising edge register 0x1C 32 read-write 0 0xFF RDET Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. 0 8 read-write FALL Pin interrupt falling edge register 0x20 32 read-write 0 0xFF FDET Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. 0 8 read-write IST Pin interrupt status register 0x24 32 read-write 0 0xFF PSTAT Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). 0 8 read-write PMCTRL Pattern match interrupt control register 0x28 32 read-write 0 0xFF000003 SEL_PMATCH Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function. 0 1 read-write 0 Pin interrupt. Interrupts are driven in response to the standard pin interrupt function. #0 1 Pattern match. Interrupts are driven in response to pattern matches. #1 ENA_RXEV Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true. 1 1 read-write 0 Disabled. RXEV output to the CPU is disabled. #0 1 Enabled. RXEV output to the CPU is enabled. #1 PMAT This field displays the current state of pattern matches. A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs. 24 8 read-write PMSRC Pattern match interrupt bit-slice source register 0x2C 32 read-write 0 0xFFFFFF00 SRC0 Selects the input source for bit slice 0 8 3 read-write 000 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0. #000 001 Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0. #001 010 Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0. #010 011 Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0. #011 100 Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0. #100 101 Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0. #101 110 Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0. #110 111 Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0. #111 SRC1 Selects the input source for bit slice 1 11 3 read-write 000 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1. #000 001 Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1. #001 010 Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1. #010 011 Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1. #011 100 Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1. #100 101 Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1. #101 110 Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1. #110 111 Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1. #111 SRC2 Selects the input source for bit slice 2 14 3 read-write 000 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2. #000 001 Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2. #001 010 Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2. #010 011 Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2. #011 100 Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2. #100 101 Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2. #101 110 Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2. #110 111 Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2. #111 SRC3 Selects the input source for bit slice 3 17 3 read-write 000 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3. #000 001 Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3. #001 010 Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3. #010 011 Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3. #011 100 Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3. #100 101 Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3. #101 110 Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3. #110 111 Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3. #111 SRC4 Selects the input source for bit slice 4 20 3 read-write 000 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4. #000 001 Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4. #001 010 Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4. #010 011 Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4. #011 100 Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4. #100 101 Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4. #101 110 Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4. #110 111 Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4. #111 SRC5 Selects the input source for bit slice 5 23 3 read-write 000 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5. #000 001 Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5. #001 010 Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5. #010 011 Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5. #011 100 Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5. #100 101 Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5. #101 110 Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5. #110 111 Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5. #111 SRC6 Selects the input source for bit slice 6 26 3 read-write 000 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6. #000 001 Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6. #001 010 Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6. #010 011 Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6. #011 100 Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6. #100 101 Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6. #101 110 Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6. #110 111 Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6. #111 SRC7 Selects the input source for bit slice 7 29 3 read-write 000 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7. #000 001 Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7. #001 010 Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7. #010 011 Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7. #011 100 Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7. #100 101 Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7. #101 110 Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7. #110 111 Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7. #111 PMCFG Pattern match interrupt bit slice configuration register 0x30 32 read-write 0 0xFFFFFF7F PROD_ENDPTS0 Determines whether slice 0 is an endpoint. 0 1 read-write 0 No effect. Slice 0 is not an endpoint. #0 1 endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true. #1 PROD_ENDPTS1 Determines whether slice 1 is an endpoint. 1 1 read-write 0 No effect. Slice 1 is not an endpoint. #0 1 endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true. #1 PROD_ENDPTS2 Determines whether slice 2 is an endpoint. 2 1 read-write 0 No effect. Slice 2 is not an endpoint. #0 1 endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true. #1 PROD_ENDPTS3 Determines whether slice 3 is an endpoint. 3 1 read-write 0 No effect. Slice 3 is not an endpoint. #0 1 endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true. #1 PROD_ENDPTS4 Determines whether slice 4 is an endpoint. 4 1 read-write 0 No effect. Slice 4 is not an endpoint. #0 1 endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true. #1 PROD_ENDPTS5 Determines whether slice 5 is an endpoint. 5 1 read-write 0 No effect. Slice 5 is not an endpoint. #0 1 endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true. #1 PROD_ENDPTS6 Determines whether slice 6 is an endpoint. 6 1 read-write 0 No effect. Slice 6 is not an endpoint. #0 1 endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true. #1 CFG0 Specifies the match contribution condition for bit slice 0. 8 3 read-write 000 Constant HIGH. This bit slice always contributes to a product term match. #000 001 Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. #001 010 Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. #010 011 Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. #011 100 High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. #100 101 Low level. Match occurs when there is a low level on the specified input. #101 110 Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). #110 111 Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. #111 CFG1 Specifies the match contribution condition for bit slice 1. 11 3 read-write 000 Constant HIGH. This bit slice always contributes to a product term match. #000 001 Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. #001 010 Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. #010 011 Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. #011 100 High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. #100 101 Low level. Match occurs when there is a low level on the specified input. #101 110 Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). #110 111 Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. #111 CFG2 Specifies the match contribution condition for bit slice 2. 14 3 read-write 000 Constant HIGH. This bit slice always contributes to a product term match. #000 001 Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. #001 010 Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. #010 011 Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. #011 100 High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. #100 101 Low level. Match occurs when there is a low level on the specified input. #101 110 Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). #110 111 Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. #111 CFG3 Specifies the match contribution condition for bit slice 3. 17 3 read-write 000 Constant HIGH. This bit slice always contributes to a product term match. #000 001 Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. #001 010 Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. #010 011 Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. #011 100 High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. #100 101 Low level. Match occurs when there is a low level on the specified input. #101 110 Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). #110 111 Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. #111 CFG4 Specifies the match contribution condition for bit slice 4. 20 3 read-write 000 Constant HIGH. This bit slice always contributes to a product term match. #000 001 Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. #001 010 Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. #010 011 Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. #011 100 High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. #100 101 Low level. Match occurs when there is a low level on the specified input. #101 110 Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). #110 111 Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. #111 CFG5 Specifies the match contribution condition for bit slice 5. 23 3 read-write 000 Constant HIGH. This bit slice always contributes to a product term match. #000 001 Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. #001 010 Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. #010 011 Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. #011 100 High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. #100 101 Low level. Match occurs when there is a low level on the specified input. #101 110 Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). #110 111 Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. #111 CFG6 Specifies the match contribution condition for bit slice 6. 26 3 read-write 000 Constant HIGH. This bit slice always contributes to a product term match. #000 001 Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. #001 010 Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. #010 011 Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. #011 100 High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. #100 101 Low level. Match occurs when there is a low level on the specified input. #101 110 Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). #110 111 Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. #111 CFG7 Specifies the match contribution condition for bit slice 7. 29 3 read-write 000 Constant HIGH. This bit slice always contributes to a product term match. #000 001 Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. #001 010 Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. #010 011 Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. #011 100 High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. #100 101 Low level. Match occurs when there is a low level on the specified input. #101 110 Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). #110 111 Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. #111