696 lines
19 KiB
C
696 lines
19 KiB
C
/*
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* Copyright 2017-2019 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_clock.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.clock"
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#endif
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#define SYSPLL_MIN_INPUT_FREQ_HZ (10000000U) /*!< Minimum PLL input rate */
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#define SYSPLL_MAX_INPUT_FREQ_HZ (25000000U) /*!< Maximum PLL input rate */
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#define SYSPLL_MAX_OUTPUT_FREQ_HZ (100000000U) /*!< Maximum PLL output rate */
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#define SYSPLL_MIN_FCCO_FREQ_HZ (156000000U) /*!< Maximum FCCO output rate */
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#define SYSPLL_MAX_FCCO_FREQ_HZ (320000000U) /*!< Maximum FCCO output rate */
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#define SYSOSC_BOUNDARY_FREQ_HZ (15000000U) /*!< boundary frequency value */
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/* External clock rate.
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* Either external clk in rate or system oscillator frequency.
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*/
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volatile uint32_t g_Ext_Clk_Freq = 0U;
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/** watch dog oscillator rate in Hz.*/
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volatile uint32_t g_Wdt_Osc_Freq = 0U;
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*
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* @brief select post divider for system pll according to the target frequency.
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* @param outFreq: Value to be output
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* @return post divider
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*/
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static uint32_t findSyestemPllPsel(uint32_t outFreq);
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/*
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* @brief Get FRG input clock frequency.
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* @param fractional clock register base address.
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* @return input clock frequency.
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*/
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static uint32_t CLOCK_GetFRGInputClkFreq(uint32_t *base);
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/*
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* @brief Update clock source.
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* @param base clock register base address.
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* @param mask clock source update enable bit mask value.
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*/
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static void CLOCK_UpdateClkSrc(volatile uint32_t *base, uint32_t mask);
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/*******************************************************************************
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* Code
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******************************************************************************/
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static uint32_t CLOCK_GetFRGInputClkFreq(uint32_t *base)
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{
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uint32_t sel = CLK_FRG_SEL_REG_MAP(base) & SYSCON_FRG_FRGCLKSEL_SEL_MASK;
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if (sel == 0U)
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{
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return CLOCK_GetFroFreq();
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}
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else if (sel == 1U)
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{
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return CLOCK_GetMainClkFreq();
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}
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else
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{
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return CLOCK_GetSystemPLLFreq();
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}
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}
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static bool CLOCK_SetFRGClkFreq(uint32_t *base, uint32_t freq)
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{
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assert(freq);
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uint32_t input = CLOCK_GetFRGInputClkFreq(base);
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uint32_t mul;
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if ((freq > input) || (input / freq >= 2U))
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{
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return false;
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}
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mul = (uint32_t)(((uint64_t)((uint64_t)input - freq) << 8U) / ((uint64_t)freq));
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CLK_FRG_DIV_REG_MAP(base) = SYSCON_FRG_FRGDIV_DIV_MASK;
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CLK_FRG_MUL_REG_MAP(base) = SYSCON_FRG_FRGMULT_MULT(mul);
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return true;
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}
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static void CLOCK_UpdateClkSrc(volatile uint32_t *base, uint32_t mask)
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{
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assert(base);
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*base &= ~mask;
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*base |= mask;
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while ((*base & mask) == 0U)
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{
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}
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}
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/*! brief Set FRG0 output frequency.
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* param freq, target output frequency,freq < input and (input / freq) < 2 should be satisfy.
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* retval true - successfully, false - input argument is invalid.
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*
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*/
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bool CLOCK_SetFRG0ClkFreq(uint32_t freq)
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{
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return CLOCK_SetFRGClkFreq(((uint32_t *)(uint32_t)(&SYSCON->FRG[0U])), freq);
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}
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/*! brief Set FRG1 output frequency.
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* param freq, target output frequency,freq < input and (input / freq) < 2 should be satisfy.
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* retval true - successfully, false - input argument is invalid.
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*
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*/
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bool CLOCK_SetFRG1ClkFreq(uint32_t freq)
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{
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return CLOCK_SetFRGClkFreq(((uint32_t *)(uint32_t)(&SYSCON->FRG[1U])), freq);
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}
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/*! brief Return Frequency of FRG0 Clock.
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* return Frequency of FRG0 Clock.
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*/
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uint32_t CLOCK_GetFRG0ClkFreq(void)
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{
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uint32_t temp;
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temp = CLOCK_GetFRGInputClkFreq((uint32_t *)(uint32_t)(&SYSCON->FRG[0U])) << 8U;
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return (uint32_t)((uint64_t)(temp) / (((uint64_t)SYSCON->FRG[0U].FRGMULT & SYSCON_FRG_FRGMULT_MULT_MASK) + 256ULL));
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}
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/*! brief Return Frequency of FRG1 Clock.
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* return Frequency of FRG1 Clock.
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*/
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uint32_t CLOCK_GetFRG1ClkFreq(void)
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{
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uint32_t temp;
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temp = (CLOCK_GetFRGInputClkFreq((uint32_t *)(uint32_t)(&SYSCON->FRG[1U])) << 8U);
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return (uint32_t)(((uint64_t)temp) / (((uint64_t)SYSCON->FRG[1U].FRGMULT & SYSCON_FRG_FRGMULT_MULT_MASK) + 256ULL));
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}
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/*! brief Return Frequency of Main Clock.
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* return Frequency of Main Clock.
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*/
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uint32_t CLOCK_GetMainClkFreq(void)
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{
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uint32_t freq = 0U;
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if ((SYSCON->MAINCLKPLLSEL & SYSCON_MAINCLKPLLSEL_SEL_MASK) == 1U)
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{
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return CLOCK_GetSystemPLLFreq();
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}
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switch (SYSCON->MAINCLKSEL)
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{
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case 0U:
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freq = CLOCK_GetFroFreq();
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break;
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case 1U:
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freq = CLOCK_GetExtClkFreq();
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break;
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case 2U:
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freq = CLOCK_GetWdtOscFreq();
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break;
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case 3U:
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freq = CLOCK_GetFroFreq() >> 1U;
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break;
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default:
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freq = 0U;
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break;
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}
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return freq;
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}
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/*! brief Return Frequency of FRO.
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* return Frequency of FRO.
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*/
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uint32_t CLOCK_GetFroFreq(void)
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{
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uint32_t froOscSel = SYSCON->FROOSCCTRL & 3U;
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uint32_t froOscFreq = 0U;
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if (froOscSel == 0U)
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{
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froOscFreq = 18000000U;
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}
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else if (froOscSel == 1U)
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{
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froOscFreq = 24000000U;
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}
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else
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{
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froOscFreq = 30000000U;
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}
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if (((SYSCON->FROOSCCTRL & SYSCON_FROOSCCTRL_FRO_DIRECT_MASK) >> SYSCON_FROOSCCTRL_FRO_DIRECT_SHIFT) == 0U)
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{
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/* need to check the FAIM low power boot value */
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froOscFreq /= ((*((volatile uint32_t *)(CLOCK_FAIM_BASE)) & 0x2U) != 0UL) ? 16U : 2U;
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}
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return froOscFreq;
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}
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/*! brief Return Frequency of ClockOut
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* return Frequency of ClockOut
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*/
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uint32_t CLOCK_GetClockOutClkFreq(void)
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{
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uint32_t divider = SYSCON->CLKOUTDIV & 0xffU, freq = 0U;
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switch (SYSCON->CLKOUTSEL)
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{
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case 0U:
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freq = CLOCK_GetFroFreq();
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break;
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case 1U:
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freq = CLOCK_GetMainClkFreq();
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break;
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case 2U:
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freq = CLOCK_GetSystemPLLFreq();
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break;
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case 3U:
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freq = CLOCK_GetExtClkFreq();
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break;
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case 4U:
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freq = CLOCK_GetWdtOscFreq();
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break;
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default:
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freq = 0U;
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break;
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}
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return divider == 0U ? 0U : (freq / divider);
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}
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/*! brief Return Frequency of UART0
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* return Frequency of UART0
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*/
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uint32_t CLOCK_GetUart0ClkFreq(void)
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{
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uint32_t freq = 0U;
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switch (SYSCON->FCLKSEL[0])
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{
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case 0U:
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freq = CLOCK_GetFroFreq();
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break;
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case 1U:
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freq = CLOCK_GetMainClkFreq();
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break;
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case 2U:
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freq = CLOCK_GetFRG0ClkFreq();
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break;
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case 3U:
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freq = CLOCK_GetFRG1ClkFreq();
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break;
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case 4U:
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freq = CLOCK_GetFroFreq() >> 1U;
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break;
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default:
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freq = 0U;
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break;
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}
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return freq;
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}
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/*! brief Return Frequency of UART1
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* return Frequency of UART1
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*/
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uint32_t CLOCK_GetUart1ClkFreq(void)
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{
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uint32_t freq = 0U;
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switch (SYSCON->FCLKSEL[1])
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{
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case 0U:
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freq = CLOCK_GetFroFreq();
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break;
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case 1U:
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freq = CLOCK_GetMainClkFreq();
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break;
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case 2U:
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freq = CLOCK_GetFRG0ClkFreq();
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break;
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case 3U:
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freq = CLOCK_GetFRG1ClkFreq();
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break;
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case 4U:
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freq = CLOCK_GetFroFreq() >> 1U;
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break;
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default:
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freq = 0U;
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break;
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}
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return freq;
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}
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/*! brief Return Frequency of UART2
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* return Frequency of UART2
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*/
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uint32_t CLOCK_GetUart2ClkFreq(void)
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{
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uint32_t freq = 0U;
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switch (SYSCON->FCLKSEL[2])
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{
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case 0U:
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freq = CLOCK_GetFroFreq();
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break;
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case 1U:
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freq = CLOCK_GetMainClkFreq();
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break;
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case 2U:
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freq = CLOCK_GetFRG0ClkFreq();
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break;
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case 3U:
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freq = CLOCK_GetFRG1ClkFreq();
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break;
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case 4U:
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freq = CLOCK_GetFroFreq() >> 1U;
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break;
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default:
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freq = 0U;
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break;
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}
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return freq;
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}
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/*! brief Return Frequency of UART3
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* return Frequency of UART3
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*/
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uint32_t CLOCK_GetUart3ClkFreq(void)
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{
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uint32_t freq = 0U;
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switch (SYSCON->FCLKSEL[3])
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{
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case 0U:
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freq = CLOCK_GetFroFreq();
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break;
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case 1U:
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freq = CLOCK_GetMainClkFreq();
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break;
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case 2U:
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freq = CLOCK_GetFRG0ClkFreq();
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break;
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case 3U:
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freq = CLOCK_GetFRG1ClkFreq();
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break;
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case 4U:
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freq = CLOCK_GetFroFreq() >> 1U;
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break;
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default:
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freq = 0U;
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break;
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}
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return freq;
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}
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/*! brief Return Frequency of UART4
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* return Frequency of UART4
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*/
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uint32_t CLOCK_GetUart4ClkFreq(void)
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{
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uint32_t freq = 0U;
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switch (SYSCON->FCLKSEL[4])
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{
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case 0U:
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freq = CLOCK_GetFroFreq();
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break;
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case 1U:
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freq = CLOCK_GetMainClkFreq();
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break;
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case 2U:
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freq = CLOCK_GetFRG0ClkFreq();
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break;
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case 3U:
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freq = CLOCK_GetFRG1ClkFreq();
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break;
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case 4U:
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freq = CLOCK_GetFroFreq() >> 1U;
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break;
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default:
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freq = 0U;
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break;
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}
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return freq;
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}
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/*! brief Return Frequency of selected clock
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* return Frequency of selected clock
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*/
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uint32_t CLOCK_GetFreq(clock_name_t clockName)
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{
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uint32_t freq;
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switch (clockName)
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{
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case kCLOCK_CoreSysClk:
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freq = CLOCK_GetCoreSysClkFreq();
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break;
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case kCLOCK_MainClk:
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freq = CLOCK_GetMainClkFreq();
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break;
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case kCLOCK_Fro:
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freq = CLOCK_GetFroFreq();
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break;
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case kCLOCK_FroDiv:
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freq = CLOCK_GetFroFreq() >> 1U;
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break;
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case kCLOCK_ExtClk:
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freq = CLOCK_GetExtClkFreq();
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break;
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case kCLOCK_WdtOsc:
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freq = CLOCK_GetWdtOscFreq();
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break;
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case kCLOCK_PllOut:
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freq = CLOCK_GetSystemPLLFreq();
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break;
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case kCLOCK_Frg0:
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freq = CLOCK_GetFRG0ClkFreq();
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break;
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case kCLOCK_Frg1:
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freq = CLOCK_GetFRG1ClkFreq();
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break;
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default:
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freq = 0U;
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break;
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}
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return freq;
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}
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/*! brief Return System PLL input clock rate
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* return System PLL input clock rate
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*/
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uint32_t CLOCK_GetSystemPLLInClockRate(void)
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{
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uint32_t freq = 0U;
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switch ((SYSCON->SYSPLLCLKSEL))
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{
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/* source from fro div clock */
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case 0x03U:
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freq = CLOCK_GetFroFreq() >> 1U;
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break;
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/* source from the fro clock */
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case 0x00U:
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freq = CLOCK_GetFroFreq();
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break;
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/* source from external clock in */
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case 0x01U:
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freq = CLOCK_GetExtClkFreq();
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break;
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/* source from watchdog oscillator */
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case 0x02U:
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freq = CLOCK_GetWdtOscFreq();
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break;
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default:
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freq = 0U;
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break;
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}
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return freq;
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}
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static uint32_t findSyestemPllPsel(uint32_t outFreq)
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{
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uint32_t pSel = 0U;
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if (outFreq > (SYSPLL_MIN_FCCO_FREQ_HZ >> 1U))
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{
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pSel = 0U;
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}
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else if (outFreq > (SYSPLL_MIN_FCCO_FREQ_HZ >> 2U))
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{
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pSel = 1U;
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}
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else if (outFreq > (SYSPLL_MIN_FCCO_FREQ_HZ >> 3U))
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{
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pSel = 2U;
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}
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else
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{
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pSel = 3U;
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}
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return pSel;
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}
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/*! brief System PLL initialize.
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* param config System PLL configurations.
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*/
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void CLOCK_InitSystemPll(const clock_sys_pll_t *config)
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{
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assert(config->targetFreq <= SYSPLL_MAX_OUTPUT_FREQ_HZ);
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uint32_t mSel = 0U, pSel = 0U, inputFreq = 0U;
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uint32_t syspllclkseltmp;
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/* Power off PLL during setup changes */
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SYSCON->PDRUNCFG |= SYSCON_PDRUNCFG_SYSPLL_PD_MASK;
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/*set system pll clock source select register */
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syspllclkseltmp = (SYSCON->SYSPLLCLKSEL & (~SYSCON_SYSPLLCLKSEL_SEL_MASK)) | (uint32_t)(config->src);
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SYSCON->SYSPLLCLKSEL |= syspllclkseltmp;
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/* system pll clock source update */
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CLOCK_UpdateClkSrc((volatile uint32_t *)(&(SYSCON->SYSPLLCLKUEN)), SYSCON_SYSPLLCLKSEL_SEL_MASK);
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inputFreq = CLOCK_GetSystemPLLInClockRate();
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assert(inputFreq != 0U);
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/* calucate the feedback divider value and post divider value*/
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mSel = config->targetFreq / inputFreq;
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pSel = findSyestemPllPsel(config->targetFreq);
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/* configure PSEL and MSEL */
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SYSCON->SYSPLLCTRL = (SYSCON->SYSPLLCTRL & (~(SYSCON_SYSPLLCTRL_MSEL_MASK | SYSCON_SYSPLLCTRL_PSEL_MASK))) |
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SYSCON_SYSPLLCTRL_MSEL(mSel == 0U ? 0U : (mSel - 1U)) | SYSCON_SYSPLLCTRL_PSEL(pSel);
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/* Power up PLL after setup changes */
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SYSCON->PDRUNCFG &= ~SYSCON_PDRUNCFG_SYSPLL_PD_MASK;
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/* wait pll lock */
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while ((SYSCON->SYSPLLSTAT & SYSCON_SYSPLLSTAT_LOCK_MASK) == 0U)
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{
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}
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}
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|
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/*! brief Init external CLK IN, select the CLKIN as the external clock source.
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* param clkInFreq external clock in frequency.
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*/
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void CLOCK_InitExtClkin(uint32_t clkInFreq)
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{
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/* remove the pull up and pull down resistors in the IOCON */
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IOCON->PIO[IOCON_INDEX_PIO0_1] &= ~IOCON_PIO_MODE_MASK;
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/* enable the 1 bit functions for CLKIN */
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SWM0->PINENABLE0 &= ~SWM_PINENABLE0_CLKIN_MASK;
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/* enable the external clk in */
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SYSCON->EXTCLKSEL |= SYSCON_EXTCLKSEL_SEL_MASK;
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/* record the external clock rate */
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g_Ext_Clk_Freq = clkInFreq;
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}
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|
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/*! brief XTALIN init function
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* system oscillator is bypassed, sys_osc_clk is fed driectly from the XTALIN.
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* param xtalInFreq XTALIN frequency value
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* return Frequency of PLL
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*/
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void CLOCK_InitXtalin(uint32_t xtalInFreq)
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|
{
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/* remove the pull up and pull down resistors in the IOCON */
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IOCON->PIO[IOCON_INDEX_PIO0_8] &= ~IOCON_PIO_MODE_MASK;
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/* enable the 1 bit functions for XTALIN and XTALOUT */
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SWM0->PINENABLE0 &= ~SWM_PINENABLE0_XTALIN_MASK;
|
|
|
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/* system osc configure */
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SYSCON->SYSOSCCTRL |= SYSCON_SYSOSCCTRL_BYPASS_MASK;
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/* external clock select */
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SYSCON->EXTCLKSEL &= ~SYSCON_EXTCLKSEL_SEL_MASK;
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/* enable system osc power first */
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SYSCON->PDRUNCFG &= ~SYSCON_PDRUNCFG_SYSOSC_PD_MASK;
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|
|
|
/* software delay 500USs */
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SDK_DelayAtLeastUs(500U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
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|
|
|
/* record the external clock rate */
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|
g_Ext_Clk_Freq = xtalInFreq;
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|
}
|
|
|
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/*! brief Init SYS OSC
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* param oscFreq oscillator frequency value.
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|
*/
|
|
void CLOCK_InitSysOsc(uint32_t oscFreq)
|
|
{
|
|
uint32_t sysoscctrltmp;
|
|
/* remove the pull up and pull down resistors in the IOCON */
|
|
IOCON->PIO[IOCON_INDEX_PIO0_9] &= ~IOCON_PIO_MODE_MASK;
|
|
IOCON->PIO[IOCON_INDEX_PIO0_8] &= ~IOCON_PIO_MODE_MASK;
|
|
/* enable the 1 bit functions for XTALIN and XTALOUT */
|
|
SWM0->PINENABLE0 &= ~(SWM_PINENABLE0_XTALIN_MASK | SWM_PINENABLE0_XTALOUT_MASK);
|
|
|
|
/* system osc configure */
|
|
sysoscctrltmp = (SYSCON->SYSOSCCTRL & (~(SYSCON_SYSOSCCTRL_BYPASS_MASK | SYSCON_SYSOSCCTRL_FREQRANGE_MASK))) |
|
|
(oscFreq > SYSOSC_BOUNDARY_FREQ_HZ ? SYSCON_SYSOSCCTRL_FREQRANGE_MASK : 0U);
|
|
SYSCON->SYSOSCCTRL |= sysoscctrltmp;
|
|
/* external clock select */
|
|
SYSCON->EXTCLKSEL &= ~SYSCON_EXTCLKSEL_SEL_MASK;
|
|
|
|
/* enable system osc power first */
|
|
SYSCON->PDRUNCFG &= ~SYSCON_PDRUNCFG_SYSOSC_PD_MASK;
|
|
|
|
/* software delay 500USs */
|
|
SDK_DelayAtLeastUs(500U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
|
|
|
|
/* record the external clock rate */
|
|
g_Ext_Clk_Freq = oscFreq;
|
|
}
|
|
|
|
/*! brief Init watch dog OSC
|
|
* Any setting of the FREQSEL bits will yield a Fclkana value within 40% of the
|
|
* listed frequency value. The watchdog oscillator is the clock source with the lowest power
|
|
* consumption. If accurate timing is required, use the FRO or system oscillator.
|
|
* The frequency of the watchdog oscillator is undefined after reset. The watchdog
|
|
* oscillator frequency must be programmed by writing to the WDTOSCCTRL register before
|
|
* using the watchdog oscillator.
|
|
* Watchdog osc output frequency = wdtOscFreq / wdtOscDiv, should in range 9.3KHZ to 2.3MHZ.
|
|
* param wdtOscFreq watch dog analog part output frequency, reference _wdt_analog_output_freq.
|
|
* param wdtOscDiv watch dog analog part output frequency divider, shoule be a value >= 2U and multiple of 2
|
|
*/
|
|
void CLOCK_InitWdtOsc(clock_wdt_analog_freq_t wdtOscFreq, uint32_t wdtOscDiv)
|
|
{
|
|
assert(wdtOscDiv >= 2U);
|
|
|
|
uint32_t wdtOscCtrl = SYSCON->WDTOSCCTRL;
|
|
|
|
wdtOscCtrl &= ~(SYSCON_WDTOSCCTRL_DIVSEL_MASK | SYSCON_WDTOSCCTRL_FREQSEL_MASK);
|
|
|
|
wdtOscCtrl |= SYSCON_WDTOSCCTRL_DIVSEL((wdtOscDiv >> 1U) - 1U) |
|
|
SYSCON_WDTOSCCTRL_FREQSEL(CLK_WDT_OSC_GET_REG((uint32_t)wdtOscFreq));
|
|
|
|
SYSCON->WDTOSCCTRL = wdtOscCtrl;
|
|
|
|
/* power up watchdog oscillator */
|
|
SYSCON->PDRUNCFG &= ~SYSCON_PDRUNCFG_WDTOSC_PD_MASK;
|
|
/* update watch dog oscillator value */
|
|
g_Wdt_Osc_Freq = CLK_WDT_OSC_GET_FREQ(wdtOscFreq) / wdtOscDiv;
|
|
}
|
|
|
|
/*! brief Set main clock reference source.
|
|
* param src, reference clock_main_clk_src_t to set the main clock source.
|
|
*/
|
|
void CLOCK_SetMainClkSrc(clock_main_clk_src_t src)
|
|
{
|
|
uint32_t mainMux = CLK_MAIN_CLK_MUX_GET_MUX(src), mainPreMux = CLK_MAIN_CLK_MUX_GET_PRE_MUX(src);
|
|
|
|
if (((SYSCON->MAINCLKSEL & SYSCON_MAINCLKSEL_SEL_MASK) != mainPreMux) && (mainMux == 0U))
|
|
{
|
|
SYSCON->MAINCLKSEL = (SYSCON->MAINCLKSEL & (~SYSCON_MAINCLKSEL_SEL_MASK)) | SYSCON_MAINCLKSEL_SEL(mainPreMux);
|
|
CLOCK_UpdateClkSrc((volatile uint32_t *)(&(SYSCON->MAINCLKUEN)), SYSCON_MAINCLKUEN_ENA_MASK);
|
|
}
|
|
|
|
if ((SYSCON->MAINCLKPLLSEL & SYSCON_MAINCLKPLLSEL_SEL_MASK) != mainMux)
|
|
{
|
|
SYSCON->MAINCLKPLLSEL =
|
|
(SYSCON->MAINCLKPLLSEL & (~SYSCON_MAINCLKPLLSEL_SEL_MASK)) | SYSCON_MAINCLKPLLSEL_SEL(mainMux);
|
|
CLOCK_UpdateClkSrc((volatile uint32_t *)(&(SYSCON->MAINCLKPLLUEN)), SYSCON_MAINCLKPLLUEN_ENA_MASK);
|
|
}
|
|
}
|
|
|
|
/*! brief Set FRO clock source
|
|
* param src, please reference _clock_fro_src definition.
|
|
*
|
|
*/
|
|
void CLOCK_SetFroOutClkSrc(clock_fro_src_t src)
|
|
{
|
|
if ((uint32_t)src != (SYSCON->FROOSCCTRL & SYSCON_FROOSCCTRL_FRO_DIRECT_MASK))
|
|
{
|
|
SYSCON->FROOSCCTRL = (SYSCON->FROOSCCTRL & (~SYSCON_FROOSCCTRL_FRO_DIRECT_MASK)) | (uint32_t)src;
|
|
/* Update clock source */
|
|
CLOCK_UpdateClkSrc((volatile uint32_t *)(&(SYSCON->FRODIRECTCLKUEN)), SYSCON_FRODIRECTCLKUEN_ENA_MASK);
|
|
}
|
|
}
|