630 lines
21 KiB
C
630 lines
21 KiB
C
/*
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2020 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_i2c_dma.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.lpc_i2c_dma"
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#endif
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/*<! @brief Structure definition for i2c_master_dma_handle_t. The structure is private. */
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typedef struct _i2c_master_dma_private_handle
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{
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I2C_Type *base;
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i2c_master_dma_handle_t *handle;
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} i2c_master_dma_private_handle_t;
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/*******************************************************************************
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* Variables
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******************************************************************************/
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#if defined(FSL_SDK_ENABLE_I2C_DRIVER_TRANSACTIONAL_APIS) && (FSL_SDK_ENABLE_I2C_DRIVER_TRANSACTIONAL_APIS)
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/*! @brief Pointers to i2c handles for each instance. */
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static void *s_i2cHandle[FSL_FEATURE_SOC_I2C_COUNT];
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/*! @brief IRQ name array */
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static IRQn_Type const s_i2cIRQ[] = I2C_IRQS;
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/*! @brief Pointer to master IRQ handler for each instance. */
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static i2c_isr_t s_i2cMasterIsr;
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/*! @brief Pointer to slave IRQ handler for each instance. */
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static i2c_isr_t s_i2cSlaveIsr;
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#endif /* FSL_SDK_ENABLE_I2C_DRIVER_TRANSACTIONAL_APIS */
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief DMA callback for I2C master DMA driver.
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*
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* @param handle DMA handler for I2C master DMA driver
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* @param userData user param passed to the callback function
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*/
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static void I2C_MasterTransferCallbackDMA(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode);
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/*!
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* @brief Set up master transfer, send slave address and sub address(if any), wait until the
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* wait until address sent status return.
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*
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* @param base I2C peripheral base address.
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* @param handle pointer to i2c_master_dma_handle_t structure which stores the transfer state.
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* @param xfer pointer to i2c_master_transfer_t structure.
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*/
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static status_t I2C_InitTransferStateMachineDMA(I2C_Type *base,
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i2c_master_dma_handle_t *handle,
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i2c_master_transfer_t *xfer);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*<! Private handle only used for internally. */
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static i2c_master_dma_private_handle_t s_dmaPrivateHandle[FSL_FEATURE_SOC_I2C_COUNT];
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/*******************************************************************************
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* Codes
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******************************************************************************/
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/*!
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* @brief Prepares the transfer state machine and fills in the command buffer.
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* @param handle Master nonblocking driver handle.
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*/
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static status_t I2C_InitTransferStateMachineDMA(I2C_Type *base,
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i2c_master_dma_handle_t *handle,
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i2c_master_transfer_t *xfer)
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{
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struct _i2c_master_transfer *transfer;
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handle->transfer = *xfer;
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transfer = &(handle->transfer);
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handle->transferCount = 0;
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handle->remainingBytesDMA = 0;
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handle->buf = (uint8_t *)transfer->data;
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handle->remainingSubaddr = 0;
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if ((transfer->flags & (uint32_t)kI2C_TransferNoStartFlag) != 0U)
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{
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/* Start condition shall be ommited, switch directly to next phase */
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if (transfer->dataSize == 0U)
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{
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handle->state = (uint8_t)kStopState;
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}
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else if (handle->transfer.direction == kI2C_Write)
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{
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handle->state = (uint8_t)kTransmitDataState;
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}
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else if (handle->transfer.direction == kI2C_Read)
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{
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handle->state = (xfer->dataSize == 1U) ? (uint8_t)kReceiveLastDataState : (uint8_t)kReceiveDataState;
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}
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else
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{
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return kStatus_I2C_InvalidParameter;
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}
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}
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else
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{
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if (transfer->subaddressSize != 0U)
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{
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int i;
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uint32_t subaddress;
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if (transfer->subaddressSize > sizeof(handle->subaddrBuf))
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{
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return kStatus_I2C_InvalidParameter;
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}
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/* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */
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subaddress = xfer->subaddress;
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for (i = (int)xfer->subaddressSize - 1; i >= 0; i--)
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{
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handle->subaddrBuf[i] = (uint8_t)subaddress & 0xffU;
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subaddress >>= 8;
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}
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handle->remainingSubaddr = transfer->subaddressSize;
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}
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handle->state = (uint8_t)kStartState;
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}
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return kStatus_Success;
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}
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static void I2C_RunDMATransfer(I2C_Type *base, i2c_master_dma_handle_t *handle)
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{
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uint32_t transfer_size;
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dma_transfer_config_t xferConfig;
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uint32_t address;
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address = (uint32_t)&base->MSTDAT;
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/* Update transfer count */
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int32_t count = handle->buf - (uint8_t *)handle->transfer.data;
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assert(count >= 0);
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handle->transferCount = (uint32_t)count;
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/* Check if there is anything to be transferred at all */
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if (handle->remainingBytesDMA == 0U)
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{
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/* No data to be transferrred, disable DMA */
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base->MSTCTL = 0;
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return;
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}
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/* Calculate transfer size */
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transfer_size = handle->remainingBytesDMA;
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if (transfer_size > I2C_MAX_DMA_TRANSFER_COUNT)
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{
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transfer_size = I2C_MAX_DMA_TRANSFER_COUNT;
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}
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switch (handle->transfer.direction)
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{
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case kI2C_Write:
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DMA_PrepareTransfer(&xferConfig, handle->buf, (uint32_t *)address, sizeof(uint8_t), transfer_size,
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kDMA_MemoryToPeripheral, NULL);
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break;
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case kI2C_Read:
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DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, handle->buf, sizeof(uint8_t), transfer_size,
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kDMA_PeripheralToMemory, NULL);
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break;
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default:
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/* This should never happen */
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assert(false);
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break;
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}
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(void)DMA_SubmitTransfer(handle->dmaHandle, &xferConfig);
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DMA_StartTransfer(handle->dmaHandle);
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handle->remainingBytesDMA -= (uint32_t)transfer_size;
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handle->buf += transfer_size;
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}
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/*!
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* @brief Execute states until the transfer is done.
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* @param handle Master nonblocking driver handle.
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* @param[out] isDone Set to true if the transfer has completed.
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* @retval #kStatus_Success
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* @retval #kStatus_I2C_ArbitrationLost
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* @retval #kStatus_I2C_Nak
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*/
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static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, bool *isDone)
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{
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uint32_t status;
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uint32_t master_state;
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struct _i2c_master_transfer *transfer;
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dma_transfer_config_t xferConfig;
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status_t err;
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uint32_t start_flag = 0U;
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uint32_t address;
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address = (uint32_t)&base->MSTDAT;
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transfer = &(handle->transfer);
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*isDone = false;
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status = I2C_GetStatusFlags(base);
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if ((status & I2C_STAT_MSTARBLOSS_MASK) != 0U)
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{
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I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK);
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DMA_AbortTransfer(handle->dmaHandle);
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base->MSTCTL = 0;
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return kStatus_I2C_ArbitrationLost;
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}
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if ((status & I2C_STAT_MSTSTSTPERR_MASK) != 0U)
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{
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I2C_MasterClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK);
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DMA_AbortTransfer(handle->dmaHandle);
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base->MSTCTL = 0;
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return kStatus_I2C_StartStopError;
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}
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if ((status & I2C_STAT_MSTPENDING_MASK) == 0U)
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{
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return kStatus_I2C_Busy;
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}
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/* Get the state of the I2C module */
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master_state = (status & I2C_STAT_MSTSTATE_MASK) >> (uint32_t)I2C_STAT_MSTSTATE_SHIFT;
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if ((master_state == I2C_STAT_MSTCODE_NACKADR) || (master_state == I2C_STAT_MSTCODE_NACKDAT))
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{
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/* Slave NACKed last byte, issue stop and return error */
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DMA_AbortTransfer(handle->dmaHandle);
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base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
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handle->state = (uint8_t)kWaitForCompletionState;
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return kStatus_I2C_Nak;
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}
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err = kStatus_Success;
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if (handle->state == (uint8_t)kStartState)
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{
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/* set start flag for later use */
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start_flag = I2C_MSTCTL_MSTSTART_MASK;
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if (handle->remainingSubaddr != 0U)
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{
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base->MSTDAT = (uint32_t)transfer->slaveAddress << 1;
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handle->state = (uint8_t)kTransmitSubaddrState;
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}
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else if (transfer->direction == kI2C_Write)
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{
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base->MSTDAT = (uint32_t)transfer->slaveAddress << 1;
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if (transfer->dataSize == 0U)
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{
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/* No data to be transferred, initiate start and schedule stop */
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base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK;
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handle->state = (uint8_t)kStopState;
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return err;
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}
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handle->state = (uint8_t)kTransmitDataState;
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}
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else if ((transfer->direction == kI2C_Read) && (transfer->dataSize > 0U))
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{
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base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u;
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if (transfer->dataSize == 1U)
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{
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/* The very last byte is always received by means of SW */
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base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK;
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handle->state = (uint8_t)kReceiveLastDataState;
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return err;
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}
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handle->state = (uint8_t)kReceiveDataState;
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}
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else
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{
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handle->state = (uint8_t)kIdleState;
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err = kStatus_I2C_UnexpectedState;
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return err;
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}
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}
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switch (handle->state)
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{
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case (uint8_t)kTransmitSubaddrState:
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if ((master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) && (start_flag == 0U))
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{
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return kStatus_I2C_UnexpectedState;
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}
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base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK;
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/* Prepare and submit DMA transfer. */
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DMA_PrepareTransfer(&xferConfig, handle->subaddrBuf, (uint32_t *)address, sizeof(uint8_t),
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handle->remainingSubaddr, kDMA_MemoryToPeripheral, NULL);
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(void)DMA_SubmitTransfer(handle->dmaHandle, &xferConfig);
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DMA_StartTransfer(handle->dmaHandle);
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handle->remainingSubaddr = 0;
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if (transfer->dataSize != 0U)
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{
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/* There is data to be transferred, if there is write to read turnaround it is necessary to perform
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* repeated start */
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handle->state = (transfer->direction == kI2C_Read) ? (uint8_t)kStartState : (uint8_t)kTransmitDataState;
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}
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else
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{
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/* No more data, schedule stop condition */
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handle->state = (uint8_t)kStopState;
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}
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break;
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case (uint8_t)kTransmitDataState:
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if ((master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) && (start_flag == 0U))
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{
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return kStatus_I2C_UnexpectedState;
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}
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base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK;
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handle->remainingBytesDMA = handle->transfer.dataSize;
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I2C_RunDMATransfer(base, handle);
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/* Schedule stop condition */
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handle->state = (uint8_t)kStopState;
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break;
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case (uint8_t)kReceiveDataState:
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if ((master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY) && (start_flag == 0U))
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{
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if ((transfer->flags & (uint32_t)kI2C_TransferNoStartFlag) == 0U)
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{
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return kStatus_I2C_UnexpectedState;
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}
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}
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base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK;
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handle->remainingBytesDMA = (uint32_t)handle->transfer.dataSize - 1U;
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if ((transfer->flags & (uint32_t)kI2C_TransferNoStartFlag) != 0U)
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{
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/* Read the master data register to avoid the data be read again */
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(void)base->MSTDAT;
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}
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I2C_RunDMATransfer(base, handle);
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/* Schedule reception of last data byte */
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handle->state = (uint8_t)kReceiveLastDataState;
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break;
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case (uint8_t)kReceiveLastDataState:
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if (master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY)
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{
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return kStatus_I2C_UnexpectedState;
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}
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((uint8_t *)transfer->data)[transfer->dataSize - 1U] = (uint8_t)base->MSTDAT;
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handle->transferCount++;
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/* No more data expected, issue NACK and STOP right away */
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if ((transfer->flags & (uint32_t)kI2C_TransferNoStopFlag) == 0U)
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{
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base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
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}
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handle->state = (uint8_t)kWaitForCompletionState;
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break;
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case (uint8_t)kStopState:
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if ((transfer->flags & (uint32_t)kI2C_TransferNoStopFlag) != 0U)
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{
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/* Stop condition is omitted, we are done */
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*isDone = true;
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handle->state = (uint8_t)kIdleState;
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break;
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}
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/* Send stop condition */
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base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
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handle->state = (uint8_t)kWaitForCompletionState;
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break;
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case (uint8_t)kWaitForCompletionState:
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*isDone = true;
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handle->state = (uint8_t)kIdleState;
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break;
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case (uint8_t)kStartState:
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case (uint8_t)kIdleState:
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default:
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/* State machine shall not be invoked again once it enters the idle state */
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err = kStatus_I2C_UnexpectedState;
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break;
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}
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return err;
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}
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void I2C_MasterTransferDMAHandleIRQ(I2C_Type *base, void *i2cHandle)
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{
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assert(i2cHandle != NULL);
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bool isDone;
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status_t result;
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i2c_master_dma_handle_t *handle = (i2c_master_dma_handle_t *)i2cHandle;
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/* Don't do anything if we don't have a valid handle. */
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if (handle == NULL)
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{
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return;
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}
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result = I2C_RunTransferStateMachineDMA(base, handle, &isDone);
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if ((result != kStatus_Success) || isDone)
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{
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/* Restore handle to idle state. */
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handle->state = (uint8_t)kIdleState;
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/* Disable internal IRQ enables. */
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I2C_DisableInterrupts(base,
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I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK);
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/* Invoke callback. */
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if (handle->completionCallback != NULL)
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{
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handle->completionCallback(base, handle, result, handle->userData);
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}
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}
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}
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static void I2C_MasterTransferCallbackDMA(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode)
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{
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i2c_master_dma_private_handle_t *dmaPrivateHandle;
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/* Don't do anything if we don't have a valid handle. */
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if (handle == NULL)
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{
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return;
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}
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dmaPrivateHandle = (i2c_master_dma_private_handle_t *)userData;
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I2C_RunDMATransfer(dmaPrivateHandle->base, dmaPrivateHandle->handle);
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}
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/*!
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* brief Init the I2C handle which is used in transactional functions
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*
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* param base I2C peripheral base address
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* param handle pointer to i2c_master_dma_handle_t structure
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* param callback pointer to user callback function
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* param userData user param passed to the callback function
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* param dmaHandle DMA handle pointer
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*/
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void I2C_MasterTransferCreateHandleDMA(I2C_Type *base,
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i2c_master_dma_handle_t *handle,
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i2c_master_dma_transfer_callback_t callback,
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void *userData,
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dma_handle_t *dmaHandle)
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{
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uint32_t instance;
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assert(handle != NULL);
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assert(dmaHandle != NULL);
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/* Zero handle. */
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(void)memset(handle, 0, sizeof(*handle));
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/* Look up instance number */
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instance = I2C_GetInstance(base);
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/* Set the user callback and userData. */
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handle->completionCallback = callback;
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handle->userData = userData;
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/* Save the context in global variables to support the double weak mechanism. */
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s_i2cHandle[instance] = handle;
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/* Save master interrupt handler. */
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s_i2cMasterIsr = I2C_MasterTransferDMAHandleIRQ;
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/* Clear internal IRQ enables and enable NVIC IRQ. */
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I2C_DisableInterrupts(base,
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I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK);
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(void)EnableIRQ(s_i2cIRQ[instance]);
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/* Set the handle for DMA. */
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handle->dmaHandle = dmaHandle;
|
|
|
|
s_dmaPrivateHandle[instance].base = base;
|
|
s_dmaPrivateHandle[instance].handle = handle;
|
|
|
|
DMA_SetCallback(dmaHandle, I2C_MasterTransferCallbackDMA, &s_dmaPrivateHandle[instance]);
|
|
}
|
|
|
|
/*!
|
|
* brief Performs a master dma non-blocking transfer on the I2C bus
|
|
*
|
|
* param base I2C peripheral base address
|
|
* param handle pointer to i2c_master_dma_handle_t structure
|
|
* param xfer pointer to transfer structure of i2c_master_transfer_t
|
|
* retval kStatus_Success Sucessully complete the data transmission.
|
|
* retval kStatus_I2C_Busy Previous transmission still not finished.
|
|
* retval kStatus_I2C_Timeout Transfer error, wait signal timeout.
|
|
* retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
|
|
* retval kStataus_I2C_Nak Transfer error, receive Nak during transfer.
|
|
*/
|
|
status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer)
|
|
{
|
|
status_t result;
|
|
|
|
assert(handle != NULL);
|
|
assert(xfer != NULL);
|
|
assert(xfer->subaddressSize <= sizeof(xfer->subaddress));
|
|
|
|
/* Return busy if another transaction is in progress. */
|
|
if (handle->state != (uint8_t)kIdleState)
|
|
{
|
|
return kStatus_I2C_Busy;
|
|
}
|
|
|
|
/* Prepare transfer state machine. */
|
|
result = I2C_InitTransferStateMachineDMA(base, handle, xfer);
|
|
|
|
/* Clear error flags. */
|
|
I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK);
|
|
|
|
/* Enable I2C internal IRQ sources */
|
|
I2C_EnableInterrupts(base,
|
|
I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_MSTPENDING_MASK);
|
|
|
|
return result;
|
|
}
|
|
|
|
/*!
|
|
* brief Get master transfer status during a dma non-blocking transfer
|
|
*
|
|
* param base I2C peripheral base address
|
|
* param handle pointer to i2c_master_dma_handle_t structure
|
|
* param count Number of bytes transferred so far by the non-blocking transaction.
|
|
*/
|
|
status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count)
|
|
{
|
|
assert(handle != NULL);
|
|
|
|
if (count == NULL)
|
|
{
|
|
return kStatus_InvalidArgument;
|
|
}
|
|
|
|
/* Catch when there is not an active transfer. */
|
|
if (handle->state == (uint8_t)kIdleState)
|
|
{
|
|
*count = 0;
|
|
return kStatus_NoTransferInProgress;
|
|
}
|
|
|
|
/* There is no necessity to disable interrupts as we read a single integer value */
|
|
*count = handle->transferCount;
|
|
return kStatus_Success;
|
|
}
|
|
|
|
/*!
|
|
* brief Abort a master dma non-blocking transfer in a early time
|
|
*
|
|
* param base I2C peripheral base address
|
|
* param handle pointer to i2c_master_dma_handle_t structure
|
|
*/
|
|
void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle)
|
|
{
|
|
uint32_t status;
|
|
uint32_t master_state;
|
|
|
|
if (handle->state != (uint8_t)kIdleState)
|
|
{
|
|
DMA_AbortTransfer(handle->dmaHandle);
|
|
|
|
/* Disable DMA */
|
|
base->MSTCTL = 0;
|
|
|
|
/* Disable internal IRQ enables. */
|
|
I2C_DisableInterrupts(base,
|
|
I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK);
|
|
|
|
/* Wait until module is ready */
|
|
do
|
|
{
|
|
status = I2C_GetStatusFlags(base);
|
|
} while ((status & I2C_STAT_MSTPENDING_MASK) == 0U);
|
|
|
|
/* Clear controller state. */
|
|
I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK);
|
|
|
|
/* Get the state of the I2C module */
|
|
master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT;
|
|
|
|
if (master_state != (uint32_t)I2C_STAT_MSTCODE_IDLE)
|
|
{
|
|
/* Send a stop command to finalize the transfer. */
|
|
base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
|
|
|
|
/* Wait until module is ready */
|
|
do
|
|
{
|
|
status = I2C_GetStatusFlags(base);
|
|
} while ((status & I2C_STAT_MSTPENDING_MASK) == 0U);
|
|
|
|
/* Clear controller state. */
|
|
I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK);
|
|
}
|
|
|
|
/* Reset the state to idle. */
|
|
handle->state = (uint8_t)kIdleState;
|
|
}
|
|
}
|