168 lines
4.2 KiB
C
168 lines
4.2 KiB
C
/*
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2018, NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_power.h"
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.power_no_lib"
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#endif
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*******************************************************************************
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* Code
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******************************************************************************/
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/*!
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* brief API to enter sleep power mode.
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*
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* return none
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*/
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void POWER_EnterSleep(void)
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{
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uint32_t pmsk;
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pmsk = __get_PRIMASK();
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__disable_irq();
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/* sleep mode */
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PMU->PCON &= ~PMU_PCON_PM_MASK;
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/* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */
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SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
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/* Enter powerdown mode */
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__WFI();
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__set_PRIMASK(pmsk);
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}
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/*!
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* brief API to enter deep sleep power mode.
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*
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* param activePart: should be a single or combine value of _power_deep_sleep_active .
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* return none
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*/
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void POWER_EnterDeepSleep(uint32_t activePart)
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{
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assert((SYSCON->MAINCLKSEL & SYSCON_MAINCLKSEL_SEL_MASK) == 0U);
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uint32_t pmsk;
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pmsk = __get_PRIMASK();
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__disable_irq();
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PMU->PCON = (PMU->PCON & (~PMU_PCON_PM_MASK)) | PMU_PCON_PM(kPmu_Deep_Sleep);
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/* remain active during power down mode */
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SYSCON->PDSLEEPCFG &= ~activePart;
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/* enable Deepsleep mode in the ARM-CORTEX M0+ SCR register */
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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/* Enter powerdown mode */
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__WFI();
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/* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */
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SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
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__set_PRIMASK(pmsk);
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}
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/*!
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* brief API to enter power down mode.
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*
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* param activePart: should be a single or combine value of _power_deep_sleep_active .
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* return none
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*/
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void POWER_EnterPowerDown(uint32_t activePart)
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{
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assert((SYSCON->MAINCLKSEL & SYSCON_MAINCLKSEL_SEL_MASK) == 0U);
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uint32_t pmsk;
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pmsk = __get_PRIMASK();
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__disable_irq();
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PMU->PCON = (PMU->PCON & (~PMU_PCON_PM_MASK)) | PMU_PCON_PM(kPmu_PowerDown);
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/* remain active during power down mode */
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SYSCON->PDSLEEPCFG &= ~activePart;
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/* enable Deepsleep mode in the ARM-CORTEX M0+ SCR register */
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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/* Enter powerdown mode */
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__WFI();
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/* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */
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SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
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__set_PRIMASK(pmsk);
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}
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/*!
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* brief API to enter deep power down mode.
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*
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* return none
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*/
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void POWER_EnterDeepPowerDownMode(void)
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{
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uint32_t pmsk;
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pmsk = __get_PRIMASK();
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__disable_irq();
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/* make sure NODPD is cleared */
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PMU->PCON = (PMU->PCON & (~(PMU_PCON_PM_MASK | PMU_PCON_NODPD_MASK))) | PMU_PCON_PM(kPmu_Deep_PowerDown);
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/* enable Deepsleep mode in the ARM-CORTEX M0+ SCR register */
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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/* Enter powerdown mode */
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__WFI();
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/* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */
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SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
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__set_PRIMASK(pmsk);
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}
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void EnableDeepSleepIRQ(IRQn_Type interrupt)
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{
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uint32_t intNumber = (uint32_t)interrupt;
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if(intNumber >= 24u)
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{
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/* enable pin interrupt wake up in the STARTERP0 register */
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SYSCON->STARTERP0 |= 1UL << (intNumber - 24u);
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}
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else
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{
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/* enable interrupt wake up in the STARTERP1 register */
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SYSCON->STARTERP1 |= 1UL << intNumber;
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}
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/* also enable interrupt at NVIC */
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(void)EnableIRQ(interrupt);
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}
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void DisableDeepSleepIRQ(IRQn_Type interrupt)
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{
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uint32_t intNumber = (uint32_t)interrupt;
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/* also disable interrupt at NVIC */
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(void)DisableIRQ(interrupt);
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if(intNumber >= 24u)
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{
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/* disable pin interrupt wake up in the STARTERP0 register */
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SYSCON->STARTERP0 &= ~(1UL << (intNumber - 24u));
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}
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else
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{
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/* disable interrupt wake up in the STARTERP1 register */
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SYSCON->STARTERP1 &= ~(1UL << intNumber);
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}
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}
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