178 lines
7.0 KiB
C
178 lines
7.0 KiB
C
/*
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* Copyright 2017, NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _FSL_RESET_H_
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#define _FSL_RESET_H_
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#include <assert.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <string.h>
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#include "fsl_device_registers.h"
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/*!
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* @addtogroup reset
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* @{
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @name Driver version */
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/*@{*/
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/*! @brief reset driver version 2.0.1. */
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#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
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/*@}*/
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/*!
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* @brief Enumeration for peripheral reset control bits
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*
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* Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers
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*/
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typedef enum _SYSCON_RSTn
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{
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kFLASH_RST_N_SHIFT_RSTn = 0 | 4U, /**< Flash controller reset control */
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kI2C0_RST_N_SHIFT_RSTn = 0 | 5U, /**< I2C0 reset control */
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kGPIO0_RST_N_SHIFT_RSTn = 0 | 6U, /**< GPIO0 reset control */
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kSWM_RST_N_SHIFT_RSTn = 0 | 7U, /**< SWM reset control */
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kSCT_RST_N_SHIFT_RSTn = 0 | 8U, /**< SCT reset control */
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kWKT_RST_N_SHIFT_RSTn = 0 | 9U, /**< Self-wake-up timer(WKT) reset control */
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kMRT_RST_N_SHIFT_RSTn = 0 | 10U, /**< Multi-rate timer(MRT) reset control */
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kSPI0_RST_N_SHIFT_RSTn = 0 | 11U, /**< SPI0 reset control. */
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kSPI1_RST_N_SHIFT_RSTn = 0 | 12U, /**< SPI1 reset control */
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kCRC_RST_SHIFT_RSTn = 0 | 13U, /**< CRC reset control */
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kUART0_RST_N_SHIFT_RSTn = 0 | 14U, /**< UART0 reset control */
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kUART1_RST_N_SHIFT_RSTn = 0 | 15U, /**< UART1 reset control */
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kUART2_RST_N_SHIFT_RSTn = 0 | 16U, /**< UART2 reset control */
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kIOCON_RST_N_SHIFT_RSTn = 0 | 18U, /**< IOCON reset control */
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kACMP_RST_N_SHIFT_RSTn = 0 | 19U, /**< Analog comparator reset control */
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kGPIO1_RST_N_SHIFT_RSTn = 0 | 20U, /**< GPIO1 reset control */
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kI2C1_RST_N_SHIFT_RSTn = 0 | 21U, /**< I2C1 reset control */
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kI2C2_RST_N_SHIFT_RSTn = 0 | 22U, /**< I2C2 reset control */
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kI2C3_RST_N_SHIFT_RSTn = 0 | 23U, /**< I2C3 reset control */
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kADC_RST_N_SHIFT_RSTn = 0 | 24U, /**< ADC reset control */
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kCTIMER0_RST_N_SHIFT_RSTn = 0 | 25U, /**< CTIMER0 reset control */
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kDAC0_RST_N_SHIFT_RSTn = 0 | 27U, /**< DAC0 reset control */
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kGPIOINT_RST_N_SHIFT_RSTn = 0 | 28U, /**< GPIOINT reset control */
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kDMA_RST_N_SHIFT_RSTn = 0 | 29U, /**< DMA reset control */
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kUART3_RST_N_SHIFT_RSTn = 0 | 30U, /**< UART3 reset control */
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kUART4_RST_N_SHIFT_RSTn = 0 | 31U, /**< UART4 reset control */
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kCAPT_RST_N_SHIFT_RSTn = 65536 | 0U, /**< Capacitive Touch reset control */
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kDAC1_RST_N_SHIFT_RSTn = 65536 | 1U, /**< DAC1 reset control */
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kFRG0_RST_N_SHIFT_RSTn = 65536 | 3U, /**< Fractional baud rate generator 0 reset control */
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kFRG1_RST_N_SHIFT_RSTn = 65536 | 4U, /**< Fractional baud rate generator 1 reset control */
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} SYSCON_RSTn_t;
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/** Array initializers with peripheral reset bits **/
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#define FLASH_RSTS_N \
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{ \
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kFLASH_RST_N_SHIFT_RSTn \
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} /* Reset bits for Flash peripheral */
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#define I2C_RSTS_N \
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{ \
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kI2C0_RST_N_SHIFT_RSTn, kI2C1_RST_N_SHIFT_RSTn, kI2C2_RST_N_SHIFT_RSTn, kI2C3_RST_N_SHIFT_RSTn \
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} /* Reset bits for I2C peripheral */
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#define GPIO_RSTS_N \
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{ \
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kGPIO0_RST_N_SHIFT_RSTn, kGPIO1_RST_N_SHIFT_RSTn \
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} /* Reset bits for GPIO peripheral */
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#define SWM_RSTS_N \
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{ \
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kSWM_RST_N_SHIFT_RSTn \
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} /* Reset bits for SWM peripheral */
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#define SCT_RSTS_N \
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{ \
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kSCT_RST_N_SHIFT_RSTn \
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} /* Reset bits for SCT peripheral */
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#define WKT_RSTS_N \
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{ \
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kWKT_RST_N_SHIFT_RSTn \
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} /* Reset bits for WKT peripheral */
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#define MRT_RSTS_N \
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{ \
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kMRT_RST_N_SHIFT_RSTn \
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} /* Reset bits for MRT peripheral */
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#define SPI_RSTS_N \
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{ \
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kSPI0_RST_N_SHIFT_RSTn, kSPI1_RST_N_SHIFT_RSTn \
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} /* Reset bits for SPI peripheral */
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#define CRC_RSTS_N \
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{ \
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kCRC_RST_SHIFT_RSTn \
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} /* Reset bits for CRC peripheral */
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#define UART_RSTS_N \
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{ \
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kUART0_RST_N_SHIFT_RSTn, kUART1_RST_N_SHIFT_RSTn, kUART2_RST_N_SHIFT_RSTn, kUART3_RST_N_SHIFT_RSTn, \
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kUART4_RST_N_SHIFT_RSTn \
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} /* Reset bits for UART peripheral */
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#define IOCON_RSTS_N \
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{ \
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kIOCON_RST_N_SHIFT_RSTn \
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} /* Reset bits for IOCON peripheral */
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#define ACMP_RSTS_N \
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{ \
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kACMP_RST_N_SHIFT_RSTn \
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} /* Reset bits for ACMP peripheral */
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#define ADC_RSTS_N \
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{ \
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kADC_RST_N_SHIFT_RSTn \
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} /* Reset bits for ADC peripheral */
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#define CTIMER_RSTS_N \
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{ \
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kCTIMER0_RST_N_SHIFT_RSTn \
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} /* Reset bits for CTIMER peripheral */
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#define DAC_RSTS_N \
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{ \
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kDAC0_RST_N_SHIFT_RSTn, kDAC1_RST_N_SHIFT_RSTn \
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} /* Reset bits for DAC peripheral */
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#define GPIOINT_RSTS_N \
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{ \
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kGPIOINT_RST_N_SHIFT_RSTn \
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} /* Reset bits for GPIOINT peripheral */
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#define DMA_RSTS_N \
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{ \
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kDMA_RST_N_SHIFT_RSTn \
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} /* Reset bits for DMA peripheral */
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#define CAPT_RSTS_N \
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{ \
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kCAPT_RST_N_SHIFT_RSTn \
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} /* Reset bits for CAPT peripheral */
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#define FRG_RSTS_N \
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{ \
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kFRG0_RST_N_SHIFT_RSTn \
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} /* Reset bits for FRG peripheral */
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typedef SYSCON_RSTn_t reset_ip_name_t;
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/*******************************************************************************
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* API
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/*!
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* @brief Reset peripheral module.
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*
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* Reset peripheral module.
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*
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* @param peripheral Peripheral to reset. The enum argument contains encoding of reset register
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* and reset bit position in the reset register.
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*/
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void RESET_PeripheralReset(reset_ip_name_t peripheral);
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#if defined(__cplusplus)
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}
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#endif
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/*! @} */
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#endif /* _FSL_RESET_H_ */
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