nxp.com
MCXA153
1.0
MCXA153VFM,MCXA153VFT,MCXA153VLH
Copyright 2016-2023 NXP
SPDX-License-Identifier: BSD-3-Clause
CM33
r2p0
little
false
false
true
3
false
8
32
INPUTMUX0
INPUTMUX
INPUTMUX
0x40001000
0
0x664
registers
4
0x4
CTIMER0CAP[%s]
Capture select register for CTIMER inputs
0x20
32
read-write
0x7F
0xFFFFFFFF
INP
Input number for CTIMER0
0
7
read-write
val1
CT_INP0 input is selected
0x1
val2
CT_INP1 input is selected
0x2
val3
CT_INP2 input is selected
0x3
val4
CT_INP3 input is selected
0x4
val5
CT_INP4 input is selected
0x5
val6
CT_INP5 input is selected
0x6
val7
CT_INP6 input is selected
0x7
val8
CT_INP7 input is selected
0x8
val9
CT_INP8 input is selected
0x9
val10
CT_INP9 input is selected
0xA
val13
CT_INP12 input is selected
0xD
val14
CT_INP13 input is selected
0xE
val15
CT_INP14 input is selected
0xF
val16
CT_INP15 input is selected
0x10
val17
CT_INP16 input is selected
0x11
val18
CT_INP17 input is selected
0x12
val19
CT_INP18 input is selected
0x13
val20
CT_INP19 input is selected
0x14
val21
USB0 usb0 start of frame input is selected
0x15
val22
AOI0_OUT0 input is selected
0x16
val23
AOI0_OUT1 input is selected
0x17
val24
AOI0_OUT2 input is selected
0x18
val25
AOI0_OUT3 input is selected
0x19
val26
ADC0_tcomp[0] input is selected
0x1A
val27
ADC0_tcomp[1] input is selected
0x1B
val28
ADC0_tcomp[2] input is selected
0x1C
val29
ADC0_tcomp[3] input is selected
0x1D
val30
CMP0_OUT input is selected selected
0x1E
val31
CMP1_OUT input is selected selected
0x1F
val33
CTimer1_MAT1 input is selected
0x21
val34
CTimer1_MAT2 input is selected
0x22
val35
CTimer1_MAT3 input is selected
0x23
val36
CTimer2_MAT1 input is selected
0x24
val37
CTimer2_MAT2 input is selected
0x25
val38
CTimer2_MAT3 input is selected
0x26
val39
QDC0_CMP_FLAG0 input input is selected
0x27
val40
QDC0_CMP_FLAG1 input is selected
0x28
val41
QDC0_CMP_FLAG2 input is selected
0x29
val42
QDC0_CMP_FLAG3 input is selected
0x2A
val43
QDC0_POS_MATCH0 input is selected
0x2B
val44
PWM0_SM0_OUT_TRIG0 input is selected
0x2C
val45
PWM0_SM1_OUT_TRIG0 input is selected
0x2D
val46
PWM0_SM2_OUT_TRIG0 input is selected
0x2E
val48
LPI2C0 Master End of Packet input is selected
0x30
val49
LPI2C0 Slave End of Packet input is selected
0x31
val52
LPSPI0 End of Frame input is selected
0x34
val53
LPSPI0 Received Data Word input is selected
0x35
val54
LPSPI1 End of Frame input is selected
0x36
val55
LPSPI1 Received Data Word input is selected
0x37
val56
LPUART0 Received Data Word input is selected
0x38
val57
LPUART0 Transmitted Data Word input is selected
0x39
val58
LPUART0 Receive Line Idle input is selected
0x3A
val59
LPUART1 Received Data Word input is selected
0x3B
val60
LPUART1 Transmitted Data Word input is selected
0x3C
val61
LPUART1 Receive Line Idle input is selected
0x3D
val62
LPUART2 Received Data Word input is selected
0x3E
val63
LPUART2 Transmitted Data Word input is selected
0x3F
val64
LPUART2 Receive Line Idle input is selected
0x40
TIMER0TRIG
Trigger register for TIMER0
0x30
32
read-write
0x7F
0xFFFFFFFF
INP
Input number for CTIMER0
0
7
read-write
val1
CT_INP0 input is selected
0x1
val2
CT_INP1 input is selected
0x2
val3
CT_INP2 input is selected
0x3
val4
CT_INP3 input is selected
0x4
val5
CT_INP4 input is selected
0x5
val6
CT_INP5 input is selected
0x6
val7
CT_INP6 input is selected
0x7
val8
CT_INP7 input is selected
0x8
val9
CT_INP8 input is selected
0x9
val10
CT_INP9 input is selected
0xA
val13
CT_INP12 input is selected
0xD
val14
CT_INP13 input is selected
0xE
val15
CT_INP14 input is selected
0xF
val16
CT_INP15 input is selected
0x10
val17
CT_INP16 input is selected
0x11
val18
CT_INP17 input is selected
0x12
val19
CT_INP18 input is selected
0x13
val20
CT_INP19 input is selected
0x14
val21
USB0 usb0 start of frame input is selected
0x15
val22
AOI0_OUT0 input is selected
0x16
val23
AOI0_OUT1 input is selected
0x17
val24
AOI0_OUT2 input is selected
0x18
val25
AOI0_OUT3 input is selected
0x19
val26
ADC0_tcomp[0] input is selected
0x1A
val27
ADC0_tcomp[1] input is selected
0x1B
val28
ADC0_tcomp[2] input is selected
0x1C
val29
ADC0_tcomp[3] input is selected
0x1D
val30
CMP0_OUT input is selected selected
0x1E
val31
CMP1_OUT input is selected selected
0x1F
val33
CTimer1_MAT1 input is selected
0x21
val34
CTimer1_MAT2 input is selected
0x22
val35
CTimer1_MAT3 input is selected
0x23
val36
CTimer2_MAT1 input is selected
0x24
val37
CTimer2_MAT2 input is selected
0x25
val38
CTimer2_MAT3 input is selected
0x26
val39
QDC0_CMP_FLAG0 input is selected
0x27
val40
QDC0_CMP_FLAG1 input is selected
0x28
val41
QDC0_CMP_FLAG2 input is selected
0x29
val42
QDC0_CMP_FLAG3 input is selected
0x2A
val43
QDC0_POS_MATCH0 input is selected
0x2B
val44
PWM0_SM0_OUT_TRIG0 input is selected
0x2C
val45
PWM0_SM1_OUT_TRIG0 input is selected
0x2D
val46
PWM0_SM2_OUT_TRIG0 input is selected
0x2E
val48
LPI2C0 Master End of Packet input is selected
0x30
val49
LPI2C0 Slave End of Packet input is selected
0x31
val52
LPSPI0 End of Frame input is selected
0x34
val53
LPSPI0 Received Data Word input is selected
0x35
val54
LPSPI1 End of Frame input is selected
0x36
val55
LPSPI1 Received Data Word input is selected
0x37
val56
LPUART0 Received Data Word input is selected
0x38
val57
LPUART0 Transmitted Data Word input is selected
0x39
val58
LPUART0 Receive Line Idle input is selected
0x3A
val59
LPUART1 Received Data Word input is selected
0x3B
val60
LPUART1 Transmitted Data Word input is selected
0x3C
val61
LPUART1 Receive Line Idle input is selected
0x3D
val62
LPUART2 Received Data Word input is selected
0x3E
val63
LPUART2 Transmitted Data Word input is selected
0x3F
val64
LPUART2 Receive Line Idle input is selected
0x40
4
0x4
CTIMER1CAP[%s]
Capture select register for CTIMER inputs
0x40
32
read-write
0x7F
0xFFFFFFFF
INP
Input number for CTIMER0
0
7
read-write
val1
CT_INP0 input is selected
0x1
val2
CT_INP1 input is selected
0x2
val3
CT_INP2 input is selected
0x3
val4
CT_INP3 input is selected
0x4
val5
CT_INP4 input is selected
0x5
val6
CT_INP5 input is selected
0x6
val7
CT_INP6 input is selected
0x7
val8
CT_INP7 input is selected
0x8
val9
CT_INP8 input is selected
0x9
val10
CT_INP9 input is selected
0xA
val13
CT_INP12 input is selected
0xD
val14
CT_INP13 input is selected
0xE
val15
CT_INP14 input is selected
0xF
val16
CT_INP15 input is selected
0x10
val17
CT_INP16 input is selected
0x11
val18
CT_INP17 input is selected
0x12
val19
CT_INP18 input is selected
0x13
val20
CT_INP19 input is selected
0x14
val21
USB0 usb0 start of frame input is selected
0x15
val22
AOI0_OUT0 input is selected
0x16
val23
AOI0_OUT1 input is selected
0x17
val24
AOI0_OUT2 input is selected
0x18
val25
AOI0_OUT3 input is selected
0x19
val26
ADC0_tcomp[0] input is selected
0x1A
val27
ADC0_tcomp[1] input is selected
0x1B
val28
ADC0_tcomp[2] input is selected
0x1C
val29
ADC0_tcomp[3] input is selected
0x1D
val30
CMP0_OUT input is selected
0x1E
val31
CMP1_OUT input is selected
0x1F
val33
CTimer0_MAT1 input is selected
0x21
val34
CTimer0_MAT2 input is selected
0x22
val35
CTimer0_MAT3 input is selected
0x23
val36
CTimer2_MAT1 input is selected
0x24
val37
CTimer2_MAT2 input is selected
0x25
val38
CTimer2_MAT3 input is selected
0x26
val39
QDC0_CMP_FLAG0 input is selected
0x27
val40
QDC0_CMP_FLAG1 input is selected
0x28
val41
QDC0_CMP_FLAG2 input is selected
0x29
val42
QDC0_CMP_FLAG3 input is selected
0x2A
val43
QDC0_POS_MATCH0 input is selected
0x2B
val44
PWM0_SM0_OUT_TRIG0 input is selected
0x2C
val45
PWM0_SM1_OUT_TRIG0 input is selected
0x2D
val46
PWM0_SM2_OUT_TRIG0 input is selected
0x2E
val48
LPI2C0 Master End of Packet input is selected
0x30
val49
LPI2C0 Slave End of Packet input is selected
0x31
val52
LPSPI0 End of Frame input is selected
0x34
val53
LPSPI0 Received Data Word input is selected
0x35
val54
LPSPI1 End of Frame input is selected
0x36
val55
LPSPI1 Received Data Word input is selected
0x37
val56
LPUART0 Received Data Word input is selected
0x38
val57
LPUART0 Transmitted Data Word input is selected
0x39
val58
LPUART0 Receive Line Idle input is selected
0x3A
val59
LPUART1 Received Data Word input is selected
0x3B
val60
LPUART1 Transmitted Data Word input is selected
0x3C
val61
LPUART1 Receive Line Idle input is selected
0x3D
val62
LPUART2 Received Data Word input is selected
0x3E
val63
LPUART2 Transmitted Data Word input is selected
0x3F
val64
LPUART2 Receive Line Idle input is selected
0x40
TIMER1TRIG
Trigger register for TIMER1
0x50
32
read-write
0x7F
0xFFFFFFFF
INP
Input number for CTIMER0
0
7
read-write
val1
CT_INP0 input is selected
0x1
val2
CT_INP1 input is selected
0x2
val3
CT_INP2 input is selected
0x3
val4
CT_INP3 input is selected
0x4
val5
CT_INP4 input is selected
0x5
val6
CT_INP5 input is selected
0x6
val7
CT_INP6 input is selected
0x7
val8
CT_INP7 input is selected
0x8
val9
CT_INP8 input is selected
0x9
val10
CT_INP9 input is selected
0xA
val13
CT_INP12 input is selected
0xD
val14
CT_INP13 input is selected
0xE
val15
CT_INP14 input is selected
0xF
val16
CT_INP15 input is selected
0x10
val17
CT_INP16 input is selected
0x11
val18
CT_INP17 input is selected
0x12
val19
CT_INP18 input is selected
0x13
val20
CT_INP19 input is selected
0x14
val21
USB0 usb0 start of frame input is selected
0x15
val22
AOI0_OUT0 input is selected
0x16
val23
AOI0_OUT1 input is selected
0x17
val24
AOI0_OUT2 input is selected
0x18
val25
AOI0_OUT3 input is selected
0x19
val26
ADC0_tcomp[0] input is selected
0x1A
val27
ADC0_tcomp[1] input is selected
0x1B
val28
ADC0_tcomp[2] input is selected
0x1C
val29
ADC0_tcomp[3] input is selected
0x1D
val30
CMP0_OUT input is selected
0x1E
val31
CMP1_OUT input is selected
0x1F
val33
CTimer0_MAT1 input is selected
0x21
val34
CTimer0_MAT2 input is selected
0x22
val35
CTimer0_MAT3 input is selected
0x23
val36
CTimer2_MAT1 input is selected
0x24
val37
CTimer2_MAT2 input is selected
0x25
val38
CTimer2_MAT3 input is selected
0x26
val39
QDC0_CMP_FLAG0 input is selected
0x27
val40
QDC0_CMP_FLAG1 input is selected
0x28
val41
QDC0_CMP_FLAG2 input is selected
0x29
val42
QDC0_CMP_FLAG3 input is selected
0x2A
val43
QDC0_POS_MATCH0 input is selected
0x2B
val44
PWM0_SM0_OUT_TRIG0 input is selected
0x2C
val45
PWM0_SM1_OUT_TRIG0 input is selected
0x2D
val46
PWM0_SM2_OUT_TRIG0 input is selected
0x2E
val48
LPI2C0 Master End of Packet input is selected
0x30
val49
LPI2C0 Slave End of Packet input is selected
0x31
val52
LPSPI0 End of Frame input is selected
0x34
val53
LPSPI0 Received Data Word input is selected
0x35
val54
LPSPI1 End of Frame input is selected
0x36
val55
LPSPI1 Received Data Word input is selected
0x37
val56
LPUART0 Received Data Word input is selected
0x38
val57
LPUART0 Transmitted Data Word input is selected
0x39
val58
LPUART0 Receive Line Idle input is selected
0x3A
val59
LPUART1 Received Data Word input is selected
0x3B
val60
LPUART1 Transmitted Data Word input is selected
0x3C
val61
LPUART1 Receive Line Idle input is selected
0x3D
val62
LPUART2 Received Data Word input is selected
0x3E
val63
LPUART2 Transmitted Data Word input is selected
0x3F
val64
LPUART2 Receive Line Idle input is selected
0x40
4
0x4
CTIMER2CAP[%s]
Capture select register for CTIMER inputs
0x60
32
read-write
0x7F
0xFFFFFFFF
INP
Input number for CTIMER0
0
7
read-write
val1
CT_INP0 input is selected
0x1
val2
CT_INP1 input is selected
0x2
val3
CT_INP2 input is selected
0x3
val4
CT_INP3 input is selected
0x4
val5
CT_INP4 input is selected
0x5
val6
CT_INP5 input is selected
0x6
val7
CT_INP6 input is selected
0x7
val8
CT_INP7 input is selected
0x8
val9
CT_INP8 input is selected
0x9
val10
CT_INP9 input is selected
0xA
val13
CT_INP12 input is selected
0xD
val14
CT_INP13 input is selected
0xE
val15
CT_INP14 input is selected
0xF
val16
CT_INP15 input is selected
0x10
val17
CT_INP16 input is selected
0x11
val18
CT_INP17 input is selected
0x12
val19
CT_INP18 input is selected
0x13
val20
CT_INP19 input is selected
0x14
val21
USB0 usb0 start of frame input is selected
0x15
val22
AOI0_OUT0 input is selected
0x16
val23
AOI0_OUT1 input is selected
0x17
val24
AOI0_OUT2 input is selected
0x18
val25
AOI0_OUT3 input is selected
0x19
val26
ADC0_tcomp[0] input is selected
0x1A
val27
ADC0_tcomp[1] input is selected
0x1B
val28
ADC0_tcomp[2] input is selected
0x1C
val29
ADC0_tcomp[3] input is selected
0x1D
val30
CMP0_OUT input is selected
0x1E
val31
CMP1_OUT input is selected
0x1F
val33
CTimer0_MAT1 input is selected
0x21
val34
CTimer0_MAT2 input is selected
0x22
val35
CTimer0_MAT3 input is selected
0x23
val36
CTimer1_MAT1 input is selected
0x24
val37
CTimer1_MAT2 input is selected
0x25
val38
CTimer1_MAT3 input is selected
0x26
val39
QDC0_CMP_FLAG0 input is selected
0x27
val40
QDC0_CMP_FLAG1 input is selected
0x28
val41
QDC0_CMP_FLAG2 input is selected
0x29
val42
QDC0_CMP_FLAG3 input is selected
0x2A
val43
QDC0_POS_MATCH0 input is selected
0x2B
val44
PWM0_SM0_OUT_TRIG0 input is selected
0x2C
val45
PWM0_SM1_OUT_TRIG0 input is selected
0x2D
val46
PWM0_SM2_OUT_TRIG0 input is selected
0x2E
val48
LPI2C0 Master End of Packet input is selected
0x30
val49
LPI2C0 Slave End of Packet input is selected
0x31
val52
LPSPI0 End of Frame input is selected
0x34
val53
LPSPI0 Received Data Word input is selected
0x35
val54
LPSPI1 End of Frame input is selected
0x36
val55
LPSPI1 Received Data Word input is selected
0x37
val56
LPUART0 Received Data Word input is selected
0x38
val57
LPUART0 Transmitted Data Word input is selected
0x39
val58
LPUART0 Receive Line Idle input is selected
0x3A
val59
LPUART1 Received Data Word input is selected
0x3B
val60
LPUART1 Transmitted Data Word input is selected
0x3C
val61
LPUART1 Receive Line Idle input is selected
0x3D
val62
LPUART2 Received Data Word input is selected
0x3E
val63
LPUART2 Transmitted Data Word input is selected
0x3F
val64
LPUART2 Receive Line Idle input is selected
0x40
TIMER2TRIG
Trigger register for TIMER2 inputs
0x70
32
read-write
0x7F
0xFFFFFFFF
INP
Input number for CTIMER0
0
7
read-write
val1
CT_INP0 input is selected
0x1
val2
CT_INP1 input is selected
0x2
val3
CT_INP2 input is selected
0x3
val4
CT_INP3 input is selected
0x4
val5
CT_INP4 input is selected
0x5
val6
CT_INP5 input is selected
0x6
val7
CT_INP6 input is selected
0x7
val8
CT_INP7 input is selected
0x8
val9
CT_INP8 input is selected
0x9
val10
CT_INP9 input is selected
0xA
val13
CT_INP12 input is selected
0xD
val14
CT_INP13 input is selected
0xE
val15
CT_INP14 input is selected
0xF
val16
CT_INP15 input is selected
0x10
val17
CT_INP16 input is selected
0x11
val18
CT_INP17 input is selected
0x12
val19
CT_INP18 input is selected
0x13
val20
CT_INP19 input is selected
0x14
val21
USB0 usb0 start of frame input is selected
0x15
val22
AOI0_OUT0 input is selected
0x16
val23
AOI0_OUT1 input is selected
0x17
val24
AOI0_OUT2 input is selected
0x18
val25
AOI0_OUT3 input is selected
0x19
val26
ADC0_tcomp[0] input is selected
0x1A
val27
ADC0_tcomp[1] input is selected
0x1B
val28
ADC0_tcomp[2] input is selected
0x1C
val29
ADC0_tcomp[3] input is selected
0x1D
val30
CMP0_OUT input is selected selected
0x1E
val31
CMP1_OUT input is selected selected
0x1F
val33
CTimer0_MAT1 input is selected
0x21
val34
CTimer0_MAT2 input is selected
0x22
val35
CTimer0_MAT3 input is selected
0x23
val36
CTimer1_MAT1 input is selected
0x24
val37
CTimer1_MAT2 input is selected
0x25
val38
CTimer1_MAT3 input is selected
0x26
val39
QDC0_CMP_FLAG0 input is selected
0x27
val40
QDC0_CMP_FLAG1 input is selected
0x28
val41
QDC0_CMP_FLAG2 input is selected
0x29
val42
QDC0_CMP_FLAG3 input is selected
0x2A
val43
QDC0_POS_MATCH0 input is selected
0x2B
val44
PWM0_SM0_OUT_TRIG0 input is selected
0x2C
val45
PWM0_SM1_OUT_TRIG0 input is selected
0x2D
val46
PWM0_SM2_OUT_TRIG0 input is selected
0x2E
val48
LPI2C0 Master End of Packet input is selected
0x30
val49
LPI2C0 Slave End of Packet input is selected
0x31
val52
LPSPI0 End of Frame input is selected
0x34
val53
LPSPI0 Received Data Word input is selected
0x35
val54
LPSPI1 End of Frame input is selected
0x36
val55
LPSPI1 Received Data Word input is selected
0x37
val56
LPUART0 Received Data Word input is selected
0x38
val57
LPUART0 Transmitted Data Word input is selected
0x39
val58
LPUART0 Receive Line Idle input is selected
0x3A
val59
LPUART1 Received Data Word input is selected
0x3B
val60
LPUART1 Transmitted Data Word input is selected
0x3C
val61
LPUART1 Receive Line Idle input is selected
0x3D
val62
LPUART2 Received Data Word input is selected
0x3E
val63
LPUART2 Transmitted Data Word input is selected
0x3F
val64
LPUART2 Receive Line Idle input is selected
0x40
FREQMEAS_REF
Selection for frequency measurement reference clock
0x180
32
read-write
0x1F
0xFFFFFFFF
INP
Clock source number (binary value) for frequency measure function target clock.
0
5
read-write
val1
clk_in input is selected
0x1
val2
FRO_OSC_12M input is selected
0x2
val3
fro_hf_div input is selected
0x3
val5
clk_16k[1] input is selected
0x5
val6
SLOW_CLK input is selected
0x6
val7
FREQME_CLK_IN0 input is selected
0x7
val8
FREQME_CLK_IN1 input is selected
0x8
val9
AOI0_OUT0 input is selected
0x9
val10
AOI0_OUT1 input is selected
0xA
val11
PWM0_SM0_OUT_TRIG0 input is selected
0xB
val12
PWM0_SM0_OUT_TRIG1 input is selected
0xC
val13
PWM0_SM1_OUT_TRIG0 input is selected
0xD
val14
PWM0_SM1_OUT_TRIG1 input is selected
0xE
val15
PWM0_SM2_OUT_TRIG0 input is selected
0xF
val16
PWM0_SM2_OUT_TRIG1 input is selected
0x10
FREQMEAS_TAR
Selection for frequency measurement reference clock
0x184
32
read-write
0x1F
0xFFFFFFFF
INP
Clock source number (binary value) for frequency measure function target clock.
0
5
read-write
val1
clk_in input is selected
0x1
val2
FRO_OSC_12M input is selected
0x2
val3
fro_hf_div input is selected
0x3
val5
clk_16k[1] input is selected
0x5
val6
SLOW_CLK input is selected
0x6
val7
FREQME_CLK_IN0 input is selected
0x7
val8
FREQME_CLK_IN1 input is selected
0x8
val9
AOI0_OUT0 input is selected
0x9
val10
AOI0_OUT1 input is selected
0xA
val11
PWM0_SM0_OUT_TRIG0 input is selected
0xB
val12
PWM0_SM0_OUT_TRIG1 input is selected
0xC
val13
PWM0_SM1_OUT_TRIG0 input is selected
0xD
val14
PWM0_SM1_OUT_TRIG1 input is selected
0xE
val15
PWM0_SM2_OUT_TRIG0 input is selected
0xF
val16
PWM0_SM2_OUT_TRIG1 input is selected
0x10
CMP0_TRIG
CMP0 input connections
0x260
32
read-write
0x3F
0xFFFFFFFF
TRIGIN
CMP0 input trigger
0
6
read-write
val1
ARM_TXEV input is selected
0x1
val2
AOI0_OUT0 input is selected
0x2
val3
AOI0_OUT1 input is selected
0x3
val4
AOI0_OUT2 input is selected
0x4
val5
AOI0_OUT3 input is selected
0x5
val6
CMP1_OUT input is selected
0x6
val8
CTimer0_MAT0 input is selected
0x8
val9
CTimer0_MAT2 input is selected
0x9
val10
CTimer1_MAT0 input is selected
0xA
val11
CTimer1_MAT2 input is selected
0xB
val12
CTimer2_MAT0 input is selected
0xC
val13
CTimer2_MAT2 input is selected
0xD
val14
LPTMR0 input is selected
0xE
val16
QDC0_POS_MATCH0
0x10
val17
PWM0_SM0_OUT_TRIG0 input is selected
0x11
val18
PWM0_SM0_OUT_TRIG1 input is selected
0x12
val19
PWM0_SM1_OUT_TRIG0 input is selected
0x13
val20
PWM0_SM1_OUT_TRIG1 input is selected
0x14
val21
PWM0_SM2_OUT_TRIG0 input is selected
0x15
val22
PWM0_SM2_OUT_TRIG1 input is selected
0x16
val25
GPIO0 Pin Event Trig 0 input is selected
0x19
val26
GPIO1 Pin Event Trig 0 input is selected
0x1A
val27
GPIO2 Pin Event Trig 0 input is selected
0x1B
val28
GPIO3 Pin Event Trig 0 input is selected
0x1C
val30
WUU input is selected
0x1E
4
0x4
ADC0_TRIG[%s]
ADC Trigger input connections
0x280
32
read-write
0x3F
0xFFFFFFFF
TRIGIN
ADC0 trigger inputs
0
6
read-write
val1
ARM_TXEV input is selected
0x1
val2
AOI0_OUT0 input is selected
0x2
val3
AOI0_OUT1 input is selected
0x3
val4
AOI0_OUT2 input is selected
0x4
val5
AOI0_OUT3 input is selected
0x5
val6
CMP0_OUT input is selected
0x6
val7
CMP1_OUT input is selected
0x7
val9
CTimer0_MAT0 input is selected
0x9
val10
CTimer0_MAT1 input is selected
0xA
val11
CTimer1_MAT0 input is selected
0xB
val12
CTimer1_MAT1 input is selected
0xC
val13
CTimer2_MAT0 input is selected
0xD
val14
CTimer2_MAT1 input is selected
0xE
val15
LPTMR0 input is selected
0xF
val17
QDC0_POS_MATCH0 input is selected
0x11
val18
PWM0_SM0_OUT_TRIG0 input is selected
0x12
val19
PWM0_SM0_OUT_TRIG1 input is selected
0x13
val20
PWM0_SM1_OUT_TRIG0 input is selected
0x14
val21
PWM0_SM1_OUT_TRIG1 input is selected
0x15
val22
PWM0_SM2_OUT_TRIG0 input is selected
0x16
val23
PWM0_SM2_OUT_TRIG1 input is selected
0x17
val26
GPIO0 Pin Event Trig 0 input is selected
0x1A
val27
GPIO1 Pin Event Trig 0 input is selected
0x1B
val28
GPIO2 Pin Event Trig 0 input is selected
0x1C
val29
GPIO3 Pin Event Trig 0 input is selected
0x1D
val31
WUU
0x1F
QDC0_TRIG
QDC0 Trigger Input Connections
0x360
32
read-write
0x3F
0xFFFFFFFF
INP
QDC0 input connections
0
6
read-write
val1
ARM_TXEV input is selected
0x1
val2
AOI0_OUT0 input is selected
0x2
val3
AOI0_OUT1 input is selected
0x3
val4
AOI0_OUT2 input is selected
0x4
val5
AOI0_OUT3 input is selected
0x5
val6
CMP0_OUT input is selected
0x6
val7
CMP1_OUT input is selected
0x7
val9
CTimer0_MAT2 input is selected
0x9
val10
CTimer0_MAT3 input is selected
0xA
val11
CTimer1_MAT2 input is selected
0xB
val12
CTimer1_MAT3 input is selected
0xC
val13
CTimer2_MAT2 input is selected
0xD
val14
CTimer2_MAT3 input is selected
0xE
val15
QDC0_POS_MATCH0 input is selected
0xF
val16
PWM0_SM0_OUT_TRIG0 input is selected
0x10
val17
PWM0_SM0_OUT_TRIG1 input is selected
0x11
val18
PWM0_SM1_OUT_TRIG0 input is selected
0x12
val19
PWM0_SM1_OUT_TRIG1 input is selected
0x13
val20
PWM0_SM2_OUT_TRIG0 input is selected
0x14
val21
PWM0_SM2_OUT_TRIG1 input is selected
0x15
val24
TRIG_IN0 input is selected
0x18
val25
TRIG_IN1 input is selected
0x19
val26
TRIG_IN2 input is selected
0x1A
val27
TRIG_IN3 input is selected
0x1B
val28
TRIG_IN4 input is selected
0x1C
val29
TRIG_IN5 input is selected
0x1D
val30
TRIG_IN6 input is selected
0x1E
val31
TRIG_IN7 input is selected
0x1F
val32
TRIG_IN8 input is selected
0x20
val33
TRIG_IN9 input is selected
0x21
val34
TRIG_IN10 input is selected
0x22
val35
TRIG_IN11 input is selected
0x23
val36
GPIO0 Pin Event Trig 0 input is selected
0x24
val37
GPIO1 Pin Event Trig 0 input is selected
0x25
val38
GPIO2 Pin Event Trig 0 input is selected
0x26
val39
GPIO3 Pin Event Trig 0 input is selected
0x27
QDC0_HOME
QDC0 Trigger Input Connections
0x364
32
read-write
0x3F
0xFFFFFFFF
INP
QDC0 input connections
0
6
read-write
val1
ARM_TXEV input is selected
0x1
val2
AOI0_OUT0 input is selected
0x2
val3
AOI0_OUT1 input is selected
0x3
val4
AOI0_OUT2 input is selected
0x4
val5
AOI0_OUT3 input is selected
0x5
val6
CMP0_OUT input is selected
0x6
val7
CMP1_OUT input is selected
0x7
val9
CTimer0_MAT2 input is selected
0x9
val10
CTimer0_MAT3 input is selected
0xA
val11
CTimer1_MAT2 input is selected
0xB
val12
CTimer1_MAT3 input is selected
0xC
val13
CTimer2_MAT2 input is selected
0xD
val14
CTimer2_MAT3 input is selected
0xE
val15
QDC0_POS_MATCH0 input is selected
0xF
val16
PWM0_SM0_OUT_TRIG0 input is selected
0x10
val17
PWM0_SM0_OUT_TRIG1 input is selected
0x11
val18
PWM0_SM1_OUT_TRIG0 input is selected
0x12
val19
PWM0_SM1_OUT_TRIG1 input is selected
0x13
val20
PWM0_SM2_OUT_TRIG0 input is selected
0x14
val21
PWM0_SM2_OUT_TRIG1 input is selected
0x15
val24
TRIG_IN0 input is selected
0x18
val25
TRIG_IN1 input is selected
0x19
val26
TRIG_IN2 input is selected
0x1A
val27
TRIG_IN3 input is selected
0x1B
val28
TRIG_IN4 input is selected
0x1C
val29
TRIG_IN5 input is selected
0x1D
val30
TRIG_IN6 input is selected
0x1E
val31
TRIG_IN7 input is selected
0x1F
val32
TRIG_IN8 input is selected
0x20
val33
TRIG_IN9 input is selected
0x21
val34
TRIG_IN10 input is selected
0x22
val35
TRIG_IN11 input is selected
0x23
val36
GPIO0 Pin Event Trig 0 input is selected
0x24
val37
GPIO1 Pin Event Trig 0 input is selected
0x25
val38
GPIO2 Pin Event Trig 0 input is selected
0x26
val39
GPIO3 Pin Event Trig 0 input is selected
0x27
QDC0_INDEX
QDC0 Trigger Input Connections
0x368
32
read-write
0x3F
0xFFFFFFFF
INP
QDC0 input connections
0
6
read-write
val1
ARM_TXEV input is selected
0x1
val2
AOI0_OUT0 input is selected
0x2
val3
AOI0_OUT1 input is selected
0x3
val4
AOI0_OUT2 input is selected
0x4
val5
AOI0_OUT3 input is selected
0x5
val6
CMP0_OUT input is selected
0x6
val7
CMP1_OUT input is selected
0x7
val9
CTimer0_MAT2 input is selected
0x9
val10
CTimer0_MAT3 input is selected
0xA
val11
CTimer1_MAT2 input is selected
0xB
val12
CTimer1_MAT3 input is selected
0xC
val13
CTimer2_MAT2 input is selected
0xD
val14
CTimer2_MAT3 input is selected
0xE
val15
QDC0_POS_MATCH0 input is selected
0xF
val16
PWM0_SM0_OUT_TRIG0 input is selected
0x10
val17
PWM0_SM0_OUT_TRIG1 input is selected
0x11
val18
PWM0_SM1_OUT_TRIG0 input is selected
0x12
val19
PWM0_SM1_OUT_TRIG1 input is selected
0x13
val20
PWM0_SM2_OUT_TRIG0 input is selected
0x14
val21
PWM0_SM2_OUT_TRIG1 input is selected
0x15
val24
TRIG_IN0 input is selected
0x18
val25
TRIG_IN1 input is selected
0x19
val26
TRIG_IN2 input is selected
0x1A
val27
TRIG_IN3 input is selected
0x1B
val28
TRIG_IN4 input is selected
0x1C
val29
TRIG_IN5 input is selected
0x1D
val30
TRIG_IN6 input is selected
0x1E
val31
TRIG_IN7 input is selected
0x1F
val32
TRIG_IN8 input is selected
0x20
val33
TRIG_IN9 input is selected
0x21
val34
TRIG_IN10 input is selected
0x22
val35
TRIG_IN11 input is selected
0x23
val36
GPIO0 Pin Event Trig 0 input is selected
0x24
val37
GPIO1 Pin Event Trig 0 input is selected
0x25
val38
GPIO2 Pin Event Trig 0 input is selected
0x26
val39
GPIO3 Pin Event Trig 0 input is selected
0x27
QDC0_PHASEB
QDC0 Trigger Input Connections
0x36C
32
read-write
0x3F
0xFFFFFFFF
INP
QDC0 input connections
0
6
read-write
val1
ARM_TXEV input is selected
0x1
val2
AOI0_OUT0 input is selected
0x2
val3
AOI0_OUT1 input is selected
0x3
val4
AOI0_OUT2 input is selected
0x4
val5
AOI0_OUT3 input is selected
0x5
val6
CMP0_OUT input is selected
0x6
val7
CMP1_OUT input is selected
0x7
val9
CTimer0_MAT2 input is selected
0x9
val10
CTimer0_MAT3 input is selected
0xA
val11
CTimer1_MAT2 input is selected
0xB
val12
CTimer1_MAT3 input is selected
0xC
val13
CTimer2_MAT2 input is selected
0xD
val14
CTimer2_MAT3 input is selected
0xE
val15
QDC0_POS_MATCH0 input is selected
0xF
val16
PWM0_SM0_OUT_TRIG0 input is selected
0x10
val17
PWM0_SM0_OUT_TRIG1 input is selected
0x11
val18
PWM0_SM1_OUT_TRIG0 input is selected
0x12
val19
PWM0_SM1_OUT_TRIG1 input is selected
0x13
val20
PWM0_SM2_OUT_TRIG0 input is selected
0x14
val21
PWM0_SM2_OUT_TRIG1 input is selected
0x15
val24
TRIG_IN0 input is selected
0x18
val25
TRIG_IN1 input is selected
0x19
val26
TRIG_IN2 input is selected
0x1A
val27
TRIG_IN3 input is selected
0x1B
val28
TRIG_IN4 input is selected
0x1C
val29
TRIG_IN5 input is selected
0x1D
val30
TRIG_IN6 input is selected
0x1E
val31
TRIG_IN7 input is selected
0x1F
val32
TRIG_IN8 input is selected
0x20
val33
TRIG_IN9 input is selected
0x21
val34
TRIG_IN10 input is selected
0x22
val35
TRIG_IN11 input is selected
0x23
val36
GPIO0 Pin Event Trig 0 input is selected
0x24
val37
GPIO1 Pin Event Trig 0 input is selected
0x25
val38
GPIO2 Pin Event Trig 0 input is selected
0x26
val39
GPIO3 Pin Event Trig 0 input is selected
0x27
QDC0_PHASEA
QDC0 Trigger Input Connections
0x370
32
read-write
0x3F
0xFFFFFFFF
INP
QDC0 input connections
0
6
read-write
val1
ARM_TXEV input is selected
0x1
val2
AOI0_OUT0 input is selected
0x2
val3
AOI0_OUT1 input is selected
0x3
val4
AOI0_OUT2 input is selected
0x4
val5
AOI0_OUT3 input is selected
0x5
val6
CMP0_OUT input is selected
0x6
val7
CMP1_OUT input is selected
0x7
val9
CTimer0_MAT2 input is selected
0x9
val10
CTimer0_MAT3 input is selected
0xA
val11
CTimer1_MAT2 input is selected
0xB
val12
CTimer1_MAT3 input is selected
0xC
val13
CTimer2_MAT2 input is selected
0xD
val14
CTimer2_MAT3 input is selected
0xE
val15
QDC0_POS_MATCH0 input is selected
0xF
val16
PWM0_SM0_OUT_TRIG0 input is selected
0x10
val17
PWM0_SM0_OUT_TRIG1 input is selected
0x11
val18
PWM0_SM1_OUT_TRIG0 input is selected
0x12
val19
PWM0_SM1_OUT_TRIG1 input is selected
0x13
val20
PWM0_SM2_OUT_TRIG0 input is selected
0x14
val21
PWM0_SM2_OUT_TRIG1 input is selected
0x15
val24
TRIG_IN0 input is selected
0x18
val25
TRIG_IN1 input is selected
0x19
val26
TRIG_IN2 input is selected
0x1A
val27
TRIG_IN3 input is selected
0x1B
val28
TRIG_IN4 input is selected
0x1C
val29
TRIG_IN5 input is selected
0x1D
val30
TRIG_IN6 input is selected
0x1E
val31
TRIG_IN7 input is selected
0x1F
val32
TRIG_IN8 input is selected
0x20
val33
TRIG_IN9 input is selected
0x21
val34
TRIG_IN10 input is selected
0x22
val35
TRIG_IN11 input is selected
0x23
val36
GPIO0 Pin Event Trig 0 input is selected
0x24
val37
GPIO1 Pin Event Trig 0 input is selected
0x25
val38
GPIO2 Pin Event Trig 0 input is selected
0x26
val39
GPIO3 Pin Event Trig 0 input is selected
0x27
QDC0_ICAP1
QDC0 Trigger Input Connections
0x374
32
read-write
0x3F
0xFFFFFFFF
INP
QDC0 input connections
0
6
read-write
val1
ARM_TXEV input is selected
0x1
val2
AOI0_OUT0 input is selected
0x2
val3
AOI0_OUT1 input is selected
0x3
val4
AOI0_OUT2 input is selected
0x4
val5
AOI0_OUT3 input is selected
0x5
val6
CMP0_OUT input is selected
0x6
val7
CMP1_OUT input is selected
0x7
val9
CTimer0_MAT2 input is selected
0x9
val10
CTimer0_MAT3 input is selected
0xA
val11
CTimer1_MAT2 input is selected
0xB
val12
CTimer1_MAT3 input is selected
0xC
val13
CTimer2_MAT2 input is selected
0xD
val14
CTimer2_MAT3 input is selected
0xE
val15
QDC0_POS_MATCH0 input is selected
0xF
val16
PWM0_SM0_OUT_TRIG0 input is selected
0x10
val17
PWM0_SM0_OUT_TRIG1 input is selected
0x11
val18
PWM0_SM1_OUT_TRIG0 input is selected
0x12
val19
PWM0_SM1_OUT_TRIG1 input is selected
0x13
val20
PWM0_SM2_OUT_TRIG0 input is selected
0x14
val21
PWM0_SM2_OUT_TRIG1 input is selected
0x15
val24
TRIG_IN0 input is selected
0x18
val25
TRIG_IN1 input is selected
0x19
val26
TRIG_IN2 input is selected
0x1A
val27
TRIG_IN3 input is selected
0x1B
val28
TRIG_IN4 input is selected
0x1C
val29
TRIG_IN5 input is selected
0x1D
val30
TRIG_IN6 input is selected
0x1E
val31
TRIG_IN7 input is selected
0x1F
val32
TRIG_IN8 input is selected
0x20
val33
TRIG_IN9 input is selected
0x21
val34
TRIG_IN10 input is selected
0x22
val35
TRIG_IN11 input is selected
0x23
val36
GPIO0 Pin Event Trig 0 input is selected
0x24
val37
GPIO1 Pin Event Trig 0 input is selected
0x25
val38
GPIO2 Pin Event Trig 0 input is selected
0x26
val39
GPIO3 Pin Event Trig 0 input is selected
0x27
QDC0_ICAP2
QDC0 Trigger Input Connections
0x378
32
read-write
0x3F
0xFFFFFFFF
INP
QDC0 input connections
0
6
read-write
val1
ARM_TXEV input is selected
0x1
val2
AOI0_OUT0 input is selected
0x2
val3
AOI0_OUT1 input is selected
0x3
val4
AOI0_OUT2 input is selected
0x4
val5
AOI0_OUT3 input is selected
0x5
val6
CMP0_OUT input is selected
0x6
val7
CMP1_OUT input is selected
0x7
val9
CTimer0_MAT2 input is selected
0x9
val10
CTimer0_MAT3 input is selected
0xA
val11
CTimer1_MAT2 input is selected
0xB
val12
CTimer1_MAT3 input is selected
0xC
val13
CTimer2_MAT2 input is selected
0xD
val14
CTimer2_MAT3 input is selected
0xE
val15
QDC0_POS_MATCH0 input is selected
0xF
val16
PWM0_SM0_OUT_TRIG0 input is selected
0x10
val17
PWM0_SM0_OUT_TRIG1 input is selected
0x11
val18
PWM0_SM1_OUT_TRIG0 input is selected
0x12
val19
PWM0_SM1_OUT_TRIG1 input is selected
0x13
val20
PWM0_SM2_OUT_TRIG0 input is selected
0x14
val21
PWM0_SM2_OUT_TRIG1 input is selected
0x15
val24
TRIG_IN0 input is selected
0x18
val25
TRIG_IN1 input is selected
0x19
val26
TRIG_IN2 input is selected
0x1A
val27
TRIG_IN3 input is selected
0x1B
val28
TRIG_IN4 input is selected
0x1C
val29
TRIG_IN5 input is selected
0x1D
val30
TRIG_IN6 input is selected
0x1E
val31
TRIG_IN7 input is selected
0x1F
val32
TRIG_IN8 input is selected
0x20
val33
TRIG_IN9 input is selected
0x21
val34
TRIG_IN10 input is selected
0x22
val35
TRIG_IN11 input is selected
0x23
val36
GPIO0 Pin Event Trig 0 input is selected
0x24
val37
GPIO1 Pin Event Trig 0 input is selected
0x25
val38
GPIO2 Pin Event Trig 0 input is selected
0x26
val39
GPIO3 Pin Event Trig 0 input is selected
0x27
QDC0_ICAP3
QDC0 Trigger Input Connections
0x37C
32
read-write
0x3F
0xFFFFFFFF
INP
QDC0 input connections
0
6
read-write
val1
ARM_TXEV input is selected
0x1
val2
AOI0_OUT0 input is selected
0x2
val3
AOI0_OUT1 input is selected
0x3
val4
AOI0_OUT2 input is selected
0x4
val5
AOI0_OUT3 input is selected
0x5
val6
CMP0_OUT input is selected
0x6
val7
CMP1_OUT input is selected
0x7
val9
CTimer0_MAT2 input is selected
0x9
val10
CTimer0_MAT3 input is selected
0xA
val11
CTimer1_MAT2 input is selected
0xB
val12
CTimer1_MAT3 input is selected
0xC
val13
CTimer2_MAT2 input is selected
0xD
val14
CTimer2_MAT3 input is selected
0xE
val15
QDC0_POS_MATCH0 input is selected
0xF
val16
PWM0_SM0_OUT_TRIG0 input is selected
0x10
val17
PWM0_SM0_OUT_TRIG1 input is selected
0x11
val18
PWM0_SM1_OUT_TRIG0 input is selected
0x12
val19
PWM0_SM1_OUT_TRIG1 input is selected
0x13
val20
PWM0_SM2_OUT_TRIG0 input is selected
0x14
val21
PWM0_SM2_OUT_TRIG1 input is selected
0x15
val24
TRIG_IN0 input is selected
0x18
val25
TRIG_IN1 input is selected
0x19
val26
TRIG_IN2 input is selected
0x1A
val27
TRIG_IN3 input is selected
0x1B
val28
TRIG_IN4 input is selected
0x1C
val29
TRIG_IN5 input is selected
0x1D
val30
TRIG_IN6 input is selected
0x1E
val31
TRIG_IN7 input is selected
0x1F
val32
TRIG_IN8 input is selected
0x20
val33
TRIG_IN9 input is selected
0x21
val34
TRIG_IN10 input is selected
0x22
val35
TRIG_IN11 input is selected
0x23
val36
GPIO0 Pin Event Trig 0 input is selected
0x24
val37
GPIO1 Pin Event Trig 0 input is selected
0x25
val38
GPIO2 Pin Event Trig 0 input is selected
0x26
val39
GPIO3 Pin Event Trig 0 input is selected
0x27
FlexPWM0_SM0_EXTA0
PWM0 input trigger connections
0x3A0
32
read-write
0x3F
0xFFFFFFFF
TRIGIN
Trigger input connections for PWM0
0
6
read-write
val1
ARM_TXEV input is selected
0x1
val2
AOI0_OUT0 input is selected
0x2
val3
AOI0_OUT1 input is selected
0x3
val4
AOI0_OUT2 input is selected
0x4
val5
AOI0_OUT3 input is selected
0x5
val6
CMP0_OUT input is selected
0x6
val7
CMP1_OUT input is selected
0x7
val9
CTimer0_MAT2 input is selected
0x9
val10
CTimer0_MAT3 input is selected
0xA
val11
CTimer1_MAT2 input is selected
0xB
val12
CTimer1_MAT3 input is selected
0xC
val13
CTimer2_MAT2 input is selected
0xD
val14
CTimer2_MAT3 input is selected
0xE
val15
QDC0_CMP_FLAG0 input is selected
0xF
val16
QDC0_CMP_FLAG1 input is selected
0x10
val17
QDC0_CMP_FLAG2 input is selected
0x11
val18
QDC0_CMP_FLAG3 input is selected
0x12
val19
QDC0_POS_MATCH0 input is selected
0x13
val20
TRIG_IN0 input is selected
0x14
val21
TRIG_IN1 input is selected
0x15
val22
TRIG_IN2 input is selected
0x16
val23
TRIG_IN3 input is selected
0x17
val24
TRIG_IN4 input is selected
0x18
val25
TRIG_IN5 input is selected
0x19
val26
TRIG_IN6 input is selected
0x1A
val27
TRIG_IN7 input is selected
0x1B
val28
TRIG_IN8 input is selected
0x1C
val29
TRIG_IN9 input is selected
0x1D
val30
TRIG_IN10 input is selected
0x1E
val31
TRIG_IN11 input is selected
0x1F
val32
GPIO0 Pin Event Trig 0 input is selected
0x20
val33
GPIO1 Pin Event Trig 0 input is selected
0x21
val34
GPIO2 Pin Event Trig 0 input is selected
0x22
val35
GPIO3 Pin Event Trig 0 input is selected
0x23
FlexPWM0_SM0_EXTSYNC0
PWM0 input trigger connections
0x3A4
32
read-write
0x3F
0xFFFFFFFF
TRIGIN
Trigger input connections for PWM0
0
6
read-write
val1
ARM_TXEV input is selected
0x1
val2
AOI0_OUT0 input is selected
0x2
val3
AOI0_OUT1 input is selected
0x3
val4
AOI0_OUT2 input is selected
0x4
val5
AOI0_OUT3 input is selected
0x5
val6
CMP0_OUT input is selected
0x6
val7
CMP1_OUT input is selected
0x7
val9
CTimer0_MAT2 input is selected
0x9
val10
CTimer0_MAT3 input is selected
0xA
val11
CTimer1_MAT2 input is selected
0xB
val12
CTimer1_MAT3 input is selected
0xC
val13
CTimer2_MAT2 input is selected
0xD
val14
CTimer2_MAT3 input is selected
0xE
val15
QDC0_CMP_FLAG0 input is selected
0xF
val16
QDC0_CMP_FLAG1 input is selected
0x10
val17
QDC0_CMP_FLAG2 input is selected
0x11
val18
QDC0_CMP_FLAG3 input is selected
0x12
val19
QDC0_POS_MATCH0 input is selected
0x13
val20
TRIG_IN0 input is selected
0x14
val21
TRIG_IN1 input is selected
0x15
val22
TRIG_IN2 input is selected
0x16
val23
TRIG_IN3 input is selected
0x17
val24
TRIG_IN4 input is selected
0x18
val25
TRIG_IN5 input is selected
0x19
val26
TRIG_IN6 input is selected
0x1A
val27
TRIG_IN7 input is selected
0x1B
val28
TRIG_IN8 input is selected
0x1C
val29
TRIG_IN9 input is selected
0x1D
val30
TRIG_IN10 input is selected
0x1E
val31
TRIG_IN11 input is selected
0x1F
val32
GPIO0 Pin Event Trig 0 input is selected
0x20
val33
GPIO1 Pin Event Trig 0 input is selected
0x21
val34
GPIO2 Pin Event Trig 0 input is selected
0x22
val35
GPIO3 Pin Event Trig 0 input is selected
0x23
FlexPWM0_SM1_EXTA1
PWM0 input trigger connections
0x3A8
32
read-write
0x3F
0xFFFFFFFF
TRIGIN
Trigger input connections for PWM0
0
6
read-write
val1
ARM_TXEV input is selected
0x1
val2
AOI0_OUT0 input is selected
0x2
val3
AOI0_OUT1 input is selected
0x3
val4
AOI0_OUT2 input is selected
0x4
val5
AOI0_OUT3 input is selected
0x5
val6
CMP0_OUT input is selected
0x6
val7
CMP1_OUT input is selected
0x7
val9
CTimer0_MAT2 input is selected
0x9
val10
CTimer0_MAT3 input is selected
0xA
val11
CTimer1_MAT2 input is selected
0xB
val12
CTimer1_MAT3 input is selected
0xC
val13
CTimer2_MAT2 input is selected
0xD
val14
CTimer2_MAT3 input is selected
0xE
val15
QDC0_CMP_FLAG0 input is selected
0xF
val16
QDC0_CMP_FLAG1 input is selected
0x10
val17
QDC0_CMP_FLAG2 input is selected
0x11
val18
QDC0_CMP_FLAG3 input is selected
0x12
val19
QDC0_POS_MATCH0 input is selected
0x13
val20
TRIG_IN0 input is selected
0x14
val21
TRIG_IN1 input is selected
0x15
val22
TRIG_IN2 input is selected
0x16
val23
TRIG_IN3 input is selected
0x17
val24
TRIG_IN4 input is selected
0x18
val25
TRIG_IN5 input is selected
0x19
val26
TRIG_IN6 input is selected
0x1A
val27
TRIG_IN7 input is selected
0x1B
val28
TRIG_IN8 input is selected
0x1C
val29
TRIG_IN9 input is selected
0x1D
val30
TRIG_IN10 input is selected
0x1E
val31
TRIG_IN11 input is selected
0x1F
val32
GPIO0 Pin Event Trig 0 input is selected
0x20
val33
GPIO1 Pin Event Trig 0 input is selected
0x21
val34
GPIO2 Pin Event Trig 0 input is selected
0x22
val35
GPIO3 Pin Event Trig 0 input is selected
0x23
FlexPWM0_SM1_EXTSYNC1
PWM0 input trigger connections
0x3AC
32
read-write
0x3F
0xFFFFFFFF
TRIGIN
Trigger input connections for PWM0
0
6
read-write
val1
ARM_TXEV input is selected
0x1
val2
AOI0_OUT0 input is selected
0x2
val3
AOI0_OUT1 input is selected
0x3
val4
AOI0_OUT2 input is selected
0x4
val5
AOI0_OUT3 input is selected
0x5
val6
CMP0_OUT input is selected
0x6
val7
CMP1_OUT input is selected
0x7
val9
CTimer0_MAT2 input is selected
0x9
val10
CTimer0_MAT3 input is selected
0xA
val11
CTimer1_MAT2 input is selected
0xB
val12
CTimer1_MAT3 input is selected
0xC
val13
CTimer2_MAT2 input is selected
0xD
val14
CTimer2_MAT3 input is selected
0xE
val15
QDC0_CMP_FLAG0 input is selected
0xF
val16
QDC0_CMP_FLAG1 input is selected
0x10
val17
QDC0_CMP_FLAG2 input is selected
0x11
val18
QDC0_CMP_FLAG3 input is selected
0x12
val19
QDC0_POS_MATCH0 input is selected
0x13
val20
TRIG_IN0 input is selected
0x14
val21
TRIG_IN1 input is selected
0x15
val22
TRIG_IN2 input is selected
0x16
val23
TRIG_IN3 input is selected
0x17
val24
TRIG_IN4 input is selected
0x18
val25
TRIG_IN5 input is selected
0x19
val26
TRIG_IN6 input is selected
0x1A
val27
TRIG_IN7 input is selected
0x1B
val28
TRIG_IN8 input is selected
0x1C
val29
TRIG_IN9 input is selected
0x1D
val30
TRIG_IN10 input is selected
0x1E
val31
TRIG_IN11 input is selected
0x1F
val32
GPIO0 Pin Event Trig 0 input is selected
0x20
val33
GPIO1 Pin Event Trig 0 input is selected
0x21
val34
GPIO2 Pin Event Trig 0 input is selected
0x22
val35
GPIO3 Pin Event Trig 0 input is selected
0x23
FlexPWM0_SM2_EXTA2
PWM0 input trigger connections
0x3B0
32
read-write
0x3F
0xFFFFFFFF
TRIGIN
Trigger input connections for PWM0
0
6
read-write
val1
ARM_TXEV input is selected
0x1
val2
AOI0_OUT0 input is selected
0x2
val3
AOI0_OUT1 input is selected
0x3
val4
AOI0_OUT2 input is selected
0x4
val5
AOI0_OUT3 input is selected
0x5
val6
CMP0_OUT input is selected
0x6
val7
CMP1_OUT input is selected
0x7
val9
CTimer0_MAT2 input is selected
0x9
val10
CTimer0_MAT3 input is selected
0xA
val11
CTimer1_MAT2 input is selected
0xB
val12
CTimer1_MAT3 input is selected
0xC
val13
CTimer2_MAT2 input is selected
0xD
val14
CTimer2_MAT3 input is selected
0xE
val15
QDC0_CMP_FLAG0 input is selected
0xF
val16
QDC0_CMP_FLAG1 input is selected
0x10
val17
QDC0_CMP_FLAG2 input is selected
0x11
val18
QDC0_CMP_FLAG3 input is selected
0x12
val19
QDC0_POS_MATCH0 input is selected
0x13
val20
TRIG_IN0 input is selected
0x14
val21
TRIG_IN1 input is selected
0x15
val22
TRIG_IN2 input is selected
0x16
val23
TRIG_IN3 input is selected
0x17
val24
TRIG_IN4 input is selected
0x18
val25
TRIG_IN5 input is selected
0x19
val26
TRIG_IN6 input is selected
0x1A
val27
TRIG_IN7 input is selected
0x1B
val28
TRIG_IN8 input is selected
0x1C
val29
TRIG_IN9 input is selected
0x1D
val30
TRIG_IN10 input is selected
0x1E
val31
TRIG_IN11 input is selected
0x1F
val32
GPIO0 Pin Event Trig 0 input is selected
0x20
val33
GPIO1 Pin Event Trig 0 input is selected
0x21
val34
GPIO2 Pin Event Trig 0 input is selected
0x22
val35
GPIO3 Pin Event Trig 0 input is selected
0x23
FlexPWM0_SM2_EXTSYNC2
PWM0 input trigger connections
0x3B4
32
read-write
0x3F
0xFFFFFFFF
TRIGIN
Trigger input connections for PWM0
0
6
read-write
val1
ARM_TXEV input is selected
0x1
val2
AOI0_OUT0 input is selected
0x2
val3
AOI0_OUT1 input is selected
0x3
val4
AOI0_OUT2 input is selected
0x4
val5
AOI0_OUT3 input is selected
0x5
val6
CMP0_OUT input is selected
0x6
val7
CMP1_OUT input is selected
0x7
val9
CTimer0_MAT2 input is selected
0x9
val10
CTimer0_MAT3 input is selected
0xA
val11
CTimer1_MAT2 input is selected
0xB
val12
CTimer1_MAT3 input is selected
0xC
val13
CTimer2_MAT2 input is selected
0xD
val14
CTimer2_MAT3 input is selected
0xE
val15
QDC0_CMP_FLAG0 input is selected
0xF
val16
QDC0_CMP_FLAG1 input is selected
0x10
val17
QDC0_CMP_FLAG2 input is selected
0x11
val18
QDC0_CMP_FLAG3 input is selected
0x12
val19
QDC0_POS_MATCH0 input is selected
0x13
val20
TRIG_IN0 input is selected
0x14
val21
TRIG_IN1 input is selected
0x15
val22
TRIG_IN2 input is selected
0x16
val23
TRIG_IN3 input is selected
0x17
val24
TRIG_IN4 input is selected
0x18
val25
TRIG_IN5 input is selected
0x19
val26
TRIG_IN6 input is selected
0x1A
val27
TRIG_IN7 input is selected
0x1B
val28
TRIG_IN8 input is selected
0x1C
val29
TRIG_IN9 input is selected
0x1D
val30
TRIG_IN10 input is selected
0x1E
val31
TRIG_IN11 input is selected
0x1F
val32
GPIO0 Pin Event Trig 0 input is selected
0x20
val33
GPIO1 Pin Event Trig 0 input is selected
0x21
val34
GPIO2 Pin Event Trig 0 input is selected
0x22
val35
GPIO3 Pin Event Trig 0 input is selected
0x23
FlexPWM0_FAULT0
PWM0 input trigger connections
0x3C0
32
read-write
0x3F
0xFFFFFFFF
TRIGIN
Trigger input connections for PWM0
0
6
read-write
val1
ARM_TXEV input is selected
0x1
val2
AOI0_OUT0 input is selected
0x2
val3
AOI0_OUT1 input is selected
0x3
val4
AOI0_OUT2 input is selected
0x4
val5
AOI0_OUT3 input is selected
0x5
val6
CMP0_OUT input is selected
0x6
val7
CMP1_OUT input is selected
0x7
val9
CTimer0_MAT2 input is selected
0x9
val10
CTimer0_MAT3 input is selected
0xA
val11
CTimer1_MAT2 input is selected
0xB
val12
CTimer1_MAT3 input is selected
0xC
val13
CTimer2_MAT2 input is selected
0xD
val14
CTimer2_MAT3 input is selected
0xE
val15
QDC0_CMP_FLAG0 input is selected
0xF
val16
QDC0_CMP_FLAG1 input is selected
0x10
val17
QDC0_CMP_FLAG2 input is selected
0x11
val18
QDC0_CMP_FLAG3 input is selected
0x12
val19
QDC0_POS_MATCH0 input is selected
0x13
val20
TRIG_IN0 input is selected
0x14
val21
TRIG_IN1 input is selected
0x15
val22
TRIG_IN2 input is selected
0x16
val23
TRIG_IN3 input is selected
0x17
val24
TRIG_IN4 input is selected
0x18
val25
TRIG_IN5 input is selected
0x19
val26
TRIG_IN6 input is selected
0x1A
val27
TRIG_IN7 input is selected
0x1B
val28
TRIG_IN8 input is selected
0x1C
val29
TRIG_IN9 input is selected
0x1D
val30
TRIG_IN10 input is selected
0x1E
val31
TRIG_IN11 input is selected
0x1F
val32
GPIO0 Pin Event Trig 0 input is selected
0x20
val33
GPIO1 Pin Event Trig 0 input is selected
0x21
val34
GPIO2 Pin Event Trig 0 input is selected
0x22
val35
GPIO3 Pin Event Trig 0 input is selected
0x23
FlexPWM0_FAULT1
PWM0 input trigger connections
0x3C4
32
read-write
0x3F
0xFFFFFFFF
TRIGIN
Trigger input connections for PWM0
0
6
read-write
val1
ARM_TXEV input is selected
0x1
val2
AOI0_OUT0 input is selected
0x2
val3
AOI0_OUT1 input is selected
0x3
val4
AOI0_OUT2 input is selected
0x4
val5
AOI0_OUT3 input is selected
0x5
val6
CMP0_OUT input is selected
0x6
val7
CMP1_OUT input is selected
0x7
val9
CTimer0_MAT2 input is selected
0x9
val10
CTimer0_MAT3 input is selected
0xA
val11
CTimer1_MAT2 input is selected
0xB
val12
CTimer1_MAT3 input is selected
0xC
val13
CTimer2_MAT2 input is selected
0xD
val14
CTimer2_MAT3 input is selected
0xE
val15
QDC0_CMP_FLAG0 input is selected
0xF
val16
QDC0_CMP_FLAG1 input is selected
0x10
val17
QDC0_CMP_FLAG2 input is selected
0x11
val18
QDC0_CMP_FLAG3 input is selected
0x12
val19
QDC0_POS_MATCH0 input is selected
0x13
val20
TRIG_IN0 input is selected
0x14
val21
TRIG_IN1 input is selected
0x15
val22
TRIG_IN2 input is selected
0x16
val23
TRIG_IN3 input is selected
0x17
val24
TRIG_IN4 input is selected
0x18
val25
TRIG_IN5 input is selected
0x19
val26
TRIG_IN6 input is selected
0x1A
val27
TRIG_IN7 input is selected
0x1B
val28
TRIG_IN8 input is selected
0x1C
val29
TRIG_IN9 input is selected
0x1D
val30
TRIG_IN10 input is selected
0x1E
val31
TRIG_IN11 input is selected
0x1F
val32
GPIO0 Pin Event Trig 0 input is selected
0x20
val33
GPIO1 Pin Event Trig 0 input is selected
0x21
val34
GPIO2 Pin Event Trig 0 input is selected
0x22
val35
GPIO3 Pin Event Trig 0 input is selected
0x23
FlexPWM0_FAULT2
PWM0 input trigger connections
0x3C8
32
read-write
0x3F
0xFFFFFFFF
TRIGIN
Trigger input connections for PWM0
0
6
read-write
val1
ARM_TXEV input is selected
0x1
val2
AOI0_OUT0 input is selected
0x2
val3
AOI0_OUT1 input is selected
0x3
val4
AOI0_OUT2 input is selected
0x4
val5
AOI0_OUT3 input is selected
0x5
val6
CMP0_OUT input is selected
0x6
val7
CMP1_OUT input is selected
0x7
val9
CTimer0_MAT2 input is selected
0x9
val10
CTimer0_MAT3 input is selected
0xA
val11
CTimer1_MAT2 input is selected
0xB
val12
CTimer1_MAT3 input is selected
0xC
val13
CTimer2_MAT2 input is selected
0xD
val14
CTimer2_MAT3 input is selected
0xE
val15
QDC0_CMP_FLAG0 input is selected
0xF
val16
QDC0_CMP_FLAG1 input is selected
0x10
val17
QDC0_CMP_FLAG2 input is selected
0x11
val18
QDC0_CMP_FLAG3 input is selected
0x12
val19
QDC0_POS_MATCH0 input is selected
0x13
val20
TRIG_IN0 input is selected
0x14
val21
TRIG_IN1 input is selected
0x15
val22
TRIG_IN2 input is selected
0x16
val23
TRIG_IN3 input is selected
0x17
val24
TRIG_IN4 input is selected
0x18
val25
TRIG_IN5 input is selected
0x19
val26
TRIG_IN6 input is selected
0x1A
val27
TRIG_IN7 input is selected
0x1B
val28
TRIG_IN8 input is selected
0x1C
val29
TRIG_IN9 input is selected
0x1D
val30
TRIG_IN10 input is selected
0x1E
val31
TRIG_IN11 input is selected
0x1F
val32
GPIO0 Pin Event Trig 0 input is selected
0x20
val33
GPIO1 Pin Event Trig 0 input is selected
0x21
val34
GPIO2 Pin Event Trig 0 input is selected
0x22
val35
GPIO3 Pin Event Trig 0 input is selected
0x23
FlexPWM0_FAULT3
PWM0 input trigger connections
0x3CC
32
read-write
0x3F
0xFFFFFFFF
TRIGIN
Trigger input connections for PWM0
0
6
read-write
val1
ARM_TXEV input is selected
0x1
val2
AOI0_OUT0 input is selected
0x2
val3
AOI0_OUT1 input is selected
0x3
val4
AOI0_OUT2 input is selected
0x4
val5
AOI0_OUT3 input is selected
0x5
val6
CMP0_OUT input is selected
0x6
val7
CMP1_OUT input is selected
0x7
val9
CTimer0_MAT2 input is selected
0x9
val10
CTimer0_MAT3 input is selected
0xA
val11
CTimer1_MAT2 input is selected
0xB
val12
CTimer1_MAT3 input is selected
0xC
val13
CTimer2_MAT2 input is selected
0xD
val14
CTimer2_MAT3 input is selected
0xE
val15
QDC0_CMP_FLAG0 input is selected
0xF
val16
QDC0_CMP_FLAG1 input is selected
0x10
val17
QDC0_CMP_FLAG2 input is selected
0x11
val18
QDC0_CMP_FLAG3 input is selected
0x12
val19
QDC0_POS_MATCH0 input is selected
0x13
val20
TRIG_IN0 input is selected
0x14
val21
TRIG_IN1 input is selected
0x15
val22
TRIG_IN2 input is selected
0x16
val23
TRIG_IN3 input is selected
0x17
val24
TRIG_IN4 input is selected
0x18
val25
TRIG_IN5 input is selected
0x19
val26
TRIG_IN6 input is selected
0x1A
val27
TRIG_IN7 input is selected
0x1B
val28
TRIG_IN8 input is selected
0x1C
val29
TRIG_IN9 input is selected
0x1D
val30
TRIG_IN10 input is selected
0x1E
val31
TRIG_IN11 input is selected
0x1F
val32
GPIO0 Pin Event Trig 0 input is selected
0x20
val33
GPIO1 Pin Event Trig 0 input is selected
0x21
val34
GPIO2 Pin Event Trig 0 input is selected
0x22
val35
GPIO3 Pin Event Trig 0 input is selected
0x23
FlexPWM0_FORCE
PWM0 input trigger connections
0x3D0
32
read-write
0x3F
0xFFFFFFFF
TRIGIN
Trigger input connections for PWM0
0
6
read-write
val1
ARM_TXEV input is selected
0x1
val2
AOI0_OUT0 input is selected
0x2
val3
AOI0_OUT1 input is selected
0x3
val4
AOI0_OUT2 input is selected
0x4
val5
AOI0_OUT3 input is selected
0x5
val6
CMP0_OUT input is selected
0x6
val7
CMP1_OUT input is selected
0x7
val9
CTimer0_MAT2 input is selected
0x9
val10
CTimer0_MAT3 input is selected
0xA
val11
CTimer1_MAT2 input is selected
0xB
val12
CTimer1_MAT3 input is selected
0xC
val13
CTimer2_MAT2 input is selected
0xD
val14
CTimer2_MAT3 input is selected
0xE
val15
QDC0_CMP_FLAG0 input is selected
0xF
val16
QDC0_CMP_FLAG1 input is selected
0x10
val17
QDC0_CMP_FLAG2 input is selected
0x11
val18
QDC0_CMP_FLAG3 input is selected
0x12
val19
QDC0_POS_MATCH0 input is selected
0x13
val20
TRIG_IN0 input is selected
0x14
val21
TRIG_IN1 input is selected
0x15
val22
TRIG_IN2 input is selected
0x16
val23
TRIG_IN3 input is selected
0x17
val24
TRIG_IN4 input is selected
0x18
val25
TRIG_IN5 input is selected
0x19
val26
TRIG_IN6 input is selected
0x1A
val27
TRIG_IN7 input is selected
0x1B
val28
TRIG_IN8 input is selected
0x1C
val29
TRIG_IN9 input is selected
0x1D
val30
TRIG_IN10 input is selected
0x1E
val31
TRIG_IN11 input is selected
0x1F
val32
GPIO0 Pin Event Trig 0 input is selected
0x20
val33
GPIO1 Pin Event Trig 0 input is selected
0x21
val34
GPIO2 Pin Event Trig 0 input is selected
0x22
val35
GPIO3 Pin Event Trig 0 input is selected
0x23
PWM0_EXT_CLK
PWM0 external clock trigger
0x420
32
read-write
0x7
0xFFFFFFFF
TRIGIN
Trigger input connections for PWM
0
3
read-write
val1
clk_16k[1] input is selected
0x1
val2
clk_in input is selected
0x2
val3
AOI0_OUT0 input is selected
0x3
val4
AOI0_OUT1 input is selected
0x4
val5
EXTTRIG_IN0 input is selected
0x5
val6
EXTTRIG_IN7 input is selected
0x6
16
0x4
AOI0_MUX[%s]
AOI0 trigger input connections 0-15
0x440
32
read-write
0x3F
0xFFFFFFFF
INP
AOI0 trigger input connections
0
6
read-write
val1
ADC0_tcomp[0] input is selected input is selected input is selected
0x1
val2
ADC0_tcomp[1] input is selected input is selected
0x2
val3
ADC0_tcomp[2] input is selected input is selected
0x3
val4
ADC0_tcomp[3] input is selected input is selected
0x4
val5
CMP0_OUT input is selected
0x5
val6
CMP1_OUT input is selected
0x6
val8
CTimer0_MAT0 input is selected
0x8
val9
CTimer0_MAT1 input is selected
0x9
val10
CTimer0_MAT2 input is selected
0xA
val11
CTimer0_MAT3 input is selected
0xB
val12
CTimer1_MAT0 input is selected
0xC
val13
CTimer1_MAT1 input is selected
0xD
val14
CTimer1_MAT2 input is selected
0xE
val15
CTimer1_MAT3 input is selected
0xF
val16
CTimer2_MAT0 input is selected
0x10
val17
CTimer2_MAT1 input is selected
0x11
val18
CTimer2_MAT2 input is selected
0x12
val19
CTimer2_MAT3 input is selected
0x13
val20
LPTMR0 input is selected
0x14
val22
QDC0_CMP_FLAG0 input input is selected
0x16
val23
QDC0_CMP_FLAG1 input is selected
0x17
val24
QDC0_CMP_FLAG2 input is selected
0x18
val25
QDC0_CMP_FLAG3 input is selected
0x19
val26
QDC0_POS_MATCH input is selected
0x1A
val27
PWM0_SM0_OUT_TRIG0 0 input is selected
0x1B
val28
PWM0_SM0_OUT_TRIG1 input is selected
0x1C
val29
PWM0_SM1_OUT_TRIG0 input is selected
0x1D
val30
PWM0_SM1_OUT_TRIG1 input is selected
0x1E
val31
PWM0_SM2_OUT_TRIG0 input is selected
0x1F
val32
PWM0_SM2_OUT_TRIG1 input is selected
0x20
val35
TRIG_IN0 input is selected
0x23
val36
TRIG_IN1 input is selected
0x24
val37
TRIG_IN2 input is selected
0x25
val38
TRIG_IN3 input is selected
0x26
val39
TRIG_IN4 input is selected
0x27
val40
TRIG_IN5 input is selected
0x28
val41
TRIG_IN6 input is selected
0x29
val42
TRIG_IN7 input is selected
0x2A
val43
TRIG_IN8 input is selected
0x2B
val44
TRIG_IN9 input is selected
0x2C
val45
TRIG_IN10 input is selected
0x2D
val46
TRIG_IN11 input is selected
0x2E
val47
GPIO0 Pin Event Trig 0 input is selected
0x2F
val48
GPIO1 Pin Event Trig 0 input is selected
0x30
val49
GPIO2 Pin Event Trig 0 input is selected
0x31
val50
GPIO3 Pin Event Trig 0 input is selected
0x32
USBFS_TRIG
USB-FS trigger input connections
0x480
32
read-write
0x7
0xFFFFFFFF
INP
USB-FS trigger input connections.
0
3
read-write
val1
LPUART0 lpuart_trg_txdata input is selected
0x1
val2
LPUART1 lpuart_trg_txdata input is selected
0x2
val3
LPUART2 lpuart_trg_txdata input is selected
0x3
5
0x4
EXT_TRIG[%s]
EXT trigger connections 0-4
0x4C0
32
read-write
0x1F
0xFFFFFFFF
INP
EXT trigger input connections
0
5
read-write
val1
ARM_TXEV input is selected
0x1
val2
AOI0_OUT0 input is selected
0x2
val3
AOI0_OUT1 input is selected
0x3
val4
AOI0_OUT2 input is selected
0x4
val5
AOI0_OUT3 input is selected
0x5
val6
CMP0_OUT input is selected
0x6
val7
CMP1_OUT input is selected
0x7
val9
LPUART0 input is selected
0x9
val10
LPUART1 input is selected
0xA
val11
LPUART2 input is selected
0xB
2
0x4
6,7
EXT_TRIG%s
EXT trigger connections 6-7
0x4D8
32
read-write
0x1F
0xFFFFFFFF
INP
EXT trigger input connections
0
5
read-write
val1
ARM_TXEV input is selected
0x1
val2
AOI0_OUT0 input is selected
0x2
val3
AOI0_OUT1 input is selected
0x3
val4
AOI0_OUT2 input is selected
0x4
val5
AOI0_OUT3 input is selected
0x5
val6
CMP0_OUT input is selected
0x6
val7
CMP1_OUT input is selected
0x7
val9
LPUART0 input is selected
0x9
val10
LPUART1 input is selected
0xA
val11
LPUART2 input is selected
0xB
CMP1_TRIG
CMP1 input connections
0x4E0
32
read-write
0x3F
0xFFFFFFFF
TRIGIN
CMP0 input trigger
0
6
read-write
val1
ARM_TXEV input is selected
0x1
val2
AOI0_OUT0 input is selected
0x2
val3
AOI0_OUT1 input is selected
0x3
val4
AOI0_OUT2 input is selected
0x4
val5
AOI0_OUT3 input is selected
0x5
val6
CMP0_OUT input is selected
0x6
val8
CTimer0_MAT0 input is selected
0x8
val9
CTimer0_MAT2 input is selected
0x9
val10
CTimer1_MAT0 input is selected
0xA
val11
CTimer1_MAT2 input is selected
0xB
val12
CTimer2_MAT0 input is selected
0xC
val13
CTimer2_MAT2 input is selected
0xD
val14
LPTMR0 input is selected
0xE
val16
QDC0_CMP/POS_MATCH0
0x10
val17
PWM0_SM0_OUT_TRIG0 input is selected
0x11
val18
PWM0_SM0_OUT_TRIG1 input is selected
0x12
val19
PWM0_SM1_OUT_TRIG0 input is selected
0x13
val20
PWM0_SM1_OUT_TRIG1 input is selected
0x14
val21
PWM0_SM2_OUT_TRIG0 input is selected
0x15
val22
PWM0_SM2_OUT_TRIG1 input is selected
0x16
val25
GPIO0 Pin Event Trig 0 input is selected
0x19
val26
GPIO1 Pin Event Trig 0 input is selected
0x1A
val27
GPIO2 Pin Event Trig 0 input is selected
0x1B
val28
GPIO3 Pin Event Trig 0 input is selected
0x1C
val30
WUU input is selected
0x1E
LPI2C0_TRIG
LPI2C0 trigger input connections
0x5A0
32
read-write
0x3F
0xFFFFFFFF
INP
LPI2C0 trigger input connections
0
6
read-write
val1
ARM_TXEV
0x1
val2
AOI0_OUT0 input is selected
0x2
val3
AOI0_OUT1 input is selected
0x3
val4
AOI0_OUT2 input is selected
0x4
val5
AOI0_OUT3 input is selected
0x5
val6
CMP0_OUT input is selected
0x6
val7
CMP1_OUT input is selected
0x7
val9
CTimer0_MAT0 input is selected
0x9
val10
CTimer0_MAT1 input is selected
0xA
val11
CTimer1_MAT0 input is selected
0xB
val12
CTimer1_MAT1 input is selected
0xC
val13
CTimer2_MAT0 input is selected
0xD
val14
CTimer2_MAT1 input is selected
0xE
val15
LPTMR0 input is selected
0xF
val17
TRIG_IN0 input is selected
0x11
val18
TRIG_IN1 input is selected
0x12
val19
TRIG_IN2 input is selected
0x13
val20
TRIG_IN3 input is selected
0x14
val21
TRIG_IN4 input is selected
0x15
val22
TRIG_IN5 input is selected
0x16
val23
TRIG_IN6 input is selected
0x17
val24
TRIG_IN7 input is selected
0x18
val25
GPIO0 Pin Event Trig 0 input is selected
0x19
val26
GPIO1 Pin Event Trig 0 input is selected
0x1A
val27
GPIO2 Pin Event Trig 0 input is selected
0x1B
val28
GPIO3 Pin Event Trig 0 input is selected
0x1C
val42
WUU input is selected
0x2A
LPSPI0_TRIG
LPSPI0 trigger input connections
0x5E0
32
read-write
0x3F
0xFFFFFFFF
INP
LPSPI0 trigger input connections
0
6
read-write
val1
ARM_TXEV
0x1
val2
AOI0_OUT0 input is selected
0x2
val3
AOI0_OUT1 input is selected
0x3
val4
AOI0_OUT2 input is selected
0x4
val5
AOI0_OUT3 input is selected
0x5
val6
CMP0_OUT input is selected
0x6
val7
CMP1_OUT input is selected
0x7
val9
CTimer0_MAT1 input is selected
0x9
val10
CTimer0_MAT2 input is selected
0xA
val11
CTimer1_MAT1 input is selected
0xB
val12
CTimer1_MAT2 input is selected
0xC
val13
CTimer2_MAT1 input is selected
0xD
val14
CTimer2_MAT2 input is selected
0xE
val15
LPTMR0 input is selected
0xF
val17
TRIG_IN0 input is selected
0x11
val18
TRIG_IN1 input is selected
0x12
val19
TRIG_IN2 input is selected
0x13
val20
TRIG_IN3 input is selected
0x14
val21
TRIG_IN4 input is selected
0x15
val22
TRIG_IN5 input is selected
0x16
val23
TRIG_IN6 input is selected
0x17
val24
TRIG_IN7 input is selected
0x18
val25
GPIO0 Pin Event Trig 0 input is selected
0x19
val26
GPIO1 Pin Event Trig 0 input is selected
0x1A
val27
GPIO2 Pin Event Trig 0 input is selected
0x1B
val28
GPIO3 Pin Event Trig 0 input is selected
0x1C
val42
WUU input is selected
0x2A
LPSPI1_TRIG
LPSPI1 trigger input connections
0x600
32
read-write
0x3F
0xFFFFFFFF
INP
LPSPI1 trigger input connections
0
6
read-write
val1
ARM_TXEV
0x1
val2
AOI0_OUT0 input is selected
0x2
val3
AOI0_OUT1 input is selected
0x3
val4
AOI0_OUT2 input is selected
0x4
val5
AOI0_OUT3 input is selected
0x5
val6
CMP0_OUT input is selected
0x6
val7
CMP1_OUT input is selected
0x7
val9
CTimer0_MAT1 input is selected
0x9
val10
CTimer0_MAT2 input is selected
0xA
val11
CTimer1_MAT1 input is selected
0xB
val12
CTimer1_MAT2 input is selected
0xC
val13
CTimer2_MAT1 input is selected
0xD
val14
CTimer2_MAT2 input is selected
0xE
val15
LPTMR0 input is selected
0xF
val17
TRIG_IN0 input is selected
0x11
val18
TRIG_IN1 input is selected
0x12
val19
TRIG_IN2 input is selected
0x13
val20
TRIG_IN3 input is selected
0x14
val21
TRIG_IN4 input is selected
0x15
val22
TRIG_IN5 input is selected
0x16
val23
TRIG_IN6 input is selected
0x17
val24
TRIG_IN7 input is selected
0x18
val25
GPIO0 Pin Event Trig 0 input is selected
0x19
val26
GPIO1 Pin Event Trig 0 input is selected
0x1A
val27
GPIO2 Pin Event Trig 0 input is selected
0x1B
val28
GPIO3 Pin Event Trig 0 input is selected
0x1C
val42
WUU input is selected
0x2A
LPUART0
LPUART0 trigger input connections
0x620
32
read-write
0x3F
0xFFFFFFFF
INP
LPUART0 trigger input connections
0
6
read-write
val1
ARM_TXEV
0x1
val2
AOI0_OUT0 input is selected
0x2
val3
AOI0_OUT1 input is selected
0x3
val4
AOI0_OUT2 input is selected
0x4
val5
AOI0_OUT3 input is selected
0x5
val6
CMP0_OUT input is selected
0x6
val7
CMP1_OUT input is selected
0x7
val9
CTimer0_MAT2 input is selected
0x9
val10
CTimer0_MAT3 input is selected
0xA
val11
CTimer1_MAT2 input is selected
0xB
val12
CTimer1_MAT3 input is selected
0xC
val13
CTimer2_MAT2 input is selected
0xD
val14
CTimer2_MAT3 input is selected
0xE
val15
LPTMR0 input is selected
0xF
val17
TRIG_IN0 input is selected
0x11
val18
TRIG_IN1 input is selected
0x12
val19
TRIG_IN2 input is selected
0x13
val20
TRIG_IN3 input is selected
0x14
val21
TRIG_IN4 input is selected
0x15
val22
TRIG_IN5 input is selected
0x16
val23
TRIG_IN6 input is selected
0x17
val24
TRIG_IN7 input is selected
0x18
val25
TRIG_IN8 input is selected
0x19
val26
TRIG_IN9 input is selected
0x1A
val27
TRIG_IN10 input is selected
0x1B
val28
TRIG_IN11 input is selected
0x1C
val29
GPIO0 Pin Event Trig 0 input is selected
0x1D
val30
GPIO0 Pin Event Trig 0 input is selected
0x1E
val31
GPIO0 Pin Event Trig 0 input is selected
0x1F
val32
GPIO0 Pin Event Trig 0 input is selected
0x20
val34
WUU input is selected
0x22
val35
USB0 ipp_ind_uart_rxd_usbmux input is selected
0x23
LPUART1
LPUART1 trigger input connections
0x640
32
read-write
0x3F
0xFFFFFFFF
INP
LPUART1 trigger input connections
0
6
read-write
val1
ARM_TXEV
0x1
val2
AOI0_OUT0 input is selected
0x2
val3
AOI0_OUT1 input is selected
0x3
val4
AOI0_OUT2 input is selected
0x4
val5
AOI0_OUT3 input is selected
0x5
val6
CMP0_OUT input is selected
0x6
val7
CMP1_OUT input is selected
0x7
val9
CTimer0_MAT2 input is selected
0x9
val10
CTimer0_MAT3 input is selected
0xA
val11
CTimer1_MAT2 input is selected
0xB
val12
CTimer1_MAT3 input is selected
0xC
val13
CTimer2_MAT2 input is selected
0xD
val14
CTimer2_MAT3 input is selected
0xE
val15
LPTMR0 input is selected
0xF
val17
TRIG_IN0 input is selected
0x11
val18
TRIG_IN1 input is selected
0x12
val19
TRIG_IN2 input is selected
0x13
val20
TRIG_IN3 input is selected
0x14
val21
TRIG_IN4 input is selected
0x15
val22
TRIG_IN5 input is selected
0x16
val23
TRIG_IN6 input is selected
0x17
val24
TRIG_IN7 input is selected
0x18
val25
TRIG_IN8 input is selected
0x19
val26
TRIG_IN9 input is selected
0x1A
val27
TRIG_IN10 input is selected
0x1B
val28
TRIG_IN11 input is selected
0x1C
val29
GPIO0 Pin Event Trig 0 input is selected
0x1D
val30
GPIO0 Pin Event Trig 0 input is selected
0x1E
val31
GPIO0 Pin Event Trig 0 input is selected
0x1F
val32
GPIO0 Pin Event Trig 0 input is selected
0x20
val34
WUU input is selected
0x22
val35
USB0 ipp_ind_uart_rxd_usbmux input is selected
0x23
LPUART2
LPUART2 trigger input connections
0x660
32
read-write
0x3F
0xFFFFFFFF
INP
LPUART2 trigger input connections
0
6
read-write
val1
ARM_TXEV
0x1
val2
AOI0_OUT0 input is selected
0x2
val3
AOI0_OUT1 input is selected
0x3
val4
AOI0_OUT2 input is selected
0x4
val5
AOI0_OUT3 input is selected
0x5
val6
CMP0_OUT input is selected
0x6
val7
CMP1_OUT input is selected
0x7
val9
CTimer0_MAT2 input is selected
0x9
val10
CTimer0_MAT3 input is selected
0xA
val11
CTimer1_MAT2 input is selected
0xB
val12
CTimer1_MAT3 input is selected
0xC
val13
CTimer2_MAT2 input is selected
0xD
val14
CTimer2_MAT3 input is selected
0xE
val15
LPTMR0 input is selected
0xF
val17
TRIG_IN0 input is selected
0x11
val18
TRIG_IN1 input is selected
0x12
val19
TRIG_IN2 input is selected
0x13
val20
TRIG_IN3 input is selected
0x14
val21
TRIG_IN4 input is selected
0x15
val22
TRIG_IN5 input is selected
0x16
val23
TRIG_IN6 input is selected
0x17
val24
TRIG_IN7 input is selected
0x18
val25
TRIG_IN8 input is selected
0x19
val26
TRIG_IN9 input is selected
0x1A
val27
TRIG_IN10 input is selected
0x1B
val28
TRIG_IN11 input is selected
0x1C
val29
GPIO0 Pin Event Trig 0 input is selected
0x1D
val30
GPIO0 Pin Event Trig 0 input is selected
0x1E
val31
GPIO0 Pin Event Trig 0 input is selected
0x1F
val32
GPIO0 Pin Event Trig 0 input is selected
0x20
val34
WUU input is selected
0x22
val35
USB0 ipp_ind_uart_rxd_usbmux input is selected
0x23
I3C0
I3C
I3C
0x40002000
0
0x1000
registers
I3C0
24
MCONFIG
Controller Configuration
0
32
read-write
0
0xFFFFFFFF
MSTENA
Controller Enable
0
2
read-write
MASTER_OFF
CONTROLLER_OFF
0
MASTER_ON
CONTROLLER_ON
0x1
MASTER_CAPABLE
CONTROLLER_CAPABLE
0x2
I2C_MASTER_MODE
I2C_CONTROLLER_MODE
0x3
DISTO
Disable Timeout
3
1
read-write
ENABLE
Timeout enabled
0
DISABLE
Timeout disabled, if timeout is configured
0x1
HKEEP
High-Keeper
4
2
read-write
NONE
NONE
0
WIRED_IN
WIRED_IN
0x1
PASSIVE_SDA
PASSIVE_SDA
0x2
PASSIVE_ON_SDA_SCL
PASSIVE_ON_SDA_SCL
0x3
ODSTOP
Open Drain Stop
6
1
read-write
DISABLE
Disable open-drain stop. ODSTOP must be disabled when sending an HDR exit pattern.
0
ENABLE
Enable open-drain stop. STOP is emitted at open-drain speeds even for I3C messages. In legacy devices, this feature can ensure that the legacy devices see the STOP.
0x1
PPBAUD
Push-Pull Baud Rate
8
4
read-write
PPLOW
Push-Pull Low
12
4
read-write
ODBAUD
Open Drain Baud Rate
16
8
read-write
ODHPP
Open Drain High Push-Pull
24
1
read-write
DISABLE
ODHPP disabled. Open-Drain SCL High half-clock period is the same as the Open-Drain Low SCL half-period.
0
ENABLE
ODHPP enabled. Open-Drain High SCL half-lock period is one PPBAUD count for I3C messages. This setting is faster (and works for I3C devices). Any legacy I2C devices on the bus will not see the SCL High at all (less than the spike filter period).
0x1
SKEW
Skew
25
3
read-write
I2CBAUD
I2C Baud Rate
28
4
read-write
SCONFIG
Target Configuration
0x4
32
read-write
0x170000
0xFFFFFFFF
SLVENA
Target Enable
0
1
read-write
DISABLE
Target ignores the I2C or I3C bus
0
ENABLE
Target can operate on the I2C or I3C bus
0x1
NACK
Not Acknowledge
1
1
read-write
DISABLE
Always NACK disable
0
ENABLE
Always NACK enable. The target rejects all requests to it, except for a Common Command Code (CCC) broadcast. NACK = 1 should be used with caution, because the controller may decide that the target is missing, if NACK is overused.
0x1
MATCHSS
Match START or STOP
2
1
read-write
DISABLE
Match START or STOP disable
0
ENABLE
Match START or STOP enable. START and STOP sticky SSTATUS bits only become 1 when SSTATUS[MATCHED] is 1. This setting allows START and STOP to be used to detect the end of a message to/from this target.
0x1
S0IGNORE
Ignore TE0/TE1 Errors
3
1
read-write
DISABLE
Do not ignore TE0/TE1 errors
0
ENABLE
Ignore TE0/TE1 errors. Target does not detect TE0 or TE1 errors, so it does not lock up waiting on an Exit Pattern. This setting should only be used when the bus does not use HDR mode.
0x1
HDROK
HDR OK
4
1
read-write
DISABLE
Disable HDR OK.
0
ENABLE
Enable HDR OK. Allow HDR-DDR and/or HDR-BT messaging if available by setting the corresponding SIDEXT[BCR] bit to say HDR is available, and the corresponding GETCAPS bit for DDR and/or BT bit permitting use.
0x1
OFFLINE
Offline
9
1
read-write
DISABLE
Disable
0
ENABLE
Enables wait to ensure the bus is not in HDR mode.
0x1
BAMATCH
Bus Available Match
16
8
read-write
SADDR
Static Address
25
7
read-write
SSTATUS
Target Status
0x8
32
read-write
0x1400
0xFFFFFFFF
STNOTSTOP
Status Not Stop
0
1
read-only
STOPPED
I3C module is in a STOP condition.
0
BUSY
The bus is busy (has activity).
0x1
STMSG
Status message
1
1
read-only
IDLE
Bus target not listening or responding.
0
BUSY
This bus target is listening to the bus traffic or responding.
0x1
STCCCH
Status Common Command Code Handler
2
1
read-only
IDLE
No CCC message is being handled.
0
BUSY
A CCC message is being handled automatically.
0x1
STREQRD
Status Request Read
3
1
read-only
IDLE
REQ in process is not an SDR read from this target.
0
BUSY
The REQ in process is an SDR read from this target, or an In-Band Interrupt (IBI) is being pushed out.
0x1
STREQWR
Status Request Write
4
1
read-only
IDLE
REQ in process is not SDR write data from the controller.
0
BUSY
REQ in process is SDR write data from the controller to this bus target (or all targets), but not in ENTDAA mode.
0x1
STDAA
Status Dynamic Address Assignment
5
1
read-only
NOT_IN_ENTDAA
Not in ENTDAA mode.
0
IN_ENTDAA
I3C bus is in Enter Dynamic Address Assignment (ENTDAA) mode, regardless of whether this bus target has a Dynamic Address or not.
0x1
STHDR
Status High Data Rate
6
1
read-only
NOT_IN_HDR_DDR
I3C bus not in HDR-DDR mode
0
IN_HDR_DDR
The I3C bus is in HDR-DDR mode, regardless of whether HDR mode is supported by this module or not, and regardless of whether the message is to this module or to some other module.
0x1
START
Start
8
1
read-write
oneToClear
START_NOT_DETECTED
No START seen.
0
START_DETECTED
A START or repeated START was seen after the START bit was last cleared.
0x1
MATCHED
Matched
9
1
read-write
oneToClear
NOT_MATCHED
No header matched.
0
MATCHED
An incoming header matched the I3C Dynamic or I2C Static address of this device (if any) since the bus was last cleared.
0x1
STOP
Stop
10
1
read-write
oneToClear
NO_STOP_DETECTED
No STOP detected.
0
STOP_DETECTED
Stopped state detected. A STOP state was present on the bus since the bus was last cleared.
0x1
RX_PEND
Received Message Pending
11
1
read-only
NO_MSG_PENDING
No received message is pending.
0
MSG_PENDING
Received message is pending.
0x1
TXNOTFULL
Transmit Buffer Is Not Full
12
1
read-only
FULL
Transmit buffer full
0
NOT_FULL
Transmit buffer not full
0x1
DACHG
Dynamic Address Change
13
1
read-write
oneToClear
NO_CHANGE_DETECTED
No DA change detected.
0
CHANGE_DETECTED
DA change detected. The target DA has been assigned, re-assigned, or reset (lost) and is now in the state of being valid or none.
0x1
CCC
Common Command Code
14
1
read-write
oneToClear
NO_CCC_RECEIVED
No CCC received.
0
CCC_RECEIVED
CCC received.
0x1
ERRWARN
Error Warning
15
1
read-only
HDRMATCH
High Data Rate Command Match
16
1
read-write
oneToClear
NO_MATCH
HDR command did not match.
0
MATCH
HDR command matched the I3C Dynamic Address of this device.
0x1
CHANDLED
Common Command Code Handled
17
1
read-write
oneToClear
NOT_HANDLED
CCC handling not in progress.
0
HANDLED
CCC handling in progress.
0x1
EVENT
Event
18
1
read-write
oneToClear
NO_EVENT
No event has occurred.
0
EVENT
An IBI, CR, or HJ has occurred.
0x1
EVDET
Event Details
20
2
read-only
NONE
NONE
0
NO_REQUEST
NO_REQUEST
0x1
NACKED
NACKED
0x2
ACKED
ACKED
0x3
IBIDIS
In-Band Interrupts Are Disabled
24
1
read-only
INTERRUPTS_ENABLED
In-Band Interrupts not disabled
0
INTERRUPTS_DISABLED
In-Band Interrupts disabled
0x1
MRDIS
Controller Requests Are Disabled
25
1
read-only
MR_ENABLED
Controller Requests not disabled
0
MR_DISABLED
Controller Requests disabled
0x1
HJDIS
Hot-Join Disabled
27
1
read-only
MR_ENABLED
Hot-Join not disabled
0
MR_DISABLED
Hot-Join disabled
0x1
ACTSTATE
Activity State from Common Command Codes (CCC)
28
2
read-only
NO_LATENCY
NO_LATENCY
0
LATENCY_1MS
LATENCY_1MS
0x1
LATENCY_100MS
LATENCY_100MS
0x2
LATENCY_10S
LATENCY_10S
0x3
TIMECTRL
Time Control
30
2
read-only
NO_TIME_CONTROL
NO_TIME_CONTROL
0
SYNC
SYNC_MODE
0x1
ASYNC_MODE
ASYNC_MODE
0x2
BOTHSYNCASYNC
BOTHSYNCASYNC
0x3
SCTRL
Target Control
0xC
32
read-write
0
0xFFFFFFFF
EVENT
Event
0
2
read-write
NORMAL_MODE
NORMAL_MODE
0
IBI
IBI
0x1
MASTER_REQUEST
CONTROLLER_REQUEST
0x2
HOT_JOIN_REQUEST
HOT_JOIN_REQUEST
0x3
EXTDATA
Extended Data
3
1
read-write
DISABLE
Extended data disabled.
0
ENABLE
Extended data enabled. After IBIDATA is emitted, extended data is taken from IBIEXT1 and IBIEXT2 if configured.
0x1
IBIDATA
In-Band Interrupt Data
8
8
read-write
PENDINT
Pending Interrupt
16
4
read-write
ACTSTATE
Activity State of Target
20
2
read-write
VENDINFO
Vendor Information
24
8
read-write
SINTSET
Target Interrupt Set
0x10
32
read-write
0
0xFFFFFFFF
oneToSet
START
Start Interrupt Enable
8
1
read-write
oneToSet
DISABLE
Disable START interrupt
0
ENABLE
Enable START interrupt
0x1
MATCHED
Match Interrupt Enable
9
1
read-write
oneToSet
DISABLE
Disable match interrupt
0
ENABLE
Enable match interrupt
0x1
STOP
Stop Interrupt Enable
10
1
read-write
oneToSet
DISABLE
Disable STOP interrupt
0
ENABLE
Enable STOP interrupt
0x1
RXPEND
Receive Interrupt Enable
11
1
read-write
oneToSet
DISABLE
Disable Receive interrupt
0
ENABLE
Enable Receive interrupt
0x1
TXSEND
Transmit Interrupt Enable
12
1
read-write
oneToSet
DISABLE
Disable Transmit interrupt
0
ENABLE
Enable Transmit interrupt
0x1
DACHG
Dynamic Address Change Interrupt Enable
13
1
read-write
oneToSet
DISABLE
Disable DA Change interrupt
0
ENABLE
Enable DA Change interrupt
0x1
CCC
Common Command Code (CCC) Interrupt Enable
14
1
read-write
oneToSet
DISABLE
Disable CCC interrupt
0
ENABLE
Enable CCC interrupt
0x1
ERRWARN
Error or Warning Interrupt Enable
15
1
read-write
oneToSet
DISABLE
Disable error or warning interrupt
0
ENABLE
Enable error or warning interrupt
0x1
DDRMATCHED
Double Data Rate Interrupt Enable
16
1
read-write
oneToSet
DISABLE
Disable DDR interrupt
0
ENABLE
Enable DDR interrupt
0x1
CHANDLED
Common Command Code (CCC) Interrupt Enable
17
1
read-write
oneToSet
DISABLE
Disable CCC Handled interrupt
0
ENABLE
Enable CCC Handled interrupt
0x1
EVENT
Event Interrupt Enable
18
1
read-write
oneToSet
DISABLE
Disable Event interrupt
0
ENABLE
Enable Event interrupt
0x1
SINTCLR
Target Interrupt Clear
0x14
32
read-write
0
0
oneToClear
START
START Interrupt Enable Clear
8
1
read-write
oneToClear
MATCHED
MATCHED Interrupt Enable Clear
9
1
read-write
oneToClear
STOP
STOP Interrupt Enable Clear
10
1
read-write
oneToClear
RXPEND
RXPEND Interrupt Enable Clear
11
1
read-write
oneToClear
TXSEND
TXSEND Interrupt Enable Clear
12
1
read-write
oneToClear
DACHG
DACHG Interrupt Enable Clear
13
1
read-write
oneToClear
CCC
CCC Interrupt Enable Clear
14
1
read-write
oneToClear
ERRWARN
ERRWARN Interrupt Enable Clear
15
1
read-write
oneToClear
DDRMATCHED
DDRMATCHED Interrupt Enable Clear
16
1
read-write
oneToClear
CHANDLED
CHANDLED Interrupt Enable Clear
17
1
read-write
oneToClear
EVENT
EVENT Interrupt Enable Clear
18
1
read-write
oneToClear
SINTMASKED
Target Interrupt Mask
0x18
32
read-only
0
0xFFFFFFFF
START
START interrupt mask
8
1
read-only
MATCHED
MATCHED Interrupt Mask
9
1
read-only
STOP
STOP Interrupt Mask
10
1
read-only
RXPEND
RXPEND Interrupt Mask
11
1
read-only
TXSEND
TXSEND Interrupt Mask
12
1
read-only
DACHG
DACHG Interrupt Mask
13
1
read-only
CCC
CCC Interrupt Mask
14
1
read-only
ERRWARN
ERRWARN Interrupt Mask
15
1
read-only
DDRMATCHED
DDRMATCHED Interrupt Mask
16
1
read-only
CHANDLED
CHANDLED Interrupt Mask
17
1
read-only
EVENT
EVENT Interrupt Mask
18
1
read-only
SERRWARN
Target Errors and Warnings
0x1C
32
read-write
0
0xFFFFFFFF
oneToClear
ORUN
Overrun Error
0
1
read-write
oneToClear
NO_ERROR
No overrun error
0
ERROR
Overrun error
0x1
URUN
Underrun Error
1
1
read-write
oneToClear
NO_ERROR
No underrun error
0
ERROR
Underrun error
0x1
URUNNACK
Underrun and Not Acknowledged (NACKED) Error
2
1
read-write
oneToClear
NO_ERROR
No underrun and not acknowledged error
0
ERROR
Underrun and not acknowledged error
0x1
TERM
Terminated Error
3
1
read-write
oneToClear
NO_ERROR
No terminated error
0
ERROR
Terminated error
0x1
INVSTART
Invalid Start Error
4
1
read-write
oneToClear
NO_ERROR
No invalid start error
0
ERROR
Invalid start error
0x1
SPAR
SDR Parity Error
8
1
read-write
oneToClear
NO_ERROR
No SDR Parity error
0
ERROR
SDR Parity error
0x1
HPAR
HDR Parity Error
9
1
read-write
oneToClear
NO_ERROR
No HDR Parity error
0
ERROR
HDR Parity error
0x1
HCRC
HDR-DDR CRC Error
10
1
read-write
oneToClear
NO_ERROR
No HDR-DDR CRC error
0
ERROR
HDR-DDR CRC error
0x1
S0S1
TE0 or TE1 Error
11
1
read-write
oneToClear
NO_ERROR
No TE0 or TE1 error
0
ERROR
TE0 or TE1 error
0x1
OREAD
Over-read Error
16
1
read-write
oneToClear
NO_ERROR
No Over-read error
0
ERROR
Over-read error
0x1
OWRITE
Over-write Error
17
1
read-write
oneToClear
NO_ERROR
No Overwrite error
0
ERROR
Overwrite error
0x1
SDMACTRL
Target DMA Control
0x20
32
read-write
0x10
0xFFFFFFFF
DMAFB
DMA Read (From-bus) Trigger
0
2
read-write
NOT_USED
DMA not used
0
ENABLE_ONE_FRAME
DMA is enabled for one frame
0x1
ENABLE
DMA enabled until turned off
0x2
DMATB
DMA Write (To-bus) Trigger
2
2
read-write
NOT_USED
DMA not used
0
ENABLE_ONE_FRAME
DMA enabled for one frame (ended by DMA or terminated)
0x1
ENABLE
DMA enabled until turned off
0x2
DMAWIDTH
Width of DMA Operations
4
2
read-write
BYTE_0
Byte
0
BYTE_1
Byte
0x1
HALF_WORD
Half word (16 bits)
0x2
SDATACTRL
Target Data Control
0x2C
32
read-write
0x80000030
0xFFFFFFFF
FLUSHTB
Flush the To-bus Buffer or FIFO
0
1
write-only
FLUSHFB
Flush the From-bus Buffer or FIFO
1
1
write-only
UNLOCK
Unlock
3
1
write-only
DISABLED
RXTRIG and TXTRIG fields cannot be changed on a write.
0
ENABLED
RXTRIG and TXTRIG fields can be changed on a write.
0x1
TXTRIG
Transmit Trigger Level
4
2
read-write
TRIGGREMPTY
Trigger when empty
0
TRIGGRONEFOURTH
Trigger when 1/4 full or less
0x1
TRIGGRONEHALF
Trigger when 1/2 full or less
0x2
TRIGGRONELESS
Default. Trigger when 1 less than full or less
0x3
RXTRIG
Receive Trigger Level
6
2
read-write
TRIGGRNOTEMPTY
Trigger when not empty
0
TRIGGRONEFOURTH
Trigger when 1/4 or more full
0x1
TRIGGRONEHALF
Trigger when 1/2 or more full
0x2
TRIGGRTHREEFOURTHS
Trigger when 3/4 or more full
0x3
TXCOUNT
Count of Bytes in Transmit
16
5
read-only
RXCOUNT
Count of Bytes in Receive
24
5
read-only
TXFULL
Transmit Is Full
30
1
read-only
TXISNOTFULL
Not full
0
TXISFULL
Full
0x1
RXEMPTY
Receive Is Empty
31
1
read-only
RXISNOTEMPTY
Not empty
0
RXISEMPTY
Empty
0x1
SWDATAB
Target Write Data Byte
0x30
32
write-only
0
0
DATA
Data
0
8
write-only
END
End
8
1
write-only
NOT_END
Not the end. There are more bytes in the message.
0
END
End. This bit marks the last byte of the message.
0x1
END_ALSO
End Also
16
1
write-only
NOT_END
Not the end. There are more bytes in the message.
0
END
End. This bit marks the last byte of the message.
0x1
SWDATABE
Target Write Data Byte End
0x34
32
write-only
0
0
DATA
Data
0
8
write-only
SWDATAH
Target Write Data Half-word
0x38
32
write-only
0
0
DATA0
Data 0
0
8
write-only
DATA1
Data 1
8
8
write-only
END
End of message
16
1
write-only
NOT_END
Not the end. There are more bytes in the message.
0
END
End. This bit marks the last byte of the message.
0x1
SWDATAHE
Target Write Data Half-word End
0x3C
32
write-only
0
0
DATA0
Data 0
0
8
write-only
DATA1
Data 1
8
8
write-only
SRDATAB
Target Read Data Byte
0x40
32
read-only
0
0xFFFFFFFF
DATA0
Data 0
0
8
read-only
SRDATAH
Target Read Data Halfword
0x48
32
read-only
0
0xFFFF
LSB
The first byte read from the target
0
8
read-only
MSB
The second byte read from the target
8
8
read-only
SWDATAB1
Target Write Data Byte
SWDATA_B_H
0x54
32
write-only
0
0xFFFFFFFF
DATA
Data
0
8
write-only
SWDATAH1
Target Write Data Halfword
SWDATA_B_H
0x54
32
write-only
0
0xFFFFFFFF
DATA
Data
0
16
write-only
SCAPABILITIES2
Target Capabilities 2
0x5C
32
read-only
0x300
0xFFFFFFFF
MAPCNT
Map Count
0
4
read-only
I2C10B
I2C 10-bit Address
4
1
read-only
DISABLE
Does not support 10-bit I2C address
0
ENABLE
Supports 10-bit I2C address
0x1
I2CRST
I2C Software Reset
5
1
read-only
DISABLE
Does not support I2C software reset
0
ENABLE
Supports I2C software reset
0x1
I2CDEVID
I2C Device ID
6
1
read-only
DISABLE
Does not support I2C device ID
0
ENABLE
Supports I2C device ID
0x1
IBIEXT
In-Band Interrupt EXTDATA
8
1
read-only
DISABLE
Does not support IBIEXT
0
ENABLE
Supports IBIEXT
0x1
IBIXREG
In-Band Interrupt Extended Register
9
1
read-only
DISABLE
Does not support extended registers for IBIs
0
ENABLE
Supports extended registers for IBIs
0x1
SLVRST
Target Reset
17
1
read-only
DISABLE
Does not support Target Reset
0
ENABLE
Supports Target Reset
0x1
GROUP
Group
18
2
read-only
NOTSUPPORTED
Does not supports v1.1 Group addressing
0
ONE
Supports one group
0x1
TWO
Supports two groups
0x2
THREE
Supports three groups
0x3
AASA
Supports SETAASA
21
1
read-only
NOTSUPPORTED
Does not support SETAASA
0
SUPPORTED
Supports SETAASA
0x1
SSTSUB
Target-Target(s)-Tunnel Subscriber Capable
22
1
read-only
NOTSUPPORTED
Not subscriber capable
0
SUPPORTED
Subscriber capable
0x1
SSTWR
Target-Target(s)-Tunnel Write Capable
23
1
read-only
NOTSUPPORTED
Not write capable
0
SUPPORTED
Write capable
0x1
SCAPABILITIES
Target Capabilities
0x60
32
read-only
0xE83FFE70
0xFFFFFFFF
IDENA
ID 48b Handler
0
2
read-only
APPLICATION
Application
0
HW
Hardware
0x1
HW_BUT
Hardware, but the I3C module instance handles ID 48b
0x2
PARTNO
A part number register (PARTNO)
0x3
IDREG
ID Register
2
4
read-only
ALL_DISABLED
All ID register features below are disabled.
0
ID_INSTANCE
ID Instance is a register, and is used if there is no PARTNO register.
#xxx1
HDRSUPP
High Data Rate Support
6
2
read-only
NO_HDR
No HDR modes supported
0
DDR
Double Data Rate mode supported
0x1
MASTER
Controller
9
1
read-only
MASTERNOTSUPPORTED
Not supported
0
MASTERSUPPORTED
Supported
0x1
SADDR
Static Address
10
2
read-only
NO_STATIC
No static address
0
STATIC
Static address is fixed in hardware
0x1
HW_CONTROL
Hardware controls the static address dynamically (for example, from the pin strap)
0x2
CONFIG
SCONFIG register supplies the static address
0x3
CCCHANDLE
Common Command Codes Handling
12
4
read-only
ALL_DISABLED
All handling features below are disabled.
0
BLOCK_HANDLE
The block (I3C module) manages events, activities, status, HDR, and if enabled for it, ID and static-address-related items.
#xxx1
IBI_MR_HJ
In-Band Interrupts, Controller Requests, Hot-Join Events
16
5
read-only
ALL_DISABLED
Application cannot generate IBI, CR, or HJ.
0
IBI
Application can generate an IBI.
#xxxx1
TIMECTRL
Time Control
21
1
read-only
NO_TIME_CONTROL_TYPE
No time control enabled
0
ATLEAST1_TIME_CONTROL
At least one time-control type supported
0x1
EXTFIFO
External FIFO
23
3
read-only
NO_EXT_FIFO
No external FIFO is available
0
STD_EXT_FIFO
Standard available or free external FIFO
0x1
REQUEST_EXT_FIFO
Request track external FIFO
0x2
FIFOTX
FIFO Transmit
26
2
read-only
FIFO_2BYTE
Two
0
FIFO_4BYTE
Four
0x1
FIFO_8BYTE
Eight
0x2
FIFO_16BYTE
16 or larger
0x3
FIFORX
FIFO Receive
28
2
read-only
FIFO_2BYTE
Two or three
0
FIFO_4BYTE
Four
0x1
FIFO_8BYTE
Eight
0x2
FIFO_16BYTE
16 or larger
0x3
INT
Interrupts
30
1
read-only
INTERRUPTSNO
Not supported
0
INTERRUPTSYES
Supported
0x1
DMA
Direct Memory Access
31
1
read-only
DMANO
Not supported
0
DMAYES
Supported
0x1
SDYNADDR
Target Dynamic Address
0x64
32
read-write
0
0xFFFFFFFF
DAVALID
Dynamic Address Valid
0
1
read-write
DANOTASSIGNED
DANOTASSIGNED: a Dynamic Address is not assigned
0
DAASSIGNED
DAASSIGNED: a Dynamic Address is assigned
0x1
DADDR
Dynamic Address
1
7
read-write
MAPSA
Map a Static Address
12
1
write-only
SA10B
10bit Static Address
13
3
write-only
KEY
Key
16
16
read-write
SMAXLIMITS
Target Maximum Limits
0x68
32
read-write
0
0xFFFFFFFF
MAXRD
Maximum Read Length
0
12
read-write
MAXWR
Maximum Write Length
16
12
read-write
SIDPARTNO
Target ID Part Number
0x6C
32
read-write
0x30000000
0xFFFFFFFF
PARTNO
Part number
0
32
read-write
SIDEXT
Target ID Extension
0x70
32
read-write
0x66EF00
0xFFFFFFFF
DCR
Device Characteristic Register
8
8
read-write
BCR
Bus Characteristics Register
16
8
read-write
SVENDORID
Target Vendor ID
0x74
32
read-write
0x11B
0xFFFFFFFF
VID
Vendor ID
0
15
read-write
STCCLOCK
Target Time Control Clock
0x78
32
read-write
0x3014
0xFFFFFFFF
ACCURACY
Clock Accuracy
0
8
read-write
FREQ
Clock Frequency
8
8
read-write
SMSGMAPADDR
Target Message Map Address
0x7C
32
read-only
0
0xFFFFFFFF
MAPLAST
Matched Address Index
0
4
read-only
LASTSTATIC
Last Static Address Matched
4
1
read-only
I3C
I3C dynamic address
0
I2C
I2C static address
0x1
MAPLASTM1
Matched Previous Address Index 1
8
4
read-only
MAPLASTM2
Matched Previous Index 2
16
4
read-only
MCONFIG_EXT
Controller Extended Configuration
0x80
32
read-write
0
0xFFFFFFFF
I3C_CAS_DEL
I3C CAS Delay after START
16
2
read-write
NO_DELAY
No Delay
0
ONE_HALF_CLK
Increases SCL clock period by 1/2.
0x1
ONE_CLK
Increases SCL clock period by 1.
0x2
ONE_AND_ONE_HALF_CLK
Increases SCL clock period by 1 1/2.
0x3
I3C_CASR_DEL
I3C CAS Delay After Repeated START
18
2
read-write
NO_DELAY
No Delay
0
ONE_HALF_CLK
Increases SCL clock period by 1/2.
0x1
ONE_CLK
Increases SCL clock period by 1.
0x2
ONE_AND_ONE_HALF_CLK
Increases SCL clock period by 1 1/2.
0x3
MCTRL
Controller Control
0x84
32
read-write
0
0xFFFFFFFF
REQUEST
Request
0
3
read-write
NONE
NONE
0
EMITSTARTADDR
EMITSTARTADDR
0x1
EMITSTOP
EMITSTOP
0x2
IBIACKNACK
IBIACKNACK
0x3
PROCESSDAA
PROCESSDAA
0x4
FORCEEXIT
Force Exit and Target Reset
0x6
AUTOIBI
AUTOIBI
0x7
TYPE
Bus Type with EmitStartAddr
4
2
read-write
I3C
I3C
0
I2C
I2C
0x1
DDR
DDR
0x2
IBIRESP
In-Band Interrupt Response
6
2
read-write
ACK
ACK (acknowledge)
0
NACK
NACK (reject)
0x1
ACK_WITH_MANDATORY
Acknowledge with mandatory byte
0x2
MANUAL
Manual
0x3
DIR
Direction
8
1
read-write
DIRWRITE
Write
0
DIRREAD
Read
0x1
ADDR
Address
9
7
read-write
RDTERM
Read Terminate Counter
16
8
read-write
MSTATUS
Controller Status
0x88
32
read-write
0x1000
0xFFFFFFFF
STATE
State Of The Controller
0
3
read-only
IDLE
IDLE
0
SLVREQ
SLVREQ
0x1
MSGSDR
MSGSDR
0x2
NORMACT
NORMACT
0x3
DDR
MSGDDR
0x4
DAA
DAA
0x5
IBIACK
IBIACK
0x6
IBIRCV
IBIRCV
0x7
BETWEEN
Between
4
1
read-only
INACTIVE
Inactive
0
ACTIVE
Active
0x1
NACKED
Not Acknowledged
5
1
read-only
NOT_NACKED
Not NACKed
0
NACKED
NACKed (not acknowledged)
0x1
IBITYPE
In-Band Interrupt (IBI) Type
6
2
read-only
NONE
NONE
0
IBI
In-Band Interrupt
0x1
MR
Controller Request
0x2
HJ
Hot-Join
0x3
SLVSTART
Target Start
8
1
read-write
oneToClear
NOT_START
Target not requesting START
0
START
Target requesting START
0x1
MCTRLDONE
Controller Control Done
9
1
read-write
oneToClear
NOT_DONE
Not done
0
DONE
Done
0x1
COMPLETE
Complete
10
1
read-write
oneToClear
NOT_COMPLETE
Not complete
0
COMPLETE
Complete
0x1
RXPEND
RXPEND
11
1
read-only
IDLE
No receive message pending
0
PENDING
Receive message pending
0x1
TXNOTFULL
TX Buffer or FIFO Not Full
12
1
read-only
FULL
Receive buffer or FIFO full
0
NOTFULL
Receive buffer or FIFO not full
0x1
IBIWON
In-Band Interrupt (IBI) Won
13
1
read-write
oneToClear
NOT_WON
No IBI arbitration won
0
WON
IBI arbitration won
0x1
ERRWARN
Error Or Warning
15
1
read-only
NO_ERROR
No error or warning
0
ERROR
Error or warning
0x1
NOWMASTER
Module Is Now Controller
19
1
read-write
oneToClear
NOT_MASTER
Module has not become controller
0
MASTER
Module has become controller
0x1
IBIADDR
IBI Address
24
7
read-only
MIBIRULES
Controller In-band Interrupt Registry and Rules
0x8C
32
read-write
0
0xFFFFFFFF
ADDR0
ADDR0
0
6
read-write
ADDR1
ADDR1
6
6
read-write
ADDR2
ADDR2
12
6
read-write
ADDR3
ADDR3
18
6
read-write
ADDR4
ADDR4
24
6
read-write
MSB0
Most Significant Address Bit Is 0
30
1
read-write
DISABLE
MSB is not 0.
0
ENABLE
For all I3C dynamic addresses, MSB is 0.
0x1
NOBYTE
No IBI byte
31
1
read-write
IBIBYTE
With mandatory IBI byte
0
NO_IBIBYTE
Without mandatory IBI byte
0x1
MINTSET
Controller Interrupt Set
0x90
32
read-write
0
0xFFFFFFFF
oneToSet
SLVSTART
Target Start Interrupt Enable
8
1
read-write
oneToSet
DISABLE
Disable
0
ENABLE
Enable
0x1
MCTRLDONE
Controller Control Done Interrupt Enable
9
1
read-write
oneToSet
DISABLE
Disable
0
ENABLE
Enable
0x1
COMPLETE
Completed Message Interrupt Enable
10
1
read-write
oneToSet
DISABLE
Disable
0
ENABLE
Enable
0x1
RXPEND
Receive Pending Interrupt Enable
11
1
read-write
oneToSet
TXNOTFULL
Transmit Buffer/FIFO is not full interrupt enable
12
1
read-write
oneToSet
DISABLE
Disable
0
ENABLE
Enable
0x1
IBIWON
In-Band Interrupt (IBI) Won Interrupt Enable
13
1
read-write
oneToSet
DISABLE
Disable
0
ENABLE
Enable
0x1
ERRWARN
Error or Warning (ERRWARN) Interrupt Enable
15
1
read-write
oneToSet
DISABLE
Disable
0
ENABLE
Enable
0x1
NOWMASTER
Now Controller (now this I3C module is a controller) Interrupt Enable
19
1
read-write
oneToSet
DISABLE
Disable
0
ENABLE
Enable
0x1
MINTCLR
Controller Interrupt Clear
0x94
32
read-write
0
0
oneToClear
SLVSTART
SLVSTART Interrupt Enable Clear
8
1
read-write
oneToClear
NONE
No effect
0
CLEAR
Corresponding interrupt enable becomes 0
0x1
MCTRLDONE
MCTRLDONE Interrupt Enable Clear
9
1
read-write
oneToClear
NONE
No effect
0
CLEAR
Corresponding interrupt enable becomes 0
0x1
COMPLETE
COMPLETE Interrupt Enable Clear
10
1
read-write
oneToClear
NONE
No effect
0
CLEAR
Corresponding interrupt enable becomes 0
0x1
RXPEND
RXPEND Interrupt Enable Clear
11
1
read-write
oneToClear
NONE
No effect
0
CLEAR
Corresponding interrupt enable becomes 0
0x1
TXNOTFULL
TXNOTFULL Interrupt Enable Clear
12
1
read-write
oneToClear
NONE
No effect
0
CLEAR
Corresponding interrupt enable becomes 0
0x1
IBIWON
IBIWON Interrupt Enable Clear
13
1
read-write
oneToClear
NONE
No effect
0
CLEAR
Corresponding interrupt enable becomes 0
0x1
ERRWARN
ERRWARN Interrupt Enable Clear
15
1
read-write
oneToClear
NONE
No effect
0
CLEAR
Corresponding interrupt enable becomes 0
0x1
NOWMASTER
NOWCONTROLLER Interrupt Enable Clear
19
1
read-write
oneToClear
NONE
No effect
0
CLEAR
Corresponding interrupt enable becomes 0
0x1
MINTMASKED
Controller Interrupt Mask
0x98
32
read-only
0
0xFFFFFFFF
SLVSTART
SLVSTART Interrupt Mask
8
1
read-only
NOT_ENABLED
Interrupt not enabled and/or not active
0
ENABLED
Interrupt enabled and active
0x1
MCTRLDONE
MCTRLDONE Interrupt Mask
9
1
read-only
NOT_ENABLED
Interrupt not enabled and/or not active
0
ENABLED
Interrupt enabled and active
0x1
COMPLETE
COMPLETE Interrupt Mask
10
1
read-only
NOT_ENABLED
Interrupt not enabled and/or not active
0
ENABLED
Interrupt enabled and active
0x1
RXPEND
RXPEND Interrupt Mask
11
1
read-only
TXNOTFULL
TXNOTFULL Interrupt Mask
12
1
read-only
NOT_ENABLED
Interrupt not enabled and/or not active
0
ENABLED
Interrupt enabled and active
0x1
IBIWON
IBIWON Interrupt Mask
13
1
read-only
NOT_ENABLED
Interrupt not enabled and/or not active
0
ENABLED
Interrupt enabled and active
0x1
ERRWARN
ERRWARN Interrupt Mask
15
1
read-only
NOT_ENABLED
Interrupt not enabled and/or not active
0
ENABLED
Interrupt enabled and active
0x1
NOWMASTER
NOWCONTROLLER Interrupt Mask
19
1
read-only
NOT_ENABLED
Interrupt not enabled and/or not active
0
ENABLED
Interrupt enabled and active
0x1
MERRWARN
Controller Errors and Warnings
0x9C
32
read-write
0
0xFFFFFFFF
oneToClear
URUN
Underrun error
1
1
read-write
oneToClear
NO_ERROR
No error
0
ERROR
Error
0x1
NACK
Not Acknowledge Error
2
1
read-write
oneToClear
NO_ERROR
No error
0
ERROR
Error
0x1
WRABT
Write Abort Error
3
1
read-write
oneToClear
NO_ERROR
No error
0
ERROR
Error
0x1
TERM
Terminate Error
4
1
read-write
oneToClear
NO_ERROR
No error
0
ERROR
Error
0x1
HPAR
High Data Rate Parity
9
1
read-write
oneToClear
NO_ERROR
No error
0
ERROR
Error
0x1
HCRC
High Data Rate CRC Error
10
1
read-write
oneToClear
NO_ERROR
No error
0
ERROR
Error
0x1
OREAD
Over-read Error
16
1
read-write
oneToClear
NO_ERROR
No error
0
ERROR
Error
0x1
OWRITE
Over-write Error
17
1
read-write
oneToClear
NO_ERROR
No error
0
ERROR
Error
0x1
MSGERR
Message Error
18
1
read-write
oneToClear
NO_ERROR
No error
0
ERROR
Error
0x1
INVREQ
Invalid Request Error
19
1
read-write
oneToClear
NO_ERROR
No error
0
ERROR
Error
0x1
TIMEOUT
Timeout Error
20
1
read-write
oneToClear
NO_ERROR
No error
0
ERROR
Error
0x1
MDMACTRL
Controller DMA Control
0xA0
32
read-write
0x10
0xFFFFFFFF
DMAFB
DMA From Bus
0
2
read-write
NOT_USED
DMA is not used
0
ENABLE_ONE_FRAME
Enable DMA for one frame
0x1
ENABLE
Enable DMA until DMA is turned off
0x2
DMATB
DMA To Bus
2
2
read-write
NOT_USED
DMA is not used
0
ENABLE_ONE_FRAME
Enable DMA for one frame (ended by DMA or Terminated)
0x1
ENABLE
Enable DMA until DMA is turned off
0x2
DMAWIDTH
DMA Width
4
2
read-write
BYTE_0
Byte
0
BYTE_1
Byte
0x1
HALF_WORD
Halfword (16 bits)
0x2
MDATACTRL
Controller Data Control
0xAC
32
read-write
0x80000030
0xFFFFFFFF
FLUSHTB
Flush To-bus Buffer or FIFO
0
1
write-only
NO_ACTION
No action
0
FLUSH
Flush the buffer
0x1
FLUSHFB
Flush From-bus Buffer or FIFO
1
1
write-only
NO_ACTION
No action
0
FLUSH
Flush the buffer
0x1
UNLOCK
Unlock
3
1
write-only
DISABLED
Locked. RXTRIG and TXTRIG fields cannot be changed on a write.
0
ENABLED
Unlocked. RXTRIG and TXTRIG fields can be changed on a write.
0x1
TXTRIG
Transmit Trigger Level
4
2
read-write
EMPTY
Trigger when empty
0
QUARTER_OR_LESS
Trigger when 1/4 full or less
0x1
HALF_OR_LESS
Trigger when 1/2 full or less
0x2
FULL_OR_LESS
Default. Trigger when 1 less than full or less
0x3
RXTRIG
Receive Trigger Level
6
2
read-write
NOT_EMPTY
Trigger when not empty
0
QUARTER_OR_MORE
Trigger when 1/4 full or more
0x1
HALF_OR_MORE
Trigger when 1/2 full or more
0x2
THREE_QUARTER_OR_MORE
Trigger when 3/4 full or more
0x3
TXCOUNT
Transmit Byte Count
16
5
read-only
RXCOUNT
Receive Byte Count
24
5
read-only
TXFULL
Transmit Is Full
30
1
read-only
NOT_FULL
Transmit FIFO or buffer is not yet full.
0
FULL
Transmit FIFO or buffer is full.
0x1
RXEMPTY
Receive Is Empty
31
1
read-only
NOT_EMPTY
Receive FIFO or buffer is not yet empty.
0
EMPTY
Receive FIFO or buffer is empty.
0x1
MWDATAB
Controller Write Data Byte
0xB0
32
write-only
0
0
VALUE
Data Byte
0
8
write-only
END
End of Message
8
1
write-only
NOT_END
Not the end. More bytes are assumed to be in the message.
0
END
End. The END bit marks the last byte of the message.
0x1
END_ALSO
End of Message Also
16
1
write-only
NOT_END
Not the end. More bytes are assumed to be in the message.
0
END
End. The END bit marks the last byte of the message.
0x1
MWDATABE
Controller Write Data Byte End
0xB4
32
write-only
0
0
VALUE
Data
0
8
write-only
MWDATAH
Controller Write Data Halfword
0xB8
32
write-only
0
0
DATA0
Data Byte 0
0
8
write-only
DATA1
Data Byte 1
8
8
write-only
END
End of message
16
1
write-only
NOT_END
Not the end. More bytes are assumed to be in the message.
0
END
End. The END bit marks the last byte of the message.
0x1
MWDATAHE
Controller Write Data Halfword End
0xBC
32
write-only
0
0
DATA0
Data Byte 0
0
8
write-only
DATA1
Data Byte 1
8
8
write-only
MRDATAB
Controller Read Data Byte
0xC0
32
read-only
0
0xFFFFFFFF
VALUE
Value
0
8
read-only
MRDATAH
Controller Read Data Halfword
0xC8
32
read-only
0
0xFFFFFFFF
LSB
LSB
0
8
read-only
MSB
MSB
8
8
read-only
MWDATAB1
Controller Write Byte Data 1(to bus)
MWDATA_B1_H1
0xCC
32
write-only
0
0xFFFFFFFF
VALUE
Value
0
8
write-only
MWDATAH1
Controller Write Halfword Data (to bus)
MWDATA_B1_H1
0xCC
32
write-only
0
0xFFFFFFFF
VALUE
Value
0
16
write-only
MWMSG_SDR_CONTROL
Controller Write Message Control in SDR mode
MWMSG_SDR
0xD0
32
write-only
0
0
DIR
Direction
0
1
write-only
WRITE
Write
0
READ
Read
0x1
ADDR
Address
1
7
write-only
END
End of SDR Message
8
1
write-only
NOT_END
Not the end. SDR message ends waiting for a new SDR message (issues a repeated START for a new message).
0
END
End. SDR message ends at the STOP.
0x1
I2C
I2C
10
1
write-only
I3CMESSAGE
I3C message
0
I2CMESSAGE
I2C message
0x1
LEN
Length
11
5
write-only
MWMSG_SDR_DATA
Controller Write Message Data in SDR mode
MWMSG_SDR
0xD0
32
write-only
0
0xFFFFFFFF
DATA16B
Data
0
16
write-only
MRMSG_SDR
Controller Read Message in SDR mode
0xD4
32
read-only
0
0xFFFFFFFF
DATA
Data
0
16
read-only
MWMSG_DDR_CONTROL
Controller Write Message in DDR mode: First Control Word
MWMSG_DDR
0xD8
32
write-only
0
0
ADDRCMD
Address Command
0
16
write-only
MWMSG_DDR_CONTROL2
Controller Write Message in DDR mode Control 2
MWMSG_DDR
0xD8
32
write-only
0
0
LEN
Length of Message
0
10
write-only
END
End of message
14
1
write-only
NOT_END
Not the end. DDR message ends waiting for a new DDR message (will issue a HDR Restart for the new message).
0
END
End. DDR message ends on HDR Exit.
0x1
MWMSG_DDR_DATA
Controller Write Message Data in DDR mode
MWMSG_DDR
0xD8
32
write-only
0
0xFFFFFFFF
DATA16B
Data
0
16
write-only
MRMSG_DDR
Controller Read Message in DDR mode
0xDC
32
read-only
0
0xFFFFFFFF
DATA
Data
0
16
read-only
MDYNADDR
Controller Dynamic Address
0xE4
32
read-write
0
0xFFFFFFFF
DAVALID
Dynamic address valid
0
1
read-write
NO_VALID
No valid DA assigned
0
VALID
Valid DA assigned
0x1
DADDR
Dynamic address
1
7
read-write
SMAPCTRL0
Map Feature Control 0
0x11C
32
read-only
0
0xFFFFFFFF
ENA
Enable Primary Dynamic Address
0
1
read-only
DISABLE
Disable
0
ENABLE
Enable
0x1
DA
Dynamic Address
1
7
read-only
CAUSE
Cause
8
3
read-only
NONE
No information. This value occurs when not configured to write DA.
0
ENTDAA
Set using ENTDAA
0x1
SETDASA
Set using SETDASA, SETAASA, or SETNEWDA
0x2
RSTDAA
Cleared using RSTDAA
0x3
AUTOMAP
Auto MAP change happened last. The change may have changed this DA as well (for example, ENTDAA, and SETAASA), but at least one MAP entry automatically changed after.
0x4
IBIEXT1
Extended IBI Data 1
0x140
32
read-write
0x70
0xFFFFFFFF
CNT
Count
0
3
read-write
MAX
Maximum
4
3
read-only
EXT1
Extra byte 1
8
8
read-write
EXT2
Extra byte 2
16
8
read-write
EXT3
Extra byte 3
24
8
read-write
IBIEXT2
Extended IBI Data 2
0x144
32
read-write
0
0xFFFFFFFF
EXT4
Extra byte 4
0
8
read-write
EXT5
Extra byte 5
8
8
read-write
EXT6
Extra byte 6
16
8
read-write
EXT7
Extra byte 7
24
8
read-write
SID
Target Module ID
0xFFC
32
read-only
0xEDCB0100
0xFFFFFFFF
ID
ID
0
32
read-only
CTIMER0
CTIMER
CTIMER
CTIMER
0x40004000
0
0x88
registers
CTIMER0
39
IR
Interrupt
0
32
read-write
0
0xFF
MR0INT
Interrupt Flag for Match Channel 0 Event
0
1
read-write
MR1INT
Interrupt Flag for Match Channel 1 Event
1
1
read-write
MR2INT
Interrupt Flag for Match Channel 2 Event
2
1
read-write
MR3INT
Interrupt Flag for Match Channel 3 Event
3
1
read-write
CR0INT
Interrupt Flag for Capture Channel 0 Event
4
1
read-write
CR1INT
Interrupt Flag for Capture Channel 1 Event
5
1
read-write
CR2INT
Interrupt Flag for Capture Channel 2 Event
6
1
read-write
CR3INT
Interrupt Flag for Capture Channel 3 Event
7
1
read-write
TCR
Timer Control
0x4
32
read-write
0
0x33
CEN
Counter Enable
0
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
CRST
Counter Reset Enable
1
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
AGCEN
Allow Global Count Enable
4
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
ATCEN
Allow Trigger Count Enable
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
TC
Timer Counter
0x8
32
read-write
0
0xFFFFFFFF
TCVAL
Timer Counter Value
0
32
read-write
PR
Prescale
0xC
32
read-write
0
0xFFFFFFFF
PRVAL
Prescale Reload Value
0
32
read-write
PC
Prescale Counter
0x10
32
read-write
0
0xFFFFFFFF
PCVAL
Prescale Counter Value
0
32
read-write
MCR
Match Control
0x14
32
read-write
0
0xF000FFF
MR0I
Interrupt on MR0
0
1
read-write
MR0I_0
Does not generate
0
MR0I_1
Generates
0x1
MR0R
Reset on MR0
1
1
read-write
MR0R_0
Does not reset
0
MR0R_1
Resets
0x1
MR0S
Stop on MR0
2
1
read-write
MR0S_0
Does not stop
0
MR0S_1
Stops
0x1
MR1I
Interrupt on MR1
3
1
read-write
MR1I_0
Does not generate
0
MR1I_1
Generates
0x1
MR1R
Reset on MR1
4
1
read-write
MR1R_0
Does not reset
0
MR1R_1
Resets
0x1
MR1S
Stop on MR1
5
1
read-write
MRIS_0
Does not stop
0
MRIS_1
Stops
0x1
MR2I
Interrupt on MR2
6
1
read-write
MR2I_0
Does not generate
0
MR2I_1
Generates
0x1
MR2R
Reset on MR2
7
1
read-write
MR2R_0
Does not reset
0
MR2R_1
Resets
0x1
MR2S
Stop on MR2
8
1
read-write
MR2S_0
Does not stop
0
MR2S_1
Stops
0x1
MR3I
Interrupt on MR3
9
1
read-write
MR3I_0
Does not generate
0
MR3I_1
Generates
0x1
MR3R
Reset on MR3
10
1
read-write
MR3R_0
Does not reset
0
MR3R_1
Resets
0x1
MR3S
Stop on MR3
11
1
read-write
MR3S_0
Does not stop
0
MR3S_1
Stops
0x1
MR0RL
Reload MR
24
1
read-write
MR0RL_0
Does not reload
0
MR0RL_1
Reloads
0x1
MR1RL
Reload MR
25
1
read-write
MR1RL_0
Does not reload
0
MR1RL_1
Reloads
0x1
MR2RL
Reload MR
26
1
read-write
MR2RL_0
Does not reload
0
MR2RL_1
Reloads
0x1
MR3RL
Reload MR
27
1
read-write
MR3RL_0
Does not reload
0
MR3RL_1
Reloads
0x1
4
0x4
MR[%s]
Match
0x18
32
read-write
0
0xFFFFFFFF
MATCH
Timer Counter Match Value
0
32
read-write
CCR
Capture Control
0x28
32
read-write
0
0xFFF
CAP0RE
Rising Edge of Capture Channel 0
0
1
read-write
CAP0RE_0
Does not load
0
CAPORE_1
Loads
0x1
CAP0FE
Falling Edge of Capture Channel 0
1
1
read-write
CAP0FE_0
Does not load
0
CAPOFE_1
Loads
0x1
CAP0I
Generate Interrupt on Channel 0 Capture Event
2
1
read-write
CAP0I_0
Does not generate
0
CAPOI_1
Generates
0x1
CAP1RE
Rising Edge of Capture Channel 1
3
1
read-write
CAP1RE_0
Does not load
0
CAP1RE_1
Loads
0x1
CAP1FE
Falling Edge of Capture Channel 1
4
1
read-write
CAP1FE_0
Does not load
0
CAP1FE_1
Loads
0x1
CAP1I
Generate Interrupt on Channel 1 Capture Event
5
1
read-write
CAP1I_0
Does not generates
0
CAP1I_1
Generates
0x1
CAP2RE
Rising Edge of Capture Channel 2
6
1
read-write
CAP2RE_0
Does not load
0
CAP2RE_1
Loads
0x1
CAP2FE
Falling Edge of Capture Channel 2
7
1
read-write
CAP2FE_0
Does not load
0
CAP2FE_1
Loads
0x1
CAP2I
Generate Interrupt on Channel 2 Capture Event
8
1
read-write
CAP2I_0
Does not generate
0
CAP2I_1
Generates
0x1
CAP3RE
Rising Edge of Capture Channel 3
9
1
read-write
CAP3RE_0
Does not load
0
CAP3RE_1
Loads
0x1
CAP3FE
Falling Edge of Capture Channel 3
10
1
read-write
CAP3FE_0
Does not load
0
CAP3FE_1
Loads
0x1
CAP3I
Generate Interrupt on Channel 3 Capture Event
11
1
read-write
CAP3I_0
Does not generate
0
CAP3I_1
Generates
0x1
4
0x4
CR[%s]
Capture
0x2C
32
read-only
0
0xFFFFFFFF
CAP
Timer Counter Capture Value
0
32
read-only
EMR
External Match
0x3C
32
read-write
0
0xFFF
EM0
External Match 0
0
1
read-write
CLEAR
Low
0
SET
High
0x1
EM1
External Match 1
1
1
read-write
CLEAR
Low
0
SET
High
0x1
EM2
External Match 2
2
1
read-write
CLEAR
Low
0
SET
High
0x1
EM3
External Match 3
3
1
read-write
CLEAR
Low
0
SET
High
0x1
EMC0
External Match Control 0
4
2
read-write
DO_NOTHING
Does nothing
0
CLEAR
Goes low
0x1
SET
Goes high
0x2
TOGGLE
Toggles
0x3
EMC1
External Match Control 1
6
2
read-write
DO_NOTHING
Does nothing
0
CLEAR
Goes low
0x1
SET
Goes high
0x2
TOGGLE
Toggles
0x3
EMC2
External Match Control 2
8
2
read-write
DO_NOTHING
Does nothing
0
CLEAR
Goes low
0x1
SET
Goes high
0x2
TOGGLE
Toggles
0x3
EMC3
External Match Control 3
10
2
read-write
DO_NOTHING
Does nothing
0
CLEAR
Goes low
0x1
SET
Goes high
0x2
TOGGLE
Toggles
0x3
CTCR
Count Control
0x70
32
read-write
0
0xFF
CTMODE
Counter Timer Mode
0
2
read-write
TIMER
Timer mode
0
COUNTER_RISING_EDGE
Counter mode rising edge
0x1
COUNTER_FALLING_EDGE
Counter mode falling edge
0x2
COUNTER_DUAL_EDGE
Counter mode dual edge
0x3
CINSEL
Count Input Select
2
2
read-write
CHANNEL_0
Channel 0, CAPn[0] for CTIMERn
0
CHANNEL_1
Channel 1, CAPn[1] for CTIMERn
0x1
CHANNEL_2
Channel 2, CAPn[2] for CTIMERn
0x2
CHANNEL_3
Channel 3, CAPn[3] for CTIMERn
0x3
ENCC
Capture Channel Enable
4
1
read-write
SELCC
Edge Select
5
3
read-write
CHANNEL_0_RISING
Capture channel 0 rising edge
0
CHANNEL_0_FALLING
Capture channel 0 falling edge
0x1
CHANNEL_1_RISING
Capture channel 1 rising edge
0x2
CHANNEL_1_FALLING
Capture channel 1 falling edge
0x3
CHANNEL_2_RISING
Capture channel 2 rising edge
0x4
CHANNEL_2_FALLING
Capture channel 2 falling edge
0x5
PWMC
PWM Control
0x74
32
read-write
0
0xF
PWMEN0
PWM Mode Enable for Channel 0
0
1
read-write
MATCH
Disable
0
PWM
Enable
0x1
PWMEN1
PWM Mode Enable for Channel 1
1
1
read-write
MATCH
Disable
0
PWM
Enable
0x1
PWMEN2
PWM Mode Enable for Channel 2
2
1
read-write
MATCH
Disable
0
PWM
Enable
0x1
PWMEN3
PWM Mode Enable for Channel 3
3
1
read-write
MATCH
Disable
0
PWM
Enable
0x1
4
0x4
MSR[%s]
Match Shadow
0x78
32
read-write
0
0xFFFFFFFF
MATCH_SHADOW
Timer Counter Match Shadow Value
0
32
read-write
CTIMER1
CTIMER
CTIMER
0x40005000
0
0x88
registers
CTIMER1
40
CTIMER2
CTIMER
CTIMER
0x40006000
0
0x88
registers
CTIMER2
41
FREQME0
FREQME
FREQME
0x40009000
0
0x10
registers
FREQME0
54
CTRL_R
Control (in Read mode)
FREQME
0
32
read-only
0
0xFFFFFFFF
RESULT
Indicates the measurement result-either the target clock counter value (for Frequency Measurement mode) or pulse width measurement (for Pulse Width Measurement mode)
0
31
read-only
MEASURE_IN_PROGRESS
Measurement In Progress
31
1
read-only
CYCLE_DONE
Complete
0
IN_PROGRESS
In progress
0x1
CTRL_W
Control (in Write mode)
FREQME
0
32
write-only
0
0xFFFFFFFF
REF_SCALE
Reference Clock Scaling Factor
0
5
write-only
PULSE_MODE
Pulse Width Measurement Mode Select
8
1
write-only
FREQ_ME_MODE
Frequency Measurement mode
0
PULSE_ME_MODE
Pulse Width Measurement mode
0x1
PULSE_POL
Pulse Polarity
9
1
write-only
HIGH_PERIOD
High period
0
LOW_PERIOD
Low period
0x1
LT_MIN_INT_EN
Less Than Minimum Interrupt Enable
12
1
write-only
DISABLE
Disable
0
ENABLE
Enable
0x1
GT_MAX_INT_EN
Greater Than Maximum Interrupt Enable
13
1
write-only
DISABLE
Disable
0
ENABLE
Enable
0x1
RESULT_READY_INT_EN
Result Ready Interrupt Enable
14
1
write-only
DISABLE
Disable
0
ENABLE
Enable
0x1
CONTINUOUS_MODE_EN
Continuous Mode Enable
30
1
write-only
DISABLE
Disable
0
ENABLE
Enable
0x1
MEASURE_IN_PROGRESS
Measurement In Progress
31
1
write-only
FORCE_TERMINATE
Terminates measurement
0
INITIATE_A_FREQME_CYCLE
Initiates measurement
0x1
CTRLSTAT
Control Status
0x4
32
read-write
0
0xFFFFFFFF
REF_SCALE
Reference Scale
0
5
read-only
PULSE_MODE
Pulse Mode
8
1
read-only
FREQ
Frequency Measurement mode
0
PULSE
Pulse Width Measurement mode
0x1
PULSE_POL
Pulse Polarity
9
1
read-only
HIGH
High period
0
LOW
Low period
0x1
LT_MIN_INT_EN
Less Than Minimum Interrupt Enable
12
1
read-only
DISABLED
Disabled
0
ENABLED
Enabled
0x1
GT_MAX_INT_EN
Greater Than Maximum Interrupt Enable
13
1
read-only
DISABLED
Disabled
0
ENABLED
Enabled
0x1
RESULT_READY_INT_EN
Result Ready Interrupt Enable
14
1
read-only
DISABLED
Disabled
0
ENABLED
Enabled
0x1
LT_MIN_STAT
Less Than Minimum Results Status
24
1
read-write
oneToClear
IN_RANGE
Greater than MIN[MIN_VALUE]
0
LT_MIN
Less than MIN[MIN_VALUE]
0x1
GT_MAX_STAT
Greater Than Maximum Result Status
25
1
read-write
oneToClear
IN_RANGE
Less than MAX[MAX_VALUE]
0
GT_MAX
Greater than MAX[MAX_VALUE]
0x1
RESULT_READY_STAT
Result Ready Status
26
1
read-write
oneToClear
NOT_COMPLETE
Not complete
0
COMPLETE
Complete
0x1
CONTINUOUS_MODE_EN
Continuous Mode Enable Status
30
1
read-only
DISABLED
Disabled
0
ENABLED
Enabled
0x1
MEASURE_IN_PROGRESS
Measurement in Progress Status
31
1
read-only
IDLE
Not in progress
0
ONGOING
In progress
0x1
MIN
Minimum
0x8
32
read-write
0
0xFFFFFFFF
MIN_VALUE
Minimum Value
0
31
read-write
MAX
Maximum
0xC
32
read-write
0x7FFFFFFF
0xFFFFFFFF
MAX_VALUE
Maximum Value
0
31
read-write
UTICK0
UTICK
UTICK
0x4000B000
0
0x20
registers
UTICK0
59
CTRL
Control
0
32
read-write
0
0xFFFFFFFF
DELAYVAL
Tick Interval
0
31
read-write
REPEAT
Repeat Delay
31
1
read-write
DELAYONCE
One-time delay
0
DELAYREPEATS
Delay repeats continuously
0x1
STAT
Status
0x4
32
read-write
0
0x3
INTR
Interrupt Flag
0
1
read-write
NOPENDINGINTERRUPT
Not pending
0
PENDINGINTERRUPT
Pending
0x1
ACTIVE
Timer Active Flag
1
1
read-write
oneToClear
TIMERISNOTACTIVE
Inactive (stopped)
0
TIMERISACTIVE
Active
0x1
CFG
Capture Configuration
0x8
32
read-write
0
0xF0F
CAPEN0
Enable Capture 0
0
1
read-write
CAPEN0ISDISABLED
Disable
0
CAPEN0ISENABLED
Enable
0x1
CAPEN1
Enable Capture 1
1
1
read-write
CAPEN1ISDISABLED
Disable
0
CAPEN1ISENABLED
Enable
0x1
CAPEN2
Enable Capture 2
2
1
read-write
CAPEN2ISDISABLED
Disable
0
CAPEN2ISENABLED
Enable
0x1
CAPEN3
Enable Capture 3
3
1
read-write
CAPEN3ISDISABLED
Disable
0
CAPEN3ISENABLED
Enable
0x1
CAPPOL0
Capture Polarity 0
8
1
read-write
CAPPOL0POSEDGECAPTURE
Positive
0
CAPPOL0NEGEDGECAPTURE
Negative
0x1
CAPPOL1
Capture-Polarity 1
9
1
read-write
CAPPOL1POSEDGECAPTURE
Positive
0
CAPPOL1NEGEDGECAPTURE
Negative
0x1
CAPPOL2
Capture Polarity 2
10
1
read-write
CAPPOL2POSEDGECAPTURE
Positive
0
CAPPOL2NEGEDGECAPTURE
Negative
0x1
CAPPOL3
Capture Polarity 3
11
1
read-write
CAPPOL3POSEDGECAPTURE
Positive
0
CAPPOL3NEGEDGECAPTURE
Negative
0x1
CAPCLR
Capture Clear
0xC
32
write-only
0
0
CAPCLR0
Clear Capture 0
0
1
write-only
CAPCLR0NOTHING
Does nothing
0
CAPCLR0CLEARED
Clears the CAP0 register value
0x1
CAPCLR1
Clear Capture 1
1
1
write-only
CAPCLR1NOTHING
Does nothing
0
CAPCLR1CLEARED
Clears the CAP1 register value
0x1
CAPCLR2
Clear Capture 2
2
1
write-only
CAPCLR2NOTHING
Does nothing
0
CAPCLR2CLEARED
Clears the CAP2 register value
0x1
CAPCLR3
Clear Capture 3
3
1
write-only
CAPCLR3NOTHING
Does nothing
0
CAPCLR3CLEARED
Clears the CAP3 register value
0x1
4
0x4
CAP[%s]
Capture
0x10
32
read-only
0
0xFFFFFFFF
CAP_VALUE
Captured Value for the Related Capture Event
0
31
read-only
VALID
Captured Value Valid Flag
31
1
read-only
NOTVALID
Valid value not captured
0
VALID
Valid value captured
0x1
WWDT0
WWDT
WWDT
0x4000C000
0
0x1C
registers
WWDT0
60
MOD
Mode
0
32
read-write
0
0xFFFFFFFF
WDEN
Watchdog Enable
0
1
read-write
STOP
Timer stopped
0
RUN
Timer running
0x1
WDRESET
Watchdog Reset Enable
1
1
read-write
INTERRUPT
Interrupt
0
RESET
Reset
0x1
WDTOF
Watchdog Timeout Flag
2
1
read-write
CLEAR
Watchdog event has not occurred.
0
RESET
Watchdog event has occurred (causes a chip reset if WDRESET = 1).
0x1
WDINT
Warning Interrupt Flag
3
1
read-write
oneToClear
NO_FLAG
No flag
0
FLAG
Flag
0x1
WDPROTECT
Watchdog Update Mode
4
1
read-write
FLEXIBLE
Flexible
0
THRESHOLD
Threshold
0x1
LOCK
Lock
5
1
read-write
NO_LOCK
No Lock
0
LOCK
Lock
0x1
DEBUG_EN
Debug Enable
6
1
read-write
DISABLE
Disabled
0
ENABLE
Enabled
0x1
TC
Timer Constant
0x4
32
read-write
0xFF
0xFFFFFFFF
COUNT
Watchdog Timeout Value
0
24
read-write
FEED
Feed Sequence
0x8
32
write-only
0
0
FEED
Feed Value
0
8
write-only
TV
Timer Value
0xC
32
read-only
0xFF
0xFFFFFFFF
COUNT
Counter Timer Value
0
24
read-only
WARNINT
Warning Interrupt Compare Value
0x14
32
read-write
0
0xFFFFFFFF
WARNINT
Watchdog Warning Interrupt Compare Value
0
10
read-write
WINDOW
Window Compare Value
0x18
32
read-write
0xFFFFFF
0xFFFFFFFF
WINDOW
Watchdog Window Value
0
24
read-write
DMA0
DMA MP
eDMA_1_MP
0x40080000
0
0x110
registers
DMA_CH0
2
DMA_CH1
3
DMA_CH2
4
DMA_CH3
5
MP_CSR
Management Page Control
0
32
read-write
0x310000
0xFFFFFFFF
EDBG
Enable Debug
1
1
read-write
DISABLE
Debug mode disabled
0
ENABLE
Debug mode is enabled.
0x1
ERCA
Enable Round Robin Channel Arbitration
2
1
read-write
DISABLE
Round-robin channel arbitration disabled
0
ENABLE
Round-robin channel arbitration enabled
0x1
HAE
Halt After Error
4
1
read-write
NORMAL_OPERATION
Normal operation
0
HALT
Any error causes the HALT field to be set to 1
0x1
HALT
Halt DMA Operations
5
1
read-write
NORMAL_OPERATION
Normal operation
0
STALL
Stall the start of any new channels
0x1
GCLC
Global Channel Linking Control
6
1
read-write
DISABLE
Channel linking disabled for all channels
0
AVAILABLE
Channel linking available and controlled by each channel's link settings
0x1
GMRC
Global Master ID Replication Control
7
1
read-write
DISABLE
Master ID replication disabled for all channels
0
AVAILABLE
Master ID replication available and controlled by each channel's CHn_SBR[EMI] setting
0x1
ECX
Cancel Transfer With Error
8
1
read-write
NORMAL_OPERATION
Normal operation
0
CANCEL
Cancel the remaining data transfer
0x1
CX
Cancel Transfer
9
1
read-write
NORMAL_OPERATION
Normal operation
0
DATA_TRANSFER_CANCEL
Cancel the remaining data transfer
0x1
ACTIVE_ID
Active Channel ID
24
2
read-only
ACTIVE
DMA Active Status
31
1
read-only
IDLE
eDMA is idle
0
EXECUTION
eDMA is executing a channel
0x1
MP_ES
Management Page Error Status
0x4
32
read-only
0
0xFFFFFFFF
DBE
Destination Bus Error
0
1
read-only
NO_ERROR
No destination bus error
0
BUS_ERROR
Last recorded error was a bus error on a destination write
0x1
SBE
Source Bus Error
1
1
read-only
NO_ERROR
No source bus error
0
BUS_ERROR
Last recorded error was a bus error on a source read
0x1
SGE
Scatter/Gather Configuration Error
2
1
read-only
NO_ERROR
No scatter/gather configuration error
0
CONFIGURATION_ERROR
Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field
0x1
NCE
NBYTES/CITER Configuration Error
3
1
read-only
NO_ERROR
No NBYTES/CITER configuration error
0
CONFIGURATION_ERROR
The last recorded error was NBYTES equal to zero or a CITER not equal to BITER error
0x1
DOE
Destination Offset Error
4
1
read-only
NO_ERROR
No destination offset configuration error
0
CONFIGURATION_ERROR
Last recorded error was a configuration error detected in the TCDn_DOFF field
0x1
DAE
Destination Address Error
5
1
read-only
NO_ERROR
No destination address configuration error
0
CONFIGURATION_ERROR
Last recorded error was a configuration error detected in the TCDn_DADDR field
0x1
SOE
Source Offset Error
6
1
read-only
NO_ERROR
No source offset configuration error
0
CONFIGURATION_ERROR
Last recorded error was a configuration error detected in the TCDn_SOFF field
0x1
SAE
Source Address Error
7
1
read-only
NO_ERROR
No source address configuration error
0
CONFIGURATION_ERROR
Last recorded error was a configuration error detected in the TCDn_SADDR field
0x1
ECX
Transfer Canceled
8
1
read-only
NO_CANCELED_TRANSFERS
No canceled transfers
0
CANCELED_TRANSFER
Last recorded entry was a canceled transfer by the error cancel transfer input
0x1
ERRCHN
Error Channel Number or Canceled Channel Number
24
2
read-only
VLD
Valid
31
1
read-only
NO_FIELD_SET_ONE
No CHn_ES[ERR] fields are set to 1
0
ATLEAST_ONE_FIELD
At least one CHn_ES[ERR] field is set to 1, indicating a valid error exists that software has not cleared
0x1
MP_INT
Management Page Interrupt Request Status
0x8
32
read-only
0
0xFFFFFFFF
INT
Interrupt Request Status
0
4
read-only
MP_HRS
Management Page Hardware Request Status
0xC
32
read-only
0
0xFFFFFFFF
HRS
Hardware Request Status
0
32
read-only
4
0x4
CH_GRPRI[%s]
Channel Arbitration Group
0x100
32
read-write
0
0xFFFFFFFF
GRPRI
Arbitration Group For Channel n
0
5
read-write
EDMA_0_TCD0
DMA TCD
eDMA_1_TCD
0x40081000
0
0x3040
registers
4
0x1000
TCD[%s]
no description available
0
CH_CSR
Channel Control and Status
0
32
read-write
0
0xFFFFFFFF
ERQ
Enable DMA Request
0
1
read-write
DISABLE
DMA hardware request signal for corresponding channel disabled
0
ENABLE
DMA hardware request signal for corresponding channel enabled
0x1
EARQ
Enable Asynchronous DMA Request
1
1
read-write
DISABLE
Disable asynchronous DMA request for the channel
0
ENABLE
Enable asynchronous DMA request for the channel
0x1
EEI
Enable Error Interrupt
2
1
read-write
NO_ERROR
Error signal for corresponding channel does not generate error interrupt
0
ERROR
Assertion of error signal for corresponding channel generates error interrupt request
0x1
EBW
Enable Buffered Writes
3
1
read-write
DISABLE
Buffered writes on system bus disabled
0
ENABLE
Buffered writes on system bus enabled
0x1
DONE
Channel Done
30
1
read-write
oneToClear
ACTIVE
Channel Active
31
1
read-only
CH_ES
Channel Error Status
0x4
32
read-write
0
0xFFFFFFFF
DBE
Destination Bus Error
0
1
read-only
NO_ERROR
No destination bus error
0
ERROR
Last recorded error was bus error on destination write
0x1
SBE
Source Bus Error
1
1
read-only
NO_ERROR
No source bus error
0
ERROR
Last recorded error was bus error on source read
0x1
SGE
Scatter/Gather Configuration Error
2
1
read-only
NO_ERROR
No scatter/gather configuration error
0
ERROR
Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field
0x1
NCE
NBYTES/CITER Configuration Error
3
1
read-only
NO_ERROR
No NBYTES/CITER configuration error
0
ERROR
Last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields
0x1
DOE
Destination Offset Error
4
1
read-only
NO_ERROR
No destination offset configuration error
0
ERROR
Last recorded error was a configuration error detected in the TCDn_DOFF field
0x1
DAE
Destination Address Error
5
1
read-only
NO_ERROR
No destination address configuration error
0
ERROR
Last recorded error was a configuration error detected in the TCDn_DADDR field
0x1
SOE
Source Offset Error
6
1
read-only
NO_ERROR
No source offset configuration error
0
ERROR
Last recorded error was a configuration error detected in the TCDn_SOFF field
0x1
SAE
Source Address Error
7
1
read-only
NO_ERROR
No source address configuration error
0
ERROR
Last recorded error was a configuration error detected in the TCDn_SADDR field
0x1
ERR
Error In Channel
31
1
read-write
oneToClear
NO_ERROR
An error in this channel has not occurred
0
ERROR
An error in this channel has occurred
0x1
CH_INT
Channel Interrupt Status
0x8
32
read-write
0
0xFFFFFFFF
oneToClear
INT
Interrupt Request
0
1
read-write
oneToClear
INTERRUPT_CLEARED
Interrupt request for corresponding channel cleared
0
INTERRUPT_ACTIVE
Interrupt request for corresponding channel active
0x1
CH_SBR
Channel System Bus
0xC
32
read-write
0x5
0xFFFFFFFF
MID
Master ID
0
4
read-only
PAL
Privileged Access Level
15
1
read-only
USER_PROTECTION
User protection level for DMA transfers
0
PRIVILEGED_PROTECTION
Privileged protection level for DMA transfers
0x1
EMI
Enable Master ID Replication
16
1
read-write
DISABLE
Master ID replication is disabled
0
ENABLE
Master ID replication is enabled
0x1
CH_PRI
Channel Priority
0x10
32
read-write
0
0xFFFFFFFF
APL
Arbitration Priority Level
0
3
read-write
DPA
Disable Preempt Ability
30
1
read-write
SUSPEND
Channel can suspend a lower-priority channel
0
CANNOT_SUSPEND
Channel cannot suspend any other channel, regardless of channel priority
0x1
ECP
Enable Channel Preemption
31
1
read-write
CANNOT_SUSPEND
Channel cannot be suspended by a higher-priority channel's service request
0
SUSPEND
Channel can be temporarily suspended by a higher-priority channel's service request
0x1
CH_MUX
Channel Multiplexor Configuration
0x14
32
read-write
0
0xFFFFFFFF
SRC
Service Request Source
0
7
read-write
TCD_SADDR
TCD Source Address
0x20
32
read-write
0
0
SADDR
Source Address
0
32
read-write
TCD_SOFF
TCD Signed Source Address Offset
0x24
16
read-write
0
0
SOFF
Source Address Signed Offset
0
16
read-write
TCD_ATTR
TCD Transfer Attributes
0x26
16
read-write
0
0
DSIZE
Destination Data Transfer Size
0
3
read-write
DMOD
Destination Address Modulo
3
5
read-write
SSIZE
Source Data Transfer Size
8
3
read-write
EIGHT_BIT
8-bit
0
SIXTEEN_BIT
16-bit
0x1
THIRTYTWO_BIT
32-bit
0x2
SIXTYFOUR_BIT
64-bit
0x3
SIXTEEN_BYTE
16-byte
0x4
THIRTYTWO_BYTE
32-byte
0x5
SMOD
Source Address Modulo
11
5
read-write
DISABLE
Source address modulo feature disabled
0
ENABLE
Source address modulo feature enabled for any non-zero value [1-31]
0x1
TCD_NBYTES_MLOFFNO
TCD Transfer Size Without Minor Loop Offsets
NBYTES
0x28
32
read-write
0
0
NBYTES
Number of Bytes To Transfer Per Service Request
0
30
read-write
DMLOE
Destination Minor Loop Offset Enable
30
1
read-write
OFFSET_NOT_APPLIED
Minor loop offset not applied to DADDR
0
OFFSET_APPLIED
Minor loop offset applied to DADDR
0x1
SMLOE
Source Minor Loop Offset Enable
31
1
read-write
OFFSET_NOT_APPLIED
Minor loop offset not applied to SADDR
0
OFFSET_APPLIED
Minor loop offset applied to SADDR
0x1
TCD_NBYTES_MLOFFYES
TCD Transfer Size with Minor Loop Offsets
NBYTES
0x28
32
read-write
0
0
NBYTES
Number of Bytes To Transfer Per Service Request
0
10
read-write
MLOFF
Minor Loop Offset
10
20
read-write
DMLOE
Destination Minor Loop Offset Enable
30
1
read-write
OFFSET_NOT_APPLIED
Minor loop offset not applied to DADDR
0
OFFSET_APPLIED
Minor loop offset applied to DADDR
0x1
SMLOE
Source Minor Loop Offset Enable
31
1
read-write
OFFSET_NOT_APPLIED
Minor loop offset not applied to SADDR
0
OFFSET_APPLIED
Minor loop offset applied to SADDR
0x1
TCD_SLAST_SDA
TCD Last Source Address Adjustment / Store DADDR Address
0x2C
32
read-write
0
0
SLAST_SDA
Last Source Address Adjustment / Store DADDR Address
0
32
read-write
TCD_DADDR
TCD Destination Address
0x30
32
read-write
0
0
DADDR
Destination Address
0
32
read-write
TCD_DOFF
TCD Signed Destination Address Offset
0x34
16
read-write
0
0
DOFF
Destination Address Signed Offset
0
16
read-write
TCD_CITER_ELINKNO
TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)
CITER
0x36
16
read-write
0
0
CITER
Current Major Iteration Count
0
15
read-write
ELINK
Enable Link
15
1
read-write
DISABLE
Channel-to-channel linking disabled
0
ENABLE
Channel-to-channel linking enabled
0x1
TCD_CITER_ELINKYES
TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)
CITER
0x36
16
read-write
0
0
CITER
Current Major Iteration Count
0
9
read-write
LINKCH
Minor Loop Link Channel Number
9
2
read-write
ELINK
Enable Link
15
1
read-write
DISABLE
Channel-to-channel linking disabled
0
ENABLE
Channel-to-channel linking enabled
0x1
TCD_DLAST_SGA
TCD Last Destination Address Adjustment / Scatter Gather Address
0x38
32
read-write
0
0
DLAST_SGA
Last Destination Address Adjustment / Scatter Gather Address
0
32
read-write
TCD_CSR
TCD Control and Status
0x3C
16
read-write
0
0x1
START
Channel Start
0
1
read-write
CHANNEL_NOT_STARTED
Channel not explicitly started
0
CHANNEL_STARTED
Channel explicitly started via a software-initiated service request
0x1
INTMAJOR
Enable Interrupt If Major count complete
1
1
read-write
DISABLE
End-of-major loop interrupt disabled
0
ENABLE
End-of-major loop interrupt enabled
0x1
INTHALF
Enable Interrupt If Major Counter Half-complete
2
1
read-write
DISABLE
Halfway point interrupt disabled
0
ENABLE
Halfway point interrupt enabled
0x1
DREQ
Disable Request
3
1
read-write
CHANNEL_NOT_AFFECTED
No operation
0
ERQ_FIELD_CLEAR
Clear the ERQ field to 0 upon major loop completion, thus disabling hardware service requests
0x1
ESG
Enable Scatter/Gather Processing
4
1
read-write
NORMAL_FORMAT
Current channel's TCD is normal format
0
SCATTER_GATHER_FORMAT
Current channel's TCD specifies scatter/gather format.
0x1
MAJORELINK
Enable Link When Major Loop Complete
5
1
read-write
DISABLE
Channel-to-channel linking disabled
0
ENABLE
Channel-to-channel linking enabled
0x1
EEOP
Enable End-Of-Packet Processing
6
1
read-write
DISABLE
End-of-packet operation disabled
0
ENABLE
End-of-packet hardware input signal enabled
0x1
ESDA
Enable Store Destination Address
7
1
read-write
DISABLE
Ability to store destination address to system memory disabled
0
ENABLE
Ability to store destination address to system memory enabled
0x1
MAJORLINKCH
Major Loop Link Channel Number
8
2
read-write
BWC
Bandwidth Control
14
2
read-write
NO_STALL
No eDMA engine stalls
0
ENGINE_STALLS_FOUR
eDMA engine stalls for 4 cycles after each R/W
0x2
ENGINE_STALLS_EIGHT
eDMA engine stalls for 8 cycles after each R/W
0x3
TCD_BITER_ELINKNO
TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)
BITER
0x3E
16
read-write
0
0
BITER
Starting Major Iteration Count
0
15
read-write
ELINK
Enables Link
15
1
read-write
DISABLE
Channel-to-channel linking disabled
0
ENABLE
Channel-to-channel linking enabled
0x1
TCD_BITER_ELINKYES
TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)
BITER
0x3E
16
read-write
0
0
BITER
Starting Major Iteration Count
0
9
read-write
LINKCH
Link Channel Number
9
2
read-write
ELINK
Enable Link
15
1
read-write
DISABLE
Channel-to-channel linking disabled
0
ENABLE
Channel-to-channel linking enabled
0x1
AOI0
AOI
AOI
0x40089000
0
0x10
registers
BFCRT010
Boolean Function Term 0 and 1 Configuration for EVENT0
0
16
read-write
0
0xFFFF
PT1_DC
Product Term 1, Input D Configuration
0
2
read-write
FORCE_0
Force input D to become 0
0
PASS
Pass input D
0x1
COMPLEMENT
Complement input D
0x2
FORCE_1
Force input D to become 1
0x3
PT1_CC
Product Term 1, Input C Configuration
2
2
read-write
FORCE_0
Force input C to become 0
0
PASS
Pass input C
0x1
COMPLEMENT
Complement input C
0x2
FORCE_1
Force input C to become 1
0x3
PT1_BC
Product Term 1, Input B Configuration
4
2
read-write
FORCE_0
Force input B to become 0
0
PASS
Pass input B
0x1
COMPLEMENT
Complement input B
0x2
FORCE_1
Force input B to become 1
0x3
PT1_AC
Product Term 1, Input A Configuration
6
2
read-write
FORCE_0
Force input A to become 0
0
PASS
Pass input A
0x1
COMPLEMENT
Complement input A
0x2
FORCE_1
Force input A to become 1
0x3
PT0_DC
Product Term 0, Input D Configuration
8
2
read-write
FORCE_0
Force input D to become 0
0
PASS
Pass input D
0x1
COMPLEMENT
Complement input D
0x2
FORCE_1
Force input D to become 1
0x3
PT0_CC
Product Term 0, Input C Configuration
10
2
read-write
FORCE_0
Force input C to become 0
0
PASS
Pass input C
0x1
COMPLEMENT
Complement input C
0x2
FORCE_1
Force input C to become 1
0x3
PT0_BC
Product Term 0, Input B Configuration
12
2
read-write
FORCE_0
Force input B to become 0
0
PASS
Pass input B
0x1
COMPLEMENT
Complement input B
0x2
FORCE_1
Force input B to become 1
0x3
PT0_AC
Product Term 0, Input A Configuration
14
2
read-write
FORCE_0
Force input A to become 0
0
PASS
Pass input A
0x1
COMPLEMENT
Complement input A
0x2
FORCE_1
Force input A to become 1
0x3
BFCRT230
Boolean Function Term 2 and 3 Configuration for EVENT0
0x2
16
read-write
0
0xFFFF
PT3_DC
Product Term 3, Input D Configuration
0
2
read-write
FORCE_0
Force input D to become 0
0
PASS
Pass input D
0x1
COMPLEMENT
Complement input D
0x2
FORCE_1
Force input D to become 1
0x3
PT3_CC
Product Term 3, Input C Configuration
2
2
read-write
FORCE_0
Force input C to become 0
0
PASS
Pass input C
0x1
COMPLEMENT
Complement input C
0x2
FORCE_1
Force input C to become 1
0x3
PT3_BC
Product Term 3, Input B Configuration
4
2
read-write
FORCE_0
Force input B to become 0
0
PASS
Pass input B
0x1
COMPLEMENT
Complement input B
0x2
FORCE_1
Force input B to become 1
0x3
PT3_AC
Product Term 3, Input A Configuration
6
2
read-write
FORCE_0
Force input A to become 0
0
PASS
Pass input A
0x1
COMPLEMENT
Complement input A
0x2
FORCE_1
Force input to become 1
0x3
PT2_DC
Product Term 2, Input D Configuration
8
2
read-write
FORCE_0
Force input D to become 0
0
PASS
Pass input D
0x1
COMPLEMENT
Complement input D
0x2
FORCE_1
Force input D to become 1
0x3
PT2_CC
Product Term 2, Input C Configuration
10
2
read-write
FORCE_0
Force input C to become 0
0
PASS
Pass input C
0x1
COMPLEMENT
Complement input C
0x2
FORCE_1
Force input C to become 1
0x3
PT2_BC
Product Term 2, Input B Configuration
12
2
read-write
FORCE_0
Force input B to become 0
0
PASS
Pass input B
0x1
COMPLEMENT
Complement input B
0x2
FORCE_1
Force input B to become 1
0x3
PT2_AC
Product Term 2, Input A Configuration
14
2
read-write
FORCE_0
Force input A to become 0
0
PASS
Pass input A
0x1
COMPLEMENT
Complement input A
0x2
FORCE_1
Force input A to become 1
0x3
BFCRT011
Boolean Function Term 0 and 1 Configuration for EVENT1
0x4
16
read-write
0
0xFFFF
PT1_DC
Product Term 1, Input D Configuration
0
2
read-write
FORCE_0
Force input D to become 0
0
PASS
Pass input D
0x1
COMPLEMENT
Complement input D
0x2
FORCE_1
Force input D to become 1
0x3
PT1_CC
Product Term 1, Input C Configuration
2
2
read-write
FORCE_0
Force input C to become 0
0
PASS
Pass input C
0x1
COMPLEMENT
Complement input C
0x2
FORCE_1
Force input C to become 1
0x3
PT1_BC
Product Term 1, Input B Configuration
4
2
read-write
FORCE_0
Force input B to become 0
0
PASS
Pass input B
0x1
COMPLEMENT
Complement input B
0x2
FORCE_1
Force input B to become 1
0x3
PT1_AC
Product Term 1, Input A Configuration
6
2
read-write
FORCE_0
Force input A to become 0
0
PASS
Pass input A
0x1
COMPLEMENT
Complement input A
0x2
FORCE_1
Force input A to become 1
0x3
PT0_DC
Product Term 0, Input D Configuration
8
2
read-write
FORCE_0
Force input D to become 0
0
PASS
Pass input D
0x1
COMPLEMENT
Complement input D
0x2
FORCE_1
Force input D to become 1
0x3
PT0_CC
Product Term 0, Input C Configuration
10
2
read-write
FORCE_0
Force input C to become 0
0
PASS
Pass input C
0x1
COMPLEMENT
Complement input C
0x2
FORCE_1
Force input C to become 1
0x3
PT0_BC
Product Term 0, Input B Configuration
12
2
read-write
FORCE_0
Force input B to become 0
0
PASS
Pass input B
0x1
COMPLEMENT
Complement input B
0x2
FORCE_1
Force input B to become 1
0x3
PT0_AC
Product Term 0, Input A Configuration
14
2
read-write
FORCE_0
Force input A to become 0
0
PASS
Pass input A
0x1
COMPLEMENT
Complement input A
0x2
FORCE_1
Force input A to become 1
0x3
BFCRT231
Boolean Function Term 2 and 3 Configuration for EVENT1
0x6
16
read-write
0
0xFFFF
PT3_DC
Product Term 3, Input D Configuration
0
2
read-write
FORCE_0
Force input D to become 0
0
PASS
Pass input D
0x1
COMPLEMENT
Complement input D
0x2
FORCE_1
Force input D to become 1
0x3
PT3_CC
Product Term 3, Input C Configuration
2
2
read-write
FORCE_0
Force input C to become 0
0
PASS
Pass input C
0x1
COMPLEMENT
Complement input C
0x2
FORCE_1
Force input C to become 1
0x3
PT3_BC
Product Term 3, Input B Configuration
4
2
read-write
FORCE_0
Force input B to become 0
0
PASS
Pass input B
0x1
COMPLEMENT
Complement input B
0x2
FORCE_1
Force input B to become 1
0x3
PT3_AC
Product Term 3, Input A Configuration
6
2
read-write
FORCE_0
Force input A to become 0
0
PASS
Pass input A
0x1
COMPLEMENT
Complement input A
0x2
FORCE_1
Force input to become 1
0x3
PT2_DC
Product Term 2, Input D Configuration
8
2
read-write
FORCE_0
Force input D to become 0
0
PASS
Pass input D
0x1
COMPLEMENT
Complement input D
0x2
FORCE_1
Force input D to become 1
0x3
PT2_CC
Product Term 2, Input C Configuration
10
2
read-write
FORCE_0
Force input C to become 0
0
PASS
Pass input C
0x1
COMPLEMENT
Complement input C
0x2
FORCE_1
Force input C to become 1
0x3
PT2_BC
Product Term 2, Input B Configuration
12
2
read-write
FORCE_0
Force input B to become 0
0
PASS
Pass input B
0x1
COMPLEMENT
Complement input B
0x2
FORCE_1
Force input B to become 1
0x3
PT2_AC
Product Term 2, Input A Configuration
14
2
read-write
FORCE_0
Force input A to become 0
0
PASS
Pass input A
0x1
COMPLEMENT
Complement input A
0x2
FORCE_1
Force input A to become 1
0x3
BFCRT012
Boolean Function Term 0 and 1 Configuration for EVENT2
0x8
16
read-write
0
0xFFFF
PT1_DC
Product Term 1, Input D Configuration
0
2
read-write
FORCE_0
Force input D to become 0
0
PASS
Pass input D
0x1
COMPLEMENT
Complement input D
0x2
FORCE_1
Force input D to become 1
0x3
PT1_CC
Product Term 1, Input C Configuration
2
2
read-write
FORCE_0
Force input C to become 0
0
PASS
Pass input C
0x1
COMPLEMENT
Complement input C
0x2
FORCE_1
Force input C to become 1
0x3
PT1_BC
Product Term 1, Input B Configuration
4
2
read-write
FORCE_0
Force input B to become 0
0
PASS
Pass input B
0x1
COMPLEMENT
Complement input B
0x2
FORCE_1
Force input B to become 1
0x3
PT1_AC
Product Term 1, Input A Configuration
6
2
read-write
FORCE_0
Force input A to become 0
0
PASS
Pass input A
0x1
COMPLEMENT
Complement input A
0x2
FORCE_1
Force input A to become 1
0x3
PT0_DC
Product Term 0, Input D Configuration
8
2
read-write
FORCE_0
Force input D to become 0
0
PASS
Pass input D
0x1
COMPLEMENT
Complement input D
0x2
FORCE_1
Force input D to become 1
0x3
PT0_CC
Product Term 0, Input C Configuration
10
2
read-write
FORCE_0
Force input C to become 0
0
PASS
Pass input C
0x1
COMPLEMENT
Complement input C
0x2
FORCE_1
Force input C to become 1
0x3
PT0_BC
Product Term 0, Input B Configuration
12
2
read-write
FORCE_0
Force input B to become 0
0
PASS
Pass input B
0x1
COMPLEMENT
Complement input B
0x2
FORCE_1
Force input B to become 1
0x3
PT0_AC
Product Term 0, Input A Configuration
14
2
read-write
FORCE_0
Force input A to become 0
0
PASS
Pass input A
0x1
COMPLEMENT
Complement input A
0x2
FORCE_1
Force input A to become 1
0x3
BFCRT232
Boolean Function Term 2 and 3 Configuration for EVENT2
0xA
16
read-write
0
0xFFFF
PT3_DC
Product Term 3, Input D Configuration
0
2
read-write
FORCE_0
Force input D to become 0
0
PASS
Pass input D
0x1
COMPLEMENT
Complement input D
0x2
FORCE_1
Force input D to become 1
0x3
PT3_CC
Product Term 3, Input C Configuration
2
2
read-write
FORCE_0
Force input C to become 0
0
PASS
Pass input C
0x1
COMPLEMENT
Complement input C
0x2
FORCE_1
Force input C to become 1
0x3
PT3_BC
Product Term 3, Input B Configuration
4
2
read-write
FORCE_0
Force input B to become 0
0
PASS
Pass input B
0x1
COMPLEMENT
Complement input B
0x2
FORCE_1
Force input B to become 1
0x3
PT3_AC
Product Term 3, Input A Configuration
6
2
read-write
FORCE_0
Force input A to become 0
0
PASS
Pass input A
0x1
COMPLEMENT
Complement input A
0x2
FORCE_1
Force input to become 1
0x3
PT2_DC
Product Term 2, Input D Configuration
8
2
read-write
FORCE_0
Force input D to become 0
0
PASS
Pass input D
0x1
COMPLEMENT
Complement input D
0x2
FORCE_1
Force input D to become 1
0x3
PT2_CC
Product Term 2, Input C Configuration
10
2
read-write
FORCE_0
Force input C to become 0
0
PASS
Pass input C
0x1
COMPLEMENT
Complement input C
0x2
FORCE_1
Force input C to become 1
0x3
PT2_BC
Product Term 2, Input B Configuration
12
2
read-write
FORCE_0
Force input B to become 0
0
PASS
Pass input B
0x1
COMPLEMENT
Complement input B
0x2
FORCE_1
Force input B to become 1
0x3
PT2_AC
Product Term 2, Input A Configuration
14
2
read-write
FORCE_0
Force input A to become 0
0
PASS
Pass input A
0x1
COMPLEMENT
Complement input A
0x2
FORCE_1
Force input A to become 1
0x3
BFCRT013
Boolean Function Term 0 and 1 Configuration for EVENT3
0xC
16
read-write
0
0xFFFF
PT1_DC
Product Term 1, Input D Configuration
0
2
read-write
FORCE_0
Force input D to become 0
0
PASS
Pass input D
0x1
COMPLEMENT
Complement input D
0x2
FORCE_1
Force input D to become 1
0x3
PT1_CC
Product Term 1, Input C Configuration
2
2
read-write
FORCE_0
Force input C to become 0
0
PASS
Pass input C
0x1
COMPLEMENT
Complement input C
0x2
FORCE_1
Force input C to become 1
0x3
PT1_BC
Product Term 1, Input B Configuration
4
2
read-write
FORCE_0
Force input B to become 0
0
PASS
Pass input B
0x1
COMPLEMENT
Complement input B
0x2
FORCE_1
Force input B to become 1
0x3
PT1_AC
Product Term 1, Input A Configuration
6
2
read-write
FORCE_0
Force input A to become 0
0
PASS
Pass input A
0x1
COMPLEMENT
Complement input A
0x2
FORCE_1
Force input A to become 1
0x3
PT0_DC
Product Term 0, Input D Configuration
8
2
read-write
FORCE_0
Force input D to become 0
0
PASS
Pass input D
0x1
COMPLEMENT
Complement input D
0x2
FORCE_1
Force input D to become 1
0x3
PT0_CC
Product Term 0, Input C Configuration
10
2
read-write
FORCE_0
Force input C to become 0
0
PASS
Pass input C
0x1
COMPLEMENT
Complement input C
0x2
FORCE_1
Force input C to become 1
0x3
PT0_BC
Product Term 0, Input B Configuration
12
2
read-write
FORCE_0
Force input B to become 0
0
PASS
Pass input B
0x1
COMPLEMENT
Complement input B
0x2
FORCE_1
Force input B to become 1
0x3
PT0_AC
Product Term 0, Input A Configuration
14
2
read-write
FORCE_0
Force input A to become 0
0
PASS
Pass input A
0x1
COMPLEMENT
Complement input A
0x2
FORCE_1
Force input A to become 1
0x3
BFCRT233
Boolean Function Term 2 and 3 Configuration for EVENT3
0xE
16
read-write
0
0xFFFF
PT3_DC
Product Term 3, Input D Configuration
0
2
read-write
FORCE_0
Force input D to become 0
0
PASS
Pass input D
0x1
COMPLEMENT
Complement input D
0x2
FORCE_1
Force input D to become 1
0x3
PT3_CC
Product Term 3, Input C Configuration
2
2
read-write
FORCE_0
Force input C to become 0
0
PASS
Pass input C
0x1
COMPLEMENT
Complement input C
0x2
FORCE_1
Force input C to become 1
0x3
PT3_BC
Product Term 3, Input B Configuration
4
2
read-write
FORCE_0
Force input B to become 0
0
PASS
Pass input B
0x1
COMPLEMENT
Complement input B
0x2
FORCE_1
Force input B to become 1
0x3
PT3_AC
Product Term 3, Input A Configuration
6
2
read-write
FORCE_0
Force input A to become 0
0
PASS
Pass input A
0x1
COMPLEMENT
Complement input A
0x2
FORCE_1
Force input to become 1
0x3
PT2_DC
Product Term 2, Input D Configuration
8
2
read-write
FORCE_0
Force input D to become 0
0
PASS
Pass input D
0x1
COMPLEMENT
Complement input D
0x2
FORCE_1
Force input D to become 1
0x3
PT2_CC
Product Term 2, Input C Configuration
10
2
read-write
FORCE_0
Force input C to become 0
0
PASS
Pass input C
0x1
COMPLEMENT
Complement input C
0x2
FORCE_1
Force input C to become 1
0x3
PT2_BC
Product Term 2, Input B Configuration
12
2
read-write
FORCE_0
Force input B to become 0
0
PASS
Pass input B
0x1
COMPLEMENT
Complement input B
0x2
FORCE_1
Force input B to become 1
0x3
PT2_AC
Product Term 2, Input A Configuration
14
2
read-write
FORCE_0
Force input A to become 0
0
PASS
Pass input A
0x1
COMPLEMENT
Complement input A
0x2
FORCE_1
Force input A to become 1
0x3
CRC0
CRC
CRC
0x4008A000
0
0xC
registers
DATA
CRC Data
0
32
read-write
0xFFFFFFFF
0xFFFFFFFF
LL
CRC Low Lower Byte
0
8
read-write
LU
CRC Low Upper Byte
8
8
read-write
HL
CRC High Lower Byte
16
8
read-write
HU
CRC High Upper Byte
24
8
read-write
GPOLY
CRC Polynomial
0x4
32
read-write
0x1021
0xFFFFFFFF
LOW
Low Polynomial Half-Word
0
16
read-write
HIGH
High Polynomial Half-Word
16
16
read-write
CTRL
CRC Control
0x8
32
read-write
0
0xFFFFFFFF
TCRC
TCRC
24
1
read-write
B16
16-bit
0
B32
32-bit
0x1
WAS
Write as Seed
25
1
read-write
DATA
Data values
0
SEED
Seed values
0x1
FXOR
Complement Read of CRC Data Register
26
1
read-write
NOXOR
No XOR on reading
0
INVERT
Inverts or complements the read value of the CRC Data
0x1
TOTR
Transpose Type for Read
28
2
read-write
NOTRNPS
No transposition
0
BTS_TRNPS
Bits in bytes are transposed; bytes are not transposed
0x1
BYTS_BTS_TRNPS
Both bits in bytes and bytes are transposed
0x2
BYTS_TRNPS
Only bytes are transposed; no bits in a byte are transposed
0x3
TOT
Transpose Type for Writes
30
2
read-write
NOTRNPS
No transposition
0
BTS_TRNPS
Bits in bytes are transposed; bytes are not transposed
0x1
BYTS_BTS_TRNPS
Both bits in bytes and bytes are transposed
0x2
BYTS_TRNPS
Only bytes are transposed; no bits in a byte are transposed
0x3
CMC
CMC
CMC
0x4008B000
0
0x124
registers
CMC
1
VERID
Version ID
0
32
read-only
0x3010000
0xFFFFFFFF
FEATURE
Feature Specification Number
0
16
read-only
MINOR
Minor Version Number
16
8
read-only
MAJOR
Major Version Number
24
8
read-only
CKCTRL
Clock Control
0x10
32
read-write
0
0xFFFFFFFF
CKMODE
Clocking Mode
0
4
read-write
CKMODE0000
No clock gating
0
CKMODE1111
Core, platform, and peripheral clocks are gated, and core enters Low-Power mode.
0xF
LOCK
Lock
31
1
read-write
DISABLED
Allowed
0
ENABLED
Blocked
0x1
CKSTAT
Clock Status
0x14
32
read-write
0
0xFFFFFFFF
CKMODE
Low Power Status
0
4
read-only
CKMODE0000
Core clock not gated
0
CKMODE1111
Core, platform, and peripheral clocks were gated, and power domain entered Low-Power mode
0xF
WAKEUP
Wake-up Source
8
8
read-only
VALID
Clock Status Valid
31
1
read-write
oneToClear
DISABLED
Core clock not gated
0
ENABLED
Core clock was gated due to Low-Power mode entry
0x1
PMPROT
Power Mode Protection
0x18
32
read-write
0
0xFFFFFFFF
LPMODE
Low-Power Mode
0
4
read-write
DISABLED
Not allowed
0
EN
Allowed
0x1
EN1
Allowed
0x2
EN2
Allowed
0x3
EN3
Allowed
0x4
EN4
Allowed
0x5
EN5
Allowed
0x6
EN6
Allowed
0x7
EN7
Allowed
0x8
EN8
Allowed
0x9
EN9
Allowed
0xA
EN10
Allowed
0xB
EN11
Allowed
0xC
EN12
Allowed
0xD
EN13
Allowed
0xE
EN14
Allowed
0xF
LOCK
Lock Register
31
1
read-write
DISABLED
Allowed
0
ENABLED
Blocked
0x1
GPMCTRL
Global Power Mode Control
0x1C
32
read-write
0
0xFFFFFFFF
LPMODE
Low-Power Mode
0
4
read-write
PMCTRLMAIN
Power Mode Control
0x20
32
read-write
0
0xFFFFFFFF
LPMODE
Low-Power Mode
0
4
read-write
LPMODE0000
Active/Sleep
0
LPMODE0001
Deep Sleep
0x1
LPMODE0011
Power Down
0x3
LPMODE1111
Deep-Power Down
0xF
SRS
System Reset Status
0x80
32
read-only
0
0
WAKEUP
Wake-up Reset
0
1
read-only
DISABLED
Reset not generated
0
ENABLED
Reset generated
0x1
POR
Power-on Reset
1
1
read-only
DISABLED
Reset not generated
0
ENABLED
Reset generated
0x1
VD
Voltage Detect Reset
2
1
read-only
DISABLED
Reset not generated
0
ENABLED
Reset generated
0x1
WARM
Warm Reset
4
1
read-only
DISABLED
Reset not generated
0
ENABLED
Reset generated
0x1
FATAL
Fatal Reset
5
1
read-only
DISABLED
Reset was not generated
0
ENABLED
Reset was generated
0x1
PIN
Pin Reset
8
1
read-only
DISABLED
Reset was not generated
0
ENABLED
Reset was generated
0x1
DAP
Debug Access Port Reset
9
1
read-only
DISABLED
Reset was not generated
0
ENABLED
Reset was generated
0x1
RSTACK
Reset Timeout
10
1
read-only
DISABLED
Reset not generated
0
ENABLED
Reset generated
0x1
LPACK
Low Power Acknowledge Timeout Reset
11
1
read-only
DISABLED
Reset not generated
0
ENABLED
Reset generated
0x1
SCG
System Clock Generation Reset
12
1
read-only
DISABLED
Reset is not generated
0
ENABLED
Reset is generated
0x1
WWDT0
Windowed Watchdog 0 Reset
13
1
read-only
DISABLED
Reset is not generated
0
ENABLED
Reset is generated
0x1
SW
Software Reset
14
1
read-only
DISABLED
Reset not generated
0
ENABLED
Reset generated
0x1
LOCKUP
Lockup Reset
15
1
read-only
DISABLED
Reset not generated
0
ENABLED
Reset generated
0x1
CDOG0
Code Watchdog 0 Reset
26
1
read-only
DISABLED
Reset is not generated
0
ENABLED
Reset is generated
0x1
JTAG
JTAG System Reset
28
1
read-only
DISABLED
Reset not generated
0
ENABLED
Reset generated
0x1
RPC
Reset Pin Control
0x84
32
read-write
0
0xFFFFFFFF
FILTCFG
Reset Filter Configuration
0
5
read-write
FILTEN
Filter Enable
8
1
read-write
DISABLED
Disables
0
ENABLED
Enables
0x1
LPFEN
Low-Power Filter Enable
9
1
read-write
DISABLED
Disables
0
ENABLED
Enables
0x1
SSRS
Sticky System Reset Status
0x88
32
read-write
0x6
0xFFFFFFFF
WAKEUP
Wake-up Reset
0
1
read-write
oneToClear
DISABLED
Reset not generated
0
ENABLED
Reset generated
0x1
POR
Power-on Reset
1
1
read-write
oneToClear
DISABLED
Reset not generated
0
ENABLED
Reset generated
0x1
VD
Voltage Detect Reset
2
1
read-only
DISABLED
Reset not generated
0
ENABLED
Reset generated
0x1
WARM
Warm Reset
4
1
read-write
oneToClear
DISABLED
Reset not generated
0
ENABLED
Reset generated
0x1
FATAL
Fatal Reset
5
1
read-write
oneToClear
DISABLED
Reset was not generated
0
ENABLED
Reset was generated
0x1
PIN
Pin Reset
8
1
read-write
oneToClear
DISABLED
Reset not generated
0
ENABLED
Reset generated
0x1
DAP
DAP Reset
9
1
read-write
oneToClear
DISABLED
Reset not generated
0
ENABLED
Reset generated
0x1
RSTACK
Reset Timeout
10
1
read-write
oneToClear
DISABLED
Reset not generated
0
ENABLED
Reset generated
0x1
LPACK
Low Power Acknowledge Timeout Reset
11
1
read-write
oneToClear
DISABLED
Reset not generated
0
ENABLED
Reset generated
0x1
SCG
System Clock Generation Reset
12
1
read-write
oneToClear
DISABLED
Reset is not generated
0
ENABLED
Reset is generated
0x1
WWDT0
Windowed Watchdog 0 Reset
13
1
read-write
oneToClear
DISABLED
Reset is not generated
0
ENABLED
Reset is generated
0x1
SW
Software Reset
14
1
read-write
oneToClear
DISABLED
Reset not generated
0
ENABLED
Reset generated
0x1
LOCKUP
Lockup Reset
15
1
read-write
oneToClear
DISABLED
Reset not generated
0
ENABLED
Reset generated
0x1
CDOG0
Code Watchdog 0 Reset
26
1
read-write
oneToClear
DISABLED
Reset is not generated
0
ENABLED
Reset is generated
0x1
JTAG
JTAG System Reset
28
1
read-write
oneToClear
DISABLED
Reset not generated
0
ENABLED
Reset generated
0x1
SRIE
System Reset Interrupt Enable
0x8C
32
read-write
0x8800
0xFFFFFFFF
PIN
Pin Reset
8
1
read-write
DISABLED
Interrupt disabled
0
ENABLED
Interrupt enabled
0x1
DAP
DAP Reset
9
1
read-write
DISABLED
Interrupt disabled
0
ENABLED
Interrupt enabled
0x1
LPACK
Low Power Acknowledge Timeout Reset
11
1
read-write
DISABLED
Interrupt disabled
0
ENABLED
Interrupt enabled
0x1
SCG
System Clock Generation Reset
12
1
read-write
DISABLED
Interrupt disabled
0
ENABLED
Interrupt enabled
0x1
WWDT0
Windowed Watchdog 0 Reset
13
1
read-write
DISABLED
Interrupt disabled
0
ENABLED
Interrupt enabled
0x1
SW
Software Reset
14
1
read-write
DISABLED
Interrupt disabled
0
ENABLED
Interrupt enabled
0x1
LOCKUP
Lockup Reset
15
1
read-write
DISABLED
Interrupt disabled
0
ENABLED
Interrupt enabled
0x1
CDOG0
Code Watchdog 0 Reset
26
1
read-write
DISABLED
Interrupt disabled
0
ENABLED
Interrupt enabled
0x1
SRIF
System Reset Interrupt Flag
0x90
32
read-write
0
0xFFFFFFFF
oneToClear
PIN
Pin Reset
8
1
read-write
oneToClear
DISABLED
Reset source not pending
0
ENABLED
Reset source pending
0x1
DAP
DAP Reset
9
1
read-write
oneToClear
DISABLED
Reset source not pending
0
ENABLED
Reset source pending
0x1
LPACK
Low Power Acknowledge Timeout Reset
11
1
read-write
oneToClear
DISABLED
Reset source not pending
0
ENABLED
Reset source pending
0x1
WWDT0
Windowed Watchdog 0 Reset
13
1
read-write
oneToClear
DISABLED
Reset source not pending
0
ENABLED
Reset source pending
0x1
SW
Software Reset
14
1
read-write
oneToClear
DISABLED
Reset source not pending
0
ENABLED
Reset source pending
0x1
LOCKUP
Lockup Reset
15
1
read-write
oneToClear
DISABLED
Reset source not pending
0
ENABLED
Reset source pending
0x1
CDOG0
Code Watchdog 0 Reset
26
1
read-write
oneToClear
DISABLED
Reset source not pending
0
ENABLED
Reset source pending
0x1
RSTCNT
Reset Count Register
0x9C
32
read-only
0
0xFFFFFFFF
COUNT
Count
0
8
read-only
MR0
Mode
0xA0
32
read-write
0
0xFFFFFFFF
oneToClear
ISPMODE_n
In System Programming Mode
0
1
read-write
oneToClear
FM0
Force Mode
0xB0
32
read-write
0
0xFFFFFFFF
FORCECFG
Boot Configuration
0
1
read-write
DISABLED
No effect
0
ENABLED
Asserts
0x1
FLASHCR
Flash Control
0xE0
32
read-write
0
0xFFFFFFFF
FLASHDIS
Flash Disable
0
1
read-write
DISABLED
No effect
0
ENABLED
Flash memory is disabled
0x1
FLASHDOZE
Flash Doze
1
1
read-write
DISABLED
No effect
0
ENABLED
Flash memory is disabled when core is sleeping (CKMODE > 0)
0x1
FLASHWAKE
Flash Wake
2
1
read-write
DISABLED
No effect
0
ENABLED
Flash memory is not disabled during flash memory accesses
0x1
CORECTL
Core Control
0x110
32
read-write
0
0xFFFFFFFF
NPIE
Non-maskable Pin Interrupt Enable
0
1
read-write
DISABLED
Disables
0
ENABLED
Enables
0x1
DBGCTL
Debug Control
0x120
32
read-write
0
0xFFFFFFFF
SOD
Sleep Or Debug
0
1
read-write
DISABLED
Remains enabled
0
ENABLED
Disabled
0x1
EIM0
EIM
EIM
0x4008C000
0
0x108
registers
EIMCR
Error Injection Module Configuration Register
0
32
read-write
0
0xFFFFFFFF
GEIEN
Global Error Injection Enable
0
1
read-write
DISABLE
Disabled
0
ENABLE
Enabled
0x1
EICHEN
Error Injection Channel Enable register
0x4
32
read-write
0
0xFFFFFFFF
EICH0EN
Error Injection Channel 0 Enable
31
1
read-write
DISABLE
Error injection is disabled on Error Injection Channel 0
0
ENABLE
Error injection is enabled on Error Injection Channel 0
0x1
EICHD0_WORD0
Error Injection Channel Descriptor 0, Word0
0x100
32
read-write
0
0xFFFFFFFF
CHKBIT_MASK
Checkbit Mask
25
7
read-write
EICHD0_WORD1
Error Injection Channel Descriptor 0, Word1
0x104
32
read-write
0
0xFFFFFFFF
B0_3DATA_MASK
Data Mask Bytes 0-3
0
32
read-write
ERM0
ERM
ERM
0x4008D000
0
0x11C
registers
ERM0_SINGLE_BIT
10
ERM0_MULTI_BIT
11
CR0
ERM Configuration Register 0
0
32
read-write
0
0xFFFFFFFF
ENCIE1
ENCIE1
26
1
read-write
DISABLE
Interrupt notification of Memory 1 non-correctable error events is disabled.
0
ENABLE
Interrupt notification of Memory 1 non-correctable error events is enabled.
0x1
ESCIE1
ESCIE1
27
1
read-write
DISABLE
Interrupt notification of Memory 1 single-bit correction events is disabled.
0
ENABLE
Interrupt notification of Memory 1 single-bit correction events is enabled.
0x1
ENCIE0
ENCIE0
30
1
read-write
DISABLE
Interrupt notification of Memory 0 non-correctable error events is disabled.
0
ENABLE
Interrupt notification of Memory 0 non-correctable error events is enabled.
0x1
ESCIE0
ESCIE0
31
1
read-write
DISABLE
Interrupt notification of Memory 0 single-bit correction events is disabled.
0
ENABLE
Interrupt notification of Memory 0 single-bit correction events is enabled.
0x1
SR0
ERM Status Register 0
0x10
32
read-write
0
0xFFFFFFFF
oneToClear
NCE1
NCE1
26
1
read-write
oneToClear
NO_ERROR
No non-correctable error event on Memory 1 detected.
0
ERROR
Non-correctable error event on Memory 1 detected.
0x1
SBC1
SBC1
27
1
read-write
oneToClear
NO_EVENT
No single-bit correction event on Memory 1 detected.
0
EVENT
Single-bit correction event on Memory 1 detected.
0x1
NCE0
NCE0
30
1
read-write
oneToClear
NO_ERROR
No non-correctable error event on Memory 0 detected.
0
ERROR
Non-correctable error event on Memory 0 detected.
0x1
SBC0
SBC0
31
1
read-write
oneToClear
NO_EVENT
No single-bit correction event on Memory 0 detected.
0
EVENT
Single-bit correction event on Memory 0 detected.
0x1
EAR0
ERM Memory 0 Error Address Register
0x100
32
read-only
0
0xFFFFFFFF
EAR
EAR
0
32
read-only
SYN0
ERM Memory 0 Syndrome Register
0x104
32
read-only
0
0xFFFFFFFF
SYNDROME
SYNDROME
24
8
read-only
CORR_ERR_CNT0
ERM Memory 0 Correctable Error Count Register
0x108
32
read-write
0
0xFFFFFFFF
COUNT
Memory n Correctable Error Count
0
8
read-write
CORR_ERR_CNT1
ERM Memory 1 Correctable Error Count Register
0x118
32
read-write
0
0xFFFFFFFF
COUNT
Memory n Correctable Error Count
0
8
read-write
MBC0
TRDC
MBC
0x4008E000
0
0x1CC
registers
MBC0
14
MBC0_MEM0_GLBCFG
MBC Global Configuration Register
0
32
read-only
0xD0010
0xFFFFFFFF
NBLKS
Number of blocks in this memory
0
10
read-only
SIZE_LOG2
Log2 size per block
16
5
read-only
MBC0_MEM1_GLBCFG
MBC Global Configuration Register
0x4
32
read-only
0xD0004
0xFFFFFFFF
NBLKS
Number of blocks in this memory
0
10
read-only
SIZE_LOG2
Log2 size per block
16
5
read-only
MBC0_MEM2_GLBCFG
MBC Global Configuration Register
0x8
32
read-only
0xB0004
0xFFFFFFFF
NBLKS
Number of blocks in this memory
0
10
read-only
SIZE_LOG2
Log2 size per block
16
5
read-only
MBC0_MEM3_GLBCFG
MBC Global Configuration Register
0xC
32
read-write
0
0xFFFFFFFF
NBLKS
Number of blocks in this memory
0
10
read-only
SIZE_LOG2
Log2 size per block
16
5
read-only
CLRE
Clear Error
30
2
read-write
MBC0_NSE_BLK_INDEX
MBC NonSecure Enable Block Index
0x10
32
read-write
0
0xFFFFFFFF
WNDX
Word index into the block NSE bitmap. It selects the BLK_NSE_Wn register, where WNDX determines the value of n.
2
4
read-write
MEM_SEL
Memory Select
8
4
read-write
DID_SEL0
DID Select
16
1
read-write
LOGIC_0
No effect.
0
LOGIC_1
Selects NSE bits for this domain.
0x1
AI
Auto Increment
31
1
read-write
LOGIC_0
No effect.
0
LOGIC_1
Add 1 to the WNDX field after the register write.
0x1
MBC0_NSE_BLK_SET
MBC NonSecure Enable Block Set
0x14
32
read-write
0
0xFFFFFFFF
W1SET
Write-1 Set
0
32
read-write
MBC0_NSE_BLK_CLR
MBC NonSecure Enable Block Clear
0x18
32
read-write
0
0xFFFFFFFF
W1CLR
Write-1 Clear
0
32
read-write
MBC0_NSE_BLK_CLR_ALL
MBC NonSecure Enable Block Clear All
0x1C
32
read-write
0
0xFFFFFFFF
MEMSEL
Memory Select
8
4
read-write
DID_SEL0
DID Select
16
1
read-write
LOGIC_0
No effect.
0
LOGIC_1
Clear all NSE bits for this domain.
0x1
MBC0_MEMN_GLBAC0
MBC Global Access Control
0x20
32
read-write
0x6600
0xFFFFFFFF
NUX
NonsecureUser Execute
0
1
read-write
NOTALLOWED
Execute access is not allowed in Nonsecure User mode.
0
ALLOWED
Execute access is allowed in Nonsecure User mode.
0x1
NUW
NonsecureUser Write
1
1
read-write
NOTALLOWED
Write access is not allowed in Nonsecure User mode.
0
ALLOWED
Write access is allowed in Nonsecure User mode.
0x1
NUR
NonsecureUser Read
2
1
read-write
NOTALLOWED
Read access is not allowed in Nonsecure User mode.
0
ALLOWED
Read access is allowed in Nonsecure User mode.
0x1
NPX
NonsecurePriv Execute
4
1
read-write
NOTALLOWED
Execute access is not allowed in Nonsecure Privilege mode.
0
ALLOWED
Execute access is allowed in Nonsecure Privilege mode.
0x1
NPW
NonsecurePriv Write
5
1
read-write
NOTALLOWED
Write access is not allowed in Nonsecure Privilege mode.
0
ALLOWED
Write access is allowed in Nonsecure Privilege mode.
0x1
NPR
NonsecurePriv Read
6
1
read-write
NOTALLOWED
Read access is not allowed in Nonsecure Privilege mode.
0
ALLOWED
Read access is allowed in Nonsecure Privilege mode.
0x1
SUX
SecureUser Execute
8
1
read-write
NOTALLOWED
Execute access is not allowed in Secure User mode.
0
ALLOWED
Execute access is allowed in Secure User mode.
0x1
SUW
SecureUser Write
9
1
read-write
NOTALLOWED
Write access is not allowed in Secure User mode.
0
ALLOWED
Write access is allowed in Secure User mode.
0x1
SUR
SecureUser Read
10
1
read-write
NOTALLOWED
Read access is not allowed in Secure User mode.
0
ALLOWED
Read access is allowed in Secure User mode.
0x1
SPX
SecurePriv Execute
12
1
read-write
NOTALLOWED
Execute access is not allowed in Secure Privilege mode.
0
ALLOWED
Execute access is allowed in Secure Privilege mode.
0x1
SPW
SecurePriv Write
13
1
read-write
NOTALLOWED
Write access is not allowed in Secure Privilege mode.
0
ALLOWED
Write access is allowed in Secure Privilege mode.
0x1
SPR
SecurePriv Read
14
1
read-write
NOTALLOWED
Read access is not allowed in Secure Privilege mode.
0
ALLOWED
Read access is allowed in Secure Privilege mode.
0x1
MBC0_MEMN_GLBAC1
MBC Global Access Control
0x24
32
read-write
0x80006600
0xFFFFFFFF
NUX
NonsecureUser Execute
0
1
read-write
NOTALLOWED
Execute access is not allowed in Nonsecure User mode.
0
ALLOWED
Execute access is allowed in Nonsecure User mode.
0x1
NUW
NonsecureUser Write
1
1
read-write
NOTALLOWED
Write access is not allowed in Nonsecure User mode.
0
ALLOWED
Write access is allowed in Nonsecure User mode.
0x1
NUR
NonsecureUser Read
2
1
read-write
NOTALLOWED
Read access is not allowed in Nonsecure User mode.
0
ALLOWED
Read access is allowed in Nonsecure User mode.
0x1
NPX
NonsecurePriv Execute
4
1
read-write
NOTALLOWED
Execute access is not allowed in Nonsecure Privilege mode.
0
ALLOWED
Execute access is allowed in Nonsecure Privilege mode.
0x1
NPW
NonsecurePriv Write
5
1
read-write
NOTALLOWED
Write access is not allowed in Nonsecure Privilege mode.
0
ALLOWED
Write access is allowed in Nonsecure Privilege mode.
0x1
NPR
NonsecurePriv Read
6
1
read-write
NOTALLOWED
Read access is not allowed in Nonsecure Privilege mode.
0
ALLOWED
Read access is allowed in Nonsecure Privilege mode.
0x1
SUX
SecureUser Execute
8
1
read-write
NOTALLOWED
Execute access is not allowed in Secure User mode.
0
ALLOWED
Execute access is allowed in Secure User mode.
0x1
SUW
SecureUser Write
9
1
read-write
NOTALLOWED
Write access is not allowed in Secure User mode.
0
ALLOWED
Write access is allowed in Secure User mode.
0x1
SUR
SecureUser Read
10
1
read-write
NOTALLOWED
Read access is not allowed in Secure User mode.
0
ALLOWED
Read access is allowed in Secure User mode.
0x1
SPX
SecurePriv Execute
12
1
read-write
NOTALLOWED
Execute access is not allowed in Secure Privilege mode.
0
ALLOWED
Execute access is allowed in Secure Privilege mode.
0x1
SPW
SecurePriv Write
13
1
read-write
NOTALLOWED
Write access is not allowed in Secure Privilege mode.
0
ALLOWED
Write access is allowed in Secure Privilege mode.
0x1
SPR
SecurePriv Read
14
1
read-write
NOTALLOWED
Read access is not allowed in Secure Privilege mode.
0
ALLOWED
Read access is allowed in Secure Privilege mode.
0x1
LK
LOCK
31
1
read-write
UNLOCKED
This register is not locked and can be altered.
0
LOCKED
This register is locked and cannot be altered.
0x1
MBC0_MEMN_GLBAC2
MBC Global Access Control
0x28
32
read-write
0x80005500
0xFFFFFFFF
NUX
NonsecureUser Execute
0
1
read-write
NOTALLOWED
Execute access is not allowed in Nonsecure User mode.
0
ALLOWED
Execute access is allowed in Nonsecure User mode.
0x1
NUW
NonsecureUser Write
1
1
read-write
NOTALLOWED
Write access is not allowed in Nonsecure User mode.
0
ALLOWED
Write access is allowed in Nonsecure User mode.
0x1
NUR
NonsecureUser Read
2
1
read-write
NOTALLOWED
Read access is not allowed in Nonsecure User mode.
0
ALLOWED
Read access is allowed in Nonsecure User mode.
0x1
NPX
NonsecurePriv Execute
4
1
read-write
NOTALLOWED
Execute access is not allowed in Nonsecure Privilege mode.
0
ALLOWED
Execute access is allowed in Nonsecure Privilege mode.
0x1
NPW
NonsecurePriv Write
5
1
read-write
NOTALLOWED
Write access is not allowed in Nonsecure Privilege mode.
0
ALLOWED
Write access is allowed in Nonsecure Privilege mode.
0x1
NPR
NonsecurePriv Read
6
1
read-write
NOTALLOWED
Read access is not allowed in Nonsecure Privilege mode.
0
ALLOWED
Read access is allowed in Nonsecure Privilege mode.
0x1
SUX
SecureUser Execute
8
1
read-write
NOTALLOWED
Execute access is not allowed in Secure User mode.
0
ALLOWED
Execute access is allowed in Secure User mode.
0x1
SUW
SecureUser Write
9
1
read-write
NOTALLOWED
Write access is not allowed in Secure User mode.
0
ALLOWED
Write access is allowed in Secure User mode.
0x1
SUR
SecureUser Read
10
1
read-write
NOTALLOWED
Read access is not allowed in Secure User mode.
0
ALLOWED
Read access is allowed in Secure User mode.
0x1
SPX
SecurePriv Execute
12
1
read-write
NOTALLOWED
Execute access is not allowed in Secure Privilege mode.
0
ALLOWED
Execute access is allowed in Secure Privilege mode.
0x1
SPW
SecurePriv Write
13
1
read-write
NOTALLOWED
Write access is not allowed in Secure Privilege mode.
0
ALLOWED
Write access is allowed in Secure Privilege mode.
0x1
SPR
SecurePriv Read
14
1
read-write
NOTALLOWED
Read access is not allowed in Secure Privilege mode.
0
ALLOWED
Read access is allowed in Secure Privilege mode.
0x1
LK
LOCK
31
1
read-write
UNLOCKED
This register is not locked and can be altered.
0
LOCKED
This register is locked and cannot be altered.
0x1
MBC0_MEMN_GLBAC3
MBC Global Access Control
0x2C
32
read-write
0x80004400
0xFFFFFFFF
NUX
NonsecureUser Execute
0
1
read-write
NOTALLOWED
Execute access is not allowed in Nonsecure User mode.
0
ALLOWED
Execute access is allowed in Nonsecure User mode.
0x1
NUW
NonsecureUser Write
1
1
read-write
NOTALLOWED
Write access is not allowed in Nonsecure User mode.
0
ALLOWED
Write access is allowed in Nonsecure User mode.
0x1
NUR
NonsecureUser Read
2
1
read-write
NOTALLOWED
Read access is not allowed in Nonsecure User mode.
0
ALLOWED
Read access is allowed in Nonsecure User mode.
0x1
NPX
NonsecurePriv Execute
4
1
read-write
NOTALLOWED
Execute access is not allowed in Nonsecure Privilege mode.
0
ALLOWED
Execute access is allowed in Nonsecure Privilege mode.
0x1
NPW
NonsecurePriv Write
5
1
read-write
NOTALLOWED
Write access is not allowed in Nonsecure Privilege mode.
0
ALLOWED
Write access is allowed in Nonsecure Privilege mode.
0x1
NPR
NonsecurePriv Read
6
1
read-write
NOTALLOWED
Read access is not allowed in Nonsecure Privilege mode.
0
ALLOWED
Read access is allowed in Nonsecure Privilege mode.
0x1
SUX
SecureUser Execute
8
1
read-write
NOTALLOWED
Execute access is not allowed in Secure User mode.
0
ALLOWED
Execute access is allowed in Secure User mode.
0x1
SUW
SecureUser Write
9
1
read-write
NOTALLOWED
Write access is not allowed in Secure User mode.
0
ALLOWED
Write access is allowed in Secure User mode.
0x1
SUR
SecureUser Read
10
1
read-write
NOTALLOWED
Read access is not allowed in Secure User mode.
0
ALLOWED
Read access is allowed in Secure User mode.
0x1
SPX
SecurePriv Execute
12
1
read-write
NOTALLOWED
Execute access is not allowed in Secure Privilege mode.
0
ALLOWED
Execute access is allowed in Secure Privilege mode.
0x1
SPW
SecurePriv Write
13
1
read-write
NOTALLOWED
Write access is not allowed in Secure Privilege mode.
0
ALLOWED
Write access is allowed in Secure Privilege mode.
0x1
SPR
SecurePriv Read
14
1
read-write
NOTALLOWED
Read access is not allowed in Secure Privilege mode.
0
ALLOWED
Read access is allowed in Secure Privilege mode.
0x1
LK
LOCK
31
1
read-write
UNLOCKED
This register is not locked and can be altered.
0
LOCKED
This register is locked and cannot be altered.
0x1
MBC0_MEMN_GLBAC4
MBC Global Access Control
0x30
32
read-write
0x5500
0xFFFFFFFF
NUX
NonsecureUser Execute
0
1
read-write
NOTALLOWED
Execute access is not allowed in Nonsecure User mode.
0
ALLOWED
Execute access is allowed in Nonsecure User mode.
0x1
NUW
NonsecureUser Write
1
1
read-write
NOTALLOWED
Write access is not allowed in Nonsecure User mode.
0
ALLOWED
Write access is allowed in Nonsecure User mode.
0x1
NUR
NonsecureUser Read
2
1
read-write
NOTALLOWED
Read access is not allowed in Nonsecure User mode.
0
ALLOWED
Read access is allowed in Nonsecure User mode.
0x1
NPX
NonsecurePriv Execute
4
1
read-write
NOTALLOWED
Execute access is not allowed in Nonsecure Privilege mode.
0
ALLOWED
Execute access is allowed in Nonsecure Privilege mode.
0x1
NPW
NonsecurePriv Write
5
1
read-write
NOTALLOWED
Write access is not allowed in Nonsecure Privilege mode.
0
ALLOWED
Write access is allowed in Nonsecure Privilege mode.
0x1
NPR
NonsecurePriv Read
6
1
read-write
NOTALLOWED
Read access is not allowed in Nonsecure Privilege mode.
0
ALLOWED
Read access is allowed in Nonsecure Privilege mode.
0x1
SUX
SecureUser Execute
8
1
read-write
NOTALLOWED
Execute access is not allowed in Secure User mode.
0
ALLOWED
Execute access is allowed in Secure User mode.
0x1
SUW
SecureUser Write
9
1
read-write
NOTALLOWED
Write access is not allowed in Secure User mode.
0
ALLOWED
Write access is allowed in Secure User mode.
0x1
SUR
SecureUser Read
10
1
read-write
NOTALLOWED
Read access is not allowed in Secure User mode.
0
ALLOWED
Read access is allowed in Secure User mode.
0x1
SPX
SecurePriv Execute
12
1
read-write
NOTALLOWED
Execute access is not allowed in Secure Privilege mode.
0
ALLOWED
Execute access is allowed in Secure Privilege mode.
0x1
SPW
SecurePriv Write
13
1
read-write
NOTALLOWED
Write access is not allowed in Secure Privilege mode.
0
ALLOWED
Write access is allowed in Secure Privilege mode.
0x1
SPR
SecurePriv Read
14
1
read-write
NOTALLOWED
Read access is not allowed in Secure Privilege mode.
0
ALLOWED
Read access is allowed in Secure Privilege mode.
0x1
LK
LOCK
31
1
read-write
UNLOCKED
This register is not locked and can be altered.
0
LOCKED
This register is locked and cannot be altered.
0x1
MBC0_MEMN_GLBAC5
MBC Global Access Control
0x34
32
read-write
0x1100
0xFFFFFFFF
NUX
NonsecureUser Execute
0
1
read-write
NOTALLOWED
Execute access is not allowed in Nonsecure User mode.
0
ALLOWED
Execute access is allowed in Nonsecure User mode.
0x1
NUW
NonsecureUser Write
1
1
read-write
NOTALLOWED
Write access is not allowed in Nonsecure User mode.
0
ALLOWED
Write access is allowed in Nonsecure User mode.
0x1
NUR
NonsecureUser Read
2
1
read-write
NOTALLOWED
Read access is not allowed in Nonsecure User mode.
0
ALLOWED
Read access is allowed in Nonsecure User mode.
0x1
NPX
NonsecurePriv Execute
4
1
read-write
NOTALLOWED
Execute access is not allowed in Nonsecure Privilege mode.
0
ALLOWED
Execute access is allowed in Nonsecure Privilege mode.
0x1
NPW
NonsecurePriv Write
5
1
read-write
NOTALLOWED
Write access is not allowed in Nonsecure Privilege mode.
0
ALLOWED
Write access is allowed in Nonsecure Privilege mode.
0x1
NPR
NonsecurePriv Read
6
1
read-write
NOTALLOWED
Read access is not allowed in Nonsecure Privilege mode.
0
ALLOWED
Read access is allowed in Nonsecure Privilege mode.
0x1
SUX
SecureUser Execute
8
1
read-write
NOTALLOWED
Execute access is not allowed in Secure User mode.
0
ALLOWED
Execute access is allowed in Secure User mode.
0x1
SUW
SecureUser Write
9
1
read-write
NOTALLOWED
Write access is not allowed in Secure User mode.
0
ALLOWED
Write access is allowed in Secure User mode.
0x1
SUR
SecureUser Read
10
1
read-write
NOTALLOWED
Read access is not allowed in Secure User mode.
0
ALLOWED
Read access is allowed in Secure User mode.
0x1
SPX
SecurePriv Execute
12
1
read-write
NOTALLOWED
Execute access is not allowed in Secure Privilege mode.
0
ALLOWED
Execute access is allowed in Secure Privilege mode.
0x1
SPW
SecurePriv Write
13
1
read-write
NOTALLOWED
Write access is not allowed in Secure Privilege mode.
0
ALLOWED
Write access is allowed in Secure Privilege mode.
0x1
SPR
SecurePriv Read
14
1
read-write
NOTALLOWED
Read access is not allowed in Secure Privilege mode.
0
ALLOWED
Read access is allowed in Secure Privilege mode.
0x1
LK
LOCK
31
1
read-write
UNLOCKED
This register is not locked and can be altered.
0
LOCKED
This register is locked and cannot be altered.
0x1
MBC0_MEMN_GLBAC6
MBC Global Access Control
0x38
32
read-write
0x80001100
0xFFFFFFFF
NUX
NonsecureUser Execute
0
1
read-write
NOTALLOWED
Execute access is not allowed in Nonsecure User mode.
0
ALLOWED
Execute access is allowed in Nonsecure User mode.
0x1
NUW
NonsecureUser Write
1
1
read-write
NOTALLOWED
Write access is not allowed in Nonsecure User mode.
0
ALLOWED
Write access is allowed in Nonsecure User mode.
0x1
NUR
NonsecureUser Read
2
1
read-write
NOTALLOWED
Read access is not allowed in Nonsecure User mode.
0
ALLOWED
Read access is allowed in Nonsecure User mode.
0x1
NPX
NonsecurePriv Execute
4
1
read-write
NOTALLOWED
Execute access is not allowed in Nonsecure Privilege mode.
0
ALLOWED
Execute access is allowed in Nonsecure Privilege mode.
0x1
NPW
NonsecurePriv Write
5
1
read-write
NOTALLOWED
Write access is not allowed in Nonsecure Privilege mode.
0
ALLOWED
Write access is allowed in Nonsecure Privilege mode.
0x1
NPR
NonsecurePriv Read
6
1
read-write
NOTALLOWED
Read access is not allowed in Nonsecure Privilege mode.
0
ALLOWED
Read access is allowed in Nonsecure Privilege mode.
0x1
SUX
SecureUser Execute
8
1
read-write
NOTALLOWED
Execute access is not allowed in Secure User mode.
0
ALLOWED
Execute access is allowed in Secure User mode.
0x1
SUW
SecureUser Write
9
1
read-write
NOTALLOWED
Write access is not allowed in Secure User mode.
0
ALLOWED
Write access is allowed in Secure User mode.
0x1
SUR
SecureUser Read
10
1
read-write
NOTALLOWED
Read access is not allowed in Secure User mode.
0
ALLOWED
Read access is allowed in Secure User mode.
0x1
SPX
SecurePriv Execute
12
1
read-write
NOTALLOWED
Execute access is not allowed in Secure Privilege mode.
0
ALLOWED
Execute access is allowed in Secure Privilege mode.
0x1
SPW
SecurePriv Write
13
1
read-write
NOTALLOWED
Write access is not allowed in Secure Privilege mode.
0
ALLOWED
Write access is allowed in Secure Privilege mode.
0x1
SPR
SecurePriv Read
14
1
read-write
NOTALLOWED
Read access is not allowed in Secure Privilege mode.
0
ALLOWED
Read access is allowed in Secure Privilege mode.
0x1
LK
LOCK
31
1
read-write
UNLOCKED
This register is not locked and can be altered.
0
LOCKED
This register is locked and cannot be altered.
0x1
MBC0_MEMN_GLBAC7
MBC Global Access Control
0x3C
32
read-write
0x80000000
0xFFFFFFFF
NUX
NonsecureUser Execute
0
1
read-write
NOTALLOWED
Execute access is not allowed in Nonsecure User mode.
0
ALLOWED
Execute access is allowed in Nonsecure User mode.
0x1
NUW
NonsecureUser Write
1
1
read-write
NOTALLOWED
Write access is not allowed in Nonsecure User mode.
0
ALLOWED
Write access is allowed in Nonsecure User mode.
0x1
NUR
NonsecureUser Read
2
1
read-write
NOTALLOWED
Read access is not allowed in Nonsecure User mode.
0
ALLOWED
Read access is allowed in Nonsecure User mode.
0x1
NPX
NonsecurePriv Execute
4
1
read-write
NOTALLOWED
Execute access is not allowed in Nonsecure Privilege mode.
0
ALLOWED
Execute access is allowed in Nonsecure Privilege mode.
0x1
NPW
NonsecurePriv Write
5
1
read-write
NOTALLOWED
Write access is not allowed in Nonsecure Privilege mode.
0
ALLOWED
Write access is allowed in Nonsecure Privilege mode.
0x1
NPR
NonsecurePriv Read
6
1
read-write
NOTALLOWED
Read access is not allowed in Nonsecure Privilege mode.
0
ALLOWED
Read access is allowed in Nonsecure Privilege mode.
0x1
SUX
SecureUser Execute
8
1
read-write
NOTALLOWED
Execute access is not allowed in Secure User mode.
0
ALLOWED
Execute access is allowed in Secure User mode.
0x1
SUW
SecureUser Write
9
1
read-write
NOTALLOWED
Write access is not allowed in Secure User mode.
0
ALLOWED
Write access is allowed in Secure User mode.
0x1
SUR
SecureUser Read
10
1
read-write
NOTALLOWED
Read access is not allowed in Secure User mode.
0
ALLOWED
Read access is allowed in Secure User mode.
0x1
SPX
SecurePriv Execute
12
1
read-write
NOTALLOWED
Execute access is not allowed in Secure Privilege mode.
0
ALLOWED
Execute access is allowed in Secure Privilege mode.
0x1
SPW
SecurePriv Write
13
1
read-write
NOTALLOWED
Write access is not allowed in Secure Privilege mode.
0
ALLOWED
Write access is allowed in Secure Privilege mode.
0x1
SPR
SecurePriv Read
14
1
read-write
NOTALLOWED
Read access is not allowed in Secure Privilege mode.
0
ALLOWED
Read access is allowed in Secure Privilege mode.
0x1
LK
LOCK
31
1
read-write
UNLOCKED
This register is not locked and can be altered.
0
LOCKED
This register is locked and cannot be altered.
0x1
MBC0_DOM0_MEM0_BLK_CFG_W0
MBC Memory Block Configuration Word
0x40
32
read-write
0
0xFFFFFFFF
MBACSEL0
Memory Block Access Control Select for block B
0
3
read-write
GLBAC0
select MBC_MEMN_GLBAC0 access control policy for block B
0
GLBAC1
select MBC_MEMN_GLBAC1 access control policy for block B
0x1
GLBAC2
select MBC_MEMN_GLBAC2 access control policy for block B
0x2
GLBAC3
select MBC_MEMN_GLBAC3 access control policy for block B
0x3
GLBAC4
select MBC_MEMN_GLBAC4 access control policy for block B
0x4
GLBAC5
select MBC_MEMN_GLBAC5 access control policy for block B
0x5
GLBAC6
select MBC_MEMN_GLBAC6 access control policy for block B
0x6
GLBAC7
select MBC_MEMN_GLBAC7 access control policy for block B
0x7
NSE0
NonSecure Enable for block B
3
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
MBACSEL1
Memory Block Access Control Select for block B
4
3
read-write
GLBAC0
select MBC_MEMN_GLBAC0 access control policy for block B
0
GLBAC1
select MBC_MEMN_GLBAC1 access control policy for block B
0x1
GLBAC2
select MBC_MEMN_GLBAC2 access control policy for block B
0x2
GLBAC3
select MBC_MEMN_GLBAC3 access control policy for block B
0x3
GLBAC4
select MBC_MEMN_GLBAC4 access control policy for block B
0x4
GLBAC5
select MBC_MEMN_GLBAC5 access control policy for block B
0x5
GLBAC6
select MBC_MEMN_GLBAC6 access control policy for block B
0x6
GLBAC7
select MBC_MEMN_GLBAC7 access control policy for block B
0x7
NSE1
NonSecure Enable for block B
7
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
MBACSEL2
Memory Block Access Control Select for block B
8
3
read-write
GLBAC0
select MBC_MEMN_GLBAC0 access control policy for block B
0
GLBAC1
select MBC_MEMN_GLBAC1 access control policy for block B
0x1
GLBAC2
select MBC_MEMN_GLBAC2 access control policy for block B
0x2
GLBAC3
select MBC_MEMN_GLBAC3 access control policy for block B
0x3
GLBAC4
select MBC_MEMN_GLBAC4 access control policy for block B
0x4
GLBAC5
select MBC_MEMN_GLBAC5 access control policy for block B
0x5
GLBAC6
select MBC_MEMN_GLBAC6 access control policy for block B
0x6
GLBAC7
select MBC_MEMN_GLBAC7 access control policy for block B
0x7
NSE2
NonSecure Enable for block B
11
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
MBACSEL3
Memory Block Access Control Select for block B
12
3
read-write
GLBAC0
select MBC_MEMN_GLBAC0 access control policy for block B
0
GLBAC1
select MBC_MEMN_GLBAC1 access control policy for block B
0x1
GLBAC2
select MBC_MEMN_GLBAC2 access control policy for block B
0x2
GLBAC3
select MBC_MEMN_GLBAC3 access control policy for block B
0x3
GLBAC4
select MBC_MEMN_GLBAC4 access control policy for block B
0x4
GLBAC5
select MBC_MEMN_GLBAC5 access control policy for block B
0x5
GLBAC6
select MBC_MEMN_GLBAC6 access control policy for block B
0x6
GLBAC7
select MBC_MEMN_GLBAC7 access control policy for block B
0x7
NSE3
NonSecure Enable for block B
15
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
MBACSEL4
Memory Block Access Control Select for block B
16
3
read-write
GLBAC0
select MBC_MEMN_GLBAC0 access control policy for block B
0
GLBAC1
select MBC_MEMN_GLBAC1 access control policy for block B
0x1
GLBAC2
select MBC_MEMN_GLBAC2 access control policy for block B
0x2
GLBAC3
select MBC_MEMN_GLBAC3 access control policy for block B
0x3
GLBAC4
select MBC_MEMN_GLBAC4 access control policy for block B
0x4
GLBAC5
select MBC_MEMN_GLBAC5 access control policy for block B
0x5
GLBAC6
select MBC_MEMN_GLBAC6 access control policy for block B
0x6
GLBAC7
select MBC_MEMN_GLBAC7 access control policy for block B
0x7
NSE4
NonSecure Enable for block B
19
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
MBACSEL5
Memory Block Access Control Select for block B
20
3
read-write
GLBAC0
select MBC_MEMN_GLBAC0 access control policy for block B
0
GLBAC1
select MBC_MEMN_GLBAC1 access control policy for block B
0x1
GLBAC2
select MBC_MEMN_GLBAC2 access control policy for block B
0x2
GLBAC3
select MBC_MEMN_GLBAC3 access control policy for block B
0x3
GLBAC4
select MBC_MEMN_GLBAC4 access control policy for block B
0x4
GLBAC5
select MBC_MEMN_GLBAC5 access control policy for block B
0x5
GLBAC6
select MBC_MEMN_GLBAC6 access control policy for block B
0x6
GLBAC7
select MBC_MEMN_GLBAC7 access control policy for block B
0x7
NSE5
NonSecure Enable for block B
23
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
MBACSEL6
Memory Block Access Control Select for block B
24
3
read-write
GLBAC0
select MBC_MEMN_GLBAC0 access control policy for block B
0
GLBAC1
select MBC_MEMN_GLBAC1 access control policy for block B
0x1
GLBAC2
select MBC_MEMN_GLBAC2 access control policy for block B
0x2
GLBAC3
select MBC_MEMN_GLBAC3 access control policy for block B
0x3
GLBAC4
select MBC_MEMN_GLBAC4 access control policy for block B
0x4
GLBAC5
select MBC_MEMN_GLBAC5 access control policy for block B
0x5
GLBAC6
select MBC_MEMN_GLBAC6 access control policy for block B
0x6
GLBAC7
select MBC_MEMN_GLBAC7 access control policy for block B
0x7
NSE6
NonSecure Enable for block B
27
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
MBACSEL7
Memory Block Access Control Select for block B
28
3
read-write
GLBAC0
select MBC_MEMN_GLBAC0 access control policy for block B
0
GLBAC1
select MBC_MEMN_GLBAC1 access control policy for block B
0x1
GLBAC2
select MBC_MEMN_GLBAC2 access control policy for block B
0x2
GLBAC3
select MBC_MEMN_GLBAC3 access control policy for block B
0x3
GLBAC4
select MBC_MEMN_GLBAC4 access control policy for block B
0x4
GLBAC5
select MBC_MEMN_GLBAC5 access control policy for block B
0x5
GLBAC6
select MBC_MEMN_GLBAC6 access control policy for block B
0x6
GLBAC7
select MBC_MEMN_GLBAC7 access control policy for block B
0x7
NSE7
NonSecure Enable for block B
31
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
MBC0_DOM0_MEM0_BLK_CFG_W1
MBC Memory Block Configuration Word
0x44
32
read-write
0
0xFFFFFFFF
MBACSEL0
Memory Block Access Control Select for block B
0
3
read-write
GLBAC0
select MBC_MEMN_GLBAC0 access control policy for block B
0
GLBAC1
select MBC_MEMN_GLBAC1 access control policy for block B
0x1
GLBAC2
select MBC_MEMN_GLBAC2 access control policy for block B
0x2
GLBAC3
select MBC_MEMN_GLBAC3 access control policy for block B
0x3
GLBAC4
select MBC_MEMN_GLBAC4 access control policy for block B
0x4
GLBAC5
select MBC_MEMN_GLBAC5 access control policy for block B
0x5
GLBAC6
select MBC_MEMN_GLBAC6 access control policy for block B
0x6
GLBAC7
select MBC_MEMN_GLBAC7 access control policy for block B
0x7
NSE0
NonSecure Enable for block B
3
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
MBACSEL1
Memory Block Access Control Select for block B
4
3
read-write
GLBAC0
select MBC_MEMN_GLBAC0 access control policy for block B
0
GLBAC1
select MBC_MEMN_GLBAC1 access control policy for block B
0x1
GLBAC2
select MBC_MEMN_GLBAC2 access control policy for block B
0x2
GLBAC3
select MBC_MEMN_GLBAC3 access control policy for block B
0x3
GLBAC4
select MBC_MEMN_GLBAC4 access control policy for block B
0x4
GLBAC5
select MBC_MEMN_GLBAC5 access control policy for block B
0x5
GLBAC6
select MBC_MEMN_GLBAC6 access control policy for block B
0x6
GLBAC7
select MBC_MEMN_GLBAC7 access control policy for block B
0x7
NSE1
NonSecure Enable for block B
7
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
MBACSEL2
Memory Block Access Control Select for block B
8
3
read-write
GLBAC0
select MBC_MEMN_GLBAC0 access control policy for block B
0
GLBAC1
select MBC_MEMN_GLBAC1 access control policy for block B
0x1
GLBAC2
select MBC_MEMN_GLBAC2 access control policy for block B
0x2
GLBAC3
select MBC_MEMN_GLBAC3 access control policy for block B
0x3
GLBAC4
select MBC_MEMN_GLBAC4 access control policy for block B
0x4
GLBAC5
select MBC_MEMN_GLBAC5 access control policy for block B
0x5
GLBAC6
select MBC_MEMN_GLBAC6 access control policy for block B
0x6
GLBAC7
select MBC_MEMN_GLBAC7 access control policy for block B
0x7
NSE2
NonSecure Enable for block B
11
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
MBACSEL3
Memory Block Access Control Select for block B
12
3
read-write
GLBAC0
select MBC_MEMN_GLBAC0 access control policy for block B
0
GLBAC1
select MBC_MEMN_GLBAC1 access control policy for block B
0x1
GLBAC2
select MBC_MEMN_GLBAC2 access control policy for block B
0x2
GLBAC3
select MBC_MEMN_GLBAC3 access control policy for block B
0x3
GLBAC4
select MBC_MEMN_GLBAC4 access control policy for block B
0x4
GLBAC5
select MBC_MEMN_GLBAC5 access control policy for block B
0x5
GLBAC6
select MBC_MEMN_GLBAC6 access control policy for block B
0x6
GLBAC7
select MBC_MEMN_GLBAC7 access control policy for block B
0x7
NSE3
NonSecure Enable for block B
15
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
MBACSEL4
Memory Block Access Control Select for block B
16
3
read-write
GLBAC0
select MBC_MEMN_GLBAC0 access control policy for block B
0
GLBAC1
select MBC_MEMN_GLBAC1 access control policy for block B
0x1
GLBAC2
select MBC_MEMN_GLBAC2 access control policy for block B
0x2
GLBAC3
select MBC_MEMN_GLBAC3 access control policy for block B
0x3
GLBAC4
select MBC_MEMN_GLBAC4 access control policy for block B
0x4
GLBAC5
select MBC_MEMN_GLBAC5 access control policy for block B
0x5
GLBAC6
select MBC_MEMN_GLBAC6 access control policy for block B
0x6
GLBAC7
select MBC_MEMN_GLBAC7 access control policy for block B
0x7
NSE4
NonSecure Enable for block B
19
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
MBACSEL5
Memory Block Access Control Select for block B
20
3
read-write
GLBAC0
select MBC_MEMN_GLBAC0 access control policy for block B
0
GLBAC1
select MBC_MEMN_GLBAC1 access control policy for block B
0x1
GLBAC2
select MBC_MEMN_GLBAC2 access control policy for block B
0x2
GLBAC3
select MBC_MEMN_GLBAC3 access control policy for block B
0x3
GLBAC4
select MBC_MEMN_GLBAC4 access control policy for block B
0x4
GLBAC5
select MBC_MEMN_GLBAC5 access control policy for block B
0x5
GLBAC6
select MBC_MEMN_GLBAC6 access control policy for block B
0x6
GLBAC7
select MBC_MEMN_GLBAC7 access control policy for block B
0x7
NSE5
NonSecure Enable for block B
23
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
MBACSEL6
Memory Block Access Control Select for block B
24
3
read-write
GLBAC0
select MBC_MEMN_GLBAC0 access control policy for block B
0
GLBAC1
select MBC_MEMN_GLBAC1 access control policy for block B
0x1
GLBAC2
select MBC_MEMN_GLBAC2 access control policy for block B
0x2
GLBAC3
select MBC_MEMN_GLBAC3 access control policy for block B
0x3
GLBAC4
select MBC_MEMN_GLBAC4 access control policy for block B
0x4
GLBAC5
select MBC_MEMN_GLBAC5 access control policy for block B
0x5
GLBAC6
select MBC_MEMN_GLBAC6 access control policy for block B
0x6
GLBAC7
select MBC_MEMN_GLBAC7 access control policy for block B
0x7
NSE6
NonSecure Enable for block B
27
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
MBACSEL7
Memory Block Access Control Select for block B
28
3
read-write
GLBAC0
select MBC_MEMN_GLBAC0 access control policy for block B
0
GLBAC1
select MBC_MEMN_GLBAC1 access control policy for block B
0x1
GLBAC2
select MBC_MEMN_GLBAC2 access control policy for block B
0x2
GLBAC3
select MBC_MEMN_GLBAC3 access control policy for block B
0x3
GLBAC4
select MBC_MEMN_GLBAC4 access control policy for block B
0x4
GLBAC5
select MBC_MEMN_GLBAC5 access control policy for block B
0x5
GLBAC6
select MBC_MEMN_GLBAC6 access control policy for block B
0x6
GLBAC7
select MBC_MEMN_GLBAC7 access control policy for block B
0x7
NSE7
NonSecure Enable for block B
31
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
MBC0_DOM0_MEM0_BLK_NSE_W0
MBC Memory Block NonSecure Enable Word
0x140
32
read-write
0
0xFFFFFFFF
BIT0
Bit b NonSecure Enable [b = 0 - 31]
0
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT1
Bit b NonSecure Enable [b = 0 - 31]
1
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT2
Bit b NonSecure Enable [b = 0 - 31]
2
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT3
Bit b NonSecure Enable [b = 0 - 31]
3
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT4
Bit b NonSecure Enable [b = 0 - 31]
4
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT5
Bit b NonSecure Enable [b = 0 - 31]
5
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT6
Bit b NonSecure Enable [b = 0 - 31]
6
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT7
Bit b NonSecure Enable [b = 0 - 31]
7
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT8
Bit b NonSecure Enable [b = 0 - 31]
8
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT9
Bit b NonSecure Enable [b = 0 - 31]
9
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT10
Bit b NonSecure Enable [b = 0 - 31]
10
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT11
Bit b NonSecure Enable [b = 0 - 31]
11
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT12
Bit b NonSecure Enable [b = 0 - 31]
12
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT13
Bit b NonSecure Enable [b = 0 - 31]
13
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT14
Bit b NonSecure Enable [b = 0 - 31]
14
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT15
Bit b NonSecure Enable [b = 0 - 31]
15
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT16
Bit b NonSecure Enable [b = 0 - 31]
16
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT17
Bit b NonSecure Enable [b = 0 - 31]
17
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT18
Bit b NonSecure Enable [b = 0 - 31]
18
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT19
Bit b NonSecure Enable [b = 0 - 31]
19
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT20
Bit b NonSecure Enable [b = 0 - 31]
20
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT21
Bit b NonSecure Enable [b = 0 - 31]
21
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT22
Bit b NonSecure Enable [b = 0 - 31]
22
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT23
Bit b NonSecure Enable [b = 0 - 31]
23
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT24
Bit b NonSecure Enable [b = 0 - 31]
24
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT25
Bit b NonSecure Enable [b = 0 - 31]
25
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT26
Bit b NonSecure Enable [b = 0 - 31]
26
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT27
Bit b NonSecure Enable [b = 0 - 31]
27
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT28
Bit b NonSecure Enable [b = 0 - 31]
28
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT29
Bit b NonSecure Enable [b = 0 - 31]
29
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT30
Bit b NonSecure Enable [b = 0 - 31]
30
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT31
Bit b NonSecure Enable [b = 0 - 31]
31
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
MBC0_DOM0_MEM1_BLK_CFG_W0
MBC Memory Block Configuration Word
0x180
32
read-write
0
0xFFFFFFFF
MBACSEL0
Memory Block Access Control Select for block B
0
3
read-write
GLBAC0
select MBC_MEMN_GLBAC0 access control policy for block B
0
GLBAC1
select MBC_MEMN_GLBAC1 access control policy for block B
0x1
GLBAC2
select MBC_MEMN_GLBAC2 access control policy for block B
0x2
GLBAC3
select MBC_MEMN_GLBAC3 access control policy for block B
0x3
GLBAC4
select MBC_MEMN_GLBAC4 access control policy for block B
0x4
GLBAC5
select MBC_MEMN_GLBAC5 access control policy for block B
0x5
GLBAC6
select MBC_MEMN_GLBAC6 access control policy for block B
0x6
GLBAC7
select MBC_MEMN_GLBAC7 access control policy for block B
0x7
NSE0
NonSecure Enable for block B
3
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
MBACSEL1
Memory Block Access Control Select for block B
4
3
read-write
GLBAC0
select MBC_MEMN_GLBAC0 access control policy for block B
0
GLBAC1
select MBC_MEMN_GLBAC1 access control policy for block B
0x1
GLBAC2
select MBC_MEMN_GLBAC2 access control policy for block B
0x2
GLBAC3
select MBC_MEMN_GLBAC3 access control policy for block B
0x3
GLBAC4
select MBC_MEMN_GLBAC4 access control policy for block B
0x4
GLBAC5
select MBC_MEMN_GLBAC5 access control policy for block B
0x5
GLBAC6
select MBC_MEMN_GLBAC6 access control policy for block B
0x6
GLBAC7
select MBC_MEMN_GLBAC7 access control policy for block B
0x7
NSE1
NonSecure Enable for block B
7
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
MBACSEL2
Memory Block Access Control Select for block B
8
3
read-write
GLBAC0
select MBC_MEMN_GLBAC0 access control policy for block B
0
GLBAC1
select MBC_MEMN_GLBAC1 access control policy for block B
0x1
GLBAC2
select MBC_MEMN_GLBAC2 access control policy for block B
0x2
GLBAC3
select MBC_MEMN_GLBAC3 access control policy for block B
0x3
GLBAC4
select MBC_MEMN_GLBAC4 access control policy for block B
0x4
GLBAC5
select MBC_MEMN_GLBAC5 access control policy for block B
0x5
GLBAC6
select MBC_MEMN_GLBAC6 access control policy for block B
0x6
GLBAC7
select MBC_MEMN_GLBAC7 access control policy for block B
0x7
NSE2
NonSecure Enable for block B
11
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
MBACSEL3
Memory Block Access Control Select for block B
12
3
read-write
GLBAC0
select MBC_MEMN_GLBAC0 access control policy for block B
0
GLBAC1
select MBC_MEMN_GLBAC1 access control policy for block B
0x1
GLBAC2
select MBC_MEMN_GLBAC2 access control policy for block B
0x2
GLBAC3
select MBC_MEMN_GLBAC3 access control policy for block B
0x3
GLBAC4
select MBC_MEMN_GLBAC4 access control policy for block B
0x4
GLBAC5
select MBC_MEMN_GLBAC5 access control policy for block B
0x5
GLBAC6
select MBC_MEMN_GLBAC6 access control policy for block B
0x6
GLBAC7
select MBC_MEMN_GLBAC7 access control policy for block B
0x7
NSE3
NonSecure Enable for block B
15
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
MBACSEL4
Memory Block Access Control Select for block B
16
3
read-write
GLBAC0
select MBC_MEMN_GLBAC0 access control policy for block B
0
GLBAC1
select MBC_MEMN_GLBAC1 access control policy for block B
0x1
GLBAC2
select MBC_MEMN_GLBAC2 access control policy for block B
0x2
GLBAC3
select MBC_MEMN_GLBAC3 access control policy for block B
0x3
GLBAC4
select MBC_MEMN_GLBAC4 access control policy for block B
0x4
GLBAC5
select MBC_MEMN_GLBAC5 access control policy for block B
0x5
GLBAC6
select MBC_MEMN_GLBAC6 access control policy for block B
0x6
GLBAC7
select MBC_MEMN_GLBAC7 access control policy for block B
0x7
NSE4
NonSecure Enable for block B
19
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
MBACSEL5
Memory Block Access Control Select for block B
20
3
read-write
GLBAC0
select MBC_MEMN_GLBAC0 access control policy for block B
0
GLBAC1
select MBC_MEMN_GLBAC1 access control policy for block B
0x1
GLBAC2
select MBC_MEMN_GLBAC2 access control policy for block B
0x2
GLBAC3
select MBC_MEMN_GLBAC3 access control policy for block B
0x3
GLBAC4
select MBC_MEMN_GLBAC4 access control policy for block B
0x4
GLBAC5
select MBC_MEMN_GLBAC5 access control policy for block B
0x5
GLBAC6
select MBC_MEMN_GLBAC6 access control policy for block B
0x6
GLBAC7
select MBC_MEMN_GLBAC7 access control policy for block B
0x7
NSE5
NonSecure Enable for block B
23
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
MBACSEL6
Memory Block Access Control Select for block B
24
3
read-write
GLBAC0
select MBC_MEMN_GLBAC0 access control policy for block B
0
GLBAC1
select MBC_MEMN_GLBAC1 access control policy for block B
0x1
GLBAC2
select MBC_MEMN_GLBAC2 access control policy for block B
0x2
GLBAC3
select MBC_MEMN_GLBAC3 access control policy for block B
0x3
GLBAC4
select MBC_MEMN_GLBAC4 access control policy for block B
0x4
GLBAC5
select MBC_MEMN_GLBAC5 access control policy for block B
0x5
GLBAC6
select MBC_MEMN_GLBAC6 access control policy for block B
0x6
GLBAC7
select MBC_MEMN_GLBAC7 access control policy for block B
0x7
NSE6
NonSecure Enable for block B
27
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
MBACSEL7
Memory Block Access Control Select for block B
28
3
read-write
GLBAC0
select MBC_MEMN_GLBAC0 access control policy for block B
0
GLBAC1
select MBC_MEMN_GLBAC1 access control policy for block B
0x1
GLBAC2
select MBC_MEMN_GLBAC2 access control policy for block B
0x2
GLBAC3
select MBC_MEMN_GLBAC3 access control policy for block B
0x3
GLBAC4
select MBC_MEMN_GLBAC4 access control policy for block B
0x4
GLBAC5
select MBC_MEMN_GLBAC5 access control policy for block B
0x5
GLBAC6
select MBC_MEMN_GLBAC6 access control policy for block B
0x6
GLBAC7
select MBC_MEMN_GLBAC7 access control policy for block B
0x7
NSE7
NonSecure Enable for block B
31
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
MBC0_DOM0_MEM1_BLK_NSE_W0
MBC Memory Block NonSecure Enable Word
0x1A0
32
read-write
0
0xFFFFFFFF
BIT0
Bit b NonSecure Enable [b = 0 - 31]
0
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT1
Bit b NonSecure Enable [b = 0 - 31]
1
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT2
Bit b NonSecure Enable [b = 0 - 31]
2
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT3
Bit b NonSecure Enable [b = 0 - 31]
3
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT4
Bit b NonSecure Enable [b = 0 - 31]
4
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT5
Bit b NonSecure Enable [b = 0 - 31]
5
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT6
Bit b NonSecure Enable [b = 0 - 31]
6
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT7
Bit b NonSecure Enable [b = 0 - 31]
7
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT8
Bit b NonSecure Enable [b = 0 - 31]
8
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT9
Bit b NonSecure Enable [b = 0 - 31]
9
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT10
Bit b NonSecure Enable [b = 0 - 31]
10
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT11
Bit b NonSecure Enable [b = 0 - 31]
11
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT12
Bit b NonSecure Enable [b = 0 - 31]
12
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT13
Bit b NonSecure Enable [b = 0 - 31]
13
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT14
Bit b NonSecure Enable [b = 0 - 31]
14
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT15
Bit b NonSecure Enable [b = 0 - 31]
15
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT16
Bit b NonSecure Enable [b = 0 - 31]
16
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT17
Bit b NonSecure Enable [b = 0 - 31]
17
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT18
Bit b NonSecure Enable [b = 0 - 31]
18
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT19
Bit b NonSecure Enable [b = 0 - 31]
19
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT20
Bit b NonSecure Enable [b = 0 - 31]
20
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT21
Bit b NonSecure Enable [b = 0 - 31]
21
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT22
Bit b NonSecure Enable [b = 0 - 31]
22
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT23
Bit b NonSecure Enable [b = 0 - 31]
23
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT24
Bit b NonSecure Enable [b = 0 - 31]
24
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT25
Bit b NonSecure Enable [b = 0 - 31]
25
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT26
Bit b NonSecure Enable [b = 0 - 31]
26
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT27
Bit b NonSecure Enable [b = 0 - 31]
27
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT28
Bit b NonSecure Enable [b = 0 - 31]
28
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT29
Bit b NonSecure Enable [b = 0 - 31]
29
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT30
Bit b NonSecure Enable [b = 0 - 31]
30
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT31
Bit b NonSecure Enable [b = 0 - 31]
31
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
MBC0_DOM0_MEM2_BLK_CFG_W0
MBC Memory Block Configuration Word
0x1A8
32
read-write
0
0xFFFFFFFF
MBACSEL0
Memory Block Access Control Select for block B
0
3
read-write
GLBAC0
select MBC_MEMN_GLBAC0 access control policy for block B
0
GLBAC1
select MBC_MEMN_GLBAC1 access control policy for block B
0x1
GLBAC2
select MBC_MEMN_GLBAC2 access control policy for block B
0x2
GLBAC3
select MBC_MEMN_GLBAC3 access control policy for block B
0x3
GLBAC4
select MBC_MEMN_GLBAC4 access control policy for block B
0x4
GLBAC5
select MBC_MEMN_GLBAC5 access control policy for block B
0x5
GLBAC6
select MBC_MEMN_GLBAC6 access control policy for block B
0x6
GLBAC7
select MBC_MEMN_GLBAC7 access control policy for block B
0x7
NSE0
NonSecure Enable for block B
3
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
MBACSEL1
Memory Block Access Control Select for block B
4
3
read-write
GLBAC0
select MBC_MEMN_GLBAC0 access control policy for block B
0
GLBAC1
select MBC_MEMN_GLBAC1 access control policy for block B
0x1
GLBAC2
select MBC_MEMN_GLBAC2 access control policy for block B
0x2
GLBAC3
select MBC_MEMN_GLBAC3 access control policy for block B
0x3
GLBAC4
select MBC_MEMN_GLBAC4 access control policy for block B
0x4
GLBAC5
select MBC_MEMN_GLBAC5 access control policy for block B
0x5
GLBAC6
select MBC_MEMN_GLBAC6 access control policy for block B
0x6
GLBAC7
select MBC_MEMN_GLBAC7 access control policy for block B
0x7
NSE1
NonSecure Enable for block B
7
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
MBACSEL2
Memory Block Access Control Select for block B
8
3
read-write
GLBAC0
select MBC_MEMN_GLBAC0 access control policy for block B
0
GLBAC1
select MBC_MEMN_GLBAC1 access control policy for block B
0x1
GLBAC2
select MBC_MEMN_GLBAC2 access control policy for block B
0x2
GLBAC3
select MBC_MEMN_GLBAC3 access control policy for block B
0x3
GLBAC4
select MBC_MEMN_GLBAC4 access control policy for block B
0x4
GLBAC5
select MBC_MEMN_GLBAC5 access control policy for block B
0x5
GLBAC6
select MBC_MEMN_GLBAC6 access control policy for block B
0x6
GLBAC7
select MBC_MEMN_GLBAC7 access control policy for block B
0x7
NSE2
NonSecure Enable for block B
11
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
MBACSEL3
Memory Block Access Control Select for block B
12
3
read-write
GLBAC0
select MBC_MEMN_GLBAC0 access control policy for block B
0
GLBAC1
select MBC_MEMN_GLBAC1 access control policy for block B
0x1
GLBAC2
select MBC_MEMN_GLBAC2 access control policy for block B
0x2
GLBAC3
select MBC_MEMN_GLBAC3 access control policy for block B
0x3
GLBAC4
select MBC_MEMN_GLBAC4 access control policy for block B
0x4
GLBAC5
select MBC_MEMN_GLBAC5 access control policy for block B
0x5
GLBAC6
select MBC_MEMN_GLBAC6 access control policy for block B
0x6
GLBAC7
select MBC_MEMN_GLBAC7 access control policy for block B
0x7
NSE3
NonSecure Enable for block B
15
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
MBACSEL4
Memory Block Access Control Select for block B
16
3
read-write
GLBAC0
select MBC_MEMN_GLBAC0 access control policy for block B
0
GLBAC1
select MBC_MEMN_GLBAC1 access control policy for block B
0x1
GLBAC2
select MBC_MEMN_GLBAC2 access control policy for block B
0x2
GLBAC3
select MBC_MEMN_GLBAC3 access control policy for block B
0x3
GLBAC4
select MBC_MEMN_GLBAC4 access control policy for block B
0x4
GLBAC5
select MBC_MEMN_GLBAC5 access control policy for block B
0x5
GLBAC6
select MBC_MEMN_GLBAC6 access control policy for block B
0x6
GLBAC7
select MBC_MEMN_GLBAC7 access control policy for block B
0x7
NSE4
NonSecure Enable for block B
19
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
MBACSEL5
Memory Block Access Control Select for block B
20
3
read-write
GLBAC0
select MBC_MEMN_GLBAC0 access control policy for block B
0
GLBAC1
select MBC_MEMN_GLBAC1 access control policy for block B
0x1
GLBAC2
select MBC_MEMN_GLBAC2 access control policy for block B
0x2
GLBAC3
select MBC_MEMN_GLBAC3 access control policy for block B
0x3
GLBAC4
select MBC_MEMN_GLBAC4 access control policy for block B
0x4
GLBAC5
select MBC_MEMN_GLBAC5 access control policy for block B
0x5
GLBAC6
select MBC_MEMN_GLBAC6 access control policy for block B
0x6
GLBAC7
select MBC_MEMN_GLBAC7 access control policy for block B
0x7
NSE5
NonSecure Enable for block B
23
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
MBACSEL6
Memory Block Access Control Select for block B
24
3
read-write
GLBAC0
select MBC_MEMN_GLBAC0 access control policy for block B
0
GLBAC1
select MBC_MEMN_GLBAC1 access control policy for block B
0x1
GLBAC2
select MBC_MEMN_GLBAC2 access control policy for block B
0x2
GLBAC3
select MBC_MEMN_GLBAC3 access control policy for block B
0x3
GLBAC4
select MBC_MEMN_GLBAC4 access control policy for block B
0x4
GLBAC5
select MBC_MEMN_GLBAC5 access control policy for block B
0x5
GLBAC6
select MBC_MEMN_GLBAC6 access control policy for block B
0x6
GLBAC7
select MBC_MEMN_GLBAC7 access control policy for block B
0x7
NSE6
NonSecure Enable for block B
27
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
MBACSEL7
Memory Block Access Control Select for block B
28
3
read-write
GLBAC0
select MBC_MEMN_GLBAC0 access control policy for block B
0
GLBAC1
select MBC_MEMN_GLBAC1 access control policy for block B
0x1
GLBAC2
select MBC_MEMN_GLBAC2 access control policy for block B
0x2
GLBAC3
select MBC_MEMN_GLBAC3 access control policy for block B
0x3
GLBAC4
select MBC_MEMN_GLBAC4 access control policy for block B
0x4
GLBAC5
select MBC_MEMN_GLBAC5 access control policy for block B
0x5
GLBAC6
select MBC_MEMN_GLBAC6 access control policy for block B
0x6
GLBAC7
select MBC_MEMN_GLBAC7 access control policy for block B
0x7
NSE7
NonSecure Enable for block B
31
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
MBC0_DOM0_MEM2_BLK_NSE_W0
MBC Memory Block NonSecure Enable Word
0x1C8
32
read-write
0
0xFFFFFFFF
BIT0
Bit b NonSecure Enable [b = 0 - 31]
0
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT1
Bit b NonSecure Enable [b = 0 - 31]
1
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT2
Bit b NonSecure Enable [b = 0 - 31]
2
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT3
Bit b NonSecure Enable [b = 0 - 31]
3
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT4
Bit b NonSecure Enable [b = 0 - 31]
4
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT5
Bit b NonSecure Enable [b = 0 - 31]
5
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT6
Bit b NonSecure Enable [b = 0 - 31]
6
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT7
Bit b NonSecure Enable [b = 0 - 31]
7
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT8
Bit b NonSecure Enable [b = 0 - 31]
8
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT9
Bit b NonSecure Enable [b = 0 - 31]
9
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT10
Bit b NonSecure Enable [b = 0 - 31]
10
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT11
Bit b NonSecure Enable [b = 0 - 31]
11
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT12
Bit b NonSecure Enable [b = 0 - 31]
12
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT13
Bit b NonSecure Enable [b = 0 - 31]
13
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT14
Bit b NonSecure Enable [b = 0 - 31]
14
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT15
Bit b NonSecure Enable [b = 0 - 31]
15
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT16
Bit b NonSecure Enable [b = 0 - 31]
16
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT17
Bit b NonSecure Enable [b = 0 - 31]
17
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT18
Bit b NonSecure Enable [b = 0 - 31]
18
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT19
Bit b NonSecure Enable [b = 0 - 31]
19
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT20
Bit b NonSecure Enable [b = 0 - 31]
20
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT21
Bit b NonSecure Enable [b = 0 - 31]
21
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT22
Bit b NonSecure Enable [b = 0 - 31]
22
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT23
Bit b NonSecure Enable [b = 0 - 31]
23
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT24
Bit b NonSecure Enable [b = 0 - 31]
24
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT25
Bit b NonSecure Enable [b = 0 - 31]
25
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT26
Bit b NonSecure Enable [b = 0 - 31]
26
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT27
Bit b NonSecure Enable [b = 0 - 31]
27
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT28
Bit b NonSecure Enable [b = 0 - 31]
28
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT29
Bit b NonSecure Enable [b = 0 - 31]
29
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT30
Bit b NonSecure Enable [b = 0 - 31]
30
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
BIT31
Bit b NonSecure Enable [b = 0 - 31]
31
1
read-write
ALLOWED
Secure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
0
NOTALLOWED
Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
0x1
SCG0
SCG
SCG
0x4008F000
0
0x404
registers
SCG0
15
VERID
Version ID Register
0
32
read-only
0
0xFFFFFFFF
VERSION
SCG Version Number
0
32
read-only
PARAM
Parameter Register
0x4
32
read-only
0x1E
0xFFFFFFFF
SOSCCLKPRES
SOSC Clock Present
1
1
read-only
NOPRES
SOSC clock source is not present
0
PRES
SOSC clock source is present
0x1
SIRCCLKPRES
SIRC Clock Present
2
1
read-only
NOPRES
SIRC clock source is not present
0
PRES
SIRC clock source is present
0x1
FIRCCLKPRES
FIRC Clock Present
3
1
read-only
NOPRES
FIRC clock source is not present
0
PRES
FIRC clock source is present
0x1
ROSCCLKPRES
ROSC Clock Present
4
1
read-only
NOPRES
ROSC clock source is not present
0
PRES
ROSC clock source is present
0x1
TRIM_LOCK
Trim Lock register
0x8
32
read-write
0
0xFFFFFFFF
TRIM_UNLOCK
TRIM_UNLOCK
0
1
read-write
LOCKED
SCG Trim Registers locked and not writable.
0
NOT_LOCKED
SCG Trim registers unlocked and writable.
0x1
IFR_DISABLE
IFR_DISABLE
1
1
read-write
ENABLED
IFR write access to SCG trim registers not disabled. The SCG Trim registers are reprogrammed with the IFR values after any system reset.
0
DISABLED
IFR write access to SCG trim registers during system reset is blocked.
0x1
TRIM_LOCK_KEY
TRIM_LOCK_KEY
16
16
read-write
CSR
Clock Status Register
0x10
32
read-only
0x3000000
0xFFFFFFFF
SCS
System Clock Source
24
3
read-only
SOSC
SOSC
0x1
SIRC
SIRC
0x2
FIRC
FIRC
0x3
ROSC
ROSC
0x4
RCCR
Run Clock Control Register
0x14
32
read-write
0x3000000
0xFFFFFFFF
SCS
System Clock Source
24
3
read-write
SOSC
SOSC
0x1
SIRC
SIRC
0x2
FIRC
FIRC
0x3
ROSC
ROSC
0x4
SOSCCSR
SOSC Control Status Register
0x100
32
read-write
0
0xFFFFFFFF
SOSCEN
SOSC Enable
0
1
read-write
DISABLED
SOSC is disabled
0
ENABLED
SOSC is enabled
0x1
SOSCSTEN
SOSC Stop Enable
1
1
read-write
DISABLED
SOSC is disabled in Deep Sleep mode
0
ENABLED
SOSC is enabled in Deep Sleep mode only if SOSCEN is set
0x1
SOSCCM
SOSC Clock Monitor Enable
16
1
read-write
DISABLED
SOSC Clock Monitor is disabled
0
ENABLED
SOSC Clock Monitor is enabled
0x1
SOSCCMRE
SOSC Clock Monitor Reset Enable
17
1
read-write
GENERATE_INTERRUPT
Clock monitor generates an interrupt when an error is detected
0
GENERATE_RESET
Clock monitor generates a reset when an error is detected
0x1
LK
Lock Register
23
1
read-write
WRITE_ENABLED
This Control Status Register can be written
0
WRITE_DISABLED
This Control Status Register cannot be written
0x1
SOSCVLD
SOSC Valid
24
1
read-only
DISABLED
SOSC is not enabled or clock is not valid
0
ENABLED
SOSC is enabled and output clock is valid
0x1
SOSCSEL
SOSC Selected
25
1
read-only
NOT_SOSC
SOSC is not the system clock source
0
SOSC
SOSC is the system clock source
0x1
SOSCERR
SOSC Clock Error
26
1
read-write
oneToClear
DISABLED_OR_NO_ERROR
SOSC Clock Monitor is disabled or has not detected an error
0
ENABLED_AND_ERROR
SOSC Clock Monitor is enabled and detected an error
0x1
SOSCVLD_IE
SOSC Valid Interrupt Enable
30
1
read-write
NOT_SOSC
SOSCVLD interrupt is not enabled
0
SOSC
SOSCVLD interrupt is enabled
0x1
SOSCCFG
SOSC Configuration Register
0x108
32
read-write
0
0xFFFFFFFF
EREFS
External Reference Select
2
1
read-write
EXTERNAL
External reference clock selected.
0
INTERNAL
Internal crystal oscillator of OSC selected.
0x1
RANGE
SOSC Range Select
4
2
read-write
FREQ_16TO20MHz
Frequency range select of 8-16 MHz.
0
LOW_FREQ
Frequency range select of 16-25 MHz.
0x1
MEDIUM_FREQ
Frequency range select of 25-40 MHz.
0x2
HIGH_FREQ
Frequency range select of 40-50 MHz.
0x3
SIRCCSR
SIRC Control Status Register
0x200
32
read-write
0x1000020
0xFFFFFFFF
SIRCSTEN
SIRC Stop Enable
1
1
read-write
DISABLED
SIRC is disabled in Deep Sleep mode
0
ENABLED
SIRC is enabled in Deep Sleep mode
0x1
SIRC_CLK_PERIPH_EN
SIRC Clock to Peripherals Enable
5
1
read-write
DISABLED
SIRC clock to peripherals is disabled
0
ENABLED
SIRC clock to peripherals is enabled
0x1
SIRCTREN
SIRC 12 MHz Trim Enable (SIRCCFG[RANGE]=1)
8
1
read-write
DISABLED
Disables trimming SIRC to an external clock source
0
ENABLED
Enables trimming SIRC to an external clock source
0x1
SIRCTRUP
SIRC Trim Update
9
1
read-write
DISABLED
Disables SIRC trimming updates
0
ENABLED
Enables SIRC trimming updates
0x1
TRIM_LOCK
SIRC TRIM LOCK
10
1
read-only
SIRC_NOT_LOCKED
SIRC auto trim not locked to target frequency range
0
SIRC_LOCKED
SIRC auto trim locked to target frequency range
0x1
COARSE_TRIM_BYPASS
Coarse Auto Trim Bypass
11
1
read-write
NOT_BYPASSED
SIRC Coarse Auto Trim NOT Bypassed
0
BYPASSED
SIRC Coarse Auto Trim Bypassed
0x1
LK
Lock Register
23
1
read-write
WRITE_ENABLED
Control Status Register can be written
0
WRITE_DISABLED
Control Status Register cannot be written
0x1
SIRCVLD
SIRC Valid
24
1
read-only
DISABLED_OR_NOT_VALID
SIRC is not enabled or clock is not valid
0
ENABLED_AND_VALID
SIRC is enabled and output clock is valid
0x1
SIRCSEL
SIRC Selected
25
1
read-only
NOT_SIRC
SIRC is not the system clock source
0
SIRC
SIRC is the system clock source
0x1
SIRCERR
SIRC Clock Error
26
1
read-write
oneToClear
ERROR_NOT_DETECTED
Error not detected with the SIRC trimming
0
ERROR_DETECTED
Error detected with the SIRC trimming
0x1
SIRCERR_IE
SIRC Clock Error Interrupt Enable
27
1
read-write
ERROR_NOT_DETECTED
SIRCERR interrupt is not enabled
0
ERROR_DETECTED
SIRCERR interrupt is enabled
0x1
SIRCTCFG
SIRC Trim Configuration Register
0x20C
32
read-write
0
0xFFFFFFFF
TRIMSRC
Trim Source
0
2
read-write
SOSC
SOSC. This option requires that SOSC be divided using the TRIMDIV field to get a frequency of 1 MHz.
0x2
TRIMDIV
SIRC Trim Pre-divider
16
7
read-write
SIRCSTAT
SIRC Auto-trimming Status Register
0x218
32
read-write
0
0xFFFFC0C0
CCOTRIM
CCO Trim
0
6
read-write
CLTRIM
CL Trim
8
6
read-write
FIRCCSR
FIRC Control Status Register
0x300
32
read-write
0x3000031
0x7FFFFFFF
FIRCEN
FIRC Enable
0
1
read-write
DISABLED
FIRC is disabled
0
ENABLED
FIRC is enabled
0x1
FIRCSTEN
FIRC Stop Enable
1
1
read-write
DISABLED_IN_STOP_MODES
FIRC is disabled in Deep Sleep mode
0
ENABLED_IN_STOP_MODES
FIRC is enabled in Deep Sleep mode
0x1
FIRC_SCLK_PERIPH_EN
FIRC 48 MHz Clock to peripherals Enable
4
1
read-write
DISABLED
FIRC 48 MHz to peripherals is disabled
0
ENABLED
FIRC 48 MHz to peripherals is enabled
0x1
FIRC_FCLK_PERIPH_EN
FRO_HF Clock to peripherals Enable
5
1
read-write
DISABLED
FRO_HF to peripherals is disabled
0
ENABLED
FRO_HF to peripherals is enabled
0x1
FIRCTREN
FRO_HF Trim Enable
8
1
read-write
DISABLED
Disables trimming FRO_HF by an external clock source
0
ENABLED
Enables trimming FRO_HF by an external clock source
0x1
FIRCTRUP
FIRC Trim Update
9
1
read-write
DISABLED
Disables FIRC trimming updates
0
ENABLED
Enables FIRC trimming updates
0x1
TRIM_LOCK
FIRC TRIM LOCK
10
1
read-only
FIRC_NOT_LOCKED
FIRC auto trim not locked to target frequency range
0
FIRC_LOCKED
FIRC auto trim locked to target frequency range
0x1
COARSE_TRIM_BYPASS
Coarse Auto Trim Bypass
11
1
read-write
NOT_BYPASSED
FIRC Coarse Auto Trim NOT Bypassed
0
BYPASSED
FIRC Coarse Auto Trim Bypassed
0x1
LK
Lock Register
23
1
read-write
WRITE_ENABLED
Control Status Register can be written
0
WRITE_DISABLED
Control Status Register cannot be written
0x1
FIRCVLD
FIRC Valid status
24
1
read-only
NOT_ENABLED_OR_NOT_VALID
FIRC is not enabled or clock is not valid.
0
ENABLED_AND_VALID
FIRC is enabled and output clock is valid. The clock is valid after there is an output clock from the FIRC analog.
0x1
FIRCSEL
FIRC Selected
25
1
read-only
NOT_FIRC
FIRC is not the system clock source
0
FIRC
FIRC is the system clock source
0x1
FIRCERR
FIRC Clock Error
26
1
read-write
oneToClear
ERROR_NOT_DETECTED
Error not detected with the FIRC trimming
0
ERROR_DETECTED
Error detected with the FIRC trimming
0x1
FIRCERR_IE
FIRC Clock Error Interrupt Enable
27
1
read-write
ERROR_NOT_DETECTED
FIRCERR interrupt is not enabled
0
ERROR_DETECTED
FIRCERR interrupt is enabled
0x1
FIRCACC_IE
FIRC Accurate Interrupt Enable
30
1
read-write
FIRCACCNOT
FIRCACC interrupt is not enabled
0
FIRCACCYES
FIRCACC interrupt is enabled
0x1
FIRCACC
FIRC Frequency Accurate
31
1
read-only
NOT_ENABLED_OR_NOT_VALID
FIRC is not enabled or clock is not accurate.
0
ENABLED_AND_VALID
FIRC is enabled and output clock is accurate. The clock is accurate after 4096 clock cycles of FRO_HF clock(It also takes 4096 clock cycles when FIRCCFG_FREQ_SEL[0] changes) or 1365 clock cycles of 48 MHz from the FIRC analog.
0x1
FIRCCFG
FIRC Configuration Register
0x308
32
read-write
0x3
0xFFFFFFFF
FREQ_SEL
Frequency select
1
3
read-write
FIRC_36MHz
36 MHz FIRC clock selected
0
FIRC_48MHz_192S
48 MHz FIRC clock selected, divided from 192 MHz
0x1
FIRC_48MHz_144S
48 MHz FIRC clock selected, divided from 144 MHz
0x2
FIRC_64MHz
64 MHz FIRC clock selected
0x3
FIRC_72MHz
72 MHz FIRC clock selected
0x4
FIRC_96MHz
96 MHz FIRC clock selected
0x5
FIRC_144MHz
144 MHz FIRC clock selected
0x6
FIRC_192MHz
192 MHz FIRC clock selected
0x7
FIRCTCFG
FIRC Trim Configuration Register
0x30C
32
read-write
0
0xFFFFFFFF
TRIMSRC
Trim Source
0
2
read-write
USB0
USB0 Start of Frame (1 KHz). This option does not use TRIMDIV .
0
SOSC
SOSC. This option requires that SOSC be divided using the TRIMDIV field to get a frequency of 1 MHz.
0x2
TRIMDIV
FIRC Trim Pre-divider
16
7
read-write
FIRCTRIM
FIRC Trim Register
0x310
32
read-write
0
0xC0F0C000
TRIMFINE
Trim Fine
0
8
read-write
TRIMCOAR
Trim Coarse
8
6
read-write
TRIMTEMP1
Trim Temperature1
16
2
read-write
TRIMTEMP2
Trim Temperature2
18
2
read-write
TRIMSTART
Trim Start
24
6
read-write
FIRCSTAT
FIRC Auto-trimming Status Register
0x318
32
read-write
0
0xFFFFC000
TRIMFINE
Trim Fine
0
8
read-write
TRIMCOAR
Trim Coarse
8
6
read-write
ROSCCSR
ROSC Control Status Register
0x400
32
read-write
0
0xFFFFFFFF
LK
Lock Register
23
1
read-write
WRITE_ENABLED
Control Status Register can be written
0
WRITE_DISABLED
Control Status Register cannot be written
0x1
ROSCVLD
ROSC Valid
24
1
read-only
DISABLED_OR_NOT_VALID
ROSC is not enabled or clock is not valid
0
ENABLED_AND_VALID
ROSC is enabled and output clock is valid
0x1
ROSCSEL
ROSC Selected
25
1
read-only
NOT_ROSC
ROSC is not the system clock source
0
ROSC
ROSC is the system clock source
0x1
ROSCERR
ROSC Clock Error
26
1
read-write
oneToClear
DISABLED_OR_NO_ERROR
ROSC Clock has not detected an error
0
ENABLED_AND_ERROR
ROSC Clock has detected an error
0x1
SPC0
SPC
SPC
0x40090000
0
0x600
registers
SPC0
16
VERID
Version ID
0
32
read-only
0
0xFFFFFFFF
FEATURE
Feature Specification Number
0
16
read-only
STANDARD
Standard features
0
MINOR
Minor Version Number
16
8
read-only
MAJOR
Major Version Number
24
8
read-only
SC
Status Control
0x10
32
read-write
0
0xFFFFFFFF
BUSY
SPC Busy Status Flag
0
1
read-only
BUSY_NO
Not busy
0
BUSY_YES
Busy
0x1
SPC_LP_REQ
SPC Power Mode Configuration Status Flag
1
1
read-write
oneToClear
read
ACTIVE
SPC is in Active mode; the ACTIVE_CFG register has control
0
LOW_POWER
All power domains requested low-power mode; SPC entered a low-power state; power-mode configuration based on the LP_CFG register
0x1
SPC_LP_MODE
Power Domain Low-Power Mode Request
4
4
read-only
MODE0
Sleep mode with system clock running
0
MODE1
DSLEEP with system clock off
0x1
MODE2
PDOWN with system clock off
0x2
MODE8
DPDOWN with system clock off
0x8
ISO_CLR
Isolation Clear Flags
16
1
read-write
oneToClear
SWITCH_STATE
Power Switch State
31
1
read-only
OFF
Off
0
ON
On
0x1
LPREQ_CFG
Low-Power Request Configuration
0x1C
32
read-write
0
0xFFFFFFFF
LPREQOE
Low-Power Request Output Enable
0
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
LPREQPOL
Low-Power Request Output Pin Polarity Control
1
1
read-write
HIGH
High
0
LOW
Low
0x1
LPREQOV
Low-Power Request Output Override
2
2
read-write
FORCE_NO
Not forced
0
FORCE_LOW
Forced low (ignore LPREQPOL settings)
0x2
FORCE_HIGH
Forced high (ignore LPREQPOL settings)
0x3
CFG
SPC Configuration
0x20
32
read-write
0
0xFFFFFFFF
INTG_PWSWTCH_SLEEP_EN
Integrated Power Switch Sleep Enable
0
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INTG_PWSWTCH_WKUP_EN
Integrated Power Switch Wake-up Enable
1
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INTG_PWSWTCH_SLEEP_ACTIVE_EN
Integrated Power Switch Active Enable
2
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INTG_PWSWTCH_WKUP_ACTIVE_EN
Integrated Power Switch Wake-up Enable
3
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
PD_STATUS0
SPC Power Domain Mode Status
0x30
32
read-write
0
0xFFFFFFFF
PWR_REQ_STATUS
Power Request Status Flag
0
1
read-only
REQ_NO
Did not request
0
REQ_YES
Requested
0x1
PD_LP_REQ
Power Domain Low Power Request Flag
4
1
read-write
oneToClear
REQ_NO
Did not request
0
REQ_YES
Requested
0x1
LP_MODE
Power Domain Low Power Mode Request
8
4
read-only
MODE0
SLEEP with system clock running
0
MODE1
DSLEEP with system clock off
0x1
MODE2
PDOWN with system clock off
0x2
MODE8
DPDOWN with system clock off
0x8
SRAMCTL
SRAM Control
0x40
32
read-write
0x1
0xFFFFFFFF
VSM
Voltage Select Margin
0
2
read-write
VSM1
1.0 V
0x1
VSM2
1.1 V
0x2
VSM3
SRAM configured for 1.2 V operation
0x3
REQ
SRAM Voltage Update Request
30
1
read-write
REQ_NO
Do not request
0
REQ_YES
Request
0x1
ACK
SRAM Voltage Update Request Acknowledge
31
1
read-only
ACK_NO
Not acknowledged
0
ACK_YES
Acknowledged
0x1
SRAMRETLDO_REFTRIM
SRAM Retention Reference Trim
0x54
32
read-write
0x17
0xFFFFFFFF
REFTRIM
Reference Trim. Voltage range is around 0.48V - 0.85V. Trim step is 12 mV.
0
5
read-write
SRAMRETLDO_CNTRL
SRAM Retention LDO Control
0x58
32
read-write
0xF01
0xFFFFFFFF
SRAMLDO_ON
SRAM LDO Regulator Enable
0
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
SRAM_RET_EN
SRAM Retention
8
4
read-write
ACTIVE_CFG
Active Power Mode Configuration
0x100
32
read-write
0x13100005
0xFFFFFFFF
CORELDO_VDD_DS
LDO_CORE VDD Drive Strength
0
1
read-write
LOW
Low
0
NORMAL
Normal
0x1
CORELDO_VDD_LVL
LDO_CORE VDD Regulator Voltage Level
2
2
read-write
MID
Regulate to mid voltage (1.0 V)
0x1
NORMAL
Regulate to normal voltage (1.1 V)
0x2
OVER
Regulate to overdrive voltage (1.15 V)
0x3
BGMODE
Bandgap Mode
20
2
read-write
BGMODE0
Bandgap disabled
0
BGMODE01
Bandgap enabled, buffer disabled
0x1
BGMODE10
Bandgap enabled, buffer enabled
0x2
VDD_VD_DISABLE
VDD Voltage Detect Disable
23
1
read-write
ENABLE
Enable
0
DISABLE
Disable
0x1
CORE_LVDE
Core Low-Voltage Detection Enable
24
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
SYS_LVDE
System Low-Voltage Detection Enable
25
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
SYS_HVDE
System High-Voltage Detection Enable
28
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
ACTIVE_CFG1
Active Power Mode Configuration 1
0x104
32
read-write
0x2
0xFFFFFFFF
SOC_CNTRL
Active Config Chip Control
0
32
read-write
LP_CFG
Low-Power Mode Configuration
0x108
32
read-write
0x80004
0xFFFFFFFF
CORELDO_VDD_DS
LDO_CORE VDD Drive Strength
0
1
read-write
LOW
Low
0
NORMAL
Normal
0x1
CORELDO_VDD_LVL
LDO_CORE VDD Regulator Voltage Level
2
2
read-write
MID
Mid voltage (1.0 V)
0x1
NORMAL
Normal voltage (1.1 V)
0x2
OVER
Overdrive voltage (1.15 V)
0x3
SRAMLDO_DPD_ON
SRAM_LDO Deep Power Low Power IREF Enable
19
1
read-write
DISABLED
Low Power IREF is disabled for power saving in Deep Power Down mode
0
ENABLED
Low Power IREF is enabled
0x1
BGMODE
Bandgap Mode
20
2
read-write
BGMODE0
Bandgap disabled
0
BGMODE01
Bandgap enabled, buffer disabled
0x1
BGMODE10
Bandgap enabled, buffer enabled
0x2
LP_IREFEN
Low-Power IREF Enable
23
1
read-write
DISABLE
Disable for power saving in Deep Power Down mode
0
ENABLE
Enable
0x1
CORE_LVDE
Core Low Voltage Detect Enable
24
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
SYS_LVDE
System Low Voltage Detect Enable
25
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
SYS_HVDE
System High Voltage Detect Enable
28
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
LP_CFG1
Low Power Mode Configuration 1
0x10C
32
read-write
0x2
0xFFFFFFFF
SOC_CNTRL
Low-Power Configuration Chip Control
0
32
read-write
LPWKUP_DELAY
Low Power Wake-Up Delay
0x120
32
read-write
0
0xFFFFFFFF
LPWKUP_DELAY
Low-Power Wake-Up Delay
0
16
read-write
ACTIVE_VDELAY
Active Voltage Trim Delay
0x124
32
read-write
0xC8
0xFFFFFFFF
ACTIVE_VDELAY
Active Voltage Delay
0
16
read-write
VD_STAT
Voltage Detect Status
0x130
32
read-write
0
0xFFFFFFFF
oneToClear
COREVDD_LVDF
Core Low-Voltage Detect Flag
0
1
read-write
oneToClear
read
EVENT_NO
Event not detected
0
EVENT_YES
Event detected
0x1
SYSVDD_LVDF
System Low-Voltage Detect Flag
1
1
read-write
oneToClear
read
EVENT_NO
Event not detected
0
EVENT_YES
Event detected
0x1
SYSVDD_HVDF
System HVD Flag
5
1
read-write
oneToClear
read
EVENT_NO
Event not detected
0
EVENT_YES
Event detected
0x1
VD_CORE_CFG
Core Voltage Detect Configuration
0x134
32
read-write
0x1
0xFFFFFFFF
LVDRE
Core LVD Reset Enable
0
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
LVDIE
Core LVD Interrupt Enable
1
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
LOCK
Core Voltage Detect Reset Enable Lock
16
1
read-write
ALLOW
Allow
0
DENY
Deny
0x1
VD_SYS_CFG
System Voltage Detect Configuration
0x138
32
read-write
0x101
0xFFFFFFFF
LVDRE
System LVD Reset Enable
0
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
LVDIE
System LVD Interrupt Enable
1
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
HVDRE
System HVD Reset Enable
2
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
HVDIE
System HVD Interrupt Enable
3
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
LVSEL
System Low-Voltage Level Select
8
1
read-write
NORMAL
Normal
0
SAFE
Safe
0x1
LOCK
System Voltage Detect Reset Enable Lock
16
1
read-write
ALLOW
Allow
0
DENY
Deny
0x1
EVD_CFG
External Voltage Domain Configuration
0x140
32
read-write
0
0xFFFFFFFF
EVDISO
External Voltage Domain Isolation
0
3
read-write
EVDLPISO
External Voltage Domain Low-Power Isolation
8
3
read-write
EVDSTAT
External Voltage Domain Status
16
3
read-only
CORELDO_CFG
LDO_CORE Configuration
0x300
32
read-only
0
0xFFFFFFFF
MRCC0
MRCC
MRCC
0x40091000
0
0x10000
registers
MRCC_GLB_RST0
Peripheral Reset Control 0
0
32
read-write
0
0xFFFFFFFF
INPUTMUX0
Write to INPUTMUX0
0
1
read-write
DISABLED
Peripheral is held in reset
0
ENABLED
Peripheral is released from reset
0x1
I3C0
Write to I3C0
1
1
read-write
DISABLED
Peripheral is held in reset
0
ENABLED
Peripheral is released from reset
0x1
CTIMER0
Write to CTIMER0
2
1
read-write
DISABLED
Peripheral is held in reset
0
ENABLED
Peripheral is released from reset
0x1
CTIMER1
Write to CTIMER1
3
1
read-write
DISABLED
Peripheral is held in reset
0
ENABLED
Peripheral is released from reset
0x1
CTIMER2
Write to CTIMER2
4
1
read-write
DISABLED
Peripheral is held in reset
0
ENABLED
Peripheral is released from reset
0x1
FREQME
Write to FREQME
5
1
read-write
DISABLED
Peripheral is held in reset
0
ENABLED
Peripheral is released from reset
0x1
UTICK0
Write to UTICK0
6
1
read-write
DISABLED
Peripheral is held in reset
0
ENABLED
Peripheral is released from reset
0x1
DMA
Write to DMA
8
1
read-write
DISABLED
Peripheral is held in reset
0
ENABLED
Peripheral is released from reset
0x1
AOI0
Write to AOI0
9
1
read-write
DISABLED
Peripheral is held in reset
0
ENABLED
Peripheral is released from reset
0x1
CRC
Write to CRC
10
1
read-write
DISABLED
Peripheral is held in reset
0
ENABLED
Peripheral is released from reset
0x1
EIM
Write to EIM
11
1
read-write
DISABLED
Peripheral is held in reset
0
ENABLED
Peripheral is released from reset
0x1
ERM
Write to ERM
12
1
read-write
DISABLED
Peripheral is held in reset
0
ENABLED
Peripheral is released from reset
0x1
LPI2C0
Write to LPI2C0
16
1
read-write
DISABLED
Peripheral is held in reset
0
ENABLED
Peripheral is released from reset
0x1
LPSPI0
Write to LPSPI0
17
1
read-write
DISABLED
Peripheral is held in reset
0
ENABLED
Peripheral is released from reset
0x1
LPSPI1
Write to LPSPI1
18
1
read-write
DISABLED
Peripheral is held in reset
0
ENABLED
Peripheral is released from reset
0x1
LPUART0
Write to LPUART0
19
1
read-write
DISABLED
Peripheral is held in reset
0
ENABLED
Peripheral is released from reset
0x1
LPUART1
Write to LPUART1
20
1
read-write
DISABLED
Peripheral is held in reset
0
ENABLED
Peripheral is released from reset
0x1
LPUART2
Write to LPUART2
21
1
read-write
DISABLED
Peripheral is held in reset
0
ENABLED
Peripheral is released from reset
0x1
USB0
Write to USB0
22
1
read-write
DISABLED
Peripheral is held in reset
0
ENABLED
Peripheral is released from reset
0x1
QDC0
Write to QDC0
23
1
read-write
DISABLED
Peripheral is held in reset
0
ENABLED
Peripheral is released from reset
0x1
FLEXPWM0
Write to FLEXPWM0
24
1
read-write
DISABLED
Peripheral is held in reset
0
ENABLED
Peripheral is released from reset
0x1
OSTIMER0
Write to OSTIMER0
25
1
read-write
DISABLED
Peripheral is held in reset
0
ENABLED
Peripheral is released from reset
0x1
ADC0
Write to ADC0
26
1
read-write
DISABLED
Peripheral is held in reset
0
ENABLED
Peripheral is released from reset
0x1
CMP1
Write to CMP1
28
1
read-write
DISABLED
Peripheral is held in reset
0
ENABLED
Peripheral is released from reset
0x1
PORT0
Write to PORT0
29
1
read-write
DISABLED
Peripheral is held in reset
0
ENABLED
Peripheral is released from reset
0x1
PORT1
Write to PORT1
30
1
read-write
DISABLED
Peripheral is held in reset
0
ENABLED
Peripheral is released from reset
0x1
PORT2
Write to PORT2
31
1
read-write
DISABLED
Peripheral is held in reset
0
ENABLED
Peripheral is released from reset
0x1
MRCC_GLB_RST0_SET
Peripheral Reset Control Set 0
0x4
32
write-only
0
0xFFFFFFFF
DATA
Data array value, refer to corresponding position in MRCC_GLB_RSTn.
0
32
write-only
MRCC_GLB_RST0_CLR
Peripheral Reset Control Clear 0
0x8
32
write-only
0
0xFFFFFFFF
DATA
Data array value, refer to corresponding position in MRCC_GLB_RSTn.
0
32
write-only
MRCC_GLB_RST1
Peripheral Reset Control 1
0x10
32
read-write
0
0xFFFFFFFF
PORT3
Write to PORT3
0
1
read-write
DISABLED
Peripheral is held in reset
0
ENABLED
Peripheral is released from reset
0x1
GPIO0
Write to GPIO0
5
1
read-write
DISABLED
Peripheral is held in reset
0
ENABLED
Peripheral is released from reset
0x1
GPIO1
Write to GPIO1
6
1
read-write
DISABLED
Peripheral is held in reset
0
ENABLED
Peripheral is released from reset
0x1
GPIO2
Write to GPIO2
7
1
read-write
DISABLED
Peripheral is held in reset
0
ENABLED
Peripheral is released from reset
0x1
GPIO3
Write to GPIO3
8
1
read-write
DISABLED
Peripheral is held in reset
0
ENABLED
Peripheral is released from reset
0x1
MRCC_GLB_RST1_SET
Peripheral Reset Control Set 1
0x14
32
write-only
0
0xFFFFFFFF
DATA
Data array value, refer to corresponding position in MRCC_GLB_RSTn.
0
32
write-only
MRCC_GLB_RST1_CLR
Peripheral Reset Control Clear 1
0x18
32
write-only
0
0xFFFFFFFF
DATA
Data array value, refer to corresponding position in MRCC_GLB_RSTn.
0
32
write-only
MRCC_GLB_CC0
AHB Clock Control 0
0x40
32
read-write
0
0xFFFFFFFF
INPUTMUX0
write to INPUTMUX0
0
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
I3C0
Write to I3C0
1
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
CTIMER0
Write to CTIMER0
2
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
CTIMER1
Write to CTIMER1
3
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
CTIMER2
Write to CTIMER2
4
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
FREQME
Write to FREQME
5
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
UTICK0
Write to UTICK0
6
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
WWDT0
Write to WWDT0
7
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
DMA
Write to DMA
8
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
AOI0
Write to AOI0
9
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
CRC
Write to CRC
10
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
EIM
Write to EIM
11
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
ERM
Write to ERM
12
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
LPI2C0
Write to LPI2C0
16
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
LPSPI0
Write to LPSPI0
17
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
LPSPI1
write to LPSPI1
18
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
LPUART0
Write to LPUART0
19
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
LPUART1
Write to LPUART1
20
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
LPUART2
Write to LPUART2
21
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
USB0
Write to USB0
22
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
QDC0
Write to QDC0
23
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
FLEXPWM0
Write to FLEXPWM0
24
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
OSTIMER0
Write to OSTIMER0
25
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
ADC0
Write to ADC0
26
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
CMP0
Write to CMP0
27
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
CMP1
Write to CMP1
28
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
PORT0
Write to PORT0
29
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
PORT1
Write to PORT1
30
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
PORT2
Write to PORT2
31
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
MRCC_GLB_CC0_SET
AHB Clock Control Set 0
0x44
32
write-only
0
0xFFFFFFFF
DATA
Data array value, refer to corresponding position in MRCC_GLB_CCn.
0
32
write-only
MRCC_GLB_CC0_CLR
AHB Clock Control Clear 0
0x48
32
write-only
0
0xFFFFFFFF
DATA
Data array value, refer to corresponding position in MRCC_GLB_CCn.
0
32
write-only
MRCC_GLB_CC1
AHB Clock Control 1
0x50
32
read-write
0
0xFFFFFFFF
PORT3
Write to PORT3
0
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
MTR
Write to MTR
2
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
TCU
Write to TCU
3
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
EZRAMC_RAMA
Write to EZRAMC_RAMA
4
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
GPIO0
Write to GPIO0
5
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
GPIO1
Write to GPIO1
6
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
GPIO2
Write to GPIO2
7
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
GPIO3
Write to GPIO3
8
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
ROMCP
Write to ROMCP
9
1
read-write
DISABLED
Peripheral clock is disabled
0
ENABLED
Peripheral clock is enabled
0x1
MRCC_GLB_CC1_SET
AHB Clock Control Set 1
0x54
32
write-only
0
0xFFFFFFFF
DATA
Data array value, refer to corresponding position in MRCC_GLB_CCn.
0
32
write-only
MRCC_GLB_CC1_CLR
AHB Clock Control Clear 1
0x58
32
write-only
0
0xFFFFFFFF
DATA
Data array value, refer to corresponding position in MRCC_GLB_CCn.
0
32
write-only
MRCC_GLB_ACC0
Control Automatic Clock Gating 0
0x80
32
read-write
0x80
0xFFFFFFFF
INPUTMUX0
Write to INPUTMUX0
0
1
read-write
DISABLED
Automatic clock gating is disabled
0
ENABLED
Automatic clock gating is enabled
0x1
I3C0
Write to I3C0
1
1
read-write
DISABLED
Automatic clock gating is disabled
0
ENABLED
Automatic clock gating is enabled
0x1
CTIMER0
Write to CTIMER0
2
1
read-write
DISABLED
Automatic clock gating is disabled
0
ENABLED
Automatic clock gating is enabled
0x1
CTIMER1
Write to CTIMER1
3
1
read-write
DISABLED
Automatic clock gating is disabled
0
ENABLED
Automatic clock gating is enabled
0x1
CTIMER2
Write to CTIMER2
4
1
read-write
DISABLED
Automatic clock gating is disabled
0
ENABLED
Automatic clock gating is enabled
0x1
FREQME
Write to FREQME
5
1
read-write
DISABLED
Automatic clock gating is disabled
0
ENABLED
Automatic clock gating is enabled
0x1
UTICK0
Write to UTICK0
6
1
read-write
DISABLED
Automatic clock gating is disabled
0
ENABLED
Automatic clock gating is enabled
0x1
WWDT0
Write to WWDT0
7
1
read-write
DISABLED
Automatic clock gating is disabled
0
ENABLED
Automatic clock gating is enabled
0x1
DMA
Write to DMA
8
1
read-write
DISABLED
Automatic clock gating is disabled
0
ENABLED
Automatic clock gating is enabled
0x1
AOI0
Write to AOI0
9
1
read-write
DISABLED
Automatic clock gating is disabled
0
ENABLED
Automatic clock gating is enabled
0x1
CRC
Write to CRC
10
1
read-write
DISABLED
Automatic clock gating is disabled
0
ENABLED
Automatic clock gating is enabled
0x1
EIM
Write to EIM
11
1
read-write
DISABLED
Automatic clock gating is disabled
0
ENABLED
Automatic clock gating is enabled
0x1
ERM
Write to ERM
12
1
read-write
DISABLED
Automatic clock gating is disabled
0
ENABLED
Automatic clock gating is enabled
0x1
LPI2C0
Write to LPI2C0
16
1
read-write
DISABLED
Automatic clock gating is disabled
0
ENABLED
Automatic clock gating is enabled
0x1
LPSPI0
Write to LPSPI0
17
1
read-write
DISABLED
Automatic clock gating is disabled
0
ENABLED
Automatic clock gating is enabled
0x1
LPSPI1
Write to LPSPI1
18
1
read-write
DISABLED
Automatic clock gating is disabled
0
ENABLED
Automatic clock gating is enabled
0x1
LPUART0
Write to LPUART0
19
1
read-write
DISABLED
Automatic clock gating is disabled
0
ENABLED
Automatic clock gating is enabled
0x1
LPUART1
Write to LPUART1
20
1
read-write
DISABLED
Automatic clock gating is disabled
0
ENABLED
Automatic clock gating is enabled
0x1
LPUART2
Write to LPUART2
21
1
read-write
DISABLED
Automatic clock gating is disabled
0
ENABLED
Automatic clock gating is enabled
0x1
USB0
Write to USB0
22
1
read-write
DISABLED
Automatic clock gating is disabled
0
ENABLED
Automatic clock gating is enabled
0x1
QDC0
Write to QDC0
23
1
read-write
DISABLED
Automatic clock gating is disabled
0
ENABLED
Automatic clock gating is enabled
0x1
FLEXPWM0
Write to FLEXPWM0
24
1
read-write
DISABLED
Automatic clock gating is disabled
0
ENABLED
Automatic clock gating is enabled
0x1
OSTIMER0
Write to OSTIMER0
25
1
read-write
DISABLED
Automatic clock gating is disabled
0
ENABLED
Automatic clock gating is enabled
0x1
ADC0
Write to ADC0
26
1
read-write
DISABLED
Automatic clock gating is disabled
0
ENABLED
Automatic clock gating is enabled
0x1
CMP0
Write to CMP0
27
1
read-write
DISABLED
Automatic clock gating is disabled
0
ENABLED
Automatic clock gating is enabled
0x1
CMP1
Write to CMP1
28
1
read-write
DISABLED
Automatic clock gating is disabled
0
ENABLED
Automatic clock gating is enabled
0x1
PORT0
Write to PORT0
29
1
read-write
DISABLED
Automatic clock gating is disabled
0
ENABLED
Automatic clock gating is enabled
0x1
PORT1
Write to PORT1
30
1
read-write
DISABLED
Automatic clock gating is disabled
0
ENABLED
Automatic clock gating is enabled
0x1
PORT2
Write to PORT2
31
1
read-write
DISABLED
Automatic clock gating is disabled
0
ENABLED
Automatic clock gating is enabled
0x1
MRCC_GLB_ACC1
Control Automatic Clock Gating 1
0x84
32
read-write
0x210
0xFFFFFFFF
PORT3
Write to PORT3
0
1
read-write
DISABLED
Automatic clock gating is disabled
0
ENABLED
Automatic clock gating is enabled
0x1
EZRAMC_RAMA
Write to EZRAMC_RAMA
4
1
read-write
DISABLED
Automatic clock gating is disabled
0
ENABLED
Automatic clock gating is enabled
0x1
GPIO0
Write to GPIO0
5
1
read-write
DISABLED
Automatic clock gating is disabled
0
ENABLED
Automatic clock gating is enabled
0x1
GPIO1
Write to GPIO1
6
1
read-write
DISABLED
Automatic clock gating is disabled
0
ENABLED
Automatic clock gating is enabled
0x1
GPIO2
Write to GPIO2
7
1
read-write
DISABLED
Automatic clock gating is disabled
0
ENABLED
Automatic clock gating is enabled
0x1
GPIO3
Write to GPIO3
8
1
read-write
DISABLED
Automatic clock gating is disabled
0
ENABLED
Automatic clock gating is enabled
0x1
ROMCP
Write to ROMCP
9
1
read-write
DISABLED
Automatic clock gating is disabled
0
ENABLED
Automatic clock gating is enabled
0x1
MRCC_I3C0_FCLK_CLKSEL
I3C0_FCLK clock selection control
0xA0
32
read-write
0x7
0xFFFFFFFF
MUX
Functional Clock Mux Select
0
3
read-write
clkroot_func_0
FRO_12M
0
clkroot_func_2
FRO_HF_DIV
0x2
clkroot_func_3
CLK_IN
0x3
clkroot_func_5
CLK_1M
0x5
MRCC_I3C0_FCLK_CLKDIV
I3C0_FCLK clock divider control
0xA4
32
read-write
0x40000000
0xFFFFFFFF
DIV
Functional Clock Divider
0
4
read-write
RESET
Reset divider counter
29
1
write-only
ON
Divider isn't reset
0
OFF
Divider is reset
0x1
HALT
Halt divider counter
30
1
read-write
ON
Divider clock is running
0
OFF
Divider clock is stopped
0x1
UNSTAB
Divider status flag
31
1
read-only
ON
Divider clock is stable
0
OFF
Clock frequency isn't stable
0x1
MRCC_CTIMER0_CLKSEL
CTIMER0 clock selection control
0xA8
32
read-write
0x7
0xFFFFFFFF
MUX
Functional Clock Mux Select
0
3
read-write
clkroot_func_0
FRO_12M
0
clkroot_func_1
FRO_HF_GATED
0x1
clkroot_func_3
CLK_IN
0x3
clkroot_func_4
CLK_16K
0x4
clkroot_func_5
CLK_1M
0x5
MRCC_CTIMER0_CLKDIV
CTIMER0 clock divider control
0xAC
32
read-write
0x40000000
0xFFFFFFFF
DIV
Functional Clock Divider
0
4
read-write
RESET
Reset divider counter
29
1
write-only
ON
Divider isn't reset
0
OFF
Divider is reset
0x1
HALT
Halt divider counter
30
1
read-write
ON
Divider clock is running
0
OFF
Divider clock is stopped
0x1
UNSTAB
Divider status flag
31
1
read-only
ON
Divider clock is stable
0
OFF
Clock frequency isn't stable
0x1
MRCC_CTIMER1_CLKSEL
CTIMER1 clock selection control
0xB0
32
read-write
0x7
0xFFFFFFFF
MUX
Functional Clock Mux Select
0
3
read-write
clkroot_func_0
FRO_12M
0
clkroot_func_1
FRO_HF_GATED
0x1
clkroot_func_3
CLK_IN
0x3
clkroot_func_4
CLK_16K
0x4
clkroot_func_5
CLK_1M
0x5
MRCC_CTIMER1_CLKDIV
CTIMER1 clock divider control
0xB4
32
read-write
0x40000000
0xFFFFFFFF
DIV
Functional Clock Divider
0
4
read-write
RESET
Reset divider counter
29
1
write-only
ON
Divider isn't reset
0
OFF
Divider is reset
0x1
HALT
Halt divider counter
30
1
read-write
ON
Divider clock is running
0
OFF
Divider clock is stopped
0x1
UNSTAB
Divider status flag
31
1
read-only
ON
Divider clock is stable
0
OFF
Clock frequency isn't stable
0x1
MRCC_CTIMER2_CLKSEL
CTIMER2 clock selection control
0xB8
32
read-write
0x7
0xFFFFFFFF
MUX
Functional Clock Mux Select
0
3
read-write
clkroot_func_0
FRO_12M
0
clkroot_func_1
FRO_HF_GATED
0x1
clkroot_func_3
CLK_IN
0x3
clkroot_func_4
CLK_16K
0x4
clkroot_func_5
CLK_1M
0x5
MRCC_CTIMER2_CLKDIV
CTIMER2 clock divider control
0xBC
32
read-write
0x40000000
0xFFFFFFFF
DIV
Functional Clock Divider
0
4
read-write
RESET
Reset divider counter
29
1
write-only
ON
Divider isn't reset
0
OFF
Divider is reset
0x1
HALT
Halt divider counter
30
1
read-write
ON
Divider clock is running
0
OFF
Divider clock is stopped
0x1
UNSTAB
Divider status flag
31
1
read-only
ON
Divider clock is stable
0
OFF
Clock frequency isn't stable
0x1
MRCC_WWDT0_CLKDIV
WWDT0 clock divider control
0xC4
32
read-write
0
0xFFFFFFFF
DIV
Functional Clock Divider
0
4
read-write
RESET
Reset divider counter
29
1
write-only
ON
Divider isn't reset
0
OFF
Divider is reset
0x1
HALT
Halt divider counter
30
1
read-write
ON
Divider clock is running
0
OFF
Divider clock is stopped
0x1
UNSTAB
Divider status flag
31
1
read-only
ON
Divider clock is stable
0
OFF
Clock frequency isn't stable
0x1
MRCC_LPI2C0_CLKSEL
LPI2C0 clock selection control
0xC8
32
read-write
0x7
0xFFFFFFFF
MUX
Functional Clock Mux Select
0
3
read-write
clkroot_func_0
FRO_12M
0
clkroot_func_2
FRO_HF_DIV
0x2
clkroot_func_3
CLK_IN
0x3
clkroot_func_5
CLK_1M
0x5
MRCC_LPI2C0_CLKDIV
LPI2C0 clock divider control
0xCC
32
read-write
0x40000000
0xFFFFFFFF
DIV
Functional Clock Divider
0
4
read-write
RESET
Reset divider counter
29
1
write-only
ON
Divider isn't reset
0
OFF
Divider is reset
0x1
HALT
Halt divider counter
30
1
read-write
ON
Divider clock is running
0
OFF
Divider clock is stopped
0x1
UNSTAB
Divider status flag
31
1
read-only
ON
Divider clock is stable
0
OFF
Clock frequency isn't stable
0x1
MRCC_LPSPI0_CLKSEL
LPSPI0 clock selection control
0xD0
32
read-write
0x7
0xFFFFFFFF
MUX
Functional Clock Mux Select
0
3
read-write
clkroot_func_0
FRO_12M
0
clkroot_func_2
FRO_HF_DIV
0x2
clkroot_func_3
CLK_IN
0x3
clkroot_func_5
CLK_1M
0x5
MRCC_LPSPI0_CLKDIV
LPSPI0 clock divider control
0xD4
32
read-write
0x40000000
0xFFFFFFFF
DIV
Functional Clock Divider
0
4
read-write
RESET
Reset divider counter
29
1
write-only
ON
Divider isn't reset
0
OFF
Divider is reset
0x1
HALT
Halt divider counter
30
1
read-write
ON
Divider clock is running
0
OFF
Divider clock is stopped
0x1
UNSTAB
Divider status flag
31
1
read-only
ON
Divider clock is stable
0
OFF
Clock frequency isn't stable
0x1
MRCC_LPSPI1_CLKSEL
LPSPI1 clock selection control
0xD8
32
read-write
0x7
0xFFFFFFFF
MUX
Functional Clock Mux Select
0
3
read-write
clkroot_func_0
FRO_12M
0
clkroot_func_2
FRO_HF_DIV
0x2
clkroot_func_3
CLK_IN
0x3
clkroot_func_5
CLK_1M
0x5
MRCC_LPSPI1_CLKDIV
LPSPI1 clock divider control
0xDC
32
read-write
0x40000000
0xFFFFFFFF
DIV
Functional Clock Divider
0
4
read-write
RESET
Reset divider counter
29
1
write-only
ON
Divider isn't reset
0
OFF
Divider is reset
0x1
HALT
Halt divider counter
30
1
read-write
ON
Divider clock is running
0
OFF
Divider clock is stopped
0x1
UNSTAB
Divider status flag
31
1
read-only
ON
Divider clock is stable
0
OFF
Clock frequency isn't stable
0x1
MRCC_LPUART0_CLKSEL
LPUART0 clock selection control
0xE0
32
read-write
0x7
0xFFFFFFFF
MUX
Functional Clock Mux Select
0
3
read-write
clkroot_func_0
FRO_12M
0
clkroot_func_2
FRO_HF_DIV
0x2
clkroot_func_3
CLK_IN
0x3
clkroot_func_4
CLK_16K
0x4
clkroot_func_5
CLK_1M
0x5
MRCC_LPUART0_CLKDIV
LPUART0 clock divider control
0xE4
32
read-write
0x40000000
0xFFFFFFFF
DIV
Functional Clock Divider
0
4
read-write
RESET
Reset divider counter
29
1
write-only
ON
Divider isn't reset
0
OFF
Divider is reset
0x1
HALT
Halt divider counter
30
1
read-write
ON
Divider clock is running
0
OFF
Divider clock is stopped
0x1
UNSTAB
Divider status flag
31
1
read-only
ON
Divider clock is stable
0
OFF
Clock frequency isn't stable
0x1
MRCC_LPUART1_CLKSEL
LPUART1 clock selection control
0xE8
32
read-write
0x7
0xFFFFFFFF
MUX
Functional Clock Mux Select
0
3
read-write
clkroot_func_0
FRO_12M
0
clkroot_func_2
FRO_HF_DIV
0x2
clkroot_func_3
CLK_IN
0x3
clkroot_func_4
CLK_16K
0x4
clkroot_func_5
CLK_1M
0x5
MRCC_LPUART1_CLKDIV
LPUART1 clock divider control
0xEC
32
read-write
0x40000000
0xFFFFFFFF
DIV
Functional Clock Divider
0
4
read-write
RESET
Reset divider counter
29
1
write-only
ON
Divider isn't reset
0
OFF
Divider is reset
0x1
HALT
Halt divider counter
30
1
read-write
ON
Divider clock is running
0
OFF
Divider clock is stopped
0x1
UNSTAB
Divider status flag
31
1
read-only
ON
Divider clock is stable
0
OFF
Clock frequency isn't stable
0x1
MRCC_LPUART2_CLKSEL
LPUART2 clock selection control
0xF0
32
read-write
0x7
0xFFFFFFFF
MUX
Functional Clock Mux Select
0
3
read-write
clkroot_func_0
FRO_12M
0
clkroot_func_2
FRO_HF_DIV
0x2
clkroot_func_3
CLK_IN
0x3
clkroot_func_4
CLK_16K
0x4
clkroot_func_5
CLK_1M
0x5
MRCC_LPUART2_CLKDIV
LPUART2 clock divider control
0xF4
32
read-write
0x40000000
0xFFFFFFFF
DIV
Functional Clock Divider
0
4
read-write
RESET
Reset divider counter
29
1
write-only
ON
Divider isn't reset
0
OFF
Divider is reset
0x1
HALT
Halt divider counter
30
1
read-write
ON
Divider clock is running
0
OFF
Divider clock is stopped
0x1
UNSTAB
Divider status flag
31
1
read-only
ON
Divider clock is stable
0
OFF
Clock frequency isn't stable
0x1
MRCC_USB0_CLKSEL
USB0 clock selection control
0xF8
32
read-write
0x3
0xFFFFFFFF
MUX
Functional Clock Mux Select
0
2
read-write
scg_scg_firc_48mhz_clk
scg_scg_firc_48mhz_clk
0x1
clkroot_sosc
clkroot_sosc
0x2
MRCC_LPTMR0_CLKSEL
LPTMR0 clock selection control
0x100
32
read-write
0x7
0xFFFFFFFF
MUX
Functional Clock Mux Select
0
3
read-write
clkroot_func_0
FRO_12M
0
clkroot_func_2
FRO_HF_DIV
0x2
clkroot_func_3
CLK_IN
0x3
clkroot_func_5
CLK_1M
0x5
MRCC_LPTMR0_CLKDIV
LPTMR0 clock divider control
0x104
32
read-write
0x40000000
0xFFFFFFFF
DIV
Functional Clock Divider
0
4
read-write
RESET
Reset divider counter
29
1
write-only
ON
Divider isn't reset
0
OFF
Divider is reset
0x1
HALT
Halt divider counter
30
1
read-write
ON
Divider clock is running
0
OFF
Divider clock is stopped
0x1
UNSTAB
Divider status flag
31
1
read-only
ON
Divider clock is stable
0
OFF
Clock frequency isn't stable
0x1
MRCC_OSTIMER0_CLKSEL
OSTIMER0 clock selection control
0x108
32
read-write
0x3
0xFFFFFFFF
MUX
Functional Clock Mux Select
0
2
read-write
clkroot_16k
clkroot_16k
0
clkroot_1m
clkroot_1m
0x2
MRCC_ADC0_CLKSEL
ADC0 clock selection control
0x110
32
read-write
0x7
0xFFFFFFFF
MUX
Functional Clock Mux Select
0
3
read-write
clkroot_func_0
FRO_12M
0
clkroot_func_1
FRO_HF_GATED
0x1
clkroot_func_3
CLK_IN
0x3
clkroot_func_5
CLK_1M
0x5
MRCC_ADC0_CLKDIV
ADC0 clock divider control
0x114
32
read-write
0x40000000
0xFFFFFFFF
DIV
Functional Clock Divider
0
4
read-write
RESET
Reset divider counter
29
1
write-only
ON
Divider isn't reset
0
OFF
Divider is reset
0x1
HALT
Halt divider counter
30
1
read-write
ON
Divider clock is running
0
OFF
Divider clock is stopped
0x1
UNSTAB
Divider status flag
31
1
read-only
ON
Divider clock is stable
0
OFF
Clock frequency isn't stable
0x1
MRCC_CMP0_FUNC_CLKDIV
CMP0_FUNC clock divider control
0x11C
32
read-write
0
0xFFFFFFFF
DIV
Functional Clock Divider
0
4
read-write
RESET
Reset divider counter
29
1
write-only
ON
Divider isn't reset
0
OFF
Divider is reset
0x1
HALT
Halt divider counter
30
1
read-write
ON
Divider clock is running
0
OFF
Divider clock is stopped
0x1
UNSTAB
Divider status flag
31
1
read-only
ON
Divider clock is stable
0
OFF
Clock frequency isn't stable
0x1
MRCC_CMP0_RR_CLKSEL
CMP0_RR clock selection control
0x120
32
read-write
0x7
0xFFFFFFFF
MUX
Functional Clock Mux Select
0
3
read-write
clkroot_func_0
FRO_12M
0
clkroot_func_2
FRO_HF_DIV
0x2
clkroot_func_3
CLK_IN
0x3
clkroot_func_5
CLK_1M
0x5
MRCC_CMP0_RR_CLKDIV
CMP0_RR clock divider control
0x124
32
read-write
0x40000000
0xFFFFFFFF
DIV
Functional Clock Divider
0
2
read-write
RESET
Reset divider counter
29
1
write-only
ON
Divider isn't reset
0
OFF
Divider is reset
0x1
HALT
Halt divider counter
30
1
read-write
ON
Divider clock is running
0
OFF
Divider clock is stopped
0x1
UNSTAB
Divider status flag
31
1
read-only
ON
Divider clock is stable
0
OFF
Clock frequency isn't stable
0x1
MRCC_CMP1_FUNC_CLKDIV
CMP1_FUNC clock divider control
0x12C
32
read-write
0
0xFFFFFFFF
DIV
Functional Clock Divider
0
4
read-write
RESET
Reset divider counter
29
1
write-only
ON
Divider isn't reset
0
OFF
Divider is reset
0x1
HALT
Halt divider counter
30
1
read-write
ON
Divider clock is running
0
OFF
Divider clock is stopped
0x1
UNSTAB
Divider status flag
31
1
read-only
ON
Divider clock is stable
0
OFF
Clock frequency isn't stable
0x1
MRCC_CMP1_RR_CLKSEL
CMP1_RR clock selection control
0x130
32
read-write
0x7
0xFFFFFFFF
MUX
Functional Clock Mux Select
0
3
read-write
clkroot_func_0
FRO_12M
0
clkroot_func_2
FRO_HF_DIV
0x2
clkroot_func_3
CLK_IN
0x3
clkroot_func_5
CLK_1M
0x5
MRCC_CMP1_RR_CLKDIV
CMP1_RR clock divider control
0x134
32
read-write
0x40000000
0xFFFFFFFF
DIV
Functional Clock Divider
0
2
read-write
RESET
Reset divider counter
29
1
write-only
ON
Divider isn't reset
0
OFF
Divider is reset
0x1
HALT
Halt divider counter
30
1
read-write
ON
Divider clock is running
0
OFF
Divider clock is stopped
0x1
UNSTAB
Divider status flag
31
1
read-only
ON
Divider clock is stable
0
OFF
Clock frequency isn't stable
0x1
MRCC_DBG_TRACE_CLKSEL
DBG_TRACE clock selection control
0x138
32
read-write
0
0xFFFFFFFF
MUX
Functional Clock Mux Select
0
2
read-write
clkroot_cpu
clkroot_cpu
0
clkroot_1m
clkroot_1m
0x1
clkroot_16k
clkroot_16k
0x2
MRCC_DBG_TRACE_CLKDIV
DBG_TRACE clock divider control
0x13C
32
read-write
0
0xFFFFFFFF
DIV
Functional Clock Divider
0
4
read-write
RESET
Reset divider counter
29
1
write-only
ON
Divider isn't reset
0
OFF
Divider is reset
0x1
HALT
Halt divider counter
30
1
read-write
ON
Divider clock is running
0
OFF
Divider clock is stopped
0x1
UNSTAB
Divider status flag
31
1
read-only
ON
Divider clock is stable
0
OFF
Clock frequency isn't stable
0x1
MRCC_CLKOUT_CLKSEL
CLKOUT clock selection control
0x140
32
read-write
0x7
0xFFFFFFFF
MUX
Functional Clock Mux Select
0
3
read-write
clkroot_12m
clkroot_12m
0
clkroot_firc_div
clkroot_firc_div
0x1
clkroot_sosc
clkroot_sosc
0x2
clkroot_16k
clkroot_16k
0x3
clkroot_slow
clkroot_slow
0x6
MRCC_CLKOUT_CLKDIV
CLKOUT clock divider control
0x144
32
read-write
0x40000000
0xFFFFFFFF
DIV
Functional Clock Divider
0
4
read-write
RESET
Reset divider counter
29
1
write-only
ON
Divider isn't reset
0
OFF
Divider is reset
0x1
HALT
Halt divider counter
30
1
read-write
ON
Divider clock is running
0
OFF
Divider clock is stopped
0x1
UNSTAB
Divider status flag
31
1
read-only
ON
Divider clock is stable
0
OFF
Clock frequency is not stable
0x1
MRCC_SYSTICK_CLKSEL
SYSTICK clock selection control
0x148
32
read-write
0x3
0xFFFFFFFF
MUX
Functional Clock Mux Select
0
2
read-write
clkroot_cpu
clkroot_cpu
0
clkroot_1m
clkroot_1m
0x1
clkroot_16k
clkroot_16k
0x2
MRCC_SYSTICK_CLKDIV
SYSTICK clock divider control
0x14C
32
read-write
0x40000000
0xFFFFFFFF
DIV
Functional Clock Divider
0
4
read-write
RESET
Reset divider counter
29
1
write-only
ON
Divider isn't reset
0
OFF
Divider is reset
0x1
HALT
Halt divider counter
30
1
read-write
ON
Divider clock is running
0
OFF
Divider clock is stopped
0x1
UNSTAB
Divider status flag
31
1
read-only
ON
Divider clock is stable
0
OFF
Clock frequency isn't stable
0x1
MRCC_FRO_HF_DIV_CLKDIV
FRO_HF_DIV clock divider control
0x154
32
read-write
0
0xFFFFFFFF
DIV
Functional Clock Divider
0
4
read-write
UNSTAB
Divider status flag
31
1
read-only
ON
Divider clock is stable
0
OFF
Clock frequency isn't stable
0x1
SYSCON
SYSCON
MRCC0
SYSCON
0x40091000
0
0x1000
registers
REMAP
AHB Matrix Remap Control
0x200
32
read-write
0
0xFFFFFFFF
CPU0_SBUS
RAMX0 address remap for CPU System bus
0
2
read-write
CPU0_SBUS_0
RAMX0: 0x04000000 - 0x04001fff
0
CPU0_SBUS_1
RAMX0: 0x20006000 - 0x20007fff
0x1
DMA0
RAMX0 address remap for DMA0
2
2
read-write
DMA0_0
RAMX0: 0x04000000 - 0x04001fff
0
DMA0_1
RAMX0: same alias space as CPU0_SBUS
0x1
USB0
RAMX0 address remap for USB0
4
2
read-write
USB0_0
RAMX0: 0x04000000 - 0x04001fff
0
USB0_1
RAMX0: same alias space as CPU0_SBUS
0x1
LOCK
This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until the next reset.
31
1
read-write
LOCK_0
This register is not locked and can be altered.
0
LOCK_1
This register is locked and cannot be altered.
0x1
AHBMATPRIO
AHB Matrix Priority Control
0x210
32
read-write
0
0xFFFFFFFF
CPU0_CBUS
CPU0 C-AHB bus master priority level
0
2
read-write
LEVEL0
level 0
0
LEVEL1
level 1
0x1
LEVEL2
level 2
0x2
LEVEL3
level 3
0x3
CPU0_SBUS
CPU0 S-AHB bus master priority level
2
2
read-write
LEVEL0
level 0
0
LEVEL1
level 1
0x1
LEVEL2
level 2
0x2
LEVEL3
level 3
0x3
DMA0
DMA0 controller bus master priority level
8
2
read-write
LEVEL0
level 0
0
LEVEL1
level 1
0x1
LEVEL2
level 2
0x2
LEVEL3
level 3
0x3
USB_FS_ENET
USB-FS bus master priority level
24
2
read-write
LEVEL0
level 0
0
LEVEL1
level 1
0x1
LEVEL2
level 2
0x2
LEVEL3
level 3
0x3
CPU0NSTCKCAL
Non-Secure CPU0 System Tick Calibration
0x23C
32
read-write
0
0xFFFFFFFF
TENMS
Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known.
0
24
read-write
SKEW
Indicates whether the TENMS value is exact.
24
1
read-write
EXACT
TENMS value is exact
0
INEXACT
TENMS value is not exact or not given
0x1
NOREF
Indicates whether the device provides a reference clock to the processor.
25
1
read-write
YES_REF
Reference clock is provided
0
NO_REF
No reference clock is provided
0x1
NMISRC
NMI Source Select
0x248
32
read-write
0
0xFFFFFFFF
IRQCPU0
The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for CPU0, if enabled by NMIENCPU0.
0
8
read-write
NMIENCPU0
Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU0.
31
1
read-write
DISABLE
Disable.
0
ENABLE
Enable.
0x1
SLOWCLKDIV
SLOW_CLK Clock Divider
0x378
32
read-write
0
0xFFFFFFFF
RESET
Resets the divider counter
29
1
read-write
RELEASED
Divider is not reset
0
ASSERTED
Divider is reset
0x1
HALT
Halts the divider counter
30
1
read-write
RUN
Divider clock is running
0
HALT
Divider clock is stopped
0x1
UNSTAB
Divider status flag
31
1
read-only
STABLE
Divider clock is stable
0
ONGOING
Clock frequency is not stable
0x1
AHBCLKDIV
System Clock Divider
0x380
32
read-write
0
0xFFFFFFFF
DIV
Clock divider value
0
8
read-write
UNSTAB
Divider status flag
31
1
read-only
STABLE
Divider clock is stable
0
ONGOING
Clock frequency is not stable
0x1
CLKUNLOCK
Clock Configuration Unlock
0x3FC
32
read-write
0
0xFFFFFFFF
UNLOCK
Controls clock configuration registers access (for example, MRCC_xxx_CLKDIV, MRCC_xxx_CLKSEL, MRCC_GLB_xxx)
0
1
read-write
ENABLE
Updates are allowed to all clock configuration registers
0
FREEZE
Freezes all clock configuration registers update.
0x1
NVM_CTRL
NVM Control
0x400
32
read-write
0x20400
0xFFFFFFFF
DIS_FLASH_SPEC
Flash speculation control
0
1
read-write
ENABLE
Enables flash speculation
0
DISABLE
Disables flash speculation
0x1
DIS_DATA_SPEC
Flash data speculation control
1
1
read-write
ENABLE
Enables data speculation
0
DISABLE
Disables data speculation
0x1
FLASH_STALL_EN
FLASH stall on busy control
10
1
read-write
ENABLE
No stall on FLASH busy
0
DISABLE
Stall on FLASH busy
0x1
DIS_MBECC_ERR_INST
Bus error on data multi-bit ECC error control Set this field to 0 if you want to enable flash speculative
16
1
read-write
ENABLE
Enables bus error on multi-bit ECC error for instruction
0
DISABLE
Disables bus error on multi-bit ECC error for instruction
0x1
DIS_MBECC_ERR_DATA
Bus error on data multi-bit ECC error control Set this field to 0 if you want to enable flash speculative
17
1
read-write
ENABLE
Enables bus error on multi-bit ECC error for data
0
DISABLE
Disables bus error on multi-bit ECC error for data
0x1
ROMCR
ROM Wait State
0x404
32
read-only
0
0xFFFFFFFF
CPUSTAT
CPU Status
0x80C
32
read-only
0
0xFFFFFFFF
CPU0SLEEPING
CPU0 sleeping state
0
1
read-only
AWAKE
CPU is not sleeping
0
SLEEPING
CPU is sleeping
0x1
CPU0LOCKUP
CPU0 lockup state
2
1
read-only
AWAKE
CPU is not in lockup
0
SLEEPING
CPU is in lockup
0x1
LPCAC_CTRL
LPCAC Control
0x824
32
read-write
0x31
0xFFFFFFFF
DIS_LPCAC
Disables/enables the cache function.
0
1
read-write
ENABLE
Enabled
0
DISABLE
Disabled
0x1
CLR_LPCAC
Clears the cache function.
1
1
read-write
ENABLE
Unclears the cache
0
DISABLE
Clears the cache
0x1
FRC_NO_ALLOC
Forces no allocation.
2
1
read-write
ENABLE
Forces allocation
0
DISABLE
Forces no allocation
0x1
DIS_LPCAC_WTBF
Disable LPCAC Write Through Buffer.
4
1
read-write
DISABLE
Enables write through buffer
0
ENABLE
Disables write through buffer
0x1
LIM_LPCAC_WTBF
Limit LPCAC Write Through Buffer.
5
1
read-write
DISABLE
Write buffer enabled when transaction is bufferable.
0
ENABLE
Write buffer enabled when transaction is cacheable and bufferable
0x1
LPCAC_XOM
LPCAC XOM(eXecute-Only-Memory) attribute control
7
1
read-write
DISABLE
Disabled.
0
ENABLE
Enabled.
0x1
LPCAC_MEM_REQ
Request LPCAC memories.
8
1
read-write
DISABLE
Configure shared memories RAMX1 as general memories.
0
ENABLE
Configure shared memories RAMX1 as LPCAC memories, write one lock.
0x1
PWM0SUBCTL
PWM0 Submodule Control
0x938
32
read-write
0
0xFFFFFFFF
CLK0_EN
Enables PWM0 SUB Clock0
0
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
CLK1_EN
Enables PWM0 SUB Clock1
1
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
CLK2_EN
Enables PWM0 SUB Clock2
2
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
CLK3_EN
Enables PWM0 SUB Clock3
3
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
CTIMERGLOBALSTARTEN
CTIMER Global Start Enable
0x940
32
read-write
0
0xFFFFFFFF
CTIMER0_CLK_EN
Enables the CTIMER0 function clock
0
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
CTIMER1_CLK_EN
Enables the CTIMER1 function clock
1
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
CTIMER2_CLK_EN
Enables the CTIMER2 function clock
2
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
RAM_CTRL
RAM Control
0x944
32
read-write
0x1
0xFFFFFFFF
RAMA_ECC_ENABLE
RAMA ECC enable
0
1
read-write
DISABLE
ECC is disabled
0
ENABLE
ECC is enabled
0x1
RAMA_CG_OVERRIDE
RAMA bank clock gating control, only avaiable when RAMA_ECC_ENABLE = 0.
16
1
read-write
DISABLE
Memory bank clock is gated automatically if no access more than 16 clock cycles
0
ENABLE
Auto clock gating feature is disabled
0x1
RAMX_CG_OVERRIDE
RAMX bank clock gating control
17
1
read-write
DISABLE
Memory bank clock is gated automatically if no access more than 16 clock cycles
0
ENABLE
Auto clock gating feature is disabled
0x1
GRAY_CODE_LSB
Gray to Binary Converter Gray Code [31:0]
0xB60
32
read-write
0
0xFFFFFFFF
code_gray_31_0
Gray code [31:0]
0
32
read-write
GRAY_CODE_MSB
Gray to Binary Converter Gray Code [41:32]
0xB64
32
read-write
0
0xFFFFFFFF
code_gray_41_32
Gray code [41:32]
0
10
read-write
BINARY_CODE_LSB
Gray to Binary Converter Binary Code [31:0]
0xB68
32
read-only
0
0xFFFFFFFF
code_bin_31_0
Binary code [31:0]
0
32
read-only
BINARY_CODE_MSB
Gray to Binary Converter Binary Code [41:32]
0xB6C
32
read-only
0
0xFFFFFFFF
code_bin_41_32
Binary code [41:32]
0
10
read-only
OVP_PAD_STATE
OVP_PAD_STATE
0xE40
32
read-only
0
0
OVP_PAD_STATE
OVP_PAD_STATE
0
32
read-only
PROBE_STATE
PROBE_STATE
0xE44
32
read-only
0
0
PROBE_STATE
PROBE_STATE
0
32
read-only
FT_STATE_A
FT_STATE_A
0xE48
32
read-only
0
0
FT_STATE_A
FT_STATE_A
0
32
read-only
ROP_STATE
ROP State Register
0xE4C
32
read-only
0
0
ROP_STATE
ROP state
0
32
read-only
SRAM_XEN
RAM XEN Control
0xE58
32
read-write
0
0xFFFFFFFF
RAMX0_XEN
RAMX0 Execute permission control.
0
1
read-write
DISABLE
Execute permission is disabled, R/W are enabled.
0
ENABLE
Execute permission is enabled, R/W/X are enabled.
0x1
RAMX1_XEN
RAMX1 Execute permission control.
1
1
read-write
DISABLE
Execute permission is disabled, R/W are enabled.
0
ENABLE
Execute permission is enabled, R/W/X are enabled.
0x1
RAMA0_XEN
RAMA0 Execute permission control.
2
1
read-write
DISABLE
Execute permission is disabled, R/W are enabled.
0
ENABLE
Execute permission is enabled, R/W/X are enabled.
0x1
RAMA1_XEN
RAMAx (excepts RAMA0) Execute permission control.
3
1
read-write
DISABLE
Execute permission is disabled, R/W are enabled.
0
ENABLE
Execute permission is enabled, R/W/X are enabled.
0x1
LOCK
This 1-bit field provides a mechanism to limit writes to the this register (and SRAM_XEN_DP) to protect its contents. Once set, this bit remains asserted until the next reset.
31
1
read-write
LOCK_0
This register is not locked and can be altered.
0
LOCK_1
This register is locked and cannot be altered.
0x1
SRAM_XEN_DP
RAM XEN Control (Duplicate)
0xE5C
32
read-write
0
0xFFFFFFFF
RAMX0_XEN
Refer to SRAM_XEN for more details.
0
1
read-write
RAMX1_XEN
Refer to SRAM_XEN for more details.
1
1
read-write
RAMA0_XEN
Refer to SRAM_XEN for more details.
2
1
read-write
RAMA1_XEN
Refer to SRAM_XEN for more details.
3
1
read-write
ELS_OTP_LC_STATE
Life Cycle State Register
0xE80
32
read-only
0
0xFFFFFF00
OTP_LC_STATE
OTP life cycle state
0
8
read-only
ELS_OTP_LC_STATE_DP
Life Cycle State Register (Duplicate)
0xE84
32
read-only
0
0xFFFFFF00
OTP_LC_STATE_DP
OTP life cycle state
0
8
read-only
DEBUG_LOCK_EN
Control Write Access to Security
0xFA0
32
read-write
0xA
0xFFFFFFFF
LOCK_ALL
Controls write access to the security registers
0
4
read-write
DISABLE
Any other value than b1010: disables write access to all registers
0
ENABLE
Enables write access to all registers
0xA
DEBUG_FEATURES
Cortex Debug Features Control
0xFA4
32
read-write
0
0
CPU0_DBGEN
CPU0 invasive debug control
0
2
read-write
DISABLE
Disables debug
0x1
ENABLE
Enables debug
0x2
CPU0_NIDEN
CPU0 non-invasive debug control
2
2
read-write
DISABLE
Disables debug
0x1
ENABLE
Enables debug
0x2
DEBUG_FEATURES_DP
Cortex Debug Features Control (Duplicate)
0xFA8
32
read-write
0
0
CPU0_DBGEN
CPU0 invasive debug control
0
2
read-write
DISABLE
Disables debug
0x1
ENABLE
Enables debug
0x2
CPU0_NIDEN
CPU0 non-invasive debug control
2
2
read-write
DISABLE
Disables debug
0x1
ENABLE
Enables debug
0x2
SWD_ACCESS_CPU0
CPU0 Software Debug Access
0xFB4
32
read-write
0
0xFFFFFFFF
SEC_CODE
CPU0 SWD-AP: 0x12345678
0
32
read-write
DISABLE
CPU0 DAP is not allowed. Reading back register is read as 0x5.
0
ENABLE
Value to write to enable CPU0 SWD access. Reading back register is read as 0xA.
0x12345678
DEBUG_AUTH_BEACON
Debug Authentication BEACON
0xFC0
32
read-write
0
0xFFFFFFFF
BEACON
Sets by the debug authentication code in ROM to pass the debug beacons (Credential Beacon and Authentication Beacon) to the application code.
0
32
read-write
JTAG_ID
JTAG Chip ID
0xFF0
32
read-only
0x726602B
0xFFFFFFFF
JTAG_ID
Indicates the device ID
0
32
read-only
DEVICE_TYPE
Device Type
0xFF4
32
read-only
0x2000
0xF000
DEVICE_TYPE
Indicates DEVICE TYPE.
0
32
read-only
DEVICE_ID0
Device ID
0xFF8
32
read-only
0
0xF00FFF00
ROM_REV_MINOR
ROM revision.
20
4
read-only
DIEID
Chip Revision ID and Number
0xFFC
32
read-only
0x55F1A0
0xFFFFFFFF
MINOR_REVISION
Chip minor revision
0
4
read-only
MAJOR_REVISION
Chip major revision
4
4
read-only
MCO_NUM_IN_DIE_ID
Chip number
8
20
read-only
GLIKEY0
GLIKEY
IP_GLIKEY
0x40091D00
0
0x1000
registers
GLIKEY0
13
CTRL_0
Control Register 0 SFR
0
32
read-write
0x20000
0x700FF
WRITE_INDEX
Write Index
0
8
read-write
RESERVED15
Reserved for Future Use
8
8
read-only
WR_EN_0
Write Enable 0
16
2
read-write
SFT_RST
Soft reset for the core reset (SFR configuration will be preseved).This register reads as 0
18
1
read-write
DISABLE
No effect
0
ENABLE
Triggers the soft reset
0x1
RESERVED31
Reserved for Future Use
19
13
read-only
CTRL_1
Control Regsiter 1 SFR
0x4
32
read-write
0x280000
0x3F00FF
READ_INDEX
Index status, Writing an index value to this register will request the block to return the lock status of this index.
0
8
read-write
RESERVED15
Reserved for Future Use
8
8
read-only
WR_EN_1
Write Enable One
16
2
read-write
SFR_LOCK
LOCK register for GLIKEY
18
4
read-write
RESERVED31
Reserved for Future Use
22
10
read-only
INTR_CTRL
Interrupt Control
0x8
32
read-write
0
0x7
INT_EN
Interrupt Enable. Writing a 1, Interrupt asserts on Interrupt output port
0
1
read-write
INT_CLR
Interrupt Clear. Writing a 1 to this register creates a single interrupt clear pulse. This register reads as 0
1
1
read-write
INT_SET
Interrupt Set. Writing a 1 to this register asserts the interrupt. This register reads as 0
2
1
read-write
DISABLE
No effect
0
ENABLE
Triggers interrupt
0x1
RESERVED31
Reserved for Future Use
3
29
read-only
STATUS
Status
0xC
32
read-only
0xB00000
0xFFF8001F
INT_STATUS
Interrupt Status.
0
1
read-only
DISABLE
No effect
0
ENABLE
Triggers interrupt
0x1
LOCK_STATUS
Provides the current lock status of indexes.
1
1
read-only
LOCK0
Current read index is not locked
0
LOCK1
Current read index is locked
0x1
ERROR_STATUS
Status of the Error
2
3
read-only
STAT0
No error
0
STAT1
FSM error has occurred
0x1
STAT2
Write index out of the bound (OOB) error
0x2
STAT3
Write index OOB and FSM error
0x3
STAT4
Read index OOB error
0x4
STAT5
Write index and read index OOB error
0x6
STAT6
Read index OOB, write index OOB, and FSM error
0x7
RESERVED18
Reserved for Future Use
5
14
read-only
FSM_STATE
Status of FSM
19
13
read-only
VERSION
IP Version
0xFC
32
read-only
0x7B0100
0xFFFFFFFF
Reserved3
Reserved
0
4
read-only
Reserved7
Reserved
4
4
read-only
Reserved11
Reserved
8
4
read-only
Reserved15
Reserved
12
4
read-only
Reserved16
Reserved
16
2
read-only
FSM_CONFIG
0:4 step, 1:8 step
18
1
read-only
INDEX_CONFIG
Configured number of addressable indexes
19
8
read-only
Reserved31
Reserved for Future Use
27
5
read-only
WUU0
WUU
WUU
0x40092000
0
0x5C
registers
WUU0
18
VERID
Version ID
0
32
read-only
0x1000001
0xFFFFFFFF
FEATURE
Feature Specification Number
0
16
read-only
STANDARD
Standard features implemented
0
FILT_ALL_PWR
Support for DMA/Trigger generation from wake-up pins and filters enabled. Support for external pin/filter detection during all power modes enabled.
0x1
MINOR
Minor Version Number
16
8
read-only
MAJOR
Major Version Number
24
8
read-only
PARAM
Parameter
0x4
32
read-only
0x20202002
0xFFFFFFFF
FILTERS
Filter Number
0
8
read-only
DMAS
DMA Number
8
8
read-only
MODULES
Module Number
16
8
read-only
PINS
Pin Number
24
8
read-only
PE1
Pin Enable 1
0x8
32
read-write
0
0xFFFFFFFF
Reserved0
Reserved
0
2
read-only
DISABLE
Not supported
0
EN_RISE_HI
Not supported
0x1
EN_FALL_LO
Not supported
0x2
EN_ANY
Not supported
0x3
Reserved1
Reserved
2
2
read-only
DISABLE
Not supported
0
EN_RISE_HI
Not supported
0x1
EN_FALL_LO
Not supported
0x2
EN_ANY
Not supported
0x3
WUPE2
Wake-up Pin Enable for WUU_Pn
4
2
read-write
DISABLE
Disable
0
EN_RISE_HI
Enable (detect on rising edge or high level)
0x1
EN_FALL_LO
Enable (detect on falling edge or low level)
0x2
EN_ANY
Enable (detect on any edge)
0x3
Reserved3
Reserved
6
2
read-only
DISABLE
Not supported
0
EN_RISE_HI
Not supported
0x1
EN_FALL_LO
Not supported
0x2
EN_ANY
Not supported
0x3
Reserved4
Reserved
8
2
read-only
DISABLE
Not supported
0
EN_RISE_HI
Not supported
0x1
EN_FALL_LO
Not supported
0x2
EN_ANY
Not supported
0x3
Reserved5
Reserved
10
2
read-only
DISABLE
Not supported
0
EN_RISE_HI
Not supported
0x1
EN_FALL_LO
Not supported
0x2
EN_ANY
Not supported
0x3
WUPE6
Wake-up Pin Enable for WUU_Pn
12
2
read-write
DISABLE
Disable
0
EN_RISE_HI
Enable (detect on rising edge or high level)
0x1
EN_FALL_LO
Enable (detect on falling edge or low level)
0x2
EN_ANY
Enable (detect on any edge)
0x3
WUPE7
Wake-up Pin Enable for WUU_Pn
14
2
read-write
DISABLE
Disable
0
EN_RISE_HI
Enable (detect on rising edge or high level)
0x1
EN_FALL_LO
Enable (detect on falling edge or low level)
0x2
EN_ANY
Enable (detect on any edge)
0x3
WUPE8
Wake-up Pin Enable for WUU_Pn
16
2
read-write
DISABLE
Disable
0
EN_RISE_HI
Enable (detect on rising edge or high level)
0x1
EN_FALL_LO
Enable (detect on falling edge or low level)
0x2
EN_ANY
Enable (detect on any edge)
0x3
WUPE9
Wake-up Pin Enable for WUU_Pn
18
2
read-write
DISABLE
Disable
0
EN_RISE_HI
Enable (detect on rising edge or high level)
0x1
EN_FALL_LO
Enable (detect on falling edge or low level)
0x2
EN_ANY
Enable (detect on any edge)
0x3
WUPE10
Wake-up Pin Enable for WUU_Pn
20
2
read-write
DISABLE
Disable
0
EN_RISE_HI
Enable (detect on rising edge or high level)
0x1
EN_FALL_LO
Enable (detect on falling edge or low level)
0x2
EN_ANY
Enable (detect on any edge)
0x3
WUPE11
Wake-up Pin Enable for WUU_Pn
22
2
read-write
DISABLE
Disable
0
EN_RISE_HI
Enable (detect on rising edge or high level)
0x1
EN_FALL_LO
Enable (detect on falling edge or low level)
0x2
EN_ANY
Enable (detect on any edge)
0x3
WUPE12
Wake-up Pin Enable for WUU_Pn
24
2
read-write
DISABLE
Disable
0
EN_RISE_HI
Enable (detect on rising edge or high level)
0x1
EN_FALL_LO
Enable (detect on falling edge or low level)
0x2
EN_ANY
Enable (detect on any edge)
0x3
Reserved13
Reserved
26
2
read-only
DISABLE
Not supported
0
EN_RISE_HI
Not supported
0x1
EN_FALL_LO
Not supported
0x2
EN_ANY
Not supported
0x3
Reserved14
Reserved
28
2
read-only
DISABLE
Not supported
0
EN_RISE_HI
Not supported
0x1
EN_FALL_LO
Not supported
0x2
EN_ANY
Not supported
0x3
Reserved15
Reserved
30
2
read-only
DISABLE
Not supported
0
EN_RISE_HI
Not supported
0x1
EN_FALL_LO
Not supported
0x2
EN_ANY
Not supported
0x3
PE2
Pin Enable 2
0xC
32
read-write
0
0xFFFFFFFF
Reserved16
Reserved
0
2
read-only
DISABLE
Not supported
0
EN_RISE_HI
Not supported
0x1
EN_FALL_LO
Not supported
0x2
EN_ANY
Not supported
0x3
Reserved17
Reserved
2
2
read-only
DISABLE
Not supported
0
EN_RISE_HI
Not supported
0x1
EN_FALL_LO
Not supported
0x2
EN_ANY
Not supported
0x3
WUPE18
Wake-up Pin Enable for WUU_Pn
4
2
read-write
DISABLE
Disable
0
EN_RISE_HI
Enable (detect on rising edge or high level)
0x1
EN_FALL_LO
Enable (detect on falling edge or low level)
0x2
EN_ANY
Enable (detect on any edge)
0x3
WUPE19
Wake-up Pin Enable for WUU_Pn
6
2
read-write
DISABLE
Disable
0
EN_RISE_HI
Enable (detect on rising edge or high level)
0x1
EN_FALL_LO
Enable (detect on falling edge or low level)
0x2
EN_ANY
Enable (detect on any edge)
0x3
WUPE20
Wake-up Pin Enable for WUU_Pn
8
2
read-write
DISABLE
Disable
0
EN_RISE_HI
Enable (detect on rising edge or high level)
0x1
EN_FALL_LO
Enable (detect on falling edge or low level)
0x2
EN_ANY
Enable (detect on any edge)
0x3
Reserved21
Reserved
10
2
read-only
DISABLE
Not supported
0
EN_RISE_HI
Not supported
0x1
EN_FALL_LO
Not supported
0x2
EN_ANY
Not supported
0x3
WUPE22
Wake-up Pin Enable for WUU_Pn
12
2
read-write
DISABLE
Disable
0
EN_RISE_HI
Enable (detect on rising edge or high level)
0x1
EN_FALL_LO
Enable (detect on falling edge or low level)
0x2
EN_ANY
Enable (detect on any edge)
0x3
WUPE23
Wake-up Pin Enable for WUU_Pn
14
2
read-write
DISABLE
Disable
0
EN_RISE_HI
Enable (detect on rising edge or high level)
0x1
EN_FALL_LO
Enable (detect on falling edge or low level)
0x2
EN_ANY
Enable (detect on any edge)
0x3
WUPE24
Wake-up Pin Enable for WUU_Pn
16
2
read-write
DISABLE
Disable
0
EN_RISE_HI
Enable (detect on rising edge or high level)
0x1
EN_FALL_LO
Enable (detect on falling edge or low level)
0x2
EN_ANY
Enable (detect on any edge)
0x3
WUPE25
Wake-up Pin Enable for WUU_Pn
18
2
read-write
DISABLE
Disable
0
EN_RISE_HI
Enable (detect on rising edge or high level)
0x1
EN_FALL_LO
Enable (detect on falling edge or low level)
0x2
EN_ANY
Enable (detect on any edge)
0x3
WUPE26
Wake-up Pin Enable for WUU_Pn
20
2
read-write
DISABLE
Disable
0
EN_RISE_HI
Enable (detect on rising edge or high level)
0x1
EN_FALL_LO
Enable (detect on falling edge or low level)
0x2
EN_ANY
Enable (detect on any edge)
0x3
WUPE27
Wake-up Pin Enable for WUU_Pn
22
2
read-write
DISABLE
Disable
0
EN_RISE_HI
Enable (detect on rising edge or high level)
0x1
EN_FALL_LO
Enable (detect on falling edge or low level)
0x2
EN_ANY
Enable (detect on any edge)
0x3
WUPE28
Wake-up Pin Enable for WUU_Pn
24
2
read-write
DISABLE
Disable
0
EN_RISE_HI
Enable (detect on rising edge or high level)
0x1
EN_FALL_LO
Enable (detect on falling edge or low level)
0x2
EN_ANY
Enable (detect on any edge)
0x3
WUPE29
Wake-up Pin Enable for WUU_Pn
26
2
read-write
DISABLE
Disable
0
EN_RISE_HI
Enable (detect on rising edge or high level)
0x1
EN_FALL_LO
Enable (detect on falling edge or low level)
0x2
EN_ANY
Enable (detect on any edge)
0x3
Reserved30
Reserved
28
2
read-only
DISABLE
Not supported
0
EN_RISE_HI
Not supported
0x1
EN_FALL_LO
Not supported
0x2
EN_ANY
Not supported
0x3
WUPE31
Wake-up Pin Enable for WUU_Pn
30
2
read-write
DISABLE
Disable
0
EN_RISE_HI
Enable (detect on rising edge or high level)
0x1
EN_FALL_LO
Enable (detect on falling edge or low level)
0x2
EN_ANY
Enable (detect on any edge)
0x3
ME
Module Interrupt Enable
0x18
32
read-write
0
0xFFFFFFFF
WUME0
Module Interrupt Wake-up Enable for Module 0
0
1
read-write
WUME2
Module Interrupt Wake-up Enable for Module 2
2
1
read-write
WUME6
Module Interrupt Wake-up Enable for Module 6
6
1
read-write
WUME8
Module Interrupt Wake-up Enable for Module 8
8
1
read-write
DE
Module DMA/Trigger Enable
0x1C
32
read-write
0
0xFFFFFFFF
WUDE4
DMA/Trigger Wake-up Enable for Module 4
4
1
read-write
WUDE6
DMA/Trigger Wake-up Enable for Module 6
6
1
read-write
WUDE8
DMA/Trigger Wake-up Enable for Module 8
8
1
read-write
PF
Pin Flag
0x20
32
read-write
0
0xFFFFFFFF
Reserved0
Reserved
0
1
read-only
NO_FLAG
Not supported
0
FLAG
Not supported
0x1
Reserved1
Reserved
1
1
read-only
NO_FLAG
Not supported
0
FLAG
Not supported
0x1
WUF2
Wake-up Flag for WUU_Pn
2
1
read-write
oneToClear
NO_FLAG
No
0
FLAG
Yes
0x1
Reserved3
Reserved
3
1
read-only
NO_FLAG
Not supported
0
FLAG
Not supported
0x1
Reserved4
Reserved
4
1
read-only
NO_FLAG
Not supported
0
FLAG
Not supported
0x1
Reserved5
Reserved
5
1
read-only
NO_FLAG
Not supported
0
FLAG
Not supported
0x1
WUF6
Wake-up Flag for WUU_Pn
6
1
read-write
oneToClear
NO_FLAG
No
0
FLAG
Yes
0x1
WUF7
Wake-up Flag for WUU_Pn
7
1
read-write
oneToClear
NO_FLAG
No
0
FLAG
Yes
0x1
WUF8
Wake-up Flag for WUU_Pn
8
1
read-write
oneToClear
NO_FLAG
No
0
FLAG
Yes
0x1
WUF9
Wake-up Flag for WUU_Pn
9
1
read-write
oneToClear
NO_FLAG
No
0
FLAG
Yes
0x1
WUF10
Wake-up Flag for WUU_Pn
10
1
read-write
oneToClear
NO_FLAG
No
0
FLAG
Yes
0x1
WUF11
Wake-up Flag for WUU_Pn
11
1
read-write
oneToClear
NO_FLAG
No
0
FLAG
Yes
0x1
WUF12
Wake-up Flag for WUU_Pn
12
1
read-write
oneToClear
NO_FLAG
No
0
FLAG
Yes
0x1
Reserved13
Reserved
13
1
read-only
NO_FLAG
Not supported
0
FLAG
Not supported
0x1
Reserved14
Reserved
14
1
read-only
NO_FLAG
Not supported
0
FLAG
Not supported
0x1
Reserved15
Reserved
15
1
read-only
NO_FLAG
Not supported
0
FLAG
Not supported
0x1
Reserved16
Reserved
16
1
read-only
NO_FLAG
Not supported
0
FLAG
Not supported
0x1
Reserved17
Reserved
17
1
read-only
NO_FLAG
Not supported
0
FLAG
Not supported
0x1
WUF18
Wake-up Flag for WUU_Pn
18
1
read-write
oneToClear
NO_FLAG
No
0
FLAG
Yes
0x1
WUF19
Wake-up Flag for WUU_Pn
19
1
read-write
oneToClear
NO_FLAG
No
0
FLAG
Yes
0x1
WUF20
Wake-up Flag for WUU_Pn
20
1
read-write
oneToClear
NO_FLAG
No
0
FLAG
Yes
0x1
Reserved21
Reserved
21
1
read-only
NO_FLAG
Not supported
0
FLAG
Not supported
0x1
WUF22
Wake-up Flag for WUU_Pn
22
1
read-write
oneToClear
NO_FLAG
No
0
FLAG
Yes
0x1
WUF23
Wake-up Flag for WUU_Pn
23
1
read-write
oneToClear
NO_FLAG
No
0
FLAG
Yes
0x1
WUF24
Wake-up Flag for WUU_Pn
24
1
read-write
oneToClear
NO_FLAG
No
0
FLAG
Yes
0x1
WUF25
Wake-up Flag for WUU_Pn
25
1
read-write
oneToClear
NO_FLAG
No
0
FLAG
Yes
0x1
WUF26
Wake-up Flag for WUU_Pn
26
1
read-write
oneToClear
NO_FLAG
No
0
FLAG
Yes
0x1
WUF27
Wake-up Flag for WUU_Pn
27
1
read-write
oneToClear
NO_FLAG
No
0
FLAG
Yes
0x1
WUF28
Wake-up Flag for WUU_Pn
28
1
read-write
oneToClear
NO_FLAG
No
0
FLAG
Yes
0x1
WUF29
Wake-up Flag for WUU_Pn
29
1
read-write
oneToClear
NO_FLAG
No
0
FLAG
Yes
0x1
Reserved30
Reserved
30
1
read-only
NO_FLAG
Not supported
0
FLAG
Not supported
0x1
WUF31
Wake-up Flag for WUU_Pn
31
1
read-write
oneToClear
NO_FLAG
No
0
FLAG
Yes
0x1
FILT
Pin Filter
0x30
32
read-write
0
0xFFFFFFFF
FILTSEL1
Filter 1 Pin Select
0
5
read-write
FILTE1
Filter 1 Enable
5
2
read-write
DISABLE
Disable
0
EN_RISE_HI
Enable (Detect on rising edge or high level)
0x1
EN_FALL_LO
Enable (Detect on falling edge or low level)
0x2
EN_ANY
Enable (Detect on any edge)
0x3
FILTF1
Filter 1 Flag
7
1
read-write
oneToClear
NO_FLAG
No
0
FLAG
Yes
0x1
FILTSEL2
Filter 2 Pin Select
8
5
read-write
FILTE2
Filter 2 Enable
13
2
read-write
DISABLE
Disable
0
EN_RISE_HI
Enable (Detect on rising edge or high level)
0x1
EN_FALL_LO
Enable (Detect on falling edge or low level)
0x2
EN_ANY
Enable (Detect on any edge)
0x3
FILTF2
Filter 2 Flag
15
1
read-write
oneToClear
NO_FLAG
No
0
FLAG
Yes
0x1
PDC1
Pin DMA/Trigger Configuration 1
0x38
32
read-write
0
0xFFFFFFFF
Reserved0
Reserved
0
2
read-only
INTERRUPT
Not supported
0
DMA_REQ
Not supported
0x1
TRIGGER
Not supported
0x2
RES
Not supported
0x3
Reserved1
Reserved
2
2
read-only
INTERRUPT
Not supported
0
DMA_REQ
Not supported
0x1
TRIGGER
Not supported
0x2
RES
Not supported
0x3
WUPDC2
Wake-up Pin Configuration for WUU_Pn
4
2
read-write
INTERRUPT
Interrupt
0
DMA_REQ
DMA request
0x1
TRIGGER
Trigger event
0x2
RES
Reserved
0x3
Reserved3
Reserved
6
2
read-only
INTERRUPT
Not supported
0
DMA_REQ
Not supported
0x1
TRIGGER
Not supported
0x2
RES
Not supported
0x3
Reserved4
Reserved
8
2
read-only
INTERRUPT
Not supported
0
DMA_REQ
Not supported
0x1
TRIGGER
Not supported
0x2
RES
Not supported
0x3
Reserved5
Reserved
10
2
read-only
INTERRUPT
Not supported
0
DMA_REQ
Not supported
0x1
TRIGGER
Not supported
0x2
RES
Not supported
0x3
WUPDC6
Wake-up Pin Configuration for WUU_Pn
12
2
read-write
INTERRUPT
Interrupt
0
DMA_REQ
DMA request
0x1
TRIGGER
Trigger event
0x2
RES
Reserved
0x3
WUPDC7
Wake-up Pin Configuration for WUU_Pn
14
2
read-write
INTERRUPT
Interrupt
0
DMA_REQ
DMA request
0x1
TRIGGER
Trigger event
0x2
RES
Reserved
0x3
WUPDC8
Wake-up Pin Configuration for WUU_Pn
16
2
read-write
INTERRUPT
Interrupt
0
DMA_REQ
DMA request
0x1
TRIGGER
Trigger event
0x2
RES
Reserved
0x3
WUPDC9
Wake-up Pin Configuration for WUU_Pn
18
2
read-write
INTERRUPT
Interrupt
0
DMA_REQ
DMA request
0x1
TRIGGER
Trigger event
0x2
RES
Reserved
0x3
WUPDC10
Wake-up Pin Configuration for WUU_Pn
20
2
read-write
INTERRUPT
Interrupt
0
DMA_REQ
DMA request
0x1
TRIGGER
Trigger event
0x2
RES
Reserved
0x3
WUPDC11
Wake-up Pin Configuration for WUU_Pn
22
2
read-write
INTERRUPT
Interrupt
0
DMA_REQ
DMA request
0x1
TRIGGER
Trigger event
0x2
RES
Reserved
0x3
WUPDC12
Wake-up Pin Configuration for WUU_Pn
24
2
read-write
INTERRUPT
Interrupt
0
DMA_REQ
DMA request
0x1
TRIGGER
Trigger event
0x2
RES
Reserved
0x3
Reserved13
Reserved
26
2
read-only
INTERRUPT
Not supported
0
DMA_REQ
Not supported
0x1
TRIGGER
Not supported
0x2
RES
Not supported
0x3
Reserved14
Reserved
28
2
read-only
INTERRUPT
Not supported
0
DMA_REQ
Not supported
0x1
TRIGGER
Not supported
0x2
RES
Not supported
0x3
Reserved15
Reserved
30
2
read-only
INTERRUPT
Not supported
0
DMA_REQ
Not supported
0x1
TRIGGER
Not supported
0x2
RES
Not supported
0x3
PDC2
Pin DMA/Trigger Configuration 2
0x3C
32
read-write
0
0xFFFFFFFF
Reserved16
Reserved
0
2
read-only
INTERRUPT
Not supported
0
DMA_REQ
Not supported
0x1
TRIGGER
Not supported
0x2
RES
Not supported
0x3
Reserved17
Reserved
2
2
read-only
INTERRUPT
Not supported
0
DMA_REQ
Not supported
0x1
TRIGGER
Not supported
0x2
RES
Not supported
0x3
WUPDC18
Wake-up Pin Configuration for WUU_Pn
4
2
read-write
INTERRUPT
Interrupt
0
DMA_REQ
DMA request
0x1
TRIGGER
Trigger event
0x2
RES
Reserved
0x3
WUPDC19
Wake-up Pin Configuration for WUU_Pn
6
2
read-write
INTERRUPT
Interrupt
0
DMA_REQ
DMA request
0x1
TRIGGER
Trigger event
0x2
RES
Reserved
0x3
WUPDC20
Wake-up Pin Configuration for WUU_Pn
8
2
read-write
INTERRUPT
Interrupt
0
DMA_REQ
DMA request
0x1
TRIGGER
Trigger event
0x2
RES
Reserved
0x3
Reserved21
Reserved
10
2
read-only
INTERRUPT
Not supported
0
DMA_REQ
Not supported
0x1
TRIGGER
Not supported
0x2
RES
Not supported
0x3
WUPDC22
Wake-up Pin Configuration for WUU_Pn
12
2
read-write
INTERRUPT
Interrupt
0
DMA_REQ
DMA request
0x1
TRIGGER
Trigger event
0x2
RES
Reserved
0x3
WUPDC23
Wake-up Pin Configuration for WUU_Pn
14
2
read-write
INTERRUPT
Interrupt
0
DMA_REQ
DMA request
0x1
TRIGGER
Trigger event
0x2
RES
Reserved
0x3
WUPDC24
Wake-up Pin Configuration for WUU_Pn
16
2
read-write
INTERRUPT
Interrupt
0
DMA_REQ
DMA request
0x1
TRIGGER
Trigger event
0x2
RES
Reserved
0x3
WUPDC25
Wake-up Pin Configuration for WUU_Pn
18
2
read-write
INTERRUPT
Interrupt
0
DMA_REQ
DMA request
0x1
TRIGGER
Trigger event
0x2
RES
Reserved
0x3
WUPDC26
Wake-up Pin Configuration for WUU_Pn
20
2
read-write
INTERRUPT
Interrupt
0
DMA_REQ
DMA request
0x1
TRIGGER
Trigger event
0x2
RES
Reserved
0x3
WUPDC27
Wake-up Pin Configuration for WUU_Pn
22
2
read-write
INTERRUPT
Interrupt
0
DMA_REQ
DMA request
0x1
TRIGGER
Trigger event
0x2
RES
Reserved
0x3
WUPDC28
Wake-up Pin Configuration for WUU_Pn
24
2
read-write
INTERRUPT
Interrupt
0
DMA_REQ
DMA request
0x1
TRIGGER
Trigger event
0x2
RES
Reserved
0x3
WUPDC29
Wake-up Pin Configuration for WUU_Pn
26
2
read-write
INTERRUPT
Interrupt
0
DMA_REQ
DMA request
0x1
TRIGGER
Trigger event
0x2
RES
Reserved
0x3
Reserved30
Reserved
28
2
read-only
INTERRUPT
Not supported
0
DMA_REQ
Not supported
0x1
TRIGGER
Not supported
0x2
RES
Not supported
0x3
WUPDC31
Wake-up Pin Configuration for WUU_Pn
30
2
read-write
INTERRUPT
Interrupt
0
DMA_REQ
DMA request
0x1
TRIGGER
Trigger event
0x2
RES
Reserved
0x3
FDC
Pin Filter DMA/Trigger Configuration
0x48
32
read-write
0
0xFFFFFFFF
FILTC1
Filter Configuration for FILTn
0
2
read-write
INTERRUPT
Interrupt
0
DMA_REQ
DMA request
0x1
TRIGGER
Trigger event
0x2
FILTC2
Filter Configuration for FILTn
2
2
read-write
INTERRUPT
Interrupt
0
DMA_REQ
DMA request
0x1
TRIGGER
Trigger event
0x2
PMC
Pin Mode Configuration
0x50
32
read-write
0
0xFFFFFFFF
Reserved0
Reserved
0
1
read-only
LOW_PWR_ONLY
Not supported
0
ANY_PWR
Not supported
0x1
Reserved1
Reserved
1
1
read-only
LOW_PWR_ONLY
Not supported
0
ANY_PWR
Not supported
0x1
WUPMC2
Wake-up Pin Mode Configuration for WUU_Pn
2
1
read-write
LOW_PWR_ONLY
Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0
ANY_PWR
Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0x1
Reserved3
Reserved
3
1
read-only
LOW_PWR_ONLY
Not supported
0
ANY_PWR
Not supported
0x1
Reserved4
Reserved
4
1
read-only
LOW_PWR_ONLY
Not supported
0
ANY_PWR
Not supported
0x1
Reserved5
Reserved
5
1
read-only
LOW_PWR_ONLY
Not supported
0
ANY_PWR
Not supported
0x1
WUPMC6
Wake-up Pin Mode Configuration for WUU_Pn
6
1
read-write
LOW_PWR_ONLY
Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0
ANY_PWR
Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0x1
WUPMC7
Wake-up Pin Mode Configuration for WUU_Pn
7
1
read-write
LOW_PWR_ONLY
Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0
ANY_PWR
Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0x1
WUPMC8
Wake-up Pin Mode Configuration for WUU_Pn
8
1
read-write
LOW_PWR_ONLY
Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0
ANY_PWR
Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0x1
WUPMC9
Wake-up Pin Mode Configuration for WUU_Pn
9
1
read-write
LOW_PWR_ONLY
Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0
ANY_PWR
Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0x1
WUPMC10
Wake-up Pin Mode Configuration for WUU_Pn
10
1
read-write
LOW_PWR_ONLY
Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0
ANY_PWR
Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0x1
WUPMC11
Wake-up Pin Mode Configuration for WUU_Pn
11
1
read-write
LOW_PWR_ONLY
Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0
ANY_PWR
Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0x1
WUPMC12
Wake-up Pin Mode Configuration for WUU_Pn
12
1
read-write
LOW_PWR_ONLY
Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0
ANY_PWR
Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0x1
Reserved13
Reserved
13
1
read-only
LOW_PWR_ONLY
Not supported
0
ANY_PWR
Not supported
0x1
Reserved14
Reserved
14
1
read-only
LOW_PWR_ONLY
Not supported
0
ANY_PWR
Not supported
0x1
Reserved15
Reserved
15
1
read-only
LOW_PWR_ONLY
Not supported
0
ANY_PWR
Not supported
0x1
Reserved16
Reserved
16
1
read-only
LOW_PWR_ONLY
Not supported
0
ANY_PWR
Not supported
0x1
Reserved17
Reserved
17
1
read-only
LOW_PWR_ONLY
Not supported
0
ANY_PWR
Not supported
0x1
WUPMC18
Wake-up Pin Mode Configuration for WUU_Pn
18
1
read-write
LOW_PWR_ONLY
Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0
ANY_PWR
Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0x1
WUPMC19
Wake-up Pin Mode Configuration for WUU_Pn
19
1
read-write
LOW_PWR_ONLY
Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0
ANY_PWR
Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0x1
WUPMC20
Wake-up Pin Mode Configuration for WUU_Pn
20
1
read-write
LOW_PWR_ONLY
Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0
ANY_PWR
Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0x1
Reserved21
Reserved
21
1
read-only
LOW_PWR_ONLY
Not supported
0
ANY_PWR
Not supported
0x1
WUPMC22
Wake-up Pin Mode Configuration for WUU_Pn
22
1
read-write
LOW_PWR_ONLY
Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0
ANY_PWR
Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0x1
WUPMC23
Wake-up Pin Mode Configuration for WUU_Pn
23
1
read-write
LOW_PWR_ONLY
Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0
ANY_PWR
Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0x1
WUPMC24
Wake-up Pin Mode Configuration for WUU_Pn
24
1
read-write
LOW_PWR_ONLY
Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0
ANY_PWR
Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0x1
WUPMC25
Wake-up Pin Mode Configuration for WUU_Pn
25
1
read-write
LOW_PWR_ONLY
Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0
ANY_PWR
Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0x1
WUPMC26
Wake-up Pin Mode Configuration for WUU_Pn
26
1
read-write
LOW_PWR_ONLY
Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0
ANY_PWR
Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0x1
WUPMC27
Wake-up Pin Mode Configuration for WUU_Pn
27
1
read-write
LOW_PWR_ONLY
Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0
ANY_PWR
Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0x1
WUPMC28
Wake-up Pin Mode Configuration for WUU_Pn
28
1
read-write
LOW_PWR_ONLY
Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0
ANY_PWR
Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0x1
WUPMC29
Wake-up Pin Mode Configuration for WUU_Pn
29
1
read-write
LOW_PWR_ONLY
Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0
ANY_PWR
Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0x1
Reserved30
Reserved
30
1
read-only
LOW_PWR_ONLY
Not supported
0
ANY_PWR
Not supported
0x1
WUPMC31
Wake-up Pin Mode Configuration for WUU_Pn
31
1
read-write
LOW_PWR_ONLY
Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0
ANY_PWR
Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
0x1
FMC
Pin Filter Mode Configuration
0x58
32
read-write
0
0xFFFFFFFF
FILTM1
Filter Mode for FILTn
0
1
read-write
LOW_PWR_ONLY
Active only during Power Down/Deep Power Down mode
0
ANY_PWR
Active during all power modes
0x1
FILTM2
Filter Mode for FILTn
1
1
read-write
LOW_PWR_ONLY
Active only during Power Down/Deep Power Down mode
0
ANY_PWR
Active during all power modes
0x1
VBAT0
VBAT
VBAT
0x40093000
0
0x7FC
registers
VERID
Version ID
0
32
read-only
0x1010001
0xFFFFFFFF
FEATURE
Feature Specification Number
0
16
read-only
MINOR
Minor Version Number
16
8
read-only
MAJOR
Major Version Number
24
8
read-only
FROCTLA
FRO16K Control A
0x200
32
read-write
0x1
0xFFFFFFFF
FRO_EN
FRO16K Enable
0
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
FROLCKA
FRO16K Lock A
0x218
32
read-write
0
0xFFFFFFFF
LOCK
Lock
0
1
read-write
DISABLE
Do not block
0
ENABLE
Block
0x1
FROCLKE
FRO16K Clock Enable
0x220
32
read-write
0
0xFFFFFFFF
CLKE
Clock Enable
0
2
read-write
2
0x8
WAKEUP[%s]
no description available
0x700
WAKEUPA
Wakeup 0 Register A
0
32
read-write
0
0xFFFFFFFF
REG
Register
0
32
read-write
WAKLCKA
Wakeup Lock A
0x7F8
32
read-write
0
0xFFFFFFFF
LOCK
Lock
0
1
read-write
DISABLE
Lock is disabled
0
ENABLE
Lock is enabled
0x1
FMC0
NPX
FMC
0x40094000
0
0x24
registers
REMAP
Data Remap
0x20
32
read-write
0
0xFFFFFFFF
REMAPLK
Remap Lock Enable
0
1
read-write
LOCK_DISABLED
Lock disabled: can write to REMAP
0
LOCK_ENABLED
Lock enabled: cannot write to REMAP
0x1
LIM
LIM Remapping Address
16
5
read-write
LIMDP
LIMDP Remapping Address
24
5
read-write
FMU0
Flash
MSF1_B
0x40095000
0
0x30
registers
FMU0
12
FSTAT
Flash Status Register
0
32
read-write
0x80
0xFFFFFFFE
FAIL
Command Fail Flag
0
1
read-only
fail0
Error not detected
0
fail1
Error detected
0x1
CMDABT
Command Abort Flag
2
1
read-write
oneToClear
cmdabt0
No command abort detected
0
cmdabt1
Command abort detected
0x1
PVIOL
Command Protection Violation Flag
4
1
read-write
oneToClear
pviol0
No protection violation detected
0
pviol1
Protection violation detected
0x1
ACCERR
Command Access Error Flag
5
1
read-write
oneToClear
accerr0
No access error detected
0
accerr1
Access error detected
0x1
CWSABT
Command Write Sequence Abort Flag
6
1
read-write
oneToClear
cwsabt0
Command write sequence not aborted
0
cwsabt1
Command write sequence aborted
0x1
CCIF
Command Complete Interrupt Flag
7
1
read-write
oneToClear
ccif0
Flash command, initialization, or power mode recovery in progress
0
ccif1
Flash command, initialization, or power mode recovery has completed
0x1
CMDPRT
Command protection level
8
2
read-only
cmdprt00
Secure, normal access
0
cmdprt01
Secure, privileged access
0x1
cmdprt10
Nonsecure, normal access
0x2
cmdprt11
Nonsecure, privileged access
0x3
CMDP
Command protection status flag
11
1
read-only
cmdp0
Command protection level and domain ID are stale
0
cmdp1
Command protection level (CMDPRT) and domain ID (CMDDID) are set
0x1
CMDDID
Command domain ID
12
4
read-only
DFDIF
Double Bit Fault Detect Interrupt Flag
16
1
read-write
oneToClear
dfdif0
Double bit fault not detected during a valid flash read access
0
dfdif1
Double bit fault detected (or FCTRL[FDFD] is set) during a valid flash read access
0x1
SALV_USED
Salvage Used for Erase operation
17
1
read-only
salv_used0
Salvage not used during last operation
0
salv_used1
Salvage used during the last erase operation
0x1
PEWEN
Program-Erase Write Enable Control
24
2
read-only
pewen00
Writes are not enabled
0
pewen01
Writes are enabled for one flash or IFR phrase (phrase programming, sector erase)
0x1
pewen10
Writes are enabled for one flash or IFR page (page programming)
0x2
PERDY
Program-Erase Ready Control/Status Flag
31
1
read-write
oneToClear
perdy0
Program or sector erase command operation not stalled
0
perdy1
Program or sector erase command operation ready to execute
0x1
FCNFG
Flash Configuration Register
0x4
32
read-write
0
0xFFFFFF
CCIE
Command Complete Interrupt Enable
7
1
read-write
ccie0
Command complete interrupt disabled
0
ccie1
Command complete interrupt enabled
0x1
ERSREQ
Mass Erase Request
8
1
read-only
ersreq0
No request or request complete
0
ersreq1
Request to run the Mass Erase operation
0x1
DFDIE
Double Bit Fault Detect Interrupt Enable
16
1
read-write
dfdie0
Double bit fault detect interrupt disabled
0
dfdie1
Double bit fault detect interrupt enabled
0x1
ERSIEN0
Erase IFR Sector Enable - Block 0
24
4
read-only
ersien00
Block 0 IFR Sector X is protected from erase by ERSSCR command
0
ersien01
Block 0 IFR Sector X is not protected from erase by ERSSCR command
0x1
ERSIEN1
Erase IFR Sector Enable - Block 1 (for dual block configs)
28
4
read-only
ersien10
Block 1 IFR Sector X is protected from erase by ERSSCR command
0
ersien11
Block 1 IFR Sector X is not protected from erase by ERSSCR command
0x1
FCTRL
Flash Control Register
0x8
32
read-write
0x100
0xFFFFFFF0
RWSC
Read Wait-State Control
0
4
read-write
LSACTIVE
Low speed active mode
8
1
read-write
lsactive0
Full speed active mode requested
0
lsactive1
Low speed active mode requested
0x1
FDFD
Force Double Bit Fault Detect
16
1
read-write
fdfd0
FSTAT[DFDIF] sets only if a double bit fault is detected during a valid flash read access from the platform flash controller
0
fdfd1
FSTAT[DFDIF] sets during any valid flash read access from the platform flash controller. An interrupt request is generated if the DFDIE bit is set.
0x1
ABTREQ
Abort Request
24
1
read-write
abtreq0
No request to abort a command write sequence
0
abtreq1
Request to abort a command write sequence
0x1
8
0x4
0,1,2,3,4,5,6,7
FCCOB%s
Flash Common Command Object Registers
0x10
32
read-write
0
0xFFFFFFFF
CCOBn
CCOBn
0
32
read-write
FMU0TEST
FlashTest
MSF1_B_test
0x40096000
0
0x1000
registers
FSTAT
Flash Status Register
0
32
read-write
0
0xFFFFFFFF
FAIL
Command Fail Flag
0
1
read-write
zz27
Error not detected
0
zz28
Error detected
0x1
CMDABT
Command Abort Flag
2
1
read-only
zz25
No command abort detected
0
zz26
Command abort detected
0x1
PVIOL
Command Protection Violation Flag
4
1
read-write
oneToClear
zz23
No protection violation detected
0
zz24
Protection violation detected
0x1
ACCERR
Command Access Error Flag
5
1
read-write
oneToClear
zz21
No access error detected
0
zz22
Access error detected
0x1
CWSABT
Command Write Sequence Abort Flag
6
1
read-only
zz19
Command write sequence not aborted
0
zz20
Command write sequence aborted
0x1
CCIF
Command Complete Interrupt Flag
7
1
read-write
oneToClear
zz17
Flash command or initialization in progress
0
zz18
Flash command or initialization has completed
0x1
CMDPRT
Command Protection Level
8
2
read-only
zz13
Secure, normal access
0
zz14
Secure, privileged access
0x1
zz15
Nonsecure, normal access
0x2
zz16
Nonsecure, privileged access
0x3
CMDP
Command Protection Status Flag
11
1
read-only
zz11
Command protection level and domain ID are stale
0
zz12
Command protection level (CMDPRT) and domain ID (CMDDID) are set
0x1
CMDDID
Command Domain ID
12
4
read-only
DFDIF
Double Bit Fault Detect Interrupt Flag
16
1
read-only
zz9
Double bit fault not detected during a valid flash read access from the FMC
0
zz10
Double bit fault detected (or FCTRL[FDFD] is set) during a valid flash read access from the FMC
0x1
SALV_USED
Salvage Used for Erase operation
17
1
read-write
zz7
Salvage not used during the last operation
0
zz8
Salvage used during the last erase operation
0x1
PEWEN
Program-Erase Write Enable Control
24
2
read-write
zz3
Writes are not enabled
0
zz4
Writes are enabled for one flash or IFR phrase (phrase programming, sector erase)
0x1
zz5
Writes are enabled for one flash or IFR page (page programming)
0x2
PERDY
Program/Erase Ready Control/Status Flag
31
1
read-write
zz1
Program or sector erase command operation is not stalled
0
zz2
Program or sector erase command operation is stalled
0x1
FCNFG
Flash Configuration Register
0x4
32
read-write
0xFE000000
0xFFFFFFFF
CCIE
Command Complete Interrupt Enable
7
1
read-only
zz37
Command complete interrupt disabled
0
zz38
Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set.
0x1
ERSREQ
Mass Erase (Erase All) Request
8
1
read-only
zz35
No request or request complete
0
zz36
Request to run the Mass Erase operation
0x1
DFDIE
Double Bit Fault Detect Interrupt Enable
16
1
read-only
zz33
Double bit fault detect interrupt disabled
0
zz34
Double bit fault detect interrupt enabled; an interrupt request is generated whenever the FSTAT[DFDIF] flag is set
0x1
ERSIEN0
Erase IFR Sector Enable - Block 0
24
4
read-write
zz31
Block 0 IFR Sector X is protected from erase by ERSSCR command
0
zz32
Block 0 IFR Sector X is not protected from erase by ERSSCR command
0x1
ERSIEN1
Erase IFR Sector Enable - Block 1 (for dual block configs)
28
4
read-write
zz29
Block 1 IFR Sector X is protected from erase by ERSSCR command
0
zz30
Block 1 IFR Sector X is not protected from erase by ERSSCR command
0x1
FCTRL
Flash Control Register
0x8
32
read-write
0x100
0xFFFFFFFF
RWSC
Read Wait-State Control
0
4
read-write
zz45
no additional wait-states are added (single cycle access)
0
zz46
1 additional wait-state is added
0x1
zz47
2 additional wait-states are added
0x2
zz48
3 additional wait-states are added
0x3
zz49
4 additional wait-states are added
0x4
zz50
5 additional wait-states are added
0x5
zz51
6 additional wait-states are added
0x6
zz52
7 additional wait-states are added
0x7
zz53
8 additional wait-states are added
0x8
zz54
9 additional wait-states are added
0x9
zz55
10 additional wait-states are added
0xA
zz56
11 additional wait-states are added
0xB
zz57
12 additional wait-states are added
0xC
zz58
13 additional wait-states are added
0xD
zz59
14 additional wait-states are added
0xE
zz60
15 additional wait-states are added
0xF
LSACTIVE
Low Speed Active Mode
8
1
read-write
zz43
Full speed active mode requested
0
zz44
Low speed active mode requested
0x1
FDFD
Force Double Bit Fault Detect
16
1
read-only
zz41
FSTAT[DFDIF] sets only if a double bit fault is detected during a valid flash read access from the FMC
0
zz42
FSTAT[DFDIF] sets during any valid flash read access from the FMC; an interrupt request is generated if the DFDIE bit is set
0x1
ABTREQ
Abort Request
24
1
read-only
zz39
No request to abort a command write sequence
0
zz40
Request to abort a command write sequence
0x1
FTEST
Flash Test Register
0xC
32
read-only
0x1
0xFFFFFFFF
TMECTL
Test Mode Entry Control
0
1
read-only
zz69
FTEST register always reads 0 and writes to FTEST are ignored
0
zz70
FTEST register is readable and can be written to enable writability of TME
0x1
TMEWR
Test Mode Entry Writable
1
1
read-only
zz67
TME bit is not writable
0
zz68
TME bit is writable
0x1
TME
Test Mode Entry
2
1
read-only
zz65
Test mode entry not requested
0
zz66
Test mode entry requested
0x1
TMODE
Test Mode Status
3
1
read-only
zz63
Test mode not active
0
zz64
Test mode active
0x1
TMELOCK
Test Mode Entry Lock
4
1
read-only
zz61
FTEST register not locked from accepting writes
0
zz62
FTEST register locked from accepting writes
0x1
FCCOB0
Flash Command Control 0 Register
0x10
32
read-write
0
0xFFFFFFFF
CMDCODE
Command code
0
8
read-write
FCCOB1
Flash Command Control 1 Register
0x14
32
read-write
0
0xFFFFFFFF
CMDOPT
Command options
0
8
read-write
FCCOB2
Flash Command Control 2 Register
0x18
32
read-write
0
0xFFFFFFFF
CMDADDR
Command starting address
0
32
read-write
FCCOB3
Flash Command Control 3 Register
0x1C
32
read-write
0
0xFFFFFFFF
CMDADDRE
Command ending address
0
32
read-write
FCCOB4
Flash Command Control 4 Register
0x20
32
read-write
0
0xFFFFFFFF
CMDDATA0
Command data word 0
0
32
read-write
FCCOB5
Flash Command Control 5 Register
0x24
32
read-write
0
0xFFFFFFFF
CMDDATA1
Command data word 1
0
32
read-write
FCCOB6
Flash Command Control 6 Register
0x28
32
read-write
0
0xFFFFFFFF
CMDDATA2
Command data word 2
0
32
read-write
FCCOB7
Flash Command Control 7 Register
0x2C
32
read-write
0
0xFFFFFFFF
CMDDATA3
Command data word 3
0
32
read-write
RESET_STATUS
FMU Initialization Tracking Register
0x100
32
read-write
0
0xFFFFFFFF
ARY_TRIM_DONE
Array Trim Complete
0
1
read-write
zz93
Recall register load operation has not been completed
0
zz94
Recall register load operation has completed
0x1
FMU_PARM_EN
Status of the C0DE_C0DEh check to enable loading of the FMU parameters
1
1
read-write
zz91
C0DE_C0DEh check not attempted
0
zz92
C0DE_C0DEh check completed
0x1
FMU_PARM_DONE
FMU Register Load Complete
2
1
read-write
zz89
FMU registers have not been loaded
0
zz90
FMU registers have been loaded
0x1
SOC_TRIM_EN
Status of the C0DE_C0DEh check to enable loading of the SoC trim settings
3
1
read-write
zz87
C0DE_C0DEh check not attempted
0
zz88
C0DE_C0DEh check completed
0x1
SOC_TRIM_ECC
Status of the C0DE_C0DEh check for enabling ECC decoder during reads of SoC trim settings
4
1
read-write
zz85
C0DE_C0DEh check failed
0
zz86
C0DE_C0DEh check passed
0x1
SOC_TRIM_DONE
SoC Trim Complete
5
1
read-write
zz83
SoC Trim registers have not been updated
0
zz84
All SoC Trim registers have been updated
0x1
RPR_DONE
Array Repair Complete
6
1
read-write
zz81
Repair registers have not been loaded
0
zz82
Repair registers have been loaded
0x1
INIT_DONE
Initialization Done
7
1
read-write
zz79
All initialization steps did not complete
0
zz80
All initialization steps completed
0x1
RST_SF_ERR
ECC Single Fault during Reset Recovery
8
1
read-write
zz77
No single-bit faults detected during initialization
0
zz78
At least one single ECC fault was detected during initialization
0x1
RST_DF_ERR
ECC Double Fault during Reset Recovery
9
1
read-write
zz75
No double-bit faults detected during initialization
0
zz76
Double-bit ECC fault was detected during initialization
0x1
SOC_TRIM_DF_ERR
ECC Double Fault during load of SoC Trim phrases
10
8
read-write
RST_PATCH_LD
Reset Patch Required
18
1
read-write
zz73
No patch required to be loaded during reset
0
zz74
Patch loaded during reset
0x1
RECALL_DATA_MISMATCH
Recall Data Mismatch
19
1
read-write
zz71
Data read towards end of reset matched data read for Recall
0
zz72
Data read towards end of reset did not match data read for recall
0x1
MCTL
FMU Control Register
0x104
32
read-write
0x213048FD
0xFFFFFFFF
COREHLD
Core Hold
0
1
read-write
zz125
CPU access is allowed
0
zz126
CPU access must be blocked
0x1
LSACT_EN
LSACTIVE Feature Enable
2
1
read-write
zz123
LSACTIVE feature disabled completely: FCTRL[LSACTIVE] is forced low and no longer writable, LVE cannot assert at the TSMC array interface.
0
zz124
LSACTIVE feature fully enabled and controllable by SoC and internal UINT SM.
0x1
LSACTWREN
LSACTIVE Write Enable
3
1
read-write
zz121
Unrestricted write access allowed
0
zz122
Write access while CMP set must match CMDDID and CMDPRT
0x1
MASTER_REPAIR_EN
Master Repair Enable
4
1
read-write
zz119
Repair disabled
0
zz120
Repair enable determined by bit 0 of each REPAIR register
0x1
RFCMDEN
RF Active Command Enable Control
5
1
read-write
zz117
Flash commands blocked (CCIF not writable)
0
zz118
Flash commands allowed
0x1
CWSABTEN
Command Write Sequence Abort Enable
6
1
read-write
zz115
CWS abort feature is disabled
0
zz116
CWS abort feature is enabled
0x1
MRGRDDIS
Margin Read Disable
7
1
read-write
zz113
Margin Read Settings are enabled
0
zz114
Margin Read Settings are disabled
0x1
MRGRD0
Margin Read Setting for Program
8
4
read-write
MRGRD1
Margin Read Setting for Erase
12
4
read-write
ERSAACK
Mass Erase (Erase All) Acknowledge
16
1
read-write
zz111
Mass Erase operation is not active (operation has completed or has not started)
0
zz112
Mass Erase operation is active (controller acknowledges that the soc_ersall_req input is asserted and will continue with the operation)
0x1
SCAN_OBS
Scan Observability Control
19
1
read-write
zz109
Normal functional behavior
0
zz110
Enables observation of signals that may otherwise be ATPG untestable
0x1
BIST_CTL
BIST IP Control
20
1
read-write
zz107
BIST IP disabled
0
zz108
BIST IP enabled
0x1
SMWR_CTL
SMWR IP Control
21
1
read-write
zz105
SMWR IP disabled
0
zz106
SMWR IP enabled
0x1
SALV_DIS
Salvage Disable
24
1
read-write
zz103
Salvage enabled (ECC used during erase verify)
0
zz104
Salvage disabled (ECC not used during erase verify)
0x1
SOC_ECC_CTL
SOC ECC Control
25
1
read-write
zz101
ECC is enabled for SOC read access
0
zz102
ECC is disabled for SOC read access
0x1
FMU_ECC_CTL
FMU ECC Control
26
1
read-write
zz99
ECC is enabled for FMU program operations
0
zz100
ECC is disabled for FMU program operations
0x1
BIST_PWR_DIS
BIST Power Mode Disable
29
1
read-write
zz97
BIST DFT logic has full control of SLM and LVE when BIST is enabled (including during commands)
0
zz98
BIST DFT logic has no control of SLM and LVE; power mode RTL is in complete control of SLM and LVE values
0x1
OSC_H
Oscillator control
31
1
read-write
zz95
Use APB clock
0
zz96
Use a known fixed-frequency clock, e.g. 12 MHz
0x1
BSEL_GEN
FMU Block Select Generation Register
0x108
32
read-only
0x301
0xFFFFFFFF
SBSEL_GEN
Generated SBSEL
0
2
read-only
MBSEL_GEN
Generated MBSEL
8
2
read-only
PWR_OPT
Power Mode Options Register
0x10C
32
read-write
0x80FA0032
0xFFFFFFFF
PD_CDIV
Power Down Clock Divider Setting
0
8
read-write
SLM_COUNT
Sleep Recovery Timer Count
16
10
read-write
PD_TIMER_EN
Power Down BIST Timer Enable
31
1
read-write
zz127
BIST timer is not triggered during Power Down recovery
0
zz128
BIST timer is triggered during Power Down recovery (default behavior)
0x1
CMD_CHECK
FMU Command Check Register
0x110
32
read-only
0x40
0xFFFFFFFF
ALIGNFAIL_PHR
Phrase Alignment Fail
0
1
read-only
zz149
The address is phrase-aligned
0
zz150
The address is not phrase-aligned
0x1
ALIGNFAIL_PG
Page Alignment Fail
1
1
read-only
zz147
The address is page-aligned
0
zz148
The address is not page-aligned
0x1
ALIGNFAIL_SCR
Sector Alignment Fail
2
1
read-only
zz145
The address is sector-aligned
0
zz146
The address is not sector-aligned
0x1
ALIGNFAIL_BLK
Block Alignment Fail
3
1
read-only
zz143
The address is block-aligned
0
zz144
The address is not block-aligned
0x1
ADDR_FAIL
Address Fail
4
1
read-only
zz141
The address is within the flash or IFR address space
0
zz142
The address is outside the flash or IFR address space
0x1
IFR_CMD
IFR Command
5
1
read-only
zz139
The command operates on a main flash address
0
zz140
The command operates on an IFR address
0x1
ALL_CMD
All Blocks Command
6
1
read-only
zz137
The command operates on a single flash block
0
zz138
The command operates on all flash blocks
0x1
RANGE_FAIL
Address Range Fail
7
1
read-only
zz135
The address range is valid
0
zz136
The address range is invalid
0x1
SCR_ALIGN_CHK
Sector Alignment Check
8
1
read-only
zz133
No sector alignment check
0
zz134
Sector alignment check
0x1
OPTION_FAIL
Option Check Fail
9
1
read-only
zz131
Option check passes for read command or command is not a read command
0
zz132
Option check fails for read command
0x1
ILLEGAL_CMD
Illegal Command
10
1
read-only
zz129
Command is legal
0
zz130
Command is illegal
0x1
BSEL
FMU Block Select Register
0x120
32
read-write
0x101
0xFFFFFFFF
SBSEL
Slave Block Select
0
2
read-write
MBSEL
Master Block Select
8
2
read-write
MSIZE
FMU Memory Size Register
0x124
32
read-write
0x4
0xFFFFFFFF
MAXADDR0
Size of Flash Block 0
0
8
read-write
FLASH_RD_ADD
Flash Read Address Register
0x128
32
read-write
0
0xFFFFFFFF
FLASH_RD_ADD
Flash Read Address
0
32
read-write
FLASH_STOP_ADD
Flash Stop Address Register
0x130
32
read-write
0
0xFFFFFFFF
FLASH_STOP_ADD
Flash Stop Address
0
32
read-write
FLASH_RD_CTRL
Flash Read Control Register
0x134
32
read-write
0
0xFFFFFFFF
FLASH_RD
Flash Read Enable
0
1
read-write
zz155
Manual flash read not enabled.(default)
0
zz156
Manual flash read enabled
0x1
WIDE_LOAD
Wide Load Enable
1
1
read-write
zz153
Wide load mode disabled (default)
0
zz154
Wide load mode enabled
0x1
SINGLE_RD
Single Flash Read
2
1
read-write
zz151
Normal UINT operation
0
zz152
UINT configured for single cycle reads
0x1
MM_ADDR
Memory Map Address Register
0x138
32
read-write
0
0xFFFFFFFF
MM_ADDR
Memory Map Address
0
32
read-write
MM_WDATA
Memory Map Write Data Register
0x140
32
read-write
0
0xFFFFFFFF
MM_WDATA
Memory Map Write Data
0
32
read-write
MM_CTL
Memory Map Control Register
0x144
32
read-write
0
0xFFFFFFFF
MM_SEL
Register Access Enable
0
1
read-write
MM_RD
Register R/W Control
1
1
read-write
zz161
Write to register
0
zz162
Read register
0x1
BIST_ON
BIST on
2
1
read-write
zz159
BIST enable not forced by user interface
0
zz160
BIST enable control by user interface
0x1
FORCE_SW_CLK
Force Switch Clock
3
1
read-write
zz157
Switch clock not forced on (gated normally)
0
zz158
Switch clock forced on
0x1
UINT_CTL
User Interface Control Register
0x148
32
read-write
0
0xFFFFFFFF
SET_FAIL
Set Fail On Exit
0
1
read-write
zz165
FAIL flag should not be set on command exit (no failure detected)
0
zz166
FAIL flag should be set on command exit
0x1
DBERR
Double-Bit ECC Fault Detect
1
1
read-write
zz163
No double-bit fault detected during UINT-driven read sequence
0
zz164
Double-bit fault detected during UINT-driven read sequence
0x1
RD_DATA0
Read Data 0 Register
0x14C
32
read-write
0
0xFFFFFFFF
RD_DATA0
Read Data 0
0
32
read-write
RD_DATA1
Read Data 1 Register
0x150
32
read-write
0
0xFFFFFFFF
RD_DATA1
Read Data 1
0
32
read-write
RD_DATA2
Read Data 2 Register
0x154
32
read-write
0
0xFFFFFFFF
RD_DATA2
Read Data 2
0
32
read-write
RD_DATA3
Read Data 3 Register
0x158
32
read-write
0
0xFFFFFFFF
RD_DATA3
Read Data 3
0
32
read-write
PARITY
Parity Register
0x15C
32
read-write
0
0xFFFFFFFF
PARITY
Read data [136:128]
0
9
read-write
RD_PATH_CTRL_STATUS
Read Path Control and Status Register
0x160
32
read-write
0
0xFFFFFFFF
RD_CAPT
Read Capture Clock Periods
0
8
read-write
SE_SIZE
SE Clock Periods
8
8
read-write
ECC_ENABLEB
ECC Decoder Control
16
1
read-write
zz189
ECC decoder enabled (default)
0
zz190
ECC decoder disabled
0x1
MISR_EN
MISR Enable
17
1
read-write
zz187
MISR option disabled (default)
0
zz188
MISR option enabled
0x1
CPY_PAR_EN
Copy Parity Enable
18
1
read-write
zz185
Copy parity disabled
0
zz186
Copy parity enabled
0x1
BIST_MUX_TO_SMW
BIST Mux to SMW
19
1
read-write
zz183
BIST drives fields
0
zz184
SMW registers drive fields
0x1
AD_SET
Multi-Cycle Address Setup Time
20
4
read-write
WR_PATH_EN
Write Path Enable
24
1
read-write
zz181
Writes to BIST setting registers driven by MM_WDATA
0
zz182
Writes to BIST setting registers driven by SMW_DIN
0x1
WR_PATH_ECC_EN
Write Path ECC Enable
25
1
read-write
zz179
ECC encoding disabled
0
zz180
ECC encoding enabled
0x1
DBERR_REG
Double-Bit Error
26
1
read-only
zz177
Double-bit fault not detected
0
zz178
Double-bit fault detected on previous UINT flash read
0x1
SBERR_REG
Single-Bit Error
27
1
read-only
zz175
Single-bit fault not detected
0
zz176
Single-bit fault detected on previous UINT flash read
0x1
CPY_PHRASE_EN
Copy Phrase Enable
28
1
read-write
zz173
Copy Flash read data disabled
0
zz174
Copy Flash read data enabled
0x1
SMW_ARRAY1_SMW0_SEL
SMW_ARRAY1_SMW0_SEL
29
1
read-write
zz171
Select block 0
0
zz172
Select block 1
0x1
BIST_ECC_EN
BIST ECC Enable
30
1
read-write
zz169
ECC correction disabled
0
zz170
ECC correction enabled
0x1
LAST_READ
Last Read
31
1
read-write
zz167
Latest read not last in multi-address operation
0
zz168
Latest read last in multi-address operation
0x1
SMW_DIN0
SMW DIN 0 Register
0x164
32
read-write
0
0xFFFFFFFF
SMW_DIN0
SMW DIN 0
0
32
read-write
SMW_DIN1
SMW DIN 1 Register
0x168
32
read-write
0
0xFFFFFFFF
SMW_DIN1
SMW DIN 1
0
32
read-write
SMW_DIN2
SMW DIN 2 Register
0x16C
32
read-write
0
0xFFFFFFFF
SMW_DIN2
SMW DIN 2
0
32
read-write
SMW_DIN3
SMW DIN 3 Register
0x170
32
read-write
0
0xFFFFFFFF
SMW_DIN3
SMW DIN 3
0
32
read-write
SMW_ADDR
SMW Address Register
0x174
32
read-write
0
0xFFFFFFFF
SMW_ADDR
SMW Address
0
32
read-write
SMW_CMD_WAIT
SMW Command and Wait Register
0x178
32
read-write
0
0xFFFFFFFF
CMD
SMW Command
0
3
read-write
zz193
IDLE
0
zz194
ABORT
0x1
zz195
SME2 to one-shot mass erase
0x2
zz196
SME3 to sector erase on selected array
0x3
zz197
SMP1 to program phrase or page on selected array with shot disabled on previously programmed bit
0x4
zz199
SMP2 to program phrase or page on selected array to repair cells of weak program after power loss
0x6
WAIT_EN
SMW Wait Enable
3
1
read-write
zz191
Wait feature disabled
0
zz192
Wait feature enabled
0x1
WAIT_AUTO_SET
SMW Wait Auto Set
4
1
read-write
SMW_STATUS
SMW Status Register
0x17C
32
read-only
0
0xFFFFFFFF
SMW_ERR
SMW Error
0
1
read-only
zz205
Error not detected
0
zz206
Error detected
0x1
SMW_BUSY
SMW Busy
1
1
read-only
zz203
SMW command not active
0
zz204
SMW command is active
0x1
BIST_BUSY
BIST Busy
2
1
read-only
zz201
BIST Command not active
0
zz202
BIST Command is active
0x1
SOCTRIM0_0
SoC Trim Phrase 0 Word 0 Register
0x180
32
read-write
0xFFFFFFFF
0xFFFFFFFF
TRIM0_0
TRIM0_0
0
32
read-write
SOCTRIM0_1
SoC Trim Phrase 0 Word 1 Register
0x184
32
read-write
0xFFFFFFFF
0xFFFFFFFF
TRIM0_1
TRIM0_1
0
32
read-write
SOCTRIM0_2
SoC Trim Phrase 0 Word 2 Register
0x188
32
read-write
0xFFFFFFFF
0xFFFFFFFF
TRIM0_2
TRIM0_2
0
32
read-write
SOCTRIM0_3
SoC Trim Phrase 0 Word 3 Register
0x18C
32
read-write
0xFFFFFFFF
0xFFFFFFFF
TRIM0_3
TRIM0_3
0
32
read-write
SOCTRIM1_0
SoC Trim Phrase 1 Word 0 Register
0x190
32
read-write
0xFFFFFFFF
0xFFFFFFFF
TRIM1_0
TRIM1_0
0
32
read-write
SOCTRIM1_1
SoC Trim Phrase 1 Word 1 Register
0x194
32
read-write
0xFFFFFFFF
0xFFFFFFFF
TRIM1_1
TRIM1_1
0
32
read-write
SOCTRIM1_2
SoC Trim Phrase 1 Word 2 Register
0x198
32
read-write
0xFFFFFFFF
0xFFFFFFFF
TRIM1_2
TRIM1_2
0
32
read-write
SOCTRIM1_3
SoC Trim Phrase 1 Word 3 Register
0x19C
32
read-write
0xFFFFFFFF
0xFFFFFFFF
TRIM1_3
TRIM1_3
0
32
read-write
SOCTRIM2_0
SoC Trim Phrase 2 Word 0 Register
0x1A0
32
read-write
0xFFFFFFFF
0xFFFFFFFF
TRIM2_0
TRIM2_0
0
32
read-write
SOCTRIM2_1
SoC Trim Phrase 2 Word 1 Register
0x1A4
32
read-write
0xFFFFFFFF
0xFFFFFFFF
TRIM2_1
TRIM2_1
0
32
read-write
SOCTRIM2_2
SoC Trim Phrase 2 Word 2 Register
0x1A8
32
read-write
0xFFFFFFFF
0xFFFFFFFF
TRIM2_2
TRIM2_2
0
32
read-write
SOCTRIM2_3
SoC Trim Phrase 2 Word 3 Register
0x1AC
32
read-write
0xFFFFFFFF
0xFFFFFFFF
TRIM2_3
TRIM2_3
0
32
read-write
SOCTRIM3_0
SoC Trim Phrase 3 Word 0 Register
0x1B0
32
read-write
0xFFFFFFFF
0xFFFFFFFF
TRIM3_0
TRIM3_0
0
32
read-write
SOCTRIM3_1
SoC Trim Phrase 3 Word 1 Register
0x1B4
32
read-write
0xFFFFFFFF
0xFFFFFFFF
TRIM3_1
TRIM3_1
0
32
read-write
SOCTRIM3_2
SoC Trim Phrase 3 Word 2 Register
0x1B8
32
read-write
0xFFFFFFFF
0xFFFFFFFF
TRIM3_2
TRIM3_2
0
32
read-write
SOCTRIM3_3
SoC Trim Phrase 3 Word 3 Register
0x1BC
32
read-write
0xFFFFFFFF
0xFFFFFFFF
TRIM3_3
TRIM3_3
0
32
read-write
SOCTRIM4_0
SoC Trim Phrase 4 Word 0 Register
0x1C0
32
read-write
0xFFFFFFFF
0xFFFFFFFF
TRIM4_0
TRIM4_0
0
32
read-write
SOCTRIM4_1
SoC Trim Phrase 4 Word 1 Register
0x1C4
32
read-write
0xFFFFFFFF
0xFFFFFFFF
TRIM4_1
TRIM4_1
0
32
read-write
SOCTRIM4_2
SoC Trim Phrase 4 Word 2 Register
0x1C8
32
read-write
0xFFFFFFFF
0xFFFFFFFF
TRIM4_2
TRIM4_2
0
32
read-write
SOCTRIM4_3
SoC Trim Phrase 4 Word 3 Register
0x1CC
32
read-write
0xFFFFFFFF
0xFFFFFFFF
TRIM4_3
TRIM4_3
0
32
read-write
SOCTRIM5_0
SoC Trim Phrase 5 Word 0 Register
0x1D0
32
read-write
0xFFFFFFFF
0xFFFFFFFF
TRIM5_0
TRIM5_0
0
32
read-write
SOCTRIM5_1
SoC Trim Phrase 5 Word 1 Register
0x1D4
32
read-write
0xFFFFFFFF
0xFFFFFFFF
TRIM5_1
TRIM5_1
0
32
read-write
SOCTRIM5_2
SoC Trim Phrase 5 Word 2 Register
0x1D8
32
read-write
0xFFFFFFFF
0xFFFFFFFF
TRIM5_2
TRIM5_2
0
32
read-write
SOCTRIM5_3
SoC Trim Phrase 5 Word 3 Register
0x1DC
32
read-write
0xFFFFFFFF
0xFFFFFFFF
TRIM5_3
TRIM5_3
0
32
read-write
SOCTRIM6_0
SoC Trim Phrase 6 Word 0 Register
0x1E0
32
read-write
0xFFFFFFFF
0xFFFFFFFF
TRIM6_0
TRIM6_0
0
32
read-write
SOCTRIM6_1
SoC Trim Phrase 6 Word 1 Register
0x1E4
32
read-write
0xFFFFFFFF
0xFFFFFFFF
TRIM6_1
TRIM6_1
0
32
read-write
SOCTRIM6_2
SoC Trim Phrase 6 Word 2 Register
0x1E8
32
read-write
0xFFFFFFFF
0xFFFFFFFF
TRIM6_2
TRIM6_2
0
32
read-write
SOCTRIM6_3
SoC Trim Phrase 6 Word 3 Register
0x1EC
32
read-write
0xFFFFFFFF
0xFFFFFFFF
TRIM6_3
TRIM6_3
0
32
read-write
SOCTRIM7_0
SoC Trim Phrase 7 Word 0 Register
0x1F0
32
read-write
0xFFFFFFFF
0xFFFFFFFF
TRIM7_0
TRIM7_0
0
32
read-write
SOCTRIM7_1
SoC Trim Phrase 7 Word 1 Register
0x1F4
32
read-write
0xFFFFFFFF
0xFFFFFFFF
TRIM7_1
TRIM7_1
0
32
read-write
SOCTRIM7_2
SoC Trim Phrase 7 Word 2 Register
0x1F8
32
read-write
0xFFFFFFFF
0xFFFFFFFF
TRIM7_2
TRIM7_2
0
32
read-write
SOCTRIM7_3
SoC Trim Phrase 7 Word 3 Register
0x1FC
32
read-write
0xFFFFFFFF
0xFFFFFFFF
TRIM7_3
TRIM7_3
0
32
read-write
R_IP_CONFIG
BIST Configuration Register
0x204
32
read-write
0
0xFFFFFFFF
IPSEL0
Block 0 Select Control
0
2
read-write
zz223
Unselect block 0
0
zz224
not used, reserved
0x1
zz225
Enable block 0 test, repair off (default)
0x2
zz226
Enable block 0 test, repair on
0x3
IPSEL1
Block 1 Select Control
2
2
read-write
zz219
Unselect block 1
0
zz220
not used, reserved
0x1
zz221
Enable block 1 test, repair off (default)
0x2
zz222
Enable block 1 test, repair on
0x3
BIST_CDIVL
Clock Divide Scalar for Long Pulse
4
8
read-write
CDIVS
Number of clock cycles to generate short pulse
12
3
read-write
BIST_TVFY
Timer adjust for verify
15
5
read-write
TSTCTL
BIST self-test control
20
2
read-write
zz215
Default, disable both BIST self-test and MISR
0
zz216
Enable BIST self-test mode DOUT from macro will be forced to '0', and disable MISR.
0x1
zz217
Enable MISR
0x2
zz218
Enable both BIST self-test mode and MISR
0x3
DBGCTL
Debug feature control
22
1
read-write
zz213
Default
0
zz214
Enable debug feature to collect failure address and data.
0x1
BIST_CLK_SEL
BIST Clock Select
23
1
read-write
SMWTST
SMWR DOUT Function Control
24
2
read-write
zz209
Default
0
zz210
Enable SMWR self-test mode, DOUT from macro will be forced to all 0
0x1
zz211
Enable SMWR self-test mode, DOUT from macro will be forced to all 1
0x2
ECCEN
BIST ECC Control
26
1
read-write
zz207
Default mode (no ECC encode or decode)
0
zz208
Enable ECC encode/decode
0x1
R_TESTCODE
BIST Test Code Register
0x208
32
read-write
0
0xFFFFFFFF
TESTCODE
Used to store test code information before running TMR-RST/TMRSET BIST command
0
6
read-write
R_DFT_CTRL
BIST DFT Control Register
0x20C
32
read-write
0
0xFFFFFFFF
DFT_XADR
DFT XADR Pattern
0
4
read-write
zz252
XADR fixed, no change at all
0
zz253
XADR increased by 1 after row. For READ operation, XADR increases by 1 after reading the last word of row. For PROG operation, XADR increases by 1 after NVSTR falls.
0x1
zz254
XADR increased for diagonal. For PROG-DIAGONAL operation, XADR is increased to create diagonal pattern.
0x2
zz255
XADR increased by sector. During ERASE operation, XADR increased by number of rows in a sector when NVSTR falls.
0x3
zz256
XADR inversed. XADR is inversed after reading one word or after programming one row when NVSTR falls.
0x4
zz257
XADR increased by 2 after row. For READ operation, XADR is increased by 2 after reading the last word of a row. For PROG operation, XADR is increased by 2 when NVSTR falls.
0x5
zz258
XADR[0] inversed. XADR[0] is inversed after reading one word or after programming one row when NVSTR falls.
0x6
zz259
XADR increased by 1. For READ operations only, XADR increased by 1 after each read cycle.
0x7
zz260
XADR decreased by 1 after row. For READ operations only, XADR is decreased by 1 after YADR decreases to 0.
0x8
zz261
XADR decreased by 1. For READ operations only, XADR is decreased by 1 after each read cycle.
0x9
DFT_YADR
DFT YADR Pattern
4
4
read-write
zz242
YADR fixed, no change at all
0
zz243
YADR for ICKBD. For PROG and READ operations, YADR changed to generate inverse checkerboard pattern.
0x1
zz244
YADR for CKBD. For PROG and READ operations, YADR changed to generate checkerboard pattern.
0x2
zz245
YADR increased by 1. For READ operations, YADR increased by 1 after each read cycle. For PROG operations, YADR increased by 1 after YE falls.
0x3
zz246
YADR increased for diagonal. For PROG-DIAGONAL operation, YADR is increased to create diagonal pattern.
0x4
zz247
YADR inversed. YADR is inversed after reading one word or after programming one word when YE falls.
0x5
zz248
YADR[0] inversed. YADR[0] is inversed after reading one word or after programming one word when YE falls.
0x6
zz249
YADR increased by 1 after last row. For READ operations only, YADR is increased by 1 after XADR reaches last row.
0x7
zz250
YADR decreased by 1. For READ operations only, YADR is decreased by 1 after each read cycle.
0x8
zz251
YADR decreased by 1 after first row. For READ operations only, YADR is decreased by 1 after XADR decreases to 0.
0x9
DFT_DATA
DFT Data Pattern
8
4
read-write
zz232
CKBD pattern. For READ operations only, compare DOUT with checkerboard data pattern for each read cycle.
0
zz233
ICKBD pattern. For READ operations only, compare DOUT with inverse checkerboard data pattern for each read cycle.
0x1
zz234
Diagonal pattern. Used for READ operations only, compare DOUT to diagonal pattern.
0x2
zz235
Fixed data pattern. For READ operations, comparison to DOUT for selected groups; refer to R_ADR_CTRL[GRPSEL] for modules with multiple groups.
0x3
zz236
Random data pattern which will be generated based on the initial seed set in R_DATA; for READ operations, used for DOUT comparison of selected groups. For PROG operations, used to control DIN of selected groups.
0x4
zz237
DOUT based pattern. For READ operations only, DOUT of selected group will be latched in R_DATA. If more than one group is selected in R_ADR_CTRL[GRPSEL], the group with the lower index will be latched.
0x5
zz238
R_DATA based pattern. For READ operations, expected DOUT value of selected groups equals to R_DATA when XADR[0]==YADR[0] or ~R_DATA when XADR[0]!=YADR[0]. For PROG operations, DIN of selected groups equals R_DATA when XADR[0]==YADR[0] or ~R_DATA when XADR[0]!=YADR[0].
0x6
zz239
SCAN-IO pattern. For READ operations, control expected DOUT value of selected groups to SCAN-IO data pattern. For PROG operations, control DIN of selected groups to SCAN-IO data pattern.
0x7
zz240
REPAIR set. For PROG operation to IFR1(7,1) and IFR1(7,2), R_REPAIR0_0 and R_REPAIR0_1 or R_REPAIR1_0 and R_REPAIR1_1 will control DIN. For READ operation on IFR1(7,1) and IFR1(7,2), DOUT will be compared against R_REPAIR0_0 and R_REPAIR0_1 or R_REPAIR1_0 andR_REPAIR1_1. When this option is selected, only one flash block can be selected.
0x8
zz241
REPAIR load. For READ operation only, DOUT from IFR1(7,1) and IFR1(7,2) is loaded to R_REPAIR0 and R_REPAIR1.
0x9
CMP_MASK
Data Compare Mask
12
2
read-write
zz229
Expected data is compared to DOUT
0
zz230
Expected data (only 0s are considered) are compared to DOUT
0x1
zz231
Expected data (only 1s are considered) are compared to DOUT
0x2
DFT_DATA_SRC
DFT Data Source
14
1
read-write
zz227
{R_DATA_CTRL0,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0} is used
0
zz228
{R_DATA_CTRL3,R_DATA_CTRL2_EX[2:0],R_DATA_CTRL2,R_DATA_CTRL1_EX[2:0],R_DATA_CTRL1,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0} is used
0x1
R_ADR_CTRL
BIST Address Control Register
0x210
32
read-write
0
0xFFFFFFFF
GRPSEL
Data Group Select
0
4
read-write
zz270
Select no data
0
zz271
Select data slice [34:0]
0x1
zz272
Select data slice [69:35]
0x2
zz273
Select data slice [104:70]
0x4
zz274
Select data slice [136:105]
0x8
zz275
Select data [136:0]
0xF
XADR
BIST XADR
4
12
read-write
YADR
BIST YADR
16
5
read-write
PROG_ATTR
Program Attribute
21
3
read-write
zz262
One YE pulse will program one data slice group
0
zz263
One YE pulse will program two data slice groups
0x1
zz264
One YE pulse will program three data slice groups (reserved)
0x2
zz265
One YE pulse will program four data slice groups
0x3
zz266
One YE pulse will program five data slice groups (reserved)
0x4
zz267
One YE pulse will program six data slice groups (reserved)
0x5
zz268
One YE pulse will program seven data slice groups (reserved)
0x6
zz269
One YE pulse will program eight data slice groups (reserved)
0x7
R_DATA_CTRL0
BIST Data Control 0 Register
0x214
32
read-write
0
0xFFFFFFFF
DATA0
BIST Data 0 Low
0
32
read-write
R_PIN_CTRL
BIST Pin Control Register
0x218
32
read-write
0
0xFFFFFFFF
MAS1
Mass Erase
0
1
read-write
IFREN
IFR Enable
1
1
read-write
IFREN1
IFR1 Enable
2
1
read-write
REDEN
Redundancy Block Enable
3
1
read-write
LVE
Low Voltage Enable
4
1
read-write
PV
Program Verify Enable
5
1
read-write
EV
Erase Verify Enable
6
1
read-write
WIPGM
Program Current
7
2
read-write
WHV
High Voltage Level
9
4
read-write
WMV
Medium Voltage Level
13
3
read-write
XE
X Address Enable
16
1
read-write
YE
Y Address Enable
17
1
read-write
SE
Sense Amp Enable
18
1
read-write
ERASE
Erase Mode
19
1
read-write
PROG
Program Mode
20
1
read-write
NVSTR
NVM Store
21
1
read-write
SLM
Sleep Mode Enable
22
1
read-write
RECALL
Recall Trim Code
23
1
read-write
HEM
HEM Control
24
1
read-write
R_CNT_LOOP_CTRL
BIST Loop Count Control Register
0x21C
32
read-write
0
0xFFFFFFFF
LOOPCNT
Loop Count Control
0
12
read-write
LOOPOPT
Loop Option
12
3
read-write
zz284
Loop is disabled; selected BIST operation is run once
0
zz285
Loop is enabled; XADR increments by 1 XADR increments by 1 for each new loop. Stops when total loop count meets LOOPCNT+1.
0x1
zz286
Loop is enabled; YADR increments by 1 YADR increments by 1 for each new loop. Stops when total loop count meets LOOPCNT+1.
0x2
zz287
Loop is enabled; XADR increments by 2 XADR increments by 2 for each new loop. Stops when total loop count meets LOOPCNT+1.
0x3
zz288
Loop is enabled; XADR increments by sector XADR increments by 16 for each new loop. Stops when total loop count meets LOOPCNT+1.
0x4
LOOPUNIT
Loop Time Unit
15
3
read-write
zz276
Clock cycles
0
zz277
0.5 usec
0x1
zz278
1 usec
0x2
zz279
10 usec
0x3
zz280
100 usec
0x4
zz281
1 msec
0x5
zz282
10 msec
0x6
zz283
100 msec
0x7
LOOPDLY
Loop Time Delay Scalar
18
7
read-write
R_TIMER_CTRL
BIST Timer Control Register
0x220
32
read-write
0x9A449542
0xFFFFFFFF
TNVSUNIT
Tnvs Time Unit
0
3
read-write
zz321
Clock cycles
0
zz322
0.5 usec
0x1
zz323
1 usec
0x2
zz324
10 usec
0x3
zz325
100 usec
0x4
zz326
1 msec
0x5
zz327
10 msec
0x6
zz328
100 msec
0x7
TNVSDLY
Tnvs Time Delay Scalar
3
4
read-write
TNVHUNIT
Tnvh Time Unit
7
3
read-write
zz313
Clock cycles
0
zz314
0.5 usec
0x1
zz315
1 usec
0x2
zz316
10 usec
0x3
zz317
100 usec
0x4
zz318
1 msec
0x5
zz319
10 msec
0x6
zz320
100 msec
0x7
TNVHDLY
Tnvh Time Delay Scalar
10
4
read-write
TPGSUNIT
Tpgs Time Unit
14
3
read-write
zz305
Clock cycles
0
zz306
0.5 usec
0x1
zz307
1 usec
0x2
zz308
10 usec
0x3
zz309
100 usec
0x4
zz310
1 msec
0x5
zz311
10 msec
0x6
zz312
100 msec
0x7
TPGSDLY
Tpgs Time Delay Scalar
17
4
read-write
TRCVUNIT
Trcv Time Unit
21
3
read-write
zz297
Clock cycles
0
zz298
0.5 usec
0x1
zz299
1 usec
0x2
zz300
10 usec
0x3
zz301
100 usec
0x4
zz302
1 msec
0x5
zz303
10 msec
0x6
zz304
100 msec
0x7
TRCVDLY
Trcv Time Delay Scalar
24
4
read-write
TLVSUNIT
Tlvs Time Unit
28
3
read-write
zz289
Clock cycles
0
zz290
0.5 usec
0x1
zz291
1 usec
0x2
zz292
10 usec
0x3
zz293
100 usec
0x4
zz294
1 msec
0x5
zz295
10 msec
0x6
zz296
100 msec
0x7
TLVSDLY_L
Tlvs Time Delay Scalar Low
31
1
read-write
R_TEST_CTRL
BIST Test Control Register
0x224
32
read-write
0
0xFFFFFFFF
BUSY
BIST Busy Status
0
1
read-only
zz333
BIST is idle
0
zz334
BIST is busy
0x1
DEBUG
BIST Debug Status
1
1
read-only
STATUS0
BIST Status 0
2
1
read-only
zz331
BIST test passed on flash block 0
0
zz332
BIST test failed on flash block 0
0x1
STATUS1
BIST status 1
3
1
read-only
zz329
BIST test passed on flash block 1
0
zz330
BIST test failed on flash block 1
0x1
DEBUGRUN
BIST Continue Debug Run
4
1
read-write
STARTRUN
Run New BIST Operation
5
1
read-write
CMDINDEX
BIST Command Index (code)
6
10
read-write
DISABLE_IP1
BIST Disable IP1
16
1
read-write
R_ABORT_LOOP
BIST Abort Loop Register
0x228
32
read-write
0
0xFFFFFFFF
ABORT_LOOP
Abort Loop
0
1
read-write
zz335
No effect
0
zz336
Abort BIST loop commands and force the loop counter to return to 0x0
0x1
R_ADR_QUERY
BIST Address Query Register
0x22C
32
read-only
0
0xFFFFFFFF
YADRFAIL
Failing YADR
0
5
read-only
XADRFAIL
Failing XADR
5
12
read-only
R_DOUT_QUERY0
BIST DOUT Query 0 Register
0x230
32
read-only
0
0xFFFFFFFF
DOUTFAIL
Failing DOUT Low
0
32
read-only
R_SMW_QUERY
BIST SMW Query Register
0x23C
32
read-only
0
0xFFFFFFFF
SMWLOOP
SMW Total Loop Count
0
10
read-only
SMWLAST
SMW Last Voltage Setting
10
9
read-only
R_SMW_SETTING0
BIST SMW Setting 0 Register
0x240
32
read-write
0xF0B4000
0xFFFFFFFF
SMWPARM0
SMW Parameter Set 0
0
31
read-write
R_SMW_SETTING1
BIST SMW Setting 1 Register
0x244
32
read-write
0x315CE2A
0xFFFFFFFF
SMWPARM1
SMW Parameter Set 1
0
28
read-write
R_SMP_WHV0
BIST SMP WHV Setting 0 Register
0x248
32
read-write
0x77777765
0xFFFFFFFF
SMPWHV0
SMP WHV Parameter Set 0
0
32
read-write
R_SMP_WHV1
BIST SMP WHV Setting 1 Register
0x24C
32
read-write
0x77777777
0xFFFFFFFF
SMPWHV1
SMP WHV Parameter Set 1
0
32
read-write
R_SME_WHV0
BIST SME WHV Setting 0 Register
0x250
32
read-write
0xCCBA9876
0xFFFFFFFF
SMEWHV0
SME WHV Parameter Set 0
0
32
read-write
R_SME_WHV1
BIST SME WHV Setting 1 Register
0x254
32
read-write
0xCCCCCCCC
0xFFFFFFFF
SMEWHV1
SME WHV Parameter Set 1
0
32
read-write
R_SMW_SETTING2
BIST SMW Setting 2 Register
0x258
32
read-write
0xA80151
0xFFFFFFFF
SMWPARM2
SMW Parameter Set 2
0
29
read-write
R_D_MISR0
BIST DIN MISR 0 Register
0x25C
32
read-only
0
0xFFFFFFFF
DATASIG0
Data Signature
0
32
read-only
R_A_MISR0
BIST Address MISR 0 Register
0x260
32
read-only
0
0xFFFFFFFF
ADRSIG0
Address Signature
0
32
read-only
R_C_MISR0
BIST Control MISR 0 Register
0x264
32
read-only
0
0xFFFFFFFF
CTRLSIG0
Control Signature
0
32
read-only
R_SMW_SETTING3
BIST SMW Setting 3 Register
0x268
32
read-write
0x1BE00
0xFFFFFFFF
SMWPARM3
SMW Parameter Set 3
0
17
read-write
R_DATA_CTRL1
BIST Data Control 1 Register
0x26C
32
read-write
0
0xFFFFFFFF
DATA1
BIST Data 1 Low
0
32
read-write
R_DATA_CTRL2
BIST Data Control 2 Register
0x270
32
read-write
0
0xFFFFFFFF
DATA2
BIST Data 2 Low
0
32
read-write
R_DATA_CTRL3
BIST Data Control 3 Register
0x274
32
read-write
0
0xFFFFFFFF
DATA3
BIST Data 3 Low
0
32
read-write
R_REPAIR0_0
BIST Repair 0 for Block 0 Register
0x280
32
read-only
0x1FF
0xFFFFFFFF
RDIS0_0
Control Repair 0 in Block 0.
0
1
read-only
zz337
Repair address is valid
0
zz338
Repair address is not valid
0x1
RADR0_0
XADR for Repair 0 in Block 0
1
8
read-only
R_REPAIR0_1
BIST Repair 1 Block 0 Register
0x284
32
read-only
0x1FF
0xFFFFFFFF
RDIS0_1
Control Repair 1 in Block 0.
0
1
read-only
zz339
Repair address is valid
0
zz340
Repair address is not valid
0x1
RADR0_1
XADR for Repair 1 in Block 0.
1
8
read-only
R_REPAIR1_0
BIST Repair 0 Block 1 Register
0x288
32
read-only
0x1FF
0xFFFFFFFF
RDIS1_0
Control Repair 0 in Block 1.
0
1
read-only
zz341
Repair address is valid
0
zz342
Repair address is not valid
0x1
RADR1_0
XADR for Repair 0 in Block 1.
1
8
read-only
R_REPAIR1_1
BIST Repair 1 Block 1 Register
0x28C
32
read-only
0x1FF
0xFFFFFFFF
RDIS1_1
Control Repair 1 in Block 1.
0
1
read-only
zz343
Repair address is valid
0
zz344
Repair address is not valid
0x1
RADR1_1
XADR for Repair 1 in Block 1.
1
8
read-only
R_DATA_CTRL0_EX
BIST Data Control 0 Extension Register
0x314
32
read-write
0
0xFFFFFFFF
DATA0X
BIST Data 0 High
0
3
read-write
R_TIMER_CTRL_EX
BIST Timer Control Extension Register
0x320
32
read-write
0x1
0xFFFFFFFF
TLVSDLY_H
Tlvs Time Delay Scalar High
0
3
read-write
R_DOUT_QUERY1
BIST DOUT Query 1 Register
0x330
32
read-only
0
0xFFFFFFFF
DOUT
Failing DOUT High
0
3
read-only
R_D_MISR1
BIST DIN MISR 1 Register
0x35C
32
read-only
0
0xFFFFFFFF
DATASIG1
MISR Data Signature High
0
8
read-only
R_A_MISR1
BIST Address MISR 1 Register
0x360
32
read-only
0
0xFFFFFFFF
ADRSIG1
MISR Address Signature High
0
8
read-only
R_C_MISR1
BIST Control MISR 1 Register
0x364
32
read-only
0
0xFFFFFFFF
CTRLSIG1
MISR Control Signature High
0
8
read-only
R_DATA_CTRL1_EX
BIST Data Control 1 Extension Register
0x36C
32
read-write
0
0xFFFFFFFF
DATA1X
BIST Data 1 High
0
3
read-write
R_DATA_CTRL2_EX
BIST Data Control 2 Extension Register
0x370
32
read-write
0
0xFFFFFFFF
DATA2X
BIST Data 2 High
0
3
read-write
R_DATA_CTRL3_EX
BIST Data Control 3 Extension Register
0x374
32
read-write
0
0xFFFFFFFF
DATA3X
BIST Data 3 High
0
3
read-write
SMW_TIMER_OPTION
SMW Timer Option Register
0x400
32
read-write
0
0xFFFFFFFF
SMW_CDIVL
Clock Divide Scalar for Long Pulse
0
8
read-write
SMW_TVFY
Timer Adjust for Verify
8
5
read-write
SMW_SETTING_OPTION0
SMW Setting Option 0 Register
0x404
32
read-write
0xF0B4000
0xFFFFFFFF
MV_INIT
Medium Voltage Level Select Initial
14
3
read-write
MV_END
Medium Voltage Level Select Final
17
3
read-write
MV_MISC
Medium Voltage Control Misc
20
4
read-write
IPGM_INIT
Program Current Control Initial
24
2
read-write
IPGM_END
Program Current Control Final
26
2
read-write
IPGM_MISC
Program Current Control Misc
28
3
read-write
SMW_SETTING_OPTION2
SMW Setting Option 2 Register
0x408
32
read-write
0xA80151
0xFFFFFFFF
THVS_CTRL
Thvs control
0
3
read-write
TRCV_CTRL
Trcv Control
3
3
read-write
XTRA_ERS
Number of Post Shots for SME
6
2
read-write
XTRA_PGM
Number of Post Shots for SMP
8
2
read-write
WHV_CNTR
WHV Counter
10
8
read-write
POST_TERS
Post Ters Time
18
3
read-write
zz361
50 usec
0
zz362
100 usec
0x1
zz363
200 usec
0x2
zz364
300 usec
0x3
zz365
500 usec
0x4
zz366
1 msec
0x5
zz367
1.5 msec
0x6
zz368
2 msec
0x7
POST_TPGM
Post Tpgm Time
21
2
read-write
zz357
1 usec
0
zz358
2 usec
0x1
zz359
4 usec
0x2
zz360
8 usec
0x3
VFY_OPT
Verify Option
23
2
read-write
zz353
Skip verify for post shot only, verify for all other shots
0
zz354
Skip verify for the 1st and post shots
0x1
zz355
Skip the 1st, 2nd, and post shots
0x2
zz356
Skip verify for all shots
0x3
TPGM_OPT
Tpgm Option
25
2
read-write
zz349
Fixed Tpgm for all shots, except post shot
0
zz350
Increase Tpgm option by 1 for each loop until Tpgm reaches 4 usec
0x1
zz351
Increase Tpgm option by 1 for each loop until Tpgm reaches 8 usec
0x2
zz352
Unused
0x3
MASK0_OPT
MASK0_OPT
27
1
read-write
zz347
Mask programmed bits passing PV until extra shot
0
zz348
Always program bits even if they pass PV
0x1
DIS_PRER
Disable pre-PV Read before First Program Shot
28
1
read-write
zz345
Enable pre-PV read before first program shot
0
zz346
Disable pre-PV read before first program shot
0x1
SMW_SETTING_OPTION3
SMW Setting Option 3 Register
0x40C
32
read-write
0x1BD00
0xFFFFFFFF
HEM_WHV_CNTR
WHV_COUNTER for HEM-erase Cycle
0
8
read-write
HEM_MAX_ERS
HEM Max Erase Shot Count
8
9
read-write
SMW_SMP_WHV_OPTION0
SMW SMP WHV Option 0 Register
0x410
32
read-write
0x77777765
0xFFFFFFFF
SMP_WHV_OPT0
Smart Program WHV Option Low
0
32
read-write
SMW_SME_WHV_OPTION0
SMW SME WHV Option 0 Register
0x414
32
read-write
0xCCBA9876
0xFFFFFFFF
SME_WHV_OPT0
Smart Erase WHV Option Low
0
32
read-write
SMW_SETTING_OPTION1
SMW Setting Option 1 Register
0x418
32
read-write
0x2958E2A
0xFFFFFFFF
TERS_CTRL0
Ters Control
0
3
read-write
zz397
50 usec
0
zz398
100 usec
0x1
zz399
200 usec
0x2
zz400
300 usec
0x3
zz401
500 usec
0x4
zz402
1 msec
0x5
zz403
1.5 msec
0x6
zz404
2 msec
0x7
TPGM_CTRL
Tpgm Control
3
2
read-write
zz393
1 usec
0
zz394
2 usec
0x1
zz395
4 usec
0x2
zz396
8 usec
0x3
TNVS_CTRL
Tnvs Control
5
3
read-write
zz385
5 usec
0
zz386
8 usec
0x1
zz387
11 usec
0x2
zz388
14 usec
0x3
zz389
17 usec
0x4
zz390
20 usec
0x5
zz391
23 usec
0x6
zz392
26 usec
0x7
TNVH_CTRL
Tnvh Control
8
3
read-write
zz377
2 usec
0
zz378
2.5 usec
0x1
zz379
3 usec
0x2
zz380
3.5 usec
0x3
zz381
4 usec
0x4
zz382
4.5 usec
0x5
zz383
5 usec
0x6
zz384
5.5 usec
0x7
TPGS_CTRL
Tpgs Control
11
3
read-write
zz369
1 usec
0
zz370
2 usec
0x1
zz371
3 usec
0x2
zz372
4 usec
0x3
zz373
5 usec
0x4
zz374
6 usec
0x5
zz375
7 usec
0x6
zz376
8 usec
0x7
MAX_ERASE
Number of Erase Shots
14
9
read-write
MAX_PROG
Number of Program Shots
23
5
read-write
SMW_SMP_WHV_OPTION1
SMW SMP WHV Option 1 Register
0x41C
32
read-write
0x77777777
0xFFFFFFFF
SMP_WHV_OPT1
Smart Program WHV Option High
0
32
read-write
SMW_SME_WHV_OPTION1
SMW SME WHV Option 1 Register
0x420
32
read-write
0xCCCCCCCC
0xFFFFFFFF
SME_WHV_OPT1
Smart Erase WHV Option High
0
32
read-write
REPAIR0_0
FMU Repair 0 Block 0 Register
0x500
32
read-write
0x1FF
0xFFFFFFFF
RDIS0_0
RDIS0_0
0
1
read-write
zz405
Repair address is valid
0
zz406
Repair address is not valid
0x1
RADR0_0
RADR0_0
1
8
read-write
REPAIR0_1
FMU Repair 1 Block 0 Register
0x504
32
read-write
0x1FF
0xFFFFFFFF
RDIS0_1
RDIS0_1
0
1
read-write
zz407
Repair address is valid
0
zz408
Repair address is not valid
0x1
RADR0_1
RADR0_1
1
8
read-write
REPAIR1_0
FMU Repair 0 Block 1 Register
0x508
32
read-write
0x1FF
0xFFFFFFFF
RDIS1_0
RDIS1_0
0
1
read-write
zz409
Repair address is valid
0
zz410
Repair address is not valid
0x1
RADR1_0
RADR1_0
1
8
read-write
REPAIR1_1
FMU Repair 1 Block 1 Register
0x50C
32
read-write
0x1FF
0xFFFFFFFF
RDIS1_1
RDIS1_1
0
1
read-write
zz411
Repair address is valid
0
zz412
Repair address is not valid
0x1
RADR1_1
RADR1_1
1
8
read-write
SMW_HB_SIGNALS
SMW HB Signals Register
0x600
32
read-write
0x8
0xFFFFFFFF
SMW_ARRAY
SMW Region Select
0
3
read-write
zz425
Main array
0
zz426
IFR space only or main (and REDEN space) with IFR space for mass erase
0x1
zz427
IFR1 space
0x2
zz428
REDEN space
0x4
USER_IFREN1
IFR1 Enable
3
1
read-write
zz423
IFREN1 input to the flash array is driven LOW
0
zz424
IFREN1 input to the flash array is driven HIGH
0x1
USER_PV
Program Verify
4
1
read-write
zz421
PV input to the flash array is driven LOW
0
zz422
PV input to the flash array is driven HIGH
0x1
USER_EV
Erase Verify
5
1
read-write
zz419
EV input to the flash array is driven LOW
0
zz420
EV input to the flash array is driven HIGH
0x1
USER_IFREN
IFR Enable
6
1
read-write
zz417
IFREN input to the flash array is driven LOW
0
zz418
IFREN input to the flash array is driven HIGH
0x1
USER_REDEN
Repair Read Enable
7
1
read-write
zz415
REDEN input to the flash array is driven LOW
0
zz416
REDEN input to the flash array is driven HIGH
0x1
USER_HEM
High Endurance Enable
8
1
read-write
zz413
HEM input to SMW / BIST PIN_CTRL[24] is driven LOW
0
zz414
HEM input to SMW / BIST PIN_CTRL[24] is driven HIGH
0x1
BIST_DUMP_CTRL
BIST Datadump Control Register
0x604
32
read-write
0x10000
0xFFFFFFFF
BIST_DONE
BIST Done
16
1
read-write
zz439
The BIST (or data dump) is running
0
zz440
The BIST (or data dump) has completed
0x1
BIST_FAIL
BIST Fail
17
1
read-write
zz437
The last BIST operation completed successfully (or could not fail)
0
zz438
The last BIST operation failed
0x1
DATADUMP
Data Dump Enable
18
1
read-write
DATADUMP_TRIG
Data Dump Trigger
19
1
read-write
DATADUMP_PATT
Data Dump Pattern Select
20
2
read-write
zz433
All ones
0
zz434
All zeroes
0x1
zz435
Checkerboard
0x2
zz436
Inverse checkerboard
0x3
DATADUMP_MRGEN
Data Dump Margin Enable
22
1
read-write
zz431
Normal read pulse shape
0
zz432
Margin read pulse shape
0x1
DATADUMP_MRGTYPE
Data Dump Margin Type
23
1
read-write
zz429
DIN method used
0
zz430
TM method used
0x1
ATX_PIN_CTRL
ATX Pin Control Register
0x60C
32
read-write
0
0xFFFFFFFF
TM_TO_ATX
TM to ATX
0
8
read-write
zz441
TM[0] to ATX0
0x1
zz442
TM[1] to ATX0
0x2
zz443
TM[2] to ATX0
0x4
zz444
TM[3] to ATX0
0x8
zz445
TM[0] to ATX1
0x10
zz446
TM[1] to ATX1
0x20
zz447
TM[2] to ATX1
0x40
zz448
TM[3] to ATX1
0x80
FAILCNT
Fail Count Register
0x610
32
read-write
0
0xFFFFFFFF
FAILCNT
Fail Count
0
32
read-write
PGM_PULSE_CNT0
Block 0 Program Pulse Count Register
0x614
32
read-write
0
0xFFFFFFFF
PGM_CNT0
Program Pulse Count
0
32
read-write
PGM_PULSE_CNT1
Block 1 Program Pulse Count Register
0x618
32
read-write
0
0xFFFFFFFF
PGM_CNT1
Program Pulse Count
0
32
read-write
ERS_PULSE_CNT
Erase Pulse Count Register
0x61C
32
read-write
0
0xFFFFFFFF
ERS_CNT0
Block 0 Erase Pulse Count
0
16
read-write
ERS_CNT1
Block 1 Erase Pulse Count
16
16
read-write
MAX_PULSE_CNT
Maximum Pulse Count Register
0x620
32
read-write
0
0xFFFFFFFF
LAST_PCNT
Last SMW Operation's Pulse Count
0
9
read-write
MAX_ERS_CNT
Maximum Erase Pulse Count
16
9
read-write
MAX_PGM_CNT
Maximum Program Pulse Count
27
5
read-write
PORT_CTRL
Port Control Register
0x624
32
read-write
0
0xFFFFFFFF
BDONE_SEL
BIST Done Select
0
2
read-write
zz453
Select internal bist_done signal from current module instantiation
0
zz454
Select ipt_bist_fail signal from current module instantiation
0x1
zz455
Select ipt_bist_done signal from other module instantiation
0x2
zz456
Select AND of internal bist_done signal from current module instantiation with ipt_bist_done signal from other module instantiation
0x3
BSDO_SEL
BIST Serial Data Output Select
2
2
read-write
zz449
Select internal bist_sdo signal from current module instantiation
0
zz450
Select ipt_bist_done signal from current module instantiation
0x1
zz451
Select ipt_bist_sdo signal from other module instantiation
0x2
zz452
Select ipt_bist_done signal from other module instantiation
0x3
LPI2C0
Low-Power Inter-Integrated Circuit
LPI2C
0x4009A000
0
0x17C
registers
LPI2C0
26
VERID
Version ID
0
32
read-only
0x1030003
0xFFFFFFFF
FEATURE
Feature Specification Number
0
16
read-only
MASTER_ONLY
Controller only, with standard feature set
0x2
MASTER_AND_SLAVE
Controller and target, with standard feature set
0x3
MINOR
Minor Version Number
16
8
read-only
MAJOR
Major Version Number
24
8
read-only
PARAM
Parameter
0x4
32
read-only
0x202
0xFFFFFFFF
MTXFIFO
Controller Transmit FIFO Size
0
4
read-only
MRXFIFO
Controller Receive FIFO Size
8
4
read-only
MCR
Controller Control
0x10
32
read-write
0
0xFFFFFFFF
MEN
Controller Enable
0
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
RST
Software Reset
1
1
read-write
NOT_RESET
No effect
0
RESET
Reset
0x1
DOZEN
Doze Mode Enable
2
1
read-write
ENABLED
Enable
0
DISABLED
Disable
0x1
DBGEN
Debug Enable
3
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
RTF
Reset Transmit FIFO
8
1
read-write
NO_EFFECT
No effect
0
RESET
Reset transmit FIFO
0x1
RRF
Reset Receive FIFO
9
1
read-write
NO_EFFECT
No effect
0
RESET
Reset receive FIFO
0x1
MSR
Controller Status
0x14
32
read-write
0x1
0xFFFFFFFF
TDF
Transmit Data Flag
0
1
read-only
DISABLED
Transmit data not requested
0
ENABLED
Transmit data requested
0x1
RDF
Receive Data Flag
1
1
read-only
DISABLED
Receive data not ready
0
ENABLED
Receive data ready
0x1
EPF
End Packet Flag
8
1
read-write
oneToClear
read
INT_NO
No Stop or repeated Start generated
0
INT_YES
Stop or repeated Start generated
0x1
SDF
Stop Detect Flag
9
1
read-write
oneToClear
read
INT_NO
No Stop condition generated
0
INT_YES
Stop condition generated
0x1
NDF
NACK Detect Flag
10
1
read-write
oneToClear
read
INT_NO
No unexpected NACK detected
0
INT_YES
Unexpected NACK detected
0x1
ALF
Arbitration Lost Flag
11
1
read-write
oneToClear
read
INT_NO
Controller did not lose arbitration
0
INT_YES
Controller lost arbitration
0x1
FEF
FIFO Error Flag
12
1
read-write
oneToClear
read
INT_NO
No FIFO error
0
INT_YES
FIFO error
0x1
PLTF
Pin Low Timeout Flag
13
1
read-write
oneToClear
read
INT_NO
Pin low timeout did not occur
0
INT_YES
Pin low timeout occurred
0x1
DMF
Data Match Flag
14
1
read-write
oneToClear
read
INT_NO
Matching data not received
0
INT_YES
Matching data received
0x1
STF
Start Flag
15
1
read-write
oneToClear
read
INT_NO
Start condition not detected
0
INT_YES
Start condition detected
0x1
MBF
Controller Busy Flag
24
1
read-only
IDLE
Idle
0
BUSY
Busy
0x1
BBF
Bus Busy Flag
25
1
read-only
IDLE
Idle
0
BUSY
Busy
0x1
MIER
Controller Interrupt Enable
0x18
32
read-write
0
0xFFFFFFFF
TDIE
Transmit Data Interrupt Enable
0
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
RDIE
Receive Data Interrupt Enable
1
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
EPIE
End Packet Interrupt Enable
8
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
SDIE
Stop Detect Interrupt Enable
9
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
NDIE
NACK Detect Interrupt Enable
10
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
ALIE
Arbitration Lost Interrupt Enable
11
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
FEIE
FIFO Error Interrupt Enable
12
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
PLTIE
Pin Low Timeout Interrupt Enable
13
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
DMIE
Data Match Interrupt Enable
14
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
STIE
Start Interrupt Enable
15
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
MDER
Controller DMA Enable
0x1C
32
read-write
0
0xFFFFFFFF
TDDE
Transmit Data DMA Enable
0
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
RDDE
Receive Data DMA Enable
1
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
MCFGR0
Controller Configuration 0
0x20
32
read-write
0
0xFFFFFFFF
HREN
Host Request Enable
0
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
HRPOL
Host Request Polarity
1
1
read-write
ACTIVE_LOW
Active low
0
ACTIVE_HIGH
Active high
0x1
HRSEL
Host Request Select
2
1
read-write
DISABLED
Host request input is pin HREQ
0
ENABLED
Host request input is input trigger
0x1
HRDIR
Host Request Direction
3
1
read-write
INPUT
HREQ pin is input (for LPI2C controller)
0
OUTPUT
HREQ pin is output (for LPI2C target)
0x1
CIRFIFO
Circular FIFO Enable
8
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
RDMO
Receive Data Match Only
9
1
read-write
DISABLED
Received data is stored in the receive FIFO
0
ENABLED
Received data is discarded unless MSR[DMF] is set
0x1
RELAX
Relaxed Mode
16
1
read-write
NORMAL_TRANSFER
Normal transfer
0
RELAXED_TRANSFER
Relaxed transfer
0x1
ABORT
Abort Transfer
17
1
read-write
DISABLED
Normal transfer
0
ENABLED
Abort existing transfer and do not start a new one
0x1
MCFGR1
Controller Configuration 1
0x24
32
read-write
0
0xFFFFFFFF
PRESCALE
Prescaler
0
3
read-write
DIVIDE_BY_1
Divide by 1
0
DIVIDE_BY_2
Divide by 2
0x1
DIVIDE_BY_4
Divide by 4
0x2
DIVIDE_BY_8
Divide by 8
0x3
DIVIDE_BY_16
Divide by 16
0x4
DIVIDE_BY_32
Divide by 32
0x5
DIVIDE_BY_64
Divide by 64
0x6
DIVIDE_BY_128
Divide by 128
0x7
AUTOSTOP
Automatic Stop Generation
8
1
read-write
DISABLED
No effect
0
ENABLED
Stop automatically generated
0x1
IGNACK
Ignore NACK
9
1
read-write
DISABLED
No effect
0
ENABLED
Treat a received NACK as an ACK
0x1
TIMECFG
Timeout Configuration
10
1
read-write
IF_SCL_LOW
SCL
0
IF_SCL_OR_SDA_LOW
SCL or SDA
0x1
STOPCFG
Stop Configuration
11
1
read-write
ANY_STOP
Any Stop condition
0
LAST_STOP
Last Stop condition
0x1
STARTCFG
Start Configuration
12
1
read-write
BOTH_I2C_AND_LPI2C_IDLE
Sets when both I2C bus and LPI2C controller are idle
0
I2C_IDLE
Sets when I2C bus is idle
0x1
MATCFG
Match Configuration
16
3
read-write
DISABLED
Match is disabled
0
FIRST_DATA_WORD_EQUALS_MATCH0_OR_MATCH1
Match is enabled: first data word equals MDMR[MATCH0] OR MDMR[MATCH1]
0x2
ANY_DATA_WORD_EQUALS_MATCH0_OR_MATCH1
Match is enabled: any data word equals MDMR[MATCH0] OR MDMR[MATCH1]
0x3
FIRST_DATA_WORD_MATCH0_AND_SECOND_DATA_WORD_MATCH1
Match is enabled: (first data word equals MDMR[MATCH0]) AND (second data word equals MDMR[MATCH1)
0x4
ANY_DATA_WORD_MATCH0_NEXT_DATA_WORD_MATCH1
Match is enabled: (any data word equals MDMR[MATCH0]) AND (next data word equals MDMR[MATCH1)
0x5
FIRST_DATA_WORD_AND_MATCH1_EQUALS_MATCH0_AND_MATCH1
Match is enabled: (first data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1])
0x6
ANY_DATA_WORD_AND_MATCH1_EQUALS_MATCH0_AND_MATCH1
Match is enabled: (any data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1])
0x7
PINCFG
Pin Configuration
24
3
read-write
OPEN_DRAIN_2_PIN
Two-pin open drain mode
0
OUTPUT_2_PIN_ONLY
Two-pin output only mode (Ultra-Fast mode)
0x1
PUSH_PULL_2_PIN
Two-pin push-pull mode
0x2
PUSH_PULL_4_PIN
Four-pin push-pull mode
0x3
OPEN_DRAIN_2_PIN_W_LPI2C_SLAVE
Two-pin open-drain mode with separate LPI2C target
0x4
OUTPUT_2_PIN_ONLY_W_LPI2C_SLAVE
Two-pin output only mode (Ultra-Fast mode) with separate LPI2C target
0x5
PUSH_PULL_2_PIN_W_LPI2C_SLAVE
Two-pin push-pull mode with separate LPI2C target
0x6
PUSH_PULL_4_PIN_W_LPI2C_SLAVE
Four-pin push-pull mode (inverted outputs)
0x7
MCFGR2
Controller Configuration 2
0x28
32
read-write
0
0xFFFFFFFF
BUSIDLE
Bus Idle Timeout
0
12
read-write
FILTSCL
Glitch Filter SCL
16
4
read-write
FILTSDA
Glitch Filter SDA
24
4
read-write
MCFGR3
Controller Configuration 3
0x2C
32
read-write
0
0xFFFFFFFF
PINLOW
Pin Low Timeout
8
12
read-write
MDMR
Controller Data Match
0x40
32
read-write
0
0xFFFFFFFF
MATCH0
Match 0 Value
0
8
read-write
MATCH1
Match 1 Value
16
8
read-write
MCCR0
Controller Clock Configuration 0
0x48
32
read-write
0
0xFFFFFFFF
CLKLO
Clock Low Period
0
6
read-write
CLKHI
Clock High Period
8
6
read-write
SETHOLD
Setup Hold Delay
16
6
read-write
DATAVD
Data Valid Delay
24
6
read-write
MCCR1
Controller Clock Configuration 1
0x50
32
read-write
0
0xFFFFFFFF
CLKLO
Clock Low Period
0
6
read-write
CLKHI
Clock High Period
8
6
read-write
SETHOLD
Setup Hold Delay
16
6
read-write
DATAVD
Data Valid Delay
24
6
read-write
MFCR
Controller FIFO Control
0x58
32
read-write
0
0xFFFFFFFF
TXWATER
Transmit FIFO Watermark
0
2
read-write
RXWATER
Receive FIFO Watermark
16
2
read-write
MFSR
Controller FIFO Status
0x5C
32
read-only
0
0xFFFFFFFF
TXCOUNT
Transmit FIFO Count
0
3
read-only
RXCOUNT
Receive FIFO Count
16
3
read-only
MTDR
Controller Transmit Data
0x60
32
write-only
0
0xFFFFFFFF
DATA
Transmit Data
0
8
write-only
CMD
Command Data
8
3
write-only
TRANSMIT_DATA_7_THROUGH_0
Transmit the value in DATA[7:0]
0
RECEIVE_DATA_7_THROUGH_0_PLUS_ONE
Receive (DATA[7:0] + 1) bytes
0x1
GENERATE_STOP_CONDITION
Generate Stop condition on I2C bus
0x2
RECEIVE_AND_DISCARD_DATA_7_THROUGH_0_PLUS_ONE
Receive and discard (DATA[7:0] + 1) bytes
0x3
GENERATE_START_AND_TRANSMIT_ADDRESS_IN_DATA_7_THROUGH_0
Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0]
0x4
GENERATE_START_AND_TRANSMIT_ADDRESS_IN_DATA_7_THROUGH_0_EXPECT_NACK
Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] (this transfer expects a NACK to be returned)
0x5
GENERATE_START_AND_TRANSMIT_ADDRESS_IN_DATA_7_THROUGH_0_USING_HIGH_SPEED_MODE
Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode
0x6
GENERATE_START_AND_TRANSMIT_ADDRESS_IN_DATA_7_THROUGH_0_USING_HIGH_SPEED_MODE_EXPECT_NACK
Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode (this transfer expects a NACK to be returned)
0x7
MRDR
Controller Receive Data
0x70
32
read-only
0x4000
0xFFFFFFFF
DATA
Receive Data
0
8
read-only
RXEMPTY
Receive Empty
14
1
read-only
NOT_EMPTY
Not empty
0
EMPTY
Empty
0x1
MRDROR
Controller Receive Data Read Only
0x78
32
read-only
0x4000
0xFFFFFFFF
DATA
Receive Data
0
8
read-only
RXEMPTY
RX Empty
14
1
read-only
NOT_EMPTY
Not empty
0
EMPTY
Empty
0x1
SCR
Target Control
0x110
32
read-write
0
0xFFFFFFFF
SEN
Target Enable
0
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
RST
Software Reset
1
1
read-write
NOT_RESET
Not reset
0
RESET
Reset
0x1
FILTEN
Filter Enable
4
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
FILTDZ
Filter Doze Enable
5
1
read-write
FILTER_ENABLED
Enable
0
FILTER_DISABLED
Disable
0x1
RTF
Reset Transmit FIFO
8
1
read-write
NO_EFFECT
No effect
0
NOW_EMPTY
STDR is now empty
0x1
RRF
Reset Receive FIFO
9
1
read-write
NO_EFFECT
No effect
0
NOW_EMPTY
SRDR is now empty
0x1
SSR
Target Status
0x114
32
read-write
0
0xFFFFFFFF
TDF
Transmit Data Flag
0
1
read-only
NO_FLAG
Transmit data not requested
0
FLAG
Transmit data is requested
0x1
RDF
Receive Data Flag
1
1
read-only
NOT_READY
Not ready
0
READY
Ready
0x1
AVF
Address Valid Flag
2
1
read-only
NOT_VALID
Not valid
0
VALID
Valid
0x1
TAF
Transmit ACK Flag
3
1
read-only
NOT_REQUIRED
Not required
0
REQUIRED
Required
0x1
RSF
Repeated Start Flag
8
1
read-write
oneToClear
read
INT_NO
No repeated Start detected
0
INT_YES
Repeated Start detected
0x1
SDF
Stop Detect Flag
9
1
read-write
oneToClear
read
INT_NO
No Stop detected
0
INT_YES
Stop detected
0x1
BEF
Bit Error Flag
10
1
read-write
oneToClear
read
INT_NO
No bit error occurred
0
INT_YES
Bit error occurred
0x1
FEF
FIFO Error Flag
11
1
read-write
oneToClear
read
INT_NO
No FIFO error
0
INT_YES
FIFO error
0x1
AM0F
Address Match 0 Flag
12
1
read-only
NO_FLAG
ADDR0 matching address not received
0
FLAG
ADDR0 matching address received
0x1
AM1F
Address Match 1 Flag
13
1
read-only
NO_FLAG
Matching address not received
0
FLAG
Matching address received
0x1
GCF
General Call Flag
14
1
read-only
NO_FLAG
General call address disabled or not detected
0
FLAG
General call address detected
0x1
SARF
SMBus Alert Response Flag
15
1
read-only
NO_FLAG
Disabled or not detected
0
FLAG
Enabled and detected
0x1
SBF
Target Busy Flag
24
1
read-only
IDLE
Idle
0
BUSY
Busy
0x1
BBF
Bus Busy Flag
25
1
read-only
IDLE
Idle
0
BUSY
Busy
0x1
SIER
Target Interrupt Enable
0x118
32
read-write
0
0xFFFFFFFF
TDIE
Transmit Data Interrupt Enable
0
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
RDIE
Receive Data Interrupt Enable
1
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
AVIE
Address Valid Interrupt Enable
2
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
TAIE
Transmit ACK Interrupt Enable
3
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
RSIE
Repeated Start Interrupt Enable
8
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
SDIE
Stop Detect Interrupt Enable
9
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
BEIE
Bit Error Interrupt Enable
10
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
FEIE
FIFO Error Interrupt Enable
11
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
AM0IE
Address Match 0 Interrupt Enable
12
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
AM1IE
Address Match 1 Interrupt Enable
13
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
GCIE
General Call Interrupt Enable
14
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
SARIE
SMBus Alert Response Interrupt Enable
15
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
SDER
Target DMA Enable
0x11C
32
read-write
0
0xFFFFFFFF
TDDE
Transmit Data DMA Enable
0
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
RDDE
Receive Data DMA Enable
1
1
read-write
DISABLED
Disable DMA request
0
ENABLED
Enable DMA request
0x1
AVDE
Address Valid DMA Enable
2
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
RSDE
Repeated Start DMA Enable
8
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
SDDE
Stop Detect DMA Enable
9
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
SCFGR0
Target Configuration 0
0x120
32
read-write
0
0xFFFFFFFF
RDREQ
Read Request
0
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
RDACK
Read Acknowledge Flag
1
1
read-only
NOT_ACKNOWLEDGED
Read Request not acknowledged
0
ACKNOWLEDGED
Read Request acknowledged
0x1
SCFGR1
Target Configuration 1
0x124
32
read-write
0
0xFFFFFFFF
ADRSTALL
Address SCL Stall
0
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
RXSTALL
RX SCL Stall
1
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
TXDSTALL
Transmit Data SCL Stall
2
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
ACKSTALL
ACK SCL Stall
3
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
RXNACK
Receive NACK
4
1
read-write
SET_BY_TXNACK
ACK or NACK always determined by STAR[TXNACK]
0
ALWAYS_GENERATED_ON_ADDRESS_OR_RECEIVE_DATA_OVERRUN
NACK always generated on address overrun or receive data overrun, otherwise ACK or NACK is determined by STAR[TXNACK]
0x1
GCEN
General Call Enable
8
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
SAEN
SMBus Alert Enable
9
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
TXCFG
Transmit Flag Configuration
10
1
read-write
ASSERTS_DURING_SLAVE_TRANSMIT_TRANSFER_WHEN_TX_DATA_EMPTY
MSR[TDF] is set only during a target-transmit transfer when STDR is empty
0
ASSERTS_WHEN_TX_DATA_EMPTY
MSR[TDF] is set whenever STDR is empty
0x1
RXCFG
Receive Data Configuration
11
1
read-write
RETURNS_RECEIVED_DATA_AND_CLEARS_RX_DATA_FLAG
Return received data, clear MSR[RDF]
0
WHEN_ADDRESS_VALID_FLAG_SET_RETURNS_ADDRESS_STATUS_AND_CLEARS_ADDRESS_VALID_FLAG
Return SASR and clear SSR[AVF] when SSR[AVF] is set, return received data and clear MSR[RDF] when SSR[AFV] is not set
0x1
IGNACK
Ignore NACK
12
1
read-write
ENDS_TRANSFER_ON_NACK
End transfer on NACK
0
DOES_NOT_END_TRANSFER_ON_NACK
Do not end transfer on NACK
0x1
HSMEN
HS Mode Enable
13
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
ADDRCFG
Address Configuration
16
3
read-write
ADDRESS_MATCH0_7_BIT
Address match 0 (7-bit)
0
ADDRESS_MATCH0_10_BIT
Address match 0 (10-bit)
0x1
ADDRESS_MATCH0_7_BIT_OR_ADDRESS_MATCH1_7_BIT
Address match 0 (7-bit) or address match 1 (7-bit)
0x2
ADDRESS_MATCH0_10_BIT_OR_ADDRESS_MATCH1_10_BIT
Address match 0 (10-bit) or address match 1 (10-bit)
0x3
ADDRESS_MATCH0_7_BIT_OR_ADDRESS_MATCH1_10_BIT
Address match 0 (7-bit) or address match 1 (10-bit)
0x4
ADDRESS_MATCH0_10_BIT_OR_ADDRESS_MATCH1_7_BIT
Address match 0 (10-bit) or address match 1 (7-bit)
0x5
FROM_ADDRESS_MATCH0_7_BIT_TO_ADDRESS_MATCH1_7_BIT
From address match 0 (7-bit) to address match 1 (7-bit)
0x6
FROM_ADDRESS_MATCH0_10_BIT_TO_ADDRESS_MATCH1_10_BIT
From address match 0 (10-bit) to address match 1 (10-bit)
0x7
RXALL
Receive All
24
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
RSCFG
Repeated Start Configuration
25
1
read-write
ANY_REPEATED_START_AFTER_ADDRESS_MATCH
Any repeated Start condition following an address match
0
ANY_REPEATED_START
Any repeated Start condition
0x1
SDCFG
Stop Detect Configuration
26
1
read-write
ANY_STOP_AFTER_ADDRESS_MATCH
Any Stop condition following an address match
0
ANY_STOP
Any Stop condition
0x1
SCFGR2
Target Configuration 2
0x128
32
read-write
0
0xFFFFFFFF
CLKHOLD
Clock Hold Time
0
4
read-write
DATAVD
Data Valid Delay
8
6
read-write
FILTSCL
Glitch Filter SCL
16
4
read-write
FILTSDA
Glitch Filter SDA
24
4
read-write
SAMR
Target Address Match
0x140
32
read-write
0
0xFFFFFFFF
ADDR0
Address 0 Value
1
10
read-write
ADDR1
Address 1 Value
17
10
read-write
SASR
Target Address Status
0x150
32
read-only
0x4000
0xFFFFFFFF
RADDR
Received Address
0
11
read-only
ANV
Address Not Valid
14
1
read-only
VALID
Valid
0
NOT_VALID
Not valid
0x1
STAR
Target Transmit ACK
0x154
32
read-write
0
0xFFFFFFFF
TXNACK
Transmit NACK
0
1
read-write
TRANSMIT_ACK
Transmit ACK
0
TRANSMIT_NACK
Transmit NACK
0x1
STDR
Target Transmit Data
0x160
32
write-only
0
0xFFFFFFFF
DATA
Transmit Data
0
8
write-only
SRDR
Target Receive Data
0x170
32
read-only
0x4000
0xFFFFFFFF
DATA
Received Data
0
8
read-only
RADDR
Received Address
8
3
read-only
RXEMPTY
Receive Empty
14
1
read-only
NOT_EMPTY
Not empty
0
EMPTY
Empty
0x1
SOF
Start of Frame
15
1
read-only
NOT_FIRST_DATA_WORD
Not first
0
FIRST_DATA_WORD
First
0x1
SRDROR
Target Receive Data Read Only
0x178
32
read-only
0x4000
0xFFFFFFFF
DATA
Receive Data
0
8
read-only
RADDR
Received Address
8
3
read-only
RXEMPTY
Receive Empty
14
1
read-only
NOT_EMPTY
Not empty
0
EMPTY
Empty
0x1
SOF
Start of Frame
15
1
read-only
NOT_FIRST_DATA_WORD
Not the first
0
FIRST_DATA_WORD
First
0x1
LPSPI0
Low-Power Serial Peripheral Interface
LPSPI
LPSPI
0x4009C000
0
0x800
registers
LPSPI0
28
VERID
Version ID
0
32
read-only
0x2000004
0xFFFFFFFF
FEATURE
Module Identification Number
0
16
read-only
STANDARD
Standard feature set supporting a 32-bit shift register.
0x4
MINOR
Minor Version Number
16
8
read-only
MAJOR
Major Version Number
24
8
read-only
PARAM
Parameter
0x4
32
read-only
0x40202
0xFFFFFFFF
TXFIFO
Transmit FIFO Size
0
8
read-only
RXFIFO
Receive FIFO Size
8
8
read-only
PCSNUM
PCS Number
16
8
read-only
CR
Control
0x10
32
read-write
0
0xFFFFFFFF
MEN
Module Enable
0
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
RST
Software Reset
1
1
read-write
NOT_RESET
Not reset
0
RESET
Reset
0x1
DBGEN
Debug Enable
3
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
RTF
Reset Transmit FIFO
8
1
write-only
NO_EFFECT
No effect
0
TXFIFO_RST
Reset
0x1
RRF
Reset Receive FIFO
9
1
write-only
NO_EFFECT
No effect
0
RXFIFO_RST
Reset
0x1
SR
Status
0x14
32
read-write
0x1
0xFFFFFFFF
TDF
Transmit Data Flag
0
1
read-only
TXDATA_NOT_REQST
Transmit data not requested
0
TXDATA_REQST
Transmit data requested
0x1
RDF
Receive Data Flag
1
1
read-only
NOTREADY
Receive data not ready
0
READY
Receive data ready
0x1
WCF
Word Complete Flag
8
1
read-write
oneToClear
read
NOT_COMPLETED
Not complete
0
COMPLETED
Complete
0x1
FCF
Frame Complete Flag
9
1
read-write
oneToClear
read
NOT_COMPLETED
Not complete
0
COMPLETED
Complete
0x1
TCF
Transfer Complete Flag
10
1
read-write
oneToClear
read
NOT_COMPLETED
Not complete
0
COMPLETED
Complete
0x1
TEF
Transmit Error Flag
11
1
read-write
oneToClear
read
NO_UNDERRUN
No underrun
0
UNDERRUN
Underrun
0x1
REF
Receive Error Flag
12
1
read-write
oneToClear
read
NOT_OVERFLOWED
No overflow
0
OVERFLOWED
Overflow
0x1
DMF
Data Match Flag
13
1
read-write
oneToClear
read
NO_MATCH
No match
0
MATCH
Match
0x1
MBF
Module Busy Flag
24
1
read-only
IDLE
LPSPI is idle
0
BUSY
LPSPI is busy
0x1
IER
Interrupt Enable
0x18
32
read-write
0
0xFFFFFFFF
TDIE
Transmit Data Interrupt Enable
0
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
RDIE
Receive Data Interrupt Enable
1
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
WCIE
Word Complete Interrupt Enable
8
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
FCIE
Frame Complete Interrupt Enable
9
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
TCIE
Transfer Complete Interrupt Enable
10
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
TEIE
Transmit Error Interrupt Enable
11
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
REIE
Receive Error Interrupt Enable
12
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
DMIE
Data Match Interrupt Enable
13
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
DER
DMA Enable
0x1C
32
read-write
0
0xFFFFFFFF
TDDE
Transmit Data DMA Enable
0
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
RDDE
Receive Data DMA Enable
1
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
FCDE
Frame Complete DMA Enable
9
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
CFGR0
Configuration 0
0x20
32
read-write
0
0xFFFFFFFF
HREN
Host Request Enable
0
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
HRPOL
Host Request Polarity
1
1
read-write
DISABLED
Active high
0
ENABLED
Active low
0x1
HRSEL
Host Request Select
2
1
read-write
HREQPIN
HREQ pin
0
INPUT_TRIGGER
Input trigger
0x1
HRDIR
Host Request Direction
3
1
read-write
INPUT
Input
0
OUTPUT
Output
0x1
CIRFIFO
Circular FIFO Enable
8
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
RDMO
Receive Data Match Only
9
1
read-write
STORED
Disable
0
DISCARDED
Enable
0x1
CFGR1
Configuration 1
0x24
32
read-write
0
0xFFFFFFFF
MASTER
Master Mode
0
1
read-write
SLAVE_MODE
Slave mode
0
MASTER_MODE
Master mode
0x1
SAMPLE
Sample Point
1
1
read-write
ON_SCK_EDGE
SCK edge
0
ON_DELAYED_SCK_EDGE
Delayed SCK edge
0x1
AUTOPCS
Automatic PCS
2
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
NOSTALL
No Stall
3
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
PARTIAL
Partial Enable
4
1
read-write
DISCARDED
Discard
0
STORED
Store
0x1
PCSPOL
Peripheral Chip Select Polarity
8
4
read-write
DISCARDED
Active low
0
STORED
Active high
0x1
MATCFG
Match Configuration
16
3
read-write
DISABLED
Match is disabled
0
ENABLED_FIRSTDATAMATCH
Match first data word with compare word
0x2
ENABLED_ANYDATAMATCH
Match any data word with compare word
0x3
ENABLED_DATAMATCH_100
Sequential match, first data word
0x4
ENABLED_DATAMATCH_101
Sequential match, any data word
0x5
ENABLED_DATAMATCH_110
Match first data word (masked) with compare word (masked)
0x6
ENABLED_DATAMATCH_111
Match any data word (masked) with compare word (masked)
0x7
PINCFG
Pin Configuration
24
2
read-write
SIN_IN_SOUT_OUT
SIN is used for input data; SOUT is used for output data
0
SIN_BOTH_IN_OUT
SIN is used for both input and output data; only half-duplex serial transfers are supported
0x1
SOUT_BOTH_IN_OUT
SOUT is used for both input and output data; only half-duplex serial transfers are supported
0x2
SOUT_IN_SIN_OUT
SOUT is used for input data; SIN is used for output data
0x3
OUTCFG
Output Configuration
26
1
read-write
RETAIN_LASTVALUE
Retain last value
0
TRISTATED
3-stated
0x1
PCSCFG
Peripheral Chip Select Configuration
27
1
read-write
CHIP_SELECT
PCS[3:2] configured for chip select function
0
HALFDUPLEX4BIT
PCS[3:2] configured for half-duplex 4-bit transfers (PCS[3:2] = DATA[3:2])
0x1
DMR0
Data Match 0
0x30
32
read-write
0
0xFFFFFFFF
MATCH0
Match 0 Value
0
32
read-write
DMR1
Data Match 1
0x34
32
read-write
0
0xFFFFFFFF
MATCH1
Match 1 Value
0
32
read-write
CCR
Clock Configuration
0x40
32
read-write
0
0xFFFFFFFF
SCKDIV
SCK Divider
0
8
read-write
DBT
Delay Between Transfers
8
8
read-write
PCSSCK
PCS-to-SCK Delay
16
8
read-write
SCKPCS
SCK-to-PCS Delay
24
8
read-write
CCR1
Clock Configuration 1
0x44
32
read-write
0
0xFFFFFFFF
SCKSET
SCK Setup
0
8
read-write
SCKHLD
SCK Hold
8
8
read-write
PCSPCS
PCS to PCS Delay
16
8
read-write
SCKSCK
SCK Inter-Frame Delay
24
8
read-write
FCR
FIFO Control
0x58
32
read-write
0
0xFFFFFFFF
TXWATER
Transmit FIFO Watermark
0
2
read-write
RXWATER
Receive FIFO Watermark
16
2
read-write
FSR
FIFO Status
0x5C
32
read-only
0
0xFFFFFFFF
TXCOUNT
Transmit FIFO Count
0
3
read-only
RXCOUNT
Receive FIFO Count
16
3
read-only
TCR
Transmit Command
0x60
32
read-write
0x1F
0xFFFFFFFF
FRAMESZ
Frame Size
0
12
read-write
WIDTH
Transfer Width
16
2
read-write
ONEBIT
1-bit transfer
0
TWOBIT
2-bit transfer
0x1
FOURBIT
4-bit transfer
0x2
TXMSK
Transmit Data Mask
18
1
read-write
NORMAL
Normal transfer
0
MASK
Mask transmit data
0x1
RXMSK
Receive Data Mask
19
1
read-write
NORMAL
Normal transfer
0
MASK
Mask receive data
0x1
CONTC
Continuing Command
20
1
read-write
START
Command word for start of new transfer
0
CONTINUE
Command word for continuing transfer
0x1
CONT
Continuous Transfer
21
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
BYSW
Byte Swap
22
1
read-write
DISABLED
Disable byte swap
0
ENABLED
Enable byte swap
0x1
LSBF
LSB First
23
1
read-write
MSB_FIRST
MSB first
0
LSB_FIRST
LSB first
0x1
PCS
Peripheral Chip Select
24
2
read-write
TX_PCS0
Transfer using PCS[0]
0
TX_PCS1
Transfer using PCS[1]
0x1
TX_PCS2
Transfer using PCS[2]
0x2
TX_PCS3
Transfer using PCS[3]
0x3
PRESCALE
Prescaler Value
27
3
read-write
DIVIDEBY1
Divide by 1
0
DIVIDEBY2
Divide by 2
0x1
DIVIDEBY4
Divide by 4
0x2
DIVIDEBY8
Divide by 8
0x3
DIVIDEBY16
Divide by 16
0x4
DIVIDEBY32
Divide by 32
0x5
DIVIDEBY64
Divide by 64
0x6
DIVIDEBY128
Divide by 128
0x7
CPHA
Clock Phase
30
1
read-write
CAPTURED
Captured
0
CHANGED
Changed
0x1
CPOL
Clock Polarity
31
1
read-write
INACTIVE_LOW
Inactive low
0
INACTIVE_HIGH
Inactive high
0x1
TDR
Transmit Data
0x64
32
write-only
0
0xFFFFFFFF
DATA
Transmit Data
0
32
write-only
RSR
Receive Status
0x70
32
read-only
0x2
0xFFFFFFFF
SOF
Start of Frame
0
1
read-only
NEXT_DATAWORD
Subsequent data word
0
FIRST_DATAWORD
First data word
0x1
RXEMPTY
RX FIFO Empty
1
1
read-only
NOT_EMPTY
Not empty
0
EMPTY
Empty
0x1
RDR
Receive Data
0x74
32
read-only
0
0xFFFFFFFF
DATA
Receive Data
0
32
read-only
RDROR
Receive Data Read Only
0x78
32
read-only
0
0xFFFFFFFF
DATA
Receive Data
0
32
read-only
TCBR
Transmit Command Burst
0x3FC
32
write-only
0
0xFFFFFFFF
DATA
Command Data
0
32
write-only
128
0x4
TDBR[%s]
Transmit Data Burst
0x400
32
write-only
0
0xFFFFFFFF
DATA
Data
0
32
write-only
128
0x4
RDBR[%s]
Receive Data Burst
0x600
32
read-only
0
0xFFFFFFFF
DATA
Data
0
32
read-only
LPSPI1
Low-Power Serial Peripheral Interface
LPSPI
0x4009D000
0
0x800
registers
LPSPI1
29
LPUART0
LPUART
LPUART
LPUART
0x4009F000
0
0x34
registers
LPUART0
31
VERID
Version ID
0
32
read-only
0x4040003
0xFFFFFFFF
FEATURE
Feature Identification Number
0
16
read-only
STANDARD
Standard feature set
0x1
MODEM
Standard feature set with MODEM and IrDA support
0x3
MINOR
Minor Version Number
16
8
read-only
MAJOR
Major Version Number
24
8
read-only
PARAM
Parameter
0x4
32
read-only
0x202
0xFFFFFFFF
TXFIFO
Transmit FIFO Size
0
8
read-only
RXFIFO
Receive FIFO Size
8
8
read-only
GLOBAL
Global
0x8
32
read-write
0
0xFFFFFFFF
RST
Software Reset
1
1
read-write
NO_EFFECT
Not reset
0
RESET
Reset
0x1
PINCFG
Pin Configuration
0xC
32
read-write
0
0xFFFFFFFF
TRGSEL
Trigger Select
0
2
read-write
DISABLED
Input trigger disabled
0
TRG_RXD
Input trigger used instead of the RXD pin input
0x1
TRG_CTS
Input trigger used instead of the CTS_B pin input
0x2
TRG_TXD
Input trigger used to modulate the TXD pin output, which (after TXINV configuration) is internally ANDed with the input trigger
0x3
BAUD
Baud Rate
0x10
32
read-write
0xF000004
0xFFFFFFFF
SBR
Baud Rate Modulo Divisor
0
13
read-write
SBNS
Stop Bit Number Select
13
1
read-write
ONE
One stop bit
0
TWO
Two stop bits
0x1
RXEDGIE
RX Input Active Edge Interrupt Enable
14
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
LBKDIE
LIN Break Detect Interrupt Enable
15
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
RESYNCDIS
Resynchronization Disable
16
1
read-write
RESYNC
Enable
0
NO_RESYNC
Disable
0x1
BOTHEDGE
Both Edge Sampling
17
1
read-write
DISABLED
Rising edge
0
ENABLED
Both rising and falling edges
0x1
MATCFG
Match Configuration
18
2
read-write
ADDR_MATCH
Address match wake-up
0
IDLE_MATCH
Idle match wake-up
0x1
ONOFF_MATCH
Match on and match off
0x2
RWU_MATCH
Enables RWU on data match and match on or off for the transmitter CTS input
0x3
RIDMAE
Receiver Idle DMA Enable
20
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
RDMAE
Receiver Full DMA Enable
21
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
TDMAE
Transmitter DMA Enable
23
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
OSR
Oversampling Ratio
24
5
read-write
DEFAULT
Results in an OSR of 16
0
OSR_4
Results in an OSR of 4 (requires BAUD[BOTHEDGE] to be 1)
0x3
OSR_5
Results in an OSR of 5 (requires BAUD[BOTHEDGE] to be 1)
0x4
OSR_6
Results in an OSR of 6 (requires BAUD[BOTHEDGE] to be 1)
0x5
OSR_7
Results in an OSR of 7 (requires BAUD[BOTHEDGE] to be 1)
0x6
OSR_8
Results in an OSR of 8
0x7
OSR_9
Results in an OSR of 9
0x8
OSR_10
Results in an OSR of 10
0x9
OSR_11
Results in an OSR of 11
0xA
OSR_12
Results in an OSR of 12
0xB
OSR_13
Results in an OSR of 13
0xC
OSR_14
Results in an OSR of 14
0xD
OSR_15
Results in an OSR of 15
0xE
OSR_16
Results in an OSR of 16
0xF
OSR_17
Results in an OSR of 17
0x10
OSR_18
Results in an OSR of 18
0x11
OSR_19
Results in an OSR of 19
0x12
OSR_20
Results in an OSR of 20
0x13
OSR_21
Results in an OSR of 21
0x14
OSR_22
Results in an OSR of 22
0x15
OSR_23
Results in an OSR of 23
0x16
OSR_24
Results in an OSR of 24
0x17
OSR_25
Results in an OSR of 25
0x18
OSR_26
Results in an OSR of 26
0x19
OSR_27
Results in an OSR of 27
0x1A
OSR_28
Results in an OSR of 28
0x1B
OSR_29
Results in an OSR of 29
0x1C
OSR_30
Results in an OSR of 30
0x1D
OSR_31
Results in an OSR of 31
0x1E
OSR_32
Results in an OSR of 32
0x1F
M10
10-Bit Mode Select
29
1
read-write
DISABLED
Receiver and transmitter use 7-bit to 9-bit data characters
0
ENABLED
Receiver and transmitter use 10-bit data characters
0x1
MAEN2
Match Address Mode Enable 2
30
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
MAEN1
Match Address Mode Enable 1
31
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
STAT
Status
0x14
32
read-write
0xC00000
0xFFFFFFFF
LBKFE
LIN Break Flag Enable
0
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
AME
Address Mark Enable
1
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
MA2F
Match 2 Flag
14
1
read-write
oneToClear
read
NOMATCH
Not equal to MA2
0
MATCH
Equal to MA2
0x1
MA1F
Match 1 Flag
15
1
read-write
oneToClear
read
NOMATCH
Not equal to MA1
0
MATCH
Equal to MA1
0x1
PF
Parity Error Flag
16
1
read-write
oneToClear
read
NOPARITY
No parity error detected
0
PARITY
Parity error detected
0x1
FE
Framing Error Flag
17
1
read-write
oneToClear
read
NOERROR
No framing error detected (this does not guarantee that the framing is correct)
0
ERROR
Framing error detected
0x1
NF
Noise Flag
18
1
read-write
oneToClear
read
NONOISE
No noise detected
0
NOISE
Noise detected
0x1
OR
Receiver Overrun Flag
19
1
read-write
oneToClear
read
NO_OVERRUN
No overrun
0
OVERRUN
Receive overrun (new LPUART data is lost)
0x1
IDLE
Idle Line Flag
20
1
read-write
oneToClear
read
NOIDLE
Idle line detected
0
IDLE
Idle line not detected
0x1
RDRF
Receive Data Register Full Flag
21
1
read-only
NO_RXDATA
Equal to or less than watermark
0
RXDATA
Greater than watermark
0x1
TC
Transmission Complete Flag
22
1
read-only
ACTIVE
Transmitter active
0
COMPLETE
Transmitter idle
0x1
TDRE
Transmit Data Register Empty Flag
23
1
read-only
TXDATA
Greater than watermark
0
NO_TXDATA
Equal to or less than watermark
0x1
RAF
Receiver Active Flag
24
1
read-only
IDLE
Idle, waiting for a start bit
0
ACTIVE
Receiver active (RXD pin input not idle)
0x1
LBKDE
LIN Break Detection Enable
25
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
BRK13
Break Character Generation Length
26
1
read-write
SHORT
9 to 13 bit times
0
LONG
12 to 15 bit times
0x1
RWUID
Receive Wake Up Idle Detect
27
1
read-write
IDLE_NOTSET
STAT[IDLE] does not become 1
0
IDLE_SET
STAT[IDLE] becomes 1
0x1
RXINV
Receive Data Inversion
28
1
read-write
NOT_INVERTED
Inverted
0
INVERTED
Not inverted
0x1
MSBF
MSB First
29
1
read-write
LSB_FIRST
LSB
0
MSB_FIRST
MSB
0x1
RXEDGIF
RXD Pin Active Edge Interrupt Flag
30
1
read-write
oneToClear
read
NO_EDGE
Not occurred
0
EDGE
Occurred
0x1
LBKDIF
LIN Break Detect Interrupt Flag
31
1
read-write
oneToClear
read
NOT_DETECTED
Not detected
0
DETECTED
Detected
0x1
CTRL
Control
0x18
32
read-write
0
0xFFFFFFFF
PT
Parity Type
0
1
read-write
EVEN
Even parity
0
ODD
Odd parity
0x1
PE
Parity Enable
1
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
ILT
Idle Line Type Select
2
1
read-write
FROM_START
After the start bit
0
FROM_STOP
After the stop bit
0x1
WAKE
Receiver Wake-Up Method Select
3
1
read-write
IDLE
Idle
0
MARK
Mark
0x1
M
9-Bit Or 8-Bit Mode Select
4
1
read-write
DATA8
8-bit
0
DATA9
9-bit
0x1
RSRC
Receiver Source Select
5
1
read-write
NO_EFFECT
Internal Loopback mode
0
ONEWIRE
Single-wire mode
0x1
DOZEEN
Doze Mode
6
1
read-write
ENABLED
Enable
0
DISABLED
Disable
0x1
LOOPS
Loop Mode Select
7
1
read-write
NOFFECT
Normal operation: RXD and TXD use separate pins
0
LOOPBACK
Loop mode or Single-Wire mode
0x1
IDLECFG
Idle Configuration
8
3
read-write
IDLE_1
1
0
IDLE_2
2
0x1
IDLE_4
4
0x2
IDLE_8
8
0x3
IDLE_16
16
0x4
IDLE_32
32
0x5
IDLE_64
64
0x6
IDLE_128
128
0x7
M7
7-Bit Mode Select
11
1
read-write
NO_EFFECT
8-bit to 10-bit
0
DATA7
7-bit
0x1
MA2IE
Match 2 (MA2F) Interrupt Enable
14
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
MA1IE
Match 1 (MA1F) Interrupt Enable
15
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
SBK
Send Break
16
1
read-write
NO_EFFECT
Normal transmitter operation
0
TX_BREAK
Queue break character(s) to be sent
0x1
RWU
Receiver Wake-Up Control
17
1
read-write
NO_EFFECT
Normal receiver operation
0
RX_WAKEUP
LPUART receiver in standby, waiting for a wake-up condition
0x1
RE
Receiver Enable
18
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
TE
Transmitter Enable
19
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
ILIE
Idle Line Interrupt Enable
20
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
RIE
Receiver Interrupt Enable
21
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
TCIE
Transmission Complete Interrupt Enable
22
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
TIE
Transmit Interrupt Enable
23
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
PEIE
Parity Error Interrupt Enable
24
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
FEIE
Framing Error Interrupt Enable
25
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
NEIE
Noise Error Interrupt Enable
26
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
ORIE
Overrun Interrupt Enable
27
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
TXINV
Transmit Data Inversion
28
1
read-write
NOT_INVERTED
Not inverted
0
INVERTED
Inverted
0x1
TXDIR
TXD Pin Direction in Single-Wire Mode
29
1
read-write
TX_INPUT
Input
0
TX_OUTPUT
Output
0x1
R9T8
Receive Bit 9 Transmit Bit 8
30
1
read-write
R8T9
Receive Bit 8 Transmit Bit 9
31
1
read-write
DATA
Data
0x1C
32
read-write
0x1000
0xFFFFFFFF
R0T0
Read receive FIFO bit 0 or write transmit FIFO bit 0
0
1
read-write
R1T1
Read receive FIFO bit 1 or write transmit FIFO bit 1
1
1
read-write
R2T2
Read receive FIFO bit 2 or write transmit FIFO bit 2
2
1
read-write
R3T3
Read receive FIFO bit 3 or write transmit FIFO bit 3
3
1
read-write
R4T4
Read receive FIFO bit 4 or write transmit FIFO bit 4
4
1
read-write
R5T5
Read receive FIFO bit 5 or write transmit FIFO bit 5
5
1
read-write
R6T6
Read receive FIFO bit 6 or write transmit FIFO bit 6
6
1
read-write
R7T7
Read receive FIFO bit 7 or write transmit FIFO bit 7
7
1
read-write
R8T8
Read receive FIFO bit 8 or write transmit FIFO bit 8
8
1
read-write
R9T9
Read receive FIFO bit 9 or write transmit FIFO bit 9
9
1
read-write
LINBRK
LIN Break
10
1
read-only
NO_BREAK
Not detected
0
BREAK
Detected
0x1
IDLINE
Idle Line
11
1
read-only
NO_IDLE
Not idle
0
IDLE
Idle
0x1
RXEMPT
Receive Buffer Empty
12
1
read-only
NOT_EMPTY
Valid data
0
EMPTY
Invalid data and empty
0x1
FRETSC
Frame Error Transmit Special Character
13
1
read-write
NO_ERROR
Received without a frame error on reads or transmits a normal character on writes
0
ERROR
Received with a frame error on reads or transmits an idle or break character on writes
0x1
PARITYE
Parity Error
14
1
read-only
NO_PARITY
Received without a parity error
0
PARITY
Received with a parity error
0x1
NOISY
Noisy Data Received
15
1
read-only
NO_NOISE
Received without noise
0
NOISE
Received with noise
0x1
MATCH
Match Address
0x20
32
read-write
0
0xFFFFFFFF
MA1
Match Address 1
0
10
read-write
MA2
Match Address 2
16
10
read-write
MODIR
MODEM IrDA
0x24
32
read-write
0
0xFFFFFFFF
TXCTSE
Transmitter CTS Enable
0
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
TXRTSE
Transmitter RTS Enable
1
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
TXRTSPOL
Transmitter RTS Polarity
2
1
read-write
LOW
Active low
0
HIGH
Active high
0x1
RXRTSE
Receiver RTS Enable
3
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
TXCTSC
Transmit CTS Configuration
4
1
read-write
START
Sampled at the start of each character
0
IDLE
Sampled when the transmitter is idle
0x1
TXCTSSRC
Transmit CTS Source
5
1
read-write
CTS
The CTS_B pin
0
MATCH
An internal connection to the receiver address match result
0x1
RTSWATER
Receive RTS Configuration
8
2
read-write
TNP
Transmitter Narrow Pulse
16
2
read-write
ONE_SAMPLE
1 / OSR
0
TWO_SAMPLE
2 / OSR
0x1
THREE_SAMPLE
3 / OSR
0x2
FOUR_SAMPLE
4 / OSR
0x3
IREN
IR Enable
18
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
FIFO
FIFO
0x28
32
read-write
0xC00011
0xFFFFFFFF
RXFIFOSIZE
Receive FIFO Buffer Depth
0
3
read-only
FIFO_1
1
0
FIFO_4
4
0x1
FIFO_8
8
0x2
FIFO_16
16
0x3
FIFO_32
32
0x4
FIFO_64
64
0x5
FIFO_128
128
0x6
FIFO_256
256
0x7
RXFE
Receive FIFO Enable
3
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
TXFIFOSIZE
Transmit FIFO Buffer Depth
4
3
read-only
FIFO_1
1
0
FIFO_4
4
0x1
FIFO_8
8
0x2
FIFO_16
16
0x3
FIFO_32
32
0x4
FIFO_64
64
0x5
FIFO_128
128
0x6
FIFO_256
256
0x7
TXFE
Transmit FIFO Enable
7
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
RXUFE
Receive FIFO Underflow Interrupt Enable
8
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
TXOFE
Transmit FIFO Overflow Interrupt Enable
9
1
read-write
DISABLED
Disable
0
ENABLED
Enable
0x1
RXIDEN
Receiver Idle Empty Enable
10
3
read-write
DISABLED
Disable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle
0
IDLE_1
Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for one character
0x1
IDLE_2
Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for two characters
0x2
IDLE_4
Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for four characters
0x3
IDLE_8
Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for eight characters
0x4
IDLE_16
Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 16 characters
0x5
IDLE_32
Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 32 characters
0x6
IDLE_64
Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 64 characters
0x7
RXFLUSH
Receive FIFO Flush
14
1
read-write
NO_EFFECT
No effect
0
RXFIFO_RST
All data flushed out
0x1
TXFLUSH
Transmit FIFO Flush
15
1
read-write
NO_EFFECT
No effect
0
TXFIFO_RST
All data flushed out
0x1
RXUF
Receiver FIFO Underflow Flag
16
1
read-write
oneToClear
read
NO_UNDERFLOW
No underflow
0
UNDERFLOW
Underflow
0x1
TXOF
Transmitter FIFO Overflow Flag
17
1
read-write
oneToClear
read
NO_OVERFLOW
No overflow
0
OVERFLOW
Overflow
0x1
RXEMPT
Receive FIFO Or Buffer Empty
22
1
read-only
NOT_EMPTY
Not empty
0
EMPTY
Empty
0x1
TXEMPT
Transmit FIFO Or Buffer Empty
23
1
read-only
NOT_EMPTY
Not empty
0
EMPTY
Empty
0x1
WATER
Watermark
0x2C
32
read-write
0
0xFFFFFFFF
TXWATER
Transmit Watermark
0
2
read-write
TXCOUNT
Transmit Counter
8
3
read-only
RXWATER
Receive Watermark
16
2
read-write
RXCOUNT
Receive Counter
24
3
read-only
DATARO
Data Read-Only
0x30
32
read-only
0x1000
0xFFFFFFFF
DATA
Receive Data
0
16
read-only
LPUART1
LPUART
LPUART
0x400A0000
0
0x34
registers
LPUART1
32
LPUART2
LPUART
LPUART
0x400A1000
0
0x34
registers
LPUART2
33
USB0
USBFS
USB
0x400A4000
0
0x15D
registers
USB0
36
PERID
Peripheral ID
0
8
read-only
0x4
0xFF
ID
Peripheral Identification
0
6
read-only
IDCOMP
Peripheral ID Complement
0x4
8
read-only
0xFB
0xFF
NID
Negative Peripheral ID
0
6
read-only
REV
Peripheral Revision
0x8
8
read-only
0x33
0xFF
REV
Revision
0
8
read-only
OTGCTL
OTG Control
0x1C
8
read-write
0
0xFF
DPHIGH
D+ Data Line Pullup Resistor Enable
7
1
read-write
DIS_DP_PULLUP
Disable
0
EN_DP_PULLUP
Enable
0x1
ISTAT
Interrupt Status
0x80
8
read-write
0
0xFF
oneToClear
USBRST
USB Reset Flag
0
1
read-write
oneToClear
read
INT_NO
Not detected
0
INT_YES
Detected
0x1
ERROR
Error Flag
1
1
read-write
oneToClear
read
INT_NO
Error did not occur
0
INT_YES
Error occurred
0x1
SOFTOK
Start Of Frame (SOF) Token Flag
2
1
read-write
oneToClear
read
INT_NO
Did not receive
0
INT_YES
Received
0x1
TOKDNE
Current Token Processing Flag
3
1
read-write
oneToClear
read
INT_NO
Not processed
0
INT_YES
Processed
0x1
SLEEP
Sleep Flag
4
1
read-write
oneToClear
read
INT_NO
Interrupt did not occur
0
INT_YES
Interrupt occurred
0x1
RESUME
Resume Flag
5
1
read-write
oneToClear
read
INT_NO
Interrupt did not occur
0
INT_YES
Interrupt occurred
0x1
STALL
Stall Interrupt Flag
7
1
read-write
oneToClear
read
INT_NO
Interrupt did not occur
0
INT_YES
Interrupt occurred
0x1
INTEN
Interrupt Enable
0x84
8
read-write
0
0xFF
USBRSTEN
USBRST Interrupt Enable
0
1
read-write
DIS_USBRST_INT
Disable
0
EN_USBRST_INT
Enable
0x1
ERROREN
ERROR Interrupt Enable
1
1
read-write
DIS_ERROR_INT
Disable
0
EN_ERROR_INT
Enable
0x1
SOFTOKEN
SOFTOK Interrupt Enable
2
1
read-write
DIS_SOFTOK_INT
Disable
0
EN_SOFTOK_INT
Enable
0x1
TOKDNEEN
TOKDNE Interrupt Enable
3
1
read-write
DIS_TOKDNE_INT
Disable
0
EN_TOKDNE_INT
Enable
0x1
SLEEPEN
SLEEP Interrupt Enable
4
1
read-write
DIS_SLEEP_INT
Disable
0
EN_SLEEP_INT
Enable
0x1
RESUMEEN
RESUME Interrupt Enable
5
1
read-write
DIS_RESUME_INT
Disable
0
EN_RESUME_INT
Enable
0x1
STALLEN
STALL Interrupt Enable
7
1
read-write
DIS_STALL_INT
Disable
0
EN_STALL_INT
Enable
0x1
ERRSTAT
Error Interrupt Status
0x88
8
read-write
0
0xFF
oneToClear
PIDERR
PID Error Flag
0
1
read-write
oneToClear
read
INT_NO
Did not fail
0
INT_YES
Failed
0x1
CRC5EOF
CRC5 Error or End of Frame Error Flag
1
1
read-write
oneToClear
read
INT_NO
Interrupt did not occur
0
INT_YES
Interrupt occurred
0x1
CRC16
CRC16 Error Flag
2
1
read-write
oneToClear
read
INT_NO
Not rejected
0
INT_YES
Rejected
0x1
DFN8
Data Field Not 8 Bits Flag
3
1
read-write
oneToClear
read
INT_NO
Integer number of bytes
0
INT_YES
Not an integer number of bytes
0x1
BTOERR
Bus Turnaround Timeout Error Flag
4
1
read-write
oneToClear
read
INT_NO
Not timed out
0
INT_YES
Timed out
0x1
DMAERR
DMA Access Error Flag
5
1
read-write
oneToClear
read
INT_NO
Interrupt did not occur
0
INT_YES
Interrupt occurred
0x1
OWNERR
BD Unavailable Error Flag
6
1
read-write
oneToClear
read
INT_NO
Interrupt did not occur
0
INT_YES
Interrupt occurred
0x1
BTSERR
Bit Stuff Error Flag
7
1
read-write
oneToClear
read
INT_NO
Packet not rejected due to the error
0
INT_YES
Packet rejected due to the error
0x1
ERREN
Error Interrupt Enable
0x8C
8
read-write
0
0xFF
PIDERREN
PIDERR Interrupt Enable
0
1
read-write
DIS_PIDERR_INT
Disable
0
EN_PIDERR_INT
Enable
0x1
CRC5EOFEN
CRC5/EOF Interrupt Enable
1
1
read-write
DIS_CRC5_INT
Disable
0
EN_CRC5_INT
Enable
0x1
CRC16EN
CRC16 Interrupt Enable
2
1
read-write
DIS_CRC16_INT
Disable
0
EN_CRC16_INT
Enable
0x1
DFN8EN
DFN8 (Data Field Not Integer Number of Bytes) Interrupt Enable
3
1
read-write
DIS_DFN8_INT
Disable
0
EN_DFN8_INT
Enable
0x1
BTOERREN
BTOERR (Bus Timeout Error) Interrupt Enable
4
1
read-write
DIS_BTOERR_INT
Disable
0
EN_BTOERR_INT
Enable
0x1
DMAERREN
DMAERR Interrupt Enable
5
1
read-write
DIS_DMAERR_INT
Disable
0
EN_DMAERR_INT
Enable
0x1
OWNERREN
OWNERR Interrupt Enable
6
1
read-write
DIS_OWNERR_INT
Disable
0
EN_OWNERR_INT
Enable
0x1
BTSERREN
BTSERR (Bit Stuff Error) Interrupt Enable
7
1
read-write
DIS_BTSERREN_INT
Disable
0
EN_BTSERREN_INT
Enable
0x1
STAT
Status
0x90
8
read-only
0
0xFF
ODD
Odd Bank
2
1
read-only
NOT_IN_ODD_BANK
Not in the odd bank
0
ODD_BANK
In the odd bank
0x1
TX
Transmit Indicator
3
1
read-only
RX_TRANSACTION
Receive
0
TX_TRANSACTION
Transmit
0x1
ENDP
Endpoint address
4
4
read-only
CTL
Control
0x94
8
read-write
0
0xFF
USBENSOFEN
USB Enable
0
1
read-write
DIS_USB_SOF
Disable
0
EN_USB_SOF
Enable
0x1
ODDRST
Odd Reset
1
1
read-write
RESUME
Resume
2
1
read-write
TXSUSPENDTOKENBUSY
TXD Suspend And Token Busy
5
1
read-write
SE0
Live USB Single-Ended Zero signal
6
1
read-write
ADDR
Address
0x98
8
read-write
0
0xFF
ADDR
USB Address
0
7
read-write
BDTPAGE1
BDT Page 1
0x9C
8
read-write
0
0xFF
BDTBA
BDT Base Address
1
7
read-write
FRMNUML
Frame Number Register Low
0xA0
8
read-only
0
0xFF
FRM
Frame Number, Bits 0-7
0
8
read-only
FRMNUMH
Frame Number Register High
0xA4
8
read-only
0
0xFF
FRM
Frame Number, Bits 8-10
0
3
read-only
BDTPAGE2
BDT Page 2
0xB0
8
read-write
0
0xFF
BDTBA
BDT Base Address
0
8
read-write
BDTPAGE3
BDT Page 3
0xB4
8
read-write
0
0xFF
BDTBA
BDT Base Address
0
8
read-write
16
0x4
ENDPOINT[%s]
no description available
0xC0
ENDPT
Endpoint Control
0
8
read-write
0
0xFF
EPHSHK
Endpoint Handshaking Enable
0
1
read-write
EPSTALL
Endpoint Stalled
1
1
read-write
EPTXEN
Endpoint for TX transfers enable
2
1
read-write
EPRXEN
Endpoint for RX transfers enable
3
1
read-write
EPCTLDIS
Control Transfer Disable
4
1
read-write
Enable
Enable
0
Disable
Disable
0x1
USBCTRL
USB Control
0x100
8
read-write
0xC0
0xFF
DPDM_LANE_REVERSE
DP and DM Lane Reversal Control
2
1
read-write
DP_DM_STANDARD
Standard USB DP and DM package pin assignment
0
DP_DM_REVERSED
Reverse roles of USB DP and DM package pins
0x1
UARTSEL
UART Select
4
1
read-write
USB_MODE
USB DP and DM external package pins are used for USB signaling.
0
UART_MODE
USB DP and DM external package pins are used for UART signaling.
0x1
UARTCHLS
UART Signal Channel Select
5
1
read-write
UART_DP_TX
USB DP and DM signals are used as UART TX/RX.
0
UART_DM_TX
USB DP and DM signals are used as UART RX/TX.
0x1
PDE
Pulldown Enable
6
1
read-write
DIS_PULLDOWNS
Disable on D+ and D-
0
EN_PULLDOWNS
Enable on D+ and D-
0x1
SUSP
Suspend
7
1
read-write
XCVR_NOT_SUSPEND
Not in Suspend state
0
XCVR_SUSPEND
In Suspend state
0x1
OBSERVE
USB OTG Observe
0x104
8
read-only
0x50
0xFF
DMPD
D- Pulldown
4
1
read-only
DM_PD_DIS_STAT
Disabled
0
DM_PD_EN_STAT
Enabled
0x1
DPPD
D+ Pulldown
6
1
read-only
DP_PD_DIS_STAT
Disabled
0
DP_PD_EN_STAT
Enabled
0x1
DPPU
D+ Pullup
7
1
read-only
DP_PU_DIS_STAT
Disabled
0
DP_PU_EN_STAT
Enabled
0x1
CONTROL
USB OTG Control
0x108
8
read-write
0
0xFF
VBUS_SOURCE_SEL
VBUS Monitoring Source Select
0
1
read-write
RESISTIVE
Resistive divider attached to a GPIO pin
0x1
SESS_VLD
VBUS Session Valid status
1
1
read-only
SESS_VLD_LOW
Below
0
SESS_VLD_HIGH
Above
0x1
DPPULLUPNONOTG
DP Pullup in Non-OTG Device Mode
4
1
read-write
DIS_DEVICE_DP_PU
Disable
0
EN_DEVICE_DP_PU
Enabled
0x1
USBTRC0
USB Transceiver Control 0
0x10C
8
read-write
0
0xFF
USB_RESUME_INT
USB Asynchronous Interrupt
0
1
read-only
NO_ASYNC_INT
Not generated
0
SYNC_INT_GENERATED
Generated because of the USB asynchronous interrupt
0x1
SYNC_DET
Synchronous USB Interrupt Detect
1
1
read-only
NO_SYNC_INT
Not detected
0
SYNC_INT_DETECTED
Detected
0x1
USB_CLK_RECOVERY_INT
Combined USB Clock Recovery interrupt status
2
1
read-only
VREDG_DET
VREGIN Rising Edge Interrupt Detect
3
1
read-only
NO_VREG_RE_INT
Not detected
0
VREG_RE_INT_DETECTED
Detected
0x1
VFEDG_DET
VREGIN Falling Edge Interrupt Detect
4
1
read-only
NO_VREG_FE_INT
Not detected
0
VREG_FE_INT_DETECTED
Detected
0x1
USBRESMEN
Asynchronous Resume Interrupt Enable
5
1
read-write
DIS_ASYNC_WAKEUP
Disable
0
EN_ASYNC_WAKEUP
Enable
0x1
VREGIN_STS
VREGIN Status
6
1
read-only
USBRESET
USB Reset
7
1
write-only
NORMAL_OPERATION
Normal USBFS operation
0
FORCE_HARD_RESET
Returns USBFS to its reset state
0x1
KEEP_ALIVE_CTRL_RSVD
Reserved
0x124
8
read-write
0x8
0xFF
KEEP_ALIVE_WKCTRL_RSVD
Reserved
0x128
8
read-write
0x1
0xFF
MISCCTRL
Miscellaneous Control
0x12C
8
read-write
0
0xFF
OWNERRISODIS
OWN Error Detect for ISO IN and ISO OUT Disable
2
1
read-write
DIS_OWN_ERROR_DETECT_ISO
Enable
0
EN_OWN_ERROR_DETECT_ISO
Disable
0x1
VREDG_EN
VREGIN Rising Edge Interrupt Enable
3
1
read-write
DIS_VREGIN_RE_INT
Disable
0
EN_VREGIN_RE_INT
Enable
0x1
VFEDG_EN
VREGIN Falling Edge Interrupt Enable
4
1
read-write
DIS_VREGIN_FE_INT
Disable
0
EN_VREGIN_FE_INT
Enable
0x1
STL_ADJ_EN
USB Peripheral Mode Stall Adjust Enable
7
1
read-write
STALL_BOTH_IN_OUT
If ENDPTn[END_STALL] = 1, both IN and OUT directions for the associated endpoint stalls.
0
STALL_SINGLE_DIRECTION
If ENDPTn[END_STALL] = 1, the STALL_xx_DIS registers control which directions for the associated endpoint stalls.
0x1
STALL_IL_DIS
Peripheral Mode Stall Disable for Endpoints 7 to 0 in IN Direction
0x130
8
read-write
0
0xFF
STALL_I_DIS0
Disable Endpoint 0 IN Direction
0
1
read-write
EN_EP0_IN_STALL
Enable
0
DIS_EP0_IN_STALL
Disable
0x1
STALL_I_DIS1
Disable Endpoint 1 IN Direction
1
1
read-write
EN_EP1_IN_STALL
Enable
0
DIS_EP1_IN_STALL
Disable
0x1
STALL_I_DIS2
Disable Endpoint 2 IN Direction
2
1
read-write
EN_EP2_IN_STALL
Enable
0
DIS_EP2_IN_STALL
Disable
0x1
STALL_I_DIS3
Disable Endpoint 3 IN Direction
3
1
read-write
EN_EP3_IN_STALL
Enable
0
DIS_EP3_IN_STALL
Disable
0x1
STALL_I_DIS4
Disable Endpoint 4 IN Direction
4
1
read-write
EN_EP4_IN_STALL
Enable
0
DIS_EP4_IN_STALL
Disable
0x1
STALL_I_DIS5
Disable Endpoint 5 IN Direction
5
1
read-write
EN_EP5_IN_STALL
Enable
0
DIS_EP5_IN_STALL
Disable
0x1
STALL_I_DIS6
Disable Endpoint 6 IN Direction
6
1
read-write
EN_EP6_IN_STALL
Enable
0
DIS_EP6_IN_STALL
Disable
0x1
STALL_I_DIS7
Disable Endpoint 7 IN Direction
7
1
read-write
EN_EP7_IN_STALL
Enable
0
DIS_EP7_IN_STALL
Disable
0x1
STALL_IH_DIS
Peripheral Mode Stall Disable for Endpoints 15 to 8 in IN Direction
0x134
8
read-write
0
0xFF
STALL_I_DIS8
Disable Endpoint 8 IN Direction
0
1
read-write
EN_EP8_IN_STALL
Enable
0
DIS_EP8_IN_STALL
Disable
0x1
STALL_I_DIS9
Disable Endpoint 9 IN Direction
1
1
read-write
EN_EP9_IN_STALL
Enable
0
DIS_EP9_IN_STALL
Disable
0x1
STALL_I_DIS10
Disable Endpoint 10 IN Direction
2
1
read-write
EN_EP10_IN_STALL
Enable
0
DIS_EP10_IN_STALL
Disable
0x1
STALL_I_DIS11
Disable Endpoint 11 IN Direction
3
1
read-write
EN_EP11_IN_STALL
Enable
0
DIS_EP11_IN_STALL
Disable
0x1
STALL_I_DIS12
Disable Endpoint 12 IN Direction
4
1
read-write
EN_EP12_IN_STALL
Enable
0
DIS_EP12_IN_STALL
Disable
0x1
STALL_I_DIS13
Disable Endpoint 13 IN Direction
5
1
read-write
EN_EP13_IN_STALL
Enable
0
DIS_EP13_IN_STALL
Disable
0x1
STALL_I_DIS14
Disable Endpoint 14 IN Direction
6
1
read-write
EN_EP14_IN_STALL
Enable
0
DIS_EP14_IN_STALL
Disable
0x1
STALL_I_DIS15
Disable Endpoint 15 IN Direction
7
1
read-write
EN_EP15_IN_STALL
Enable
0
DIS_EP15_IN_STALL
Disable
0x1
STALL_OL_DIS
Peripheral Mode Stall Disable for Endpoints 7 to 0 in OUT Direction
0x138
8
read-write
0
0xFF
STALL_O_DIS0
Disable Endpoint 0 OUT Direction
0
1
read-write
EN_EP0_OUT_STALL
Enable
0
DIS_EP0_OUT_STALL
Disable
0x1
STALL_O_DIS1
Disable Endpoint 1 OUT Direction
1
1
read-write
EN_EP1_OUT_STALL
Enable
0
DIS_EP1_OUT_STALL
Disable
0x1
STALL_O_DIS2
Disable Endpoint 2 OUT Direction
2
1
read-write
EN_EP2_OUT_STALL
Enable
0
DIS_EP2_OUT_STALL
Disable
0x1
STALL_O_DIS3
Disable Endpoint 3 OUT Direction
3
1
read-write
EN_EP3_OUT_STALL
Enable
0
DIS_EP3_OUT_STALL
Disable
0x1
STALL_O_DIS4
Disable Endpoint 4 OUT Direction
4
1
read-write
EN_EP4_OUT_STALL
Enable
0
DIS_EP4_OUT_STALL
Disable
0x1
STALL_O_DIS5
Disable Endpoint 5 OUT Direction
5
1
read-write
EN_EP5_OUT_STALL
Enable
0
DIS_EP5_OUT_STALL
Disable
0x1
STALL_O_DIS6
Disable Endpoint 6 OUT Direction
6
1
read-write
EN_EP6_OUT_STALL
Enable
0
DIS_EP6_OUT_STALL
Disable
0x1
STALL_O_DIS7
Disable Endpoint 7 OUT Direction
7
1
read-write
EN_EP7_OUT_STALL
Enable
0
DIS_EP7_OUT_STALL
Disable
0x1
STALL_OH_DIS
Peripheral Mode Stall Disable for Endpoints 15 to 8 in OUT Direction
0x13C
8
read-write
0
0xFF
STALL_O_DIS8
Disable Endpoint 8 OUT Direction
0
1
read-write
EN_EP8_OUT_STALL
Enable
0
DIS_EP8_OUT_STALL
Disable
0x1
STALL_O_DIS9
Disable Endpoint 9 OUT Direction
1
1
read-write
EN_EP9_OUT_STALL
Enable
0
DIS_EP9_OUT_STALL
Disable
0x1
STALL_O_DIS10
Disable Endpoint 10 OUT Direction
2
1
read-write
EN_EP10_OUT_STALL
Enable
0
DIS_EP10_OUT_STALL
Disable
0x1
STALL_O_DIS11
Disable Endpoint 11 OUT Direction
3
1
read-write
EN_EP11_OUT_STALL
Enable
0
DIS_EP11_OUT_STALL
Disable
0x1
STALL_O_DIS12
Disable endpoint 12 OUT direction
4
1
read-write
EN_EP12_OUT_STALL
Enable
0
DIS_EP12_OUT_STALL
Disable
0x1
STALL_O_DIS13
Disable Endpoint 13 OUT Direction
5
1
read-write
EN_EP13_OUT_STALL
Enable
0
DIS_EP13_OUT_STALL
Disable
0x1
STALL_O_DIS14
Disable Endpoint 14 OUT Direction
6
1
read-write
EN_EP14_OUT_STALL
Enable
0
DIS_EP14_OUT_STALL
Disable
0x1
STALL_O_DIS15
Disable Endpoint 15 OUT Direction
7
1
read-write
EN_EP15_OUT_STALL
Enable
0
DIS_EP15_OUT_STALL
Disable
0x1
CLK_RECOVER_CTRL
USB Clock Recovery Control
0x140
8
read-write
0
0xFF
TRIM_INIT_VAL_SEL
Selects the source for the initial FIRC trim fine value used after a reset.
3
1
read-write
INIT_TRIM_FINE_MID
Mid-scale
0
INIT_TRIM_FINE_IFR
IFR
0x1
RESTART_IFRTRIM_EN
Restart from IFR Trim Value
5
1
read-write
LOAD_TRIM_FINE_MID
Trim fine adjustment always works based on the previous updated trim fine value.
0
LOAD_TRIM_FINE_IFR
Trim fine restarts from the IFR trim value whenever you detect bus_reset or bus_resume or deassert module enable.
0x1
RESET_RESUME_ROUGH_EN
Reset or Resume to Rough Phase Enable
6
1
read-write
KEEP_TRIM_FINE_ON_RESET
Always works in tracking phase after the first time rough phase, to track transition.
0
USE_IFR_TRIM_FINE_ON_RESET
Go back to rough stage whenever a bus reset or bus resume occurs.
0x1
CLOCK_RECOVER_EN
Crystal-Less USB Enable
7
1
read-write
DIS_CLK_RECOVER
Disable
0
EN_CLK_RECOVER
Enable
0x1
CLK_RECOVER_IRC_EN
FIRC Oscillator Enable
0x144
8
read-write
0x1
0xFF
IRC_EN
Fast IRC enable
1
1
read-write
DIS_IRC
Disable
0
EN_IRC
Enable
0x1
CLK_RECOVER_INT_EN
Clock Recovery Combined Interrupt Enable
0x154
8
read-write
0x10
0xFF
OVF_ERROR_EN
Overflow error interrupt enable
4
1
read-write
MASK_OVF_ERR_INT
The interrupt is masked
0
EN_OVF_ERR_INT
The interrupt is enabled
0x1
CLK_RECOVER_INT_STATUS
Clock Recovery Separated Interrupt Status
0x15C
8
read-write
0
0xFF
oneToClear
OVF_ERROR
Overflow Error Interrupt Status Flag
4
1
read-write
oneToClear
read
INT_NO
Interrupt did not occur
0
INT_YES
Unmasked interrupt occurred
0x1
QDC0
Quadrature_Decoder
QDC
0x400A7000
0
0x54
registers
QDC0_COMPARE
50
QDC0_HOME
51
QDC0_WATCHDOG
52
QDC0_INDEX
53
CTRL
Control Register
0
16
read-write
0
0xFFFF
LDOK
Load Okay
0
1
read-write
LDOK0
No loading action taken. Users can write new values to buffered registers (writing into outer-set of these buffered registers)
0
LDOK1
Outer-set values are ready to be loaded into inner-set and take effect. The loading time point depends on CTRL2[LDMOD].
0x1
DMAEN
DMA Enable
1
1
read-write
DMAEN_0
DMA is disabled
0
DMAEN_1
DMA is enabled. DMA request asserts automatically when the values in the outer-set of buffered compare registers (UCOMP0/LCOMP0;UCOMP1/LCOMP1;UCOMP2/LCOMP2;UCOMP3/LCOMP3), initial registers(UINIT/LINIT) and modulus registers (UMOD/LMOD) are loaded into the inner-set of buffer and then LDOK is cleared automatically. After the completion of this DMA transfer, LDOK is set automatically, it ensures outer-set values can be loaded into inner-set which in turn triggers DMA again.
0x1
WDE
Watchdog Enable
2
1
read-write
WDE0
Disabled
0
WDE1
Enabled
0x1
WDIE
Watchdog Timeout Interrupt Enable
3
1
read-write
WDIE0
Disabled
0
WDIE1
Enabled
0x1
WDIRQ
Watchdog Timeout Interrupt Request
4
1
read-write
oneToClear
WDIRQ0
No Watchdog timeout interrupt has occurred
0
WDIRQ1
Watchdog timeout interrupt has occurred
0x1
XNE
Select Positive/Negative Edge of INDEX/PRESET Pulse
5
1
read-write
XNE0
Use positive edge of INDEX/PRESET pulse
0
XNE1
Use negative edge of INDEX/PRESET pulse
0x1
XIP
INDEX Triggered Initialization of Position Counters UPOS and LPOS
6
1
read-write
XIP0
INDEX pulse does not initialize the position counter
0
XIP1
INDEX pulse initializes the position counter
0x1
XIE
INDEX/PRESET Pulse Interrupt Enable
7
1
read-write
XIE0
Disabled
0
XIE1
Enabled
0x1
XIRQ
INDEX/PRESET Pulse Interrupt Request
8
1
read-write
oneToClear
XIRQ0
INDEX/PRESET pulse has not occurred
0
XIRQ1
INDEX/PRESET pulse has occurred
0x1
PH1
Enable Single Phase Mode
9
1
read-write
PH10
Standard quadrature decoder, where PHASEA and PHASEB represent a two-phase quadrature signal.
0
PH11
Single phase mode, bypass the quadrature decoder, refer to CTRL2[CMODE] description
0x1
REV
Enable Reverse Direction Counting
10
1
read-write
REV0
Count normally and the position counter initialization uses upper/lower initialization register UINIT/LINIT
0
REV1
Count in the reverse direction and the position counter initialization uses upper/lower modulus register UMOD/LMOD
0x1
SWIP
Software-Triggered Initialization of Position Counters UPOS and LPOS
11
1
read-write
SWIP0
No action
0
SWIP1
Initialize position counter
0x1
HNE
Use Negative Edge of HOME/ENABLE Input
12
1
read-write
HNE0
When CTRL[OPMODE] = 0,use HOME positive edge to trigger initialization of position counters. When CTRL[OPMODE] = 1,use ENABLE high level to enable POS/POSD/WDG/REV counters
0
HNE1
When CTRL[OPMODE] = 0,use HOME negative edge to trigger initialization of position counters. When CTRL[OPMODE] = 1,use ENABLE low level to enable POS/POSD/WDG/REV counters
0x1
HIP
Enable HOME to Initialize Position Counter UPOS/LPOS
13
1
read-write
HIP0
No action
0
HIP1
HOME signal initializes the position counter
0x1
HIE
HOME/ENABLE Interrupt Enable
14
1
read-write
HIE0
Disabled
0
HIE1
Enabled
0x1
HIRQ
HOME/ENABLE Signal Transition Interrupt Request
15
1
read-write
oneToClear
HIRQ0
No transition on the HOME/ENABLE signal has occurred
0
HIRQ1
A transition on the HOME/ENABLE signal has occurred
0x1
CTRL2
Control 2 Register
0x2
16
read-write
0
0xFFFF
UPDHLD
Update Hold Registers
0
1
read-write
UPDPOS
Update Position Registers
1
1
read-write
OPMODE
Operation Mode Select
2
1
read-write
OPMODE0
Decode Mode: Input nodes INDEX/PRESET and HOME/ENABLE are assigned to function of INDEX and HOME.
0
OPMODE1
Count Mode: Input nodes INDEX/PRESET and HOME/ENABLE are assigned to functions of PRESET and ENABLE. In this mode: (1)only when ENABLE=1, all counters (position/position difference/revolution/watchdog) can run, when ENABLE=0, all counters (position/position difference/revolution/watchdog) can't run. (2) the rising edge of PRESET input can initialize position/revolution/watchdog counters (position counter initialization also need referring to bit CTRL[REV]).
0x1
LDMOD
Buffered Register Load (Update) Mode Select
3
1
read-write
LDMOD0
Buffered registers are loaded and take effect immediately upon CTRL[LDOK] is set.
0
LDMOD1
Buffered registers are loaded and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.
0x1
REVMOD
Revolution Counter Modulus Enable
8
1
read-write
REVMOD0
Use INDEX pulse to increment/decrement revolution counter (REV)
0
REVMOD1
Use modulus counting roll-over/under to increment/decrement revolution counter (REV)
0x1
OUTCTL
Output Control
9
1
read-write
OUTCTL0
POS_MATCH[x](x range is 0-3) is asserted when the Position Counter is equal to according compare value (UCOMPx/LCOMPx)(x range is 0-3), and de-asserted when the Position Counter not equal to the compare value (UCOMPx/LCOMPx)(x range is 0-3)
0
OUTCTL1
All POS_MATCH[x](x range is 0-3) are asserted a pulse, when the UPOS, LPOS, REV, or POSD registers are read
0x1
PMEN
Period measurement function enable
10
1
read-write
PMEN0
Period measurement functions are not used. POSD is loaded to POSDH and then cleared whenever POSD, UPOS, LPOS or REV is read.
0
PMEN1
Period measurement functions are used. POSD is loaded into POSDH and then cleared only when POSD is read.
0x1
EMIP
Enables/disables the position counter to be initialized by Index Event Edge Mark
11
1
read-write
EMIP0
disables the position counter to be initialized by Index Event Edge Mark
0
EMIP1
enables the position counter to be initialized by Index Event Edge Mark.
0x1
INITPOS
Initial Position Register
12
1
read-write
INITPOS0
Don't initialize position counter on rising edge of TRIGGER
0
INITPOS1
Initialize position counter on rising edge of TRIGGER
0x1
ONCE
Count Once
13
1
read-write
ONCE0
Position counter counts repeatedly
0
ONCE1
Position counter counts until roll-over or roll-under, then stop.
0x1
CMODE
Counting Mode
14
2
read-write
FILT
Input Filter Register
0x4
16
read-write
0
0xFFFF
FILT_PER
Input Filter Sample Period
0
8
read-write
FILT_CNT
Input Filter Sample Count
8
3
read-write
FILT_CS
Filter Clock Source selection
11
1
read-write
FILT_CS0
Peripheral Clock
0
FILT_CS1
Prescaled peripheral clock by PRSC
0x1
PRSC
Prescaler
12
4
read-write
LASTEDGE
Last Edge Time Register
0x6
16
read-only
0xFFFF
0xFFFF
LASTEDGE
Last Edge Time Counter
0
16
read-only
POSDPER
Position Difference Period Counter Register
0x8
16
read-only
0xFFFF
0xFFFF
POSDPER
Position difference period
0
16
read-only
POSDPERBFR
Position Difference Period Buffer Register
0xA
16
read-only
0xFFFF
0xFFFF
POSDPERBFR
Position difference period buffer
0
16
read-only
UPOS
Upper Position Counter Register
0xC
16
read-write
0
0xFFFF
POS
POS
0
16
read-write
LPOS
Lower Position Counter Register
0xE
16
read-write
0
0xFFFF
POS
POS
0
16
read-write
POSD
Position Difference Counter Register
0x10
16
read-write
0
0xFFFF
POSD
POSD
0
16
read-write
POSDH
Position Difference Hold Register
0x12
16
read-only
0
0xFFFF
POSDH
POSDH
0
16
read-only
UPOSH
Upper Position Hold Register
0x14
16
read-only
0
0xFFFF
POSH
POSH
0
16
read-only
LPOSH
Lower Position Hold Register
0x16
16
read-only
0
0xFFFF
LPOSH
POSH
0
16
read-only
LASTEDGEH
Last Edge Time Hold Register
0x18
16
read-only
0xFFFF
0xFFFF
LASTEDGEH
Last Edge Time Hold
0
16
read-only
POSDPERH
Position Difference Period Hold Register
0x1A
16
read-only
0xFFFF
0xFFFF
POSDPERH
Position difference period hold
0
16
read-only
REVH
Revolution Hold Register
0x1C
16
read-only
0
0xFFFF
REVH
REVH
0
16
read-only
REV
Revolution Counter Register
0x1E
16
read-write
0
0xFFFF
REV
REV
0
16
read-write
UINIT
Upper Initialization Register
0x20
16
read-write
0
0xFFFF
INIT
INIT
0
16
read-write
LINIT
Lower Initialization Register
0x22
16
read-write
0
0xFFFF
INIT
INIT
0
16
read-write
UMOD
Upper Modulus Register
0x24
16
read-write
0
0xFFFF
MOD
MOD
0
16
read-write
LMOD
Lower Modulus Register
0x26
16
read-write
0
0xFFFF
MOD
MOD
0
16
read-write
UCOMP0
Upper Position Compare Register 0
0x28
16
read-write
0x8000
0xFFFF
UCOMP0
UCOMP0
0
16
read-write
LCOMP0
Lower Position Compare Register 0
0x2A
16
read-write
0
0xFFFF
LCOMP0
LCOMP0
0
16
read-write
UCOMP1
Upper Position Compare 1
UCOMP1_UPOSH1
0x2C
16
write-only
0x8000
0xFFFF
UCOMP1
UCOMP1
0
16
write-only
UPOSH1
Upper Position Holder Register 1
UCOMP1_UPOSH1
0x2C
16
read-only
0
0xFFFF
UPOSH1
UPOSH1
0
16
read-only
LCOMP1
Lower Position Compare 1
LCOMP1_LPOSH1
0x2E
16
write-only
0
0xFFFF
LCOMP1
LCOMP1
0
16
write-only
LPOSH1
Lower Position Holder Register 1
LCOMP1_LPOSH1
0x2E
16
read-only
0
0xFFFF
LPOSH1
LPOSH1
0
16
read-only
UCOMP2
Upper Position Compare 2
UCOMP2_UPOSH2
0x30
16
write-only
0x8000
0xFFFF
UCOMP2
UCOMP2
0
16
write-only
UPOSH2
Upper Position Holder Register 3
UCOMP2_UPOSH2
0x30
16
read-only
0
0xFFFF
UPOSH2
UPOSH2
0
16
read-only
LCOMP2
Lower Position Compare 2
LCOMP2_LPOSH2
0x32
16
write-only
0
0xFFFF
LCOMP2
LCOMP2
0
16
write-only
LPOSH2
Lower Position Holder Register 2
LCOMP2_LPOSH2
0x32
16
read-only
0
0xFFFF
LPOSH2
LPOSH2
0
16
read-only
UCOMP3
Upper Position Compare 3
UCOMP3_UPOSH3
0x34
16
write-only
0x8000
0xFFFF
UCOMP3
UCOMP3
0
16
write-only
UPOSH3
Upper Position Holder Register 3
UCOMP3_UPOSH3
0x34
16
read-only
0
0xFFFF
UPOSH3
UPOSH3
0
16
read-only
LCOMP3
Lower Position Compare 3
LCOMP3_LPOSH3
0x36
16
write-only
0
0xFFFF
LCOMP3
LCOMP3
0
16
write-only
LPOSH3
Lower Position Holder Register 3
LCOMP3_LPOSH3
0x36
16
read-only
0
0xFFFF
LPOSH3
LPOSH3
0
16
read-only
INTCTRL
Interrupt Control Register
0x38
16
read-write
0
0xFFFF
SABIE
Simultaneous PHASEA and PHASEB Change Interrupt Enable
0
1
read-write
SABIE0
Disabled
0
SABIE1
Enabled
0x1
SABIRQ
Simultaneous PHASEA and PHASEB Change Interrupt Request
1
1
read-write
oneToClear
SABIRQ0
No simultaneous change of PHASEA and PHASEB has occurred
0
SABIRQ1
A simultaneous change of PHASEA and PHASEB has occurred
0x1
DIRIE
Count direction change interrupt enable
2
1
read-write
DIRIE0
Disabled
0
DIRIE1
Enabled
0x1
DIRIRQ
Count direction change interrupt
3
1
read-write
oneToClear
DIRIRQ0
Count direction unchanged
0
DIRIRQ1
Count direction changed
0x1
RUIE
Roll-under Interrupt Enable
4
1
read-write
RUIE0
Disabled
0
RUIE1
Enabled
0x1
RUIRQ
Roll-under Interrupt Request
5
1
read-write
oneToClear
RUIRQ0
No roll-under has occurred
0
RUIRQ1
Roll-under has occurred
0x1
ROIE
Roll-over Interrupt Enable
6
1
read-write
ROIE
Disabled
0
ROIE1
Enabled
0x1
ROIRQ
Roll-over Interrupt Request
7
1
read-write
oneToClear
ROIRQ0
No roll-over has occurred
0
ROIRQ1
Roll-over has occurred
0x1
CMP0IE
Compare 0 Interrupt Enable
8
1
read-write
CMP0IE0
Disabled
0
CMP0IE1
Enabled
0x1
CMP0IRQ
Compare 0 Interrupt Request
9
1
read-write
oneToClear
CMP0IRQ0
No match has occurred (the position counter does not match the COMP0 value)
0
CMP0IRQ1
COMP match has occurred (the position counter matches the COMP0 value)
0x1
CMP1IE
Compare1 Interrupt Enable
10
1
read-write
CMP1IE0
Disabled
0
CMP1IE1
Enabled
0x1
CMP1IRQ
Compare1 Interrupt Request
11
1
read-write
oneToClear
CMP1IRQ0
No match has occurred (the position counter does not match the COMP1 value)
0
CMP1IRQ1
COMP1 match has occurred (the position counter matches the COMP1 value)
0x1
CMP2IE
Compare2 Interrupt Enable
12
1
read-write
CMP2IE0
Disabled
0
CMP2IE1
Enabled
0x1
CMP2IRQ
Compare2 Interrupt Request
13
1
read-write
oneToClear
CMP2IRQ0
No match has occurred (the position counter does not match the COMP2 value)
0
CMP2IRQ1
COMP2 match has occurred (the position counter matches the COMP2 value)
0x1
CMP3IE
Compare3 Interrupt Enable
14
1
read-write
CMP3IE0
Disabled
0
CMP3IE1
Enabled
0x1
CMP3IRQ
Compare3 Interrupt Request
15
1
read-write
oneToClear
CMP3IRQ0
No match has occurred (the position counter does not match the COMP3 value)
0
CMP3IRQ1
COMP3 match has occurred (the position counter matches the COMP3 value)
0x1
WTR
Watchdog Timeout Register
0x3A
16
read-write
0
0xFFFF
WDOG
WDOG
0
16
read-write
IMR
Input Monitor Register
0x3C
16
read-write
0
0xFFFF
HOME_ENABLE
HOME_ENABLE
0
1
read-only
INDEX_PRESET
INDEX_PRESET
1
1
read-only
PHB
PHB
2
1
read-only
PHA
PHA
3
1
read-only
FHOM_ENA
filter operation on HOME/ENABLE input
4
1
read-write
FIND_PRE
filter operation on INDEX/PRESET input
5
1
read-write
FPHB
filter operation on PHASEB input
6
1
read-write
FPHA
filter operation on PHASEA input
7
1
read-write
CMPF0
Position Compare 0 Flag Output
8
1
read-only
CMPF00
When the position counter is less than value of COMP0 register
0
CMPF01
When the position counter is greater or equal than value of COMP0 register
0x1
CMP1F
Position Compare1 Flag Output
9
1
read-only
CMP1F0
When the position counter is less than value of COMP1 register
0
CMP1F1
When the position counter is greater or equal than value of COMP1 register
0x1
CMP2F
Position Compare2 Flag Output
10
1
read-only
CMP2F0
When the position counter is less than value of COMP2 register
0
CMP2F1
When the position counter is greater or equal than value of COMP2 register
0x1
CMP3F
Position Compare3 Flag Output
11
1
read-only
CMP3F0
When the position counter value is less than value of COMP3 register
0
CMP3F1
When the position counter is greater or equal than value of COMP3 register
0x1
DIRH
Count Direction Flag Hold
14
1
read-only
DIR
Count Direction Flag Output
15
1
read-only
DIR0
Current count was in the down direction
0
DIR1
Current count was in the up direction
0x1
TST
Test Register
0x3E
16
read-write
0
0xFFFF
TEST_COUNT
TEST_COUNT
0
8
read-write
TEST_PERIOD
TEST_PERIOD
8
5
read-write
QDN
Quadrature Decoder Negative Signal
13
1
read-write
QDN0
Generates a positive quadrature decoder signal
0
QDN1
Generates a negative quadrature decoder signal
0x1
TCE
Test Counter Enable
14
1
read-write
TCE0
Disabled
0
TCE1
Enabled
0x1
TEN
Test Mode Enable
15
1
read-write
TEN0
Disabled
0
TEN1
Enabled
0x1
UVERID
Upper VERID
0x50
16
read-only
0x1
0xFFFF
UVERID
UVERID
0
16
read-only
LVERID
Lower VERID
0x52
16
read-only
0x1
0xFFFF
LVERID
LVERID
0
16
read-only
FLEXPWM0
PWM
FLEXPWM
0x400A9000
0
0x196
registers
FLEXPWM0_RELOAD_ERROR
44
FLEXPWM0_FAULT
45
FLEXPWM0_SUBMODULE0
46
FLEXPWM0_SUBMODULE1
47
FLEXPWM0_SUBMODULE2
48
SM0CNT
Counter Register
0
16
read-only
0
0xFFFF
CNT
Counter Register Bits
0
16
read-only
SM0INIT
Initial Count Register
0x2
16
read-write
0
0xFFFF
INIT
Initial Count Register Bits
0
16
read-write
SM0CTRL2
Control 2 Register
0x4
16
read-write
0
0xFFFF
CLK_SEL
Clock Source Select
0
2
read-write
IPBUS
The IPBus clock is used as the clock for the local prescaler and counter.
0
EXT_CLK
EXT_CLK is used as the clock for the local prescaler and counter.
0x1
AUX_CLK
Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it forces the clock to logic 0.
0x2
RELOAD_SEL
Reload Source Select
2
1
read-write
LOCAL
The local RELOAD signal is used to reload registers.
0
MASTER
The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it forces the RELOAD signal to logic 0.
0x1
FORCE_SEL
Force Select
3
3
read-write
LOCAL
The local force signal, CTRL2[FORCE], from this submodule is used to force updates.
0
MASTER
The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it holds the FORCE OUTPUT signal to logic 0.
0x1
LOCAL_RELOAD
The local reload signal from this submodule is used to force updates without regard to the state of LDOK.
0x2
MASTER_RELOAD
The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0.
0x3
LOCAL_SYNC
The local sync signal from this submodule is used to force updates.
0x4
MASTER_SYNC
The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0.
0x5
EXT_FORCE
The external force signal, EXT_FORCE, from outside the PWM module causes updates.
0x6
EXT_SYNC
The external sync signal, EXT_SYNC, from outside the PWM module causes updates.
0x7
FORCE
Force Initialization
6
1
read-write
FRCEN
Force Enable
7
1
read-write
DISABLED
Initialization from a FORCE_OUT is disabled.
0
ENABLED
Initialization from a FORCE_OUT is enabled.
0x1
INIT_SEL
Initialization Control Select
8
2
read-write
PWM_X
Local sync (PWM_X) causes initialization.
0
MASTER_RELOAD
Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload occurs.
0x1
MASTER_SYNC
Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0.
0x2
EXT_SYNC
EXT_SYNC causes initialization.
0x3
PWMX_INIT
PWM_X Initial Value
10
1
read-write
PWM45_INIT
PWM45 Initial Value
11
1
read-write
PWM23_INIT
PWM23 Initial Value
12
1
read-write
INDEP
Independent or Complementary Pair Operation
13
1
read-write
COMPLEMENTARY
PWM_A and PWM_B form a complementary PWM pair.
0
INDEPENDENT
PWM_A and PWM_B outputs are independent PWMs.
0x1
DBGEN
Debug Enable
15
1
read-write
SM0CTRL
Control Register
0x6
16
read-write
0x400
0xFFFF
DBLEN
Double Switching Enable
0
1
read-write
DISABLED
Double switching disabled.
0
ENABLED
Double switching enabled.
0x1
DBLX
PWM_X Double Switching Enable
1
1
read-write
DISABLED
PWM_X double pulse disabled.
0
ENABLED
PWM_X double pulse enabled.
0x1
LDMOD
Load Mode Select
2
1
read-write
NEXT_PWM_RELOAD
Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set.
0
MTCTRL_LDOK_SET
Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case, it is not necessary to set CTRL[FULL] or CTRL[HALF].
0x1
SPLIT
Split the DBLPWM signal to PWM_A and PWM_B
3
1
read-write
DISABLED
DBLPWM is not split. PWM_A and PWM_B each have double pulses.
0
ENABLED
DBLPWM is split to PWM_A and PWM_B.
0x1
PRSC
Prescaler
4
3
read-write
ONE
Prescaler 1
0
TWO
Prescaler 2
0x1
FOUR
Prescaler 4
0x2
EIGHT
Prescaler 8
0x3
SIXTEEN
Prescaler 16
0x4
THIRTYTWO
Prescaler 32
0x5
SIXTYFOUR
Prescaler 64
0x6
HUNDREDTWENTYEIGHT
Prescaler 128
0x7
COMPMODE
Compare Mode
7
1
read-write
EQUAL_TO
The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period maintains this state until a match with VAL3 clears the output in the following period.
0
EQUAL_TO_OR_GREATER_THAN
The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value.
0x1
DT
Deadtime
8
2
read-only
FULL
Full Cycle Reload
10
1
read-write
DISABLED
Full-cycle reloads disabled.
0
ENABLED
Full-cycle reloads enabled.
0x1
HALF
Half Cycle Reload
11
1
read-write
DISABLED
Half-cycle reloads disabled.
0
ENABLED
Half-cycle reloads enabled.
0x1
LDFQ
Load Frequency
12
4
read-write
EVERYPWM
Every PWM opportunity
0
EVERY2PWM
Every 2 PWM opportunities
0x1
EVERY3PWM
Every 3 PWM opportunities
0x2
EVERY4PWM
Every 4 PWM opportunities
0x3
EVERY5PWM
Every 5 PWM opportunities
0x4
EVERY6PWM
Every 6 PWM opportunities
0x5
EVERY7PWM
Every 7 PWM opportunities
0x6
EVERY8PWM
Every 8 PWM opportunities
0x7
EVERY9PWM
Every 9 PWM opportunities
0x8
EVERY10PWM
Every 10 PWM opportunities
0x9
EVERY11PWM
Every 11 PWM opportunities
0xA
EVERY12PWM
Every 12 PWM opportunities
0xB
EVERY13PWM
Every 13 PWM opportunities
0xC
EVERY14PWM
Every 14 PWM opportunities
0xD
EVERY15PWM
Every 15 PWM opportunities
0xE
EVERY16PWM
Every 16 PWM opportunities
0xF
SM0VAL0
Value Register 0
0xA
16
read-write
0
0xFFFF
VAL0
Value 0
0
16
read-write
SM0VAL1
Value Register 1
0xE
16
read-write
0
0xFFFF
VAL1
Value 1
0
16
read-write
SM0VAL2
Value Register 2
0x12
16
read-write
0
0xFFFF
VAL2
Value 2
0
16
read-write
SM0VAL3
Value Register 3
0x16
16
read-write
0
0xFFFF
VAL3
Value 3
0
16
read-write
SM0VAL4
Value Register 4
0x1A
16
read-write
0
0xFFFF
VAL4
Value 4
0
16
read-write
SM0VAL5
Value Register 5
0x1E
16
read-write
0
0xFFFF
VAL5
Value 5
0
16
read-write
SM0OCTRL
Output Control Register
0x22
16
read-write
0
0xFFFF
PWMXFS
PWM_X Fault State
0
2
read-write
LOGIC_0
Output is forced to logic 0 state prior to consideration of output polarity control.
0
LOGIC_1
Output is forced to logic 1 state prior to consideration of output polarity control.
0x1
TRISTATED_2
Output is put in a high-impedance state.
0x2
TRISTATED_3
Output is put in a high-impedance state.
0x3
PWMBFS
PWM_B Fault State
2
2
read-write
LOGIC_0
Output is forced to logic 0 state prior to consideration of output polarity control.
0
LOGIC_1
Output is forced to logic 1 state prior to consideration of output polarity control.
0x1
TRISTATED_2
Output is put in a high-impedance state.
0x2
TRISTATED_3
Output is put in a high-impedance state.
0x3
PWMAFS
PWM_A Fault State
4
2
read-write
LOGIC_0
Output is forced to logic 0 state prior to consideration of output polarity control.
0
LOGIC_1
Output is forced to logic 1 state prior to consideration of output polarity control.
0x1
TRISTATED_2
Output is put in a high-impedance state.
0x2
TRISTATED_3
Output is put in a high-impedance state.
0x3
POLX
PWM_X Output Polarity
8
1
read-write
NOT_INVERTED
PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state.
0
INVERTED
PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state.
0x1
POLB
PWM_B Output Polarity
9
1
read-write
NOT_INVERTED
PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state.
0
INVERTED
PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state.
0x1
POLA
PWM_A Output Polarity
10
1
read-write
NOT_INVERTED
PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state.
0
INVERTED
PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state.
0x1
PWMX_IN
PWM_X Input
13
1
read-only
PWMB_IN
PWM_B Input
14
1
read-only
PWMA_IN
PWM_A Input
15
1
read-only
SM0STS
Status Register
0x24
16
read-write
0
0xFFFF
CMPF
Compare Flags
0
6
read-write
oneToClear
NO_EVENT
No compare event has occurred for a particular VALx value.
0
EVENT
A compare event has occurred for a particular VALx value.
0x1
CFX0
Capture Flag X0
6
1
read-write
oneToClear
CFX1
Capture Flag X1
7
1
read-write
oneToClear
RF
Reload Flag
12
1
read-write
oneToClear
NO_FLAG
No new reload cycle since last STS[RF] clearing
0
FLAG
New reload cycle since last STS[RF] clearing
0x1
REF
Reload Error Flag
13
1
read-write
oneToClear
NO_FLAG
No reload error occurred.
0
FLAG
Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0.
0x1
RUF
Registers Updated Flag
14
1
read-only
NO_FLAG
No register update has occurred since last reload.
0
FLAG
At least one of the double buffered registers has been updated since the last reload.
0x1
SM0INTEN
Interrupt Enable Register
0x26
16
read-write
0
0xFFFF
CMPIE
Compare Interrupt Enables
0
6
read-write
DISABLED
The corresponding STS[CMPF] bit will not cause an interrupt request.
0
ENABLED
The corresponding STS[CMPF] bit will cause an interrupt request.
0x1
CX0IE
Capture X 0 Interrupt Enable
6
1
read-write
DISABLED
Interrupt request disabled for STS[CFX0].
0
ENABLED
Interrupt request enabled for STS[CFX0].
0x1
CX1IE
Capture X 1 Interrupt Enable
7
1
read-write
DISABLED
Interrupt request disabled for STS[CFX1].
0
ENABLED
Interrupt request enabled for STS[CFX1].
0x1
RIE
Reload Interrupt Enable
12
1
read-write
DISABLED
STS[RF] CPU interrupt requests disabled
0
ENABLED
STS[RF] CPU interrupt requests enabled
0x1
REIE
Reload Error Interrupt Enable
13
1
read-write
DISABLED
STS[REF] CPU interrupt requests disabled
0
ENABLED
STS[REF] CPU interrupt requests enabled
0x1
SM0DMAEN
DMA Enable Register
0x28
16
read-write
0
0xFFFF
CX0DE
Capture X0 FIFO DMA Enable
0
1
read-write
CX1DE
Capture X1 FIFO DMA Enable
1
1
read-write
CAPTDE
Capture DMA Enable Source Select
6
2
read-write
DISABLED
Read DMA requests disabled.
0
EXCEEDFIFO
Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to be set to determine which watermark(s) the DMA request is sensitive.
0x1
LOCAL_SYNC
A local synchronization (VAL1 matches counter) sets the read DMA request.
0x2
LOCAL_RELOAD
A local reload (STS[RF] being set) sets the read DMA request.
0x3
FAND
FIFO Watermark AND Control
8
1
read-write
OR
Selected FIFO watermarks are OR'ed together.
0
AND
Selected FIFO watermarks are AND'ed together.
0x1
VALDE
Value Registers DMA Enable
9
1
read-write
DISABLED
DMA write requests disabled
0
ENABLED
Enabled
0x1
SM0TCTRL
Output Trigger Control Register
0x2A
16
read-write
0
0xFFFF
OUT_TRIG_EN
Output Trigger Enables
0
6
read-write
VAL0
PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value.
#xxxxx1
TRGFRQ
Trigger Frequency
12
1
read-write
EVERYPWM
Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.
0
FINALPWM
Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.
0x1
PWBOT1
Mux Output Trigger 1 Source Select
14
1
read-write
PWM_OUT_TRIG1_SIGNAL
Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port.
0
PWMB_OUTPUT
Route the PWM_B output to the PWM_MUX_TRIG1 port.
0x1
PWAOT0
Mux Output Trigger 0 Source Select
15
1
read-write
PWM_OUT_TRIG0_SIGNAL
Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port.
0
PWMA_OUTPUT
Route the PWM_A output to the PWM_MUX_TRIG0 port.
0x1
SM0DISMAP0
Fault Disable Mapping Register 0
0x2C
16
read-write
0xFFFF
0xFFFF
DIS0A
PWM_A Fault Disable Mask 0
0
4
read-write
DIS0B
PWM_B Fault Disable Mask 0
4
4
read-write
DIS0X
PWM_X Fault Disable Mask 0
8
4
read-write
SM0DTCNT0
Deadtime Count Register 0
0x30
16
read-write
0x7FF
0xFFFF
DTCNT0
Deadtime Count Register 0
0
11
read-write
SM0DTCNT1
Deadtime Count Register 1
0x32
16
read-write
0x7FF
0xFFFF
DTCNT1
Deadtime Count Register 1
0
11
read-write
SM0CAPTCTRLX
Capture Control X Register
0x3C
16
read-write
0
0xFFFF
ARMX
Arm X
0
1
read-write
DISABLED
Input capture operation is disabled.
0
ENABLED
Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled.
0x1
ONESHOTX
One Shot Mode Aux
1
1
read-write
FREE_RUNNING
Free Running
0
ONE_SHOT
One Shot
0x1
EDGX0
Edge X 0
2
2
read-write
DISABLED
Disabled
0
FALLING_EDGE
Capture falling edges
0x1
RISING_EDGE
Capture rising edges
0x2
ANY_EDGE
Capture any edge
0x3
EDGX1
Edge X 1
4
2
read-write
DISABLED
Disabled
0
FALLING_EDGE
Capture falling edges
0x1
RISING_EDGE
Capture rising edges
0x2
ANY_EDGE
Capture any edge
0x3
INP_SELX
Input Select X
6
1
read-write
PWM_X
Raw PWM_X input signal selected as source.
0
EDGE_COUNTER
Edge Counter
0x1
EDGCNTX_EN
Edge Counter X Enable
7
1
read-write
DISABLED
Edge counter disabled and held in reset
0
ENABLED
Edge counter enabled
0x1
CFXWM
Capture X FIFOs Water Mark
8
2
read-write
CX0CNT
Capture X0 FIFO Word Count
10
3
read-only
CX1CNT
Capture X1 FIFO Word Count
13
3
read-only
SM0CAPTCOMPX
Capture Compare X Register
0x3E
16
read-write
0
0xFFFF
EDGCMPX
Edge Compare X
0
8
read-write
EDGCNTX
Edge Counter X
8
8
read-only
SM0CVAL0
Capture Value 0 Register
0x40
16
read-only
0
0xFFFF
CAPTVAL0
Capture Value 0
0
16
read-only
SM0CVAL0CYC
Capture Value 0 Cycle Register
0x42
16
read-only
0
0xFFFF
CVAL0CYC
Capture Value 0 Cycle
0
4
read-only
SM0CVAL1
Capture Value 1 Register
0x44
16
read-only
0
0xFFFF
CAPTVAL1
Capture Value 1
0
16
read-only
SM0CVAL1CYC
Capture Value 1 Cycle Register
0x46
16
read-only
0
0xFFFF
CVAL1CYC
Capture Value 1 Cycle
0
4
read-only
SM0CAPTFILTX
Capture PWM_X Input Filter Register
0x5E
16
read-write
0
0xFFFF
CAPTX_FILT_PER
Input Capture Filter Period
0
8
read-write
CAPTX_FILT_CNT
Input Capture Filter Count
8
3
read-write
SM1CNT
Counter Register
0x60
16
read-only
0
0xFFFF
CNT
Counter Register Bits
0
16
read-only
SM1INIT
Initial Count Register
0x62
16
read-write
0
0xFFFF
INIT
Initial Count Register Bits
0
16
read-write
SM1CTRL2
Control 2 Register
0x64
16
read-write
0
0xFFFF
CLK_SEL
Clock Source Select
0
2
read-write
IPBUS
The IPBus clock is used as the clock for the local prescaler and counter.
0
EXT_CLK
EXT_CLK is used as the clock for the local prescaler and counter.
0x1
AUX_CLK
Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it forces the clock to logic 0.
0x2
RELOAD_SEL
Reload Source Select
2
1
read-write
LOCAL
The local RELOAD signal is used to reload registers.
0
MASTER
The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it forces the RELOAD signal to logic 0.
0x1
FORCE_SEL
Force Select
3
3
read-write
LOCAL
The local force signal, CTRL2[FORCE], from this submodule is used to force updates.
0
MASTER
The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it holds the FORCE OUTPUT signal to logic 0.
0x1
LOCAL_RELOAD
The local reload signal from this submodule is used to force updates without regard to the state of LDOK.
0x2
MASTER_RELOAD
The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0.
0x3
LOCAL_SYNC
The local sync signal from this submodule is used to force updates.
0x4
MASTER_SYNC
The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0.
0x5
EXT_FORCE
The external force signal, EXT_FORCE, from outside the PWM module causes updates.
0x6
EXT_SYNC
The external sync signal, EXT_SYNC, from outside the PWM module causes updates.
0x7
FORCE
Force Initialization
6
1
read-write
FRCEN
Force Enable
7
1
read-write
DISABLED
Initialization from a FORCE_OUT is disabled.
0
ENABLED
Initialization from a FORCE_OUT is enabled.
0x1
INIT_SEL
Initialization Control Select
8
2
read-write
PWM_X
Local sync (PWM_X) causes initialization.
0
MASTER_RELOAD
Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload occurs.
0x1
MASTER_SYNC
Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0.
0x2
EXT_SYNC
EXT_SYNC causes initialization.
0x3
PWMX_INIT
PWM_X Initial Value
10
1
read-write
PWM45_INIT
PWM45 Initial Value
11
1
read-write
PWM23_INIT
PWM23 Initial Value
12
1
read-write
INDEP
Independent or Complementary Pair Operation
13
1
read-write
COMPLEMENTARY
PWM_A and PWM_B form a complementary PWM pair.
0
INDEPENDENT
PWM_A and PWM_B outputs are independent PWMs.
0x1
DBGEN
Debug Enable
15
1
read-write
SM1CTRL
Control Register
0x66
16
read-write
0x400
0xFFFF
DBLEN
Double Switching Enable
0
1
read-write
DISABLED
Double switching disabled.
0
ENABLED
Double switching enabled.
0x1
DBLX
PWM_X Double Switching Enable
1
1
read-write
DISABLED
PWM_X double pulse disabled.
0
ENABLED
PWM_X double pulse enabled.
0x1
LDMOD
Load Mode Select
2
1
read-write
NEXT_PWM_RELOAD
Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set.
0
MTCTRL_LDOK_SET
Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case, it is not necessary to set CTRL[FULL] or CTRL[HALF].
0x1
SPLIT
Split the DBLPWM signal to PWM_A and PWM_B
3
1
read-write
DISABLED
DBLPWM is not split. PWM_A and PWM_B each have double pulses.
0
ENABLED
DBLPWM is split to PWM_A and PWM_B.
0x1
PRSC
Prescaler
4
3
read-write
ONE
Prescaler 1
0
TWO
Prescaler 2
0x1
FOUR
Prescaler 4
0x2
EIGHT
Prescaler 8
0x3
SIXTEEN
Prescaler 16
0x4
THIRTYTWO
Prescaler 32
0x5
SIXTYFOUR
Prescaler 64
0x6
HUNDREDTWENTYEIGHT
Prescaler 128
0x7
COMPMODE
Compare Mode
7
1
read-write
EQUAL_TO
The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period maintains this state until a match with VAL3 clears the output in the following period.
0
EQUAL_TO_OR_GREATER_THAN
The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value.
0x1
DT
Deadtime
8
2
read-only
FULL
Full Cycle Reload
10
1
read-write
DISABLED
Full-cycle reloads disabled.
0
ENABLED
Full-cycle reloads enabled.
0x1
HALF
Half Cycle Reload
11
1
read-write
DISABLED
Half-cycle reloads disabled.
0
ENABLED
Half-cycle reloads enabled.
0x1
LDFQ
Load Frequency
12
4
read-write
EVERYPWM
Every PWM opportunity
0
EVERY2PWM
Every 2 PWM opportunities
0x1
EVERY3PWM
Every 3 PWM opportunities
0x2
EVERY4PWM
Every 4 PWM opportunities
0x3
EVERY5PWM
Every 5 PWM opportunities
0x4
EVERY6PWM
Every 6 PWM opportunities
0x5
EVERY7PWM
Every 7 PWM opportunities
0x6
EVERY8PWM
Every 8 PWM opportunities
0x7
EVERY9PWM
Every 9 PWM opportunities
0x8
EVERY10PWM
Every 10 PWM opportunities
0x9
EVERY11PWM
Every 11 PWM opportunities
0xA
EVERY12PWM
Every 12 PWM opportunities
0xB
EVERY13PWM
Every 13 PWM opportunities
0xC
EVERY14PWM
Every 14 PWM opportunities
0xD
EVERY15PWM
Every 15 PWM opportunities
0xE
EVERY16PWM
Every 16 PWM opportunities
0xF
SM1VAL0
Value Register 0
0x6A
16
read-write
0
0xFFFF
VAL0
Value 0
0
16
read-write
SM1VAL1
Value Register 1
0x6E
16
read-write
0
0xFFFF
VAL1
Value 1
0
16
read-write
SM1VAL2
Value Register 2
0x72
16
read-write
0
0xFFFF
VAL2
Value 2
0
16
read-write
SM1VAL3
Value Register 3
0x76
16
read-write
0
0xFFFF
VAL3
Value 3
0
16
read-write
SM1VAL4
Value Register 4
0x7A
16
read-write
0
0xFFFF
VAL4
Value 4
0
16
read-write
SM1VAL5
Value Register 5
0x7E
16
read-write
0
0xFFFF
VAL5
Value 5
0
16
read-write
SM1OCTRL
Output Control Register
0x82
16
read-write
0
0xFFFF
PWMXFS
PWM_X Fault State
0
2
read-write
LOGIC_0
Output is forced to logic 0 state prior to consideration of output polarity control.
0
LOGIC_1
Output is forced to logic 1 state prior to consideration of output polarity control.
0x1
TRISTATED_2
Output is put in a high-impedance state.
0x2
TRISTATED_3
Output is put in a high-impedance state.
0x3
PWMBFS
PWM_B Fault State
2
2
read-write
LOGIC_0
Output is forced to logic 0 state prior to consideration of output polarity control.
0
LOGIC_1
Output is forced to logic 1 state prior to consideration of output polarity control.
0x1
TRISTATED_2
Output is put in a high-impedance state.
0x2
TRISTATED_3
Output is put in a high-impedance state.
0x3
PWMAFS
PWM_A Fault State
4
2
read-write
LOGIC_0
Output is forced to logic 0 state prior to consideration of output polarity control.
0
LOGIC_1
Output is forced to logic 1 state prior to consideration of output polarity control.
0x1
TRISTATED_2
Output is put in a high-impedance state.
0x2
TRISTATED_3
Output is put in a high-impedance state.
0x3
POLX
PWM_X Output Polarity
8
1
read-write
NOT_INVERTED
PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state.
0
INVERTED
PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state.
0x1
POLB
PWM_B Output Polarity
9
1
read-write
NOT_INVERTED
PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state.
0
INVERTED
PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state.
0x1
POLA
PWM_A Output Polarity
10
1
read-write
NOT_INVERTED
PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state.
0
INVERTED
PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state.
0x1
PWMX_IN
PWM_X Input
13
1
read-only
PWMB_IN
PWM_B Input
14
1
read-only
PWMA_IN
PWM_A Input
15
1
read-only
SM1STS
Status Register
0x84
16
read-write
0
0xFFFF
CMPF
Compare Flags
0
6
read-write
oneToClear
NO_EVENT
No compare event has occurred for a particular VALx value.
0
EVENT
A compare event has occurred for a particular VALx value.
0x1
CFX0
Capture Flag X0
6
1
read-write
oneToClear
CFX1
Capture Flag X1
7
1
read-write
oneToClear
RF
Reload Flag
12
1
read-write
oneToClear
NO_FLAG
No new reload cycle since last STS[RF] clearing
0
FLAG
New reload cycle since last STS[RF] clearing
0x1
REF
Reload Error Flag
13
1
read-write
oneToClear
NO_FLAG
No reload error occurred.
0
FLAG
Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0.
0x1
RUF
Registers Updated Flag
14
1
read-only
NO_FLAG
No register update has occurred since last reload.
0
FLAG
At least one of the double buffered registers has been updated since the last reload.
0x1
SM1INTEN
Interrupt Enable Register
0x86
16
read-write
0
0xFFFF
CMPIE
Compare Interrupt Enables
0
6
read-write
DISABLED
The corresponding STS[CMPF] bit will not cause an interrupt request.
0
ENABLED
The corresponding STS[CMPF] bit will cause an interrupt request.
0x1
CX0IE
Capture X 0 Interrupt Enable
6
1
read-write
DISABLED
Interrupt request disabled for STS[CFX0].
0
ENABLED
Interrupt request enabled for STS[CFX0].
0x1
CX1IE
Capture X 1 Interrupt Enable
7
1
read-write
DISABLED
Interrupt request disabled for STS[CFX1].
0
ENABLED
Interrupt request enabled for STS[CFX1].
0x1
RIE
Reload Interrupt Enable
12
1
read-write
DISABLED
STS[RF] CPU interrupt requests disabled
0
ENABLED
STS[RF] CPU interrupt requests enabled
0x1
REIE
Reload Error Interrupt Enable
13
1
read-write
DISABLED
STS[REF] CPU interrupt requests disabled
0
ENABLED
STS[REF] CPU interrupt requests enabled
0x1
SM1DMAEN
DMA Enable Register
0x88
16
read-write
0
0xFFFF
CX0DE
Capture X0 FIFO DMA Enable
0
1
read-write
CX1DE
Capture X1 FIFO DMA Enable
1
1
read-write
CAPTDE
Capture DMA Enable Source Select
6
2
read-write
DISABLED
Read DMA requests disabled.
0
EXCEEDFIFO
Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to be set to determine which watermark(s) the DMA request is sensitive.
0x1
LOCAL_SYNC
A local synchronization (VAL1 matches counter) sets the read DMA request.
0x2
LOCAL_RELOAD
A local reload (STS[RF] being set) sets the read DMA request.
0x3
FAND
FIFO Watermark AND Control
8
1
read-write
OR
Selected FIFO watermarks are OR'ed together.
0
AND
Selected FIFO watermarks are AND'ed together.
0x1
VALDE
Value Registers DMA Enable
9
1
read-write
DISABLED
DMA write requests disabled
0
ENABLED
Enabled
0x1
SM1TCTRL
Output Trigger Control Register
0x8A
16
read-write
0
0xFFFF
OUT_TRIG_EN
Output Trigger Enables
0
6
read-write
VAL0
PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value.
#xxxxx1
TRGFRQ
Trigger Frequency
12
1
read-write
EVERYPWM
Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.
0
FINALPWM
Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.
0x1
PWBOT1
Mux Output Trigger 1 Source Select
14
1
read-write
PWM_OUT_TRIG1_SIGNAL
Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port.
0
PWMB_OUTPUT
Route the PWM_B output to the PWM_MUX_TRIG1 port.
0x1
PWAOT0
Mux Output Trigger 0 Source Select
15
1
read-write
PWM_OUT_TRIG0_SIGNAL
Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port.
0
PWMA_OUTPUT
Route the PWM_A output to the PWM_MUX_TRIG0 port.
0x1
SM1DISMAP0
Fault Disable Mapping Register 0
0x8C
16
read-write
0xFFFF
0xFFFF
DIS0A
PWM_A Fault Disable Mask 0
0
4
read-write
DIS0B
PWM_B Fault Disable Mask 0
4
4
read-write
DIS0X
PWM_X Fault Disable Mask 0
8
4
read-write
SM1DTCNT0
Deadtime Count Register 0
0x90
16
read-write
0x7FF
0xFFFF
DTCNT0
Deadtime Count Register 0
0
11
read-write
SM1DTCNT1
Deadtime Count Register 1
0x92
16
read-write
0x7FF
0xFFFF
DTCNT1
Deadtime Count Register 1
0
11
read-write
SM1CAPTCTRLX
Capture Control X Register
0x9C
16
read-write
0
0xFFFF
ARMX
Arm X
0
1
read-write
DISABLED
Input capture operation is disabled.
0
ENABLED
Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled.
0x1
ONESHOTX
One Shot Mode Aux
1
1
read-write
FREE_RUNNING
Free Running
0
ONE_SHOT
One Shot
0x1
EDGX0
Edge X 0
2
2
read-write
DISABLED
Disabled
0
FALLING_EDGE
Capture falling edges
0x1
RISING_EDGE
Capture rising edges
0x2
ANY_EDGE
Capture any edge
0x3
EDGX1
Edge X 1
4
2
read-write
DISABLED
Disabled
0
FALLING_EDGE
Capture falling edges
0x1
RISING_EDGE
Capture rising edges
0x2
ANY_EDGE
Capture any edge
0x3
INP_SELX
Input Select X
6
1
read-write
PWM_X
Raw PWM_X input signal selected as source.
0
EDGE_COUNTER
Edge Counter
0x1
EDGCNTX_EN
Edge Counter X Enable
7
1
read-write
DISABLED
Edge counter disabled and held in reset
0
ENABLED
Edge counter enabled
0x1
CFXWM
Capture X FIFOs Water Mark
8
2
read-write
CX0CNT
Capture X0 FIFO Word Count
10
3
read-only
CX1CNT
Capture X1 FIFO Word Count
13
3
read-only
SM1CAPTCOMPX
Capture Compare X Register
0x9E
16
read-write
0
0xFFFF
EDGCMPX
Edge Compare X
0
8
read-write
EDGCNTX
Edge Counter X
8
8
read-only
SM1CVAL0
Capture Value 0 Register
0xA0
16
read-only
0
0xFFFF
CAPTVAL0
Capture Value 0
0
16
read-only
SM1CVAL0CYC
Capture Value 0 Cycle Register
0xA2
16
read-only
0
0xFFFF
CVAL0CYC
Capture Value 0 Cycle
0
4
read-only
SM1CVAL1
Capture Value 1 Register
0xA4
16
read-only
0
0xFFFF
CAPTVAL1
Capture Value 1
0
16
read-only
SM1CVAL1CYC
Capture Value 1 Cycle Register
0xA6
16
read-only
0
0xFFFF
CVAL1CYC
Capture Value 1 Cycle
0
4
read-only
SM1PHASEDLY
Phase Delay Register
0xB8
16
read-write
0
0xFFFF
PHASEDLY
Initial Count Register Bits
0
16
read-write
SM1CAPTFILTX
Capture PWM_X Input Filter Register
0xBE
16
read-write
0
0xFFFF
CAPTX_FILT_PER
Input Capture Filter Period
0
8
read-write
CAPTX_FILT_CNT
Input Capture Filter Count
8
3
read-write
SM2CNT
Counter Register
0xC0
16
read-only
0
0xFFFF
CNT
Counter Register Bits
0
16
read-only
SM2INIT
Initial Count Register
0xC2
16
read-write
0
0xFFFF
INIT
Initial Count Register Bits
0
16
read-write
SM2CTRL2
Control 2 Register
0xC4
16
read-write
0
0xFFFF
CLK_SEL
Clock Source Select
0
2
read-write
IPBUS
The IPBus clock is used as the clock for the local prescaler and counter.
0
EXT_CLK
EXT_CLK is used as the clock for the local prescaler and counter.
0x1
AUX_CLK
Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it forces the clock to logic 0.
0x2
RELOAD_SEL
Reload Source Select
2
1
read-write
LOCAL
The local RELOAD signal is used to reload registers.
0
MASTER
The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it forces the RELOAD signal to logic 0.
0x1
FORCE_SEL
Force Select
3
3
read-write
LOCAL
The local force signal, CTRL2[FORCE], from this submodule is used to force updates.
0
MASTER
The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it holds the FORCE OUTPUT signal to logic 0.
0x1
LOCAL_RELOAD
The local reload signal from this submodule is used to force updates without regard to the state of LDOK.
0x2
MASTER_RELOAD
The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0.
0x3
LOCAL_SYNC
The local sync signal from this submodule is used to force updates.
0x4
MASTER_SYNC
The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0.
0x5
EXT_FORCE
The external force signal, EXT_FORCE, from outside the PWM module causes updates.
0x6
EXT_SYNC
The external sync signal, EXT_SYNC, from outside the PWM module causes updates.
0x7
FORCE
Force Initialization
6
1
read-write
FRCEN
Force Enable
7
1
read-write
DISABLED
Initialization from a FORCE_OUT is disabled.
0
ENABLED
Initialization from a FORCE_OUT is enabled.
0x1
INIT_SEL
Initialization Control Select
8
2
read-write
PWM_X
Local sync (PWM_X) causes initialization.
0
MASTER_RELOAD
Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload occurs.
0x1
MASTER_SYNC
Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0.
0x2
EXT_SYNC
EXT_SYNC causes initialization.
0x3
PWMX_INIT
PWM_X Initial Value
10
1
read-write
PWM45_INIT
PWM45 Initial Value
11
1
read-write
PWM23_INIT
PWM23 Initial Value
12
1
read-write
INDEP
Independent or Complementary Pair Operation
13
1
read-write
COMPLEMENTARY
PWM_A and PWM_B form a complementary PWM pair.
0
INDEPENDENT
PWM_A and PWM_B outputs are independent PWMs.
0x1
DBGEN
Debug Enable
15
1
read-write
SM2CTRL
Control Register
0xC6
16
read-write
0x400
0xFFFF
DBLEN
Double Switching Enable
0
1
read-write
DISABLED
Double switching disabled.
0
ENABLED
Double switching enabled.
0x1
DBLX
PWM_X Double Switching Enable
1
1
read-write
DISABLED
PWM_X double pulse disabled.
0
ENABLED
PWM_X double pulse enabled.
0x1
LDMOD
Load Mode Select
2
1
read-write
NEXT_PWM_RELOAD
Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set.
0
MTCTRL_LDOK_SET
Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case, it is not necessary to set CTRL[FULL] or CTRL[HALF].
0x1
SPLIT
Split the DBLPWM signal to PWM_A and PWM_B
3
1
read-write
DISABLED
DBLPWM is not split. PWM_A and PWM_B each have double pulses.
0
ENABLED
DBLPWM is split to PWM_A and PWM_B.
0x1
PRSC
Prescaler
4
3
read-write
ONE
Prescaler 1
0
TWO
Prescaler 2
0x1
FOUR
Prescaler 4
0x2
EIGHT
Prescaler 8
0x3
SIXTEEN
Prescaler 16
0x4
THIRTYTWO
Prescaler 32
0x5
SIXTYFOUR
Prescaler 64
0x6
HUNDREDTWENTYEIGHT
Prescaler 128
0x7
COMPMODE
Compare Mode
7
1
read-write
EQUAL_TO
The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period maintains this state until a match with VAL3 clears the output in the following period.
0
EQUAL_TO_OR_GREATER_THAN
The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value.
0x1
DT
Deadtime
8
2
read-only
FULL
Full Cycle Reload
10
1
read-write
DISABLED
Full-cycle reloads disabled.
0
ENABLED
Full-cycle reloads enabled.
0x1
HALF
Half Cycle Reload
11
1
read-write
DISABLED
Half-cycle reloads disabled.
0
ENABLED
Half-cycle reloads enabled.
0x1
LDFQ
Load Frequency
12
4
read-write
EVERYPWM
Every PWM opportunity
0
EVERY2PWM
Every 2 PWM opportunities
0x1
EVERY3PWM
Every 3 PWM opportunities
0x2
EVERY4PWM
Every 4 PWM opportunities
0x3
EVERY5PWM
Every 5 PWM opportunities
0x4
EVERY6PWM
Every 6 PWM opportunities
0x5
EVERY7PWM
Every 7 PWM opportunities
0x6
EVERY8PWM
Every 8 PWM opportunities
0x7
EVERY9PWM
Every 9 PWM opportunities
0x8
EVERY10PWM
Every 10 PWM opportunities
0x9
EVERY11PWM
Every 11 PWM opportunities
0xA
EVERY12PWM
Every 12 PWM opportunities
0xB
EVERY13PWM
Every 13 PWM opportunities
0xC
EVERY14PWM
Every 14 PWM opportunities
0xD
EVERY15PWM
Every 15 PWM opportunities
0xE
EVERY16PWM
Every 16 PWM opportunities
0xF
SM2VAL0
Value Register 0
0xCA
16
read-write
0
0xFFFF
VAL0
Value 0
0
16
read-write
SM2VAL1
Value Register 1
0xCE
16
read-write
0
0xFFFF
VAL1
Value 1
0
16
read-write
SM2VAL2
Value Register 2
0xD2
16
read-write
0
0xFFFF
VAL2
Value 2
0
16
read-write
SM2VAL3
Value Register 3
0xD6
16
read-write
0
0xFFFF
VAL3
Value 3
0
16
read-write
SM2VAL4
Value Register 4
0xDA
16
read-write
0
0xFFFF
VAL4
Value 4
0
16
read-write
SM2VAL5
Value Register 5
0xDE
16
read-write
0
0xFFFF
VAL5
Value 5
0
16
read-write
SM2OCTRL
Output Control Register
0xE2
16
read-write
0
0xFFFF
PWMXFS
PWM_X Fault State
0
2
read-write
LOGIC_0
Output is forced to logic 0 state prior to consideration of output polarity control.
0
LOGIC_1
Output is forced to logic 1 state prior to consideration of output polarity control.
0x1
TRISTATED_2
Output is put in a high-impedance state.
0x2
TRISTATED_3
Output is put in a high-impedance state.
0x3
PWMBFS
PWM_B Fault State
2
2
read-write
LOGIC_0
Output is forced to logic 0 state prior to consideration of output polarity control.
0
LOGIC_1
Output is forced to logic 1 state prior to consideration of output polarity control.
0x1
TRISTATED_2
Output is put in a high-impedance state.
0x2
TRISTATED_3
Output is put in a high-impedance state.
0x3
PWMAFS
PWM_A Fault State
4
2
read-write
LOGIC_0
Output is forced to logic 0 state prior to consideration of output polarity control.
0
LOGIC_1
Output is forced to logic 1 state prior to consideration of output polarity control.
0x1
TRISTATED_2
Output is put in a high-impedance state.
0x2
TRISTATED_3
Output is put in a high-impedance state.
0x3
POLX
PWM_X Output Polarity
8
1
read-write
NOT_INVERTED
PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state.
0
INVERTED
PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state.
0x1
POLB
PWM_B Output Polarity
9
1
read-write
NOT_INVERTED
PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state.
0
INVERTED
PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state.
0x1
POLA
PWM_A Output Polarity
10
1
read-write
NOT_INVERTED
PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state.
0
INVERTED
PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state.
0x1
PWMX_IN
PWM_X Input
13
1
read-only
PWMB_IN
PWM_B Input
14
1
read-only
PWMA_IN
PWM_A Input
15
1
read-only
SM2STS
Status Register
0xE4
16
read-write
0
0xFFFF
CMPF
Compare Flags
0
6
read-write
oneToClear
NO_EVENT
No compare event has occurred for a particular VALx value.
0
EVENT
A compare event has occurred for a particular VALx value.
0x1
CFX0
Capture Flag X0
6
1
read-write
oneToClear
CFX1
Capture Flag X1
7
1
read-write
oneToClear
RF
Reload Flag
12
1
read-write
oneToClear
NO_FLAG
No new reload cycle since last STS[RF] clearing
0
FLAG
New reload cycle since last STS[RF] clearing
0x1
REF
Reload Error Flag
13
1
read-write
oneToClear
NO_FLAG
No reload error occurred.
0
FLAG
Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0.
0x1
RUF
Registers Updated Flag
14
1
read-only
NO_FLAG
No register update has occurred since last reload.
0
FLAG
At least one of the double buffered registers has been updated since the last reload.
0x1
SM2INTEN
Interrupt Enable Register
0xE6
16
read-write
0
0xFFFF
CMPIE
Compare Interrupt Enables
0
6
read-write
DISABLED
The corresponding STS[CMPF] bit will not cause an interrupt request.
0
ENABLED
The corresponding STS[CMPF] bit will cause an interrupt request.
0x1
CX0IE
Capture X 0 Interrupt Enable
6
1
read-write
DISABLED
Interrupt request disabled for STS[CFX0].
0
ENABLED
Interrupt request enabled for STS[CFX0].
0x1
CX1IE
Capture X 1 Interrupt Enable
7
1
read-write
DISABLED
Interrupt request disabled for STS[CFX1].
0
ENABLED
Interrupt request enabled for STS[CFX1].
0x1
RIE
Reload Interrupt Enable
12
1
read-write
DISABLED
STS[RF] CPU interrupt requests disabled
0
ENABLED
STS[RF] CPU interrupt requests enabled
0x1
REIE
Reload Error Interrupt Enable
13
1
read-write
DISABLED
STS[REF] CPU interrupt requests disabled
0
ENABLED
STS[REF] CPU interrupt requests enabled
0x1
SM2DMAEN
DMA Enable Register
0xE8
16
read-write
0
0xFFFF
CX0DE
Capture X0 FIFO DMA Enable
0
1
read-write
CX1DE
Capture X1 FIFO DMA Enable
1
1
read-write
CAPTDE
Capture DMA Enable Source Select
6
2
read-write
DISABLED
Read DMA requests disabled.
0
EXCEEDFIFO
Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to be set to determine which watermark(s) the DMA request is sensitive.
0x1
LOCAL_SYNC
A local synchronization (VAL1 matches counter) sets the read DMA request.
0x2
LOCAL_RELOAD
A local reload (STS[RF] being set) sets the read DMA request.
0x3
FAND
FIFO Watermark AND Control
8
1
read-write
OR
Selected FIFO watermarks are OR'ed together.
0
AND
Selected FIFO watermarks are AND'ed together.
0x1
VALDE
Value Registers DMA Enable
9
1
read-write
DISABLED
DMA write requests disabled
0
ENABLED
Enabled
0x1
SM2TCTRL
Output Trigger Control Register
0xEA
16
read-write
0
0xFFFF
OUT_TRIG_EN
Output Trigger Enables
0
6
read-write
VAL0
PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value.
#xxxxx1
TRGFRQ
Trigger Frequency
12
1
read-write
EVERYPWM
Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.
0
FINALPWM
Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.
0x1
PWBOT1
Mux Output Trigger 1 Source Select
14
1
read-write
PWM_OUT_TRIG1_SIGNAL
Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port.
0
PWMB_OUTPUT
Route the PWM_B output to the PWM_MUX_TRIG1 port.
0x1
PWAOT0
Mux Output Trigger 0 Source Select
15
1
read-write
PWM_OUT_TRIG0_SIGNAL
Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port.
0
PWMA_OUTPUT
Route the PWM_A output to the PWM_MUX_TRIG0 port.
0x1
SM2DISMAP0
Fault Disable Mapping Register 0
0xEC
16
read-write
0xFFFF
0xFFFF
DIS0A
PWM_A Fault Disable Mask 0
0
4
read-write
DIS0B
PWM_B Fault Disable Mask 0
4
4
read-write
DIS0X
PWM_X Fault Disable Mask 0
8
4
read-write
SM2DTCNT0
Deadtime Count Register 0
0xF0
16
read-write
0x7FF
0xFFFF
DTCNT0
Deadtime Count Register 0
0
11
read-write
SM2DTCNT1
Deadtime Count Register 1
0xF2
16
read-write
0x7FF
0xFFFF
DTCNT1
Deadtime Count Register 1
0
11
read-write
SM2CAPTCTRLX
Capture Control X Register
0xFC
16
read-write
0
0xFFFF
ARMX
Arm X
0
1
read-write
DISABLED
Input capture operation is disabled.
0
ENABLED
Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled.
0x1
ONESHOTX
One Shot Mode Aux
1
1
read-write
FREE_RUNNING
Free Running
0
ONE_SHOT
One Shot
0x1
EDGX0
Edge X 0
2
2
read-write
DISABLED
Disabled
0
FALLING_EDGE
Capture falling edges
0x1
RISING_EDGE
Capture rising edges
0x2
ANY_EDGE
Capture any edge
0x3
EDGX1
Edge X 1
4
2
read-write
DISABLED
Disabled
0
FALLING_EDGE
Capture falling edges
0x1
RISING_EDGE
Capture rising edges
0x2
ANY_EDGE
Capture any edge
0x3
INP_SELX
Input Select X
6
1
read-write
PWM_X
Raw PWM_X input signal selected as source.
0
EDGE_COUNTER
Edge Counter
0x1
EDGCNTX_EN
Edge Counter X Enable
7
1
read-write
DISABLED
Edge counter disabled and held in reset
0
ENABLED
Edge counter enabled
0x1
CFXWM
Capture X FIFOs Water Mark
8
2
read-write
CX0CNT
Capture X0 FIFO Word Count
10
3
read-only
CX1CNT
Capture X1 FIFO Word Count
13
3
read-only
SM2CAPTCOMPX
Capture Compare X Register
0xFE
16
read-write
0
0xFFFF
EDGCMPX
Edge Compare X
0
8
read-write
EDGCNTX
Edge Counter X
8
8
read-only
SM2CVAL0
Capture Value 0 Register
0x100
16
read-only
0
0xFFFF
CAPTVAL0
Capture Value 0
0
16
read-only
SM2CVAL0CYC
Capture Value 0 Cycle Register
0x102
16
read-only
0
0xFFFF
CVAL0CYC
Capture Value 0 Cycle
0
4
read-only
SM2CVAL1
Capture Value 1 Register
0x104
16
read-only
0
0xFFFF
CAPTVAL1
Capture Value 1
0
16
read-only
SM2CVAL1CYC
Capture Value 1 Cycle Register
0x106
16
read-only
0
0xFFFF
CVAL1CYC
Capture Value 1 Cycle
0
4
read-only
SM2PHASEDLY
Phase Delay Register
0x118
16
read-write
0
0xFFFF
PHASEDLY
Initial Count Register Bits
0
16
read-write
SM2CAPTFILTX
Capture PWM_X Input Filter Register
0x11E
16
read-write
0
0xFFFF
CAPTX_FILT_PER
Input Capture Filter Period
0
8
read-write
CAPTX_FILT_CNT
Input Capture Filter Count
8
3
read-write
OUTEN
Output Enable Register
0x180
16
read-write
0
0xFFFF
PWMX_EN
PWM_X Output Enables
0
3
read-write
PWMB_EN
PWM_B Output Enables
4
3
read-write
PWMA_EN
PWM_A Output Enables
8
3
read-write
MASK
Mask Register
0x182
16
read-write
0
0xFFFF
MASKX
PWM_X Masks
0
3
read-write
MASKB
PWM_B Masks
4
3
read-write
MASKA
PWM_A Masks
8
3
read-write
UPDATE_MASK
Update Mask Bits Immediately
12
3
write-only
SWCOUT
Software Controlled Output Register
0x184
16
read-write
0
0xFFFF
SM0OUT45
Submodule 0 Software Controlled Output 45
0
1
read-write
LOGIC_0
A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45.
0
LOGIC_1
A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45.
0x1
SM0OUT23
Submodule 0 Software Controlled Output 23
1
1
read-write
LOGIC_0
A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23.
0
LOGIC_1
A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23.
0x1
SM1OUT45
Submodule 1 Software Controlled Output 45
2
1
read-write
LOGIC_0
A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45.
0
LOGIC_1
A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45.
0x1
SM1OUT23
Submodule 1 Software Controlled Output 23
3
1
read-write
LOGIC_0
A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23.
0
LOGIC_1
A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23.
0x1
SM2OUT45
Submodule 2 Software Controlled Output 45
4
1
read-write
LOGIC_0
A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45.
0
LOGIC_1
A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45.
0x1
SM2OUT23
Submodule 2 Software Controlled Output 23
5
1
read-write
LOGIC_0
A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23.
0
LOGIC_1
A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23.
0x1
DTSRCSEL
PWM Source Select Register
0x186
16
read-write
0
0xFFFF
SM0SEL45
Submodule 0 PWM45 Control Select
0
2
read-write
SM0PWM45
Generated SM0PWM45 signal used by the deadtime logic.
0
INVERTED_SM0PWM45
Inverted generated SM0PWM45 signal used by the deadtime logic.
0x1
SM0OUT45
SWCOUT[SM0OUT45] used by the deadtime logic.
0x2
SM0SEL23
Submodule 0 PWM23 Control Select
2
2
read-write
SM0PWM23
Generated SM0PWM23 signal used by the deadtime logic.
0
INVERTED_SM0PWM23
Inverted generated SM0PWM23 signal used by the deadtime logic.
0x1
SM0OUT23
SWCOUT[SM0OUT23] used by the deadtime logic.
0x2
PWM0_EXTA
PWM0_EXTA signal used by the deadtime logic.
0x3
SM1SEL45
Submodule 1 PWM45 Control Select
4
2
read-write
SM1PWM45
Generated SM1PWM45 signal used by the deadtime logic.
0
INVERTED_SM1PWM45
Inverted generated SM1PWM45 signal used by the deadtime logic.
0x1
SM1OUT45
SWCOUT[SM1OUT45] used by the deadtime logic.
0x2
SM1SEL23
Submodule 1 PWM23 Control Select
6
2
read-write
SM1PWM23
Generated SM1PWM23 signal used by the deadtime logic.
0
INVERTED_SM1PWM23
Inverted generated SM1PWM23 signal used by the deadtime logic.
0x1
SM1OUT23
SWCOUT[SM1OUT23] used by the deadtime logic.
0x2
PWM1_EXTA
PWM1_EXTA signal used by the deadtime logic.
0x3
SM2SEL45
Submodule 2 PWM45 Control Select
8
2
read-write
SM2PWM45
Generated SM2PWM45 signal used by the deadtime logic.
0
INVERTED_SM2PWM45
Inverted generated SM2PWM45 signal used by the deadtime logic.
0x1
SM2OUT45
SWCOUT[SM2OUT45] used by the deadtime logic.
0x2
SM2SEL23
Submodule 2 PWM23 Control Select
10
2
read-write
SM2PWM23
Generated SM2PWM23 signal used by the deadtime logic.
0
INVERTED_SM2PWM23
Inverted generated SM2PWM23 signal used by the deadtime logic.
0x1
SM2OUT23
SWCOUT[SM2OUT23] used by the deadtime logic.
0x2
PWM2_EXTA
PWM2_EXTA signal used by the deadtime logic.
0x3
MCTRL
Master Control Register
0x188
16
read-write
0
0xFFFF
LDOK
Load Okay
0
3
read-write
DISABLED
Do not load new values.
0
ENABLED
Load prescaler, modulus, and PWM values of the corresponding submodule.
0x1
CLDOK
Clear Load Okay
4
3
read-write
RUN
Run
8
3
read-write
DISABLED
PWM counter is stopped, but PWM outputs hold the current state.
0
ENABLED
PWM counter is started in the corresponding submodule.
0x1
IPOL
Current Polarity
12
3
read-write
PWM23
PWM23 is used to generate complementary PWM pair in the corresponding submodule.
0
PWM45
PWM45 is used to generate complementary PWM pair in the corresponding submodule.
0x1
MCTRL2
Master Control 2 Register
0x18A
16
read-write
0
0xFFFF
WRPROT
Write protect
2
2
read-write
DISABLED
Write protection off (default).
0
ENABLED
Write protection on.
0x1
DISABLED_LOCKED
Write protection off and locked until chip reset.
0x2
ENABLED_LOCKED
Write protection on and locked until chip reset.
0x3
STRETCH_CNT_PRSC
Stretch IPBus clock count prescaler for mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig
6
2
read-write
DISABLED
Stretch count is zero, no stretch.
0
ENABLED
Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 2 IPBus clock period.
0x1
DISABLED_LOCKED
Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 4 IPBus clock period.
0x2
ENABLED_LOCKED
Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 8 IPBus clock period.
0x3
FCTRL0
Fault Control Register
0x18C
16
read-write
0
0xFFFF
FIE
Fault Interrupt Enables
0
4
read-write
DISABLED
FAULTx CPU interrupt requests disabled.
0
ENABLED
FAULTx CPU interrupt requests enabled.
0x1
FSAFE
Fault Safety Mode
4
4
read-write
NORMAL
Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without regard to the state of FSTS[FFPINx]. If neither FHALF nor FFULL is set, then the fault condition cannot be cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in DISMAPn).
0
SAFE
Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared.
0x1
FAUTO
Automatic Fault Clearing
8
4
read-write
MANUAL
Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled by FCTRL[FSAFE].
0
AUTOMATIC
Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without regard to the state of FSTS[FFLAGx]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared.
0x1
FLVL
Fault Level
12
4
read-write
LOGIC_0
A logic 0 on the fault input indicates a fault condition.
0
LOGIC_1
A logic 1 on the fault input indicates a fault condition.
0x1
FSTS0
Fault Status Register
0x18E
16
read-write
0
0xF0F0
FFLAG
Fault Flags
0
4
read-write
NO_FLAG
No fault on the FAULTx pin.
0
FLAG
Fault on the FAULTx pin.
0x1
FFULL
Full Cycle
4
4
read-write
PWM_OUTPUTS_NOT_REENABLED
PWM outputs are not re-enabled at the start of a full cycle
0
PWM_OUTPUTS_REENABLED
PWM outputs are re-enabled at the start of a full cycle
0x1
FFPIN
Filtered Fault Pins
8
4
read-only
FHALF
Half Cycle Fault Recovery
12
4
read-write
PWM_OUTPUTS_NOT_REENABLED
PWM outputs are not re-enabled at the start of a half cycle.
0
PWM_OUTPUTS_REENABLED
PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0).
0x1
FFILT0
Fault Filter Register
0x190
16
read-write
0
0xFFFF
FILT_PER
Fault Filter Period
0
8
read-write
FILT_CNT
Fault Filter Count
8
3
read-write
GSTR
Fault Glitch Stretch Enable
15
1
read-write
DISABLED
Fault input glitch stretching is disabled.
0
ENABLED
Input fault signals are stretched to at least 2 IPBus clock cycles.
0x1
FTST0
Fault Test Register
0x192
16
read-write
0
0xFFFF
FTEST
Fault Test
0
1
read-write
NO_FAULT
No fault
0
FAULT
Cause a simulated fault
0x1
FCTRL20
Fault Control 2 Register
0x194
16
read-write
0
0xFFFF
NOCOMB
No Combinational Path From Fault Input To PWM Output
0
4
read-write
ENABLED
There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined with the filtered and latched fault signals to disable the PWM outputs.
0
DISABLED
The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered and latched fault signals are used to disable the PWM outputs.
0x1
LPTMR0
LPTMR
LPTMR
0x400AB000
0
0x10
registers
LPTMR0
55
CSR
Control Status
0
32
read-write
0
0xFFFFFFFF
TEN
Timer Enable
0
1
read-write
ten0
Disable
0
ten1
Enable
0x1
TMS
Timer Mode Select
1
1
read-write
tms0
Time Counter
0
tms1
Pulse Counter
0x1
TFC
Timer Free-Running Counter
2
1
read-write
tfc0
Reset when TCF asserts
0
tfc1
Reset on overflow
0x1
TPP
Timer Pin Polarity
3
1
read-write
tpp0
Active-high
0
tpp1
Active-low
0x1
TPS
Timer Pin Select
4
2
read-write
tps00
Input 0
0
tps01
Input 1
0x1
tps10
Input 2
0x2
tps11
Input 3
0x3
TIE
Timer Interrupt Enable
6
1
read-write
tie0
Disable
0
tie1
Enable
0x1
TCF
Timer Compare Flag
7
1
read-write
oneToClear
read
tcf0
CNR != (CMR + 1)
0
tcf1
CNR = (CMR + 1)
0x1
TDRE
Timer DMA Request Enable
8
1
read-write
trde0
Disable
0
trde1
Enable
0x1
PSR
Prescaler and Glitch Filter
0x4
32
read-write
0
0xFFFFFFFF
PCS
Prescaler and Glitch Filter Clock Select
0
2
read-write
pcs00
Clock 0
0
pcs01
Clock 1
0x1
pcs10
Clock 2
0x2
pcs11
Clock 3
0x3
PBYP
Prescaler and Glitch Filter Bypass
2
1
read-write
pbyp0
Prescaler and glitch filter enable
0
pbyp1
Prescaler and glitch filter bypass
0x1
PRESCALE
Prescaler and Glitch Filter Value
3
4
read-write
prescale0000
Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration
0
prescale0001
Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after two rising clock edges
0x1
prescale0010
Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after four rising clock edges
0x2
prescale0011
Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after eight rising clock edges
0x3
prescale0100
Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges
0x4
prescale0101
Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges
0x5
prescale0110
Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges
0x6
prescale0111
Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges
0x7
prescale1000
Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges
0x8
prescale1001
Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges
0x9
prescale1010
Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges
0xA
prescale1011
Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges
0xB
prescale1100
Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges
0xC
prescale1101
Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges
0xD
prescale1110
Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges
0xE
prescale1111
Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges
0xF
CMR
Compare
0x8
32
read-write
0
0xFFFFFFFF
COMPARE
Compare Value
0
32
read-write
CNR
Counter
0xC
32
read-write
0
0xFFFFFFFF
COUNTER
Counter Value
0
32
read-write
OSTIMER0
OSTIMER
OSTIMER
0x400AD000
0
0x20
registers
OS_EVENT
57
EVTIMERL
EVTIMER Low
0
32
read-only
0
0xFFFFFFFF
EVTIMER_COUNT_VALUE
EVTimer Count Value
0
32
read-only
EVTIMERH
EVTIMER High
0x4
32
read-only
0
0xFFFFFFFF
EVTIMER_COUNT_VALUE
EVTimer Count Value
0
10
read-only
CAPTURE_L
Local Capture Low for CPU
0x8
32
read-only
0
0xFFFFFFFF
CAPTURE_VALUE
EVTimer Capture Value
0
32
read-only
CAPTURE_H
Local Capture High for CPU
0xC
32
read-only
0
0xFFFFFFFF
CAPTURE_VALUE
EVTimer Capture Value
0
10
read-only
MATCH_L
Local Match Low for CPU
0x10
32
read-write
0xFFFFFFFF
0xFFFFFFFF
MATCH_VALUE
EVTimer Match Value
0
32
read-write
MATCH_H
Local Match High for CPU
0x14
32
read-write
0xFFFFFFFF
0xFFFFFFFF
MATCH_VALUE
EVTimer Match Value
0
10
read-write
OSEVENT_CTRL
OSTIMER Control for CPU
0x1C
32
read-write
0x8
0xFFFFFFFF
OSTIMER_INTRFLAG
Interrupt Flag
0
1
read-write
oneToClear
OSTIMER_INTENA
Interrupt or Wake-Up Request
1
1
read-write
INTERRUPTS_BLOCKED
Interrupts blocked
0
INTERRUPTS_ENABLED
Interrupts enabled
0x1
MATCH_WR_RDY
EVTimer Match Write Ready
2
1
read-only
DEBUG_EN
Debug Enable
3
1
read-write
DISABLE
Disables
0
ENABLE
Enables
0x1
WAKETIMER0
WAKEUP_TIMER
WAKETIMER
0x400AE000
0
0x10
registers
WAKETIMER0
58
WAKE_TIMER_CTRL
Wake Timer Control
0
32
read-write
0
0xFFFFFFFF
WAKE_FLAG
Wake Timer Status Flag
1
1
read-write
oneToClear
DISABLE
Wake timer has not timed out.
0
ENABLE
Wake timer has timed out.
0x1
CLR_WAKE_TIMER
Clear Wake Timer
2
1
write-only
DISABLE
No effect.
0
ENABLE
Clears the wake timer counter and halts operation until a new count value is loaded.
0x1
OSC_DIV_ENA
OSC Divide Enable
4
1
read-write
DISABLE
Disabled
0
ENABLE
Enabled
0x1
INTR_EN
Enable Interrupt
5
1
read-write
DISABLE
Disabled
0
ENABLE
Enabled
0x1
WAKE_TIMER_CNT
Wake Timer Counter
0xC
32
read-write
0
0xFFFFFFFF
WAKE_CNT
Wake Counter
0
32
read-write
ADC0
ADC
HSADC
0x400AF000
0
0xFFC
registers
ADC0
62
VERID
Version ID Register
0
32
read-only
0x2001409
0xFFFFFFFF
RES
Resolution
0
1
read-only
MAX_13_bit
Up to 12-bit single ended resolution supported (and 13-bit differential resolution if VERID[DIFFEN] = 1b).
0
MAX_16_bit
Up to 16-bit single ended resolution supported (and 16-bit differential resolution if VERID[DIFFEN] = 1b).
0x1
DIFFEN
Differential Supported
1
1
read-only
DIFFERENTIAL_NOT_SUPPORTED
Differential operation not supported.
0
DIFFERENTIAL_SUPPORTED
Differential operation supported.
0x1
MVI
Multi Vref Implemented
3
1
read-only
MULTIPLE_REF_NOT_SUPPORTED
Single voltage reference high (VREFH) input supported.
0
MULTIPLE_REF_SUPPORTED
Multiple voltage reference high (VREFH) inputs supported.
0x1
CSW
Channel Scale Width
4
3
read-only
CSCALE_NOT_SUPPORTED
Channel scaling not supported.
0
BIT_WIDTH_1
Channel scaling supported. 1-bit CSCALE control field.
0x1
BIT_WIDTH_6
Channel scaling supported. 6-bit CSCALE control field.
0x6
VR1RNGI
Voltage Reference 1 Range Control Bit Implemented
8
1
read-only
REF1_FIXED_VOLTAGE_RANGE
Range control not required. CFG[VREF1RNG] is not implemented.
0
REF1_SELECTABLE_VOLTAGE_RANGE
Range control required. CFG[VREF1RNG] is implemented.
0x1
IADCKI
Internal ADC Clock Implemented
9
1
read-only
INTERNAL_CLK_NOT_AVAILABLE
Internal clock source not implemented.
0
INTERNAL_CLK_AVAILABLE
Internal clock source (and CFG[ADCKEN]) implemented.
0x1
CALOFSI
Calibration Function Implemented
10
1
read-only
CAL_FUNCTION_NOT_AVAILABLE
Calibration Not Implemented.
0
CAL_FUNCTION_AVAILABLE
Calibration Implemented.
0x1
NUM_SEC
Number of Single Ended Outputs Supported
11
1
read-only
SINGLE_CONVERTOR
This design supports one single ended conversion at a time.
0
DUAL_CONVERTOR
This design supports two simultaneous single ended conversions.
0x1
NUM_FIFO
Number of FIFOs
12
3
read-only
NO_FIFO_IMPLEMENTED
N/A
0
CNT_1
This design supports one result FIFO.
0x1
CNT_2
This design supports two result FIFOs.
0x2
CNT_3
This design supports three result FIFOs.
0x3
CNT_4
This design supports four result FIFOs.
0x4
MINOR
Minor Version Number
16
8
read-only
MAJOR
Major Version Number
24
8
read-only
PARAM
Parameter Register
0x4
32
read-only
0x70F0804
0xFFFFFFFF
TRIG_NUM
Trigger Number
0
8
read-only
FIFOSIZE
Result FIFO Depth
8
8
read-only
ENTRIES_2
Result FIFO depth = 2 dataword.
0x1
ENTRIES_4
Result FIFO depth = 4 datawords.
0x4
ENTRIES_8
Result FIFO depth = 8 datawords.
0x8
ENTRIES_16
Result FIFO depth = 16 datawords.
0x10
ENTRIES_32
Result FIFO depth = 32 datawords.
0x20
ENTRIES_64
Result FIFO depth = 64 datawords.
0x40
CV_NUM
Compare Value Number
16
8
read-only
CMD_NUM
Command Buffer Number
24
8
read-only
CTRL
Control Register
0x10
32
read-write
0
0xFFFFFFFF
ADCEN
ADC Enable
0
1
read-write
DISABLED
ADC is disabled.
0
ENABLED
ADC is enabled.
0x1
RST
Software Reset
1
1
read-write
RELEASED_FROM_RESET
ADC logic is not reset.
0
HELD_IN_RESET
ADC logic is reset.
0x1
DOZEN
Doze Enable
2
1
read-write
ENABLED
ADC is enabled in low power mode.
0
DISABLED
ADC is disabled in low power mode.
0x1
CAL_REQ
Auto-Calibration Request
3
1
read-write
NO_CALIBRATION_REQUEST
No request for hardware calibration has been made
0
CALIBRATION_REQUEST_PENDING
A request for hardware calibration has been made
0x1
CALOFS
Offset Calibration Request
4
1
read-write
NO_ACTIVE_OFFSET_CALIBRATION_REQUEST
No request for offset calibration has been made
0
OFFSET_CALIBRATION_REQUEST_PENDING
Request for offset calibration function
0x1
CALHS
High Speed Mode Trim Request
6
1
read-write
NO_ACTIVE_HS_TRIM_REQUEST
No request for high speed mode trim has been made
0
HS_TRIM_REQUEST_PENDING
Request for high speed mode trim has been made
0x1
RSTFIFO0
Reset FIFO 0
8
1
read-write
NO_ACTION
No effect.
0
TRIGGER_RESET
FIFO 0 is reset.
0x1
CAL_AVGS
Auto-Calibration Averages
16
4
read-write
NO_AVERAGE
Single conversion.
0
AVERAGE_2
2 conversions averaged.
0x1
AVERAGE_4
4 conversions averaged.
0x2
AVERAGE_8
8 conversions averaged.
0x3
AVERAGE_16
16 conversions averaged.
0x4
AVERAGE_32
32 conversions averaged.
0x5
AVERAGE_64
64 conversions averaged.
0x6
AVERAGE_128
128 conversions averaged.
0x7
AVERAGE_256
256 conversions averaged.
0x8
AVERAGE_512
512 conversions averaged.
0x9
AVERAGE_1024
1024 conversions averaged.
0xA
STAT
Status Register
0x14
32
read-write
0
0xFFFFFFFF
RDY0
Result FIFO 0 Ready Flag
0
1
read-only
BELOW_THRESHOLD
Result FIFO 0 data level not above watermark level.
0
ABOVE_THRESHOLD
Result FIFO 0 holding data above watermark level.
0x1
FOF0
Result FIFO 0 Overflow Flag
1
1
read-write
oneToClear
NO_OVERFLOW
No result FIFO 0 overflow has occurred since the last time the flag was cleared.
0
OVERFLOW_DETECTED
At least one result FIFO 0 overflow has occurred since the last time the flag was cleared.
0x1
TEXC_INT
Interrupt Flag For High Priority Trigger Exception
8
1
read-write
oneToClear
NO_EXCEPTION
No trigger exceptions have occurred.
0
EXCEPTION_DETECTED
A trigger exception has occurred and is pending acknowledgement.
0x1
TCOMP_INT
Interrupt Flag For Trigger Completion
9
1
read-write
oneToClear
FLAG_CLEAR
Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion.
0
COMPLETION_DETECTED
Trigger sequence has been completed and all data is stored in the associated FIFO.
0x1
CAL_RDY
Calibration Ready
10
1
read-only
NOT_SET
Calibration is incomplete or hasn't been ran.
0
HARDWARE_CAL_STEP_COMPLETED
The ADC is calibrated.
0x1
ADC_ACTIVE
ADC Active
11
1
read-only
NOT_ACTIVE
The ADC is IDLE. There are no pending triggers to service and no active commands are being processed.
0
BUSY
The ADC is processing a conversion, running through the power up delay, or servicing a trigger.
0x1
TRGACT
Trigger Active
16
2
read-only
TRIG_0
Command (sequence) associated with Trigger 0 currently being executed.
0
TRIG_1
Command (sequence) associated with Trigger 1 currently being executed.
0x1
TRIG_2
Command (sequence) associated with Trigger 2 currently being executed.
0x2
TRIG_3
Command (sequence) associated with Trigger 3 currently being executed.
0x3
CMDACT
Command Active
24
3
read-only
NO_COMMAND_ACTIVE
No command is currently in progress.
0
COMMAND_1
Command 1 currently being executed.
0x1
COMMAND_2
Command 2 currently being executed.
0x2
COMMAND_x_3
Associated command number is currently being executed.
0x3
COMMAND_x_4
Associated command number is currently being executed.
0x4
COMMAND_x_5
Associated command number is currently being executed.
0x5
COMMAND_x_6
Associated command number is currently being executed.
0x6
COMMAND_x_7
Associated command number is currently being executed.
0x7
IE
Interrupt Enable Register
0x18
32
read-write
0
0xFFFFFFFF
FWMIE0
FIFO 0 Watermark Interrupt Enable
0
1
read-write
DISABLED
FIFO 0 watermark interrupts are not enabled.
0
ENABLED
FIFO 0 watermark interrupts are enabled.
0x1
FOFIE0
Result FIFO 0 Overflow Interrupt Enable
1
1
read-write
DISABLED
FIFO 0 overflow interrupts are not enabled.
0
ENABLED
FIFO 0 overflow interrupts are enabled.
0x1
TEXC_IE
Trigger Exception Interrupt Enable
8
1
read-write
DISABLED
Trigger exception interrupts are disabled.
0
ENABLED
Trigger exception interrupts are enabled.
0x1
TCOMP_IE
Trigger Completion Interrupt Enable
16
4
read-write
DISABLED
Trigger completion interrupts are disabled.
0
TRIGGER_0_COMPLETE_ENABLED
Trigger completion interrupts are enabled for trigger source 0 only.
0x1
TRIGGER_1_COMPLETE_ENABLED
Trigger completion interrupts are enabled for trigger source 1 only.
0x2
TRIGGER_x_COMPLETE_ENABLED_3
Associated trigger completion interrupts are enabled.
0x3
TRIGGER_x_COMPLETE_ENABLED_4
Associated trigger completion interrupts are enabled.
0x4
TRIGGER_x_COMPLETE_ENABLED_5
Associated trigger completion interrupts are enabled.
0x5
TRIGGER_x_COMPLETE_ENABLED_6
Associated trigger completion interrupts are enabled.
0x6
TRIGGER_x_COMPLETE_ENABLED_7
Associated trigger completion interrupts are enabled.
0x7
TRIGGER_x_COMPLETE_ENABLED_8
Associated trigger completion interrupts are enabled.
0x8
TRIGGER_x_COMPLETE_ENABLED_9
Associated trigger completion interrupts are enabled.
0x9
ALL_TRIGGER_COMPLETES_ENABLED
Trigger completion interrupts are enabled for every trigger source.
0xF
DE
DMA Enable Register
0x1C
32
read-write
0
0xFFFFFFFF
FWMDE0
FIFO 0 Watermark DMA Enable
0
1
read-write
DISABLED
DMA request disabled.
0
ENABLED
DMA request enabled.
0x1
CFG
Configuration Register
0x20
32
read-write
0x800000
0xFFFFFFFF
TPRICTRL
ADC Trigger Priority Control
0
2
read-write
ABORT_CURRENT_ON_PRIORITY
If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started.
0
FINISH_CURRENT_ON_PRIORITY
If a higher priority trigger is received during command processing, the current command is stopped after completing the current conversion. If averaging is enabled, the averaging loop will be completed. However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced.
0x1
FINISH_SEQUENCE_ON_PRIORITY
If a higher priority trigger is received during command processing, the current command will be completed (averaging, looping, compare) before servicing the higher priority trigger.
0x2
PWRSEL
Power Configuration Select
5
1
read-write
LOWEST
Low power
0
HIGHEST
High power
0x1
REFSEL
Voltage Reference Selection
6
2
read-write
OPTION_1
(Default) Option 1 setting.
0
OPTION_2
Option 2 setting.
0x1
OPTION_3
Option 3 setting.
0x2
TRES
Trigger Resume Enable
8
1
read-write
DISABLED
Trigger sequences interrupted by a high priority trigger exception are not automatically resumed or restarted.
0
ENABLED
Trigger sequences interrupted by a high priority trigger exception are automatically resumed or restarted.
0x1
TCMDRES
Trigger Command Resume
9
1
read-write
DISABLED
Trigger sequences interrupted by a high priority trigger exception is automatically restarted.
0
ENABLED
Trigger sequences interrupted by a high priority trigger exception is resumed from the command executing before the exception.
0x1
HPT_EXDI
High Priority Trigger Exception Disable
10
1
read-write
ENABLED
High priority trigger exceptions are enabled.
0
DISABLED
High priority trigger exceptions are disabled.
0x1
PUDLY
Power Up Delay
16
8
read-write
PWREN
ADC Analog Pre-Enable
28
1
read-write
NOT_PRE_ENABLED
ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays.
0
PRE_ENABLED
ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). Note that a single power up delay (CFG[PUDLY]) is executed immediately once PWREN is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. After this initial delay expires the analog remains pre-enabled and no additional delays are executed.
0x1
PAUSE
Pause Register
0x24
32
read-write
0
0xFFFFFFFF
PAUSEDLY
Pause Delay
0
9
read-write
PAUSEEN
PAUSE Option Enable
31
1
read-write
DISABLED
Pause operation disabled
0
ENABLED
Pause operation enabled
0x1
SWTRIG
Software Trigger Register
0x34
32
read-write
0
0xFFFFFFFF
SWT0
Software Trigger 0 Event
0
1
read-write
NO_TRIGGER
No trigger 0 event generated.
0
INITIATE_TRIGGER_0
Trigger 0 event generated.
0x1
SWT1
Software Trigger 1 Event
1
1
read-write
NO_TRIGGER
No trigger 1 event generated.
0
INITIATE_TRIGGER_1
Trigger 1 event generated.
0x1
SWT2
Software Trigger 2 Event
2
1
read-write
NO_TRIGGER
No trigger 2 event generated.
0
INITIATE_TRIGGER_2
Trigger 2 event generated.
0x1
SWT3
Software Trigger 3 Event
3
1
read-write
NO_TRIGGER
No trigger 3 event generated.
0
INITIATE_TRIGGER_3
Trigger 3 event generated.
0x1
TSTAT
Trigger Status Register
0x38
32
read-write
0
0xFFFFFFFF
oneToClear
TEXC_NUM
Trigger Exception Number
0
4
read-write
oneToClear
NO_EXCEPTIONS
No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1.
0
BIT0_MEANS_TRIGGER_0_INTERRUPTED
Trigger 0 has been interrupted by a high priority exception.
0x1
BIT1_MEANS_TRIGGER_1_INTERRUPTED
Trigger 1 has been interrupted by a high priority exception.
0x2
SET_BITS_INDICATE_TRIGGER_x_INTERRUPTED_3
Associated trigger sequence has interrupted by a high priority exception.
0x3
SET_BITS_INDICATE_TRIGGER_x_INTERRUPTED_4
Associated trigger sequence has interrupted by a high priority exception.
0x4
SET_BITS_INDICATE_TRIGGER_x_INTERRUPTED_5
Associated trigger sequence has interrupted by a high priority exception.
0x5
SET_BITS_INDICATE_TRIGGER_x_INTERRUPTED_6
Associated trigger sequence has interrupted by a high priority exception.
0x6
SET_BITS_INDICATE_TRIGGER_x_INTERRUPTED_7
Associated trigger sequence has interrupted by a high priority exception.
0x7
SET_BITS_INDICATE_TRIGGER_x_INTERRUPTED_8
Associated trigger sequence has interrupted by a high priority exception.
0x8
SET_BITS_INDICATE_TRIGGER_x_INTERRUPTED_9
Associated trigger sequence has interrupted by a high priority exception.
0x9
ALL_BITS_SET_INDICATE_ALL_TRIGGERS_INTERRUPTED
Every trigger sequence has been interrupted by a high priority exception.
0xF
TCOMP_FLAG
Trigger Completion Flag
16
4
read-write
oneToClear
NO_TRIGGER
No triggers have been completed. Trigger completion interrupts are disabled.
0
BIT0_MEANS_TRIGGER_0_COMPLETED
Trigger 0 has been completed and trigger 0 has enabled completion interrupts.
0x1
BIT1_MEANS_TRIGGER_1_COMPLETED
Trigger 1 has been completed and trigger 1 has enabled completion interrupts.
0x2
SET_BITS_INDICATE_TRIGGER_x_COMPLETED_3
Associated trigger sequence has completed and has enabled completion interrupts.
0x3
SET_BITS_INDICATE_TRIGGER_x_COMPLETED_4
Associated trigger sequence has completed and has enabled completion interrupts.
0x4
SET_BITS_INDICATE_TRIGGER_x_COMPLETED_5
Associated trigger sequence has completed and has enabled completion interrupts.
0x5
SET_BITS_INDICATE_TRIGGER_x_COMPLETED_6
Associated trigger sequence has completed and has enabled completion interrupts.
0x6
SET_BITS_INDICATE_TRIGGER_x_COMPLETED_7
Associated trigger sequence has completed and has enabled completion interrupts.
0x7
SET_BITS_INDICATE_TRIGGER_x_COMPLETED_8
Associated trigger sequence has completed and has enabled completion interrupts.
0x8
SET_BITS_INDICATE_TRIGGER_x_COMPLETED_9
Associated trigger sequence has completed and has enabled completion interrupts.
0x9
ALL_BITS_SET_INDICATE_ALL_TRIGGERS_COMPLETED
Every trigger sequence has been completed and every trigger has enabled completion interrupts.
0xF
OFSTRIM
Offset Trim Register
0x40
32
read-write
0
0xFFFFFFFF
OFSTRIM
Trim for Offset
0
10
read-write
HSTRIM
High Speed Trim Register
0x48
32
read-write
0
0xFFFFFFFF
HSTRIM
Trim for High Speed Conversions
0
5
read-write
4
0x4
TCTRL[%s]
Trigger Control Register
0xA0
32
read-write
0
0xFFFFFFFF
HTEN
Trigger Enable
0
1
read-write
DISABLED
Hardware trigger source disabled
0
ENABLED
Hardware trigger source enabled
0x1
TPRI
Trigger Priority Setting
8
2
read-write
HIGHEST_PRIORITY
Set to highest priority, Level 1
0
CORRESPONDING_LOWER_PRIORITY_1
Set to corresponding priority level
0x1
CORRESPONDING_LOWER_PRIORITY_2
Set to corresponding priority level
0x2
LOWEST_PRIORITY
Set to lowest priority, Level 4
0x3
RSYNC
Trigger Resync
15
1
read-write
TDLY
Trigger Delay Select
16
4
read-write
TSYNC
Trigger Synchronous Select
23
1
read-write
TCMD
Trigger Command Select
24
3
read-write
NOT_VALID
Not a valid selection from the command buffer. Trigger event is ignored.
0
EXECUTE_CMD1
CMD1 is executed
0x1
EXECUTE_CORRESPONDING_CMD_2
Corresponding CMD is executed
0x2
EXECUTE_CORRESPONDING_CMD_3
Corresponding CMD is executed
0x3
EXECUTE_CORRESPONDING_CMD_4
Corresponding CMD is executed
0x4
EXECUTE_CORRESPONDING_CMD_5
Corresponding CMD is executed
0x5
EXECUTE_CORRESPONDING_CMD_6
Corresponding CMD is executed
0x6
EXECUTE_CMD7
CMD7 is executed
0x7
FCTRL0
FIFO Control Register
0xE0
32
read-write
0
0xFFFFFFFF
FCOUNT
Result FIFO Counter
0
4
read-only
FWMARK
Watermark Level Selection
16
3
read-write
GCC0
Gain Calibration Control
0xF0
32
read-only
0
0xFFFFFFFF
GAIN_CAL
Gain Calibration Value
0
16
read-only
RDY
Gain Calibration Value Valid
24
1
read-only
GAIN_CAL_NOT_VALID
The GAIN_CAL value is invalid. Run the hardware calibration routine for this value to be set.
0
HARDWARE_CAL_ROUTINE_COMPLETED
The GAIN_CAL value is valid. GAIN_CAL should be used by software to derive GCRa[GCALR].
0x1
GCR0
Gain Calculation Result
0xF8
32
read-write
0x10000
0xFFFFFFFF
GCALR
Gain Calculation Result
0
17
read-write
RDY
Gain Calculation Ready
24
1
read-write
NOT_VALID
The GCALR value is invalid.
0
VALID
The GCALR value is valid.
0x1
CMDL1
Command Low Buffer Register
0x100
32
read-write
0
0xFFFFFFFF
ADCH
Input Channel Select
0
5
read-write
SELECT_CH0
Select CH0A.
0
SELECT_CH1
Select CH1A.
0x1
SELECT_CH2
Select CH2A.
0x2
SELECT_CH3
Select CH3A.
0x3
SELECT_CORRESPONDING_CHANNEL_4
Select corresponding channel CHnA.
0x4
SELECT_CORRESPONDING_CHANNEL_5
Select corresponding channel CHnA.
0x5
SELECT_CORRESPONDING_CHANNEL_6
Select corresponding channel CHnA.
0x6
SELECT_CORRESPONDING_CHANNEL_7
Select corresponding channel CHnA.
0x7
SELECT_CORRESPONDING_CHANNEL_8
Select corresponding channel CHnA.
0x8
SELECT_CORRESPONDING_CHANNEL_9
Select corresponding channel CHnA.
0x9
SELECT_CH30
Select CH30A.
0x1E
SELECT_CH31
Select CH31A.
0x1F
CTYPE
Conversion Type
5
2
read-only
SINGLE_ENDED_A_SIDE_CHANNEL
Single-Ended Mode. Only A side channel is converted.
0
MODE
Select Resolution of Conversions
7
1
read-write
DATA_12_BITS
Standard resolution. Single-ended 12-bit conversion.
0
DATA_16_BITS
High resolution. Single-ended 16-bit conversion.
0x1
CMDH1
Command High Buffer Register
0x104
32
read-write
0
0xFFFFFFFF
CMPEN
Compare Function Enable
0
2
read-write
DISABLED_ALWAYS_STORE_RESULT
Compare disabled.
0
COMPARE_RESULT_STORE_IF_TRUE
Compare enabled. Store on true.
0x2
COMPARE_RESULT_KEEP_CONVERTING_UNTIL_TRUE_STORE_IF_TRUE
Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
0x3
WAIT_TRIG
Wait for Trigger Assertion before Execution.
2
1
read-write
DISABLED
This command will be automatically executed.
0
ENABLED
The active trigger must be asserted again before executing this command.
0x1
LWI
Loop with Increment
7
1
read-write
DISABLED
Auto channel increment disabled
0
ENABLED
Auto channel increment enabled
0x1
STS
Sample Time Select
8
3
read-write
SAMPLE_3p5
Minimum sample time of 3.5 ADCK cycles.
0
SAMPLE_5p5
3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time.
0x1
SAMPLE_7p5
3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time.
0x2
SAMPLE_11p5
3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time.
0x3
SAMPLE_19p5
3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time.
0x4
SAMPLE_35p5
3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time.
0x5
SAMPLE_67p5
3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time.
0x6
SAMPLE_131p5
3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time.
0x7
AVGS
Hardware Average Select
12
4
read-write
NO_AVERAGE
Single conversion.
0
AVERAGE_2
2 conversions averaged.
0x1
AVERAGE_4
4 conversions averaged.
0x2
AVERAGE_8
8 conversions averaged.
0x3
AVERAGE_16
16 conversions averaged.
0x4
AVERAGE_32
32 conversions averaged.
0x5
AVERAGE_64
64 conversions averaged.
0x6
AVERAGE_128
128 conversions averaged.
0x7
AVERAGE_256
256 conversions averaged.
0x8
AVERAGE_512
512 conversions averaged.
0x9
AVERAGE_1024
1024 conversions averaged.
0xA
LOOP
Loop Count Select
16
4
read-write
CMD_EXEC_1x
Looping not enabled. Command executes 1 time.
0
CMD_EXEC_2x
Loop 1 time. Command executes 2 times.
0x1
CMD_EXEC_3x
Loop 2 times. Command executes 3 times.
0x2
CMD_EXECUTES_CORRESPONDING_TIMES_3
Loop corresponding number of times. Command executes LOOP+1 times.
0x3
CMD_EXECUTES_CORRESPONDING_TIMES_4
Loop corresponding number of times. Command executes LOOP+1 times.
0x4
CMD_EXECUTES_CORRESPONDING_TIMES_5
Loop corresponding number of times. Command executes LOOP+1 times.
0x5
CMD_EXECUTES_CORRESPONDING_TIMES_6
Loop corresponding number of times. Command executes LOOP+1 times.
0x6
CMD_EXECUTES_CORRESPONDING_TIMES_7
Loop corresponding number of times. Command executes LOOP+1 times.
0x7
CMD_EXECUTES_CORRESPONDING_TIMES_8
Loop corresponding number of times. Command executes LOOP+1 times.
0x8
CMD_EXECUTES_CORRESPONDING_TIMES_9
Loop corresponding number of times. Command executes LOOP+1 times.
0x9
CMD_EXEC_15x
Loop 15 times. Command executes 16 times.
0xF
NEXT
Next Command Select
24
3
read-write
NO_NEXT_CMD_TERMINATE_ON_FINISH
No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger.
0
DO_CMD1_NEXT
Select CMD1 command buffer register as next command.
0x1
DO_CORRESPONDING_CMD_NEXT_2
Select corresponding CMD command buffer register as next command
0x2
DO_CORRESPONDING_CMD_NEXT_3
Select corresponding CMD command buffer register as next command
0x3
DO_CORRESPONDING_CMD_NEXT_4
Select corresponding CMD command buffer register as next command
0x4
DO_CORRESPONDING_CMD_NEXT_5
Select corresponding CMD command buffer register as next command
0x5
DO_CORRESPONDING_CMD_NEXT_6
Select corresponding CMD command buffer register as next command
0x6
DO_CMD7_NEXT
Select CMD7 command buffer register as next command.
0x7
CMDL2
Command Low Buffer Register
0x108
32
read-write
0
0xFFFFFFFF
ADCH
Input Channel Select
0
5
read-write
SELECT_CH0
Select CH0A.
0
SELECT_CH1
Select CH1A.
0x1
SELECT_CH2
Select CH2A.
0x2
SELECT_CH3
Select CH3A.
0x3
SELECT_CORRESPONDING_CHANNEL_4
Select corresponding channel CHnA.
0x4
SELECT_CORRESPONDING_CHANNEL_5
Select corresponding channel CHnA.
0x5
SELECT_CORRESPONDING_CHANNEL_6
Select corresponding channel CHnA.
0x6
SELECT_CORRESPONDING_CHANNEL_7
Select corresponding channel CHnA.
0x7
SELECT_CORRESPONDING_CHANNEL_8
Select corresponding channel CHnA.
0x8
SELECT_CORRESPONDING_CHANNEL_9
Select corresponding channel CHnA.
0x9
SELECT_CH30
Select CH30A.
0x1E
SELECT_CH31
Select CH31A.
0x1F
CTYPE
Conversion Type
5
2
read-only
SINGLE_ENDED_A_SIDE_CHANNEL
Single-Ended Mode. Only A side channel is converted.
0
MODE
Select Resolution of Conversions
7
1
read-write
DATA_12_BITS
Standard resolution. Single-ended 12-bit conversion.
0
DATA_16_BITS
High resolution. Single-ended 16-bit conversion.
0x1
CMDH2
Command High Buffer Register
0x10C
32
read-write
0
0xFFFFFFFF
CMPEN
Compare Function Enable
0
2
read-write
DISABLED_ALWAYS_STORE_RESULT
Compare disabled.
0
COMPARE_RESULT_STORE_IF_TRUE
Compare enabled. Store on true.
0x2
COMPARE_RESULT_KEEP_CONVERTING_UNTIL_TRUE_STORE_IF_TRUE
Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
0x3
WAIT_TRIG
Wait for Trigger Assertion before Execution.
2
1
read-write
DISABLED
This command will be automatically executed.
0
ENABLED
The active trigger must be asserted again before executing this command.
0x1
LWI
Loop with Increment
7
1
read-write
DISABLED
Auto channel increment disabled
0
ENABLED
Auto channel increment enabled
0x1
STS
Sample Time Select
8
3
read-write
SAMPLE_3p5
Minimum sample time of 3.5 ADCK cycles.
0
SAMPLE_5p5
3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time.
0x1
SAMPLE_7p5
3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time.
0x2
SAMPLE_11p5
3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time.
0x3
SAMPLE_19p5
3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time.
0x4
SAMPLE_35p5
3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time.
0x5
SAMPLE_67p5
3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time.
0x6
SAMPLE_131p5
3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time.
0x7
AVGS
Hardware Average Select
12
4
read-write
NO_AVERAGE
Single conversion.
0
AVERAGE_2
2 conversions averaged.
0x1
AVERAGE_4
4 conversions averaged.
0x2
AVERAGE_8
8 conversions averaged.
0x3
AVERAGE_16
16 conversions averaged.
0x4
AVERAGE_32
32 conversions averaged.
0x5
AVERAGE_64
64 conversions averaged.
0x6
AVERAGE_128
128 conversions averaged.
0x7
AVERAGE_256
256 conversions averaged.
0x8
AVERAGE_512
512 conversions averaged.
0x9
AVERAGE_1024
1024 conversions averaged.
0xA
LOOP
Loop Count Select
16
4
read-write
CMD_EXEC_1x
Looping not enabled. Command executes 1 time.
0
CMD_EXEC_2x
Loop 1 time. Command executes 2 times.
0x1
CMD_EXEC_3x
Loop 2 times. Command executes 3 times.
0x2
CMD_EXECUTES_CORRESPONDING_TIMES_3
Loop corresponding number of times. Command executes LOOP+1 times.
0x3
CMD_EXECUTES_CORRESPONDING_TIMES_4
Loop corresponding number of times. Command executes LOOP+1 times.
0x4
CMD_EXECUTES_CORRESPONDING_TIMES_5
Loop corresponding number of times. Command executes LOOP+1 times.
0x5
CMD_EXECUTES_CORRESPONDING_TIMES_6
Loop corresponding number of times. Command executes LOOP+1 times.
0x6
CMD_EXECUTES_CORRESPONDING_TIMES_7
Loop corresponding number of times. Command executes LOOP+1 times.
0x7
CMD_EXECUTES_CORRESPONDING_TIMES_8
Loop corresponding number of times. Command executes LOOP+1 times.
0x8
CMD_EXECUTES_CORRESPONDING_TIMES_9
Loop corresponding number of times. Command executes LOOP+1 times.
0x9
CMD_EXEC_15x
Loop 15 times. Command executes 16 times.
0xF
NEXT
Next Command Select
24
3
read-write
NO_NEXT_CMD_TERMINATE_ON_FINISH
No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger.
0
DO_CMD1_NEXT
Select CMD1 command buffer register as next command.
0x1
DO_CORRESPONDING_CMD_NEXT_2
Select corresponding CMD command buffer register as next command
0x2
DO_CORRESPONDING_CMD_NEXT_3
Select corresponding CMD command buffer register as next command
0x3
DO_CORRESPONDING_CMD_NEXT_4
Select corresponding CMD command buffer register as next command
0x4
DO_CORRESPONDING_CMD_NEXT_5
Select corresponding CMD command buffer register as next command
0x5
DO_CORRESPONDING_CMD_NEXT_6
Select corresponding CMD command buffer register as next command
0x6
DO_CMD7_NEXT
Select CMD7 command buffer register as next command.
0x7
CMDL3
Command Low Buffer Register
0x110
32
read-write
0
0xFFFFFFFF
ADCH
Input Channel Select
0
5
read-write
SELECT_CH0
Select CH0A.
0
SELECT_CH1
Select CH1A.
0x1
SELECT_CH2
Select CH2A.
0x2
SELECT_CH3
Select CH3A.
0x3
SELECT_CORRESPONDING_CHANNEL_4
Select corresponding channel CHnA.
0x4
SELECT_CORRESPONDING_CHANNEL_5
Select corresponding channel CHnA.
0x5
SELECT_CORRESPONDING_CHANNEL_6
Select corresponding channel CHnA.
0x6
SELECT_CORRESPONDING_CHANNEL_7
Select corresponding channel CHnA.
0x7
SELECT_CORRESPONDING_CHANNEL_8
Select corresponding channel CHnA.
0x8
SELECT_CORRESPONDING_CHANNEL_9
Select corresponding channel CHnA.
0x9
SELECT_CH30
Select CH30A.
0x1E
SELECT_CH31
Select CH31A.
0x1F
CTYPE
Conversion Type
5
2
read-only
SINGLE_ENDED_A_SIDE_CHANNEL
Single-Ended Mode. Only A side channel is converted.
0
MODE
Select Resolution of Conversions
7
1
read-write
DATA_12_BITS
Standard resolution. Single-ended 12-bit conversion.
0
DATA_16_BITS
High resolution. Single-ended 16-bit conversion.
0x1
CMDH3
Command High Buffer Register
0x114
32
read-write
0
0xFFFFFFFF
CMPEN
Compare Function Enable
0
2
read-write
DISABLED_ALWAYS_STORE_RESULT
Compare disabled.
0
COMPARE_RESULT_STORE_IF_TRUE
Compare enabled. Store on true.
0x2
COMPARE_RESULT_KEEP_CONVERTING_UNTIL_TRUE_STORE_IF_TRUE
Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
0x3
WAIT_TRIG
Wait for Trigger Assertion before Execution.
2
1
read-write
DISABLED
This command will be automatically executed.
0
ENABLED
The active trigger must be asserted again before executing this command.
0x1
LWI
Loop with Increment
7
1
read-write
DISABLED
Auto channel increment disabled
0
ENABLED
Auto channel increment enabled
0x1
STS
Sample Time Select
8
3
read-write
SAMPLE_3p5
Minimum sample time of 3.5 ADCK cycles.
0
SAMPLE_5p5
3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time.
0x1
SAMPLE_7p5
3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time.
0x2
SAMPLE_11p5
3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time.
0x3
SAMPLE_19p5
3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time.
0x4
SAMPLE_35p5
3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time.
0x5
SAMPLE_67p5
3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time.
0x6
SAMPLE_131p5
3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time.
0x7
AVGS
Hardware Average Select
12
4
read-write
NO_AVERAGE
Single conversion.
0
AVERAGE_2
2 conversions averaged.
0x1
AVERAGE_4
4 conversions averaged.
0x2
AVERAGE_8
8 conversions averaged.
0x3
AVERAGE_16
16 conversions averaged.
0x4
AVERAGE_32
32 conversions averaged.
0x5
AVERAGE_64
64 conversions averaged.
0x6
AVERAGE_128
128 conversions averaged.
0x7
AVERAGE_256
256 conversions averaged.
0x8
AVERAGE_512
512 conversions averaged.
0x9
AVERAGE_1024
1024 conversions averaged.
0xA
LOOP
Loop Count Select
16
4
read-write
CMD_EXEC_1x
Looping not enabled. Command executes 1 time.
0
CMD_EXEC_2x
Loop 1 time. Command executes 2 times.
0x1
CMD_EXEC_3x
Loop 2 times. Command executes 3 times.
0x2
CMD_EXECUTES_CORRESPONDING_TIMES_3
Loop corresponding number of times. Command executes LOOP+1 times.
0x3
CMD_EXECUTES_CORRESPONDING_TIMES_4
Loop corresponding number of times. Command executes LOOP+1 times.
0x4
CMD_EXECUTES_CORRESPONDING_TIMES_5
Loop corresponding number of times. Command executes LOOP+1 times.
0x5
CMD_EXECUTES_CORRESPONDING_TIMES_6
Loop corresponding number of times. Command executes LOOP+1 times.
0x6
CMD_EXECUTES_CORRESPONDING_TIMES_7
Loop corresponding number of times. Command executes LOOP+1 times.
0x7
CMD_EXECUTES_CORRESPONDING_TIMES_8
Loop corresponding number of times. Command executes LOOP+1 times.
0x8
CMD_EXECUTES_CORRESPONDING_TIMES_9
Loop corresponding number of times. Command executes LOOP+1 times.
0x9
CMD_EXEC_15x
Loop 15 times. Command executes 16 times.
0xF
NEXT
Next Command Select
24
3
read-write
NO_NEXT_CMD_TERMINATE_ON_FINISH
No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger.
0
DO_CMD1_NEXT
Select CMD1 command buffer register as next command.
0x1
DO_CORRESPONDING_CMD_NEXT_2
Select corresponding CMD command buffer register as next command
0x2
DO_CORRESPONDING_CMD_NEXT_3
Select corresponding CMD command buffer register as next command
0x3
DO_CORRESPONDING_CMD_NEXT_4
Select corresponding CMD command buffer register as next command
0x4
DO_CORRESPONDING_CMD_NEXT_5
Select corresponding CMD command buffer register as next command
0x5
DO_CORRESPONDING_CMD_NEXT_6
Select corresponding CMD command buffer register as next command
0x6
DO_CMD7_NEXT
Select CMD7 command buffer register as next command.
0x7
CMDL4
Command Low Buffer Register
0x118
32
read-write
0
0xFFFFFFFF
ADCH
Input Channel Select
0
5
read-write
SELECT_CH0
Select CH0A.
0
SELECT_CH1
Select CH1A.
0x1
SELECT_CH2
Select CH2A.
0x2
SELECT_CH3
Select CH3A.
0x3
SELECT_CORRESPONDING_CHANNEL_4
Select corresponding channel CHnA.
0x4
SELECT_CORRESPONDING_CHANNEL_5
Select corresponding channel CHnA.
0x5
SELECT_CORRESPONDING_CHANNEL_6
Select corresponding channel CHnA.
0x6
SELECT_CORRESPONDING_CHANNEL_7
Select corresponding channel CHnA.
0x7
SELECT_CORRESPONDING_CHANNEL_8
Select corresponding channel CHnA.
0x8
SELECT_CORRESPONDING_CHANNEL_9
Select corresponding channel CHnA.
0x9
SELECT_CH30
Select CH30A.
0x1E
SELECT_CH31
Select CH31A.
0x1F
CTYPE
Conversion Type
5
2
read-only
SINGLE_ENDED_A_SIDE_CHANNEL
Single-Ended Mode. Only A side channel is converted.
0
MODE
Select Resolution of Conversions
7
1
read-write
DATA_12_BITS
Standard resolution. Single-ended 12-bit conversion.
0
DATA_16_BITS
High resolution. Single-ended 16-bit conversion.
0x1
CMDH4
Command High Buffer Register
0x11C
32
read-write
0
0xFFFFFFFF
CMPEN
Compare Function Enable
0
2
read-write
DISABLED_ALWAYS_STORE_RESULT
Compare disabled.
0
COMPARE_RESULT_STORE_IF_TRUE
Compare enabled. Store on true.
0x2
COMPARE_RESULT_KEEP_CONVERTING_UNTIL_TRUE_STORE_IF_TRUE
Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
0x3
WAIT_TRIG
Wait for Trigger Assertion before Execution.
2
1
read-write
DISABLED
This command will be automatically executed.
0
ENABLED
The active trigger must be asserted again before executing this command.
0x1
LWI
Loop with Increment
7
1
read-write
DISABLED
Auto channel increment disabled
0
ENABLED
Auto channel increment enabled
0x1
STS
Sample Time Select
8
3
read-write
SAMPLE_3p5
Minimum sample time of 3.5 ADCK cycles.
0
SAMPLE_5p5
3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time.
0x1
SAMPLE_7p5
3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time.
0x2
SAMPLE_11p5
3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time.
0x3
SAMPLE_19p5
3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time.
0x4
SAMPLE_35p5
3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time.
0x5
SAMPLE_67p5
3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time.
0x6
SAMPLE_131p5
3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time.
0x7
AVGS
Hardware Average Select
12
4
read-write
NO_AVERAGE
Single conversion.
0
AVERAGE_2
2 conversions averaged.
0x1
AVERAGE_4
4 conversions averaged.
0x2
AVERAGE_8
8 conversions averaged.
0x3
AVERAGE_16
16 conversions averaged.
0x4
AVERAGE_32
32 conversions averaged.
0x5
AVERAGE_64
64 conversions averaged.
0x6
AVERAGE_128
128 conversions averaged.
0x7
AVERAGE_256
256 conversions averaged.
0x8
AVERAGE_512
512 conversions averaged.
0x9
AVERAGE_1024
1024 conversions averaged.
0xA
LOOP
Loop Count Select
16
4
read-write
CMD_EXEC_1x
Looping not enabled. Command executes 1 time.
0
CMD_EXEC_2x
Loop 1 time. Command executes 2 times.
0x1
CMD_EXEC_3x
Loop 2 times. Command executes 3 times.
0x2
CMD_EXECUTES_CORRESPONDING_TIMES_3
Loop corresponding number of times. Command executes LOOP+1 times.
0x3
CMD_EXECUTES_CORRESPONDING_TIMES_4
Loop corresponding number of times. Command executes LOOP+1 times.
0x4
CMD_EXECUTES_CORRESPONDING_TIMES_5
Loop corresponding number of times. Command executes LOOP+1 times.
0x5
CMD_EXECUTES_CORRESPONDING_TIMES_6
Loop corresponding number of times. Command executes LOOP+1 times.
0x6
CMD_EXECUTES_CORRESPONDING_TIMES_7
Loop corresponding number of times. Command executes LOOP+1 times.
0x7
CMD_EXECUTES_CORRESPONDING_TIMES_8
Loop corresponding number of times. Command executes LOOP+1 times.
0x8
CMD_EXECUTES_CORRESPONDING_TIMES_9
Loop corresponding number of times. Command executes LOOP+1 times.
0x9
CMD_EXEC_15x
Loop 15 times. Command executes 16 times.
0xF
NEXT
Next Command Select
24
3
read-write
NO_NEXT_CMD_TERMINATE_ON_FINISH
No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger.
0
DO_CMD1_NEXT
Select CMD1 command buffer register as next command.
0x1
DO_CORRESPONDING_CMD_NEXT_2
Select corresponding CMD command buffer register as next command
0x2
DO_CORRESPONDING_CMD_NEXT_3
Select corresponding CMD command buffer register as next command
0x3
DO_CORRESPONDING_CMD_NEXT_4
Select corresponding CMD command buffer register as next command
0x4
DO_CORRESPONDING_CMD_NEXT_5
Select corresponding CMD command buffer register as next command
0x5
DO_CORRESPONDING_CMD_NEXT_6
Select corresponding CMD command buffer register as next command
0x6
DO_CMD7_NEXT
Select CMD7 command buffer register as next command.
0x7
CMDL5
Command Low Buffer Register
0x120
32
read-write
0
0xFFFFFFFF
ADCH
Input Channel Select
0
5
read-write
SELECT_CH0
Select CH0A.
0
SELECT_CH1
Select CH1A.
0x1
SELECT_CH2
Select CH2A.
0x2
SELECT_CH3
Select CH3A.
0x3
SELECT_CORRESPONDING_CHANNEL_4
Select corresponding channel CHnA.
0x4
SELECT_CORRESPONDING_CHANNEL_5
Select corresponding channel CHnA.
0x5
SELECT_CORRESPONDING_CHANNEL_6
Select corresponding channel CHnA.
0x6
SELECT_CORRESPONDING_CHANNEL_7
Select corresponding channel CHnA.
0x7
SELECT_CORRESPONDING_CHANNEL_8
Select corresponding channel CHnA.
0x8
SELECT_CORRESPONDING_CHANNEL_9
Select corresponding channel CHnA.
0x9
SELECT_CH30
Select CH30A.
0x1E
SELECT_CH31
Select CH31A.
0x1F
CTYPE
Conversion Type
5
2
read-only
SINGLE_ENDED_A_SIDE_CHANNEL
Single-Ended Mode. Only A side channel is converted.
0
MODE
Select Resolution of Conversions
7
1
read-write
DATA_12_BITS
Standard resolution. Single-ended 12-bit conversion.
0
DATA_16_BITS
High resolution. Single-ended 16-bit conversion.
0x1
CMDH5
Command High Buffer Register
0x124
32
read-write
0
0xFFFFFFFF
CMPEN
Compare Function Enable
0
2
read-write
DISABLED_ALWAYS_STORE_RESULT
Compare disabled.
0
COMPARE_RESULT_STORE_IF_TRUE
Compare enabled. Store on true.
0x2
COMPARE_RESULT_KEEP_CONVERTING_UNTIL_TRUE_STORE_IF_TRUE
Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
0x3
WAIT_TRIG
Wait for Trigger Assertion before Execution.
2
1
read-write
DISABLED
This command will be automatically executed.
0
ENABLED
The active trigger must be asserted again before executing this command.
0x1
LWI
Loop with Increment
7
1
read-write
DISABLED
Auto channel increment disabled
0
ENABLED
Auto channel increment enabled
0x1
STS
Sample Time Select
8
3
read-write
SAMPLE_3p5
Minimum sample time of 3.5 ADCK cycles.
0
SAMPLE_5p5
3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time.
0x1
SAMPLE_7p5
3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time.
0x2
SAMPLE_11p5
3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time.
0x3
SAMPLE_19p5
3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time.
0x4
SAMPLE_35p5
3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time.
0x5
SAMPLE_67p5
3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time.
0x6
SAMPLE_131p5
3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time.
0x7
AVGS
Hardware Average Select
12
4
read-write
NO_AVERAGE
Single conversion.
0
AVERAGE_2
2 conversions averaged.
0x1
AVERAGE_4
4 conversions averaged.
0x2
AVERAGE_8
8 conversions averaged.
0x3
AVERAGE_16
16 conversions averaged.
0x4
AVERAGE_32
32 conversions averaged.
0x5
AVERAGE_64
64 conversions averaged.
0x6
AVERAGE_128
128 conversions averaged.
0x7
AVERAGE_256
256 conversions averaged.
0x8
AVERAGE_512
512 conversions averaged.
0x9
AVERAGE_1024
1024 conversions averaged.
0xA
LOOP
Loop Count Select
16
4
read-write
CMD_EXEC_1x
Looping not enabled. Command executes 1 time.
0
CMD_EXEC_2x
Loop 1 time. Command executes 2 times.
0x1
CMD_EXEC_3x
Loop 2 times. Command executes 3 times.
0x2
CMD_EXECUTES_CORRESPONDING_TIMES_3
Loop corresponding number of times. Command executes LOOP+1 times.
0x3
CMD_EXECUTES_CORRESPONDING_TIMES_4
Loop corresponding number of times. Command executes LOOP+1 times.
0x4
CMD_EXECUTES_CORRESPONDING_TIMES_5
Loop corresponding number of times. Command executes LOOP+1 times.
0x5
CMD_EXECUTES_CORRESPONDING_TIMES_6
Loop corresponding number of times. Command executes LOOP+1 times.
0x6
CMD_EXECUTES_CORRESPONDING_TIMES_7
Loop corresponding number of times. Command executes LOOP+1 times.
0x7
CMD_EXECUTES_CORRESPONDING_TIMES_8
Loop corresponding number of times. Command executes LOOP+1 times.
0x8
CMD_EXECUTES_CORRESPONDING_TIMES_9
Loop corresponding number of times. Command executes LOOP+1 times.
0x9
CMD_EXEC_15x
Loop 15 times. Command executes 16 times.
0xF
NEXT
Next Command Select
24
3
read-write
NO_NEXT_CMD_TERMINATE_ON_FINISH
No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger.
0
DO_CMD1_NEXT
Select CMD1 command buffer register as next command.
0x1
DO_CORRESPONDING_CMD_NEXT_2
Select corresponding CMD command buffer register as next command
0x2
DO_CORRESPONDING_CMD_NEXT_3
Select corresponding CMD command buffer register as next command
0x3
DO_CORRESPONDING_CMD_NEXT_4
Select corresponding CMD command buffer register as next command
0x4
DO_CORRESPONDING_CMD_NEXT_5
Select corresponding CMD command buffer register as next command
0x5
DO_CORRESPONDING_CMD_NEXT_6
Select corresponding CMD command buffer register as next command
0x6
DO_CMD7_NEXT
Select CMD7 command buffer register as next command.
0x7
CMDL6
Command Low Buffer Register
0x128
32
read-write
0
0xFFFFFFFF
ADCH
Input Channel Select
0
5
read-write
SELECT_CH0
Select CH0A.
0
SELECT_CH1
Select CH1A.
0x1
SELECT_CH2
Select CH2A.
0x2
SELECT_CH3
Select CH3A.
0x3
SELECT_CORRESPONDING_CHANNEL_4
Select corresponding channel CHnA.
0x4
SELECT_CORRESPONDING_CHANNEL_5
Select corresponding channel CHnA.
0x5
SELECT_CORRESPONDING_CHANNEL_6
Select corresponding channel CHnA.
0x6
SELECT_CORRESPONDING_CHANNEL_7
Select corresponding channel CHnA.
0x7
SELECT_CORRESPONDING_CHANNEL_8
Select corresponding channel CHnA.
0x8
SELECT_CORRESPONDING_CHANNEL_9
Select corresponding channel CHnA.
0x9
SELECT_CH30
Select CH30A.
0x1E
SELECT_CH31
Select CH31A.
0x1F
CTYPE
Conversion Type
5
2
read-only
SINGLE_ENDED_A_SIDE_CHANNEL
Single-Ended Mode. Only A side channel is converted.
0
MODE
Select Resolution of Conversions
7
1
read-write
DATA_12_BITS
Standard resolution. Single-ended 12-bit conversion.
0
DATA_16_BITS
High resolution. Single-ended 16-bit conversion.
0x1
CMDH6
Command High Buffer Register
0x12C
32
read-write
0
0xFFFFFFFF
CMPEN
Compare Function Enable
0
2
read-write
DISABLED_ALWAYS_STORE_RESULT
Compare disabled.
0
COMPARE_RESULT_STORE_IF_TRUE
Compare enabled. Store on true.
0x2
COMPARE_RESULT_KEEP_CONVERTING_UNTIL_TRUE_STORE_IF_TRUE
Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
0x3
WAIT_TRIG
Wait for Trigger Assertion before Execution.
2
1
read-write
DISABLED
This command will be automatically executed.
0
ENABLED
The active trigger must be asserted again before executing this command.
0x1
LWI
Loop with Increment
7
1
read-write
DISABLED
Auto channel increment disabled
0
ENABLED
Auto channel increment enabled
0x1
STS
Sample Time Select
8
3
read-write
SAMPLE_3p5
Minimum sample time of 3.5 ADCK cycles.
0
SAMPLE_5p5
3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time.
0x1
SAMPLE_7p5
3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time.
0x2
SAMPLE_11p5
3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time.
0x3
SAMPLE_19p5
3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time.
0x4
SAMPLE_35p5
3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time.
0x5
SAMPLE_67p5
3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time.
0x6
SAMPLE_131p5
3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time.
0x7
AVGS
Hardware Average Select
12
4
read-write
NO_AVERAGE
Single conversion.
0
AVERAGE_2
2 conversions averaged.
0x1
AVERAGE_4
4 conversions averaged.
0x2
AVERAGE_8
8 conversions averaged.
0x3
AVERAGE_16
16 conversions averaged.
0x4
AVERAGE_32
32 conversions averaged.
0x5
AVERAGE_64
64 conversions averaged.
0x6
AVERAGE_128
128 conversions averaged.
0x7
AVERAGE_256
256 conversions averaged.
0x8
AVERAGE_512
512 conversions averaged.
0x9
AVERAGE_1024
1024 conversions averaged.
0xA
LOOP
Loop Count Select
16
4
read-write
CMD_EXEC_1x
Looping not enabled. Command executes 1 time.
0
CMD_EXEC_2x
Loop 1 time. Command executes 2 times.
0x1
CMD_EXEC_3x
Loop 2 times. Command executes 3 times.
0x2
CMD_EXECUTES_CORRESPONDING_TIMES_3
Loop corresponding number of times. Command executes LOOP+1 times.
0x3
CMD_EXECUTES_CORRESPONDING_TIMES_4
Loop corresponding number of times. Command executes LOOP+1 times.
0x4
CMD_EXECUTES_CORRESPONDING_TIMES_5
Loop corresponding number of times. Command executes LOOP+1 times.
0x5
CMD_EXECUTES_CORRESPONDING_TIMES_6
Loop corresponding number of times. Command executes LOOP+1 times.
0x6
CMD_EXECUTES_CORRESPONDING_TIMES_7
Loop corresponding number of times. Command executes LOOP+1 times.
0x7
CMD_EXECUTES_CORRESPONDING_TIMES_8
Loop corresponding number of times. Command executes LOOP+1 times.
0x8
CMD_EXECUTES_CORRESPONDING_TIMES_9
Loop corresponding number of times. Command executes LOOP+1 times.
0x9
CMD_EXEC_15x
Loop 15 times. Command executes 16 times.
0xF
NEXT
Next Command Select
24
3
read-write
NO_NEXT_CMD_TERMINATE_ON_FINISH
No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger.
0
DO_CMD1_NEXT
Select CMD1 command buffer register as next command.
0x1
DO_CORRESPONDING_CMD_NEXT_2
Select corresponding CMD command buffer register as next command
0x2
DO_CORRESPONDING_CMD_NEXT_3
Select corresponding CMD command buffer register as next command
0x3
DO_CORRESPONDING_CMD_NEXT_4
Select corresponding CMD command buffer register as next command
0x4
DO_CORRESPONDING_CMD_NEXT_5
Select corresponding CMD command buffer register as next command
0x5
DO_CORRESPONDING_CMD_NEXT_6
Select corresponding CMD command buffer register as next command
0x6
DO_CMD7_NEXT
Select CMD7 command buffer register as next command.
0x7
CMDL7
Command Low Buffer Register
0x130
32
read-write
0
0xFFFFFFFF
ADCH
Input Channel Select
0
5
read-write
SELECT_CH0
Select CH0A.
0
SELECT_CH1
Select CH1A.
0x1
SELECT_CH2
Select CH2A.
0x2
SELECT_CH3
Select CH3A.
0x3
SELECT_CORRESPONDING_CHANNEL_4
Select corresponding channel CHnA.
0x4
SELECT_CORRESPONDING_CHANNEL_5
Select corresponding channel CHnA.
0x5
SELECT_CORRESPONDING_CHANNEL_6
Select corresponding channel CHnA.
0x6
SELECT_CORRESPONDING_CHANNEL_7
Select corresponding channel CHnA.
0x7
SELECT_CORRESPONDING_CHANNEL_8
Select corresponding channel CHnA.
0x8
SELECT_CORRESPONDING_CHANNEL_9
Select corresponding channel CHnA.
0x9
SELECT_CH30
Select CH30A.
0x1E
SELECT_CH31
Select CH31A.
0x1F
CTYPE
Conversion Type
5
2
read-only
SINGLE_ENDED_A_SIDE_CHANNEL
Single-Ended Mode. Only A side channel is converted.
0
MODE
Select Resolution of Conversions
7
1
read-write
DATA_12_BITS
Standard resolution. Single-ended 12-bit conversion.
0
DATA_16_BITS
High resolution. Single-ended 16-bit conversion.
0x1
CMDH7
Command High Buffer Register
0x134
32
read-write
0
0xFFFFFFFF
CMPEN
Compare Function Enable
0
2
read-write
DISABLED_ALWAYS_STORE_RESULT
Compare disabled.
0
COMPARE_RESULT_STORE_IF_TRUE
Compare enabled. Store on true.
0x2
COMPARE_RESULT_KEEP_CONVERTING_UNTIL_TRUE_STORE_IF_TRUE
Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
0x3
WAIT_TRIG
Wait for Trigger Assertion before Execution.
2
1
read-write
DISABLED
This command will be automatically executed.
0
ENABLED
The active trigger must be asserted again before executing this command.
0x1
LWI
Loop with Increment
7
1
read-write
DISABLED
Auto channel increment disabled
0
ENABLED
Auto channel increment enabled
0x1
STS
Sample Time Select
8
3
read-write
SAMPLE_3p5
Minimum sample time of 3.5 ADCK cycles.
0
SAMPLE_5p5
3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time.
0x1
SAMPLE_7p5
3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time.
0x2
SAMPLE_11p5
3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time.
0x3
SAMPLE_19p5
3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time.
0x4
SAMPLE_35p5
3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time.
0x5
SAMPLE_67p5
3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time.
0x6
SAMPLE_131p5
3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time.
0x7
AVGS
Hardware Average Select
12
4
read-write
NO_AVERAGE
Single conversion.
0
AVERAGE_2
2 conversions averaged.
0x1
AVERAGE_4
4 conversions averaged.
0x2
AVERAGE_8
8 conversions averaged.
0x3
AVERAGE_16
16 conversions averaged.
0x4
AVERAGE_32
32 conversions averaged.
0x5
AVERAGE_64
64 conversions averaged.
0x6
AVERAGE_128
128 conversions averaged.
0x7
AVERAGE_256
256 conversions averaged.
0x8
AVERAGE_512
512 conversions averaged.
0x9
AVERAGE_1024
1024 conversions averaged.
0xA
LOOP
Loop Count Select
16
4
read-write
CMD_EXEC_1x
Looping not enabled. Command executes 1 time.
0
CMD_EXEC_2x
Loop 1 time. Command executes 2 times.
0x1
CMD_EXEC_3x
Loop 2 times. Command executes 3 times.
0x2
CMD_EXECUTES_CORRESPONDING_TIMES_3
Loop corresponding number of times. Command executes LOOP+1 times.
0x3
CMD_EXECUTES_CORRESPONDING_TIMES_4
Loop corresponding number of times. Command executes LOOP+1 times.
0x4
CMD_EXECUTES_CORRESPONDING_TIMES_5
Loop corresponding number of times. Command executes LOOP+1 times.
0x5
CMD_EXECUTES_CORRESPONDING_TIMES_6
Loop corresponding number of times. Command executes LOOP+1 times.
0x6
CMD_EXECUTES_CORRESPONDING_TIMES_7
Loop corresponding number of times. Command executes LOOP+1 times.
0x7
CMD_EXECUTES_CORRESPONDING_TIMES_8
Loop corresponding number of times. Command executes LOOP+1 times.
0x8
CMD_EXECUTES_CORRESPONDING_TIMES_9
Loop corresponding number of times. Command executes LOOP+1 times.
0x9
CMD_EXEC_15x
Loop 15 times. Command executes 16 times.
0xF
NEXT
Next Command Select
24
3
read-write
NO_NEXT_CMD_TERMINATE_ON_FINISH
No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger.
0
DO_CMD1_NEXT
Select CMD1 command buffer register as next command.
0x1
DO_CORRESPONDING_CMD_NEXT_2
Select corresponding CMD command buffer register as next command
0x2
DO_CORRESPONDING_CMD_NEXT_3
Select corresponding CMD command buffer register as next command
0x3
DO_CORRESPONDING_CMD_NEXT_4
Select corresponding CMD command buffer register as next command
0x4
DO_CORRESPONDING_CMD_NEXT_5
Select corresponding CMD command buffer register as next command
0x5
DO_CORRESPONDING_CMD_NEXT_6
Select corresponding CMD command buffer register as next command
0x6
DO_CMD7_NEXT
Select CMD7 command buffer register as next command.
0x7
15
0x4
1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
CV%s
Compare Value Register
0x200
32
read-write
0
0xFFFFFFFF
CVL
Compare Value Low
0
16
read-write
CVH
Compare Value High
16
16
read-write
RESFIFO0
Data Result FIFO Register
0x300
32
read-only
0
0xFFFFFFFF
D
Data Result
0
16
read-only
TSRC
Trigger Source
16
2
read-only
TRIGGER_0
Trigger source 0 initiated this conversion.
0
TRIGGER_1
Trigger source 1 initiated this conversion.
0x1
CORRESPONDING_TRIGGER_2
Corresponding trigger source initiated this conversion.
0x2
TRIGGER_3
Trigger source 3 initiated this conversion.
0x3
LOOPCNT
Loop Count Value
20
4
read-only
RESULT_1
Result is from initial conversion in command.
0
RESULT_2
Result is from second conversion in command.
0x1
CORRESPONDING_RESULT_2
Result is from LOOPCNT+1 conversion in command.
0x2
CORRESPONDING_RESULT_3
Result is from LOOPCNT+1 conversion in command.
0x3
CORRESPONDING_RESULT_4
Result is from LOOPCNT+1 conversion in command.
0x4
CORRESPONDING_RESULT_5
Result is from LOOPCNT+1 conversion in command.
0x5
CORRESPONDING_RESULT_6
Result is from LOOPCNT+1 conversion in command.
0x6
CORRESPONDING_RESULT_7
Result is from LOOPCNT+1 conversion in command.
0x7
CORRESPONDING_RESULT_8
Result is from LOOPCNT+1 conversion in command.
0x8
CORRESPONDING_RESULT_9
Result is from LOOPCNT+1 conversion in command.
0x9
RESULT_16
Result is from 16th conversion in command.
0xF
CMDSRC
Command Buffer Source
24
3
read-only
NOT_VALID
Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state prior to an ADC conversion result dataword being stored to a RESFIFO buffer.
0
CMD1
CMD1 buffer used as control settings for this conversion.
0x1
CORRESPONDING_CMD_2
Corresponding command buffer used as control settings for this conversion.
0x2
CORRESPONDING_CMD_3
Corresponding command buffer used as control settings for this conversion.
0x3
CORRESPONDING_CMD_4
Corresponding command buffer used as control settings for this conversion.
0x4
CORRESPONDING_CMD_5
Corresponding command buffer used as control settings for this conversion.
0x5
CORRESPONDING_CMD_6
Corresponding command buffer used as control settings for this conversion.
0x6
CMD7
CMD7 buffer used as control settings for this conversion.
0x7
VALID
FIFO Entry is Valid
31
1
read-only
NOT_VALID
FIFO is empty. Discard any read from RESFIFO.
0
VALID
FIFO record read from RESFIFO is valid.
0x1
33
0x4
CAL_GAR[%s]
Calibration General A-Side Registers
0x400
32
read-write
0
0xFFFFFFFF
CAL_GAR_VAL
Calibration General A Side Register Element
0
16
read-write
CFG2
Configuration 2 Register
0xFF8
32
read-write
0x1000
0xFFFFFFFF
JLEFT
Justified Left Enable register
8
1
read-write
HS
High Speed Enable register
9
1
read-write
DISABLED
High speed conversion mode disabled
0
ENABLED
High speed conversion mode enabled
0x1
HSEXTRA
High Speed Extra register
10
1
read-write
HSEXTRA_0
No extra cycle added
0
HSEXTRA_1
Extra cycle added
0x1
TUNE
Tune Mode register
12
2
read-write
CMP0
LPCMP
CMP
CMP
0x400B1000
0
0x3C
registers
CMP0
64
VERID
Version ID
0
32
read-only
0x1000001
0xFFFFFFFF
FEATURE
Feature Specification Number
0
16
read-only
ROUND_ROBIN
Round robin feature
0x1
MINOR
Minor Version Number
16
8
read-only
MAJOR
Major Version Number
24
8
read-only
PARAM
Parameter
0x4
32
read-only
0x2
0xFFFFFFFF
DAC_RES
DAC Resolution
0
4
read-only
RESO_4
4-bit DAC
0
RESO_6
6-bit DAC
0x1
RESO_8
8-bit DAC
0x2
RESO_10
10-bit DAC
0x3
RESO_12
12-bit DAC
0x4
RESO_14
14-bit DAC
0x5
RESO_16
16-bit DAC
0x6
CCR0
Comparator Control Register 0
0x8
32
read-write
0x2
0xFFFFFFFF
CMP_EN
Comparator Enable
0
1
read-write
DISABLE
Disables (The analog logic remains off and consumes no power.)
0
ENABLE
Enables
0x1
CMP_STOP_EN
Comparator Deep Sleep Mode Enable
1
1
read-write
DISABLE
Disable the analog comparator regardless of CMP_EN.
0
ENABLE
Allows CMP_EN to enable the analog comparator.
0x1
CCR1
Comparator Control Register 1
0xC
32
read-write
0
0xFFFFFFFF
WINDOW_EN
Windowing Enable
0
1
read-write
DISABLE
Disables
0
ENABLE
Enables
0x1
SAMPLE_EN
Sampling Enable
1
1
read-write
DISABLE
Disables
0
ENABLE
Enables
0x1
DMA_EN
DMA Enable
2
1
read-write
DISABLE
Disables
0
ENABLE
Enables
0x1
COUT_INV
Comparator Invert
3
1
read-write
NO_INVERT
Do not invert
0
INVERT
Invert
0x1
COUT_SEL
Comparator Output Select
4
1
read-write
COUT
Use COUT (filtered)
0
COUTA
Use COUTA (unfiltered)
0x1
COUT_PEN
Comparator Output Pin Enable
5
1
read-write
UNAVAILABLE
Not available
0
AVAILABLE
Available
0x1
COUTA_OWEN
COUTA_OW Enable
6
1
read-write
SAMPLED
COUTA holds the last sampled value.
0
COUTA_OW
Enables the COUTA signal value to be defined by COUTA_OW.
0x1
COUTA_OW
COUTA Output Level for Closed Window
7
1
read-write
COUTA_0
COUTA is 0
0
COUTA_1
COUTA is 1
0x1
WINDOW_INV
WINDOW/SAMPLE Signal Invert
8
1
read-write
NO_INVERT
Do not invert
0
INVERT
Invert
0x1
WINDOW_CLS
COUT Event Window Close
9
1
read-write
NO_CLOSE
COUT event cannot close the window
0
CLOSE
COUT event can close the window
0x1
EVT_SEL
COUT Event Select
10
2
read-write
RISING
Rising edge
0
FALLING
Falling edge
0x1
BOTH
Both edges
#1x
FUNC_CLK_SEL
Functional Clock Source Select
12
2
read-write
FUNC0
Select functional clock source 0
0
FUNC1
Select functional clock source 1
0x1
FUNC2
Select functional clock source 2
0x2
FUNC3
Select functional clock source 3
0x3
FILT_CNT
Filter Sample Count
16
3
read-write
BYPASSED
Filter is bypassed: COUT = COUTA
0
SAMPLE_1
1 consecutive sample (Comparator output is simply sampled.)
0x1
SAMPLE_2
2 consecutive samples
0x2
SAMPLE_3
3 consecutive samples
0x3
SAMPLE_4
4 consecutive samples
0x4
SAMPLE_5
5 consecutive samples
0x5
SAMPLE_6
6 consecutive samples
0x6
SAMPLE_7
7 consecutive samples
0x7
FILT_PER
Filter Sample Period
24
8
read-write
CCR2
Comparator Control Register 2
0x10
32
read-write
0
0xFFFFFFFF
CMP_HPMD
CMP High Power Mode Select
0
1
read-write
LOW
Low power (speed) comparison mode
0
HIGH
High power (speed) comparison mode
0x1
CMP_NPMD
CMP Nano Power Mode Select
1
1
read-write
NO_NANO
Disables CMP Nano power mode. CCR2[CMP_HPMD] determines the mode for the comparator.
0
NANO
Enables CMP Nano power mode.
0x1
HYSTCTR
Comparator Hysteresis Control
4
2
read-write
LEVEL_0
Level 0
0
LEVEL_1
Level 1
0x1
LEVEL_2
Level 2
0x2
LEVEL_3
Level 3
0x3
PSEL
Plus Input MUX Select
16
3
read-write
INPUT_0
Input 0p
0
INPUT_1
Input 1p
0x1
INPUT_2
Input 2p
0x2
INPUT_3
Input 3p
0x3
INPUT_4
Input 4p
0x4
INPUT_5
Input 5p
0x5
INPUT_7
Internal DAC output
0x7
MSEL
Minus Input MUX Select
20
3
read-write
INPUT_0
Input 0m
0
INPUT_1
Input 1m
0x1
INPUT_2
Input 2m
0x2
INPUT_3
Input 3m
0x3
INPUT_4
Input 4m
0x4
INPUT_5
Input 5m
0x5
INPUT_7
Internal DAC output
0x7
DCR
DAC Control
0x18
32
read-write
0
0xFFFFFFFF
DAC_EN
DAC Enable
0
1
read-write
DISABLE
Disables
0
ENABLE
Enables
0x1
DAC_HPMD
DAC High Power Mode Select
1
1
read-write
DISABLE
Disables
0
ENABLE
Enables
0x1
VRSEL
DAC Reference High Voltage Source Select
8
1
read-write
VREF0
vrefh0
0
VREF1
vrefh1
0x1
DAC_DATA
DAC Output Voltage Select
16
8
read-write
IER
Interrupt Enable
0x1C
32
read-write
0
0xFFFFFFFF
CFR_IE
Comparator Flag Rising Interrupt Enable
0
1
read-write
DISABLE
Disables the comparator flag rising interrupt.
0
ENABLE
Enables the comparator flag rising interrupt when CFR is set.
0x1
CFF_IE
Comparator Flag Falling Interrupt Enable
1
1
read-write
DISABLE
Disables the comparator flag falling interrupt.
0
ENABLE
Enables the comparator flag falling interrupt when CFF is set.
0x1
RRF_IE
Round-Robin Flag Interrupt Enable
2
1
read-write
DISABLE
Disables the round-robin flag interrupt.
0
ENABLE
Enables the round-robin flag interrupt when the comparison result changes for a given channel.
0x1
CSR
Comparator Status
0x20
32
read-write
0
0xFFFFFFFF
CFR
Analog Comparator Flag Rising
0
1
read-write
oneToClear
NOT_DETECTED
Not detected
0
DETECTED
Detected
0x1
CFF
Analog Comparator Flag Falling
1
1
read-write
oneToClear
NOT_DETECTED
Not detected
0
DETECTED
Detected
0x1
RRF
Round-Robin Flag
2
1
read-write
oneToClear
NOT_DETECTED
Not detected
0
DETECTED
Detected
0x1
COUT
Analog Comparator Output
8
1
read-only
RRCR0
Round Robin Control Register 0
0x24
32
read-write
0
0xFFFFFFFF
RR_EN
Round-Robin Enable
0
1
read-write
DISABLE
Disables
0
ENABLE
Enables
0x1
RR_TRG_SEL
Round-Robin Trigger Select
1
1
read-write
ENABLE
External trigger
0
DISABLE
Internal trigger
0x1
RR_NSAM
Number of Sample Clocks
8
2
read-write
WAIT_0
0 clock
0
WAIT_1
1 clock
0x1
WAIT_2
2 clocks
0x2
WAIT_3
3 clocks
0x3
RR_CLK_SEL
Round Robin Clock Source Select
12
2
read-write
RR0
Select Round Robin clock Source 0
0
RR1
Select Round Robin clock Source 1
0x1
RR2
Select Round Robin clock Source 2
0x2
RR3
Select Round Robin clock Source 3
0x3
RR_INITMOD
Initialization Delay Modulus
16
6
read-write
MOD_63
63 cycles (same as 111111b)
0
MOD_1_63_1
1 to 63 cycles
0x1
MOD_1_63_2
1 to 63 cycles
0x2
MOD_1_63_3
1 to 63 cycles
0x3
MOD_1_63_4
1 to 63 cycles
0x4
MOD_1_63_5
1 to 63 cycles
0x5
MOD_1_63_6
1 to 63 cycles
0x6
MOD_1_63_7
1 to 63 cycles
0x7
MOD_1_63_8
1 to 63 cycles
0x8
MOD_1_63_9
1 to 63 cycles
0x9
RR_SAMPLE_CNT
Number of Sample for One Channel
24
4
read-write
SAMPLE_0
1 samples
0
SAMPLE_1
2 samples
0x1
SAMPLE_2
3 samples
0x2
SAMPLE_3
4 samples
0x3
SAMPLE_4
5 samples
0x4
SAMPLE_5
6 samples
0x5
SAMPLE_6
7 samples
0x6
SAMPLE_7
8 samples
0x7
SAMPLE_8
9 samples
0x8
SAMPLE_9
10 samples
0x9
SAMPLE_10
11 samples
0xA
SAMPLE_11
12 samples
0xB
SAMPLE_12
13 samples
0xC
SAMPLE_13
14 samples
0xD
SAMPLE_14
15 samples
0xE
SAMPLE_15
16 samples
0xF
RR_SAMPLE_THRESHOLD
Sample Time Threshold
28
4
read-write
SAMPLE_0
At least 1 sampled "1", the final result is "1"
0
SAMPLE_1
At least 2 sampled "1", the final result is "1"
0x1
SAMPLE_2
At least 3 sampled "1", the final result is "1"
0x2
SAMPLE_3
At least 4 sampled "1", the final result is "1"
0x3
SAMPLE_4
At least 5 sampled "1", the final result is "1"
0x4
SAMPLE_5
At least 6 sampled "1", the final result is "1"
0x5
SAMPLE_6
At least 7 sampled "1", the final result is "1"
0x6
SAMPLE_7
At least 8 sampled "1", the final result is "1"
0x7
SAMPLE_8
At least 9 sampled "1", the final result is "1"
0x8
SAMPLE_9
At least 10 sampled "1", the final result is "1"
0x9
SAMPLE_10
At least 11 sampled "1", the final result is "1"
0xA
SAMPLE_11
At least 12 sampled "1", the final result is "1"
0xB
SAMPLE_12
At least 13 sampled "1", the final result is "1"
0xC
SAMPLE_13
At least 14 sampled "1", the final result is "1"
0xD
SAMPLE_14
At least 15 sampled "1", the final result is "1"
0xE
SAMPLE_15
At least 16 sampled "1", the final result is "1"
0xF
RRCR1
Round Robin Control Register 1
0x28
32
read-write
0
0xFFFFFFFF
RR_CH0EN
Channel 0 Input Enable in Trigger Mode
0
1
read-write
DISABLE
Disables
0
ENABLE
Enables
0x1
RR_CH1EN
Channel 1 Input Enable in Trigger Mode
1
1
read-write
DISABLE
Disables
0
ENABLE
Enables
0x1
RR_CH2EN
Channel 2 Input Enable in Trigger Mode
2
1
read-write
DISABLE
Disables
0
ENABLE
Enables
0x1
RR_CH3EN
Channel 3 Input Enable in Trigger Mode
3
1
read-write
DISABLE
Disables
0
ENABLE
Enables
0x1
RR_CH4EN
Channel 4 Input Enable in Trigger Mode
4
1
read-write
DISABLE
Disables
0
ENABLE
Enables
0x1
RR_CH5EN
Channel 5 Input Enable in Trigger Mode
5
1
read-write
DISABLE
Disables
0
ENABLE
Enables
0x1
RR_CH6EN
Channel 6 Input Enable in Trigger Mode
6
1
read-write
DISABLE
Disables
0
ENABLE
Enables
0x1
RR_CH7EN
Channel 7 Input Enable in Trigger Mode
7
1
read-write
DISABLE
Disables
0
ENABLE
Enables
0x1
FIXP
Fixed Port
16
1
read-write
FIX_PLUS
Fix the plus port. Sweep only the inputs to the minus port.
0
FIX_MINUS
Fix the minus port. Sweep only the inputs to the plus port.
0x1
FIXCH
Fixed Channel Select
20
3
read-write
FIX_CH0
Channel 0
0
FIX_CH1
Channel 1
0x1
FIX_CH2
Channel 2
0x2
FIX_CH3
Channel 3
0x3
FIX_CH4
Channel 4
0x4
FIX_CH5
Channel 5
0x5
FIX_CH6
Channel 6
0x6
FIX_CH7
Channel 7
0x7
RRCSR
Round Robin Control and Status
0x2C
32
read-write
0
0xFFFFFFFF
RR_CH0OUT
Comparison Result for Channel 0
0
1
read-write
RR_CH1OUT
Comparison Result for Channel 1
1
1
read-write
RR_CH2OUT
Comparison Result for Channel 2
2
1
read-write
RR_CH3OUT
Comparison Result for Channel 3
3
1
read-write
RR_CH4OUT
Comparison Result for Channel 4
4
1
read-write
RR_CH5OUT
Comparison Result for Channel 5
5
1
read-write
RR_CH6OUT
Comparison Result for Channel 6
6
1
read-write
RR_CH7OUT
Comparison Result for Channel 7
7
1
read-write
RRSR
Round Robin Status
0x30
32
read-write
0
0xFFFFFFFF
oneToClear
RR_CH0F
Channel 0 Input Changed Flag
0
1
read-write
oneToClear
NOT_DIFFERENT
Not different
0
DIFFERENT
Different
0x1
RR_CH1F
Channel 1 Input Changed Flag
1
1
read-write
oneToClear
NOT_DIFFERENT
Not different
0
DIFFERENT
Different
0x1
RR_CH2F
Channel 2 Input Changed Flag
2
1
read-write
oneToClear
NOT_DIFFERENT
Not different
0
DIFFERENT
Different
0x1
RR_CH3F
Channel 3 Input Changed Flag
3
1
read-write
oneToClear
NOT_DIFFERENT
Not different
0
DIFFERENT
Different
0x1
RR_CH4F
Channel 4 Input Changed Flag
4
1
read-write
oneToClear
NOT_DIFFERENT
Not different
0
DIFFERENT
Different
0x1
RR_CH5F
Channel 5 Input Changed Flag
5
1
read-write
oneToClear
NOT_DIFFERENT
Not different
0
DIFFERENT
Different
0x1
RR_CH6F
Channel 6 Input Changed Flag
6
1
read-write
oneToClear
NOT_DIFFERENT
Not different
0
DIFFERENT
Different
0x1
RR_CH7F
Channel 7 Input Changed Flag
7
1
read-write
oneToClear
NOT_DIFFERENT
Not different
0
DIFFERENT
Different
0x1
RRCR2
Round Robin Control Register 2
0x38
32
read-write
0
0xFFFFFFFF
RR_TIMER_RELOAD
Number of Sample Clocks
0
28
read-write
RR_TIMER_EN
Round-Robin Internal Timer Enable
31
1
read-write
DISABLE
Disables
0
ENABLE
Enables
0x1
CMP1
LPCMP
CMP
0x400B2000
0
0x3C
registers
CMP1
65
PORT0
PORT
PORT
0x400BC000
0
0xC8
registers
VERID
Version ID
0
32
read-only
0x2000000
0xFFFFFFFF
FEATURE
Feature Specification Number
0
16
read-only
feature0
Basic implementation
0
MINOR
Minor Version Number
16
8
read-only
MAJOR
Major Version Number
24
8
read-only
GPCLR
Global Pin Control Low
0x10
32
read-write
0
0xFFFFFFFF
GPWD
Global Pin Write Data
0
16
read-write
GPWE0
Global Pin Write Enable
16
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE1
Global Pin Write Enable
17
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE2
Global Pin Write Enable
18
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE3
Global Pin Write Enable
19
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE4
Global Pin Write Enable
20
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE5
Global Pin Write Enable
21
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE6
Global Pin Write Enable
22
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE7
Global Pin Write Enable
23
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE8
Global Pin Write Enable
24
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE9
Global Pin Write Enable
25
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE10
Global Pin Write Enable
26
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE11
Global Pin Write Enable
27
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE12
Global Pin Write Enable
28
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE13
Global Pin Write Enable
29
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE14
Global Pin Write Enable
30
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE15
Global Pin Write Enable
31
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPCHR
Global Pin Control High
0x14
32
read-write
0
0xFFFFFFFF
GPWD
Global Pin Write Data
0
16
read-write
GPWE16
Global Pin Write Enable
16
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE17
Global Pin Write Enable
17
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE18
Global Pin Write Enable
18
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE19
Global Pin Write Enable
19
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE20
Global Pin Write Enable
20
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE21
Global Pin Write Enable
21
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE22
Global Pin Write Enable
22
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE23
Global Pin Write Enable
23
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE24
Global Pin Write Enable
24
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE25
Global Pin Write Enable
25
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE26
Global Pin Write Enable
26
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE27
Global Pin Write Enable
27
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE28
Global Pin Write Enable
28
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE29
Global Pin Write Enable
29
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE30
Global Pin Write Enable
30
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE31
Global Pin Write Enable
31
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
CONFIG
Configuration
0x20
32
read-write
0
0xFFFFFFFF
RANGE
Port Voltage Range
0
1
read-write
range0
1.71 V-3.6 V
0
range1
2.70 V-3.6 V
0x1
PCR0
Pin Control 0
0x80
32
read-write
0x1143
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
3
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR1
Pin Control 1
0x84
32
read-write
0x1102
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
3
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR2
Pin Control 2
0x88
32
read-write
0x140
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
4
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
mux1000
Alternative 8 (chip-specific)
0x8
mux1001
Alternative 9 (chip-specific)
0x9
mux1010
Alternative 10 (chip-specific)
0xA
mux1011
Alternative 11 (chip-specific)
0xB
mux1100
Alternative 12 (chip-specific)
0xC
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR3
Pin Control 3
0x8C
32
read-write
0x1103
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
4
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
mux1000
Alternative 8 (chip-specific)
0x8
mux1001
Alternative 9 (chip-specific)
0x9
mux1010
Alternative 10 (chip-specific)
0xA
mux1011
Alternative 11 (chip-specific)
0xB
mux1100
Alternative 12 (chip-specific)
0xC
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR6
Pin Control 6
0x98
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
4
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
mux1000
Alternative 8 (chip-specific)
0x8
mux1001
Alternative 9 (chip-specific)
0x9
mux1010
Alternative 10 (chip-specific)
0xA
mux1011
Alternative 11 (chip-specific)
0xB
mux1100
Alternative 12 (chip-specific)
0xC
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR16
Pin Control 16
0xC0
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
PV
Pull Value
2
1
read-write
pv0
Low
0
pv1
High
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
PFE
Passive Filter Enable
4
1
read-write
pfe0
Disables
0
pfe1
Enables
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
DSE1
Drive Strength Enable
7
1
read-write
dse10
Normal
0
dse11
Double
0x1
MUX
Pin Multiplex Control
8
4
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
mux1000
Alternative 8 (chip-specific)
0x8
mux1001
Alternative 9 (chip-specific)
0x9
mux1010
Alternative 10 (chip-specific)
0xA
mux1011
Alternative 11 (chip-specific)
0xB
mux1100
Alternative 12 (chip-specific)
0xC
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR17
Pin Control 17
0xC4
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
PFE
Passive Filter Enable
4
1
read-write
pfe0
Disables
0
pfe1
Enables
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
DSE1
Drive Strength Enable
7
1
read-write
dse10
Normal
0
dse11
Double
0x1
MUX
Pin Multiplex Control
8
4
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
mux1000
Alternative 8 (chip-specific)
0x8
mux1001
Alternative 9 (chip-specific)
0x9
mux1010
Alternative 10 (chip-specific)
0xA
mux1011
Alternative 11 (chip-specific)
0xB
mux1100
Alternative 12 (chip-specific)
0xC
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PORT1
PORT
PORT
0x400BD000
0
0x100
registers
VERID
Version ID
0
32
read-only
0x2000000
0xFFFFFFFF
FEATURE
Feature Specification Number
0
16
read-only
feature0
Basic implementation
0
MINOR
Minor Version Number
16
8
read-only
MAJOR
Major Version Number
24
8
read-only
GPCLR
Global Pin Control Low
0x10
32
read-write
0
0xFFFFFFFF
GPWD
Global Pin Write Data
0
16
read-write
GPWE0
Global Pin Write Enable
16
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE1
Global Pin Write Enable
17
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE2
Global Pin Write Enable
18
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE3
Global Pin Write Enable
19
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE4
Global Pin Write Enable
20
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE5
Global Pin Write Enable
21
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE6
Global Pin Write Enable
22
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE7
Global Pin Write Enable
23
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE8
Global Pin Write Enable
24
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE9
Global Pin Write Enable
25
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE10
Global Pin Write Enable
26
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE11
Global Pin Write Enable
27
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE12
Global Pin Write Enable
28
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE13
Global Pin Write Enable
29
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE14
Global Pin Write Enable
30
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE15
Global Pin Write Enable
31
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPCHR
Global Pin Control High
0x14
32
read-write
0
0xFFFFFFFF
GPWD
Global Pin Write Data
0
16
read-write
GPWE16
Global Pin Write Enable
16
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE17
Global Pin Write Enable
17
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE18
Global Pin Write Enable
18
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE19
Global Pin Write Enable
19
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE20
Global Pin Write Enable
20
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE21
Global Pin Write Enable
21
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE22
Global Pin Write Enable
22
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE23
Global Pin Write Enable
23
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE24
Global Pin Write Enable
24
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE25
Global Pin Write Enable
25
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE26
Global Pin Write Enable
26
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE27
Global Pin Write Enable
27
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE28
Global Pin Write Enable
28
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE29
Global Pin Write Enable
29
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE30
Global Pin Write Enable
30
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE31
Global Pin Write Enable
31
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
CONFIG
Configuration
0x20
32
read-write
0
0xFFFFFFFF
RANGE
Port Voltage Range
0
1
read-write
range0
1.71 V-3.6 V
0
range1
2.70 V-3.6 V
0x1
CALIB0
Calibration 0
0x60
32
read-write
0
0xFFC0FFC0
NCAL
Calibration of NMOS Output Driver
0
6
read-write
PCAL
Calibration of PMOS Output Driver
16
6
read-write
CALIB1
Calibration 1
0x64
32
read-write
0
0xFFC0FFC0
NCAL
Calibration of NMOS Output Driver
0
6
read-write
PCAL
Calibration of PMOS Output Driver
16
6
read-write
PCR0
Pin Control 0
0x80
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
PFE
Passive Filter Enable
4
1
read-write
pfe0
Disables
0
pfe1
Enables
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
3
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR1
Pin Control 1
0x84
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
PFE
Passive Filter Enable
4
1
read-write
pfe0
Disables
0
pfe1
Enables
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
3
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR2
Pin Control 2
0x88
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
4
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
mux1000
Alternative 8 (chip-specific)
0x8
mux1001
Alternative 9 (chip-specific)
0x9
mux1010
Alternative 10 (chip-specific)
0xA
mux1011
Alternative 11 (chip-specific)
0xB
mux1100
Alternative 12 (chip-specific)
0xC
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR3
Pin Control 3
0x8C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
3
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR4
Pin Control 4
0x90
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
4
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
mux1000
Alternative 8 (chip-specific)
0x8
mux1001
Alternative 9 (chip-specific)
0x9
mux1010
Alternative 10 (chip-specific)
0xA
mux1011
Alternative 11 (chip-specific)
0xB
mux1100
Alternative 12 (chip-specific)
0xC
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR5
Pin Control 5
0x94
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
4
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
mux1000
Alternative 8 (chip-specific)
0x8
mux1001
Alternative 9 (chip-specific)
0x9
mux1010
Alternative 10 (chip-specific)
0xA
mux1011
Alternative 11 (chip-specific)
0xB
mux1100
Alternative 12 (chip-specific)
0xC
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR6
Pin Control 6
0x98
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
4
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
mux1000
Alternative 8 (chip-specific)
0x8
mux1001
Alternative 9 (chip-specific)
0x9
mux1010
Alternative 10 (chip-specific)
0xA
mux1011
Alternative 11 (chip-specific)
0xB
mux1100
Alternative 12 (chip-specific)
0xC
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR7
Pin Control 7
0x9C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
4
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
mux1000
Alternative 8 (chip-specific)
0x8
mux1001
Alternative 9 (chip-specific)
0x9
mux1010
Alternative 10 (chip-specific)
0xA
mux1011
Alternative 11 (chip-specific)
0xB
mux1100
Alternative 12 (chip-specific)
0xC
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR8
Pin Control 8
0xA0
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
PV
Pull Value
2
1
read-write
pv0
Low
0
pv1
High
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
PFE
Passive Filter Enable
4
1
read-write
pfe0
Disables
0
pfe1
Enables
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
DSE1
Drive Strength Enable
7
1
read-write
dse10
Normal
0
dse11
Double
0x1
MUX
Pin Multiplex Control
8
4
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
mux1000
Alternative 8 (chip-specific)
0x8
mux1001
Alternative 9 (chip-specific)
0x9
mux1010
Alternative 10 (chip-specific)
0xA
mux1011
Alternative 11 (chip-specific)
0xB
mux1100
Alternative 12 (chip-specific)
0xC
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR9
Pin Control 9
0xA4
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
PFE
Passive Filter Enable
4
1
read-write
pfe0
Disables
0
pfe1
Enables
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
DSE1
Drive Strength Enable
7
1
read-write
dse10
Normal
0
dse11
Double
0x1
MUX
Pin Multiplex Control
8
4
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
mux1000
Alternative 8 (chip-specific)
0x8
mux1001
Alternative 9 (chip-specific)
0x9
mux1010
Alternative 10 (chip-specific)
0xA
mux1011
Alternative 11 (chip-specific)
0xB
mux1100
Alternative 12 (chip-specific)
0xC
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR10
Pin Control 10
0xA8
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
4
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
mux1000
Alternative 8 (chip-specific)
0x8
mux1001
Alternative 9 (chip-specific)
0x9
mux1010
Alternative 10 (chip-specific)
0xA
mux1011
Alternative 11 (chip-specific)
0xB
mux1100
Alternative 12 (chip-specific)
0xC
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR11
Pin Control 11
0xAC
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
4
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
mux1000
Alternative 8 (chip-specific)
0x8
mux1001
Alternative 9 (chip-specific)
0x9
mux1010
Alternative 10 (chip-specific)
0xA
mux1011
Alternative 11 (chip-specific)
0xB
mux1100
Alternative 12 (chip-specific)
0xC
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR12
Pin Control 12
0xB0
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
4
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
mux1000
Alternative 8 (chip-specific)
0x8
mux1001
Alternative 9 (chip-specific)
0x9
mux1010
Alternative 10 (chip-specific)
0xA
mux1011
Alternative 11 (chip-specific)
0xB
mux1100
Alternative 12 (chip-specific)
0xC
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR13
Pin Control 13
0xB4
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
4
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
mux1000
Alternative 8 (chip-specific)
0x8
mux1001
Alternative 9 (chip-specific)
0x9
mux1010
Alternative 10 (chip-specific)
0xA
mux1011
Alternative 11 (chip-specific)
0xB
mux1100
Alternative 12 (chip-specific)
0xC
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR29
Pin Control 29
0xF4
32
read-write
0x133
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
PV
Pull Value
2
1
read-write
pv0
Low
0
pv1
High
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
PFE
Passive Filter Enable
4
1
read-write
pfe0
Disables
0
pfe1
Enables
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
2
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR30
Pin Control 30
0xF8
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
PV
Pull Value
2
1
read-write
pv0
Low
0
pv1
High
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
PFE
Passive Filter Enable
4
1
read-write
pfe0
Disables
0
pfe1
Enables
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
DSE1
Drive Strength Enable
7
1
read-write
dse10
Normal
0
dse11
Double
0x1
MUX
Pin Multiplex Control
8
4
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
mux1000
Alternative 8 (chip-specific)
0x8
mux1001
Alternative 9 (chip-specific)
0x9
mux1010
Alternative 10 (chip-specific)
0xA
mux1011
Alternative 11 (chip-specific)
0xB
mux1100
Alternative 12 (chip-specific)
0xC
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR31
Pin Control 31
0xFC
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
PFE
Passive Filter Enable
4
1
read-write
pfe0
Disables
0
pfe1
Enables
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
DSE1
Drive Strength Enable
7
1
read-write
dse10
Normal
0
dse11
Double
0x1
MUX
Pin Multiplex Control
8
4
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
mux1000
Alternative 8 (chip-specific)
0x8
mux1001
Alternative 9 (chip-specific)
0x9
mux1010
Alternative 10 (chip-specific)
0xA
mux1011
Alternative 11 (chip-specific)
0xB
mux1100
Alternative 12 (chip-specific)
0xC
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PORT2
PORT
PORT
0x400BE000
0
0xD8
registers
VERID
Version ID
0
32
read-only
0x2000000
0xFFFFFFFF
FEATURE
Feature Specification Number
0
16
read-only
feature0
Basic implementation
0
MINOR
Minor Version Number
16
8
read-only
MAJOR
Major Version Number
24
8
read-only
GPCLR
Global Pin Control Low
0x10
32
read-write
0
0xFFFFFFFF
GPWD
Global Pin Write Data
0
16
read-write
GPWE0
Global Pin Write Enable
16
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE1
Global Pin Write Enable
17
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE2
Global Pin Write Enable
18
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE3
Global Pin Write Enable
19
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE4
Global Pin Write Enable
20
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE5
Global Pin Write Enable
21
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE6
Global Pin Write Enable
22
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE7
Global Pin Write Enable
23
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE8
Global Pin Write Enable
24
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE9
Global Pin Write Enable
25
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE10
Global Pin Write Enable
26
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE11
Global Pin Write Enable
27
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE12
Global Pin Write Enable
28
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE13
Global Pin Write Enable
29
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE14
Global Pin Write Enable
30
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE15
Global Pin Write Enable
31
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPCHR
Global Pin Control High
0x14
32
read-write
0
0xFFFFFFFF
GPWD
Global Pin Write Data
0
16
read-write
GPWE16
Global Pin Write Enable
16
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE17
Global Pin Write Enable
17
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE18
Global Pin Write Enable
18
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE19
Global Pin Write Enable
19
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE20
Global Pin Write Enable
20
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE21
Global Pin Write Enable
21
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE22
Global Pin Write Enable
22
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE23
Global Pin Write Enable
23
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE24
Global Pin Write Enable
24
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE25
Global Pin Write Enable
25
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE26
Global Pin Write Enable
26
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE27
Global Pin Write Enable
27
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE28
Global Pin Write Enable
28
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE29
Global Pin Write Enable
29
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE30
Global Pin Write Enable
30
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE31
Global Pin Write Enable
31
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
CONFIG
Configuration
0x20
32
read-write
0
0xFFFFFFFF
RANGE
Port Voltage Range
0
1
read-write
range0
1.71 V-3.6 V
0
range1
2.70 V-3.6 V
0x1
PCR0
Pin Control 0
0x80
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
3
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR1
Pin Control 1
0x84
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
3
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR2
Pin Control 2
0x88
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
3
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR3
Pin Control 3
0x8C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
4
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
mux1000
Alternative 8 (chip-specific)
0x8
mux1001
Alternative 9 (chip-specific)
0x9
mux1010
Alternative 10 (chip-specific)
0xA
mux1011
Alternative 11 (chip-specific)
0xB
mux1100
Alternative 12 (chip-specific)
0xC
mux1101
Alternative 13 (chip-specific)
0xD
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR4
Pin Control 4
0x90
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
3
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR5
Pin Control 5
0x94
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
3
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR6
Pin Control 6
0x98
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
3
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR7
Pin Control 7
0x9C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
3
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR12
Pin Control 12
0xB0
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
3
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR13
Pin Control 13
0xB4
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
3
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR16
Pin Control 16
0xC0
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
3
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR17
Pin Control 17
0xC4
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
3
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR20
Pin Control 20
0xD0
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
3
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR21
Pin Control 21
0xD4
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
3
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PORT3
PORT
PORT
0x400BF000
0
0x100
registers
VERID
Version ID
0
32
read-only
0x2000000
0xFFFFFFFF
FEATURE
Feature Specification Number
0
16
read-only
feature0
Basic implementation
0
MINOR
Minor Version Number
16
8
read-only
MAJOR
Major Version Number
24
8
read-only
GPCLR
Global Pin Control Low
0x10
32
read-write
0
0xFFFFFFFF
GPWD
Global Pin Write Data
0
16
read-write
GPWE0
Global Pin Write Enable
16
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE1
Global Pin Write Enable
17
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE2
Global Pin Write Enable
18
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE3
Global Pin Write Enable
19
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE4
Global Pin Write Enable
20
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE5
Global Pin Write Enable
21
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE6
Global Pin Write Enable
22
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE7
Global Pin Write Enable
23
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE8
Global Pin Write Enable
24
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE9
Global Pin Write Enable
25
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE10
Global Pin Write Enable
26
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE11
Global Pin Write Enable
27
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE12
Global Pin Write Enable
28
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE13
Global Pin Write Enable
29
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE14
Global Pin Write Enable
30
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE15
Global Pin Write Enable
31
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPCHR
Global Pin Control High
0x14
32
read-write
0
0xFFFFFFFF
GPWD
Global Pin Write Data
0
16
read-write
GPWE16
Global Pin Write Enable
16
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE17
Global Pin Write Enable
17
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE18
Global Pin Write Enable
18
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE19
Global Pin Write Enable
19
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE20
Global Pin Write Enable
20
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE21
Global Pin Write Enable
21
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE22
Global Pin Write Enable
22
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE23
Global Pin Write Enable
23
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE24
Global Pin Write Enable
24
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE25
Global Pin Write Enable
25
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE26
Global Pin Write Enable
26
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE27
Global Pin Write Enable
27
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE28
Global Pin Write Enable
28
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE29
Global Pin Write Enable
29
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE30
Global Pin Write Enable
30
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
GPWE31
Global Pin Write Enable
31
1
read-write
gpwe0
Not updated
0
gpwe1
Updated
0x1
CONFIG
Configuration
0x20
32
read-write
0
0xFFFFFFFF
RANGE
Port Voltage Range
0
1
read-write
range0
1.71 V-3.6 V
0
range1
2.70 V-3.6 V
0x1
CALIB0
Calibration 0
0x60
32
read-write
0
0xFFC0FFC0
NCAL
Calibration of NMOS Output Driver
0
6
read-write
PCAL
Calibration of PMOS Output Driver
16
6
read-write
CALIB1
Calibration 1
0x64
32
read-write
0
0xFFC0FFC0
NCAL
Calibration of NMOS Output Driver
0
6
read-write
PCAL
Calibration of PMOS Output Driver
16
6
read-write
PCR0
Pin Control 0
0x80
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
PFE
Passive Filter Enable
4
1
read-write
pfe0
Disables
0
pfe1
Enables
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
DSE1
Drive Strength Enable
7
1
read-write
dse10
Normal
0
dse11
Double
0x1
MUX
Pin Multiplex Control
8
4
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
mux1000
Alternative 8 (chip-specific)
0x8
mux1001
Alternative 9 (chip-specific)
0x9
mux1010
Alternative 10 (chip-specific)
0xA
mux1011
Alternative 11 (chip-specific)
0xB
mux1100
Alternative 12 (chip-specific)
0xC
mux1101
Alternative 13 (chip-specific)
0xD
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR1
Pin Control 1
0x84
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
PFE
Passive Filter Enable
4
1
read-write
pfe0
Disables
0
pfe1
Enables
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
DSE1
Drive Strength Enable
7
1
read-write
dse10
Normal
0
dse11
Double
0x1
MUX
Pin Multiplex Control
8
4
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
mux1000
Alternative 8 (chip-specific)
0x8
mux1001
Alternative 9 (chip-specific)
0x9
mux1010
Alternative 10 (chip-specific)
0xA
mux1011
Alternative 11 (chip-specific)
0xB
mux1100
Alternative 12 (chip-specific)
0xC
mux1101
Alternative 13 (chip-specific)
0xD
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR2
Pin Control 2
0x88
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
2
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR6
Pin Control 6
0x98
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
4
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
mux1000
Alternative 8 (chip-specific)
0x8
mux1001
Alternative 9 (chip-specific)
0x9
mux1010
Alternative 10 (chip-specific)
0xA
mux1011
Alternative 11 (chip-specific)
0xB
mux1100
Alternative 12 (chip-specific)
0xC
mux1101
Alternative 13 (chip-specific)
0xD
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR7
Pin Control 7
0x9C
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
3
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR8
Pin Control 8
0xA0
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
4
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
mux1000
Alternative 8 (chip-specific)
0x8
mux1001
Alternative 9 (chip-specific)
0x9
mux1010
Alternative 10 (chip-specific)
0xA
mux1011
Alternative 11 (chip-specific)
0xB
mux1100
Alternative 12 (chip-specific)
0xC
mux1101
Alternative 13 (chip-specific)
0xD
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR9
Pin Control 9
0xA4
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
4
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
mux1000
Alternative 8 (chip-specific)
0x8
mux1001
Alternative 9 (chip-specific)
0x9
mux1010
Alternative 10 (chip-specific)
0xA
mux1011
Alternative 11 (chip-specific)
0xB
mux1100
Alternative 12 (chip-specific)
0xC
mux1101
Alternative 13 (chip-specific)
0xD
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR10
Pin Control 10
0xA8
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
4
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
mux1000
Alternative 8 (chip-specific)
0x8
mux1001
Alternative 9 (chip-specific)
0x9
mux1010
Alternative 10 (chip-specific)
0xA
mux1011
Alternative 11 (chip-specific)
0xB
mux1100
Alternative 12 (chip-specific)
0xC
mux1101
Alternative 13 (chip-specific)
0xD
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR11
Pin Control 11
0xAC
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
4
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
mux1000
Alternative 8 (chip-specific)
0x8
mux1001
Alternative 9 (chip-specific)
0x9
mux1010
Alternative 10 (chip-specific)
0xA
mux1011
Alternative 11 (chip-specific)
0xB
mux1100
Alternative 12 (chip-specific)
0xC
mux1101
Alternative 13 (chip-specific)
0xD
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR12
Pin Control 12
0xB0
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
4
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
mux1000
Alternative 8 (chip-specific)
0x8
mux1001
Alternative 9 (chip-specific)
0x9
mux1010
Alternative 10 (chip-specific)
0xA
mux1011
Alternative 11 (chip-specific)
0xB
mux1100
Alternative 12 (chip-specific)
0xC
mux1101
Alternative 13 (chip-specific)
0xD
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR13
Pin Control 13
0xB4
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
4
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
mux1000
Alternative 8 (chip-specific)
0x8
mux1001
Alternative 9 (chip-specific)
0x9
mux1010
Alternative 10 (chip-specific)
0xA
mux1011
Alternative 11 (chip-specific)
0xB
mux1100
Alternative 12 (chip-specific)
0xC
mux1101
Alternative 13 (chip-specific)
0xD
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR14
Pin Control 14
0xB8
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
4
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
mux1000
Alternative 8 (chip-specific)
0x8
mux1001
Alternative 9 (chip-specific)
0x9
mux1010
Alternative 10 (chip-specific)
0xA
mux1011
Alternative 11 (chip-specific)
0xB
mux1100
Alternative 12 (chip-specific)
0xC
mux1101
Alternative 13 (chip-specific)
0xD
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR15
Pin Control 15
0xBC
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
4
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
mux1000
Alternative 8 (chip-specific)
0x8
mux1001
Alternative 9 (chip-specific)
0x9
mux1010
Alternative 10 (chip-specific)
0xA
mux1011
Alternative 11 (chip-specific)
0xB
mux1100
Alternative 12 (chip-specific)
0xC
mux1101
Alternative 13 (chip-specific)
0xD
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR27
Pin Control 27
0xEC
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
DSE1
Drive Strength Enable
7
1
read-write
dse10
Normal
0
dse11
Double
0x1
MUX
Pin Multiplex Control
8
3
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR28
Pin Control 28
0xF0
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
DSE1
Drive Strength Enable
7
1
read-write
dse10
Normal
0
dse11
Double
0x1
MUX
Pin Multiplex Control
8
3
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR29
Pin Control 29
0xF4
32
read-write
0x1103
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
3
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR30
Pin Control 30
0xF8
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
3
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
PCR31
Pin Control 31
0xFC
32
read-write
0
0xFFFFFFFF
PS
Pull Select
0
1
read-write
ps0
Enables internal pulldown resistor
0
ps1
Enables internal pullup resistor
0x1
PE
Pull Enable
1
1
read-write
pe0
Disables
0
pe1
Enables
0x1
SRE
Slew Rate Enable
3
1
read-write
sre0
Fast
0
sre1
Slow
0x1
ODE
Open Drain Enable
5
1
read-write
ode0
Disables
0
ode1
Enables
0x1
DSE
Drive Strength Enable
6
1
read-write
dse0
Low
0
dse1
High
0x1
MUX
Pin Multiplex Control
8
3
read-write
mux00
Alternative 0 (GPIO)
0
mux01
Alternative 1 (chip-specific)
0x1
mux10
Alternative 2 (chip-specific)
0x2
mux11
Alternative 3 (chip-specific)
0x3
mux100
Alternative 4 (chip-specific)
0x4
mux101
Alternative 5 (chip-specific)
0x5
mux110
Alternative 6 (chip-specific)
0x6
mux111
Alternative 7 (chip-specific)
0x7
IBE
Input Buffer Enable
12
1
read-write
ibe0
Disables
0
ibe1
Enables
0x1
INV
Invert Input
13
1
read-write
inv0
Does not invert
0
inv1
Inverts
0x1
LK
Lock Register
15
1
read-write
lk0
Does not lock
0
lk1
Locks
0x1
CDOG
CDOG
CDOG
0x40100000
0
0x50
registers
CDOG0
38
CONTROL
Control Register
0
32
read-write
0x50092492
0xFFFFFFFF
LOCK_CTRL
Lock control
0
2
read-write
LOCKED
Locked
0x1
UNLOCKED
Unlocked
0x2
TIMEOUT_CTRL
TIMEOUT fault control
2
3
read-write
ENABLE_RESET
Enable reset
0x1
ENABLE_INTERRUPT
Enable interrupt
0x2
DISABLE_BOTH
Disable both reset and interrupt
0x4
MISCOMPARE_CTRL
MISCOMPARE fault control
5
3
read-write
ENABLE_RESET
Enable reset
0x1
ENABLE_INTERRUPT
Enable interrupt
0x2
DISABLE_BOTH
Disable both reset and interrupt
0x4
SEQUENCE_CTRL
SEQUENCE fault control
8
3
read-write
ENABLE_RESET
Enable reset
0x1
ENABLE_INTERRUPT
Enable interrupt
0x2
DISABLE_BOTH
Disable both reset and interrupt
0x4
STATE_CTRL
STATE fault control
14
3
read-write
ENABLE_RESET
Enable reset
0x1
ENABLE_INTERRUPT
Enable interrupt
0x2
DISABLE_BOTH
Disable both reset and interrupt
0x4
ADDRESS_CTRL
ADDRESS fault control
17
3
read-write
ENABLE_RESET
Enable reset
0x1
ENABLE_INTERRUPT
Enable interrupt
0x2
DISABLE_BOTH
Disable both reset and interrupt
0x4
IRQ_PAUSE
IRQ pause control
28
2
read-write
RUN_TIMER
Keep the timer running
0x1
PAUSE_TIMER
Stop the timer
0x2
DEBUG_HALT_CTRL
DEBUG_HALT control
30
2
read-write
RUN_TIMER
Keep the timer running
0x1
PAUSE_TIMER
Stop the timer
0x2
RELOAD
Instruction Timer Reload Register
0x4
32
read-write
0xFFFFFFFF
0xFFFFFFFF
RLOAD
Instruction Timer reload value
0
32
read-write
INSTRUCTION_TIMER
Instruction Timer Register
0x8
32
read-only
0xFFFFFFFF
0xFFFFFFFF
INSTIM
Current value of the Instruction Timer
0
32
read-only
STATUS
Status 1 Register
0x10
32
read-only
0x50000000
0xFFFFFFFF
NUMTOF
Number of TIMEOUT faults since the last POR
0
8
read-only
NUMMISCOMPF
Number of MISCOMPARE faults since the last POR
8
8
read-only
NUMILSEQF
Number of SEQUENCE faults since the last POR
16
8
read-only
CURST
Current State
28
4
read-only
STATUS2
Status 2 Register
0x14
32
read-only
0
0xFFFFFFFF
NUMCNTF
Number of CONTROL faults since the last POR
0
8
read-only
NUMILLSTF
Number of STATE faults since the last POR
8
8
read-only
NUMILLA
Number of ADDRESS faults since the last POR
16
8
read-only
FLAGS
Flags Register
0x18
32
read-write
0x10000
0xFFFFFFFF
oneToClear
TO_FLAG
TIMEOUT fault flag
0
1
read-write
oneToClear
NO_FLAG
A TIMEOUT fault has not occurred
0
FLAG
A TIMEOUT fault has occurred
0x1
MISCOM_FLAG
MISCOMPARE fault flag
1
1
read-write
oneToClear
NO_FLAG
A MISCOMPARE fault has not occurred
0
FLAG
A MISCOMPARE fault has occurred
0x1
SEQ_FLAG
SEQUENCE fault flag
2
1
read-write
oneToClear
NO_FLAG
A SEQUENCE fault has not occurred
0
FLAG
A SEQUENCE fault has occurred
0x1
CNT_FLAG
CONTROL fault flag
3
1
read-write
oneToClear
NO_FLAG
A CONTROL fault has not occurred
0
FLAG
A CONTROL fault has occurred
0x1
STATE_FLAG
STATE fault flag
4
1
read-write
oneToClear
NO_FLAG
A STATE fault has not occurred
0
FLAG
A STATE fault has occurred
0x1
ADDR_FLAG
ADDRESS fault flag
5
1
read-write
oneToClear
NO_FLAG
An ADDRESS fault has not occurred
0
FLAG
An ADDRESS fault has occurred
0x1
POR_FLAG
Power-on reset flag
16
1
read-write
oneToClear
NO_FLAG
A Power-on reset event has not occurred
0
FLAG
A Power-on reset event has occurred
0x1
PERSISTENT
Persistent Data Storage Register
0x1C
32
read-write
0
0xFFFFFFFF
PERSIS
Persistent Storage
0
32
read-write
START
START Command Register
0x20
32
write-only
0
0xFFFFFFFF
STRT
Start command
0
32
write-only
STOP
STOP Command Register
0x24
32
write-only
0
0xFFFFFFFF
STP
Stop command
0
32
write-only
RESTART
RESTART Command Register
0x28
32
write-only
0
0xFFFFFFFF
RSTRT
Restart command
0
32
write-only
ADD
ADD Command Register
0x2C
32
write-only
0
0xFFFFFFFF
AD
ADD Write Value
0
32
write-only
ADD1
ADD1 Command Register
0x30
32
write-only
0
0xFFFFFFFF
AD1
ADD 1
0
32
write-only
ADD16
ADD16 Command Register
0x34
32
write-only
0
0xFFFFFFFF
AD16
ADD 16
0
32
write-only
ADD256
ADD256 Command Register
0x38
32
write-only
0
0xFFFFFFFF
AD256
ADD 256
0
32
write-only
SUB
SUB Command Register
0x3C
32
write-only
0
0xFFFFFFFF
SB
Subtract Write Value
0
32
write-only
SUB1
SUB1 Command Register
0x40
32
write-only
0
0xFFFFFFFF
SB1
Subtract 1
0
32
write-only
SUB16
SUB16 Command Register
0x44
32
write-only
0
0xFFFFFFFF
SB16
Subtract 16
0
32
write-only
SUB256
SUB256 Command Register
0x48
32
write-only
0
0xFFFFFFFF
SB256
Subtract 256
0
32
write-only
ASSERT16
ASSERT16 Command Register
0x4C
32
write-only
0
0xFFFFFFFF
AST16
ASSERT16 Command
0
32
write-only
DBGMAILBOX
DBGMB
DEBUGMAILBOX
0x40101000
0
0x100
registers
CSW
Command and Status Word
0
32
read-write
0
0xFFFFFFFF
RESYNCH_REQ
Resynchronization Request
0
1
read-write
NO_REQUEST
No request
0
REQUEST
Request for resynchronization
0x1
REQ_PENDING
Request Pending
1
1
read-write
NO_REQUEST_PENDING
No request pending
0
REQUEST_PENDING
Request for resynchronization pending
0x1
DBG_OR_ERR
DBGMB Overrun Error
2
1
read-write
NO_OVERRUN_ERR
No DBGMB Overrun error
0
OVERRUN_ERR
DBGMB overrun error. A DBGMB overrun occurred.
0x1
AHB_OR_ERR
AHB Overrun Error
3
1
read-write
NO_AHB_OVERRUN_ERR
No AHB Overrun Error
0
AHB_OVERRUN_ERR
AHB Overrun Error. An AHB overrun occurred.
0x1
SOFT_RESET
Soft Reset
4
1
read-write
CHIP_RESET_REQ
Chip Reset Request
5
1
read-write
REQUEST
Request Value
0x4
32
read-write
0
0xFFFFFFFF
REQUEST
Request Value
0
32
read-write
RETURN
Return Value
0x8
32
read-write
0
0xFFFFFFFF
RET
Return Value
0
32
read-write
ID
Identification
0xFC
32
read-only
0x2A0000
0xFFFFFFFF
ID
Identification Value
0
32
read-only
GPIO0
GPIO
RGPIO
RGPIO
0x40102000
0
0x124
registers
GPIO0
71
VERID
Version ID
0
32
read-only
0x2010000
0xFFFFFFFF
FEATURE
Feature Specification Number
0
16
read-only
feature0
Basic implementation
0
feature1
Protection registers implemented
0x1
MINOR
Minor Version Number
16
8
read-only
MAJOR
Major Version Number
24
8
read-only
PARAM
Parameter
0x4
32
read-only
0x1
0xFFFFFFFF
IRQNUM
Interrupt Number
0
4
read-only
PDOR
Port Data Output
0x40
32
read-write
0
0xFFFFFFFF
PDO0
Port Data Output
0
1
read-write
pdo0
Logic level 0
0
pdo1
Logic level 1
0x1
PDO1
Port Data Output
1
1
read-write
pdo0
Logic level 0
0
pdo1
Logic level 1
0x1
PDO2
Port Data Output
2
1
read-write
pdo0
Logic level 0
0
pdo1
Logic level 1
0x1
PDO3
Port Data Output
3
1
read-write
pdo0
Logic level 0
0
pdo1
Logic level 1
0x1
PDO4
Port Data Output
4
1
read-write
pdo0
Logic level 0
0
pdo1
Logic level 1
0x1
PDO5
Port Data Output
5
1
read-write
pdo0
Logic level 0
0
pdo1
Logic level 1
0x1
PDO6
Port Data Output
6
1
read-write
pdo0
Logic level 0
0
pdo1
Logic level 1
0x1
PDO7
Port Data Output
7
1
read-write
pdo0
Logic level 0
0
pdo1
Logic level 1
0x1
PDO8
Port Data Output
8
1
read-write
pdo0
Logic level 0
0
pdo1
Logic level 1
0x1
PDO9
Port Data Output
9
1
read-write
pdo0
Logic level 0
0
pdo1
Logic level 1
0x1
PDO10
Port Data Output
10
1
read-write
pdo0
Logic level 0
0
pdo1
Logic level 1
0x1
PDO11
Port Data Output
11
1
read-write
pdo0
Logic level 0
0
pdo1
Logic level 1
0x1
PDO12
Port Data Output
12
1
read-write
pdo0
Logic level 0
0
pdo1
Logic level 1
0x1
PDO13
Port Data Output
13
1
read-write
pdo0
Logic level 0
0
pdo1
Logic level 1
0x1
PDO14
Port Data Output
14
1
read-write
pdo0
Logic level 0
0
pdo1
Logic level 1
0x1
PDO15
Port Data Output
15
1
read-write
pdo0
Logic level 0
0
pdo1
Logic level 1
0x1
PDO16
Port Data Output
16
1
read-write
pdo0
Logic level 0
0
pdo1
Logic level 1
0x1
PDO17
Port Data Output
17
1
read-write
pdo0
Logic level 0
0
pdo1
Logic level 1
0x1
PDO18
Port Data Output
18
1
read-write
pdo0
Logic level 0
0
pdo1
Logic level 1
0x1
PDO19
Port Data Output
19
1
read-write
pdo0
Logic level 0
0
pdo1
Logic level 1
0x1
PDO20
Port Data Output
20
1
read-write
pdo0
Logic level 0
0
pdo1
Logic level 1
0x1
PDO21
Port Data Output
21
1
read-write
pdo0
Logic level 0
0
pdo1
Logic level 1
0x1
PDO22
Port Data Output
22
1
read-write
pdo0
Logic level 0
0
pdo1
Logic level 1
0x1
PDO23
Port Data Output
23
1
read-write
pdo0
Logic level 0
0
pdo1
Logic level 1
0x1
PDO24
Port Data Output
24
1
read-write
pdo0
Logic level 0
0
pdo1
Logic level 1
0x1
PDO25
Port Data Output
25
1
read-write
pdo0
Logic level 0
0
pdo1
Logic level 1
0x1
PDO26
Port Data Output
26
1
read-write
pdo0
Logic level 0
0
pdo1
Logic level 1
0x1
PDO27
Port Data Output
27
1
read-write
pdo0
Logic level 0
0
pdo1
Logic level 1
0x1
PDO28
Port Data Output
28
1
read-write
pdo0
Logic level 0
0
pdo1
Logic level 1
0x1
PDO29
Port Data Output
29
1
read-write
pdo0
Logic level 0
0
pdo1
Logic level 1
0x1
PDO30
Port Data Output
30
1
read-write
pdo0
Logic level 0
0
pdo1
Logic level 1
0x1
PDO31
Port Data Output
31
1
read-write
pdo0
Logic level 0
0
pdo1
Logic level 1
0x1
PSOR
Port Set Output
0x44
32
read-write
0
0xFFFFFFFF
PTSO0
Port Set Output
0
1
read-write
ptso0
No change
0
ptso1
Corresponding field in PDOR becomes 1
0x1
PTSO1
Port Set Output
1
1
read-write
ptso0
No change
0
ptso1
Corresponding field in PDOR becomes 1
0x1
PTSO2
Port Set Output
2
1
read-write
ptso0
No change
0
ptso1
Corresponding field in PDOR becomes 1
0x1
PTSO3
Port Set Output
3
1
read-write
ptso0
No change
0
ptso1
Corresponding field in PDOR becomes 1
0x1
PTSO4
Port Set Output
4
1
read-write
ptso0
No change
0
ptso1
Corresponding field in PDOR becomes 1
0x1
PTSO5
Port Set Output
5
1
read-write
ptso0
No change
0
ptso1
Corresponding field in PDOR becomes 1
0x1
PTSO6
Port Set Output
6
1
read-write
ptso0
No change
0
ptso1
Corresponding field in PDOR becomes 1
0x1
PTSO7
Port Set Output
7
1
read-write
ptso0
No change
0
ptso1
Corresponding field in PDOR becomes 1
0x1
PTSO8
Port Set Output
8
1
read-write
ptso0
No change
0
ptso1
Corresponding field in PDOR becomes 1
0x1
PTSO9
Port Set Output
9
1
read-write
ptso0
No change
0
ptso1
Corresponding field in PDOR becomes 1
0x1
PTSO10
Port Set Output
10
1
read-write
ptso0
No change
0
ptso1
Corresponding field in PDOR becomes 1
0x1
PTSO11
Port Set Output
11
1
read-write
ptso0
No change
0
ptso1
Corresponding field in PDOR becomes 1
0x1
PTSO12
Port Set Output
12
1
read-write
ptso0
No change
0
ptso1
Corresponding field in PDOR becomes 1
0x1
PTSO13
Port Set Output
13
1
read-write
ptso0
No change
0
ptso1
Corresponding field in PDOR becomes 1
0x1
PTSO14
Port Set Output
14
1
read-write
ptso0
No change
0
ptso1
Corresponding field in PDOR becomes 1
0x1
PTSO15
Port Set Output
15
1
read-write
ptso0
No change
0
ptso1
Corresponding field in PDOR becomes 1
0x1
PTSO16
Port Set Output
16
1
read-write
ptso0
No change
0
ptso1
Corresponding field in PDOR becomes 1
0x1
PTSO17
Port Set Output
17
1
read-write
ptso0
No change
0
ptso1
Corresponding field in PDOR becomes 1
0x1
PTSO18
Port Set Output
18
1
read-write
ptso0
No change
0
ptso1
Corresponding field in PDOR becomes 1
0x1
PTSO19
Port Set Output
19
1
read-write
ptso0
No change
0
ptso1
Corresponding field in PDOR becomes 1
0x1
PTSO20
Port Set Output
20
1
read-write
ptso0
No change
0
ptso1
Corresponding field in PDOR becomes 1
0x1
PTSO21
Port Set Output
21
1
read-write
ptso0
No change
0
ptso1
Corresponding field in PDOR becomes 1
0x1
PTSO22
Port Set Output
22
1
read-write
ptso0
No change
0
ptso1
Corresponding field in PDOR becomes 1
0x1
PTSO23
Port Set Output
23
1
read-write
ptso0
No change
0
ptso1
Corresponding field in PDOR becomes 1
0x1
PTSO24
Port Set Output
24
1
read-write
ptso0
No change
0
ptso1
Corresponding field in PDOR becomes 1
0x1
PTSO25
Port Set Output
25
1
read-write
ptso0
No change
0
ptso1
Corresponding field in PDOR becomes 1
0x1
PTSO26
Port Set Output
26
1
read-write
ptso0
No change
0
ptso1
Corresponding field in PDOR becomes 1
0x1
PTSO27
Port Set Output
27
1
read-write
ptso0
No change
0
ptso1
Corresponding field in PDOR becomes 1
0x1
PTSO28
Port Set Output
28
1
read-write
ptso0
No change
0
ptso1
Corresponding field in PDOR becomes 1
0x1
PTSO29
Port Set Output
29
1
read-write
ptso0
No change
0
ptso1
Corresponding field in PDOR becomes 1
0x1
PTSO30
Port Set Output
30
1
read-write
ptso0
No change
0
ptso1
Corresponding field in PDOR becomes 1
0x1
PTSO31
Port Set Output
31
1
read-write
ptso0
No change
0
ptso1
Corresponding field in PDOR becomes 1
0x1
PCOR
Port Clear Output
0x48
32
read-write
0
0xFFFFFFFF
PTCO0
Port Clear Output
0
1
read-write
ptco0
No change
0
ptco1
Corresponding field in PDOR becomes 0
0x1
PTCO1
Port Clear Output
1
1
read-write
ptco0
No change
0
ptco1
Corresponding field in PDOR becomes 0
0x1
PTCO2
Port Clear Output
2
1
read-write
ptco0
No change
0
ptco1
Corresponding field in PDOR becomes 0
0x1
PTCO3
Port Clear Output
3
1
read-write
ptco0
No change
0
ptco1
Corresponding field in PDOR becomes 0
0x1
PTCO4
Port Clear Output
4
1
read-write
ptco0
No change
0
ptco1
Corresponding field in PDOR becomes 0
0x1
PTCO5
Port Clear Output
5
1
read-write
ptco0
No change
0
ptco1
Corresponding field in PDOR becomes 0
0x1
PTCO6
Port Clear Output
6
1
read-write
ptco0
No change
0
ptco1
Corresponding field in PDOR becomes 0
0x1
PTCO7
Port Clear Output
7
1
read-write
ptco0
No change
0
ptco1
Corresponding field in PDOR becomes 0
0x1
PTCO8
Port Clear Output
8
1
read-write
ptco0
No change
0
ptco1
Corresponding field in PDOR becomes 0
0x1
PTCO9
Port Clear Output
9
1
read-write
ptco0
No change
0
ptco1
Corresponding field in PDOR becomes 0
0x1
PTCO10
Port Clear Output
10
1
read-write
ptco0
No change
0
ptco1
Corresponding field in PDOR becomes 0
0x1
PTCO11
Port Clear Output
11
1
read-write
ptco0
No change
0
ptco1
Corresponding field in PDOR becomes 0
0x1
PTCO12
Port Clear Output
12
1
read-write
ptco0
No change
0
ptco1
Corresponding field in PDOR becomes 0
0x1
PTCO13
Port Clear Output
13
1
read-write
ptco0
No change
0
ptco1
Corresponding field in PDOR becomes 0
0x1
PTCO14
Port Clear Output
14
1
read-write
ptco0
No change
0
ptco1
Corresponding field in PDOR becomes 0
0x1
PTCO15
Port Clear Output
15
1
read-write
ptco0
No change
0
ptco1
Corresponding field in PDOR becomes 0
0x1
PTCO16
Port Clear Output
16
1
read-write
ptco0
No change
0
ptco1
Corresponding field in PDOR becomes 0
0x1
PTCO17
Port Clear Output
17
1
read-write
ptco0
No change
0
ptco1
Corresponding field in PDOR becomes 0
0x1
PTCO18
Port Clear Output
18
1
read-write
ptco0
No change
0
ptco1
Corresponding field in PDOR becomes 0
0x1
PTCO19
Port Clear Output
19
1
read-write
ptco0
No change
0
ptco1
Corresponding field in PDOR becomes 0
0x1
PTCO20
Port Clear Output
20
1
read-write
ptco0
No change
0
ptco1
Corresponding field in PDOR becomes 0
0x1
PTCO21
Port Clear Output
21
1
read-write
ptco0
No change
0
ptco1
Corresponding field in PDOR becomes 0
0x1
PTCO22
Port Clear Output
22
1
read-write
ptco0
No change
0
ptco1
Corresponding field in PDOR becomes 0
0x1
PTCO23
Port Clear Output
23
1
read-write
ptco0
No change
0
ptco1
Corresponding field in PDOR becomes 0
0x1
PTCO24
Port Clear Output
24
1
read-write
ptco0
No change
0
ptco1
Corresponding field in PDOR becomes 0
0x1
PTCO25
Port Clear Output
25
1
read-write
ptco0
No change
0
ptco1
Corresponding field in PDOR becomes 0
0x1
PTCO26
Port Clear Output
26
1
read-write
ptco0
No change
0
ptco1
Corresponding field in PDOR becomes 0
0x1
PTCO27
Port Clear Output
27
1
read-write
ptco0
No change
0
ptco1
Corresponding field in PDOR becomes 0
0x1
PTCO28
Port Clear Output
28
1
read-write
ptco0
No change
0
ptco1
Corresponding field in PDOR becomes 0
0x1
PTCO29
Port Clear Output
29
1
read-write
ptco0
No change
0
ptco1
Corresponding field in PDOR becomes 0
0x1
PTCO30
Port Clear Output
30
1
read-write
ptco0
No change
0
ptco1
Corresponding field in PDOR becomes 0
0x1
PTCO31
Port Clear Output
31
1
read-write
ptco0
No change
0
ptco1
Corresponding field in PDOR becomes 0
0x1
PTOR
Port Toggle Output
0x4C
32
read-write
0
0xFFFFFFFF
PTTO0
Port Toggle Output
0
1
read-write
ptto0
No change
0
ptto1
Set to the inverse of its current logic state
0x1
PTTO1
Port Toggle Output
1
1
read-write
ptto0
No change
0
ptto1
Set to the inverse of its current logic state
0x1
PTTO2
Port Toggle Output
2
1
read-write
ptto0
No change
0
ptto1
Set to the inverse of its current logic state
0x1
PTTO3
Port Toggle Output
3
1
read-write
ptto0
No change
0
ptto1
Set to the inverse of its current logic state
0x1
PTTO4
Port Toggle Output
4
1
read-write
ptto0
No change
0
ptto1
Set to the inverse of its current logic state
0x1
PTTO5
Port Toggle Output
5
1
read-write
ptto0
No change
0
ptto1
Set to the inverse of its current logic state
0x1
PTTO6
Port Toggle Output
6
1
read-write
ptto0
No change
0
ptto1
Set to the inverse of its current logic state
0x1
PTTO7
Port Toggle Output
7
1
read-write
ptto0
No change
0
ptto1
Set to the inverse of its current logic state
0x1
PTTO8
Port Toggle Output
8
1
read-write
ptto0
No change
0
ptto1
Set to the inverse of its current logic state
0x1
PTTO9
Port Toggle Output
9
1
read-write
ptto0
No change
0
ptto1
Set to the inverse of its current logic state
0x1
PTTO10
Port Toggle Output
10
1
read-write
ptto0
No change
0
ptto1
Set to the inverse of its current logic state
0x1
PTTO11
Port Toggle Output
11
1
read-write
ptto0
No change
0
ptto1
Set to the inverse of its current logic state
0x1
PTTO12
Port Toggle Output
12
1
read-write
ptto0
No change
0
ptto1
Set to the inverse of its current logic state
0x1
PTTO13
Port Toggle Output
13
1
read-write
ptto0
No change
0
ptto1
Set to the inverse of its current logic state
0x1
PTTO14
Port Toggle Output
14
1
read-write
ptto0
No change
0
ptto1
Set to the inverse of its current logic state
0x1
PTTO15
Port Toggle Output
15
1
read-write
ptto0
No change
0
ptto1
Set to the inverse of its current logic state
0x1
PTTO16
Port Toggle Output
16
1
read-write
ptto0
No change
0
ptto1
Set to the inverse of its current logic state
0x1
PTTO17
Port Toggle Output
17
1
read-write
ptto0
No change
0
ptto1
Set to the inverse of its current logic state
0x1
PTTO18
Port Toggle Output
18
1
read-write
ptto0
No change
0
ptto1
Set to the inverse of its current logic state
0x1
PTTO19
Port Toggle Output
19
1
read-write
ptto0
No change
0
ptto1
Set to the inverse of its current logic state
0x1
PTTO20
Port Toggle Output
20
1
read-write
ptto0
No change
0
ptto1
Set to the inverse of its current logic state
0x1
PTTO21
Port Toggle Output
21
1
read-write
ptto0
No change
0
ptto1
Set to the inverse of its current logic state
0x1
PTTO22
Port Toggle Output
22
1
read-write
ptto0
No change
0
ptto1
Set to the inverse of its current logic state
0x1
PTTO23
Port Toggle Output
23
1
read-write
ptto0
No change
0
ptto1
Set to the inverse of its current logic state
0x1
PTTO24
Port Toggle Output
24
1
read-write
ptto0
No change
0
ptto1
Set to the inverse of its current logic state
0x1
PTTO25
Port Toggle Output
25
1
read-write
ptto0
No change
0
ptto1
Set to the inverse of its current logic state
0x1
PTTO26
Port Toggle Output
26
1
read-write
ptto0
No change
0
ptto1
Set to the inverse of its current logic state
0x1
PTTO27
Port Toggle Output
27
1
read-write
ptto0
No change
0
ptto1
Set to the inverse of its current logic state
0x1
PTTO28
Port Toggle Output
28
1
read-write
ptto0
No change
0
ptto1
Set to the inverse of its current logic state
0x1
PTTO29
Port Toggle Output
29
1
read-write
ptto0
No change
0
ptto1
Set to the inverse of its current logic state
0x1
PTTO30
Port Toggle Output
30
1
read-write
ptto0
No change
0
ptto1
Set to the inverse of its current logic state
0x1
PTTO31
Port Toggle Output
31
1
read-write
ptto0
No change
0
ptto1
Set to the inverse of its current logic state
0x1
PDIR
Port Data Input
0x50
32
read-only
0
0xFFFFFFFF
PDI0
Port Data Input
0
1
read-only
pdi0
Logic 0
0
pdi1
Logic 1
0x1
PDI1
Port Data Input
1
1
read-only
pdi0
Logic 0
0
pdi1
Logic 1
0x1
PDI2
Port Data Input
2
1
read-only
pdi0
Logic 0
0
pdi1
Logic 1
0x1
PDI3
Port Data Input
3
1
read-only
pdi0
Logic 0
0
pdi1
Logic 1
0x1
PDI4
Port Data Input
4
1
read-only
pdi0
Logic 0
0
pdi1
Logic 1
0x1
PDI5
Port Data Input
5
1
read-only
pdi0
Logic 0
0
pdi1
Logic 1
0x1
PDI6
Port Data Input
6
1
read-only
pdi0
Logic 0
0
pdi1
Logic 1
0x1
PDI7
Port Data Input
7
1
read-only
pdi0
Logic 0
0
pdi1
Logic 1
0x1
PDI8
Port Data Input
8
1
read-only
pdi0
Logic 0
0
pdi1
Logic 1
0x1
PDI9
Port Data Input
9
1
read-only
pdi0
Logic 0
0
pdi1
Logic 1
0x1
PDI10
Port Data Input
10
1
read-only
pdi0
Logic 0
0
pdi1
Logic 1
0x1
PDI11
Port Data Input
11
1
read-only
pdi0
Logic 0
0
pdi1
Logic 1
0x1
PDI12
Port Data Input
12
1
read-only
pdi0
Logic 0
0
pdi1
Logic 1
0x1
PDI13
Port Data Input
13
1
read-only
pdi0
Logic 0
0
pdi1
Logic 1
0x1
PDI14
Port Data Input
14
1
read-only
pdi0
Logic 0
0
pdi1
Logic 1
0x1
PDI15
Port Data Input
15
1
read-only
pdi0
Logic 0
0
pdi1
Logic 1
0x1
PDI16
Port Data Input
16
1
read-only
pdi0
Logic 0
0
pdi1
Logic 1
0x1
PDI17
Port Data Input
17
1
read-only
pdi0
Logic 0
0
pdi1
Logic 1
0x1
PDI18
Port Data Input
18
1
read-only
pdi0
Logic 0
0
pdi1
Logic 1
0x1
PDI19
Port Data Input
19
1
read-only
pdi0
Logic 0
0
pdi1
Logic 1
0x1
PDI20
Port Data Input
20
1
read-only
pdi0
Logic 0
0
pdi1
Logic 1
0x1
PDI21
Port Data Input
21
1
read-only
pdi0
Logic 0
0
pdi1
Logic 1
0x1
PDI22
Port Data Input
22
1
read-only
pdi0
Logic 0
0
pdi1
Logic 1
0x1
PDI23
Port Data Input
23
1
read-only
pdi0
Logic 0
0
pdi1
Logic 1
0x1
PDI24
Port Data Input
24
1
read-only
pdi0
Logic 0
0
pdi1
Logic 1
0x1
PDI25
Port Data Input
25
1
read-only
pdi0
Logic 0
0
pdi1
Logic 1
0x1
PDI26
Port Data Input
26
1
read-only
pdi0
Logic 0
0
pdi1
Logic 1
0x1
PDI27
Port Data Input
27
1
read-only
pdi0
Logic 0
0
pdi1
Logic 1
0x1
PDI28
Port Data Input
28
1
read-only
pdi0
Logic 0
0
pdi1
Logic 1
0x1
PDI29
Port Data Input
29
1
read-only
pdi0
Logic 0
0
pdi1
Logic 1
0x1
PDI30
Port Data Input
30
1
read-only
pdi0
Logic 0
0
pdi1
Logic 1
0x1
PDI31
Port Data Input
31
1
read-only
pdi0
Logic 0
0
pdi1
Logic 1
0x1
PDDR
Port Data Direction
0x54
32
read-write
0
0xFFFFFFFF
PDD0
Port Data Direction
0
1
read-write
pdd0
Input
0
pdd1
Output
0x1
PDD1
Port Data Direction
1
1
read-write
pdd0
Input
0
pdd1
Output
0x1
PDD2
Port Data Direction
2
1
read-write
pdd0
Input
0
pdd1
Output
0x1
PDD3
Port Data Direction
3
1
read-write
pdd0
Input
0
pdd1
Output
0x1
PDD4
Port Data Direction
4
1
read-write
pdd0
Input
0
pdd1
Output
0x1
PDD5
Port Data Direction
5
1
read-write
pdd0
Input
0
pdd1
Output
0x1
PDD6
Port Data Direction
6
1
read-write
pdd0
Input
0
pdd1
Output
0x1
PDD7
Port Data Direction
7
1
read-write
pdd0
Input
0
pdd1
Output
0x1
PDD8
Port Data Direction
8
1
read-write
pdd0
Input
0
pdd1
Output
0x1
PDD9
Port Data Direction
9
1
read-write
pdd0
Input
0
pdd1
Output
0x1
PDD10
Port Data Direction
10
1
read-write
pdd0
Input
0
pdd1
Output
0x1
PDD11
Port Data Direction
11
1
read-write
pdd0
Input
0
pdd1
Output
0x1
PDD12
Port Data Direction
12
1
read-write
pdd0
Input
0
pdd1
Output
0x1
PDD13
Port Data Direction
13
1
read-write
pdd0
Input
0
pdd1
Output
0x1
PDD14
Port Data Direction
14
1
read-write
pdd0
Input
0
pdd1
Output
0x1
PDD15
Port Data Direction
15
1
read-write
pdd0
Input
0
pdd1
Output
0x1
PDD16
Port Data Direction
16
1
read-write
pdd0
Input
0
pdd1
Output
0x1
PDD17
Port Data Direction
17
1
read-write
pdd0
Input
0
pdd1
Output
0x1
PDD18
Port Data Direction
18
1
read-write
pdd0
Input
0
pdd1
Output
0x1
PDD19
Port Data Direction
19
1
read-write
pdd0
Input
0
pdd1
Output
0x1
PDD20
Port Data Direction
20
1
read-write
pdd0
Input
0
pdd1
Output
0x1
PDD21
Port Data Direction
21
1
read-write
pdd0
Input
0
pdd1
Output
0x1
PDD22
Port Data Direction
22
1
read-write
pdd0
Input
0
pdd1
Output
0x1
PDD23
Port Data Direction
23
1
read-write
pdd0
Input
0
pdd1
Output
0x1
PDD24
Port Data Direction
24
1
read-write
pdd0
Input
0
pdd1
Output
0x1
PDD25
Port Data Direction
25
1
read-write
pdd0
Input
0
pdd1
Output
0x1
PDD26
Port Data Direction
26
1
read-write
pdd0
Input
0
pdd1
Output
0x1
PDD27
Port Data Direction
27
1
read-write
pdd0
Input
0
pdd1
Output
0x1
PDD28
Port Data Direction
28
1
read-write
pdd0
Input
0
pdd1
Output
0x1
PDD29
Port Data Direction
29
1
read-write
pdd0
Input
0
pdd1
Output
0x1
PDD30
Port Data Direction
30
1
read-write
pdd0
Input
0
pdd1
Output
0x1
PDD31
Port Data Direction
31
1
read-write
pdd0
Input
0
pdd1
Output
0x1
PIDR
Port Input Disable
0x58
32
read-write
0
0xFFFFFFFF
PID0
Port Input Disable
0
1
read-write
pid0
Configured for general-purpose input
0
pid1
Disabled for general-purpose input
0x1
PID1
Port Input Disable
1
1
read-write
pid0
Configured for general-purpose input
0
pid1
Disabled for general-purpose input
0x1
PID2
Port Input Disable
2
1
read-write
pid0
Configured for general-purpose input
0
pid1
Disabled for general-purpose input
0x1
PID3
Port Input Disable
3
1
read-write
pid0
Configured for general-purpose input
0
pid1
Disabled for general-purpose input
0x1
PID4
Port Input Disable
4
1
read-write
pid0
Configured for general-purpose input
0
pid1
Disabled for general-purpose input
0x1
PID5
Port Input Disable
5
1
read-write
pid0
Configured for general-purpose input
0
pid1
Disabled for general-purpose input
0x1
PID6
Port Input Disable
6
1
read-write
pid0
Configured for general-purpose input
0
pid1
Disabled for general-purpose input
0x1
PID7
Port Input Disable
7
1
read-write
pid0
Configured for general-purpose input
0
pid1
Disabled for general-purpose input
0x1
PID8
Port Input Disable
8
1
read-write
pid0
Configured for general-purpose input
0
pid1
Disabled for general-purpose input
0x1
PID9
Port Input Disable
9
1
read-write
pid0
Configured for general-purpose input
0
pid1
Disabled for general-purpose input
0x1
PID10
Port Input Disable
10
1
read-write
pid0
Configured for general-purpose input
0
pid1
Disabled for general-purpose input
0x1
PID11
Port Input Disable
11
1
read-write
pid0
Configured for general-purpose input
0
pid1
Disabled for general-purpose input
0x1
PID12
Port Input Disable
12
1
read-write
pid0
Configured for general-purpose input
0
pid1
Disabled for general-purpose input
0x1
PID13
Port Input Disable
13
1
read-write
pid0
Configured for general-purpose input
0
pid1
Disabled for general-purpose input
0x1
PID14
Port Input Disable
14
1
read-write
pid0
Configured for general-purpose input
0
pid1
Disabled for general-purpose input
0x1
PID15
Port Input Disable
15
1
read-write
pid0
Configured for general-purpose input
0
pid1
Disabled for general-purpose input
0x1
PID16
Port Input Disable
16
1
read-write
pid0
Configured for general-purpose input
0
pid1
Disabled for general-purpose input
0x1
PID17
Port Input Disable
17
1
read-write
pid0
Configured for general-purpose input
0
pid1
Disabled for general-purpose input
0x1
PID18
Port Input Disable
18
1
read-write
pid0
Configured for general-purpose input
0
pid1
Disabled for general-purpose input
0x1
PID19
Port Input Disable
19
1
read-write
pid0
Configured for general-purpose input
0
pid1
Disabled for general-purpose input
0x1
PID20
Port Input Disable
20
1
read-write
pid0
Configured for general-purpose input
0
pid1
Disabled for general-purpose input
0x1
PID21
Port Input Disable
21
1
read-write
pid0
Configured for general-purpose input
0
pid1
Disabled for general-purpose input
0x1
PID22
Port Input Disable
22
1
read-write
pid0
Configured for general-purpose input
0
pid1
Disabled for general-purpose input
0x1
PID23
Port Input Disable
23
1
read-write
pid0
Configured for general-purpose input
0
pid1
Disabled for general-purpose input
0x1
PID24
Port Input Disable
24
1
read-write
pid0
Configured for general-purpose input
0
pid1
Disabled for general-purpose input
0x1
PID25
Port Input Disable
25
1
read-write
pid0
Configured for general-purpose input
0
pid1
Disabled for general-purpose input
0x1
PID26
Port Input Disable
26
1
read-write
pid0
Configured for general-purpose input
0
pid1
Disabled for general-purpose input
0x1
PID27
Port Input Disable
27
1
read-write
pid0
Configured for general-purpose input
0
pid1
Disabled for general-purpose input
0x1
PID28
Port Input Disable
28
1
read-write
pid0
Configured for general-purpose input
0
pid1
Disabled for general-purpose input
0x1
PID29
Port Input Disable
29
1
read-write
pid0
Configured for general-purpose input
0
pid1
Disabled for general-purpose input
0x1
PID30
Port Input Disable
30
1
read-write
pid0
Configured for general-purpose input
0
pid1
Disabled for general-purpose input
0x1
PID31
Port Input Disable
31
1
read-write
pid0
Configured for general-purpose input
0
pid1
Disabled for general-purpose input
0x1
32
0x1
PDR[%s]
Pin Data
0x60
8
read-write
0
0xFF
PD
Pin Data (I/O)
0
1
read-write
pd0
Logic zero
0
pd1
Logic one
0x1
32
0x4
ICR[%s]
Interrupt Control index
0x80
32
read-write
0
0xFFFFFFFF
IRQC
Interrupt Configuration
16
4
read-write
irqc0
ISF is disabled
0
irqc1
ISF and DMA request on rising edge
0x1
irqc2
ISF and DMA request on falling edge
0x2
irqc3
ISF and DMA request on either edge
0x3
irqc5
ISF sets on rising edge
0x5
irqc6
ISF sets on falling edge
0x6
irqc7
ISF sets on either edge
0x7
irqc8
ISF and interrupt when logic 0
0x8
irqc9
ISF and interrupt on rising edge
0x9
irqc10
ISF and interrupt on falling edge
0xA
irqc11
ISF and Interrupt on either edge
0xB
irqc12
ISF and interrupt when logic 1
0xC
irqc13
Enable active-high trigger output; ISF on rising edge (pin state is ORed with other enabled triggers to generate the output trigger for use by other peripherals)
0xD
irqc14
Enable active-low trigger output; ISF on falling edge (pin state is inverted and ORed with other enabled triggers to generate the output trigger for use by other peripherals)
0xE
ISF
Interrupt Status Flag
24
1
read-write
oneToClear
read
isf0
Not detected
0
isf1
Detected
0x1
GICLR
Global Interrupt Control Low
0x100
32
read-write
0
0xFFFFFFFF
GIWE0
Global Interrupt Write Enable
0
1
read-write
giwe0
Not updated
0
giwe1
Updated
0x1
GIWE1
Global Interrupt Write Enable
1
1
read-write
giwe0
Not updated
0
giwe1
Updated
0x1
GIWE2
Global Interrupt Write Enable
2
1
read-write
giwe0
Not updated
0
giwe1
Updated
0x1
GIWE3
Global Interrupt Write Enable
3
1
read-write
giwe0
Not updated
0
giwe1
Updated
0x1
GIWE4
Global Interrupt Write Enable
4
1
read-write
giwe0
Not updated
0
giwe1
Updated
0x1
GIWE5
Global Interrupt Write Enable
5
1
read-write
giwe0
Not updated
0
giwe1
Updated
0x1
GIWE6
Global Interrupt Write Enable
6
1
read-write
giwe0
Not updated
0
giwe1
Updated
0x1
GIWE7
Global Interrupt Write Enable
7
1
read-write
giwe0
Not updated
0
giwe1
Updated
0x1
GIWE8
Global Interrupt Write Enable
8
1
read-write
giwe0
Not updated
0
giwe1
Updated
0x1
GIWE9
Global Interrupt Write Enable
9
1
read-write
giwe0
Not updated
0
giwe1
Updated
0x1
GIWE10
Global Interrupt Write Enable
10
1
read-write
giwe0
Not updated
0
giwe1
Updated
0x1
GIWE11
Global Interrupt Write Enable
11
1
read-write
giwe0
Not updated
0
giwe1
Updated
0x1
GIWE12
Global Interrupt Write Enable
12
1
read-write
giwe0
Not updated
0
giwe1
Updated
0x1
GIWE13
Global Interrupt Write Enable
13
1
read-write
giwe0
Not updated
0
giwe1
Updated
0x1
GIWE14
Global Interrupt Write Enable
14
1
read-write
giwe0
Not updated
0
giwe1
Updated
0x1
GIWE15
Global Interrupt Write Enable
15
1
read-write
giwe0
Not updated
0
giwe1
Updated
0x1
GIWD
Global Interrupt Write Data
16
16
read-write
GICHR
Global Interrupt Control High
0x104
32
read-write
0
0xFFFFFFFF
GIWE16
Global Interrupt Write Enable
0
1
read-write
giwe0
Not updated.
0
giwe1
Updated
0x1
GIWE17
Global Interrupt Write Enable
1
1
read-write
giwe0
Not updated.
0
giwe1
Updated
0x1
GIWE18
Global Interrupt Write Enable
2
1
read-write
giwe0
Not updated.
0
giwe1
Updated
0x1
GIWE19
Global Interrupt Write Enable
3
1
read-write
giwe0
Not updated.
0
giwe1
Updated
0x1
GIWE20
Global Interrupt Write Enable
4
1
read-write
giwe0
Not updated.
0
giwe1
Updated
0x1
GIWE21
Global Interrupt Write Enable
5
1
read-write
giwe0
Not updated.
0
giwe1
Updated
0x1
GIWE22
Global Interrupt Write Enable
6
1
read-write
giwe0
Not updated.
0
giwe1
Updated
0x1
GIWE23
Global Interrupt Write Enable
7
1
read-write
giwe0
Not updated.
0
giwe1
Updated
0x1
GIWE24
Global Interrupt Write Enable
8
1
read-write
giwe0
Not updated.
0
giwe1
Updated
0x1
GIWE25
Global Interrupt Write Enable
9
1
read-write
giwe0
Not updated.
0
giwe1
Updated
0x1
GIWE26
Global Interrupt Write Enable
10
1
read-write
giwe0
Not updated.
0
giwe1
Updated
0x1
GIWE27
Global Interrupt Write Enable
11
1
read-write
giwe0
Not updated.
0
giwe1
Updated
0x1
GIWE28
Global Interrupt Write Enable
12
1
read-write
giwe0
Not updated.
0
giwe1
Updated
0x1
GIWE29
Global Interrupt Write Enable
13
1
read-write
giwe0
Not updated.
0
giwe1
Updated
0x1
GIWE30
Global Interrupt Write Enable
14
1
read-write
giwe0
Not updated.
0
giwe1
Updated
0x1
GIWE31
Global Interrupt Write Enable
15
1
read-write
giwe0
Not updated.
0
giwe1
Updated
0x1
GIWD
Global Interrupt Write Data
16
16
read-write
ISFR0
Interrupt Status Flag
0x120
32
read-write
0
0xFFFFFFFF
oneToClear
ISF0
Interrupt Status Flag
0
1
read-write
oneToClear
read
isf0
Not detected
0
isf1
Detected
0x1
ISF1
Interrupt Status Flag
1
1
read-write
oneToClear
read
isf0
Not detected
0
isf1
Detected
0x1
ISF2
Interrupt Status Flag
2
1
read-write
oneToClear
read
isf0
Not detected
0
isf1
Detected
0x1
ISF3
Interrupt Status Flag
3
1
read-write
oneToClear
read
isf0
Not detected
0
isf1
Detected
0x1
ISF4
Interrupt Status Flag
4
1
read-write
oneToClear
read
isf0
Not detected
0
isf1
Detected
0x1
ISF5
Interrupt Status Flag
5
1
read-write
oneToClear
read
isf0
Not detected
0
isf1
Detected
0x1
ISF6
Interrupt Status Flag
6
1
read-write
oneToClear
read
isf0
Not detected
0
isf1
Detected
0x1
ISF7
Interrupt Status Flag
7
1
read-write
oneToClear
read
isf0
Not detected
0
isf1
Detected
0x1
ISF8
Interrupt Status Flag
8
1
read-write
oneToClear
read
isf0
Not detected
0
isf1
Detected
0x1
ISF9
Interrupt Status Flag
9
1
read-write
oneToClear
read
isf0
Not detected
0
isf1
Detected
0x1
ISF10
Interrupt Status Flag
10
1
read-write
oneToClear
read
isf0
Not detected
0
isf1
Detected
0x1
ISF11
Interrupt Status Flag
11
1
read-write
oneToClear
read
isf0
Not detected
0
isf1
Detected
0x1
ISF12
Interrupt Status Flag
12
1
read-write
oneToClear
read
isf0
Not detected
0
isf1
Detected
0x1
ISF13
Interrupt Status Flag
13
1
read-write
oneToClear
read
isf0
Not detected
0
isf1
Detected
0x1
ISF14
Interrupt Status Flag
14
1
read-write
oneToClear
read
isf0
Not detected
0
isf1
Detected
0x1
ISF15
Interrupt Status Flag
15
1
read-write
oneToClear
read
isf0
Not detected
0
isf1
Detected
0x1
ISF16
Interrupt Status Flag
16
1
read-write
oneToClear
read
isf0
Not detected
0
isf1
Detected
0x1
ISF17
Interrupt Status Flag
17
1
read-write
oneToClear
read
isf0
Not detected
0
isf1
Detected
0x1
ISF18
Interrupt Status Flag
18
1
read-write
oneToClear
read
isf0
Not detected
0
isf1
Detected
0x1
ISF19
Interrupt Status Flag
19
1
read-write
oneToClear
read
isf0
Not detected
0
isf1
Detected
0x1
ISF20
Interrupt Status Flag
20
1
read-write
oneToClear
read
isf0
Not detected
0
isf1
Detected
0x1
ISF21
Interrupt Status Flag
21
1
read-write
oneToClear
read
isf0
Not detected
0
isf1
Detected
0x1
ISF22
Interrupt Status Flag
22
1
read-write
oneToClear
read
isf0
Not detected
0
isf1
Detected
0x1
ISF23
Interrupt Status Flag
23
1
read-write
oneToClear
read
isf0
Not detected
0
isf1
Detected
0x1
ISF24
Interrupt Status Flag
24
1
read-write
oneToClear
read
isf0
Not detected
0
isf1
Detected
0x1
ISF25
Interrupt Status Flag
25
1
read-write
oneToClear
read
isf0
Not detected
0
isf1
Detected
0x1
ISF26
Interrupt Status Flag
26
1
read-write
oneToClear
read
isf0
Not detected
0
isf1
Detected
0x1
ISF27
Interrupt Status Flag
27
1
read-write
oneToClear
read
isf0
Not detected
0
isf1
Detected
0x1
ISF28
Interrupt Status Flag
28
1
read-write
oneToClear
read
isf0
Not detected
0
isf1
Detected
0x1
ISF29
Interrupt Status Flag
29
1
read-write
oneToClear
read
isf0
Not detected
0
isf1
Detected
0x1
ISF30
Interrupt Status Flag
30
1
read-write
oneToClear
read
isf0
Not detected
0
isf1
Detected
0x1
ISF31
Interrupt Status Flag
31
1
read-write
oneToClear
read
isf0
Not detected
0
isf1
Detected
0x1
GPIO1
GPIO
RGPIO
0x40103000
0
0x124
registers
GPIO1
72
GPIO2
GPIO
RGPIO
0x40104000
0
0x124
registers
GPIO2
73
GPIO3
GPIO
RGPIO
0x40105000
0
0x124
registers
GPIO3
74
SCnSCB
no description available
SCNSCB
0xE000E000
0
0x10
registers
CPPWR
Coprocessor Power Control Register
0xC
32
read-write
0
0
SU0
State UNKNOWN 0.
0
1
read-write
UNKNOWN_NOT_PERMITTED
The coprocessor state is not permitted to become UNKNOWN.
0
UNKNOWN_PERMITTED
The coprocessor state is permitted to become UNKNOWN.
0x1
SUS0
State UNKNOWN Secure only 0.
1
1
read-write
SECURE_AND_NON_SECURE
The SU0 field is accessible from both Security states.
0
SECURE_ONLY
The SU0 field is only accessible from the Secure state.
0x1
SU1
State UNKNOWN 1.
2
1
read-write
UNKNOWN_NOT_PERMITTED
The coprocessor state is not permitted to become UNKNOWN.
0
UNKNOWN_PERMITTED
The coprocessor state is permitted to become UNKNOWN.
0x1
SUS1
State UNKNOWN Secure only 1.
3
1
read-write
SECURE_AND_NON_SECURE
The SU7 field is accessible from both Security states.
0
SECURE_ONLY
The SU7 field is only accessible from the Secure state.
0x1
SU2
State UNKNOWN 2.
4
1
read-write
UNKNOWN_NOT_PERMITTED
The coprocessor state is not permitted to become UNKNOWN.
0
UNKNOWN_PERMITTED
The coprocessor state is permitted to become UNKNOWN.
0x1
SUS2
State UNKNOWN Secure only 2.
5
1
read-write
SECURE_AND_NON_SECURE
The SU2 field is accessible from both Security states.
0
SECURE_ONLY
The SU2 field is only accessible from the Secure state.
0x1
SU3
State UNKNOWN 3.
6
1
read-write
UNKNOWN_NOT_PERMITTED
The coprocessor state is not permitted to become UNKNOWN.
0
UNKNOWN_PERMITTED
The coprocessor state is permitted to become UNKNOWN.
0x1
SUS3
State UNKNOWN Secure only 3.
7
1
read-write
SECURE_AND_NON_SECURE
The SU3 field is accessible from both Security states.
0
SECURE_ONLY
The SU3 field is only accessible from the Secure state.
0x1
SU4
State UNKNOWN 4.
8
1
read-write
UNKNOWN_NOT_PERMITTED
The coprocessor state is not permitted to become UNKNOWN.
0
UNKNOWN_PERMITTED
The coprocessor state is permitted to become UNKNOWN.
0x1
SUS4
State UNKNOWN Secure only 4.
9
1
read-write
SECURE_AND_NON_SECURE
The SU4 field is accessible from both Security states.
0
SECURE_ONLY
The SU4 field is only accessible from the Secure state.
0x1
SU5
State UNKNOWN 5.
10
1
read-write
UNKNOWN_NOT_PERMITTED
The coprocessor state is not permitted to become UNKNOWN.
0
UNKNOWN_PERMITTED
The coprocessor state is permitted to become UNKNOWN.
0x1
SUS5
State UNKNOWN Secure only 5.
11
1
read-write
SECURE_AND_NON_SECURE
The SU5 field is accessible from both Security states.
0
SECURE_ONLY
The SU5 field is only accessible from the Secure state.
0x1
SU6
State UNKNOWN 6.
12
1
read-write
UNKNOWN_NOT_PERMITTED
The coprocessor state is not permitted to become UNKNOWN.
0
UNKNOWN_PERMITTED
The coprocessor state is permitted to become UNKNOWN.
0x1
SUS6
State UNKNOWN Secure only 6.
13
1
read-write
SECURE_AND_NON_SECURE
The SU6 field is accessible from both Security states.
0
SECURE_ONLY
The SU6 field is only accessible from the Secure state.
0x1
SU7
State UNKNOWN 7.
14
1
read-write
UNKNOWN_NOT_PERMITTED
The coprocessor state is not permitted to become UNKNOWN.
0
UNKNOWN_PERMITTED
The coprocessor state is permitted to become UNKNOWN.
0x1
SUS7
State UNKNOWN Secure only 7.
15
1
read-write
SECURE_AND_NON_SECURE
The SU7 field is accessible from both Security states.
0
SECURE_ONLY
The SU7 field is only accessible from the Secure state.
0x1
SU10
State UNKNOWN 10.
20
1
read-write
UNKNOWN_NOT_PERMITTED
The floating-point state is not permitted to become UNKNOWN.
0
UNKNOWN_PERMITTED
The floating-point state is permitted to become UNKNOWN
0x1
SUS10
State UNKNOWN Secure only 10.
21
1
read-write
SECURE_AND_NON_SECURE
The SU10 field is accessible from both Security states.
0
SECURE_ONLY
The SU10 field is only accessible from the Secure state.
0x1
SU11
State UNKNOWN 11.
22
1
read-write
SUS11
State UNKNOWN Secure only 11.
23
1
read-write
SysTick
M33 Systick module
SYSTICK
0xE000E010
0
0x10
registers
SYST_CSR
SysTick Control and Status Register
0
32
read-write
0x4
0xFFFFFFFF
ENABLE
Enable/disable systick counter
0
1
read-write
COUNTER_DISABLED
counter disabled
0
COUNTER_ENABLED
counter enabled
0x1
TICKINT
Enable Systick interrupt.
1
1
read-write
INTERRUPT_DISABLED
counting down to 0 does not assert the SysTick exception request
0
INTERRUPT_ENABLED
counting down to 0 asserts the SysTick exception request
0x1
CLKSOURCE
Clock source selection.
2
1
read-write
EXTERNAL_CLOCK
external clock
0
PROCESSOR_CLOCK
processor clock
0x1
COUNTFLAG
Returns 1 if timer counted to 0 since the last read of this register.
16
1
read-write
SYST_RVR
SysTick Reload Value Register
0x4
32
read-write
0
0xFFFFFFFF
RELOAD
Value to load into the SysTick Current Value Register when the counter reaches 0
0
24
read-write
SYST_CVR
SysTick Current Value Register
0x8
32
read-write
0
0xFFFFFFFF
CURRENT
Current value at the time the register is accessed
0
24
read-write
SYST_CALIB
SysTick Calibration Value Register
0xC
32
read-only
0x80000000
0xFFFFFFFF
TENMS
Reload value to use for 10ms timing
0
24
read-only
SKEW
Indicates whether the TENMS value is exact:
30
1
read-only
EXACT_VALUE
10ms calibration value is exact
0
INEXACT_VALUE
10ms calibration value is inexact, because of the clock frequency
0x1
NOREF
Indicates whether the device provides a reference clock to the processor.
31
1
read-only
CLOCK_PROVIDED
The reference clock is provided
0
CLOCK_DISABLED
The reference clock is not provided
0x1
NVIC
no description available
NVIC
0xE000E100
0
0xE04
registers
16
0x4
ISER[%s]
Interrupt Set Enable Register
0
32
read-write
0
0xFFFFFFFF
SETENA0
Interrupt set-enable bits.
0
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
SETENA1
Interrupt set-enable bits.
1
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
SETENA2
Interrupt set-enable bits.
2
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
SETENA3
Interrupt set-enable bits.
3
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
SETENA4
Interrupt set-enable bits.
4
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
SETENA5
Interrupt set-enable bits.
5
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
SETENA6
Interrupt set-enable bits.
6
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
SETENA7
Interrupt set-enable bits.
7
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
SETENA8
Interrupt set-enable bits.
8
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
SETENA9
Interrupt set-enable bits.
9
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
SETENA10
Interrupt set-enable bits.
10
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
SETENA11
Interrupt set-enable bits.
11
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
SETENA12
Interrupt set-enable bits.
12
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
SETENA13
Interrupt set-enable bits.
13
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
SETENA14
Interrupt set-enable bits.
14
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
SETENA15
Interrupt set-enable bits.
15
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
SETENA16
Interrupt set-enable bits.
16
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
SETENA17
Interrupt set-enable bits.
17
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
SETENA18
Interrupt set-enable bits.
18
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
SETENA19
Interrupt set-enable bits.
19
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
SETENA20
Interrupt set-enable bits.
20
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
SETENA21
Interrupt set-enable bits.
21
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
SETENA22
Interrupt set-enable bits.
22
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
SETENA23
Interrupt set-enable bits.
23
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
SETENA24
Interrupt set-enable bits.
24
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
SETENA25
Interrupt set-enable bits.
25
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
SETENA26
Interrupt set-enable bits.
26
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
SETENA27
Interrupt set-enable bits.
27
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
SETENA28
Interrupt set-enable bits.
28
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
SETENA29
Interrupt set-enable bits.
29
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
SETENA30
Interrupt set-enable bits.
30
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
SETENA31
Interrupt set-enable bits.
31
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
16
0x4
ICER[%s]
Interrupt Clear Enable Register
0x80
32
read-write
0
0xFFFFFFFF
CLRENA0
Interrupt clear-enable bits.
0
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
CLRENA1
Interrupt clear-enable bits.
1
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
CLRENA2
Interrupt clear-enable bits.
2
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
CLRENA3
Interrupt clear-enable bits.
3
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
CLRENA4
Interrupt clear-enable bits.
4
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
CLRENA5
Interrupt clear-enable bits.
5
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
CLRENA6
Interrupt clear-enable bits.
6
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
CLRENA7
Interrupt clear-enable bits.
7
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
CLRENA8
Interrupt clear-enable bits.
8
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
CLRENA9
Interrupt clear-enable bits.
9
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
CLRENA10
Interrupt clear-enable bits.
10
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
CLRENA11
Interrupt clear-enable bits.
11
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
CLRENA12
Interrupt clear-enable bits.
12
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
CLRENA13
Interrupt clear-enable bits.
13
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
CLRENA14
Interrupt clear-enable bits.
14
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
CLRENA15
Interrupt clear-enable bits.
15
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
CLRENA16
Interrupt clear-enable bits.
16
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
CLRENA17
Interrupt clear-enable bits.
17
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
CLRENA18
Interrupt clear-enable bits.
18
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
CLRENA19
Interrupt clear-enable bits.
19
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
CLRENA20
Interrupt clear-enable bits.
20
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
CLRENA21
Interrupt clear-enable bits.
21
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
CLRENA22
Interrupt clear-enable bits.
22
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
CLRENA23
Interrupt clear-enable bits.
23
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
CLRENA24
Interrupt clear-enable bits.
24
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
CLRENA25
Interrupt clear-enable bits.
25
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
CLRENA26
Interrupt clear-enable bits.
26
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
CLRENA27
Interrupt clear-enable bits.
27
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
CLRENA28
Interrupt clear-enable bits.
28
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
CLRENA29
Interrupt clear-enable bits.
29
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
CLRENA30
Interrupt clear-enable bits.
30
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
CLRENA31
Interrupt clear-enable bits.
31
1
read-write
DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0
ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
0x1
16
0x4
ISPR[%s]
Interrupt Set Pending Register
0x100
32
read-write
0
0xFFFFFFFF
SETPEND0
Interrupt set-pending bits.
0
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
0x1
SETPEND1
Interrupt set-pending bits.
1
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
0x1
SETPEND2
Interrupt set-pending bits.
2
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
0x1
SETPEND3
Interrupt set-pending bits.
3
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
0x1
SETPEND4
Interrupt set-pending bits.
4
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
0x1
SETPEND5
Interrupt set-pending bits.
5
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
0x1
SETPEND6
Interrupt set-pending bits.
6
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
0x1
SETPEND7
Interrupt set-pending bits.
7
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
0x1
SETPEND8
Interrupt set-pending bits.
8
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
0x1
SETPEND9
Interrupt set-pending bits.
9
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
0x1
SETPEND10
Interrupt set-pending bits.
10
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
0x1
SETPEND11
Interrupt set-pending bits.
11
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
0x1
SETPEND12
Interrupt set-pending bits.
12
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
0x1
SETPEND13
Interrupt set-pending bits.
13
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
0x1
SETPEND14
Interrupt set-pending bits.
14
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
0x1
SETPEND15
Interrupt set-pending bits.
15
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
0x1
SETPEND16
Interrupt set-pending bits.
16
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
0x1
SETPEND17
Interrupt set-pending bits.
17
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
0x1
SETPEND18
Interrupt set-pending bits.
18
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
0x1
SETPEND19
Interrupt set-pending bits.
19
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
0x1
SETPEND20
Interrupt set-pending bits.
20
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
0x1
SETPEND21
Interrupt set-pending bits.
21
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
0x1
SETPEND22
Interrupt set-pending bits.
22
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
0x1
SETPEND23
Interrupt set-pending bits.
23
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
0x1
SETPEND24
Interrupt set-pending bits.
24
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
0x1
SETPEND25
Interrupt set-pending bits.
25
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
0x1
SETPEND26
Interrupt set-pending bits.
26
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
0x1
SETPEND27
Interrupt set-pending bits.
27
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
0x1
SETPEND28
Interrupt set-pending bits.
28
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
0x1
SETPEND29
Interrupt set-pending bits.
29
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
0x1
SETPEND30
Interrupt set-pending bits.
30
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
0x1
SETPEND31
Interrupt set-pending bits.
31
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
0x1
16
0x4
ICPR[%s]
Interrupt Clear Pending Register
0x180
32
read-write
0
0xFFFFFFFF
CLRPEND0
Interrupt clear-pending bits.
0
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
0x1
CLRPEND1
Interrupt clear-pending bits.
1
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
0x1
CLRPEND2
Interrupt clear-pending bits.
2
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
0x1
CLRPEND3
Interrupt clear-pending bits.
3
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
0x1
CLRPEND4
Interrupt clear-pending bits.
4
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
0x1
CLRPEND5
Interrupt clear-pending bits.
5
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
0x1
CLRPEND6
Interrupt clear-pending bits.
6
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
0x1
CLRPEND7
Interrupt clear-pending bits.
7
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
0x1
CLRPEND8
Interrupt clear-pending bits.
8
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
0x1
CLRPEND9
Interrupt clear-pending bits.
9
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
0x1
CLRPEND10
Interrupt clear-pending bits.
10
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
0x1
CLRPEND11
Interrupt clear-pending bits.
11
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
0x1
CLRPEND12
Interrupt clear-pending bits.
12
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
0x1
CLRPEND13
Interrupt clear-pending bits.
13
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
0x1
CLRPEND14
Interrupt clear-pending bits.
14
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
0x1
CLRPEND15
Interrupt clear-pending bits.
15
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
0x1
CLRPEND16
Interrupt clear-pending bits.
16
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
0x1
CLRPEND17
Interrupt clear-pending bits.
17
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
0x1
CLRPEND18
Interrupt clear-pending bits.
18
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
0x1
CLRPEND19
Interrupt clear-pending bits.
19
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
0x1
CLRPEND20
Interrupt clear-pending bits.
20
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
0x1
CLRPEND21
Interrupt clear-pending bits.
21
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
0x1
CLRPEND22
Interrupt clear-pending bits.
22
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
0x1
CLRPEND23
Interrupt clear-pending bits.
23
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
0x1
CLRPEND24
Interrupt clear-pending bits.
24
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
0x1
CLRPEND25
Interrupt clear-pending bits.
25
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
0x1
CLRPEND26
Interrupt clear-pending bits.
26
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
0x1
CLRPEND27
Interrupt clear-pending bits.
27
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
0x1
CLRPEND28
Interrupt clear-pending bits.
28
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
0x1
CLRPEND29
Interrupt clear-pending bits.
29
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
0x1
CLRPEND30
Interrupt clear-pending bits.
30
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
0x1
CLRPEND31
Interrupt clear-pending bits.
31
1
read-write
NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0
PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
0x1
16
0x4
IABR[%s]
Interrupt Active Bit Register
0x200
32
read-write
0
0
ACTIVE0
Active state bits.
0
1
read-write
NOT_ACTIVE
The interrupt is not active.
0
ACTIVE
The interrupt is active.
0x1
ACTIVE1
Active state bits.
1
1
read-write
NOT_ACTIVE
The interrupt is not active.
0
ACTIVE
The interrupt is active.
0x1
ACTIVE2
Active state bits.
2
1
read-write
NOT_ACTIVE
The interrupt is not active.
0
ACTIVE
The interrupt is active.
0x1
ACTIVE3
Active state bits.
3
1
read-write
NOT_ACTIVE
The interrupt is not active.
0
ACTIVE
The interrupt is active.
0x1
ACTIVE4
Active state bits.
4
1
read-write
NOT_ACTIVE
The interrupt is not active.
0
ACTIVE
The interrupt is active.
0x1
ACTIVE5
Active state bits.
5
1
read-write
NOT_ACTIVE
The interrupt is not active.
0
ACTIVE
The interrupt is active.
0x1
ACTIVE6
Active state bits.
6
1
read-write
NOT_ACTIVE
The interrupt is not active.
0
ACTIVE
The interrupt is active.
0x1
ACTIVE7
Active state bits.
7
1
read-write
NOT_ACTIVE
The interrupt is not active.
0
ACTIVE
The interrupt is active.
0x1
ACTIVE8
Active state bits.
8
1
read-write
NOT_ACTIVE
The interrupt is not active.
0
ACTIVE
The interrupt is active.
0x1
ACTIVE9
Active state bits.
9
1
read-write
NOT_ACTIVE
The interrupt is not active.
0
ACTIVE
The interrupt is active.
0x1
ACTIVE10
Active state bits.
10
1
read-write
NOT_ACTIVE
The interrupt is not active.
0
ACTIVE
The interrupt is active.
0x1
ACTIVE11
Active state bits.
11
1
read-write
NOT_ACTIVE
The interrupt is not active.
0
ACTIVE
The interrupt is active.
0x1
ACTIVE12
Active state bits.
12
1
read-write
NOT_ACTIVE
The interrupt is not active.
0
ACTIVE
The interrupt is active.
0x1
ACTIVE13
Active state bits.
13
1
read-write
NOT_ACTIVE
The interrupt is not active.
0
ACTIVE
The interrupt is active.
0x1
ACTIVE14
Active state bits.
14
1
read-write
NOT_ACTIVE
The interrupt is not active.
0
ACTIVE
The interrupt is active.
0x1
ACTIVE15
Active state bits.
15
1
read-write
NOT_ACTIVE
The interrupt is not active.
0
ACTIVE
The interrupt is active.
0x1
ACTIVE16
Active state bits.
16
1
read-write
NOT_ACTIVE
The interrupt is not active.
0
ACTIVE
The interrupt is active.
0x1
ACTIVE17
Active state bits.
17
1
read-write
NOT_ACTIVE
The interrupt is not active.
0
ACTIVE
The interrupt is active.
0x1
ACTIVE18
Active state bits.
18
1
read-write
NOT_ACTIVE
The interrupt is not active.
0
ACTIVE
The interrupt is active.
0x1
ACTIVE19
Active state bits.
19
1
read-write
NOT_ACTIVE
The interrupt is not active.
0
ACTIVE
The interrupt is active.
0x1
ACTIVE20
Active state bits.
20
1
read-write
NOT_ACTIVE
The interrupt is not active.
0
ACTIVE
The interrupt is active.
0x1
ACTIVE21
Active state bits.
21
1
read-write
NOT_ACTIVE
The interrupt is not active.
0
ACTIVE
The interrupt is active.
0x1
ACTIVE22
Active state bits.
22
1
read-write
NOT_ACTIVE
The interrupt is not active.
0
ACTIVE
The interrupt is active.
0x1
ACTIVE23
Active state bits.
23
1
read-write
NOT_ACTIVE
The interrupt is not active.
0
ACTIVE
The interrupt is active.
0x1
ACTIVE24
Active state bits.
24
1
read-write
NOT_ACTIVE
The interrupt is not active.
0
ACTIVE
The interrupt is active.
0x1
ACTIVE25
Active state bits.
25
1
read-write
NOT_ACTIVE
The interrupt is not active.
0
ACTIVE
The interrupt is active.
0x1
ACTIVE26
Active state bits.
26
1
read-write
NOT_ACTIVE
The interrupt is not active.
0
ACTIVE
The interrupt is active.
0x1
ACTIVE27
Active state bits.
27
1
read-write
NOT_ACTIVE
The interrupt is not active.
0
ACTIVE
The interrupt is active.
0x1
ACTIVE28
Active state bits.
28
1
read-write
NOT_ACTIVE
The interrupt is not active.
0
ACTIVE
The interrupt is active.
0x1
ACTIVE29
Active state bits.
29
1
read-write
NOT_ACTIVE
The interrupt is not active.
0
ACTIVE
The interrupt is active.
0x1
ACTIVE30
Active state bits.
30
1
read-write
NOT_ACTIVE
The interrupt is not active.
0
ACTIVE
The interrupt is active.
0x1
ACTIVE31
Active state bits.
31
1
read-write
NOT_ACTIVE
The interrupt is not active.
0
ACTIVE
The interrupt is active.
0x1
16
0x4
ITNS[%s]
Interrupt Target Non-secure Register
0x280
32
read-write
0
0
INTS0
Interrupt Targets Non-secure bits.
0
1
read-write
SECURE_STATE
The interrupt targets Secure state.
0
NON_SECURE_STATE
The interrupt targets Non-secure state.
0x1
INTS1
Interrupt Targets Non-secure bits.
1
1
read-write
SECURE_STATE
The interrupt targets Secure state.
0
NON_SECURE_STATE
The interrupt targets Non-secure state.
0x1
INTS2
Interrupt Targets Non-secure bits.
2
1
read-write
SECURE_STATE
The interrupt targets Secure state.
0
NON_SECURE_STATE
The interrupt targets Non-secure state.
0x1
INTS3
Interrupt Targets Non-secure bits.
3
1
read-write
SECURE_STATE
The interrupt targets Secure state.
0
NON_SECURE_STATE
The interrupt targets Non-secure state.
0x1
INTS4
Interrupt Targets Non-secure bits.
4
1
read-write
SECURE_STATE
The interrupt targets Secure state.
0
NON_SECURE_STATE
The interrupt targets Non-secure state.
0x1
INTS5
Interrupt Targets Non-secure bits.
5
1
read-write
SECURE_STATE
The interrupt targets Secure state.
0
NON_SECURE_STATE
The interrupt targets Non-secure state.
0x1
INTS6
Interrupt Targets Non-secure bits.
6
1
read-write
SECURE_STATE
The interrupt targets Secure state.
0
NON_SECURE_STATE
The interrupt targets Non-secure state.
0x1
INTS7
Interrupt Targets Non-secure bits.
7
1
read-write
SECURE_STATE
The interrupt targets Secure state.
0
NON_SECURE_STATE
The interrupt targets Non-secure state.
0x1
INTS8
Interrupt Targets Non-secure bits.
8
1
read-write
SECURE_STATE
The interrupt targets Secure state.
0
NON_SECURE_STATE
The interrupt targets Non-secure state.
0x1
INTS9
Interrupt Targets Non-secure bits.
9
1
read-write
SECURE_STATE
The interrupt targets Secure state.
0
NON_SECURE_STATE
The interrupt targets Non-secure state.
0x1
INTS10
Interrupt Targets Non-secure bits.
10
1
read-write
SECURE_STATE
The interrupt targets Secure state.
0
NON_SECURE_STATE
The interrupt targets Non-secure state.
0x1
INTS11
Interrupt Targets Non-secure bits.
11
1
read-write
SECURE_STATE
The interrupt targets Secure state.
0
NON_SECURE_STATE
The interrupt targets Non-secure state.
0x1
INTS12
Interrupt Targets Non-secure bits.
12
1
read-write
SECURE_STATE
The interrupt targets Secure state.
0
NON_SECURE_STATE
The interrupt targets Non-secure state.
0x1
INTS13
Interrupt Targets Non-secure bits.
13
1
read-write
SECURE_STATE
The interrupt targets Secure state.
0
NON_SECURE_STATE
The interrupt targets Non-secure state.
0x1
INTS14
Interrupt Targets Non-secure bits.
14
1
read-write
SECURE_STATE
The interrupt targets Secure state.
0
NON_SECURE_STATE
The interrupt targets Non-secure state.
0x1
INTS15
Interrupt Targets Non-secure bits.
15
1
read-write
SECURE_STATE
The interrupt targets Secure state.
0
NON_SECURE_STATE
The interrupt targets Non-secure state.
0x1
INTS16
Interrupt Targets Non-secure bits.
16
1
read-write
SECURE_STATE
The interrupt targets Secure state.
0
NON_SECURE_STATE
The interrupt targets Non-secure state.
0x1
INTS17
Interrupt Targets Non-secure bits.
17
1
read-write
SECURE_STATE
The interrupt targets Secure state.
0
NON_SECURE_STATE
The interrupt targets Non-secure state.
0x1
INTS18
Interrupt Targets Non-secure bits.
18
1
read-write
SECURE_STATE
The interrupt targets Secure state.
0
NON_SECURE_STATE
The interrupt targets Non-secure state.
0x1
INTS19
Interrupt Targets Non-secure bits.
19
1
read-write
SECURE_STATE
The interrupt targets Secure state.
0
NON_SECURE_STATE
The interrupt targets Non-secure state.
0x1
INTS20
Interrupt Targets Non-secure bits.
20
1
read-write
SECURE_STATE
The interrupt targets Secure state.
0
NON_SECURE_STATE
The interrupt targets Non-secure state.
0x1
INTS21
Interrupt Targets Non-secure bits.
21
1
read-write
SECURE_STATE
The interrupt targets Secure state.
0
NON_SECURE_STATE
The interrupt targets Non-secure state.
0x1
INTS22
Interrupt Targets Non-secure bits.
22
1
read-write
SECURE_STATE
The interrupt targets Secure state.
0
NON_SECURE_STATE
The interrupt targets Non-secure state.
0x1
INTS23
Interrupt Targets Non-secure bits.
23
1
read-write
SECURE_STATE
The interrupt targets Secure state.
0
NON_SECURE_STATE
The interrupt targets Non-secure state.
0x1
INTS24
Interrupt Targets Non-secure bits.
24
1
read-write
SECURE_STATE
The interrupt targets Secure state.
0
NON_SECURE_STATE
The interrupt targets Non-secure state.
0x1
INTS25
Interrupt Targets Non-secure bits.
25
1
read-write
SECURE_STATE
The interrupt targets Secure state.
0
NON_SECURE_STATE
The interrupt targets Non-secure state.
0x1
INTS26
Interrupt Targets Non-secure bits.
26
1
read-write
SECURE_STATE
The interrupt targets Secure state.
0
NON_SECURE_STATE
The interrupt targets Non-secure state.
0x1
INTS27
Interrupt Targets Non-secure bits.
27
1
read-write
SECURE_STATE
The interrupt targets Secure state.
0
NON_SECURE_STATE
The interrupt targets Non-secure state.
0x1
INTS28
Interrupt Targets Non-secure bits.
28
1
read-write
SECURE_STATE
The interrupt targets Secure state.
0
NON_SECURE_STATE
The interrupt targets Non-secure state.
0x1
INTS29
Interrupt Targets Non-secure bits.
29
1
read-write
SECURE_STATE
The interrupt targets Secure state.
0
NON_SECURE_STATE
The interrupt targets Non-secure state.
0x1
INTS30
Interrupt Targets Non-secure bits.
30
1
read-write
SECURE_STATE
The interrupt targets Secure state.
0
NON_SECURE_STATE
The interrupt targets Non-secure state.
0x1
INTS31
Interrupt Targets Non-secure bits.
31
1
read-write
SECURE_STATE
The interrupt targets Secure state.
0
NON_SECURE_STATE
The interrupt targets Non-secure state.
0x1
120
0x4
IPR[%s]
Interrupt Priority Register
0x300
32
read-write
0
0
PRI_0
no description available
0
8
read-write
PRI_1
no description available
8
8
read-write
PRI_2
no description available
16
8
read-write
PRI_3
no description available
24
8
read-write
STIR
Software Trigger Interrupt Register
0xE00
32
write-only
0
0xFFFFFFFF
INTID
Interrupt ID of the interrupt to trigger, in the range 0-479.
0
9
write-only
SCB
no description available
SCB
0xE000ED00
0
0x90
registers
AIRCR
Application Interrupt and Reset Control Register
0xC
32
read-write
0xFA050000
0xFFFFFFFF
VECTCLRACTIVE
Reserved for Debug use. This bit reads as 0. When writing to the register you must write 0 to this bit, otherwise behavior is UNPREDICTABLE. This bit is not banked between Security states.
1
1
write-only
SYSRESETREQ
System reset request. This bit allows software or a debugger to request a system reset. This bit is not banked between Security states. RW if SYSRESETREQS is 0. When SYSRESETREQS is set to 1, from Non-secure state this bit acts as RAZ/WI.
2
1
read-write
NO_REQUEST
Do not request a system reset.
0
REQUEST_RESET
Request a system reset.
0x1
SYSRESETREQS
System reset request, Secure state only. The value of this bit defines whether the SYSRESETREQ bit is functional for Non-secure use. This bit is not banked between Security states. RW from Secure State and RAZ/WI from Non-secure state.
3
1
read-write
SECURE_AND_NON_SECURE
SYSRESETREQ functionality is available to both Security states.
0
SECURE_ONLY
SYSRESETREQ functionality is only available to Secure state.
0x1
PRIGROUP
Interrupt priority grouping field. This field determines the split of group priority from subpriority. This bit is banked between Security states
8
3
read-write
BFHFNMINS
BusFault, HardFault, and NMI Non-secure enable. The value of this bit defines whether BusFault and NMI exceptions are Non-secure, and whether exceptions target the Non-secure HardFault exception. This bit is not banked between Security states. RW from Secure-state and RO from Non-secure state.
13
1
read-write
SECURE
BusFault, HardFault, and NMI are Secure.
0
NON_SECURE
BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault.
0x1
PRIS
Prioritize Secure exceptions. The value of this bit defines whether Secure exception priority boosting is enabled. This bit is not banked between Security states. RW from Secure state and RAZ/WI from Non-secure state.
14
1
read-write
SAME_PRIORITY
Priority ranges of Secure and Non-secure exceptions are identical
0
SECURE_PRIORITIZED
Non-secure exceptions are de-prioritized
0x1
ENDIANNESS
Data endianness bit. This bit is not banked between Security states.
15
1
read-only
LITTLE_ENDIAN
Little-endian.
0
BIG_ENDIAN
Big-endian
0x1
VECTKEY
Register key: Reads as 0xFA05. On writes, write 0x5FA to VECTKEY, otherwise the write is ignored. This Field is not banked between Security states.
16
16
read-only
SCR
The SCR controls features of entry to and exit from low-power state.
0x10
32
read-write
0
0xFFFFFFFF
SLEEPONEXIT
Indicates sleep-on-exit when returning from Handler mode to Thread mode. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. This bit is banked between Security states.
1
1
read-write
NOT_SLEEP
Do not sleep when returning to Thread mode.
0
SLEEP
Enter sleep, or deep sleep, on return from an ISR
0x1
SLEEPDEEP
Controls whether the processor uses sleep or deep sleep as its low-power mode. This bit is not banked between Security states.
2
1
read-write
SLEEP
Sleep.
0
DEEP_SLEEP
Deep sleep.
0x1
SLEEPDEEPS
Controls whether the SLEEPDEEP bit is only accessible from the Secure state. This bit in only accessible from the Secure state, and behaves as RAZ/WI when accessed from the Nonsecure state. This bit is not banked between Security states.
3
1
read-write
SECURE_AND_NON_SECURE
The SLEEPDEEP bit is accessible from both Security states.
0
SECURE_ONLY
The SLEEPDEEP bit behaves as RAZ/WI when accessed from the Non-secure state.
0x1
SEVONPEND
Send Event on Pending bit. When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction or an external event. This bit is banked between Security states.
4
1
read-write
EXCLUDE_DISABLED_INTERRUPTS
Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.
0
INCLUDE_DISABLED_INTERRUPTS
Enabled events and all interrupts, including disabled interrupts, can wakeup the processor
0x1
SHCSR
System Handler Control and State Register
0x24
32
read-write
0
0xFFFFFFFF
MEMFAULTACT
MemManage exception active.
0
1
read-write
NOT_ACTIVE
MemManage exception is not active.
0
ACTIVE
MemManage exception is active.
0x1
BUSFAULTACT
BusFault exception active.
1
1
read-write
NOT_ACTIVE
BusFault exception is not active.
0
ACTIVE
BusFault exception is active.
0x1
HARDFAULTACT
HardFault exception active.
2
1
read-write
NOT_ACTIVE
HardFault exception is not active.
0
ACTIVE
HardFault exception is active.
0x1
USGFAULTACT
UsageFault exception active.
3
1
read-write
NOT_ACTIVE
UsageFault exception is not active.
0
ACTIVE
UsageFault exception is active.
0x1
SECUREFAULTACT
SecureFault exception active
4
1
read-write
NOT_ACTIVE
SecureFault exception is not active.
0
ACTIVE
SecureFault exception is active.
0x1
NMIACT
NMI exception active.
5
1
read-write
NOT_ACTIVE
NMI exception is not active.
0
ACTIVE
NMI exception is active.
0x1
SVCALLACT
SVCall active.
7
1
read-write
NOT_ACTIVE
SVCall exception is not active.
0
ACTIVE
SVCall exception is active.
0x1
MONITORACT
Debug monitor active.
8
1
read-write
NOT_ACTIVE
Debug monitor exception is not active.
0
ACTIVE
Debug monitor exception is active.
0x1
PENDSVACT
PendSV exception active.
10
1
read-write
NOT_ACTIVE
PendSV exception is not active.
0
ACTIVE
PendSV exception is active.
0x1
SYSTICKACT
SysTick exception active.
11
1
read-write
NOT_ACTIVE
SysTick exception is not active.
0
ACTIVE
SysTick exception is active.
0x1
USGFAULTPENDED
UsageFault exception pending.
12
1
read-write
NOT_PENDING
UsageFault exception is not pending.
0
PENDING
UsageFault exception is pending.
0x1
MEMFAULTPENDED
MemManage exception pending.
13
1
read-write
NOT_PENDING
MemManage exception is not pending.
0
PENDING
MemManage exception is pending.
0x1
BUSFAULTPENDED
BusFault exception pending.
14
1
read-write
NOT_PENDING
BusFault exception is pending.
0
PENDING
BusFault exception is not pending.
0x1
SVCALLPENDED
SVCall pending.
15
1
read-write
NOT_PENDING
SVCall exception is not pending.
0
PENDING
SVCall exception is pending.
0x1
MEMFAULTENA
MemManage enable.
16
1
read-write
DISABLED
MemManage exception is disabled.
0
ENABLED
MemManage exception is enabled.
0x1
BUSFAULTENA
BusFault enable.
17
1
read-write
DISABLED
BusFault is disabled.
0
ENABLED
BusFault is enabled.
0x1
USGFAULTENA
UsageFault enable.
18
1
read-write
DISABLED
UsageFault is disabled.
0
ENABLED
UsageFault is enabled.
0x1
SECUREFAULTENA
SecureFault exception enable.
19
1
read-write
DISABLED
SecureFault exception is disabled.
0
ENABLED
SecureFault exception is enabled.
0x1
SECUREFAULTPENDED
SecureFault exception pended state bit.
20
1
read-write
DISABLED
SecureFault exception modification is disabled.
0
ENABLED
SecureFault exception modification is enabled.
0x1
HARDFAULTPENDED
HardFault exception pended state
21
1
read-write
DISABLED
HardFault exception modification is disabled.
0
ENABLED
HardFault exception modification is enabled.
0x1
CPACR
Coprocessor Access Control Register
0x88
32
read-write
0
0
CP0
CP0 Privilege.
0
2
read-write
ACCESS_DENIED
Access Denied. Any attempted accesses to this coprocessor generates a NOCP UsageFault.
0
PRIVILEGED_ONLY
Privileged access only. An unprivileged access generates a NOCP UsageFault.
0x1
FULL_ACCESS
Full access. Full access rights for this coprocessor.
0x3
CP1
CP1 Privilege.
2
2
read-write
ACCESS_DENIED
Access Denied. Any attempted accesses to this coprocessor generates a NOCP UsageFault.
0
PRIVILEGED_ONLY
Privileged access only. An unprivileged access generates a NOCP UsageFault.
0x1
FULL_ACCESS
Full access. Full access rights for this coprocessor.
0x3
CP2
CP2 Privilege.
4
2
read-write
ACCESS_DENIED
Access Denied. Any attempted accesses to this coprocessor generates a NOCP UsageFault.
0
PRIVILEGED_ONLY
Privileged access only. An unprivileged access generates a NOCP UsageFault.
0x1
FULL_ACCESS
Full access. Full access rights for this coprocessor.
0x3
CP3
CP3 Privilege.
6
2
read-write
ACCESS_DENIED
Access Denied. Any attempted accesses to this coprocessor generates a NOCP UsageFault.
0
PRIVILEGED_ONLY
Privileged access only. An unprivileged access generates a NOCP UsageFault.
0x1
FULL_ACCESS
Full access. Full access rights for this coprocessor.
0x3
CP4
CP4 Privilege.
8
2
read-write
ACCESS_DENIED
Access Denied. Any attempted accesses to this coprocessor generates a NOCP UsageFault.
0
PRIVILEGED_ONLY
Privileged access only. An unprivileged access generates a NOCP UsageFault.
0x1
FULL_ACCESS
Full access. Full access rights for this coprocessor.
0x3
CP5
CP5 Privilege.
10
2
read-write
ACCESS_DENIED
Access Denied. Any attempted accesses to this coprocessor generates a NOCP UsageFault.
0
PRIVILEGED_ONLY
Privileged access only. An unprivileged access generates a NOCP UsageFault.
0x1
FULL_ACCESS
Full access. Full access rights for this coprocessor.
0x3
CP6
CP6 Privilege.
12
2
read-write
ACCESS_DENIED
Access Denied. Any attempted accesses to this coprocessor generates a NOCP UsageFault.
0
PRIVILEGED_ONLY
Privileged access only. An unprivileged access generates a NOCP UsageFault.
0x1
FULL_ACCESS
Full access. Full access rights for this coprocessor.
0x3
CP7
CP7 Privilege.
14
2
read-write
ACCESS_DENIED
Access Denied. Any attempted accesses to this coprocessor generates a NOCP UsageFault.
0
PRIVILEGED_ONLY
Privileged access only. An unprivileged access generates a NOCP UsageFault.
0x1
FULL_ACCESS
Full access. Full access rights for this coprocessor.
0x3
CP10
CP10 Privilege.
20
2
read-write
ACCESS_DENIED
Access Denied. All accesses to the Floating-point Extension result in NOCP UsageFault.
0
PRIVILEGED_ONLY
Privileged access only. Unprivileged access to the Floatingpoint Extension result in NOCP UsageFault.
0x1
FULL_ACCESS
Full access. Full access rights to the Floatingpoint Extension.
0x3
CP11
CP11 Privilege.
22
2
read-write
ACCESS_DENIED
Access Denied. All accesses to the Floating-point Extension result in NOCP UsageFault.
0
PRIVILEGED_ONLY
Privileged access only. Unprivileged access to the Floatingpoint Extension result in NOCP UsageFault.
0x1
FULL_ACCESS
Full access. Full access rights to the Floatingpoint Extension.
0x3
NSACR
Non-secure Access Control Register
0x8C
32
read-write
0
0
CP0
CP0 access.
0
1
read-write
NOT_PERMITTED
Non-secure accesses to this coprocessor generate a NOCP UsageFault.
0
PERMITTED
Non-secure access to this coprocessor permitted.
0x1
CP1
CP1 access.
1
1
read-write
NOT_PERMITTED
Non-secure accesses to this coprocessor generate a NOCP UsageFault.
0
PERMITTED
Non-secure access to this coprocessor permitted.
0x1
CP2
CP2 access.
2
1
read-write
NOT_PERMITTED
Non-secure accesses to this coprocessor generate a NOCP UsageFault.
0
PERMITTED
Non-secure access to this coprocessor permitted.
0x1
CP3
CP3 access.
3
1
read-write
NOT_PERMITTED
Non-secure accesses to this coprocessor generate a NOCP UsageFault.
0
PERMITTED
Non-secure access to this coprocessor permitted.
0x1
CP4
CP4 access.
4
1
read-write
NOT_PERMITTED
Non-secure accesses to this coprocessor generate a NOCP UsageFault.
0
PERMITTED
Non-secure access to this coprocessor permitted.
0x1
CP5
CP5 access.
5
1
read-write
NOT_PERMITTED
Non-secure accesses to this coprocessor generate a NOCP UsageFault.
0
PERMITTED
Non-secure access to this coprocessor permitted.
0x1
CP6
CP6 access.
6
1
read-write
NOT_PERMITTED
Non-secure accesses to this coprocessor generate a NOCP UsageFault.
0
PERMITTED
Non-secure access to this coprocessor permitted.
0x1
CP7
CP7 access.
7
1
read-write
NOT_PERMITTED
Non-secure accesses to this coprocessor generate a NOCP UsageFault.
0
PERMITTED
Non-secure access to this coprocessor permitted.
0x1
CP10
CP10 access.
10
1
read-write
NOT_PERMITTED
Non-secure accesses to the Floating-point Extension generate a NOCP UsageFault.
0
PERMITTED
Non-secure access to the Floatingpoint Extension permitted.
0x1
CP11
CP11 access.
11
1
read-write
SAU
no description available
SAU
0xE000EDD0
0
0xEC
registers
CTRL
Security Attribution Unit Control Register
0xD0
32
read-write
0
0xFFFFFFFF
ENABLE
Enable. Enables the SAU. This bit is RAZ/WI when the Security Extension is implemented without an SAU region.
0
1
read-write
DISABLED
The SAU is disabled.
0
ENABLED
The SAU is enabled.
0x1
ALLNS
All Non-secure.
1
1
read-write
SECURED_MEMORY
Memory is marked as Secure and is not Non-secure callable.
0
NON_SECURED_MEMORY
Memory is marked as Non-secure.
0x1
TYPE
Security Attribution Unit Type Register
0xD4
32
read-write
0
0xFFFFFFFF
SREGION
SAU regions. The number of implemented SAU regions.
0
8
read-write
RNR
Security Attribution Unit Region Number Register
0xD8
32
read-write
0
0
REGION
Region number.
0
8
read-write
RBAR
Security Attribution Unit Region Base Address Register
0xDC
32
read-write
0
0
BADDR
Base address. Holds bits[31:5] of the base address for the selected SAU region. Bits[4:0] of the base address are defined as 0x00.
5
27
read-write
RLAR
Security Attribution Unit Region Limit Address Register
0xE0
32
read-write
0
0
ENABLE
Enable. SAU region enable.
0
1
read-write
ENABLED
SAU region is enabled.
0
DISABLED
SAU region is disabled.
0x1
NSC
Non-secure callable. Controls whether Non-secure state is permitted to execute an SG instruction from this region.
1
1
read-write
NOT_NON_SECURE_CALLABLE
Region is not Non-secure callable.
0
NON_SECURE_CALLABLE
Region is Non-secure callable.
0x1
LADDR
Limit address. Holds bits[31:5] of the limit address for the selected SAU region. Bits[4:0] of the limit address are defined as 0x1F.
5
27
read-write
SFSR
Secure Fault Status Register
0xE4
32
read-write
0
0xFFFFFFFF
INVEP
Invalid entry point.
0
1
read-write
NO_ERROR
Error has not occurred.
0
ERROR
Error has occurred.
0x1
INVIS
Invalid integrity signature flag.
1
1
read-write
NO_ERROR
Error has not occurred.
0
ERROR
Error has occurred.
0x1
INVER
Invalid exception return flag.
2
1
read-write
NO_ERROR
Error has not occurred.
0
ERROR
Error has occurred.
0x1
AUVIOL
Attribution unit violation flag.
3
1
read-write
NO_ERROR
Error has not occurred.
0
ERROR
Error has occurred.
0x1
INVTRAN
Invalid transition flag.
4
1
read-write
NO_ERROR
Error has not occurred.
0
ERROR
Error has occurred.
0x1
LSPERR
Lazy state preservation error flag.
5
1
read-write
NO_ERROR
Error has not occurred.
0
ERROR
Error has occurred.
0x1
SFARVALID
Secure fault address valid.
6
1
read-write
NOT_VALID
SFAR content not valid.
0
VALID
SFAR content valid.
0x1
LSERR
Lazy state error flag.
7
1
read-write
NO_ERROR
Error has not occurred
0
ERROR
Error has occurred.
0x1
SFAR
Secure Fault Address Register
0xE8
32
read-write
0
0
ADDRESS
When the SFARVALID bit of the SFSR is set to 1, this field holds the address of an access that caused an SAU violation.
0
32
read-write