31874 lines
1.4 MiB
31874 lines
1.4 MiB
/*
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** ###################################################################
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** Processors: MCXA153VFM
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** MCXA153VFT
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** MCXA153VLH
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**
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** Compilers: GNU C Compiler
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** IAR ANSI C/C++ Compiler for ARM
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** Keil ARM C/C++ Compiler
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** MCUXpresso Compiler
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**
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** Reference manual: MCXA1 User manual
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** Version: rev. 1.0, 2022-03-29
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** Build: b231121
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**
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** Abstract:
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** CMSIS Peripheral Access Layer for MCXA153
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**
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** Copyright 1997-2016 Freescale Semiconductor, Inc.
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** Copyright 2016-2023 NXP
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** SPDX-License-Identifier: BSD-3-Clause
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**
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** http: www.nxp.com
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** mail: support@nxp.com
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**
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** Revisions:
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** - rev. 1.0 (2022-03-29)
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** Initial version based on v0.1UM
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**
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** ###################################################################
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*/
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/*!
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* @file MCXA153.h
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* @version 1.0
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* @date 2022-03-29
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* @brief CMSIS Peripheral Access Layer for MCXA153
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*
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* CMSIS Peripheral Access Layer for MCXA153
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*/
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#if !defined(MCXA153_H_)
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#define MCXA153_H_ /**< Symbol preventing repeated inclusion */
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/** Memory map major version (memory maps with equal major version number are
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* compatible) */
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#define MCU_MEM_MAP_VERSION 0x0100U
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/** Memory map minor version */
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#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
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/* ----------------------------------------------------------------------------
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-- Interrupt vector numbers
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup Interrupt_vector_numbers Interrupt vector numbers
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* @{
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*/
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/** Interrupt Number Definitions */
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#define NUMBER_OF_INT_VECTORS 96 /**< Number of interrupts in the Vector table */
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typedef enum IRQn {
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/* Auxiliary constants */
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NotAvail_IRQn = -128, /**< Not available device specific interrupt */
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/* Core interrupts */
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NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
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HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */
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MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */
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BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */
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UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */
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SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */
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SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */
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DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */
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PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */
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SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */
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/* Device specific interrupts */
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Reserved16_IRQn = 0, /**< OR IRQ1 to IRQ53 */
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CMC_IRQn = 1, /**< Core Mode Controller interrupt */
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DMA_CH0_IRQn = 2, /**< DMA3_0_CH0 error or transfer complete */
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DMA_CH1_IRQn = 3, /**< DMA3_0_CH1 error or transfer complete */
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DMA_CH2_IRQn = 4, /**< DMA3_0_CH2 error or transfer complete */
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DMA_CH3_IRQn = 5, /**< DMA3_0_CH3 error or transfer complete */
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Reserved22_IRQn = 6, /**< Reserved interrupt */
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Reserved23_IRQn = 7, /**< Reserved interrupt */
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Reserved24_IRQn = 8, /**< Reserved interrupt */
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Reserved25_IRQn = 9, /**< Reserved interrupt */
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ERM0_SINGLE_BIT_IRQn = 10, /**< ERM Single Bit error interrupt */
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ERM0_MULTI_BIT_IRQn = 11, /**< ERM Multi Bit error interrupt */
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FMU0_IRQn = 12, /**< Flash Management Unit interrupt */
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GLIKEY0_IRQn = 13, /**< GLIKEY Interrupt */
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MBC0_IRQn = 14, /**< MBC secure violation interrupt */
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SCG0_IRQn = 15, /**< System Clock Generator interrupt */
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SPC0_IRQn = 16, /**< System Power Controller interrupt */
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Reserved33_IRQn = 17, /**< Reserved interrupt */
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WUU0_IRQn = 18, /**< Wake Up Unit interrupt */
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Reserved35_IRQn = 19, /**< Reserved interrupt */
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Reserved36_IRQn = 20, /**< Reserved interrupt */
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Reserved37_IRQn = 21, /**< Reserved interrupt */
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Reserved38_IRQn = 22, /**< Reserved interrupt */
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Reserved39_IRQn = 23, /**< Reserved interrupt */
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I3C0_IRQn = 24, /**< Improved Inter Integrated Circuit interrupt 0 */
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Reserved41_IRQn = 25, /**< Reserved interrupt */
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LPI2C0_IRQn = 26, /**< Low-Power Inter Integrated Circuit interrupt */
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Reserved43_IRQn = 27, /**< Reserved interrupt */
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LPSPI0_IRQn = 28, /**< Low-Power Serial Peripheral Interface interrupt */
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LPSPI1_IRQn = 29, /**< Low-Power Serial Peripheral Interface interrupt */
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Reserved46_IRQn = 30, /**< Reserved interrupt */
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LPUART0_IRQn = 31, /**< Low-Power Universal Asynchronous Receive/Transmit interrupt */
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LPUART1_IRQn = 32, /**< Low-Power Universal Asynchronous Receive/Transmit interrupt */
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LPUART2_IRQn = 33, /**< Low-Power Universal Asynchronous Receive/Transmit interrupt */
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Reserved50_IRQn = 34, /**< Reserved interrupt */
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Reserved51_IRQn = 35, /**< Reserved interrupt */
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USB0_IRQn = 36, /**< Universal Serial Bus - Full Speed interrupt */
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Reserved53_IRQn = 37, /**< Reserved interrupt */
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CDOG0_IRQn = 38, /**< Code Watchdog Timer 0 interrupt */
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CTIMER0_IRQn = 39, /**< Standard counter/timer 0 interrupt */
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CTIMER1_IRQn = 40, /**< Standard counter/timer 1 interrupt */
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CTIMER2_IRQn = 41, /**< Standard counter/timer 2 interrupt */
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Reserved58_IRQn = 42, /**< Reserved interrupt */
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Reserved59_IRQn = 43, /**< Reserved interrupt */
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FLEXPWM0_RELOAD_ERROR_IRQn = 44, /**< FlexPWM0_reload_error interrupt */
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FLEXPWM0_FAULT_IRQn = 45, /**< FlexPWM0_fault interrupt */
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FLEXPWM0_SUBMODULE0_IRQn = 46, /**< FlexPWM0 Submodule 0 capture/compare/reload interrupt */
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FLEXPWM0_SUBMODULE1_IRQn = 47, /**< FlexPWM0 Submodule 1 capture/compare/reload interrupt */
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FLEXPWM0_SUBMODULE2_IRQn = 48, /**< FlexPWM0 Submodule 2 capture/compare/reload interrupt */
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Reserved65_IRQn = 49, /**< Reserved interrupt */
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QDC0_COMPARE_IRQn = 50, /**< Compare */
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QDC0_HOME_IRQn = 51, /**< Home */
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QDC0_WATCHDOG_IRQn = 52, /**< Watchdog / Simultaneous A and B Change */
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QDC0_INDEX_IRQn = 53, /**< Index / Roll Over / Roll Under */
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FREQME0_IRQn = 54, /**< Frequency Measurement interrupt */
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LPTMR0_IRQn = 55, /**< Low Power Timer 0 interrupt */
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Reserved72_IRQn = 56, /**< Reserved interrupt */
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OS_EVENT_IRQn = 57, /**< OS event timer interrupt */
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WAKETIMER0_IRQn = 58, /**< Wake Timer Interrupt */
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UTICK0_IRQn = 59, /**< Micro-Tick Timer interrupt */
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WWDT0_IRQn = 60, /**< Windowed Watchdog Timer 0 interrupt */
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Reserved77_IRQn = 61, /**< Reserved interrupt */
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ADC0_IRQn = 62, /**< Analog-to-Digital Converter interrupt */
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Reserved79_IRQn = 63, /**< Reserved interrupt */
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CMP0_IRQn = 64, /**< Comparator interrupt */
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CMP1_IRQn = 65, /**< Comparator interrupt */
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Reserved82_IRQn = 66, /**< Reserved interrupt */
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Reserved83_IRQn = 67, /**< Reserved interrupt */
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Reserved84_IRQn = 68, /**< Reserved interrupt */
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Reserved85_IRQn = 69, /**< Reserved interrupt */
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Reserved86_IRQn = 70, /**< Reserved interrupt */
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GPIO0_IRQn = 71, /**< General Purpose Input/Output interrupt 0 */
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GPIO1_IRQn = 72, /**< General Purpose Input/Output interrupt 1 */
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GPIO2_IRQn = 73, /**< General Purpose Input/Output interrupt 2 */
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GPIO3_IRQn = 74, /**< General Purpose Input/Output interrupt 3 */
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Reserved91_IRQn = 75, /**< Reserved interrupt */
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Reserved92_IRQn = 76, /**< Reserved interrupt */
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Reserved93_IRQn = 77, /**< Reserved interrupt */
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Reserved94_IRQn = 78, /**< Reserved interrupt */
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Reserved95_IRQn = 79 /**< Reserved interrupt */
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} IRQn_Type;
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/*!
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* @}
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*/ /* end of group Interrupt_vector_numbers */
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/* ----------------------------------------------------------------------------
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-- Cortex M33 Core Configuration
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration
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* @{
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*/
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#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
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#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */
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#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
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#define __FPU_PRESENT 0 /**< Defines if an FPU is present or not */
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#define __DSP_PRESENT 0 /**< Defines if Armv8-M Mainline core supports DSP instructions */
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#define __SAUREGION_PRESENT 0 /**< Defines if an SAU is present or not */
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#include "core_cm33.h" /* Core Peripheral Access Layer */
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#include "system_MCXA153.h" /* Device specific configuration file */
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/*!
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* @}
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*/ /* end of group Cortex_Core_Configuration */
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/* ----------------------------------------------------------------------------
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-- Mapping Information
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup Mapping_Information Mapping Information
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* @{
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*/
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/** Mapping Information */
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/*!
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* @addtogroup dma_request
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* @{
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*!
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* @brief Structure for the DMA hardware request
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*
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* Defines the structure for the DMA hardware request collections. The user can configure the
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* hardware request to trigger the DMA transfer accordingly. The index
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* of the hardware request varies according to the to SoC.
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*/
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typedef enum _dma_request_source
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{
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kDma0RequestDisabled = 0U, /**< Disabled */
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kDma0RequestWUU0 = 1U, /**< WUU Wake up event */
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kDma0RequestMuxI3c0Rx = 7U, /**< I3C0 Receive request */
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kDma0RequestMuxI3c0Tx = 8U, /**< I3C0 Transmit request */
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kDma0RequestLPI2C0Rx = 11U, /**< LPI2C0 Receive request */
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kDma0RequestLPI2C0Tx = 12U, /**< LPI2C0 Transmit request */
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kDma0RequestLPSPI0Rx = 15U, /**< LPSPI0 Receive request */
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kDma0RequestLPSPI0Tx = 16U, /**< LPSPI0 Transmit request */
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kDma0RequestLPSPI1Rx = 17U, /**< LPSPI1 Receive request */
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kDma0RequestLPSPI1Tx = 18U, /**< LPSPI1 Transmit request */
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kDma0RequestLPUART0Rx = 21U, /**< LPUART0 Receive request */
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kDma0RequestLPUART0Tx = 22U, /**< LPUART0 Transmit request */
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kDma0RequestLPUART1Rx = 23U, /**< LPUART1 Receive request */
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kDma0RequestLPUART1Tx = 24U, /**< LPUART1 Transmit request */
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kDma0RequestLPUART2Rx = 25U, /**< LPUART2 Receive request */
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kDma0RequestLPUART2Tx = 26U, /**< LPUART2 Transmit request */
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kDma0RequestMuxCtimer0M0 = 31U, /**< CTIMER0 Match channel 0 request */
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kDma0RequestMuxCtimer0M1 = 32U, /**< CTIMER0 Match channel 1 request */
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kDma0RequestMuxCtimer1M0 = 33U, /**< CTIMER1 Match channel 0 request */
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kDma0RequestMuxCtimer1M1 = 34U, /**< CTIMER1 Match channel 1 request */
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kDma0RequestMuxCtimer2M0 = 35U, /**< CTIMER2 Match channel 0 request */
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kDma0RequestMuxCtimer2M1 = 36U, /**< CTIMER2 Match channel 1 request */
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kDma0RequestMuxFlexPWM0ReqCapt0 = 41U, /**< FlexPWM0 capture0 request */
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kDma0RequestMuxFlexPWM0ReqCapt1 = 42U, /**< FlexPWM0 capture1 request */
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kDma0RequestMuxFlexPWM0ReqCapt2 = 43U, /**< FlexPWM0 capture2 request */
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kDma0RequestMuxFlexPWM0ReqVal0 = 45U, /**< FlexPWM0 value0 request */
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kDma0RequestMuxFlexPWM0ReqVal1 = 46U, /**< FlexPWM0 value1 request */
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kDma0RequestMuxFlexPWM0ReqVal2 = 47U, /**< FlexPWM0 value2 request */
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kDma0RequestMuxLptmr0 = 49U, /**< LPTMR0 Counter match event */
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kDma0RequestMuxAdc0FifoRequest = 51U, /**< ADC0 FIFO request */
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kDma0RequestMuxHsCmp0DmaRequest = 53U, /**< CMP0 DMA_request */
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kDma0RequestMuxHsCmp1DmaRequest = 54U, /**< CMP1 DMA_request */
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kDma0RequestMuxGpio0PinEventRequest0 = 60U, /**< GPIO0 Pin event request 0 */
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kDma0RequestMuxGpio1PinEventRequest0 = 61U, /**< GPIO1 Pin event request 0 */
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kDma0RequestMuxGpio2PinEventRequest0 = 62U, /**< GPIO2 Pin event request 0 */
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kDma0RequestMuxGpio3PinEventRequest0 = 63U, /**< GPIO3 Pin event request 0 */
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kDma0RequestMuxQdc0 = 65U, /**< DMA request for new buffered value */
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} dma_request_source_t;
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/* @} */
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/*!
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* @addtogroup eim_memory_channel
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* @{
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*!
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* @brief Structure for the eim_memory_channel
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*
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* Defines the structure for the EIM resource collections.
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*/
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typedef enum _eim_memory_channel
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{
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kEIM_MemoryChannelRAMA0 = 0U, /**< Memory RAMA0 */
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} eim_memory_channel_t;
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/* @} */
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/*!
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* @addtogroup eim_error_injection_channel_enable
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* @{
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*!
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* @brief Structure for the eim_error_injection_channel_enable
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*
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* Defines the structure for the EIM error injection resource collections.
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*/
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typedef enum _eim_error_injection_channel_enable
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{
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kEIM_MemoryChannelRAMAEnable = 0x80000000U, /**< Memory channel 0(RAMA0) error injection enable */
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} eim_error_injection_channel_enable_t;
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/* @} */
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/*!
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* @addtogroup erm_memory_channel
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* @{
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*!
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* @brief Structure for the erm_memory_channel
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*
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* Defines the structure for the ERM resource collections.
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*/
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typedef enum _erm_memory_channel
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{
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kERM_MemoryChannelRAMA0 = 0U, /**< Memory RAMA0 */
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kERM_MemoryChannelFLASH = 1U, /**< Memory FLASH */
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} erm_memory_channel_t;
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/* @} */
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/*!
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* @}
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*/ /* end of group Mapping_Information */
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/* ----------------------------------------------------------------------------
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-- Device Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup Peripheral_access_layer Device Peripheral Access Layer
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* @{
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*/
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/*
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** Start of section using anonymous unions
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*/
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#if defined(__ARMCC_VERSION)
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#if (__ARMCC_VERSION >= 6010050)
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#pragma clang diagnostic push
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#else
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#pragma push
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#pragma anon_unions
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#endif
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#elif defined(__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined(__IAR_SYSTEMS_ICC__)
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#pragma language=extended
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#else
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#error Not supported compiler type
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#endif
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/* ----------------------------------------------------------------------------
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-- ADC Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
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* @{
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*/
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/** ADC - Register Layout Typedef */
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typedef struct {
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__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
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__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
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uint8_t RESERVED_0[8];
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__IO uint32_t CTRL; /**< Control Register, offset: 0x10 */
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__IO uint32_t STAT; /**< Status Register, offset: 0x14 */
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__IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */
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__IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */
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__IO uint32_t CFG; /**< Configuration Register, offset: 0x20 */
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__IO uint32_t PAUSE; /**< Pause Register, offset: 0x24 */
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uint8_t RESERVED_1[12];
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__O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */
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__IO uint32_t TSTAT; /**< Trigger Status Register, offset: 0x38 */
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uint8_t RESERVED_2[4];
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__IO uint32_t OFSTRIM; /**< Offset Trim Register, offset: 0x40 */
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uint8_t RESERVED_3[4];
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__IO uint32_t HSTRIM; /**< High Speed Trim Register, offset: 0x48 */
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uint8_t RESERVED_4[84];
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__IO uint32_t TCTRL[4]; /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */
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uint8_t RESERVED_5[48];
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__IO uint32_t FCTRL; /**< FIFO Control Register, offset: 0xE0 */
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uint8_t RESERVED_6[12];
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__I uint32_t GCC[1]; /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */
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uint8_t RESERVED_7[4];
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__IO uint32_t GCR[1]; /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */
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uint8_t RESERVED_8[4];
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struct { /* offset: 0x100, array step: 0x8 */
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__IO uint32_t CMDL; /**< Command Low Buffer Register, array offset: 0x100, array step: 0x8 */
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__IO uint32_t CMDH; /**< Command High Buffer Register, array offset: 0x104, array step: 0x8 */
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} CMD[7];
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uint8_t RESERVED_9[200];
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__IO uint32_t CV[15]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */
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uint8_t RESERVED_10[196];
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__I uint32_t RESFIFO; /**< Data Result FIFO Register, offset: 0x300 */
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uint8_t RESERVED_11[252];
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__IO uint32_t CAL_GAR0; /**< Calibration General A-Side Registers, offset: 0x400 */
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__IO uint32_t CAL_GAR1; /**< Calibration General A-Side Registers, offset: 0x404 */
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__IO uint32_t CAL_GAR2; /**< Calibration General A-Side Registers, offset: 0x408 */
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__IO uint32_t CAL_GAR3; /**< Calibration General A-Side Registers, offset: 0x40C */
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__IO uint32_t CAL_GAR4; /**< Calibration General A-Side Registers, offset: 0x410 */
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__IO uint32_t CAL_GAR5; /**< Calibration General A-Side Registers, offset: 0x414 */
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__IO uint32_t CAL_GAR6; /**< Calibration General A-Side Registers, offset: 0x418 */
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__IO uint32_t CAL_GAR7; /**< Calibration General A-Side Registers, offset: 0x41C */
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__IO uint32_t CAL_GAR8; /**< Calibration General A-Side Registers, offset: 0x420 */
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__IO uint32_t CAL_GAR9; /**< Calibration General A-Side Registers, offset: 0x424 */
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__IO uint32_t CAL_GAR10; /**< Calibration General A-Side Registers, offset: 0x428 */
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__IO uint32_t CAL_GAR11; /**< Calibration General A-Side Registers, offset: 0x42C */
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__IO uint32_t CAL_GAR12; /**< Calibration General A-Side Registers, offset: 0x430 */
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__IO uint32_t CAL_GAR13; /**< Calibration General A-Side Registers, offset: 0x434 */
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__IO uint32_t CAL_GAR14; /**< Calibration General A-Side Registers, offset: 0x438 */
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__IO uint32_t CAL_GAR15; /**< Calibration General A-Side Registers, offset: 0x43C */
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__IO uint32_t CAL_GAR16; /**< Calibration General A-Side Registers, offset: 0x440 */
|
|
__IO uint32_t CAL_GAR17; /**< Calibration General A-Side Registers, offset: 0x444 */
|
|
__IO uint32_t CAL_GAR18; /**< Calibration General A-Side Registers, offset: 0x448 */
|
|
__IO uint32_t CAL_GAR19; /**< Calibration General A-Side Registers, offset: 0x44C */
|
|
__IO uint32_t CAL_GAR20; /**< Calibration General A-Side Registers, offset: 0x450 */
|
|
__IO uint32_t CAL_GAR21; /**< Calibration General A-Side Registers, offset: 0x454 */
|
|
__IO uint32_t CAL_GAR22; /**< Calibration General A-Side Registers, offset: 0x458 */
|
|
__IO uint32_t CAL_GAR23; /**< Calibration General A-Side Registers, offset: 0x45C */
|
|
__IO uint32_t CAL_GAR24; /**< Calibration General A-Side Registers, offset: 0x460 */
|
|
__IO uint32_t CAL_GAR25; /**< Calibration General A-Side Registers, offset: 0x464 */
|
|
__IO uint32_t CAL_GAR26; /**< Calibration General A-Side Registers, offset: 0x468 */
|
|
__IO uint32_t CAL_GAR27; /**< Calibration General A-Side Registers, offset: 0x46C */
|
|
__IO uint32_t CAL_GAR28; /**< Calibration General A-Side Registers, offset: 0x470 */
|
|
__IO uint32_t CAL_GAR29; /**< Calibration General A-Side Registers, offset: 0x474 */
|
|
__IO uint32_t CAL_GAR30; /**< Calibration General A-Side Registers, offset: 0x478 */
|
|
__IO uint32_t CAL_GAR31; /**< Calibration General A-Side Registers, offset: 0x47C */
|
|
__IO uint32_t CAL_GAR32; /**< Calibration General A-Side Registers, offset: 0x480 */
|
|
uint8_t RESERVED_12[2932];
|
|
__IO uint32_t CFG2; /**< Configuration 2 Register, offset: 0xFF8 */
|
|
} ADC_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- ADC Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup ADC_Register_Masks ADC Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name VERID - Version ID Register */
|
|
/*! @{ */
|
|
|
|
#define ADC_VERID_RES_MASK (0x1U)
|
|
#define ADC_VERID_RES_SHIFT (0U)
|
|
/*! RES - Resolution
|
|
* 0b0..Up to 12-bit single ended resolution supported (and 13-bit differential resolution if VERID[DIFFEN] = 1b).
|
|
* 0b1..Up to 16-bit single ended resolution supported (and 16-bit differential resolution if VERID[DIFFEN] = 1b).
|
|
*/
|
|
#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)
|
|
|
|
#define ADC_VERID_DIFFEN_MASK (0x2U)
|
|
#define ADC_VERID_DIFFEN_SHIFT (1U)
|
|
/*! DIFFEN - Differential Supported
|
|
* 0b0..Differential operation not supported.
|
|
* 0b1..Differential operation supported.
|
|
*/
|
|
#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)
|
|
|
|
#define ADC_VERID_MVI_MASK (0x8U)
|
|
#define ADC_VERID_MVI_SHIFT (3U)
|
|
/*! MVI - Multi Vref Implemented
|
|
* 0b0..Single voltage reference high (VREFH) input supported.
|
|
* 0b1..Multiple voltage reference high (VREFH) inputs supported.
|
|
*/
|
|
#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)
|
|
|
|
#define ADC_VERID_CSW_MASK (0x70U)
|
|
#define ADC_VERID_CSW_SHIFT (4U)
|
|
/*! CSW - Channel Scale Width
|
|
* 0b000..Channel scaling not supported.
|
|
* 0b001..Channel scaling supported. 1-bit CSCALE control field.
|
|
* 0b110..Channel scaling supported. 6-bit CSCALE control field.
|
|
*/
|
|
#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)
|
|
|
|
#define ADC_VERID_VR1RNGI_MASK (0x100U)
|
|
#define ADC_VERID_VR1RNGI_SHIFT (8U)
|
|
/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented
|
|
* 0b0..Range control not required. CFG[VREF1RNG] is not implemented.
|
|
* 0b1..Range control required. CFG[VREF1RNG] is implemented.
|
|
*/
|
|
#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)
|
|
|
|
#define ADC_VERID_IADCKI_MASK (0x200U)
|
|
#define ADC_VERID_IADCKI_SHIFT (9U)
|
|
/*! IADCKI - Internal ADC Clock Implemented
|
|
* 0b0..Internal clock source not implemented.
|
|
* 0b1..Internal clock source (and CFG[ADCKEN]) implemented.
|
|
*/
|
|
#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)
|
|
|
|
#define ADC_VERID_CALOFSI_MASK (0x400U)
|
|
#define ADC_VERID_CALOFSI_SHIFT (10U)
|
|
/*! CALOFSI - Calibration Function Implemented
|
|
* 0b0..Calibration Not Implemented.
|
|
* 0b1..Calibration Implemented.
|
|
*/
|
|
#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)
|
|
|
|
#define ADC_VERID_NUM_SEC_MASK (0x800U)
|
|
#define ADC_VERID_NUM_SEC_SHIFT (11U)
|
|
/*! NUM_SEC - Number of Single Ended Outputs Supported
|
|
* 0b0..This design supports one single ended conversion at a time.
|
|
* 0b1..This design supports two simultaneous single ended conversions.
|
|
*/
|
|
#define ADC_VERID_NUM_SEC(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK)
|
|
|
|
#define ADC_VERID_NUM_FIFO_MASK (0x7000U)
|
|
#define ADC_VERID_NUM_FIFO_SHIFT (12U)
|
|
/*! NUM_FIFO - Number of FIFOs
|
|
* 0b000..N/A
|
|
* 0b001..This design supports one result FIFO.
|
|
* 0b010..This design supports two result FIFOs.
|
|
* 0b011..This design supports three result FIFOs.
|
|
* 0b100..This design supports four result FIFOs.
|
|
*/
|
|
#define ADC_VERID_NUM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK)
|
|
|
|
#define ADC_VERID_MINOR_MASK (0xFF0000U)
|
|
#define ADC_VERID_MINOR_SHIFT (16U)
|
|
/*! MINOR - Minor Version Number */
|
|
#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)
|
|
|
|
#define ADC_VERID_MAJOR_MASK (0xFF000000U)
|
|
#define ADC_VERID_MAJOR_SHIFT (24U)
|
|
/*! MAJOR - Major Version Number */
|
|
#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PARAM - Parameter Register */
|
|
/*! @{ */
|
|
|
|
#define ADC_PARAM_TRIG_NUM_MASK (0xFFU)
|
|
#define ADC_PARAM_TRIG_NUM_SHIFT (0U)
|
|
/*! TRIG_NUM - Trigger Number */
|
|
#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)
|
|
|
|
#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U)
|
|
#define ADC_PARAM_FIFOSIZE_SHIFT (8U)
|
|
/*! FIFOSIZE - Result FIFO Depth
|
|
* 0b00000001..Result FIFO depth = 2 dataword.
|
|
* 0b00000100..Result FIFO depth = 4 datawords.
|
|
* 0b00001000..Result FIFO depth = 8 datawords.
|
|
* 0b00010000..Result FIFO depth = 16 datawords.
|
|
* 0b00100000..Result FIFO depth = 32 datawords.
|
|
* 0b01000000..Result FIFO depth = 64 datawords.
|
|
*/
|
|
#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)
|
|
|
|
#define ADC_PARAM_CV_NUM_MASK (0xFF0000U)
|
|
#define ADC_PARAM_CV_NUM_SHIFT (16U)
|
|
/*! CV_NUM - Compare Value Number */
|
|
#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)
|
|
|
|
#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U)
|
|
#define ADC_PARAM_CMD_NUM_SHIFT (24U)
|
|
/*! CMD_NUM - Command Buffer Number */
|
|
#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CTRL - Control Register */
|
|
/*! @{ */
|
|
|
|
#define ADC_CTRL_ADCEN_MASK (0x1U)
|
|
#define ADC_CTRL_ADCEN_SHIFT (0U)
|
|
/*! ADCEN - ADC Enable
|
|
* 0b0..ADC is disabled.
|
|
* 0b1..ADC is enabled.
|
|
*/
|
|
#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)
|
|
|
|
#define ADC_CTRL_RST_MASK (0x2U)
|
|
#define ADC_CTRL_RST_SHIFT (1U)
|
|
/*! RST - Software Reset
|
|
* 0b0..ADC logic is not reset.
|
|
* 0b1..ADC logic is reset.
|
|
*/
|
|
#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)
|
|
|
|
#define ADC_CTRL_DOZEN_MASK (0x4U)
|
|
#define ADC_CTRL_DOZEN_SHIFT (2U)
|
|
/*! DOZEN - Doze Enable
|
|
* 0b0..ADC is enabled in low power mode.
|
|
* 0b1..ADC is disabled in low power mode.
|
|
*/
|
|
#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)
|
|
|
|
#define ADC_CTRL_CAL_REQ_MASK (0x8U)
|
|
#define ADC_CTRL_CAL_REQ_SHIFT (3U)
|
|
/*! CAL_REQ - Auto-Calibration Request
|
|
* 0b0..No request for hardware calibration has been made
|
|
* 0b1..A request for hardware calibration has been made
|
|
*/
|
|
#define ADC_CTRL_CAL_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK)
|
|
|
|
#define ADC_CTRL_CALOFS_MASK (0x10U)
|
|
#define ADC_CTRL_CALOFS_SHIFT (4U)
|
|
/*! CALOFS - Offset Calibration Request
|
|
* 0b0..No request for offset calibration has been made
|
|
* 0b1..Request for offset calibration function
|
|
*/
|
|
#define ADC_CTRL_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK)
|
|
|
|
#define ADC_CTRL_CALHS_MASK (0x40U)
|
|
#define ADC_CTRL_CALHS_SHIFT (6U)
|
|
/*! CALHS - High Speed Mode Trim Request
|
|
* 0b0..No request for high speed mode trim has been made
|
|
* 0b1..Request for high speed mode trim has been made
|
|
*/
|
|
#define ADC_CTRL_CALHS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALHS_SHIFT)) & ADC_CTRL_CALHS_MASK)
|
|
|
|
#define ADC_CTRL_RSTFIFO0_MASK (0x100U)
|
|
#define ADC_CTRL_RSTFIFO0_SHIFT (8U)
|
|
/*! RSTFIFO0 - Reset FIFO 0
|
|
* 0b0..No effect.
|
|
* 0b1..FIFO 0 is reset.
|
|
*/
|
|
#define ADC_CTRL_RSTFIFO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK)
|
|
|
|
#define ADC_CTRL_CAL_AVGS_MASK (0xF0000U)
|
|
#define ADC_CTRL_CAL_AVGS_SHIFT (16U)
|
|
/*! CAL_AVGS - Auto-Calibration Averages
|
|
* 0b0000..Single conversion.
|
|
* 0b0001..2 conversions averaged.
|
|
* 0b0010..4 conversions averaged.
|
|
* 0b0011..8 conversions averaged.
|
|
* 0b0100..16 conversions averaged.
|
|
* 0b0101..32 conversions averaged.
|
|
* 0b0110..64 conversions averaged.
|
|
* 0b0111..128 conversions averaged.
|
|
* 0b1000..256 conversions averaged.
|
|
* 0b1001..512 conversions averaged.
|
|
* 0b1010..1024 conversions averaged.
|
|
*/
|
|
#define ADC_CTRL_CAL_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name STAT - Status Register */
|
|
/*! @{ */
|
|
|
|
#define ADC_STAT_RDY0_MASK (0x1U)
|
|
#define ADC_STAT_RDY0_SHIFT (0U)
|
|
/*! RDY0 - Result FIFO 0 Ready Flag
|
|
* 0b0..Result FIFO 0 data level not above watermark level.
|
|
* 0b1..Result FIFO 0 holding data above watermark level.
|
|
*/
|
|
#define ADC_STAT_RDY0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK)
|
|
|
|
#define ADC_STAT_FOF0_MASK (0x2U)
|
|
#define ADC_STAT_FOF0_SHIFT (1U)
|
|
/*! FOF0 - Result FIFO 0 Overflow Flag
|
|
* 0b0..No result FIFO 0 overflow has occurred since the last time the flag was cleared.
|
|
* 0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared.
|
|
*/
|
|
#define ADC_STAT_FOF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK)
|
|
|
|
#define ADC_STAT_TEXC_INT_MASK (0x100U)
|
|
#define ADC_STAT_TEXC_INT_SHIFT (8U)
|
|
/*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception
|
|
* 0b0..No trigger exceptions have occurred.
|
|
* 0b1..A trigger exception has occurred and is pending acknowledgement.
|
|
*/
|
|
#define ADC_STAT_TEXC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK)
|
|
|
|
#define ADC_STAT_TCOMP_INT_MASK (0x200U)
|
|
#define ADC_STAT_TCOMP_INT_SHIFT (9U)
|
|
/*! TCOMP_INT - Interrupt Flag For Trigger Completion
|
|
* 0b0..Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion.
|
|
* 0b1..Trigger sequence has been completed and all data is stored in the associated FIFO.
|
|
*/
|
|
#define ADC_STAT_TCOMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK)
|
|
|
|
#define ADC_STAT_CAL_RDY_MASK (0x400U)
|
|
#define ADC_STAT_CAL_RDY_SHIFT (10U)
|
|
/*! CAL_RDY - Calibration Ready
|
|
* 0b0..Calibration is incomplete or hasn't been ran.
|
|
* 0b1..The ADC is calibrated.
|
|
*/
|
|
#define ADC_STAT_CAL_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK)
|
|
|
|
#define ADC_STAT_ADC_ACTIVE_MASK (0x800U)
|
|
#define ADC_STAT_ADC_ACTIVE_SHIFT (11U)
|
|
/*! ADC_ACTIVE - ADC Active
|
|
* 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed.
|
|
* 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger.
|
|
*/
|
|
#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK)
|
|
|
|
#define ADC_STAT_TRGACT_MASK (0x30000U)
|
|
#define ADC_STAT_TRGACT_SHIFT (16U)
|
|
/*! TRGACT - Trigger Active
|
|
* 0b00..Command (sequence) associated with Trigger 0 currently being executed.
|
|
* 0b01..Command (sequence) associated with Trigger 1 currently being executed.
|
|
* 0b10..Command (sequence) associated with Trigger 2 currently being executed.
|
|
* 0b11..Command (sequence) associated with Trigger 3 currently being executed.
|
|
*/
|
|
#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)
|
|
|
|
#define ADC_STAT_CMDACT_MASK (0x7000000U)
|
|
#define ADC_STAT_CMDACT_SHIFT (24U)
|
|
/*! CMDACT - Command Active
|
|
* 0b000..No command is currently in progress.
|
|
* 0b001..Command 1 currently being executed.
|
|
* 0b010..Command 2 currently being executed.
|
|
* 0b011-0b111..Associated command number is currently being executed.
|
|
*/
|
|
#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name IE - Interrupt Enable Register */
|
|
/*! @{ */
|
|
|
|
#define ADC_IE_FWMIE0_MASK (0x1U)
|
|
#define ADC_IE_FWMIE0_SHIFT (0U)
|
|
/*! FWMIE0 - FIFO 0 Watermark Interrupt Enable
|
|
* 0b0..FIFO 0 watermark interrupts are not enabled.
|
|
* 0b1..FIFO 0 watermark interrupts are enabled.
|
|
*/
|
|
#define ADC_IE_FWMIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK)
|
|
|
|
#define ADC_IE_FOFIE0_MASK (0x2U)
|
|
#define ADC_IE_FOFIE0_SHIFT (1U)
|
|
/*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable
|
|
* 0b0..FIFO 0 overflow interrupts are not enabled.
|
|
* 0b1..FIFO 0 overflow interrupts are enabled.
|
|
*/
|
|
#define ADC_IE_FOFIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK)
|
|
|
|
#define ADC_IE_TEXC_IE_MASK (0x100U)
|
|
#define ADC_IE_TEXC_IE_SHIFT (8U)
|
|
/*! TEXC_IE - Trigger Exception Interrupt Enable
|
|
* 0b0..Trigger exception interrupts are disabled.
|
|
* 0b1..Trigger exception interrupts are enabled.
|
|
*/
|
|
#define ADC_IE_TEXC_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK)
|
|
|
|
#define ADC_IE_TCOMP_IE_MASK (0xF0000U)
|
|
#define ADC_IE_TCOMP_IE_SHIFT (16U)
|
|
/*! TCOMP_IE - Trigger Completion Interrupt Enable
|
|
* 0b0000..Trigger completion interrupts are disabled.
|
|
* 0b0001..Trigger completion interrupts are enabled for trigger source 0 only.
|
|
* 0b0010..Trigger completion interrupts are enabled for trigger source 1 only.
|
|
* 0b0011-0b1110..Associated trigger completion interrupts are enabled.
|
|
* 0b1111..Trigger completion interrupts are enabled for every trigger source.
|
|
*/
|
|
#define ADC_IE_TCOMP_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DE - DMA Enable Register */
|
|
/*! @{ */
|
|
|
|
#define ADC_DE_FWMDE0_MASK (0x1U)
|
|
#define ADC_DE_FWMDE0_SHIFT (0U)
|
|
/*! FWMDE0 - FIFO 0 Watermark DMA Enable
|
|
* 0b0..DMA request disabled.
|
|
* 0b1..DMA request enabled.
|
|
*/
|
|
#define ADC_DE_FWMDE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CFG - Configuration Register */
|
|
/*! @{ */
|
|
|
|
#define ADC_CFG_TPRICTRL_MASK (0x3U)
|
|
#define ADC_CFG_TPRICTRL_SHIFT (0U)
|
|
/*! TPRICTRL - ADC Trigger Priority Control
|
|
* 0b00..If a higher priority trigger is detected during command processing, the current conversion is aborted
|
|
* and the new command specified by the trigger is started.
|
|
* 0b01..If a higher priority trigger is received during command processing, the current command is stopped after
|
|
* completing the current conversion. If averaging is enabled, the averaging loop will be completed.
|
|
* However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced.
|
|
* 0b10..If a higher priority trigger is received during command processing, the current command will be
|
|
* completed (averaging, looping, compare) before servicing the higher priority trigger.
|
|
* 0b11..
|
|
*/
|
|
#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)
|
|
|
|
#define ADC_CFG_PWRSEL_MASK (0x20U)
|
|
#define ADC_CFG_PWRSEL_SHIFT (5U)
|
|
/*! PWRSEL - Power Configuration Select
|
|
* 0b0..Low power
|
|
* 0b1..High power
|
|
*/
|
|
#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK)
|
|
|
|
#define ADC_CFG_REFSEL_MASK (0xC0U)
|
|
#define ADC_CFG_REFSEL_SHIFT (6U)
|
|
/*! REFSEL - Voltage Reference Selection
|
|
* 0b00..(Default) Option 1 setting.
|
|
* 0b01..Option 2 setting.
|
|
* 0b10..Option 3 setting.
|
|
* 0b11..Reserved
|
|
*/
|
|
#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
|
|
|
|
#define ADC_CFG_TRES_MASK (0x100U)
|
|
#define ADC_CFG_TRES_SHIFT (8U)
|
|
/*! TRES - Trigger Resume Enable
|
|
* 0b0..Trigger sequences interrupted by a high priority trigger exception are not automatically resumed or restarted.
|
|
* 0b1..Trigger sequences interrupted by a high priority trigger exception are automatically resumed or restarted.
|
|
*/
|
|
#define ADC_CFG_TRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK)
|
|
|
|
#define ADC_CFG_TCMDRES_MASK (0x200U)
|
|
#define ADC_CFG_TCMDRES_SHIFT (9U)
|
|
/*! TCMDRES - Trigger Command Resume
|
|
* 0b0..Trigger sequences interrupted by a high priority trigger exception is automatically restarted.
|
|
* 0b1..Trigger sequences interrupted by a high priority trigger exception is resumed from the command executing before the exception.
|
|
*/
|
|
#define ADC_CFG_TCMDRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK)
|
|
|
|
#define ADC_CFG_HPT_EXDI_MASK (0x400U)
|
|
#define ADC_CFG_HPT_EXDI_SHIFT (10U)
|
|
/*! HPT_EXDI - High Priority Trigger Exception Disable
|
|
* 0b0..High priority trigger exceptions are enabled.
|
|
* 0b1..High priority trigger exceptions are disabled.
|
|
*/
|
|
#define ADC_CFG_HPT_EXDI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK)
|
|
|
|
#define ADC_CFG_PUDLY_MASK (0xFF0000U)
|
|
#define ADC_CFG_PUDLY_SHIFT (16U)
|
|
/*! PUDLY - Power Up Delay */
|
|
#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)
|
|
|
|
#define ADC_CFG_PWREN_MASK (0x10000000U)
|
|
#define ADC_CFG_PWREN_SHIFT (28U)
|
|
/*! PWREN - ADC Analog Pre-Enable
|
|
* 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays.
|
|
* 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost
|
|
* of higher DC current consumption). Note that a single power up delay (CFG[PUDLY]) is executed immediately
|
|
* once PWREN is set, and any detected trigger does not begin ADC operation until the power up delay time has
|
|
* passed. After this initial delay expires the analog remains pre-enabled and no additional delays are
|
|
* executed.
|
|
*/
|
|
#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PAUSE - Pause Register */
|
|
/*! @{ */
|
|
|
|
#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU)
|
|
#define ADC_PAUSE_PAUSEDLY_SHIFT (0U)
|
|
/*! PAUSEDLY - Pause Delay */
|
|
#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)
|
|
|
|
#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U)
|
|
#define ADC_PAUSE_PAUSEEN_SHIFT (31U)
|
|
/*! PAUSEEN - PAUSE Option Enable
|
|
* 0b0..Pause operation disabled
|
|
* 0b1..Pause operation enabled
|
|
*/
|
|
#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SWTRIG - Software Trigger Register */
|
|
/*! @{ */
|
|
|
|
#define ADC_SWTRIG_SWT0_MASK (0x1U)
|
|
#define ADC_SWTRIG_SWT0_SHIFT (0U)
|
|
/*! SWT0 - Software Trigger 0 Event
|
|
* 0b0..No trigger 0 event generated.
|
|
* 0b1..Trigger 0 event generated.
|
|
*/
|
|
#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)
|
|
|
|
#define ADC_SWTRIG_SWT1_MASK (0x2U)
|
|
#define ADC_SWTRIG_SWT1_SHIFT (1U)
|
|
/*! SWT1 - Software Trigger 1 Event
|
|
* 0b0..No trigger 1 event generated.
|
|
* 0b1..Trigger 1 event generated.
|
|
*/
|
|
#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)
|
|
|
|
#define ADC_SWTRIG_SWT2_MASK (0x4U)
|
|
#define ADC_SWTRIG_SWT2_SHIFT (2U)
|
|
/*! SWT2 - Software Trigger 2 Event
|
|
* 0b0..No trigger 2 event generated.
|
|
* 0b1..Trigger 2 event generated.
|
|
*/
|
|
#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK)
|
|
|
|
#define ADC_SWTRIG_SWT3_MASK (0x8U)
|
|
#define ADC_SWTRIG_SWT3_SHIFT (3U)
|
|
/*! SWT3 - Software Trigger 3 Event
|
|
* 0b0..No trigger 3 event generated.
|
|
* 0b1..Trigger 3 event generated.
|
|
*/
|
|
#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TSTAT - Trigger Status Register */
|
|
/*! @{ */
|
|
|
|
#define ADC_TSTAT_TEXC_NUM_MASK (0xFU)
|
|
#define ADC_TSTAT_TEXC_NUM_SHIFT (0U)
|
|
/*! TEXC_NUM - Trigger Exception Number
|
|
* 0b0000..No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1.
|
|
* 0b0001..Trigger 0 has been interrupted by a high priority exception.
|
|
* 0b0010..Trigger 1 has been interrupted by a high priority exception.
|
|
* 0b0011-0b1110..Associated trigger sequence has interrupted by a high priority exception.
|
|
* 0b1111..Every trigger sequence has been interrupted by a high priority exception.
|
|
*/
|
|
#define ADC_TSTAT_TEXC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK)
|
|
|
|
#define ADC_TSTAT_TCOMP_FLAG_MASK (0xF0000U)
|
|
#define ADC_TSTAT_TCOMP_FLAG_SHIFT (16U)
|
|
/*! TCOMP_FLAG - Trigger Completion Flag
|
|
* 0b0000..No triggers have been completed. Trigger completion interrupts are disabled.
|
|
* 0b0001..Trigger 0 has been completed and trigger 0 has enabled completion interrupts.
|
|
* 0b0010..Trigger 1 has been completed and trigger 1 has enabled completion interrupts.
|
|
* 0b0011-0b1110..Associated trigger sequence has completed and has enabled completion interrupts.
|
|
* 0b1111..Every trigger sequence has been completed and every trigger has enabled completion interrupts.
|
|
*/
|
|
#define ADC_TSTAT_TCOMP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name OFSTRIM - Offset Trim Register */
|
|
/*! @{ */
|
|
|
|
#define ADC_OFSTRIM_OFSTRIM_MASK (0x3FFU)
|
|
#define ADC_OFSTRIM_OFSTRIM_SHIFT (0U)
|
|
/*! OFSTRIM - Trim for Offset */
|
|
#define ADC_OFSTRIM_OFSTRIM(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_SHIFT)) & ADC_OFSTRIM_OFSTRIM_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name HSTRIM - High Speed Trim Register */
|
|
/*! @{ */
|
|
|
|
#define ADC_HSTRIM_HSTRIM_MASK (0x1FU)
|
|
#define ADC_HSTRIM_HSTRIM_SHIFT (0U)
|
|
/*! HSTRIM - Trim for High Speed Conversions */
|
|
#define ADC_HSTRIM_HSTRIM(x) (((uint32_t)(((uint32_t)(x)) << ADC_HSTRIM_HSTRIM_SHIFT)) & ADC_HSTRIM_HSTRIM_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TCTRL - Trigger Control Register */
|
|
/*! @{ */
|
|
|
|
#define ADC_TCTRL_HTEN_MASK (0x1U)
|
|
#define ADC_TCTRL_HTEN_SHIFT (0U)
|
|
/*! HTEN - Trigger Enable
|
|
* 0b0..Hardware trigger source disabled
|
|
* 0b1..Hardware trigger source enabled
|
|
*/
|
|
#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)
|
|
|
|
#define ADC_TCTRL_TPRI_MASK (0x300U)
|
|
#define ADC_TCTRL_TPRI_SHIFT (8U)
|
|
/*! TPRI - Trigger Priority Setting
|
|
* 0b00..Set to highest priority, Level 1
|
|
* 0b01-0b10..Set to corresponding priority level
|
|
* 0b11..Set to lowest priority, Level 4
|
|
*/
|
|
#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)
|
|
|
|
#define ADC_TCTRL_RSYNC_MASK (0x8000U)
|
|
#define ADC_TCTRL_RSYNC_SHIFT (15U)
|
|
/*! RSYNC - Trigger Resync */
|
|
#define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK)
|
|
|
|
#define ADC_TCTRL_TDLY_MASK (0xF0000U)
|
|
#define ADC_TCTRL_TDLY_SHIFT (16U)
|
|
/*! TDLY - Trigger Delay Select */
|
|
#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)
|
|
|
|
#define ADC_TCTRL_TSYNC_MASK (0x800000U)
|
|
#define ADC_TCTRL_TSYNC_SHIFT (23U)
|
|
/*! TSYNC - Trigger Synchronous Select */
|
|
#define ADC_TCTRL_TSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TSYNC_SHIFT)) & ADC_TCTRL_TSYNC_MASK)
|
|
|
|
#define ADC_TCTRL_TCMD_MASK (0x7000000U)
|
|
#define ADC_TCTRL_TCMD_SHIFT (24U)
|
|
/*! TCMD - Trigger Command Select
|
|
* 0b000..Not a valid selection from the command buffer. Trigger event is ignored.
|
|
* 0b001..CMD1 is executed
|
|
* 0b010-0b110..Corresponding CMD is executed
|
|
* 0b111..CMD7 is executed
|
|
*/
|
|
#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of ADC_TCTRL */
|
|
#define ADC_TCTRL_COUNT (4U)
|
|
|
|
/*! @name FCTRL - FIFO Control Register */
|
|
/*! @{ */
|
|
|
|
#define ADC_FCTRL_FCOUNT_MASK (0xFU)
|
|
#define ADC_FCTRL_FCOUNT_SHIFT (0U)
|
|
/*! FCOUNT - Result FIFO Counter */
|
|
#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)
|
|
|
|
#define ADC_FCTRL_FWMARK_MASK (0x70000U)
|
|
#define ADC_FCTRL_FWMARK_SHIFT (16U)
|
|
/*! FWMARK - Watermark Level Selection */
|
|
#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GCC - Gain Calibration Control */
|
|
/*! @{ */
|
|
|
|
#define ADC_GCC_GAIN_CAL_MASK (0xFFFFU)
|
|
#define ADC_GCC_GAIN_CAL_SHIFT (0U)
|
|
/*! GAIN_CAL - Gain Calibration Value */
|
|
#define ADC_GCC_GAIN_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK)
|
|
|
|
#define ADC_GCC_RDY_MASK (0x1000000U)
|
|
#define ADC_GCC_RDY_SHIFT (24U)
|
|
/*! RDY - Gain Calibration Value Valid
|
|
* 0b0..The GAIN_CAL value is invalid. Run the hardware calibration routine for this value to be set.
|
|
* 0b1..The GAIN_CAL value is valid. GAIN_CAL should be used by software to derive GCRa[GCALR].
|
|
*/
|
|
#define ADC_GCC_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of ADC_GCC */
|
|
#define ADC_GCC_COUNT (1U)
|
|
|
|
/*! @name GCR - Gain Calculation Result */
|
|
/*! @{ */
|
|
|
|
#define ADC_GCR_GCALR_MASK (0x1FFFFU)
|
|
#define ADC_GCR_GCALR_SHIFT (0U)
|
|
/*! GCALR - Gain Calculation Result */
|
|
#define ADC_GCR_GCALR(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK)
|
|
|
|
#define ADC_GCR_RDY_MASK (0x1000000U)
|
|
#define ADC_GCR_RDY_SHIFT (24U)
|
|
/*! RDY - Gain Calculation Ready
|
|
* 0b0..The GCALR value is invalid.
|
|
* 0b1..The GCALR value is valid.
|
|
*/
|
|
#define ADC_GCR_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of ADC_GCR */
|
|
#define ADC_GCR_COUNT (1U)
|
|
|
|
/*! @name CMDL - Command Low Buffer Register */
|
|
/*! @{ */
|
|
|
|
#define ADC_CMDL_ADCH_MASK (0x1FU)
|
|
#define ADC_CMDL_ADCH_SHIFT (0U)
|
|
/*! ADCH - Input Channel Select
|
|
* 0b00000..Select CH0A.
|
|
* 0b00001..Select CH1A.
|
|
* 0b00010..Select CH2A.
|
|
* 0b00011..Select CH3A.
|
|
* 0b00100-0b11101..Select corresponding channel CHnA.
|
|
* 0b11110..Select CH30A.
|
|
* 0b11111..Select CH31A.
|
|
*/
|
|
#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)
|
|
|
|
#define ADC_CMDL_CTYPE_MASK (0x60U)
|
|
#define ADC_CMDL_CTYPE_SHIFT (5U)
|
|
/*! CTYPE - Conversion Type
|
|
* 0b00..Single-Ended Mode. Only A side channel is converted.
|
|
* 0b01-0b11..Reserved.
|
|
*/
|
|
#define ADC_CMDL_CTYPE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK)
|
|
|
|
#define ADC_CMDL_MODE_MASK (0x80U)
|
|
#define ADC_CMDL_MODE_SHIFT (7U)
|
|
/*! MODE - Select Resolution of Conversions
|
|
* 0b0..Standard resolution. Single-ended 12-bit conversion.
|
|
* 0b1..High resolution. Single-ended 16-bit conversion.
|
|
*/
|
|
#define ADC_CMDL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of ADC_CMDL */
|
|
#define ADC_CMDL_COUNT (7U)
|
|
|
|
/*! @name CMDH - Command High Buffer Register */
|
|
/*! @{ */
|
|
|
|
#define ADC_CMDH_CMPEN_MASK (0x3U)
|
|
#define ADC_CMDH_CMPEN_SHIFT (0U)
|
|
/*! CMPEN - Compare Function Enable
|
|
* 0b00..Compare disabled.
|
|
* 0b01..Reserved
|
|
* 0b10..Compare enabled. Store on true.
|
|
* 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
|
|
*/
|
|
#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)
|
|
|
|
#define ADC_CMDH_WAIT_TRIG_MASK (0x4U)
|
|
#define ADC_CMDH_WAIT_TRIG_SHIFT (2U)
|
|
/*! WAIT_TRIG - Wait for Trigger Assertion before Execution.
|
|
* 0b0..This command will be automatically executed.
|
|
* 0b1..The active trigger must be asserted again before executing this command.
|
|
*/
|
|
#define ADC_CMDH_WAIT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK)
|
|
|
|
#define ADC_CMDH_LWI_MASK (0x80U)
|
|
#define ADC_CMDH_LWI_SHIFT (7U)
|
|
/*! LWI - Loop with Increment
|
|
* 0b0..Auto channel increment disabled
|
|
* 0b1..Auto channel increment enabled
|
|
*/
|
|
#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)
|
|
|
|
#define ADC_CMDH_STS_MASK (0x700U)
|
|
#define ADC_CMDH_STS_SHIFT (8U)
|
|
/*! STS - Sample Time Select
|
|
* 0b000..Minimum sample time of 3.5 ADCK cycles.
|
|
* 0b001..3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time.
|
|
* 0b010..3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time.
|
|
* 0b011..3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time.
|
|
* 0b100..3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time.
|
|
* 0b101..3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time.
|
|
* 0b110..3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time.
|
|
* 0b111..3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time.
|
|
*/
|
|
#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)
|
|
|
|
#define ADC_CMDH_AVGS_MASK (0xF000U)
|
|
#define ADC_CMDH_AVGS_SHIFT (12U)
|
|
/*! AVGS - Hardware Average Select
|
|
* 0b0000..Single conversion.
|
|
* 0b0001..2 conversions averaged.
|
|
* 0b0010..4 conversions averaged.
|
|
* 0b0011..8 conversions averaged.
|
|
* 0b0100..16 conversions averaged.
|
|
* 0b0101..32 conversions averaged.
|
|
* 0b0110..64 conversions averaged.
|
|
* 0b0111..128 conversions averaged.
|
|
* 0b1000..256 conversions averaged.
|
|
* 0b1001..512 conversions averaged.
|
|
* 0b1010..1024 conversions averaged.
|
|
*/
|
|
#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)
|
|
|
|
#define ADC_CMDH_LOOP_MASK (0xF0000U)
|
|
#define ADC_CMDH_LOOP_SHIFT (16U)
|
|
/*! LOOP - Loop Count Select
|
|
* 0b0000..Looping not enabled. Command executes 1 time.
|
|
* 0b0001..Loop 1 time. Command executes 2 times.
|
|
* 0b0010..Loop 2 times. Command executes 3 times.
|
|
* 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times.
|
|
* 0b1111..Loop 15 times. Command executes 16 times.
|
|
*/
|
|
#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)
|
|
|
|
#define ADC_CMDH_NEXT_MASK (0x7000000U)
|
|
#define ADC_CMDH_NEXT_SHIFT (24U)
|
|
/*! NEXT - Next Command Select
|
|
* 0b000..No next command defined. Terminate conversions at completion of current command. If lower priority
|
|
* trigger pending, begin command associated with lower priority trigger.
|
|
* 0b001..Select CMD1 command buffer register as next command.
|
|
* 0b010-0b110..Select corresponding CMD command buffer register as next command
|
|
* 0b111..Select CMD7 command buffer register as next command.
|
|
*/
|
|
#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of ADC_CMDH */
|
|
#define ADC_CMDH_COUNT (7U)
|
|
|
|
/*! @name CV - Compare Value Register */
|
|
/*! @{ */
|
|
|
|
#define ADC_CV_CVL_MASK (0xFFFFU)
|
|
#define ADC_CV_CVL_SHIFT (0U)
|
|
/*! CVL - Compare Value Low */
|
|
#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)
|
|
|
|
#define ADC_CV_CVH_MASK (0xFFFF0000U)
|
|
#define ADC_CV_CVH_SHIFT (16U)
|
|
/*! CVH - Compare Value High */
|
|
#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of ADC_CV */
|
|
#define ADC_CV_COUNT (15U)
|
|
|
|
/*! @name RESFIFO - Data Result FIFO Register */
|
|
/*! @{ */
|
|
|
|
#define ADC_RESFIFO_D_MASK (0xFFFFU)
|
|
#define ADC_RESFIFO_D_SHIFT (0U)
|
|
/*! D - Data Result */
|
|
#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)
|
|
|
|
#define ADC_RESFIFO_TSRC_MASK (0x30000U)
|
|
#define ADC_RESFIFO_TSRC_SHIFT (16U)
|
|
/*! TSRC - Trigger Source
|
|
* 0b00..Trigger source 0 initiated this conversion.
|
|
* 0b01..Trigger source 1 initiated this conversion.
|
|
* 0b10-0b10..Corresponding trigger source initiated this conversion.
|
|
* 0b11..Trigger source 3 initiated this conversion.
|
|
*/
|
|
#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)
|
|
|
|
#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U)
|
|
#define ADC_RESFIFO_LOOPCNT_SHIFT (20U)
|
|
/*! LOOPCNT - Loop Count Value
|
|
* 0b0000..Result is from initial conversion in command.
|
|
* 0b0001..Result is from second conversion in command.
|
|
* 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command.
|
|
* 0b1111..Result is from 16th conversion in command.
|
|
*/
|
|
#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)
|
|
|
|
#define ADC_RESFIFO_CMDSRC_MASK (0x7000000U)
|
|
#define ADC_RESFIFO_CMDSRC_SHIFT (24U)
|
|
/*! CMDSRC - Command Buffer Source
|
|
* 0b000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state prior
|
|
* to an ADC conversion result dataword being stored to a RESFIFO buffer.
|
|
* 0b001..CMD1 buffer used as control settings for this conversion.
|
|
* 0b010-0b110..Corresponding command buffer used as control settings for this conversion.
|
|
* 0b111..CMD7 buffer used as control settings for this conversion.
|
|
*/
|
|
#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)
|
|
|
|
#define ADC_RESFIFO_VALID_MASK (0x80000000U)
|
|
#define ADC_RESFIFO_VALID_SHIFT (31U)
|
|
/*! VALID - FIFO Entry is Valid
|
|
* 0b0..FIFO is empty. Discard any read from RESFIFO.
|
|
* 0b1..FIFO record read from RESFIFO is valid.
|
|
*/
|
|
#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAL_GAR0 - Calibration General A-Side Registers */
|
|
/*! @{ */
|
|
|
|
#define ADC_CAL_GAR0_CAL_GAR_VAL_MASK (0xFFFFU)
|
|
#define ADC_CAL_GAR0_CAL_GAR_VAL_SHIFT (0U)
|
|
/*! CAL_GAR_VAL - Calibration General A Side Register Element */
|
|
#define ADC_CAL_GAR0_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR0_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR0_CAL_GAR_VAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAL_GAR1 - Calibration General A-Side Registers */
|
|
/*! @{ */
|
|
|
|
#define ADC_CAL_GAR1_CAL_GAR_VAL_MASK (0xFFFFU)
|
|
#define ADC_CAL_GAR1_CAL_GAR_VAL_SHIFT (0U)
|
|
/*! CAL_GAR_VAL - Calibration General A Side Register Element */
|
|
#define ADC_CAL_GAR1_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR1_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR1_CAL_GAR_VAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAL_GAR2 - Calibration General A-Side Registers */
|
|
/*! @{ */
|
|
|
|
#define ADC_CAL_GAR2_CAL_GAR_VAL_MASK (0xFFFFU)
|
|
#define ADC_CAL_GAR2_CAL_GAR_VAL_SHIFT (0U)
|
|
/*! CAL_GAR_VAL - Calibration General A Side Register Element */
|
|
#define ADC_CAL_GAR2_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR2_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR2_CAL_GAR_VAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAL_GAR3 - Calibration General A-Side Registers */
|
|
/*! @{ */
|
|
|
|
#define ADC_CAL_GAR3_CAL_GAR_VAL_MASK (0xFFFFU)
|
|
#define ADC_CAL_GAR3_CAL_GAR_VAL_SHIFT (0U)
|
|
/*! CAL_GAR_VAL - Calibration General A Side Register Element */
|
|
#define ADC_CAL_GAR3_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR3_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR3_CAL_GAR_VAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAL_GAR4 - Calibration General A-Side Registers */
|
|
/*! @{ */
|
|
|
|
#define ADC_CAL_GAR4_CAL_GAR_VAL_MASK (0xFFFFU)
|
|
#define ADC_CAL_GAR4_CAL_GAR_VAL_SHIFT (0U)
|
|
/*! CAL_GAR_VAL - Calibration General A Side Register Element */
|
|
#define ADC_CAL_GAR4_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR4_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR4_CAL_GAR_VAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAL_GAR5 - Calibration General A-Side Registers */
|
|
/*! @{ */
|
|
|
|
#define ADC_CAL_GAR5_CAL_GAR_VAL_MASK (0xFFFFU)
|
|
#define ADC_CAL_GAR5_CAL_GAR_VAL_SHIFT (0U)
|
|
/*! CAL_GAR_VAL - Calibration General A Side Register Element */
|
|
#define ADC_CAL_GAR5_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR5_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR5_CAL_GAR_VAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAL_GAR6 - Calibration General A-Side Registers */
|
|
/*! @{ */
|
|
|
|
#define ADC_CAL_GAR6_CAL_GAR_VAL_MASK (0xFFFFU)
|
|
#define ADC_CAL_GAR6_CAL_GAR_VAL_SHIFT (0U)
|
|
/*! CAL_GAR_VAL - Calibration General A Side Register Element */
|
|
#define ADC_CAL_GAR6_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR6_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR6_CAL_GAR_VAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAL_GAR7 - Calibration General A-Side Registers */
|
|
/*! @{ */
|
|
|
|
#define ADC_CAL_GAR7_CAL_GAR_VAL_MASK (0xFFFFU)
|
|
#define ADC_CAL_GAR7_CAL_GAR_VAL_SHIFT (0U)
|
|
/*! CAL_GAR_VAL - Calibration General A Side Register Element */
|
|
#define ADC_CAL_GAR7_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR7_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR7_CAL_GAR_VAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAL_GAR8 - Calibration General A-Side Registers */
|
|
/*! @{ */
|
|
|
|
#define ADC_CAL_GAR8_CAL_GAR_VAL_MASK (0xFFFFU)
|
|
#define ADC_CAL_GAR8_CAL_GAR_VAL_SHIFT (0U)
|
|
/*! CAL_GAR_VAL - Calibration General A Side Register Element */
|
|
#define ADC_CAL_GAR8_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR8_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR8_CAL_GAR_VAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAL_GAR9 - Calibration General A-Side Registers */
|
|
/*! @{ */
|
|
|
|
#define ADC_CAL_GAR9_CAL_GAR_VAL_MASK (0xFFFFU)
|
|
#define ADC_CAL_GAR9_CAL_GAR_VAL_SHIFT (0U)
|
|
/*! CAL_GAR_VAL - Calibration General A Side Register Element */
|
|
#define ADC_CAL_GAR9_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR9_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR9_CAL_GAR_VAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAL_GAR10 - Calibration General A-Side Registers */
|
|
/*! @{ */
|
|
|
|
#define ADC_CAL_GAR10_CAL_GAR_VAL_MASK (0xFFFFU)
|
|
#define ADC_CAL_GAR10_CAL_GAR_VAL_SHIFT (0U)
|
|
/*! CAL_GAR_VAL - Calibration General A Side Register Element */
|
|
#define ADC_CAL_GAR10_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR10_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR10_CAL_GAR_VAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAL_GAR11 - Calibration General A-Side Registers */
|
|
/*! @{ */
|
|
|
|
#define ADC_CAL_GAR11_CAL_GAR_VAL_MASK (0xFFFFU)
|
|
#define ADC_CAL_GAR11_CAL_GAR_VAL_SHIFT (0U)
|
|
/*! CAL_GAR_VAL - Calibration General A Side Register Element */
|
|
#define ADC_CAL_GAR11_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR11_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR11_CAL_GAR_VAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAL_GAR12 - Calibration General A-Side Registers */
|
|
/*! @{ */
|
|
|
|
#define ADC_CAL_GAR12_CAL_GAR_VAL_MASK (0xFFFFU)
|
|
#define ADC_CAL_GAR12_CAL_GAR_VAL_SHIFT (0U)
|
|
/*! CAL_GAR_VAL - Calibration General A Side Register Element */
|
|
#define ADC_CAL_GAR12_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR12_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR12_CAL_GAR_VAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAL_GAR13 - Calibration General A-Side Registers */
|
|
/*! @{ */
|
|
|
|
#define ADC_CAL_GAR13_CAL_GAR_VAL_MASK (0xFFFFU)
|
|
#define ADC_CAL_GAR13_CAL_GAR_VAL_SHIFT (0U)
|
|
/*! CAL_GAR_VAL - Calibration General A Side Register Element */
|
|
#define ADC_CAL_GAR13_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR13_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR13_CAL_GAR_VAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAL_GAR14 - Calibration General A-Side Registers */
|
|
/*! @{ */
|
|
|
|
#define ADC_CAL_GAR14_CAL_GAR_VAL_MASK (0xFFFFU)
|
|
#define ADC_CAL_GAR14_CAL_GAR_VAL_SHIFT (0U)
|
|
/*! CAL_GAR_VAL - Calibration General A Side Register Element */
|
|
#define ADC_CAL_GAR14_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR14_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR14_CAL_GAR_VAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAL_GAR15 - Calibration General A-Side Registers */
|
|
/*! @{ */
|
|
|
|
#define ADC_CAL_GAR15_CAL_GAR_VAL_MASK (0xFFFFU)
|
|
#define ADC_CAL_GAR15_CAL_GAR_VAL_SHIFT (0U)
|
|
/*! CAL_GAR_VAL - Calibration General A Side Register Element */
|
|
#define ADC_CAL_GAR15_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR15_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR15_CAL_GAR_VAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAL_GAR16 - Calibration General A-Side Registers */
|
|
/*! @{ */
|
|
|
|
#define ADC_CAL_GAR16_CAL_GAR_VAL_MASK (0xFFFFU)
|
|
#define ADC_CAL_GAR16_CAL_GAR_VAL_SHIFT (0U)
|
|
/*! CAL_GAR_VAL - Calibration General A Side Register Element */
|
|
#define ADC_CAL_GAR16_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR16_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR16_CAL_GAR_VAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAL_GAR17 - Calibration General A-Side Registers */
|
|
/*! @{ */
|
|
|
|
#define ADC_CAL_GAR17_CAL_GAR_VAL_MASK (0xFFFFU)
|
|
#define ADC_CAL_GAR17_CAL_GAR_VAL_SHIFT (0U)
|
|
/*! CAL_GAR_VAL - Calibration General A Side Register Element */
|
|
#define ADC_CAL_GAR17_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR17_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR17_CAL_GAR_VAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAL_GAR18 - Calibration General A-Side Registers */
|
|
/*! @{ */
|
|
|
|
#define ADC_CAL_GAR18_CAL_GAR_VAL_MASK (0xFFFFU)
|
|
#define ADC_CAL_GAR18_CAL_GAR_VAL_SHIFT (0U)
|
|
/*! CAL_GAR_VAL - Calibration General A Side Register Element */
|
|
#define ADC_CAL_GAR18_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR18_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR18_CAL_GAR_VAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAL_GAR19 - Calibration General A-Side Registers */
|
|
/*! @{ */
|
|
|
|
#define ADC_CAL_GAR19_CAL_GAR_VAL_MASK (0xFFFFU)
|
|
#define ADC_CAL_GAR19_CAL_GAR_VAL_SHIFT (0U)
|
|
/*! CAL_GAR_VAL - Calibration General A Side Register Element */
|
|
#define ADC_CAL_GAR19_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR19_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR19_CAL_GAR_VAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAL_GAR20 - Calibration General A-Side Registers */
|
|
/*! @{ */
|
|
|
|
#define ADC_CAL_GAR20_CAL_GAR_VAL_MASK (0xFFFFU)
|
|
#define ADC_CAL_GAR20_CAL_GAR_VAL_SHIFT (0U)
|
|
/*! CAL_GAR_VAL - Calibration General A Side Register Element */
|
|
#define ADC_CAL_GAR20_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR20_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR20_CAL_GAR_VAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAL_GAR21 - Calibration General A-Side Registers */
|
|
/*! @{ */
|
|
|
|
#define ADC_CAL_GAR21_CAL_GAR_VAL_MASK (0xFFFFU)
|
|
#define ADC_CAL_GAR21_CAL_GAR_VAL_SHIFT (0U)
|
|
/*! CAL_GAR_VAL - Calibration General A Side Register Element */
|
|
#define ADC_CAL_GAR21_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR21_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR21_CAL_GAR_VAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAL_GAR22 - Calibration General A-Side Registers */
|
|
/*! @{ */
|
|
|
|
#define ADC_CAL_GAR22_CAL_GAR_VAL_MASK (0xFFFFU)
|
|
#define ADC_CAL_GAR22_CAL_GAR_VAL_SHIFT (0U)
|
|
/*! CAL_GAR_VAL - Calibration General A Side Register Element */
|
|
#define ADC_CAL_GAR22_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR22_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR22_CAL_GAR_VAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAL_GAR23 - Calibration General A-Side Registers */
|
|
/*! @{ */
|
|
|
|
#define ADC_CAL_GAR23_CAL_GAR_VAL_MASK (0xFFFFU)
|
|
#define ADC_CAL_GAR23_CAL_GAR_VAL_SHIFT (0U)
|
|
/*! CAL_GAR_VAL - Calibration General A Side Register Element */
|
|
#define ADC_CAL_GAR23_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR23_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR23_CAL_GAR_VAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAL_GAR24 - Calibration General A-Side Registers */
|
|
/*! @{ */
|
|
|
|
#define ADC_CAL_GAR24_CAL_GAR_VAL_MASK (0xFFFFU)
|
|
#define ADC_CAL_GAR24_CAL_GAR_VAL_SHIFT (0U)
|
|
/*! CAL_GAR_VAL - Calibration General A Side Register Element */
|
|
#define ADC_CAL_GAR24_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR24_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR24_CAL_GAR_VAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAL_GAR25 - Calibration General A-Side Registers */
|
|
/*! @{ */
|
|
|
|
#define ADC_CAL_GAR25_CAL_GAR_VAL_MASK (0xFFFFU)
|
|
#define ADC_CAL_GAR25_CAL_GAR_VAL_SHIFT (0U)
|
|
/*! CAL_GAR_VAL - Calibration General A Side Register Element */
|
|
#define ADC_CAL_GAR25_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR25_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR25_CAL_GAR_VAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAL_GAR26 - Calibration General A-Side Registers */
|
|
/*! @{ */
|
|
|
|
#define ADC_CAL_GAR26_CAL_GAR_VAL_MASK (0xFFFFU)
|
|
#define ADC_CAL_GAR26_CAL_GAR_VAL_SHIFT (0U)
|
|
/*! CAL_GAR_VAL - Calibration General A Side Register Element */
|
|
#define ADC_CAL_GAR26_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR26_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR26_CAL_GAR_VAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAL_GAR27 - Calibration General A-Side Registers */
|
|
/*! @{ */
|
|
|
|
#define ADC_CAL_GAR27_CAL_GAR_VAL_MASK (0xFFFFU)
|
|
#define ADC_CAL_GAR27_CAL_GAR_VAL_SHIFT (0U)
|
|
/*! CAL_GAR_VAL - Calibration General A Side Register Element */
|
|
#define ADC_CAL_GAR27_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR27_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR27_CAL_GAR_VAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAL_GAR28 - Calibration General A-Side Registers */
|
|
/*! @{ */
|
|
|
|
#define ADC_CAL_GAR28_CAL_GAR_VAL_MASK (0xFFFFU)
|
|
#define ADC_CAL_GAR28_CAL_GAR_VAL_SHIFT (0U)
|
|
/*! CAL_GAR_VAL - Calibration General A Side Register Element */
|
|
#define ADC_CAL_GAR28_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR28_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR28_CAL_GAR_VAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAL_GAR29 - Calibration General A-Side Registers */
|
|
/*! @{ */
|
|
|
|
#define ADC_CAL_GAR29_CAL_GAR_VAL_MASK (0xFFFFU)
|
|
#define ADC_CAL_GAR29_CAL_GAR_VAL_SHIFT (0U)
|
|
/*! CAL_GAR_VAL - Calibration General A Side Register Element */
|
|
#define ADC_CAL_GAR29_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR29_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR29_CAL_GAR_VAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAL_GAR30 - Calibration General A-Side Registers */
|
|
/*! @{ */
|
|
|
|
#define ADC_CAL_GAR30_CAL_GAR_VAL_MASK (0xFFFFU)
|
|
#define ADC_CAL_GAR30_CAL_GAR_VAL_SHIFT (0U)
|
|
/*! CAL_GAR_VAL - Calibration General A Side Register Element */
|
|
#define ADC_CAL_GAR30_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR30_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR30_CAL_GAR_VAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAL_GAR31 - Calibration General A-Side Registers */
|
|
/*! @{ */
|
|
|
|
#define ADC_CAL_GAR31_CAL_GAR_VAL_MASK (0xFFFFU)
|
|
#define ADC_CAL_GAR31_CAL_GAR_VAL_SHIFT (0U)
|
|
/*! CAL_GAR_VAL - Calibration General A Side Register Element */
|
|
#define ADC_CAL_GAR31_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR31_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR31_CAL_GAR_VAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAL_GAR32 - Calibration General A-Side Registers */
|
|
/*! @{ */
|
|
|
|
#define ADC_CAL_GAR32_CAL_GAR_VAL_MASK (0xFFFFU)
|
|
#define ADC_CAL_GAR32_CAL_GAR_VAL_SHIFT (0U)
|
|
/*! CAL_GAR_VAL - Calibration General A Side Register Element */
|
|
#define ADC_CAL_GAR32_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR32_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR32_CAL_GAR_VAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CFG2 - Configuration 2 Register */
|
|
/*! @{ */
|
|
|
|
#define ADC_CFG2_JLEFT_MASK (0x100U)
|
|
#define ADC_CFG2_JLEFT_SHIFT (8U)
|
|
/*! JLEFT - Justified Left Enable register */
|
|
#define ADC_CFG2_JLEFT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_JLEFT_SHIFT)) & ADC_CFG2_JLEFT_MASK)
|
|
|
|
#define ADC_CFG2_HS_MASK (0x200U)
|
|
#define ADC_CFG2_HS_SHIFT (9U)
|
|
/*! HS - High Speed Enable register
|
|
* 0b0..High speed conversion mode disabled
|
|
* 0b1..High speed conversion mode enabled
|
|
*/
|
|
#define ADC_CFG2_HS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_HS_SHIFT)) & ADC_CFG2_HS_MASK)
|
|
|
|
#define ADC_CFG2_HSEXTRA_MASK (0x400U)
|
|
#define ADC_CFG2_HSEXTRA_SHIFT (10U)
|
|
/*! HSEXTRA - High Speed Extra register
|
|
* 0b0..No extra cycle added
|
|
* 0b1..Extra cycle added
|
|
*/
|
|
#define ADC_CFG2_HSEXTRA(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_HSEXTRA_SHIFT)) & ADC_CFG2_HSEXTRA_MASK)
|
|
|
|
#define ADC_CFG2_TUNE_MASK (0x3000U)
|
|
#define ADC_CFG2_TUNE_SHIFT (12U)
|
|
/*! TUNE - Tune Mode register */
|
|
#define ADC_CFG2_TUNE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_TUNE_SHIFT)) & ADC_CFG2_TUNE_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group ADC_Register_Masks */
|
|
|
|
|
|
/* ADC - Peripheral instance base addresses */
|
|
/** Peripheral ADC0 base address */
|
|
#define ADC0_BASE (0x400AF000u)
|
|
/** Peripheral ADC0 base pointer */
|
|
#define ADC0 ((ADC_Type *)ADC0_BASE)
|
|
/** Array initializer of ADC peripheral base addresses */
|
|
#define ADC_BASE_ADDRS { ADC0_BASE }
|
|
/** Array initializer of ADC peripheral base pointers */
|
|
#define ADC_BASE_PTRS { ADC0 }
|
|
/** Interrupt vectors for the ADC peripheral type */
|
|
#define ADC_IRQS { ADC0_IRQn }
|
|
/* Backward compatibility */
|
|
#define ADC_CTRL_RSTFIFO_MASK ADC_CTRL_RSTFIFO0_MASK
|
|
#define ADC_CTRL_RSTFIFO_SHIFT ADC_CTRL_RSTFIFO0_SHIFT
|
|
#define ADC_CTRL_RSTFIFO(x) ADC_CTRL_RSTFIFO0(x)
|
|
#define ADC_STAT_RDY_MASK ADC_STAT_RDY0_MASK
|
|
#define ADC_STAT_RDY_SHIFT ADC_STAT_RDY0_SHIFT
|
|
#define ADC_STAT_RDY(x) ADC_STAT_RDY0(x)
|
|
#define ADC_STAT_FOF_MASK ADC_STAT_FOF0_MASK
|
|
#define ADC_STAT_FOF_SHIFT ADC_STAT_FOF0_SHIFT
|
|
#define ADC_STAT_FOF(x) ADC_STAT_FOF0(x)
|
|
#define ADC_IE_FWMIE_MASK ADC_IE_FWMIE0_MASK
|
|
#define ADC_IE_FWMIE_SHIFT ADC_IE_FWMIE0_SHIFT
|
|
#define ADC_IE_FWMIE(x) ADC_IE_FWMIE0(x)
|
|
#define ADC_IE_FOFIE_MASK ADC_IE_FOFIE0_MASK
|
|
#define ADC_IE_FOFIE_SHIFT ADC_IE_FOFIE0_SHIFT
|
|
#define ADC_IE_FOFIE(x) ADC_IE_FOFIE0(x)
|
|
#define ADC_DE_FWMDE_MASK ADC_DE_FWMDE0_MASK
|
|
#define ADC_DE_FWMDE_SHIFT ADC_DE_FWMDE0_SHIFT
|
|
#define ADC_DE_FWMDE(x) ADC_DE_FWMDE0(x)
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group ADC_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- AOI Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup AOI_Peripheral_Access_Layer AOI Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** AOI - Register Layout Typedef */
|
|
typedef struct {
|
|
struct { /* offset: 0x0, array step: 0x4 */
|
|
__IO uint16_t BFCRT01; /**< Boolean Function Term 0 and 1 Configuration for EVENT0..Boolean Function Term 0 and 1 Configuration for EVENT3, array offset: 0x0, array step: 0x4 */
|
|
__IO uint16_t BFCRT23; /**< Boolean Function Term 2 and 3 Configuration for EVENT0..Boolean Function Term 2 and 3 Configuration for EVENT3, array offset: 0x2, array step: 0x4 */
|
|
} BFCRT[4];
|
|
} AOI_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- AOI Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup AOI_Register_Masks AOI Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name BFCRT01 - Boolean Function Term 0 and 1 Configuration for EVENT0..Boolean Function Term 0 and 1 Configuration for EVENT3 */
|
|
/*! @{ */
|
|
|
|
#define AOI_BFCRT01_PT1_DC_MASK (0x3U)
|
|
#define AOI_BFCRT01_PT1_DC_SHIFT (0U)
|
|
/*! PT1_DC - Product Term 1, Input D Configuration
|
|
* 0b00..Force input D to become 0
|
|
* 0b01..Pass input D
|
|
* 0b10..Complement input D
|
|
* 0b11..Force input D to become 1
|
|
*/
|
|
#define AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK)
|
|
|
|
#define AOI_BFCRT01_PT1_CC_MASK (0xCU)
|
|
#define AOI_BFCRT01_PT1_CC_SHIFT (2U)
|
|
/*! PT1_CC - Product Term 1, Input C Configuration
|
|
* 0b00..Force input C to become 0
|
|
* 0b01..Pass input C
|
|
* 0b10..Complement input C
|
|
* 0b11..Force input C to become 1
|
|
*/
|
|
#define AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK)
|
|
|
|
#define AOI_BFCRT01_PT1_BC_MASK (0x30U)
|
|
#define AOI_BFCRT01_PT1_BC_SHIFT (4U)
|
|
/*! PT1_BC - Product Term 1, Input B Configuration
|
|
* 0b00..Force input B to become 0
|
|
* 0b01..Pass input B
|
|
* 0b10..Complement input B
|
|
* 0b11..Force input B to become 1
|
|
*/
|
|
#define AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK)
|
|
|
|
#define AOI_BFCRT01_PT1_AC_MASK (0xC0U)
|
|
#define AOI_BFCRT01_PT1_AC_SHIFT (6U)
|
|
/*! PT1_AC - Product Term 1, Input A Configuration
|
|
* 0b00..Force input A to become 0
|
|
* 0b01..Pass input A
|
|
* 0b10..Complement input A
|
|
* 0b11..Force input A to become 1
|
|
*/
|
|
#define AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK)
|
|
|
|
#define AOI_BFCRT01_PT0_DC_MASK (0x300U)
|
|
#define AOI_BFCRT01_PT0_DC_SHIFT (8U)
|
|
/*! PT0_DC - Product Term 0, Input D Configuration
|
|
* 0b00..Force input D to become 0
|
|
* 0b01..Pass input D
|
|
* 0b10..Complement input D
|
|
* 0b11..Force input D to become 1
|
|
*/
|
|
#define AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK)
|
|
|
|
#define AOI_BFCRT01_PT0_CC_MASK (0xC00U)
|
|
#define AOI_BFCRT01_PT0_CC_SHIFT (10U)
|
|
/*! PT0_CC - Product Term 0, Input C Configuration
|
|
* 0b00..Force input C to become 0
|
|
* 0b01..Pass input C
|
|
* 0b10..Complement input C
|
|
* 0b11..Force input C to become 1
|
|
*/
|
|
#define AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK)
|
|
|
|
#define AOI_BFCRT01_PT0_BC_MASK (0x3000U)
|
|
#define AOI_BFCRT01_PT0_BC_SHIFT (12U)
|
|
/*! PT0_BC - Product Term 0, Input B Configuration
|
|
* 0b00..Force input B to become 0
|
|
* 0b01..Pass input B
|
|
* 0b10..Complement input B
|
|
* 0b11..Force input B to become 1
|
|
*/
|
|
#define AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK)
|
|
|
|
#define AOI_BFCRT01_PT0_AC_MASK (0xC000U)
|
|
#define AOI_BFCRT01_PT0_AC_SHIFT (14U)
|
|
/*! PT0_AC - Product Term 0, Input A Configuration
|
|
* 0b00..Force input A to become 0
|
|
* 0b01..Pass input A
|
|
* 0b10..Complement input A
|
|
* 0b11..Force input A to become 1
|
|
*/
|
|
#define AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of AOI_BFCRT01 */
|
|
#define AOI_BFCRT01_COUNT (4U)
|
|
|
|
/*! @name BFCRT23 - Boolean Function Term 2 and 3 Configuration for EVENT0..Boolean Function Term 2 and 3 Configuration for EVENT3 */
|
|
/*! @{ */
|
|
|
|
#define AOI_BFCRT23_PT3_DC_MASK (0x3U)
|
|
#define AOI_BFCRT23_PT3_DC_SHIFT (0U)
|
|
/*! PT3_DC - Product Term 3, Input D Configuration
|
|
* 0b00..Force input D to become 0
|
|
* 0b01..Pass input D
|
|
* 0b10..Complement input D
|
|
* 0b11..Force input D to become 1
|
|
*/
|
|
#define AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK)
|
|
|
|
#define AOI_BFCRT23_PT3_CC_MASK (0xCU)
|
|
#define AOI_BFCRT23_PT3_CC_SHIFT (2U)
|
|
/*! PT3_CC - Product Term 3, Input C Configuration
|
|
* 0b00..Force input C to become 0
|
|
* 0b01..Pass input C
|
|
* 0b10..Complement input C
|
|
* 0b11..Force input C to become 1
|
|
*/
|
|
#define AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK)
|
|
|
|
#define AOI_BFCRT23_PT3_BC_MASK (0x30U)
|
|
#define AOI_BFCRT23_PT3_BC_SHIFT (4U)
|
|
/*! PT3_BC - Product Term 3, Input B Configuration
|
|
* 0b00..Force input B to become 0
|
|
* 0b01..Pass input B
|
|
* 0b10..Complement input B
|
|
* 0b11..Force input B to become 1
|
|
*/
|
|
#define AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK)
|
|
|
|
#define AOI_BFCRT23_PT3_AC_MASK (0xC0U)
|
|
#define AOI_BFCRT23_PT3_AC_SHIFT (6U)
|
|
/*! PT3_AC - Product Term 3, Input A Configuration
|
|
* 0b00..Force input A to become 0
|
|
* 0b01..Pass input A
|
|
* 0b10..Complement input A
|
|
* 0b11..Force input to become 1
|
|
*/
|
|
#define AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK)
|
|
|
|
#define AOI_BFCRT23_PT2_DC_MASK (0x300U)
|
|
#define AOI_BFCRT23_PT2_DC_SHIFT (8U)
|
|
/*! PT2_DC - Product Term 2, Input D Configuration
|
|
* 0b00..Force input D to become 0
|
|
* 0b01..Pass input D
|
|
* 0b10..Complement input D
|
|
* 0b11..Force input D to become 1
|
|
*/
|
|
#define AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK)
|
|
|
|
#define AOI_BFCRT23_PT2_CC_MASK (0xC00U)
|
|
#define AOI_BFCRT23_PT2_CC_SHIFT (10U)
|
|
/*! PT2_CC - Product Term 2, Input C Configuration
|
|
* 0b00..Force input C to become 0
|
|
* 0b01..Pass input C
|
|
* 0b10..Complement input C
|
|
* 0b11..Force input C to become 1
|
|
*/
|
|
#define AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK)
|
|
|
|
#define AOI_BFCRT23_PT2_BC_MASK (0x3000U)
|
|
#define AOI_BFCRT23_PT2_BC_SHIFT (12U)
|
|
/*! PT2_BC - Product Term 2, Input B Configuration
|
|
* 0b00..Force input B to become 0
|
|
* 0b01..Pass input B
|
|
* 0b10..Complement input B
|
|
* 0b11..Force input B to become 1
|
|
*/
|
|
#define AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK)
|
|
|
|
#define AOI_BFCRT23_PT2_AC_MASK (0xC000U)
|
|
#define AOI_BFCRT23_PT2_AC_SHIFT (14U)
|
|
/*! PT2_AC - Product Term 2, Input A Configuration
|
|
* 0b00..Force input A to become 0
|
|
* 0b01..Pass input A
|
|
* 0b10..Complement input A
|
|
* 0b11..Force input A to become 1
|
|
*/
|
|
#define AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of AOI_BFCRT23 */
|
|
#define AOI_BFCRT23_COUNT (4U)
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group AOI_Register_Masks */
|
|
|
|
|
|
/* AOI - Peripheral instance base addresses */
|
|
/** Peripheral AOI0 base address */
|
|
#define AOI0_BASE (0x40089000u)
|
|
/** Peripheral AOI0 base pointer */
|
|
#define AOI0 ((AOI_Type *)AOI0_BASE)
|
|
/** Array initializer of AOI peripheral base addresses */
|
|
#define AOI_BASE_ADDRS { AOI0_BASE }
|
|
/** Array initializer of AOI peripheral base pointers */
|
|
#define AOI_BASE_PTRS { AOI0 }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group AOI_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- CDOG Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup CDOG_Peripheral_Access_Layer CDOG Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** CDOG - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t CONTROL; /**< Control Register, offset: 0x0 */
|
|
__IO uint32_t RELOAD; /**< Instruction Timer Reload Register, offset: 0x4 */
|
|
__I uint32_t INSTRUCTION_TIMER; /**< Instruction Timer Register, offset: 0x8 */
|
|
uint8_t RESERVED_0[4];
|
|
__I uint32_t STATUS; /**< Status 1 Register, offset: 0x10 */
|
|
__I uint32_t STATUS2; /**< Status 2 Register, offset: 0x14 */
|
|
__IO uint32_t FLAGS; /**< Flags Register, offset: 0x18 */
|
|
__IO uint32_t PERSISTENT; /**< Persistent Data Storage Register, offset: 0x1C */
|
|
__O uint32_t START; /**< START Command Register, offset: 0x20 */
|
|
__O uint32_t STOP; /**< STOP Command Register, offset: 0x24 */
|
|
__O uint32_t RESTART; /**< RESTART Command Register, offset: 0x28 */
|
|
__O uint32_t ADD; /**< ADD Command Register, offset: 0x2C */
|
|
__O uint32_t ADD1; /**< ADD1 Command Register, offset: 0x30 */
|
|
__O uint32_t ADD16; /**< ADD16 Command Register, offset: 0x34 */
|
|
__O uint32_t ADD256; /**< ADD256 Command Register, offset: 0x38 */
|
|
__O uint32_t SUB; /**< SUB Command Register, offset: 0x3C */
|
|
__O uint32_t SUB1; /**< SUB1 Command Register, offset: 0x40 */
|
|
__O uint32_t SUB16; /**< SUB16 Command Register, offset: 0x44 */
|
|
__O uint32_t SUB256; /**< SUB256 Command Register, offset: 0x48 */
|
|
__O uint32_t ASSERT16; /**< ASSERT16 Command Register, offset: 0x4C */
|
|
} CDOG_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- CDOG Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup CDOG_Register_Masks CDOG Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name CONTROL - Control Register */
|
|
/*! @{ */
|
|
|
|
#define CDOG_CONTROL_LOCK_CTRL_MASK (0x3U)
|
|
#define CDOG_CONTROL_LOCK_CTRL_SHIFT (0U)
|
|
/*! LOCK_CTRL - Lock control
|
|
* 0b01..Locked
|
|
* 0b10..Unlocked
|
|
*/
|
|
#define CDOG_CONTROL_LOCK_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_LOCK_CTRL_SHIFT)) & CDOG_CONTROL_LOCK_CTRL_MASK)
|
|
|
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#define CDOG_CONTROL_TIMEOUT_CTRL_MASK (0x1CU)
|
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#define CDOG_CONTROL_TIMEOUT_CTRL_SHIFT (2U)
|
|
/*! TIMEOUT_CTRL - TIMEOUT fault control
|
|
* 0b100..Disable both reset and interrupt
|
|
* 0b001..Enable reset
|
|
* 0b010..Enable interrupt
|
|
*/
|
|
#define CDOG_CONTROL_TIMEOUT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_TIMEOUT_CTRL_SHIFT)) & CDOG_CONTROL_TIMEOUT_CTRL_MASK)
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|
|
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#define CDOG_CONTROL_MISCOMPARE_CTRL_MASK (0xE0U)
|
|
#define CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT (5U)
|
|
/*! MISCOMPARE_CTRL - MISCOMPARE fault control
|
|
* 0b100..Disable both reset and interrupt
|
|
* 0b001..Enable reset
|
|
* 0b010..Enable interrupt
|
|
*/
|
|
#define CDOG_CONTROL_MISCOMPARE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT)) & CDOG_CONTROL_MISCOMPARE_CTRL_MASK)
|
|
|
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#define CDOG_CONTROL_SEQUENCE_CTRL_MASK (0x700U)
|
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#define CDOG_CONTROL_SEQUENCE_CTRL_SHIFT (8U)
|
|
/*! SEQUENCE_CTRL - SEQUENCE fault control
|
|
* 0b001..Enable reset
|
|
* 0b010..Enable interrupt
|
|
* 0b100..Disable both reset and interrupt
|
|
*/
|
|
#define CDOG_CONTROL_SEQUENCE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_SEQUENCE_CTRL_SHIFT)) & CDOG_CONTROL_SEQUENCE_CTRL_MASK)
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|
|
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#define CDOG_CONTROL_STATE_CTRL_MASK (0x1C000U)
|
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#define CDOG_CONTROL_STATE_CTRL_SHIFT (14U)
|
|
/*! STATE_CTRL - STATE fault control
|
|
* 0b001..Enable reset
|
|
* 0b010..Enable interrupt
|
|
* 0b100..Disable both reset and interrupt
|
|
*/
|
|
#define CDOG_CONTROL_STATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_STATE_CTRL_SHIFT)) & CDOG_CONTROL_STATE_CTRL_MASK)
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|
|
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#define CDOG_CONTROL_ADDRESS_CTRL_MASK (0xE0000U)
|
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#define CDOG_CONTROL_ADDRESS_CTRL_SHIFT (17U)
|
|
/*! ADDRESS_CTRL - ADDRESS fault control
|
|
* 0b001..Enable reset
|
|
* 0b010..Enable interrupt
|
|
* 0b100..Disable both reset and interrupt
|
|
*/
|
|
#define CDOG_CONTROL_ADDRESS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_ADDRESS_CTRL_SHIFT)) & CDOG_CONTROL_ADDRESS_CTRL_MASK)
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|
|
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#define CDOG_CONTROL_IRQ_PAUSE_MASK (0x30000000U)
|
|
#define CDOG_CONTROL_IRQ_PAUSE_SHIFT (28U)
|
|
/*! IRQ_PAUSE - IRQ pause control
|
|
* 0b01..Keep the timer running
|
|
* 0b10..Stop the timer
|
|
*/
|
|
#define CDOG_CONTROL_IRQ_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_IRQ_PAUSE_SHIFT)) & CDOG_CONTROL_IRQ_PAUSE_MASK)
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|
|
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#define CDOG_CONTROL_DEBUG_HALT_CTRL_MASK (0xC0000000U)
|
|
#define CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT (30U)
|
|
/*! DEBUG_HALT_CTRL - DEBUG_HALT control
|
|
* 0b01..Keep the timer running
|
|
* 0b10..Stop the timer
|
|
*/
|
|
#define CDOG_CONTROL_DEBUG_HALT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT)) & CDOG_CONTROL_DEBUG_HALT_CTRL_MASK)
|
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/*! @} */
|
|
|
|
/*! @name RELOAD - Instruction Timer Reload Register */
|
|
/*! @{ */
|
|
|
|
#define CDOG_RELOAD_RLOAD_MASK (0xFFFFFFFFU)
|
|
#define CDOG_RELOAD_RLOAD_SHIFT (0U)
|
|
/*! RLOAD - Instruction Timer reload value */
|
|
#define CDOG_RELOAD_RLOAD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RELOAD_RLOAD_SHIFT)) & CDOG_RELOAD_RLOAD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name INSTRUCTION_TIMER - Instruction Timer Register */
|
|
/*! @{ */
|
|
|
|
#define CDOG_INSTRUCTION_TIMER_INSTIM_MASK (0xFFFFFFFFU)
|
|
#define CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT (0U)
|
|
/*! INSTIM - Current value of the Instruction Timer */
|
|
#define CDOG_INSTRUCTION_TIMER_INSTIM(x) (((uint32_t)(((uint32_t)(x)) << CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT)) & CDOG_INSTRUCTION_TIMER_INSTIM_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name STATUS - Status 1 Register */
|
|
/*! @{ */
|
|
|
|
#define CDOG_STATUS_NUMTOF_MASK (0xFFU)
|
|
#define CDOG_STATUS_NUMTOF_SHIFT (0U)
|
|
/*! NUMTOF - Number of TIMEOUT faults since the last POR */
|
|
#define CDOG_STATUS_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMTOF_SHIFT)) & CDOG_STATUS_NUMTOF_MASK)
|
|
|
|
#define CDOG_STATUS_NUMMISCOMPF_MASK (0xFF00U)
|
|
#define CDOG_STATUS_NUMMISCOMPF_SHIFT (8U)
|
|
/*! NUMMISCOMPF - Number of MISCOMPARE faults since the last POR */
|
|
#define CDOG_STATUS_NUMMISCOMPF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMMISCOMPF_SHIFT)) & CDOG_STATUS_NUMMISCOMPF_MASK)
|
|
|
|
#define CDOG_STATUS_NUMILSEQF_MASK (0xFF0000U)
|
|
#define CDOG_STATUS_NUMILSEQF_SHIFT (16U)
|
|
/*! NUMILSEQF - Number of SEQUENCE faults since the last POR */
|
|
#define CDOG_STATUS_NUMILSEQF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMILSEQF_SHIFT)) & CDOG_STATUS_NUMILSEQF_MASK)
|
|
|
|
#define CDOG_STATUS_CURST_MASK (0xF0000000U)
|
|
#define CDOG_STATUS_CURST_SHIFT (28U)
|
|
/*! CURST - Current State */
|
|
#define CDOG_STATUS_CURST(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_CURST_SHIFT)) & CDOG_STATUS_CURST_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name STATUS2 - Status 2 Register */
|
|
/*! @{ */
|
|
|
|
#define CDOG_STATUS2_NUMCNTF_MASK (0xFFU)
|
|
#define CDOG_STATUS2_NUMCNTF_SHIFT (0U)
|
|
/*! NUMCNTF - Number of CONTROL faults since the last POR */
|
|
#define CDOG_STATUS2_NUMCNTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMCNTF_SHIFT)) & CDOG_STATUS2_NUMCNTF_MASK)
|
|
|
|
#define CDOG_STATUS2_NUMILLSTF_MASK (0xFF00U)
|
|
#define CDOG_STATUS2_NUMILLSTF_SHIFT (8U)
|
|
/*! NUMILLSTF - Number of STATE faults since the last POR */
|
|
#define CDOG_STATUS2_NUMILLSTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLSTF_SHIFT)) & CDOG_STATUS2_NUMILLSTF_MASK)
|
|
|
|
#define CDOG_STATUS2_NUMILLA_MASK (0xFF0000U)
|
|
#define CDOG_STATUS2_NUMILLA_SHIFT (16U)
|
|
/*! NUMILLA - Number of ADDRESS faults since the last POR */
|
|
#define CDOG_STATUS2_NUMILLA(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLA_SHIFT)) & CDOG_STATUS2_NUMILLA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FLAGS - Flags Register */
|
|
/*! @{ */
|
|
|
|
#define CDOG_FLAGS_TO_FLAG_MASK (0x1U)
|
|
#define CDOG_FLAGS_TO_FLAG_SHIFT (0U)
|
|
/*! TO_FLAG - TIMEOUT fault flag
|
|
* 0b0..A TIMEOUT fault has not occurred
|
|
* 0b1..A TIMEOUT fault has occurred
|
|
*/
|
|
#define CDOG_FLAGS_TO_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_TO_FLAG_SHIFT)) & CDOG_FLAGS_TO_FLAG_MASK)
|
|
|
|
#define CDOG_FLAGS_MISCOM_FLAG_MASK (0x2U)
|
|
#define CDOG_FLAGS_MISCOM_FLAG_SHIFT (1U)
|
|
/*! MISCOM_FLAG - MISCOMPARE fault flag
|
|
* 0b0..A MISCOMPARE fault has not occurred
|
|
* 0b1..A MISCOMPARE fault has occurred
|
|
*/
|
|
#define CDOG_FLAGS_MISCOM_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_MISCOM_FLAG_SHIFT)) & CDOG_FLAGS_MISCOM_FLAG_MASK)
|
|
|
|
#define CDOG_FLAGS_SEQ_FLAG_MASK (0x4U)
|
|
#define CDOG_FLAGS_SEQ_FLAG_SHIFT (2U)
|
|
/*! SEQ_FLAG - SEQUENCE fault flag
|
|
* 0b0..A SEQUENCE fault has not occurred
|
|
* 0b1..A SEQUENCE fault has occurred
|
|
*/
|
|
#define CDOG_FLAGS_SEQ_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_SEQ_FLAG_SHIFT)) & CDOG_FLAGS_SEQ_FLAG_MASK)
|
|
|
|
#define CDOG_FLAGS_CNT_FLAG_MASK (0x8U)
|
|
#define CDOG_FLAGS_CNT_FLAG_SHIFT (3U)
|
|
/*! CNT_FLAG - CONTROL fault flag
|
|
* 0b0..A CONTROL fault has not occurred
|
|
* 0b1..A CONTROL fault has occurred
|
|
*/
|
|
#define CDOG_FLAGS_CNT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_CNT_FLAG_SHIFT)) & CDOG_FLAGS_CNT_FLAG_MASK)
|
|
|
|
#define CDOG_FLAGS_STATE_FLAG_MASK (0x10U)
|
|
#define CDOG_FLAGS_STATE_FLAG_SHIFT (4U)
|
|
/*! STATE_FLAG - STATE fault flag
|
|
* 0b0..A STATE fault has not occurred
|
|
* 0b1..A STATE fault has occurred
|
|
*/
|
|
#define CDOG_FLAGS_STATE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_STATE_FLAG_SHIFT)) & CDOG_FLAGS_STATE_FLAG_MASK)
|
|
|
|
#define CDOG_FLAGS_ADDR_FLAG_MASK (0x20U)
|
|
#define CDOG_FLAGS_ADDR_FLAG_SHIFT (5U)
|
|
/*! ADDR_FLAG - ADDRESS fault flag
|
|
* 0b0..An ADDRESS fault has not occurred
|
|
* 0b1..An ADDRESS fault has occurred
|
|
*/
|
|
#define CDOG_FLAGS_ADDR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_ADDR_FLAG_SHIFT)) & CDOG_FLAGS_ADDR_FLAG_MASK)
|
|
|
|
#define CDOG_FLAGS_POR_FLAG_MASK (0x10000U)
|
|
#define CDOG_FLAGS_POR_FLAG_SHIFT (16U)
|
|
/*! POR_FLAG - Power-on reset flag
|
|
* 0b0..A Power-on reset event has not occurred
|
|
* 0b1..A Power-on reset event has occurred
|
|
*/
|
|
#define CDOG_FLAGS_POR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_POR_FLAG_SHIFT)) & CDOG_FLAGS_POR_FLAG_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PERSISTENT - Persistent Data Storage Register */
|
|
/*! @{ */
|
|
|
|
#define CDOG_PERSISTENT_PERSIS_MASK (0xFFFFFFFFU)
|
|
#define CDOG_PERSISTENT_PERSIS_SHIFT (0U)
|
|
/*! PERSIS - Persistent Storage */
|
|
#define CDOG_PERSISTENT_PERSIS(x) (((uint32_t)(((uint32_t)(x)) << CDOG_PERSISTENT_PERSIS_SHIFT)) & CDOG_PERSISTENT_PERSIS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name START - START Command Register */
|
|
/*! @{ */
|
|
|
|
#define CDOG_START_STRT_MASK (0xFFFFFFFFU)
|
|
#define CDOG_START_STRT_SHIFT (0U)
|
|
/*! STRT - Start command */
|
|
#define CDOG_START_STRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_START_STRT_SHIFT)) & CDOG_START_STRT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name STOP - STOP Command Register */
|
|
/*! @{ */
|
|
|
|
#define CDOG_STOP_STP_MASK (0xFFFFFFFFU)
|
|
#define CDOG_STOP_STP_SHIFT (0U)
|
|
/*! STP - Stop command */
|
|
#define CDOG_STOP_STP(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STOP_STP_SHIFT)) & CDOG_STOP_STP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RESTART - RESTART Command Register */
|
|
/*! @{ */
|
|
|
|
#define CDOG_RESTART_RSTRT_MASK (0xFFFFFFFFU)
|
|
#define CDOG_RESTART_RSTRT_SHIFT (0U)
|
|
/*! RSTRT - Restart command */
|
|
#define CDOG_RESTART_RSTRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RESTART_RSTRT_SHIFT)) & CDOG_RESTART_RSTRT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ADD - ADD Command Register */
|
|
/*! @{ */
|
|
|
|
#define CDOG_ADD_AD_MASK (0xFFFFFFFFU)
|
|
#define CDOG_ADD_AD_SHIFT (0U)
|
|
/*! AD - ADD Write Value */
|
|
#define CDOG_ADD_AD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD_AD_SHIFT)) & CDOG_ADD_AD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ADD1 - ADD1 Command Register */
|
|
/*! @{ */
|
|
|
|
#define CDOG_ADD1_AD1_MASK (0xFFFFFFFFU)
|
|
#define CDOG_ADD1_AD1_SHIFT (0U)
|
|
/*! AD1 - ADD 1 */
|
|
#define CDOG_ADD1_AD1(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD1_AD1_SHIFT)) & CDOG_ADD1_AD1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ADD16 - ADD16 Command Register */
|
|
/*! @{ */
|
|
|
|
#define CDOG_ADD16_AD16_MASK (0xFFFFFFFFU)
|
|
#define CDOG_ADD16_AD16_SHIFT (0U)
|
|
/*! AD16 - ADD 16 */
|
|
#define CDOG_ADD16_AD16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD16_AD16_SHIFT)) & CDOG_ADD16_AD16_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ADD256 - ADD256 Command Register */
|
|
/*! @{ */
|
|
|
|
#define CDOG_ADD256_AD256_MASK (0xFFFFFFFFU)
|
|
#define CDOG_ADD256_AD256_SHIFT (0U)
|
|
/*! AD256 - ADD 256 */
|
|
#define CDOG_ADD256_AD256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD256_AD256_SHIFT)) & CDOG_ADD256_AD256_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SUB - SUB Command Register */
|
|
/*! @{ */
|
|
|
|
#define CDOG_SUB_SB_MASK (0xFFFFFFFFU)
|
|
#define CDOG_SUB_SB_SHIFT (0U)
|
|
/*! SB - Subtract Write Value */
|
|
#define CDOG_SUB_SB(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_SB_SHIFT)) & CDOG_SUB_SB_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SUB1 - SUB1 Command Register */
|
|
/*! @{ */
|
|
|
|
#define CDOG_SUB1_SB1_MASK (0xFFFFFFFFU)
|
|
#define CDOG_SUB1_SB1_SHIFT (0U)
|
|
/*! SB1 - Subtract 1 */
|
|
#define CDOG_SUB1_SB1(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB1_SB1_SHIFT)) & CDOG_SUB1_SB1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SUB16 - SUB16 Command Register */
|
|
/*! @{ */
|
|
|
|
#define CDOG_SUB16_SB16_MASK (0xFFFFFFFFU)
|
|
#define CDOG_SUB16_SB16_SHIFT (0U)
|
|
/*! SB16 - Subtract 16 */
|
|
#define CDOG_SUB16_SB16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB16_SB16_SHIFT)) & CDOG_SUB16_SB16_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SUB256 - SUB256 Command Register */
|
|
/*! @{ */
|
|
|
|
#define CDOG_SUB256_SB256_MASK (0xFFFFFFFFU)
|
|
#define CDOG_SUB256_SB256_SHIFT (0U)
|
|
/*! SB256 - Subtract 256 */
|
|
#define CDOG_SUB256_SB256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB256_SB256_SHIFT)) & CDOG_SUB256_SB256_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ASSERT16 - ASSERT16 Command Register */
|
|
/*! @{ */
|
|
|
|
#define CDOG_ASSERT16_AST16_MASK (0xFFFFFFFFU)
|
|
#define CDOG_ASSERT16_AST16_SHIFT (0U)
|
|
/*! AST16 - ASSERT16 Command */
|
|
#define CDOG_ASSERT16_AST16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ASSERT16_AST16_SHIFT)) & CDOG_ASSERT16_AST16_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group CDOG_Register_Masks */
|
|
|
|
|
|
/* CDOG - Peripheral instance base addresses */
|
|
/** Peripheral CDOG base address */
|
|
#define CDOG_BASE (0x40100000u)
|
|
/** Peripheral CDOG base pointer */
|
|
#define CDOG ((CDOG_Type *)CDOG_BASE)
|
|
/** Array initializer of CDOG peripheral base addresses */
|
|
#define CDOG_BASE_ADDRS { CDOG_BASE }
|
|
/** Array initializer of CDOG peripheral base pointers */
|
|
#define CDOG_BASE_PTRS { CDOG }
|
|
/** Interrupt vectors for the CDOG peripheral type */
|
|
#define CDOG_IRQS { CDOG0_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group CDOG_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- CMC Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup CMC_Peripheral_Access_Layer CMC Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** CMC - Register Layout Typedef */
|
|
typedef struct {
|
|
__I uint32_t VERID; /**< Version ID, offset: 0x0 */
|
|
uint8_t RESERVED_0[12];
|
|
__IO uint32_t CKCTRL; /**< Clock Control, offset: 0x10 */
|
|
__IO uint32_t CKSTAT; /**< Clock Status, offset: 0x14 */
|
|
__IO uint32_t PMPROT; /**< Power Mode Protection, offset: 0x18 */
|
|
__O uint32_t GPMCTRL; /**< Global Power Mode Control, offset: 0x1C */
|
|
__IO uint32_t PMCTRL[1]; /**< Power Mode Control, array offset: 0x20, array step: 0x4 */
|
|
uint8_t RESERVED_1[92];
|
|
__I uint32_t SRS; /**< System Reset Status, offset: 0x80 */
|
|
__IO uint32_t RPC; /**< Reset Pin Control, offset: 0x84 */
|
|
__IO uint32_t SSRS; /**< Sticky System Reset Status, offset: 0x88 */
|
|
__IO uint32_t SRIE; /**< System Reset Interrupt Enable, offset: 0x8C */
|
|
__IO uint32_t SRIF; /**< System Reset Interrupt Flag, offset: 0x90 */
|
|
uint8_t RESERVED_2[8];
|
|
__I uint32_t RSTCNT; /**< Reset Count Register, offset: 0x9C */
|
|
__IO uint32_t MR[1]; /**< Mode, array offset: 0xA0, array step: 0x4 */
|
|
uint8_t RESERVED_3[12];
|
|
__IO uint32_t FM[1]; /**< Force Mode, array offset: 0xB0, array step: 0x4 */
|
|
uint8_t RESERVED_4[44];
|
|
__IO uint32_t FLASHCR; /**< Flash Control, offset: 0xE0 */
|
|
uint8_t RESERVED_5[44];
|
|
__IO uint32_t CORECTL; /**< Core Control, offset: 0x110 */
|
|
uint8_t RESERVED_6[12];
|
|
__IO uint32_t DBGCTL; /**< Debug Control, offset: 0x120 */
|
|
} CMC_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- CMC Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup CMC_Register_Masks CMC Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name VERID - Version ID */
|
|
/*! @{ */
|
|
|
|
#define CMC_VERID_FEATURE_MASK (0xFFFFU)
|
|
#define CMC_VERID_FEATURE_SHIFT (0U)
|
|
/*! FEATURE - Feature Specification Number */
|
|
#define CMC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << CMC_VERID_FEATURE_SHIFT)) & CMC_VERID_FEATURE_MASK)
|
|
|
|
#define CMC_VERID_MINOR_MASK (0xFF0000U)
|
|
#define CMC_VERID_MINOR_SHIFT (16U)
|
|
/*! MINOR - Minor Version Number */
|
|
#define CMC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << CMC_VERID_MINOR_SHIFT)) & CMC_VERID_MINOR_MASK)
|
|
|
|
#define CMC_VERID_MAJOR_MASK (0xFF000000U)
|
|
#define CMC_VERID_MAJOR_SHIFT (24U)
|
|
/*! MAJOR - Major Version Number */
|
|
#define CMC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << CMC_VERID_MAJOR_SHIFT)) & CMC_VERID_MAJOR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CKCTRL - Clock Control */
|
|
/*! @{ */
|
|
|
|
#define CMC_CKCTRL_CKMODE_MASK (0xFU)
|
|
#define CMC_CKCTRL_CKMODE_SHIFT (0U)
|
|
/*! CKMODE - Clocking Mode
|
|
* 0b0000..No clock gating
|
|
* 0b1111..Core, platform, and peripheral clocks are gated, and core enters Low-Power mode.
|
|
*/
|
|
#define CMC_CKCTRL_CKMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKCTRL_CKMODE_SHIFT)) & CMC_CKCTRL_CKMODE_MASK)
|
|
|
|
#define CMC_CKCTRL_LOCK_MASK (0x80000000U)
|
|
#define CMC_CKCTRL_LOCK_SHIFT (31U)
|
|
/*! LOCK - Lock
|
|
* 0b0..Allowed
|
|
* 0b1..Blocked
|
|
*/
|
|
#define CMC_CKCTRL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKCTRL_LOCK_SHIFT)) & CMC_CKCTRL_LOCK_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CKSTAT - Clock Status */
|
|
/*! @{ */
|
|
|
|
#define CMC_CKSTAT_CKMODE_MASK (0xFU)
|
|
#define CMC_CKSTAT_CKMODE_SHIFT (0U)
|
|
/*! CKMODE - Low Power Status
|
|
* 0b0000..Core clock not gated
|
|
* 0b1111..Core, platform, and peripheral clocks were gated, and power domain entered Low-Power mode
|
|
* *..
|
|
*/
|
|
#define CMC_CKSTAT_CKMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKSTAT_CKMODE_SHIFT)) & CMC_CKSTAT_CKMODE_MASK)
|
|
|
|
#define CMC_CKSTAT_WAKEUP_MASK (0xFF00U)
|
|
#define CMC_CKSTAT_WAKEUP_SHIFT (8U)
|
|
/*! WAKEUP - Wake-up Source */
|
|
#define CMC_CKSTAT_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKSTAT_WAKEUP_SHIFT)) & CMC_CKSTAT_WAKEUP_MASK)
|
|
|
|
#define CMC_CKSTAT_VALID_MASK (0x80000000U)
|
|
#define CMC_CKSTAT_VALID_SHIFT (31U)
|
|
/*! VALID - Clock Status Valid
|
|
* 0b0..Core clock not gated
|
|
* 0b1..Core clock was gated due to Low-Power mode entry
|
|
*/
|
|
#define CMC_CKSTAT_VALID(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKSTAT_VALID_SHIFT)) & CMC_CKSTAT_VALID_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PMPROT - Power Mode Protection */
|
|
/*! @{ */
|
|
|
|
#define CMC_PMPROT_LPMODE_MASK (0xFU)
|
|
#define CMC_PMPROT_LPMODE_SHIFT (0U)
|
|
/*! LPMODE - Low-Power Mode
|
|
* 0b0000..Not allowed
|
|
* 0b0001..Allowed
|
|
* 0b0010..Allowed
|
|
* 0b0011..Allowed
|
|
* 0b0100..Allowed
|
|
* 0b0101..Allowed
|
|
* 0b0110..Allowed
|
|
* 0b0111..Allowed
|
|
* 0b1000..Allowed
|
|
* 0b1001..Allowed
|
|
* 0b1010..Allowed
|
|
* 0b1011..Allowed
|
|
* 0b1100..Allowed
|
|
* 0b1101..Allowed
|
|
* 0b1110..Allowed
|
|
* 0b1111..Allowed
|
|
*/
|
|
#define CMC_PMPROT_LPMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_PMPROT_LPMODE_SHIFT)) & CMC_PMPROT_LPMODE_MASK)
|
|
|
|
#define CMC_PMPROT_LOCK_MASK (0x80000000U)
|
|
#define CMC_PMPROT_LOCK_SHIFT (31U)
|
|
/*! LOCK - Lock Register
|
|
* 0b0..Allowed
|
|
* 0b1..Blocked
|
|
*/
|
|
#define CMC_PMPROT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CMC_PMPROT_LOCK_SHIFT)) & CMC_PMPROT_LOCK_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GPMCTRL - Global Power Mode Control */
|
|
/*! @{ */
|
|
|
|
#define CMC_GPMCTRL_LPMODE_MASK (0xFU)
|
|
#define CMC_GPMCTRL_LPMODE_SHIFT (0U)
|
|
/*! LPMODE - Low-Power Mode */
|
|
#define CMC_GPMCTRL_LPMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_GPMCTRL_LPMODE_SHIFT)) & CMC_GPMCTRL_LPMODE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PMCTRL - Power Mode Control */
|
|
/*! @{ */
|
|
|
|
#define CMC_PMCTRL_LPMODE_MASK (0xFU)
|
|
#define CMC_PMCTRL_LPMODE_SHIFT (0U)
|
|
/*! LPMODE - Low-Power Mode
|
|
* 0b0000..Active/Sleep
|
|
* 0b0001..Deep Sleep
|
|
* 0b0011..Power Down
|
|
* 0b0111..Reserved
|
|
* 0b1111..Deep-Power Down
|
|
*/
|
|
#define CMC_PMCTRL_LPMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_PMCTRL_LPMODE_SHIFT)) & CMC_PMCTRL_LPMODE_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of CMC_PMCTRL */
|
|
#define CMC_PMCTRL_COUNT (1U)
|
|
|
|
/*! @name SRS - System Reset Status */
|
|
/*! @{ */
|
|
|
|
#define CMC_SRS_WAKEUP_MASK (0x1U)
|
|
#define CMC_SRS_WAKEUP_SHIFT (0U)
|
|
/*! WAKEUP - Wake-up Reset
|
|
* 0b0..Reset not generated
|
|
* 0b1..Reset generated
|
|
*/
|
|
#define CMC_SRS_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WAKEUP_SHIFT)) & CMC_SRS_WAKEUP_MASK)
|
|
|
|
#define CMC_SRS_POR_MASK (0x2U)
|
|
#define CMC_SRS_POR_SHIFT (1U)
|
|
/*! POR - Power-on Reset
|
|
* 0b0..Reset not generated
|
|
* 0b1..Reset generated
|
|
*/
|
|
#define CMC_SRS_POR(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_POR_SHIFT)) & CMC_SRS_POR_MASK)
|
|
|
|
#define CMC_SRS_VD_MASK (0x4U)
|
|
#define CMC_SRS_VD_SHIFT (2U)
|
|
/*! VD - Voltage Detect Reset
|
|
* 0b0..Reset not generated
|
|
* 0b1..Reset generated
|
|
*/
|
|
#define CMC_SRS_VD(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_VD_SHIFT)) & CMC_SRS_VD_MASK)
|
|
|
|
#define CMC_SRS_WARM_MASK (0x10U)
|
|
#define CMC_SRS_WARM_SHIFT (4U)
|
|
/*! WARM - Warm Reset
|
|
* 0b0..Reset not generated
|
|
* 0b1..Reset generated
|
|
*/
|
|
#define CMC_SRS_WARM(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WARM_SHIFT)) & CMC_SRS_WARM_MASK)
|
|
|
|
#define CMC_SRS_FATAL_MASK (0x20U)
|
|
#define CMC_SRS_FATAL_SHIFT (5U)
|
|
/*! FATAL - Fatal Reset
|
|
* 0b0..Reset was not generated
|
|
* 0b1..Reset was generated
|
|
*/
|
|
#define CMC_SRS_FATAL(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_FATAL_SHIFT)) & CMC_SRS_FATAL_MASK)
|
|
|
|
#define CMC_SRS_PIN_MASK (0x100U)
|
|
#define CMC_SRS_PIN_SHIFT (8U)
|
|
/*! PIN - Pin Reset
|
|
* 0b0..Reset was not generated
|
|
* 0b1..Reset was generated
|
|
*/
|
|
#define CMC_SRS_PIN(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_PIN_SHIFT)) & CMC_SRS_PIN_MASK)
|
|
|
|
#define CMC_SRS_DAP_MASK (0x200U)
|
|
#define CMC_SRS_DAP_SHIFT (9U)
|
|
/*! DAP - Debug Access Port Reset
|
|
* 0b0..Reset was not generated
|
|
* 0b1..Reset was generated
|
|
*/
|
|
#define CMC_SRS_DAP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_DAP_SHIFT)) & CMC_SRS_DAP_MASK)
|
|
|
|
#define CMC_SRS_RSTACK_MASK (0x400U)
|
|
#define CMC_SRS_RSTACK_SHIFT (10U)
|
|
/*! RSTACK - Reset Timeout
|
|
* 0b0..Reset not generated
|
|
* 0b1..Reset generated
|
|
*/
|
|
#define CMC_SRS_RSTACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_RSTACK_SHIFT)) & CMC_SRS_RSTACK_MASK)
|
|
|
|
#define CMC_SRS_LPACK_MASK (0x800U)
|
|
#define CMC_SRS_LPACK_SHIFT (11U)
|
|
/*! LPACK - Low Power Acknowledge Timeout Reset
|
|
* 0b0..Reset not generated
|
|
* 0b1..Reset generated
|
|
*/
|
|
#define CMC_SRS_LPACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_LPACK_SHIFT)) & CMC_SRS_LPACK_MASK)
|
|
|
|
#define CMC_SRS_SCG_MASK (0x1000U)
|
|
#define CMC_SRS_SCG_SHIFT (12U)
|
|
/*! SCG - System Clock Generation Reset
|
|
* 0b0..Reset is not generated
|
|
* 0b1..Reset is generated
|
|
*/
|
|
#define CMC_SRS_SCG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_SCG_SHIFT)) & CMC_SRS_SCG_MASK)
|
|
|
|
#define CMC_SRS_WWDT0_MASK (0x2000U)
|
|
#define CMC_SRS_WWDT0_SHIFT (13U)
|
|
/*! WWDT0 - Windowed Watchdog 0 Reset
|
|
* 0b0..Reset is not generated
|
|
* 0b1..Reset is generated
|
|
*/
|
|
#define CMC_SRS_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WWDT0_SHIFT)) & CMC_SRS_WWDT0_MASK)
|
|
|
|
#define CMC_SRS_SW_MASK (0x4000U)
|
|
#define CMC_SRS_SW_SHIFT (14U)
|
|
/*! SW - Software Reset
|
|
* 0b0..Reset not generated
|
|
* 0b1..Reset generated
|
|
*/
|
|
#define CMC_SRS_SW(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_SW_SHIFT)) & CMC_SRS_SW_MASK)
|
|
|
|
#define CMC_SRS_LOCKUP_MASK (0x8000U)
|
|
#define CMC_SRS_LOCKUP_SHIFT (15U)
|
|
/*! LOCKUP - Lockup Reset
|
|
* 0b0..Reset not generated
|
|
* 0b1..Reset generated
|
|
*/
|
|
#define CMC_SRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_LOCKUP_SHIFT)) & CMC_SRS_LOCKUP_MASK)
|
|
|
|
#define CMC_SRS_CDOG0_MASK (0x4000000U)
|
|
#define CMC_SRS_CDOG0_SHIFT (26U)
|
|
/*! CDOG0 - Code Watchdog 0 Reset
|
|
* 0b0..Reset is not generated
|
|
* 0b1..Reset is generated
|
|
*/
|
|
#define CMC_SRS_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_CDOG0_SHIFT)) & CMC_SRS_CDOG0_MASK)
|
|
|
|
#define CMC_SRS_JTAG_MASK (0x10000000U)
|
|
#define CMC_SRS_JTAG_SHIFT (28U)
|
|
/*! JTAG - JTAG System Reset
|
|
* 0b0..Reset not generated
|
|
* 0b1..Reset generated
|
|
*/
|
|
#define CMC_SRS_JTAG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_JTAG_SHIFT)) & CMC_SRS_JTAG_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RPC - Reset Pin Control */
|
|
/*! @{ */
|
|
|
|
#define CMC_RPC_FILTCFG_MASK (0x1FU)
|
|
#define CMC_RPC_FILTCFG_SHIFT (0U)
|
|
/*! FILTCFG - Reset Filter Configuration */
|
|
#define CMC_RPC_FILTCFG(x) (((uint32_t)(((uint32_t)(x)) << CMC_RPC_FILTCFG_SHIFT)) & CMC_RPC_FILTCFG_MASK)
|
|
|
|
#define CMC_RPC_FILTEN_MASK (0x100U)
|
|
#define CMC_RPC_FILTEN_SHIFT (8U)
|
|
/*! FILTEN - Filter Enable
|
|
* 0b0..Disables
|
|
* 0b1..Enables
|
|
*/
|
|
#define CMC_RPC_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << CMC_RPC_FILTEN_SHIFT)) & CMC_RPC_FILTEN_MASK)
|
|
|
|
#define CMC_RPC_LPFEN_MASK (0x200U)
|
|
#define CMC_RPC_LPFEN_SHIFT (9U)
|
|
/*! LPFEN - Low-Power Filter Enable
|
|
* 0b0..Disables
|
|
* 0b1..Enables
|
|
*/
|
|
#define CMC_RPC_LPFEN(x) (((uint32_t)(((uint32_t)(x)) << CMC_RPC_LPFEN_SHIFT)) & CMC_RPC_LPFEN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SSRS - Sticky System Reset Status */
|
|
/*! @{ */
|
|
|
|
#define CMC_SSRS_WAKEUP_MASK (0x1U)
|
|
#define CMC_SSRS_WAKEUP_SHIFT (0U)
|
|
/*! WAKEUP - Wake-up Reset
|
|
* 0b0..Reset not generated
|
|
* 0b1..Reset generated
|
|
*/
|
|
#define CMC_SSRS_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WAKEUP_SHIFT)) & CMC_SSRS_WAKEUP_MASK)
|
|
|
|
#define CMC_SSRS_POR_MASK (0x2U)
|
|
#define CMC_SSRS_POR_SHIFT (1U)
|
|
/*! POR - Power-on Reset
|
|
* 0b0..Reset not generated
|
|
* 0b1..Reset generated
|
|
*/
|
|
#define CMC_SSRS_POR(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_POR_SHIFT)) & CMC_SSRS_POR_MASK)
|
|
|
|
#define CMC_SSRS_VD_MASK (0x4U)
|
|
#define CMC_SSRS_VD_SHIFT (2U)
|
|
/*! VD - Voltage Detect Reset
|
|
* 0b0..Reset not generated
|
|
* 0b1..Reset generated
|
|
*/
|
|
#define CMC_SSRS_VD(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_VD_SHIFT)) & CMC_SSRS_VD_MASK)
|
|
|
|
#define CMC_SSRS_WARM_MASK (0x10U)
|
|
#define CMC_SSRS_WARM_SHIFT (4U)
|
|
/*! WARM - Warm Reset
|
|
* 0b0..Reset not generated
|
|
* 0b1..Reset generated
|
|
*/
|
|
#define CMC_SSRS_WARM(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WARM_SHIFT)) & CMC_SSRS_WARM_MASK)
|
|
|
|
#define CMC_SSRS_FATAL_MASK (0x20U)
|
|
#define CMC_SSRS_FATAL_SHIFT (5U)
|
|
/*! FATAL - Fatal Reset
|
|
* 0b0..Reset was not generated
|
|
* 0b1..Reset was generated
|
|
*/
|
|
#define CMC_SSRS_FATAL(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_FATAL_SHIFT)) & CMC_SSRS_FATAL_MASK)
|
|
|
|
#define CMC_SSRS_PIN_MASK (0x100U)
|
|
#define CMC_SSRS_PIN_SHIFT (8U)
|
|
/*! PIN - Pin Reset
|
|
* 0b0..Reset not generated
|
|
* 0b1..Reset generated
|
|
*/
|
|
#define CMC_SSRS_PIN(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_PIN_SHIFT)) & CMC_SSRS_PIN_MASK)
|
|
|
|
#define CMC_SSRS_DAP_MASK (0x200U)
|
|
#define CMC_SSRS_DAP_SHIFT (9U)
|
|
/*! DAP - DAP Reset
|
|
* 0b0..Reset not generated
|
|
* 0b1..Reset generated
|
|
*/
|
|
#define CMC_SSRS_DAP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_DAP_SHIFT)) & CMC_SSRS_DAP_MASK)
|
|
|
|
#define CMC_SSRS_RSTACK_MASK (0x400U)
|
|
#define CMC_SSRS_RSTACK_SHIFT (10U)
|
|
/*! RSTACK - Reset Timeout
|
|
* 0b0..Reset not generated
|
|
* 0b1..Reset generated
|
|
*/
|
|
#define CMC_SSRS_RSTACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_RSTACK_SHIFT)) & CMC_SSRS_RSTACK_MASK)
|
|
|
|
#define CMC_SSRS_LPACK_MASK (0x800U)
|
|
#define CMC_SSRS_LPACK_SHIFT (11U)
|
|
/*! LPACK - Low Power Acknowledge Timeout Reset
|
|
* 0b0..Reset not generated
|
|
* 0b1..Reset generated
|
|
*/
|
|
#define CMC_SSRS_LPACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_LPACK_SHIFT)) & CMC_SSRS_LPACK_MASK)
|
|
|
|
#define CMC_SSRS_SCG_MASK (0x1000U)
|
|
#define CMC_SSRS_SCG_SHIFT (12U)
|
|
/*! SCG - System Clock Generation Reset
|
|
* 0b0..Reset is not generated
|
|
* 0b1..Reset is generated
|
|
*/
|
|
#define CMC_SSRS_SCG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_SCG_SHIFT)) & CMC_SSRS_SCG_MASK)
|
|
|
|
#define CMC_SSRS_WWDT0_MASK (0x2000U)
|
|
#define CMC_SSRS_WWDT0_SHIFT (13U)
|
|
/*! WWDT0 - Windowed Watchdog 0 Reset
|
|
* 0b0..Reset is not generated
|
|
* 0b1..Reset is generated
|
|
*/
|
|
#define CMC_SSRS_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WWDT0_SHIFT)) & CMC_SSRS_WWDT0_MASK)
|
|
|
|
#define CMC_SSRS_SW_MASK (0x4000U)
|
|
#define CMC_SSRS_SW_SHIFT (14U)
|
|
/*! SW - Software Reset
|
|
* 0b0..Reset not generated
|
|
* 0b1..Reset generated
|
|
*/
|
|
#define CMC_SSRS_SW(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_SW_SHIFT)) & CMC_SSRS_SW_MASK)
|
|
|
|
#define CMC_SSRS_LOCKUP_MASK (0x8000U)
|
|
#define CMC_SSRS_LOCKUP_SHIFT (15U)
|
|
/*! LOCKUP - Lockup Reset
|
|
* 0b0..Reset not generated
|
|
* 0b1..Reset generated
|
|
*/
|
|
#define CMC_SSRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_LOCKUP_SHIFT)) & CMC_SSRS_LOCKUP_MASK)
|
|
|
|
#define CMC_SSRS_CDOG0_MASK (0x4000000U)
|
|
#define CMC_SSRS_CDOG0_SHIFT (26U)
|
|
/*! CDOG0 - Code Watchdog 0 Reset
|
|
* 0b0..Reset is not generated
|
|
* 0b1..Reset is generated
|
|
*/
|
|
#define CMC_SSRS_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_CDOG0_SHIFT)) & CMC_SSRS_CDOG0_MASK)
|
|
|
|
#define CMC_SSRS_JTAG_MASK (0x10000000U)
|
|
#define CMC_SSRS_JTAG_SHIFT (28U)
|
|
/*! JTAG - JTAG System Reset
|
|
* 0b0..Reset not generated
|
|
* 0b1..Reset generated
|
|
*/
|
|
#define CMC_SSRS_JTAG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_JTAG_SHIFT)) & CMC_SSRS_JTAG_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SRIE - System Reset Interrupt Enable */
|
|
/*! @{ */
|
|
|
|
#define CMC_SRIE_PIN_MASK (0x100U)
|
|
#define CMC_SRIE_PIN_SHIFT (8U)
|
|
/*! PIN - Pin Reset
|
|
* 0b0..Interrupt disabled
|
|
* 0b1..Interrupt enabled
|
|
*/
|
|
#define CMC_SRIE_PIN(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_PIN_SHIFT)) & CMC_SRIE_PIN_MASK)
|
|
|
|
#define CMC_SRIE_DAP_MASK (0x200U)
|
|
#define CMC_SRIE_DAP_SHIFT (9U)
|
|
/*! DAP - DAP Reset
|
|
* 0b0..Interrupt disabled
|
|
* 0b1..Interrupt enabled
|
|
*/
|
|
#define CMC_SRIE_DAP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_DAP_SHIFT)) & CMC_SRIE_DAP_MASK)
|
|
|
|
#define CMC_SRIE_LPACK_MASK (0x800U)
|
|
#define CMC_SRIE_LPACK_SHIFT (11U)
|
|
/*! LPACK - Low Power Acknowledge Timeout Reset
|
|
* 0b0..Interrupt disabled
|
|
* 0b1..Interrupt enabled
|
|
*/
|
|
#define CMC_SRIE_LPACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_LPACK_SHIFT)) & CMC_SRIE_LPACK_MASK)
|
|
|
|
#define CMC_SRIE_SCG_MASK (0x1000U)
|
|
#define CMC_SRIE_SCG_SHIFT (12U)
|
|
/*! SCG - System Clock Generation Reset
|
|
* 0b0..Interrupt disabled
|
|
* 0b1..Interrupt enabled
|
|
*/
|
|
#define CMC_SRIE_SCG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_SCG_SHIFT)) & CMC_SRIE_SCG_MASK)
|
|
|
|
#define CMC_SRIE_WWDT0_MASK (0x2000U)
|
|
#define CMC_SRIE_WWDT0_SHIFT (13U)
|
|
/*! WWDT0 - Windowed Watchdog 0 Reset
|
|
* 0b0..Interrupt disabled
|
|
* 0b1..Interrupt enabled
|
|
*/
|
|
#define CMC_SRIE_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_WWDT0_SHIFT)) & CMC_SRIE_WWDT0_MASK)
|
|
|
|
#define CMC_SRIE_SW_MASK (0x4000U)
|
|
#define CMC_SRIE_SW_SHIFT (14U)
|
|
/*! SW - Software Reset
|
|
* 0b0..Interrupt disabled
|
|
* 0b1..Interrupt enabled
|
|
*/
|
|
#define CMC_SRIE_SW(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_SW_SHIFT)) & CMC_SRIE_SW_MASK)
|
|
|
|
#define CMC_SRIE_LOCKUP_MASK (0x8000U)
|
|
#define CMC_SRIE_LOCKUP_SHIFT (15U)
|
|
/*! LOCKUP - Lockup Reset
|
|
* 0b0..Interrupt disabled
|
|
* 0b1..Interrupt enabled
|
|
*/
|
|
#define CMC_SRIE_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_LOCKUP_SHIFT)) & CMC_SRIE_LOCKUP_MASK)
|
|
|
|
#define CMC_SRIE_CDOG0_MASK (0x4000000U)
|
|
#define CMC_SRIE_CDOG0_SHIFT (26U)
|
|
/*! CDOG0 - Code Watchdog 0 Reset
|
|
* 0b0..Interrupt disabled
|
|
* 0b1..Interrupt enabled
|
|
*/
|
|
#define CMC_SRIE_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_CDOG0_SHIFT)) & CMC_SRIE_CDOG0_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SRIF - System Reset Interrupt Flag */
|
|
/*! @{ */
|
|
|
|
#define CMC_SRIF_PIN_MASK (0x100U)
|
|
#define CMC_SRIF_PIN_SHIFT (8U)
|
|
/*! PIN - Pin Reset
|
|
* 0b0..Reset source not pending
|
|
* 0b1..Reset source pending
|
|
*/
|
|
#define CMC_SRIF_PIN(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_PIN_SHIFT)) & CMC_SRIF_PIN_MASK)
|
|
|
|
#define CMC_SRIF_DAP_MASK (0x200U)
|
|
#define CMC_SRIF_DAP_SHIFT (9U)
|
|
/*! DAP - DAP Reset
|
|
* 0b0..Reset source not pending
|
|
* 0b1..Reset source pending
|
|
*/
|
|
#define CMC_SRIF_DAP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_DAP_SHIFT)) & CMC_SRIF_DAP_MASK)
|
|
|
|
#define CMC_SRIF_LPACK_MASK (0x800U)
|
|
#define CMC_SRIF_LPACK_SHIFT (11U)
|
|
/*! LPACK - Low Power Acknowledge Timeout Reset
|
|
* 0b0..Reset source not pending
|
|
* 0b1..Reset source pending
|
|
*/
|
|
#define CMC_SRIF_LPACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_LPACK_SHIFT)) & CMC_SRIF_LPACK_MASK)
|
|
|
|
#define CMC_SRIF_WWDT0_MASK (0x2000U)
|
|
#define CMC_SRIF_WWDT0_SHIFT (13U)
|
|
/*! WWDT0 - Windowed Watchdog 0 Reset
|
|
* 0b0..Reset source not pending
|
|
* 0b1..Reset source pending
|
|
*/
|
|
#define CMC_SRIF_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_WWDT0_SHIFT)) & CMC_SRIF_WWDT0_MASK)
|
|
|
|
#define CMC_SRIF_SW_MASK (0x4000U)
|
|
#define CMC_SRIF_SW_SHIFT (14U)
|
|
/*! SW - Software Reset
|
|
* 0b0..Reset source not pending
|
|
* 0b1..Reset source pending
|
|
*/
|
|
#define CMC_SRIF_SW(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_SW_SHIFT)) & CMC_SRIF_SW_MASK)
|
|
|
|
#define CMC_SRIF_LOCKUP_MASK (0x8000U)
|
|
#define CMC_SRIF_LOCKUP_SHIFT (15U)
|
|
/*! LOCKUP - Lockup Reset
|
|
* 0b0..Reset source not pending
|
|
* 0b1..Reset source pending
|
|
*/
|
|
#define CMC_SRIF_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_LOCKUP_SHIFT)) & CMC_SRIF_LOCKUP_MASK)
|
|
|
|
#define CMC_SRIF_CDOG0_MASK (0x4000000U)
|
|
#define CMC_SRIF_CDOG0_SHIFT (26U)
|
|
/*! CDOG0 - Code Watchdog 0 Reset
|
|
* 0b0..Reset source not pending
|
|
* 0b1..Reset source pending
|
|
*/
|
|
#define CMC_SRIF_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_CDOG0_SHIFT)) & CMC_SRIF_CDOG0_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RSTCNT - Reset Count Register */
|
|
/*! @{ */
|
|
|
|
#define CMC_RSTCNT_COUNT_MASK (0xFFU)
|
|
#define CMC_RSTCNT_COUNT_SHIFT (0U)
|
|
/*! COUNT - Count */
|
|
#define CMC_RSTCNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CMC_RSTCNT_COUNT_SHIFT)) & CMC_RSTCNT_COUNT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MR - Mode */
|
|
/*! @{ */
|
|
|
|
#define CMC_MR_ISPMODE_n_MASK (0x1U)
|
|
#define CMC_MR_ISPMODE_n_SHIFT (0U)
|
|
/*! ISPMODE_n - In System Programming Mode */
|
|
#define CMC_MR_ISPMODE_n(x) (((uint32_t)(((uint32_t)(x)) << CMC_MR_ISPMODE_n_SHIFT)) & CMC_MR_ISPMODE_n_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of CMC_MR */
|
|
#define CMC_MR_COUNT (1U)
|
|
|
|
/*! @name FM - Force Mode */
|
|
/*! @{ */
|
|
|
|
#define CMC_FM_FORCECFG_MASK (0x1U)
|
|
#define CMC_FM_FORCECFG_SHIFT (0U)
|
|
/*! FORCECFG - Boot Configuration
|
|
* 0b0..No effect
|
|
* 0b1..Asserts
|
|
*/
|
|
#define CMC_FM_FORCECFG(x) (((uint32_t)(((uint32_t)(x)) << CMC_FM_FORCECFG_SHIFT)) & CMC_FM_FORCECFG_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of CMC_FM */
|
|
#define CMC_FM_COUNT (1U)
|
|
|
|
/*! @name FLASHCR - Flash Control */
|
|
/*! @{ */
|
|
|
|
#define CMC_FLASHCR_FLASHDIS_MASK (0x1U)
|
|
#define CMC_FLASHCR_FLASHDIS_SHIFT (0U)
|
|
/*! FLASHDIS - Flash Disable
|
|
* 0b0..No effect
|
|
* 0b1..Flash memory is disabled
|
|
*/
|
|
#define CMC_FLASHCR_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << CMC_FLASHCR_FLASHDIS_SHIFT)) & CMC_FLASHCR_FLASHDIS_MASK)
|
|
|
|
#define CMC_FLASHCR_FLASHDOZE_MASK (0x2U)
|
|
#define CMC_FLASHCR_FLASHDOZE_SHIFT (1U)
|
|
/*! FLASHDOZE - Flash Doze
|
|
* 0b0..No effect
|
|
* 0b1..Flash memory is disabled when core is sleeping (CKMODE > 0)
|
|
*/
|
|
#define CMC_FLASHCR_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << CMC_FLASHCR_FLASHDOZE_SHIFT)) & CMC_FLASHCR_FLASHDOZE_MASK)
|
|
|
|
#define CMC_FLASHCR_FLASHWAKE_MASK (0x4U)
|
|
#define CMC_FLASHCR_FLASHWAKE_SHIFT (2U)
|
|
/*! FLASHWAKE - Flash Wake
|
|
* 0b0..No effect
|
|
* 0b1..Flash memory is not disabled during flash memory accesses
|
|
*/
|
|
#define CMC_FLASHCR_FLASHWAKE(x) (((uint32_t)(((uint32_t)(x)) << CMC_FLASHCR_FLASHWAKE_SHIFT)) & CMC_FLASHCR_FLASHWAKE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CORECTL - Core Control */
|
|
/*! @{ */
|
|
|
|
#define CMC_CORECTL_NPIE_MASK (0x1U)
|
|
#define CMC_CORECTL_NPIE_SHIFT (0U)
|
|
/*! NPIE - Non-maskable Pin Interrupt Enable
|
|
* 0b0..Disables
|
|
* 0b1..Enables
|
|
*/
|
|
#define CMC_CORECTL_NPIE(x) (((uint32_t)(((uint32_t)(x)) << CMC_CORECTL_NPIE_SHIFT)) & CMC_CORECTL_NPIE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DBGCTL - Debug Control */
|
|
/*! @{ */
|
|
|
|
#define CMC_DBGCTL_SOD_MASK (0x1U)
|
|
#define CMC_DBGCTL_SOD_SHIFT (0U)
|
|
/*! SOD - Sleep Or Debug
|
|
* 0b0..Remains enabled
|
|
* 0b1..Disabled
|
|
*/
|
|
#define CMC_DBGCTL_SOD(x) (((uint32_t)(((uint32_t)(x)) << CMC_DBGCTL_SOD_SHIFT)) & CMC_DBGCTL_SOD_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group CMC_Register_Masks */
|
|
|
|
|
|
/* CMC - Peripheral instance base addresses */
|
|
/** Peripheral CMC base address */
|
|
#define CMC_BASE (0x4008B000u)
|
|
/** Peripheral CMC base pointer */
|
|
#define CMC ((CMC_Type *)CMC_BASE)
|
|
/** Array initializer of CMC peripheral base addresses */
|
|
#define CMC_BASE_ADDRS { CMC_BASE }
|
|
/** Array initializer of CMC peripheral base pointers */
|
|
#define CMC_BASE_PTRS { CMC }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group CMC_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- CRC Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** CRC - Register Layout Typedef */
|
|
typedef struct {
|
|
union { /* offset: 0x0 */
|
|
struct { /* offset: 0x0 */
|
|
__IO uint8_t DATALL; /**< CRC_DATALL register, offset: 0x0 */
|
|
__IO uint8_t DATALU; /**< CRC_DATALU register, offset: 0x1 */
|
|
__IO uint8_t DATAHL; /**< CRC_DATAHL register, offset: 0x2 */
|
|
__IO uint8_t DATAHU; /**< CRC_DATAHU register, offset: 0x3 */
|
|
} ACCESS8BIT;
|
|
struct { /* offset: 0x0 */
|
|
__IO uint16_t DATAL; /**< CRC_DATAL register, offset: 0x0 */
|
|
__IO uint16_t DATAH; /**< CRC_DATAH register, offset: 0x2 */
|
|
} ACCESS16BIT;
|
|
__IO uint32_t DATA; /**< CRC Data, offset: 0x0 */
|
|
};
|
|
union { /* offset: 0x4 */
|
|
struct { /* offset: 0x4 */
|
|
__IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register, offset: 0x4 */
|
|
__IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register, offset: 0x5 */
|
|
__IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register, offset: 0x6 */
|
|
__IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register, offset: 0x7 */
|
|
} GPOLY_ACCESS8BIT;
|
|
struct { /* offset: 0x4 */
|
|
__IO uint16_t GPOLYL; /**< CRC_GPOLYL register, offset: 0x4 */
|
|
__IO uint16_t GPOLYH; /**< CRC_GPOLYH register, offset: 0x6 */
|
|
} GPOLY_ACCESS16BIT;
|
|
__IO uint32_t GPOLY; /**< CRC Polynomial, offset: 0x4 */
|
|
};
|
|
union { /* offset: 0x8 */
|
|
struct { /* offset: 0x8 */
|
|
uint8_t RESERVED_0[3];
|
|
__IO uint8_t CTRLHU; /**< CRC_CTRLHU register, offset: 0xB */
|
|
} CTRL_ACCESS8BIT;
|
|
__IO uint32_t CTRL; /**< CRC Control, offset: 0x8 */
|
|
};
|
|
} CRC_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- CRC Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup CRC_Register_Masks CRC Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name DATALL - CRC_DATALL register */
|
|
/*! @{ */
|
|
|
|
#define CRC_DATALL_DATALL_MASK (0xFFU)
|
|
#define CRC_DATALL_DATALL_SHIFT (0U)
|
|
#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DATALU - CRC_DATALU register */
|
|
/*! @{ */
|
|
|
|
#define CRC_DATALU_DATALU_MASK (0xFFU)
|
|
#define CRC_DATALU_DATALU_SHIFT (0U)
|
|
#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DATAHL - CRC_DATAHL register */
|
|
/*! @{ */
|
|
|
|
#define CRC_DATAHL_DATAHL_MASK (0xFFU)
|
|
#define CRC_DATAHL_DATAHL_SHIFT (0U)
|
|
#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DATAHU - CRC_DATAHU register */
|
|
/*! @{ */
|
|
|
|
#define CRC_DATAHU_DATAHU_MASK (0xFFU)
|
|
#define CRC_DATAHU_DATAHU_SHIFT (0U)
|
|
#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DATAL - CRC_DATAL register */
|
|
/*! @{ */
|
|
|
|
#define CRC_DATAL_DATAL_MASK (0xFFFFU)
|
|
#define CRC_DATAL_DATAL_SHIFT (0U)
|
|
#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DATAH - CRC_DATAH register */
|
|
/*! @{ */
|
|
|
|
#define CRC_DATAH_DATAH_MASK (0xFFFFU)
|
|
#define CRC_DATAH_DATAH_SHIFT (0U)
|
|
#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DATA - CRC Data */
|
|
/*! @{ */
|
|
|
|
#define CRC_DATA_LL_MASK (0xFFU)
|
|
#define CRC_DATA_LL_SHIFT (0U)
|
|
/*! LL - CRC Low Lower Byte */
|
|
#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
|
|
|
|
#define CRC_DATA_LU_MASK (0xFF00U)
|
|
#define CRC_DATA_LU_SHIFT (8U)
|
|
/*! LU - CRC Low Upper Byte */
|
|
#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
|
|
|
|
#define CRC_DATA_HL_MASK (0xFF0000U)
|
|
#define CRC_DATA_HL_SHIFT (16U)
|
|
/*! HL - CRC High Lower Byte */
|
|
#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
|
|
|
|
#define CRC_DATA_HU_MASK (0xFF000000U)
|
|
#define CRC_DATA_HU_SHIFT (24U)
|
|
/*! HU - CRC High Upper Byte */
|
|
#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GPOLYLL - CRC_GPOLYLL register */
|
|
/*! @{ */
|
|
|
|
#define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU)
|
|
#define CRC_GPOLYLL_GPOLYLL_SHIFT (0U)
|
|
#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GPOLYLU - CRC_GPOLYLU register */
|
|
/*! @{ */
|
|
|
|
#define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU)
|
|
#define CRC_GPOLYLU_GPOLYLU_SHIFT (0U)
|
|
#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GPOLYHL - CRC_GPOLYHL register */
|
|
/*! @{ */
|
|
|
|
#define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU)
|
|
#define CRC_GPOLYHL_GPOLYHL_SHIFT (0U)
|
|
#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GPOLYHU - CRC_GPOLYHU register */
|
|
/*! @{ */
|
|
|
|
#define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU)
|
|
#define CRC_GPOLYHU_GPOLYHU_SHIFT (0U)
|
|
#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GPOLYL - CRC_GPOLYL register */
|
|
/*! @{ */
|
|
|
|
#define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU)
|
|
#define CRC_GPOLYL_GPOLYL_SHIFT (0U)
|
|
#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GPOLYH - CRC_GPOLYH register */
|
|
/*! @{ */
|
|
|
|
#define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU)
|
|
#define CRC_GPOLYH_GPOLYH_SHIFT (0U)
|
|
#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GPOLY - CRC Polynomial */
|
|
/*! @{ */
|
|
|
|
#define CRC_GPOLY_LOW_MASK (0xFFFFU)
|
|
#define CRC_GPOLY_LOW_SHIFT (0U)
|
|
/*! LOW - Low Polynomial Half-Word */
|
|
#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
|
|
|
|
#define CRC_GPOLY_HIGH_MASK (0xFFFF0000U)
|
|
#define CRC_GPOLY_HIGH_SHIFT (16U)
|
|
/*! HIGH - High Polynomial Half-Word */
|
|
#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CTRLHU - CRC_CTRLHU register */
|
|
/*! @{ */
|
|
|
|
#define CRC_CTRLHU_TCRC_MASK (0x1U)
|
|
#define CRC_CTRLHU_TCRC_SHIFT (0U)
|
|
/*! TCRC - TCRC
|
|
* 0b0..16-bit
|
|
* 0b1..32-bit
|
|
*/
|
|
#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
|
|
|
|
#define CRC_CTRLHU_WAS_MASK (0x2U)
|
|
#define CRC_CTRLHU_WAS_SHIFT (1U)
|
|
/*! WAS - Write as Seed
|
|
* 0b0..Data values
|
|
* 0b1..Seed values
|
|
*/
|
|
#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
|
|
|
|
#define CRC_CTRLHU_FXOR_MASK (0x4U)
|
|
#define CRC_CTRLHU_FXOR_SHIFT (2U)
|
|
/*! FXOR - Complement Read of CRC Data Register
|
|
* 0b0..No XOR on reading
|
|
* 0b1..Inverts or complements the read value of the CRC Data
|
|
*/
|
|
#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
|
|
|
|
#define CRC_CTRLHU_TOTR_MASK (0x30U)
|
|
#define CRC_CTRLHU_TOTR_SHIFT (4U)
|
|
/*! TOTR - Transpose Type for Read
|
|
* 0b00..No transposition
|
|
* 0b01..Bits in bytes are transposed; bytes are not transposed
|
|
* 0b10..Both bits in bytes and bytes are transposed
|
|
* 0b11..Only bytes are transposed; no bits in a byte are transposed
|
|
*/
|
|
#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
|
|
|
|
#define CRC_CTRLHU_TOT_MASK (0xC0U)
|
|
#define CRC_CTRLHU_TOT_SHIFT (6U)
|
|
/*! TOT - Transpose Type for Writes
|
|
* 0b00..No transposition
|
|
* 0b01..Bits in bytes are transposed; bytes are not transposed
|
|
* 0b10..Both bits in bytes and bytes are transposed
|
|
* 0b11..Only bytes are transposed; no bits in a byte are transposed
|
|
*/
|
|
#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CTRL - CRC Control */
|
|
/*! @{ */
|
|
|
|
#define CRC_CTRL_TCRC_MASK (0x1000000U)
|
|
#define CRC_CTRL_TCRC_SHIFT (24U)
|
|
/*! TCRC - TCRC
|
|
* 0b0..16-bit
|
|
* 0b1..32-bit
|
|
*/
|
|
#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
|
|
|
|
#define CRC_CTRL_WAS_MASK (0x2000000U)
|
|
#define CRC_CTRL_WAS_SHIFT (25U)
|
|
/*! WAS - Write as Seed
|
|
* 0b0..Data values
|
|
* 0b1..Seed values
|
|
*/
|
|
#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
|
|
|
|
#define CRC_CTRL_FXOR_MASK (0x4000000U)
|
|
#define CRC_CTRL_FXOR_SHIFT (26U)
|
|
/*! FXOR - Complement Read of CRC Data Register
|
|
* 0b0..No XOR on reading
|
|
* 0b1..Inverts or complements the read value of the CRC Data
|
|
*/
|
|
#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
|
|
|
|
#define CRC_CTRL_TOTR_MASK (0x30000000U)
|
|
#define CRC_CTRL_TOTR_SHIFT (28U)
|
|
/*! TOTR - Transpose Type for Read
|
|
* 0b00..No transposition
|
|
* 0b01..Bits in bytes are transposed; bytes are not transposed
|
|
* 0b10..Both bits in bytes and bytes are transposed
|
|
* 0b11..Only bytes are transposed; no bits in a byte are transposed
|
|
*/
|
|
#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
|
|
|
|
#define CRC_CTRL_TOT_MASK (0xC0000000U)
|
|
#define CRC_CTRL_TOT_SHIFT (30U)
|
|
/*! TOT - Transpose Type for Writes
|
|
* 0b00..No transposition
|
|
* 0b01..Bits in bytes are transposed; bytes are not transposed
|
|
* 0b10..Both bits in bytes and bytes are transposed
|
|
* 0b11..Only bytes are transposed; no bits in a byte are transposed
|
|
*/
|
|
#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group CRC_Register_Masks */
|
|
|
|
|
|
/* CRC - Peripheral instance base addresses */
|
|
/** Peripheral CRC0 base address */
|
|
#define CRC0_BASE (0x4008A000u)
|
|
/** Peripheral CRC0 base pointer */
|
|
#define CRC0 ((CRC_Type *)CRC0_BASE)
|
|
/** Array initializer of CRC peripheral base addresses */
|
|
#define CRC_BASE_ADDRS { CRC0_BASE }
|
|
/** Array initializer of CRC peripheral base pointers */
|
|
#define CRC_BASE_PTRS { CRC0 }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group CRC_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- CTIMER Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** CTIMER - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t IR; /**< Interrupt, offset: 0x0 */
|
|
__IO uint32_t TCR; /**< Timer Control, offset: 0x4 */
|
|
__IO uint32_t TC; /**< Timer Counter, offset: 0x8 */
|
|
__IO uint32_t PR; /**< Prescale, offset: 0xC */
|
|
__IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */
|
|
__IO uint32_t MCR; /**< Match Control, offset: 0x14 */
|
|
__IO uint32_t MR[4]; /**< Match, array offset: 0x18, array step: 0x4 */
|
|
__IO uint32_t CCR; /**< Capture Control, offset: 0x28 */
|
|
__I uint32_t CR[4]; /**< Capture, array offset: 0x2C, array step: 0x4 */
|
|
__IO uint32_t EMR; /**< External Match, offset: 0x3C */
|
|
uint8_t RESERVED_0[48];
|
|
__IO uint32_t CTCR; /**< Count Control, offset: 0x70 */
|
|
__IO uint32_t PWMC; /**< PWM Control, offset: 0x74 */
|
|
__IO uint32_t MSR[4]; /**< Match Shadow, array offset: 0x78, array step: 0x4 */
|
|
} CTIMER_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- CTIMER Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup CTIMER_Register_Masks CTIMER Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name IR - Interrupt */
|
|
/*! @{ */
|
|
|
|
#define CTIMER_IR_MR0INT_MASK (0x1U)
|
|
#define CTIMER_IR_MR0INT_SHIFT (0U)
|
|
/*! MR0INT - Interrupt Flag for Match Channel 0 Event */
|
|
#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)
|
|
|
|
#define CTIMER_IR_MR1INT_MASK (0x2U)
|
|
#define CTIMER_IR_MR1INT_SHIFT (1U)
|
|
/*! MR1INT - Interrupt Flag for Match Channel 1 Event */
|
|
#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)
|
|
|
|
#define CTIMER_IR_MR2INT_MASK (0x4U)
|
|
#define CTIMER_IR_MR2INT_SHIFT (2U)
|
|
/*! MR2INT - Interrupt Flag for Match Channel 2 Event */
|
|
#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)
|
|
|
|
#define CTIMER_IR_MR3INT_MASK (0x8U)
|
|
#define CTIMER_IR_MR3INT_SHIFT (3U)
|
|
/*! MR3INT - Interrupt Flag for Match Channel 3 Event */
|
|
#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)
|
|
|
|
#define CTIMER_IR_CR0INT_MASK (0x10U)
|
|
#define CTIMER_IR_CR0INT_SHIFT (4U)
|
|
/*! CR0INT - Interrupt Flag for Capture Channel 0 Event */
|
|
#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)
|
|
|
|
#define CTIMER_IR_CR1INT_MASK (0x20U)
|
|
#define CTIMER_IR_CR1INT_SHIFT (5U)
|
|
/*! CR1INT - Interrupt Flag for Capture Channel 1 Event */
|
|
#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)
|
|
|
|
#define CTIMER_IR_CR2INT_MASK (0x40U)
|
|
#define CTIMER_IR_CR2INT_SHIFT (6U)
|
|
/*! CR2INT - Interrupt Flag for Capture Channel 2 Event */
|
|
#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)
|
|
|
|
#define CTIMER_IR_CR3INT_MASK (0x80U)
|
|
#define CTIMER_IR_CR3INT_SHIFT (7U)
|
|
/*! CR3INT - Interrupt Flag for Capture Channel 3 Event */
|
|
#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TCR - Timer Control */
|
|
/*! @{ */
|
|
|
|
#define CTIMER_TCR_CEN_MASK (0x1U)
|
|
#define CTIMER_TCR_CEN_SHIFT (0U)
|
|
/*! CEN - Counter Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)
|
|
|
|
#define CTIMER_TCR_CRST_MASK (0x2U)
|
|
#define CTIMER_TCR_CRST_SHIFT (1U)
|
|
/*! CRST - Counter Reset Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)
|
|
|
|
#define CTIMER_TCR_AGCEN_MASK (0x10U)
|
|
#define CTIMER_TCR_AGCEN_SHIFT (4U)
|
|
/*! AGCEN - Allow Global Count Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define CTIMER_TCR_AGCEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_AGCEN_SHIFT)) & CTIMER_TCR_AGCEN_MASK)
|
|
|
|
#define CTIMER_TCR_ATCEN_MASK (0x20U)
|
|
#define CTIMER_TCR_ATCEN_SHIFT (5U)
|
|
/*! ATCEN - Allow Trigger Count Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define CTIMER_TCR_ATCEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_ATCEN_SHIFT)) & CTIMER_TCR_ATCEN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TC - Timer Counter */
|
|
/*! @{ */
|
|
|
|
#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU)
|
|
#define CTIMER_TC_TCVAL_SHIFT (0U)
|
|
/*! TCVAL - Timer Counter Value */
|
|
#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PR - Prescale */
|
|
/*! @{ */
|
|
|
|
#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU)
|
|
#define CTIMER_PR_PRVAL_SHIFT (0U)
|
|
/*! PRVAL - Prescale Reload Value */
|
|
#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PC - Prescale Counter */
|
|
/*! @{ */
|
|
|
|
#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU)
|
|
#define CTIMER_PC_PCVAL_SHIFT (0U)
|
|
/*! PCVAL - Prescale Counter Value */
|
|
#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MCR - Match Control */
|
|
/*! @{ */
|
|
|
|
#define CTIMER_MCR_MR0I_MASK (0x1U)
|
|
#define CTIMER_MCR_MR0I_SHIFT (0U)
|
|
/*! MR0I - Interrupt on MR0
|
|
* 0b0..Does not generate
|
|
* 0b1..Generates
|
|
*/
|
|
#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
|
|
|
|
#define CTIMER_MCR_MR0R_MASK (0x2U)
|
|
#define CTIMER_MCR_MR0R_SHIFT (1U)
|
|
/*! MR0R - Reset on MR0
|
|
* 0b0..Does not reset
|
|
* 0b1..Resets
|
|
*/
|
|
#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)
|
|
|
|
#define CTIMER_MCR_MR0S_MASK (0x4U)
|
|
#define CTIMER_MCR_MR0S_SHIFT (2U)
|
|
/*! MR0S - Stop on MR0
|
|
* 0b0..Does not stop
|
|
* 0b1..Stops
|
|
*/
|
|
#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)
|
|
|
|
#define CTIMER_MCR_MR1I_MASK (0x8U)
|
|
#define CTIMER_MCR_MR1I_SHIFT (3U)
|
|
/*! MR1I - Interrupt on MR1
|
|
* 0b0..Does not generate
|
|
* 0b1..Generates
|
|
*/
|
|
#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)
|
|
|
|
#define CTIMER_MCR_MR1R_MASK (0x10U)
|
|
#define CTIMER_MCR_MR1R_SHIFT (4U)
|
|
/*! MR1R - Reset on MR1
|
|
* 0b0..Does not reset
|
|
* 0b1..Resets
|
|
*/
|
|
#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)
|
|
|
|
#define CTIMER_MCR_MR1S_MASK (0x20U)
|
|
#define CTIMER_MCR_MR1S_SHIFT (5U)
|
|
/*! MR1S - Stop on MR1
|
|
* 0b0..Does not stop
|
|
* 0b1..Stops
|
|
*/
|
|
#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)
|
|
|
|
#define CTIMER_MCR_MR2I_MASK (0x40U)
|
|
#define CTIMER_MCR_MR2I_SHIFT (6U)
|
|
/*! MR2I - Interrupt on MR2
|
|
* 0b0..Does not generate
|
|
* 0b1..Generates
|
|
*/
|
|
#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)
|
|
|
|
#define CTIMER_MCR_MR2R_MASK (0x80U)
|
|
#define CTIMER_MCR_MR2R_SHIFT (7U)
|
|
/*! MR2R - Reset on MR2
|
|
* 0b0..Does not reset
|
|
* 0b1..Resets
|
|
*/
|
|
#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)
|
|
|
|
#define CTIMER_MCR_MR2S_MASK (0x100U)
|
|
#define CTIMER_MCR_MR2S_SHIFT (8U)
|
|
/*! MR2S - Stop on MR2
|
|
* 0b0..Does not stop
|
|
* 0b1..Stops
|
|
*/
|
|
#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)
|
|
|
|
#define CTIMER_MCR_MR3I_MASK (0x200U)
|
|
#define CTIMER_MCR_MR3I_SHIFT (9U)
|
|
/*! MR3I - Interrupt on MR3
|
|
* 0b0..Does not generate
|
|
* 0b1..Generates
|
|
*/
|
|
#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)
|
|
|
|
#define CTIMER_MCR_MR3R_MASK (0x400U)
|
|
#define CTIMER_MCR_MR3R_SHIFT (10U)
|
|
/*! MR3R - Reset on MR3
|
|
* 0b0..Does not reset
|
|
* 0b1..Resets
|
|
*/
|
|
#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)
|
|
|
|
#define CTIMER_MCR_MR3S_MASK (0x800U)
|
|
#define CTIMER_MCR_MR3S_SHIFT (11U)
|
|
/*! MR3S - Stop on MR3
|
|
* 0b0..Does not stop
|
|
* 0b1..Stops
|
|
*/
|
|
#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)
|
|
|
|
#define CTIMER_MCR_MR0RL_MASK (0x1000000U)
|
|
#define CTIMER_MCR_MR0RL_SHIFT (24U)
|
|
/*! MR0RL - Reload MR
|
|
* 0b0..Does not reload
|
|
* 0b1..Reloads
|
|
*/
|
|
#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK)
|
|
|
|
#define CTIMER_MCR_MR1RL_MASK (0x2000000U)
|
|
#define CTIMER_MCR_MR1RL_SHIFT (25U)
|
|
/*! MR1RL - Reload MR
|
|
* 0b0..Does not reload
|
|
* 0b1..Reloads
|
|
*/
|
|
#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK)
|
|
|
|
#define CTIMER_MCR_MR2RL_MASK (0x4000000U)
|
|
#define CTIMER_MCR_MR2RL_SHIFT (26U)
|
|
/*! MR2RL - Reload MR
|
|
* 0b0..Does not reload
|
|
* 0b1..Reloads
|
|
*/
|
|
#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK)
|
|
|
|
#define CTIMER_MCR_MR3RL_MASK (0x8000000U)
|
|
#define CTIMER_MCR_MR3RL_SHIFT (27U)
|
|
/*! MR3RL - Reload MR
|
|
* 0b0..Does not reload
|
|
* 0b1..Reloads
|
|
*/
|
|
#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MR - Match */
|
|
/*! @{ */
|
|
|
|
#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU)
|
|
#define CTIMER_MR_MATCH_SHIFT (0U)
|
|
/*! MATCH - Timer Counter Match Value */
|
|
#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of CTIMER_MR */
|
|
#define CTIMER_MR_COUNT (4U)
|
|
|
|
/*! @name CCR - Capture Control */
|
|
/*! @{ */
|
|
|
|
#define CTIMER_CCR_CAP0RE_MASK (0x1U)
|
|
#define CTIMER_CCR_CAP0RE_SHIFT (0U)
|
|
/*! CAP0RE - Rising Edge of Capture Channel 0
|
|
* 0b0..Does not load
|
|
* 0b1..Loads
|
|
*/
|
|
#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)
|
|
|
|
#define CTIMER_CCR_CAP0FE_MASK (0x2U)
|
|
#define CTIMER_CCR_CAP0FE_SHIFT (1U)
|
|
/*! CAP0FE - Falling Edge of Capture Channel 0
|
|
* 0b0..Does not load
|
|
* 0b1..Loads
|
|
*/
|
|
#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)
|
|
|
|
#define CTIMER_CCR_CAP0I_MASK (0x4U)
|
|
#define CTIMER_CCR_CAP0I_SHIFT (2U)
|
|
/*! CAP0I - Generate Interrupt on Channel 0 Capture Event
|
|
* 0b0..Does not generate
|
|
* 0b1..Generates
|
|
*/
|
|
#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
|
|
|
|
#define CTIMER_CCR_CAP1RE_MASK (0x8U)
|
|
#define CTIMER_CCR_CAP1RE_SHIFT (3U)
|
|
/*! CAP1RE - Rising Edge of Capture Channel 1
|
|
* 0b0..Does not load
|
|
* 0b1..Loads
|
|
*/
|
|
#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)
|
|
|
|
#define CTIMER_CCR_CAP1FE_MASK (0x10U)
|
|
#define CTIMER_CCR_CAP1FE_SHIFT (4U)
|
|
/*! CAP1FE - Falling Edge of Capture Channel 1
|
|
* 0b0..Does not load
|
|
* 0b1..Loads
|
|
*/
|
|
#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)
|
|
|
|
#define CTIMER_CCR_CAP1I_MASK (0x20U)
|
|
#define CTIMER_CCR_CAP1I_SHIFT (5U)
|
|
/*! CAP1I - Generate Interrupt on Channel 1 Capture Event
|
|
* 0b0..Does not generates
|
|
* 0b1..Generates
|
|
*/
|
|
#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)
|
|
|
|
#define CTIMER_CCR_CAP2RE_MASK (0x40U)
|
|
#define CTIMER_CCR_CAP2RE_SHIFT (6U)
|
|
/*! CAP2RE - Rising Edge of Capture Channel 2
|
|
* 0b0..Does not load
|
|
* 0b1..Loads
|
|
*/
|
|
#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)
|
|
|
|
#define CTIMER_CCR_CAP2FE_MASK (0x80U)
|
|
#define CTIMER_CCR_CAP2FE_SHIFT (7U)
|
|
/*! CAP2FE - Falling Edge of Capture Channel 2
|
|
* 0b0..Does not load
|
|
* 0b1..Loads
|
|
*/
|
|
#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)
|
|
|
|
#define CTIMER_CCR_CAP2I_MASK (0x100U)
|
|
#define CTIMER_CCR_CAP2I_SHIFT (8U)
|
|
/*! CAP2I - Generate Interrupt on Channel 2 Capture Event
|
|
* 0b0..Does not generate
|
|
* 0b1..Generates
|
|
*/
|
|
#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)
|
|
|
|
#define CTIMER_CCR_CAP3RE_MASK (0x200U)
|
|
#define CTIMER_CCR_CAP3RE_SHIFT (9U)
|
|
/*! CAP3RE - Rising Edge of Capture Channel 3
|
|
* 0b0..Does not load
|
|
* 0b1..Loads
|
|
*/
|
|
#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK)
|
|
|
|
#define CTIMER_CCR_CAP3FE_MASK (0x400U)
|
|
#define CTIMER_CCR_CAP3FE_SHIFT (10U)
|
|
/*! CAP3FE - Falling Edge of Capture Channel 3
|
|
* 0b0..Does not load
|
|
* 0b1..Loads
|
|
*/
|
|
#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK)
|
|
|
|
#define CTIMER_CCR_CAP3I_MASK (0x800U)
|
|
#define CTIMER_CCR_CAP3I_SHIFT (11U)
|
|
/*! CAP3I - Generate Interrupt on Channel 3 Capture Event
|
|
* 0b0..Does not generate
|
|
* 0b1..Generates
|
|
*/
|
|
#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CR - Capture */
|
|
/*! @{ */
|
|
|
|
#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU)
|
|
#define CTIMER_CR_CAP_SHIFT (0U)
|
|
/*! CAP - Timer Counter Capture Value */
|
|
#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of CTIMER_CR */
|
|
#define CTIMER_CR_COUNT (4U)
|
|
|
|
/*! @name EMR - External Match */
|
|
/*! @{ */
|
|
|
|
#define CTIMER_EMR_EM0_MASK (0x1U)
|
|
#define CTIMER_EMR_EM0_SHIFT (0U)
|
|
/*! EM0 - External Match 0
|
|
* 0b0..Low
|
|
* 0b1..High
|
|
*/
|
|
#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)
|
|
|
|
#define CTIMER_EMR_EM1_MASK (0x2U)
|
|
#define CTIMER_EMR_EM1_SHIFT (1U)
|
|
/*! EM1 - External Match 1
|
|
* 0b0..Low
|
|
* 0b1..High
|
|
*/
|
|
#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)
|
|
|
|
#define CTIMER_EMR_EM2_MASK (0x4U)
|
|
#define CTIMER_EMR_EM2_SHIFT (2U)
|
|
/*! EM2 - External Match 2
|
|
* 0b0..Low
|
|
* 0b1..High
|
|
*/
|
|
#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)
|
|
|
|
#define CTIMER_EMR_EM3_MASK (0x8U)
|
|
#define CTIMER_EMR_EM3_SHIFT (3U)
|
|
/*! EM3 - External Match 3
|
|
* 0b0..Low
|
|
* 0b1..High
|
|
*/
|
|
#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)
|
|
|
|
#define CTIMER_EMR_EMC0_MASK (0x30U)
|
|
#define CTIMER_EMR_EMC0_SHIFT (4U)
|
|
/*! EMC0 - External Match Control 0
|
|
* 0b00..Does nothing
|
|
* 0b01..Goes low
|
|
* 0b10..Goes high
|
|
* 0b11..Toggles
|
|
*/
|
|
#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)
|
|
|
|
#define CTIMER_EMR_EMC1_MASK (0xC0U)
|
|
#define CTIMER_EMR_EMC1_SHIFT (6U)
|
|
/*! EMC1 - External Match Control 1
|
|
* 0b00..Does nothing
|
|
* 0b01..Goes low
|
|
* 0b10..Goes high
|
|
* 0b11..Toggles
|
|
*/
|
|
#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)
|
|
|
|
#define CTIMER_EMR_EMC2_MASK (0x300U)
|
|
#define CTIMER_EMR_EMC2_SHIFT (8U)
|
|
/*! EMC2 - External Match Control 2
|
|
* 0b00..Does nothing
|
|
* 0b01..Goes low
|
|
* 0b10..Goes high
|
|
* 0b11..Toggles
|
|
*/
|
|
#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)
|
|
|
|
#define CTIMER_EMR_EMC3_MASK (0xC00U)
|
|
#define CTIMER_EMR_EMC3_SHIFT (10U)
|
|
/*! EMC3 - External Match Control 3
|
|
* 0b00..Does nothing
|
|
* 0b01..Goes low
|
|
* 0b10..Goes high
|
|
* 0b11..Toggles
|
|
*/
|
|
#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CTCR - Count Control */
|
|
/*! @{ */
|
|
|
|
#define CTIMER_CTCR_CTMODE_MASK (0x3U)
|
|
#define CTIMER_CTCR_CTMODE_SHIFT (0U)
|
|
/*! CTMODE - Counter Timer Mode
|
|
* 0b00..Timer mode
|
|
* 0b01..Counter mode rising edge
|
|
* 0b10..Counter mode falling edge
|
|
* 0b11..Counter mode dual edge
|
|
*/
|
|
#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)
|
|
|
|
#define CTIMER_CTCR_CINSEL_MASK (0xCU)
|
|
#define CTIMER_CTCR_CINSEL_SHIFT (2U)
|
|
/*! CINSEL - Count Input Select
|
|
* 0b00..Channel 0, CAPn[0] for CTIMERn
|
|
* 0b01..Channel 1, CAPn[1] for CTIMERn
|
|
* 0b10..Channel 2, CAPn[2] for CTIMERn
|
|
* 0b11..Channel 3, CAPn[3] for CTIMERn
|
|
*/
|
|
#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)
|
|
|
|
#define CTIMER_CTCR_ENCC_MASK (0x10U)
|
|
#define CTIMER_CTCR_ENCC_SHIFT (4U)
|
|
/*! ENCC - Capture Channel Enable */
|
|
#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)
|
|
|
|
#define CTIMER_CTCR_SELCC_MASK (0xE0U)
|
|
#define CTIMER_CTCR_SELCC_SHIFT (5U)
|
|
/*! SELCC - Edge Select
|
|
* 0b000..Capture channel 0 rising edge
|
|
* 0b001..Capture channel 0 falling edge
|
|
* 0b010..Capture channel 1 rising edge
|
|
* 0b011..Capture channel 1 falling edge
|
|
* 0b100..Capture channel 2 rising edge
|
|
* 0b101..Capture channel 2 falling edge
|
|
*/
|
|
#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PWMC - PWM Control */
|
|
/*! @{ */
|
|
|
|
#define CTIMER_PWMC_PWMEN0_MASK (0x1U)
|
|
#define CTIMER_PWMC_PWMEN0_SHIFT (0U)
|
|
/*! PWMEN0 - PWM Mode Enable for Channel 0
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)
|
|
|
|
#define CTIMER_PWMC_PWMEN1_MASK (0x2U)
|
|
#define CTIMER_PWMC_PWMEN1_SHIFT (1U)
|
|
/*! PWMEN1 - PWM Mode Enable for Channel 1
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)
|
|
|
|
#define CTIMER_PWMC_PWMEN2_MASK (0x4U)
|
|
#define CTIMER_PWMC_PWMEN2_SHIFT (2U)
|
|
/*! PWMEN2 - PWM Mode Enable for Channel 2
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)
|
|
|
|
#define CTIMER_PWMC_PWMEN3_MASK (0x8U)
|
|
#define CTIMER_PWMC_PWMEN3_SHIFT (3U)
|
|
/*! PWMEN3 - PWM Mode Enable for Channel 3
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MSR - Match Shadow */
|
|
/*! @{ */
|
|
|
|
#define CTIMER_MSR_MATCH_SHADOW_MASK (0xFFFFFFFFU)
|
|
#define CTIMER_MSR_MATCH_SHADOW_SHIFT (0U)
|
|
/*! MATCH_SHADOW - Timer Counter Match Shadow Value */
|
|
#define CTIMER_MSR_MATCH_SHADOW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_MATCH_SHADOW_SHIFT)) & CTIMER_MSR_MATCH_SHADOW_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of CTIMER_MSR */
|
|
#define CTIMER_MSR_COUNT (4U)
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group CTIMER_Register_Masks */
|
|
|
|
|
|
/* CTIMER - Peripheral instance base addresses */
|
|
/** Peripheral CTIMER0 base address */
|
|
#define CTIMER0_BASE (0x40004000u)
|
|
/** Peripheral CTIMER0 base pointer */
|
|
#define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE)
|
|
/** Peripheral CTIMER1 base address */
|
|
#define CTIMER1_BASE (0x40005000u)
|
|
/** Peripheral CTIMER1 base pointer */
|
|
#define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE)
|
|
/** Peripheral CTIMER2 base address */
|
|
#define CTIMER2_BASE (0x40006000u)
|
|
/** Peripheral CTIMER2 base pointer */
|
|
#define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE)
|
|
/** Array initializer of CTIMER peripheral base addresses */
|
|
#define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE }
|
|
/** Array initializer of CTIMER peripheral base pointers */
|
|
#define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2 }
|
|
/** Interrupt vectors for the CTIMER peripheral type */
|
|
#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group CTIMER_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- DEBUGMAILBOX Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup DEBUGMAILBOX_Peripheral_Access_Layer DEBUGMAILBOX Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** DEBUGMAILBOX - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t CSW; /**< Command and Status Word, offset: 0x0 */
|
|
__IO uint32_t REQUEST; /**< Request Value, offset: 0x4 */
|
|
__IO uint32_t RETURN; /**< Return Value, offset: 0x8 */
|
|
uint8_t RESERVED_0[240];
|
|
__I uint32_t ID; /**< Identification, offset: 0xFC */
|
|
} DEBUGMAILBOX_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- DEBUGMAILBOX Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup DEBUGMAILBOX_Register_Masks DEBUGMAILBOX Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name CSW - Command and Status Word */
|
|
/*! @{ */
|
|
|
|
#define DEBUGMAILBOX_CSW_RESYNCH_REQ_MASK (0x1U)
|
|
#define DEBUGMAILBOX_CSW_RESYNCH_REQ_SHIFT (0U)
|
|
/*! RESYNCH_REQ - Resynchronization Request
|
|
* 0b0..No request
|
|
* 0b1..Request for resynchronization
|
|
*/
|
|
#define DEBUGMAILBOX_CSW_RESYNCH_REQ(x) (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_CSW_RESYNCH_REQ_SHIFT)) & DEBUGMAILBOX_CSW_RESYNCH_REQ_MASK)
|
|
|
|
#define DEBUGMAILBOX_CSW_REQ_PENDING_MASK (0x2U)
|
|
#define DEBUGMAILBOX_CSW_REQ_PENDING_SHIFT (1U)
|
|
/*! REQ_PENDING - Request Pending
|
|
* 0b0..No request pending
|
|
* 0b1..Request for resynchronization pending
|
|
*/
|
|
#define DEBUGMAILBOX_CSW_REQ_PENDING(x) (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_CSW_REQ_PENDING_SHIFT)) & DEBUGMAILBOX_CSW_REQ_PENDING_MASK)
|
|
|
|
#define DEBUGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U)
|
|
#define DEBUGMAILBOX_CSW_DBG_OR_ERR_SHIFT (2U)
|
|
/*! DBG_OR_ERR - DBGMB Overrun Error
|
|
* 0b0..No DBGMB Overrun error
|
|
* 0b1..DBGMB overrun error. A DBGMB overrun occurred.
|
|
*/
|
|
#define DEBUGMAILBOX_CSW_DBG_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DEBUGMAILBOX_CSW_DBG_OR_ERR_MASK)
|
|
|
|
#define DEBUGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U)
|
|
#define DEBUGMAILBOX_CSW_AHB_OR_ERR_SHIFT (3U)
|
|
/*! AHB_OR_ERR - AHB Overrun Error
|
|
* 0b0..No AHB Overrun Error
|
|
* 0b1..AHB Overrun Error. An AHB overrun occurred.
|
|
*/
|
|
#define DEBUGMAILBOX_CSW_AHB_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DEBUGMAILBOX_CSW_AHB_OR_ERR_MASK)
|
|
|
|
#define DEBUGMAILBOX_CSW_SOFT_RESET_MASK (0x10U)
|
|
#define DEBUGMAILBOX_CSW_SOFT_RESET_SHIFT (4U)
|
|
/*! SOFT_RESET - Soft Reset */
|
|
#define DEBUGMAILBOX_CSW_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_CSW_SOFT_RESET_SHIFT)) & DEBUGMAILBOX_CSW_SOFT_RESET_MASK)
|
|
|
|
#define DEBUGMAILBOX_CSW_CHIP_RESET_REQ_MASK (0x20U)
|
|
#define DEBUGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT (5U)
|
|
/*! CHIP_RESET_REQ - Chip Reset Request */
|
|
#define DEBUGMAILBOX_CSW_CHIP_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT)) & DEBUGMAILBOX_CSW_CHIP_RESET_REQ_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name REQUEST - Request Value */
|
|
/*! @{ */
|
|
|
|
#define DEBUGMAILBOX_REQUEST_REQUEST_MASK (0xFFFFFFFFU)
|
|
#define DEBUGMAILBOX_REQUEST_REQUEST_SHIFT (0U)
|
|
/*! REQUEST - Request Value */
|
|
#define DEBUGMAILBOX_REQUEST_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_REQUEST_REQUEST_SHIFT)) & DEBUGMAILBOX_REQUEST_REQUEST_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RETURN - Return Value */
|
|
/*! @{ */
|
|
|
|
#define DEBUGMAILBOX_RETURN_RET_MASK (0xFFFFFFFFU)
|
|
#define DEBUGMAILBOX_RETURN_RET_SHIFT (0U)
|
|
/*! RET - Return Value */
|
|
#define DEBUGMAILBOX_RETURN_RET(x) (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_RETURN_RET_SHIFT)) & DEBUGMAILBOX_RETURN_RET_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ID - Identification */
|
|
/*! @{ */
|
|
|
|
#define DEBUGMAILBOX_ID_ID_MASK (0xFFFFFFFFU)
|
|
#define DEBUGMAILBOX_ID_ID_SHIFT (0U)
|
|
/*! ID - Identification Value */
|
|
#define DEBUGMAILBOX_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_ID_ID_SHIFT)) & DEBUGMAILBOX_ID_ID_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group DEBUGMAILBOX_Register_Masks */
|
|
|
|
|
|
/* DEBUGMAILBOX - Peripheral instance base addresses */
|
|
/** Peripheral DBGMAILBOX base address */
|
|
#define DBGMAILBOX_BASE (0x40101000u)
|
|
/** Peripheral DBGMAILBOX base pointer */
|
|
#define DBGMAILBOX ((DEBUGMAILBOX_Type *)DBGMAILBOX_BASE)
|
|
/** Array initializer of DEBUGMAILBOX peripheral base addresses */
|
|
#define DEBUGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE }
|
|
/** Array initializer of DEBUGMAILBOX peripheral base pointers */
|
|
#define DEBUGMAILBOX_BASE_PTRS { DBGMAILBOX }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group DEBUGMAILBOX_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- DMA Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** DMA - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t MP_CSR; /**< Management Page Control, offset: 0x0 */
|
|
__I uint32_t MP_ES; /**< Management Page Error Status, offset: 0x4 */
|
|
__I uint32_t MP_INT; /**< Management Page Interrupt Request Status, offset: 0x8 */
|
|
__I uint32_t MP_HRS; /**< Management Page Hardware Request Status, offset: 0xC */
|
|
uint8_t RESERVED_0[240];
|
|
__IO uint32_t CH_GRPRI[4]; /**< Channel Arbitration Group, array offset: 0x100, array step: 0x4 */
|
|
uint8_t RESERVED_1[3824];
|
|
struct { /* offset: 0x1000, array step: 0x1000 */
|
|
__IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x1000, array step: 0x1000 */
|
|
__IO uint32_t CH_ES; /**< Channel Error Status, array offset: 0x1004, array step: 0x1000 */
|
|
__IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x1008, array step: 0x1000 */
|
|
__IO uint32_t CH_SBR; /**< Channel System Bus, array offset: 0x100C, array step: 0x1000 */
|
|
__IO uint32_t CH_PRI; /**< Channel Priority, array offset: 0x1010, array step: 0x1000 */
|
|
__IO uint32_t CH_MUX; /**< Channel Multiplexor Configuration, array offset: 0x1014, array step: 0x1000 */
|
|
uint8_t RESERVED_0[8];
|
|
__IO uint32_t TCD_SADDR; /**< TCD Source Address, array offset: 0x1020, array step: 0x1000 */
|
|
__IO uint16_t TCD_SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1024, array step: 0x1000 */
|
|
__IO uint16_t TCD_ATTR; /**< TCD Transfer Attributes, array offset: 0x1026, array step: 0x1000 */
|
|
union { /* offset: 0x1028, array step: 0x1000 */
|
|
__IO uint32_t TCD_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, array offset: 0x1028, array step: 0x1000 */
|
|
__IO uint32_t TCD_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, array offset: 0x1028, array step: 0x1000 */
|
|
};
|
|
__IO uint32_t TCD_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, array offset: 0x102C, array step: 0x1000 */
|
|
__IO uint32_t TCD_DADDR; /**< TCD Destination Address, array offset: 0x1030, array step: 0x1000 */
|
|
__IO uint16_t TCD_DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1034, array step: 0x1000 */
|
|
union { /* offset: 0x1036, array step: 0x1000 */
|
|
__IO uint16_t TCD_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x1036, array step: 0x1000 */
|
|
__IO uint16_t TCD_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x1036, array step: 0x1000 */
|
|
};
|
|
__IO uint32_t TCD_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, array offset: 0x1038, array step: 0x1000 */
|
|
__IO uint16_t TCD_CSR; /**< TCD Control and Status, array offset: 0x103C, array step: 0x1000 */
|
|
union { /* offset: 0x103E, array step: 0x1000 */
|
|
__IO uint16_t TCD_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x103E, array step: 0x1000 */
|
|
__IO uint16_t TCD_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x103E, array step: 0x1000 */
|
|
};
|
|
uint8_t RESERVED_1[4032];
|
|
} CH[4];
|
|
} DMA_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- DMA Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup DMA_Register_Masks DMA Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name MP_CSR - Management Page Control */
|
|
/*! @{ */
|
|
|
|
#define DMA_MP_CSR_EDBG_MASK (0x2U)
|
|
#define DMA_MP_CSR_EDBG_SHIFT (1U)
|
|
/*! EDBG - Enable Debug
|
|
* 0b0..Debug mode disabled
|
|
* 0b1..Debug mode is enabled.
|
|
*/
|
|
#define DMA_MP_CSR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_EDBG_SHIFT)) & DMA_MP_CSR_EDBG_MASK)
|
|
|
|
#define DMA_MP_CSR_ERCA_MASK (0x4U)
|
|
#define DMA_MP_CSR_ERCA_SHIFT (2U)
|
|
/*! ERCA - Enable Round Robin Channel Arbitration
|
|
* 0b0..Round-robin channel arbitration disabled
|
|
* 0b1..Round-robin channel arbitration enabled
|
|
*/
|
|
#define DMA_MP_CSR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ERCA_SHIFT)) & DMA_MP_CSR_ERCA_MASK)
|
|
|
|
#define DMA_MP_CSR_HAE_MASK (0x10U)
|
|
#define DMA_MP_CSR_HAE_SHIFT (4U)
|
|
/*! HAE - Halt After Error
|
|
* 0b0..Normal operation
|
|
* 0b1..Any error causes the HALT field to be set to 1
|
|
*/
|
|
#define DMA_MP_CSR_HAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HAE_SHIFT)) & DMA_MP_CSR_HAE_MASK)
|
|
|
|
#define DMA_MP_CSR_HALT_MASK (0x20U)
|
|
#define DMA_MP_CSR_HALT_SHIFT (5U)
|
|
/*! HALT - Halt DMA Operations
|
|
* 0b0..Normal operation
|
|
* 0b1..Stall the start of any new channels
|
|
*/
|
|
#define DMA_MP_CSR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HALT_SHIFT)) & DMA_MP_CSR_HALT_MASK)
|
|
|
|
#define DMA_MP_CSR_GCLC_MASK (0x40U)
|
|
#define DMA_MP_CSR_GCLC_SHIFT (6U)
|
|
/*! GCLC - Global Channel Linking Control
|
|
* 0b0..Channel linking disabled for all channels
|
|
* 0b1..Channel linking available and controlled by each channel's link settings
|
|
*/
|
|
#define DMA_MP_CSR_GCLC(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GCLC_SHIFT)) & DMA_MP_CSR_GCLC_MASK)
|
|
|
|
#define DMA_MP_CSR_GMRC_MASK (0x80U)
|
|
#define DMA_MP_CSR_GMRC_SHIFT (7U)
|
|
/*! GMRC - Global Master ID Replication Control
|
|
* 0b0..Master ID replication disabled for all channels
|
|
* 0b1..Master ID replication available and controlled by each channel's CHn_SBR[EMI] setting
|
|
*/
|
|
#define DMA_MP_CSR_GMRC(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GMRC_SHIFT)) & DMA_MP_CSR_GMRC_MASK)
|
|
|
|
#define DMA_MP_CSR_ECX_MASK (0x100U)
|
|
#define DMA_MP_CSR_ECX_SHIFT (8U)
|
|
/*! ECX - Cancel Transfer With Error
|
|
* 0b0..Normal operation
|
|
* 0b1..Cancel the remaining data transfer
|
|
*/
|
|
#define DMA_MP_CSR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ECX_SHIFT)) & DMA_MP_CSR_ECX_MASK)
|
|
|
|
#define DMA_MP_CSR_CX_MASK (0x200U)
|
|
#define DMA_MP_CSR_CX_SHIFT (9U)
|
|
/*! CX - Cancel Transfer
|
|
* 0b0..Normal operation
|
|
* 0b1..Cancel the remaining data transfer
|
|
*/
|
|
#define DMA_MP_CSR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_CX_SHIFT)) & DMA_MP_CSR_CX_MASK)
|
|
|
|
#define DMA_MP_CSR_ACTIVE_ID_MASK (0x3000000U)
|
|
#define DMA_MP_CSR_ACTIVE_ID_SHIFT (24U)
|
|
/*! ACTIVE_ID - Active Channel ID */
|
|
#define DMA_MP_CSR_ACTIVE_ID(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_ID_SHIFT)) & DMA_MP_CSR_ACTIVE_ID_MASK)
|
|
|
|
#define DMA_MP_CSR_ACTIVE_MASK (0x80000000U)
|
|
#define DMA_MP_CSR_ACTIVE_SHIFT (31U)
|
|
/*! ACTIVE - DMA Active Status
|
|
* 0b0..eDMA is idle
|
|
* 0b1..eDMA is executing a channel
|
|
*/
|
|
#define DMA_MP_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_SHIFT)) & DMA_MP_CSR_ACTIVE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MP_ES - Management Page Error Status */
|
|
/*! @{ */
|
|
|
|
#define DMA_MP_ES_DBE_MASK (0x1U)
|
|
#define DMA_MP_ES_DBE_SHIFT (0U)
|
|
/*! DBE - Destination Bus Error
|
|
* 0b0..No destination bus error
|
|
* 0b1..Last recorded error was a bus error on a destination write
|
|
*/
|
|
#define DMA_MP_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DBE_SHIFT)) & DMA_MP_ES_DBE_MASK)
|
|
|
|
#define DMA_MP_ES_SBE_MASK (0x2U)
|
|
#define DMA_MP_ES_SBE_SHIFT (1U)
|
|
/*! SBE - Source Bus Error
|
|
* 0b0..No source bus error
|
|
* 0b1..Last recorded error was a bus error on a source read
|
|
*/
|
|
#define DMA_MP_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SBE_SHIFT)) & DMA_MP_ES_SBE_MASK)
|
|
|
|
#define DMA_MP_ES_SGE_MASK (0x4U)
|
|
#define DMA_MP_ES_SGE_SHIFT (2U)
|
|
/*! SGE - Scatter/Gather Configuration Error
|
|
* 0b0..No scatter/gather configuration error
|
|
* 0b1..Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field
|
|
*/
|
|
#define DMA_MP_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SGE_SHIFT)) & DMA_MP_ES_SGE_MASK)
|
|
|
|
#define DMA_MP_ES_NCE_MASK (0x8U)
|
|
#define DMA_MP_ES_NCE_SHIFT (3U)
|
|
/*! NCE - NBYTES/CITER Configuration Error
|
|
* 0b0..No NBYTES/CITER configuration error
|
|
* 0b1..The last recorded error was NBYTES equal to zero or a CITER not equal to BITER error
|
|
*/
|
|
#define DMA_MP_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_NCE_SHIFT)) & DMA_MP_ES_NCE_MASK)
|
|
|
|
#define DMA_MP_ES_DOE_MASK (0x10U)
|
|
#define DMA_MP_ES_DOE_SHIFT (4U)
|
|
/*! DOE - Destination Offset Error
|
|
* 0b0..No destination offset configuration error
|
|
* 0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field
|
|
*/
|
|
#define DMA_MP_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DOE_SHIFT)) & DMA_MP_ES_DOE_MASK)
|
|
|
|
#define DMA_MP_ES_DAE_MASK (0x20U)
|
|
#define DMA_MP_ES_DAE_SHIFT (5U)
|
|
/*! DAE - Destination Address Error
|
|
* 0b0..No destination address configuration error
|
|
* 0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field
|
|
*/
|
|
#define DMA_MP_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DAE_SHIFT)) & DMA_MP_ES_DAE_MASK)
|
|
|
|
#define DMA_MP_ES_SOE_MASK (0x40U)
|
|
#define DMA_MP_ES_SOE_SHIFT (6U)
|
|
/*! SOE - Source Offset Error
|
|
* 0b0..No source offset configuration error
|
|
* 0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field
|
|
*/
|
|
#define DMA_MP_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SOE_SHIFT)) & DMA_MP_ES_SOE_MASK)
|
|
|
|
#define DMA_MP_ES_SAE_MASK (0x80U)
|
|
#define DMA_MP_ES_SAE_SHIFT (7U)
|
|
/*! SAE - Source Address Error
|
|
* 0b0..No source address configuration error
|
|
* 0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field
|
|
*/
|
|
#define DMA_MP_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SAE_SHIFT)) & DMA_MP_ES_SAE_MASK)
|
|
|
|
#define DMA_MP_ES_ECX_MASK (0x100U)
|
|
#define DMA_MP_ES_ECX_SHIFT (8U)
|
|
/*! ECX - Transfer Canceled
|
|
* 0b0..No canceled transfers
|
|
* 0b1..Last recorded entry was a canceled transfer by the error cancel transfer input
|
|
*/
|
|
#define DMA_MP_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ECX_SHIFT)) & DMA_MP_ES_ECX_MASK)
|
|
|
|
#define DMA_MP_ES_ERRCHN_MASK (0x3000000U)
|
|
#define DMA_MP_ES_ERRCHN_SHIFT (24U)
|
|
/*! ERRCHN - Error Channel Number or Canceled Channel Number */
|
|
#define DMA_MP_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ERRCHN_SHIFT)) & DMA_MP_ES_ERRCHN_MASK)
|
|
|
|
#define DMA_MP_ES_VLD_MASK (0x80000000U)
|
|
#define DMA_MP_ES_VLD_SHIFT (31U)
|
|
/*! VLD - Valid
|
|
* 0b0..No CHn_ES[ERR] fields are set to 1
|
|
* 0b1..At least one CHn_ES[ERR] field is set to 1, indicating a valid error exists that software has not cleared
|
|
*/
|
|
#define DMA_MP_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_VLD_SHIFT)) & DMA_MP_ES_VLD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MP_INT - Management Page Interrupt Request Status */
|
|
/*! @{ */
|
|
|
|
#define DMA_MP_INT_INT_MASK (0xFU)
|
|
#define DMA_MP_INT_INT_SHIFT (0U)
|
|
/*! INT - Interrupt Request Status */
|
|
#define DMA_MP_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_INT_INT_SHIFT)) & DMA_MP_INT_INT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MP_HRS - Management Page Hardware Request Status */
|
|
/*! @{ */
|
|
|
|
#define DMA_MP_HRS_HRS_MASK (0xFFFFFFFFU)
|
|
#define DMA_MP_HRS_HRS_SHIFT (0U)
|
|
/*! HRS - Hardware Request Status */
|
|
#define DMA_MP_HRS_HRS(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_HRS_HRS_SHIFT)) & DMA_MP_HRS_HRS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CH_GRPRI - Channel Arbitration Group */
|
|
/*! @{ */
|
|
|
|
#define DMA_CH_GRPRI_GRPRI_MASK (0x1FU)
|
|
#define DMA_CH_GRPRI_GRPRI_SHIFT (0U)
|
|
/*! GRPRI - Arbitration Group For Channel n */
|
|
#define DMA_CH_GRPRI_GRPRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_GRPRI_GRPRI_SHIFT)) & DMA_CH_GRPRI_GRPRI_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of DMA_CH_GRPRI */
|
|
#define DMA_CH_GRPRI_COUNT (4U)
|
|
|
|
/*! @name CH_CSR - Channel Control and Status */
|
|
/*! @{ */
|
|
|
|
#define DMA_CH_CSR_ERQ_MASK (0x1U)
|
|
#define DMA_CH_CSR_ERQ_SHIFT (0U)
|
|
/*! ERQ - Enable DMA Request
|
|
* 0b0..DMA hardware request signal for corresponding channel disabled
|
|
* 0b1..DMA hardware request signal for corresponding channel enabled
|
|
*/
|
|
#define DMA_CH_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ERQ_SHIFT)) & DMA_CH_CSR_ERQ_MASK)
|
|
|
|
#define DMA_CH_CSR_EARQ_MASK (0x2U)
|
|
#define DMA_CH_CSR_EARQ_SHIFT (1U)
|
|
/*! EARQ - Enable Asynchronous DMA Request
|
|
* 0b0..Disable asynchronous DMA request for the channel
|
|
* 0b1..Enable asynchronous DMA request for the channel
|
|
*/
|
|
#define DMA_CH_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EARQ_SHIFT)) & DMA_CH_CSR_EARQ_MASK)
|
|
|
|
#define DMA_CH_CSR_EEI_MASK (0x4U)
|
|
#define DMA_CH_CSR_EEI_SHIFT (2U)
|
|
/*! EEI - Enable Error Interrupt
|
|
* 0b0..Error signal for corresponding channel does not generate error interrupt
|
|
* 0b1..Assertion of error signal for corresponding channel generates error interrupt request
|
|
*/
|
|
#define DMA_CH_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EEI_SHIFT)) & DMA_CH_CSR_EEI_MASK)
|
|
|
|
#define DMA_CH_CSR_EBW_MASK (0x8U)
|
|
#define DMA_CH_CSR_EBW_SHIFT (3U)
|
|
/*! EBW - Enable Buffered Writes
|
|
* 0b0..Buffered writes on system bus disabled
|
|
* 0b1..Buffered writes on system bus enabled
|
|
*/
|
|
#define DMA_CH_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EBW_SHIFT)) & DMA_CH_CSR_EBW_MASK)
|
|
|
|
#define DMA_CH_CSR_DONE_MASK (0x40000000U)
|
|
#define DMA_CH_CSR_DONE_SHIFT (30U)
|
|
/*! DONE - Channel Done */
|
|
#define DMA_CH_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_DONE_SHIFT)) & DMA_CH_CSR_DONE_MASK)
|
|
|
|
#define DMA_CH_CSR_ACTIVE_MASK (0x80000000U)
|
|
#define DMA_CH_CSR_ACTIVE_SHIFT (31U)
|
|
/*! ACTIVE - Channel Active */
|
|
#define DMA_CH_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ACTIVE_SHIFT)) & DMA_CH_CSR_ACTIVE_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of DMA_CH_CSR */
|
|
#define DMA_CH_CSR_COUNT (4U)
|
|
|
|
/*! @name CH_ES - Channel Error Status */
|
|
/*! @{ */
|
|
|
|
#define DMA_CH_ES_DBE_MASK (0x1U)
|
|
#define DMA_CH_ES_DBE_SHIFT (0U)
|
|
/*! DBE - Destination Bus Error
|
|
* 0b0..No destination bus error
|
|
* 0b1..Last recorded error was bus error on destination write
|
|
*/
|
|
#define DMA_CH_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DBE_SHIFT)) & DMA_CH_ES_DBE_MASK)
|
|
|
|
#define DMA_CH_ES_SBE_MASK (0x2U)
|
|
#define DMA_CH_ES_SBE_SHIFT (1U)
|
|
/*! SBE - Source Bus Error
|
|
* 0b0..No source bus error
|
|
* 0b1..Last recorded error was bus error on source read
|
|
*/
|
|
#define DMA_CH_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SBE_SHIFT)) & DMA_CH_ES_SBE_MASK)
|
|
|
|
#define DMA_CH_ES_SGE_MASK (0x4U)
|
|
#define DMA_CH_ES_SGE_SHIFT (2U)
|
|
/*! SGE - Scatter/Gather Configuration Error
|
|
* 0b0..No scatter/gather configuration error
|
|
* 0b1..Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field
|
|
*/
|
|
#define DMA_CH_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SGE_SHIFT)) & DMA_CH_ES_SGE_MASK)
|
|
|
|
#define DMA_CH_ES_NCE_MASK (0x8U)
|
|
#define DMA_CH_ES_NCE_SHIFT (3U)
|
|
/*! NCE - NBYTES/CITER Configuration Error
|
|
* 0b0..No NBYTES/CITER configuration error
|
|
* 0b1..Last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields
|
|
*/
|
|
#define DMA_CH_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_NCE_SHIFT)) & DMA_CH_ES_NCE_MASK)
|
|
|
|
#define DMA_CH_ES_DOE_MASK (0x10U)
|
|
#define DMA_CH_ES_DOE_SHIFT (4U)
|
|
/*! DOE - Destination Offset Error
|
|
* 0b0..No destination offset configuration error
|
|
* 0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field
|
|
*/
|
|
#define DMA_CH_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DOE_SHIFT)) & DMA_CH_ES_DOE_MASK)
|
|
|
|
#define DMA_CH_ES_DAE_MASK (0x20U)
|
|
#define DMA_CH_ES_DAE_SHIFT (5U)
|
|
/*! DAE - Destination Address Error
|
|
* 0b0..No destination address configuration error
|
|
* 0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field
|
|
*/
|
|
#define DMA_CH_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DAE_SHIFT)) & DMA_CH_ES_DAE_MASK)
|
|
|
|
#define DMA_CH_ES_SOE_MASK (0x40U)
|
|
#define DMA_CH_ES_SOE_SHIFT (6U)
|
|
/*! SOE - Source Offset Error
|
|
* 0b0..No source offset configuration error
|
|
* 0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field
|
|
*/
|
|
#define DMA_CH_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SOE_SHIFT)) & DMA_CH_ES_SOE_MASK)
|
|
|
|
#define DMA_CH_ES_SAE_MASK (0x80U)
|
|
#define DMA_CH_ES_SAE_SHIFT (7U)
|
|
/*! SAE - Source Address Error
|
|
* 0b0..No source address configuration error
|
|
* 0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field
|
|
*/
|
|
#define DMA_CH_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SAE_SHIFT)) & DMA_CH_ES_SAE_MASK)
|
|
|
|
#define DMA_CH_ES_ERR_MASK (0x80000000U)
|
|
#define DMA_CH_ES_ERR_SHIFT (31U)
|
|
/*! ERR - Error In Channel
|
|
* 0b0..An error in this channel has not occurred
|
|
* 0b1..An error in this channel has occurred
|
|
*/
|
|
#define DMA_CH_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_ERR_SHIFT)) & DMA_CH_ES_ERR_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of DMA_CH_ES */
|
|
#define DMA_CH_ES_COUNT (4U)
|
|
|
|
/*! @name CH_INT - Channel Interrupt Status */
|
|
/*! @{ */
|
|
|
|
#define DMA_CH_INT_INT_MASK (0x1U)
|
|
#define DMA_CH_INT_INT_SHIFT (0U)
|
|
/*! INT - Interrupt Request
|
|
* 0b0..Interrupt request for corresponding channel cleared
|
|
* 0b1..Interrupt request for corresponding channel active
|
|
*/
|
|
#define DMA_CH_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of DMA_CH_INT */
|
|
#define DMA_CH_INT_COUNT (4U)
|
|
|
|
/*! @name CH_SBR - Channel System Bus */
|
|
/*! @{ */
|
|
|
|
#define DMA_CH_SBR_MID_MASK (0xFU)
|
|
#define DMA_CH_SBR_MID_SHIFT (0U)
|
|
/*! MID - Master ID */
|
|
#define DMA_CH_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_MID_SHIFT)) & DMA_CH_SBR_MID_MASK)
|
|
|
|
#define DMA_CH_SBR_PAL_MASK (0x8000U)
|
|
#define DMA_CH_SBR_PAL_SHIFT (15U)
|
|
/*! PAL - Privileged Access Level
|
|
* 0b0..User protection level for DMA transfers
|
|
* 0b1..Privileged protection level for DMA transfers
|
|
*/
|
|
#define DMA_CH_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_PAL_SHIFT)) & DMA_CH_SBR_PAL_MASK)
|
|
|
|
#define DMA_CH_SBR_EMI_MASK (0x10000U)
|
|
#define DMA_CH_SBR_EMI_SHIFT (16U)
|
|
/*! EMI - Enable Master ID Replication
|
|
* 0b0..Master ID replication is disabled
|
|
* 0b1..Master ID replication is enabled
|
|
*/
|
|
#define DMA_CH_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_EMI_SHIFT)) & DMA_CH_SBR_EMI_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of DMA_CH_SBR */
|
|
#define DMA_CH_SBR_COUNT (4U)
|
|
|
|
/*! @name CH_PRI - Channel Priority */
|
|
/*! @{ */
|
|
|
|
#define DMA_CH_PRI_APL_MASK (0x7U)
|
|
#define DMA_CH_PRI_APL_SHIFT (0U)
|
|
/*! APL - Arbitration Priority Level */
|
|
#define DMA_CH_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_APL_SHIFT)) & DMA_CH_PRI_APL_MASK)
|
|
|
|
#define DMA_CH_PRI_DPA_MASK (0x40000000U)
|
|
#define DMA_CH_PRI_DPA_SHIFT (30U)
|
|
/*! DPA - Disable Preempt Ability
|
|
* 0b0..Channel can suspend a lower-priority channel
|
|
* 0b1..Channel cannot suspend any other channel, regardless of channel priority
|
|
*/
|
|
#define DMA_CH_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_DPA_SHIFT)) & DMA_CH_PRI_DPA_MASK)
|
|
|
|
#define DMA_CH_PRI_ECP_MASK (0x80000000U)
|
|
#define DMA_CH_PRI_ECP_SHIFT (31U)
|
|
/*! ECP - Enable Channel Preemption
|
|
* 0b0..Channel cannot be suspended by a higher-priority channel's service request
|
|
* 0b1..Channel can be temporarily suspended by a higher-priority channel's service request
|
|
*/
|
|
#define DMA_CH_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_ECP_SHIFT)) & DMA_CH_PRI_ECP_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of DMA_CH_PRI */
|
|
#define DMA_CH_PRI_COUNT (4U)
|
|
|
|
/*! @name CH_MUX - Channel Multiplexor Configuration */
|
|
/*! @{ */
|
|
|
|
#define DMA_CH_MUX_SRC_MASK (0x7FU)
|
|
#define DMA_CH_MUX_SRC_SHIFT (0U)
|
|
/*! SRC - Service Request Source */
|
|
#define DMA_CH_MUX_SRC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_MUX_SRC_SHIFT)) & DMA_CH_MUX_SRC_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of DMA_CH_MUX */
|
|
#define DMA_CH_MUX_COUNT (4U)
|
|
|
|
/*! @name TCD_SADDR - TCD Source Address */
|
|
/*! @{ */
|
|
|
|
#define DMA_TCD_SADDR_SADDR_MASK (0xFFFFFFFFU)
|
|
#define DMA_TCD_SADDR_SADDR_SHIFT (0U)
|
|
/*! SADDR - Source Address */
|
|
#define DMA_TCD_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SADDR_SADDR_SHIFT)) & DMA_TCD_SADDR_SADDR_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of DMA_TCD_SADDR */
|
|
#define DMA_TCD_SADDR_COUNT (4U)
|
|
|
|
/*! @name TCD_SOFF - TCD Signed Source Address Offset */
|
|
/*! @{ */
|
|
|
|
#define DMA_TCD_SOFF_SOFF_MASK (0xFFFFU)
|
|
#define DMA_TCD_SOFF_SOFF_SHIFT (0U)
|
|
/*! SOFF - Source Address Signed Offset */
|
|
#define DMA_TCD_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_SOFF_SOFF_SHIFT)) & DMA_TCD_SOFF_SOFF_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of DMA_TCD_SOFF */
|
|
#define DMA_TCD_SOFF_COUNT (4U)
|
|
|
|
/*! @name TCD_ATTR - TCD Transfer Attributes */
|
|
/*! @{ */
|
|
|
|
#define DMA_TCD_ATTR_DSIZE_MASK (0x7U)
|
|
#define DMA_TCD_ATTR_DSIZE_SHIFT (0U)
|
|
/*! DSIZE - Destination Data Transfer Size */
|
|
#define DMA_TCD_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DSIZE_SHIFT)) & DMA_TCD_ATTR_DSIZE_MASK)
|
|
|
|
#define DMA_TCD_ATTR_DMOD_MASK (0xF8U)
|
|
#define DMA_TCD_ATTR_DMOD_SHIFT (3U)
|
|
/*! DMOD - Destination Address Modulo */
|
|
#define DMA_TCD_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DMOD_SHIFT)) & DMA_TCD_ATTR_DMOD_MASK)
|
|
|
|
#define DMA_TCD_ATTR_SSIZE_MASK (0x700U)
|
|
#define DMA_TCD_ATTR_SSIZE_SHIFT (8U)
|
|
/*! SSIZE - Source Data Transfer Size
|
|
* 0b000..8-bit
|
|
* 0b001..16-bit
|
|
* 0b010..32-bit
|
|
* 0b011..64-bit
|
|
* 0b100..16-byte
|
|
* 0b101..32-byte
|
|
* 0b110..
|
|
* 0b111..
|
|
*/
|
|
#define DMA_TCD_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SSIZE_SHIFT)) & DMA_TCD_ATTR_SSIZE_MASK)
|
|
|
|
#define DMA_TCD_ATTR_SMOD_MASK (0xF800U)
|
|
#define DMA_TCD_ATTR_SMOD_SHIFT (11U)
|
|
/*! SMOD - Source Address Modulo
|
|
* 0b00000..Source address modulo feature disabled
|
|
* 0b00001..Source address modulo feature enabled for any non-zero value [1-31]
|
|
*/
|
|
#define DMA_TCD_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SMOD_SHIFT)) & DMA_TCD_ATTR_SMOD_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of DMA_TCD_ATTR */
|
|
#define DMA_TCD_ATTR_COUNT (4U)
|
|
|
|
/*! @name TCD_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */
|
|
/*! @{ */
|
|
|
|
#define DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
|
|
#define DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
|
|
/*! NBYTES - Number of Bytes To Transfer Per Service Request */
|
|
#define DMA_TCD_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK)
|
|
|
|
#define DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
|
|
#define DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
|
|
/*! DMLOE - Destination Minor Loop Offset Enable
|
|
* 0b0..Minor loop offset not applied to DADDR
|
|
* 0b1..Minor loop offset applied to DADDR
|
|
*/
|
|
#define DMA_TCD_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK)
|
|
|
|
#define DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
|
|
#define DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
|
|
/*! SMLOE - Source Minor Loop Offset Enable
|
|
* 0b0..Minor loop offset not applied to SADDR
|
|
* 0b1..Minor loop offset applied to SADDR
|
|
*/
|
|
#define DMA_TCD_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of DMA_TCD_NBYTES_MLOFFNO */
|
|
#define DMA_TCD_NBYTES_MLOFFNO_COUNT (4U)
|
|
|
|
/*! @name TCD_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */
|
|
/*! @{ */
|
|
|
|
#define DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
|
|
#define DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
|
|
/*! NBYTES - Number of Bytes To Transfer Per Service Request */
|
|
#define DMA_TCD_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK)
|
|
|
|
#define DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
|
|
#define DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
|
|
/*! MLOFF - Minor Loop Offset */
|
|
#define DMA_TCD_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK)
|
|
|
|
#define DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
|
|
#define DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
|
|
/*! DMLOE - Destination Minor Loop Offset Enable
|
|
* 0b0..Minor loop offset not applied to DADDR
|
|
* 0b1..Minor loop offset applied to DADDR
|
|
*/
|
|
#define DMA_TCD_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK)
|
|
|
|
#define DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
|
|
#define DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
|
|
/*! SMLOE - Source Minor Loop Offset Enable
|
|
* 0b0..Minor loop offset not applied to SADDR
|
|
* 0b1..Minor loop offset applied to SADDR
|
|
*/
|
|
#define DMA_TCD_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of DMA_TCD_NBYTES_MLOFFYES */
|
|
#define DMA_TCD_NBYTES_MLOFFYES_COUNT (4U)
|
|
|
|
/*! @name TCD_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */
|
|
/*! @{ */
|
|
|
|
#define DMA_TCD_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU)
|
|
#define DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT (0U)
|
|
/*! SLAST_SDA - Last Source Address Adjustment / Store DADDR Address */
|
|
#define DMA_TCD_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_SLAST_SDA_SLAST_SDA_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of DMA_TCD_SLAST_SDA */
|
|
#define DMA_TCD_SLAST_SDA_COUNT (4U)
|
|
|
|
/*! @name TCD_DADDR - TCD Destination Address */
|
|
/*! @{ */
|
|
|
|
#define DMA_TCD_DADDR_DADDR_MASK (0xFFFFFFFFU)
|
|
#define DMA_TCD_DADDR_DADDR_SHIFT (0U)
|
|
/*! DADDR - Destination Address */
|
|
#define DMA_TCD_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DADDR_DADDR_SHIFT)) & DMA_TCD_DADDR_DADDR_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of DMA_TCD_DADDR */
|
|
#define DMA_TCD_DADDR_COUNT (4U)
|
|
|
|
/*! @name TCD_DOFF - TCD Signed Destination Address Offset */
|
|
/*! @{ */
|
|
|
|
#define DMA_TCD_DOFF_DOFF_MASK (0xFFFFU)
|
|
#define DMA_TCD_DOFF_DOFF_SHIFT (0U)
|
|
/*! DOFF - Destination Address Signed Offset */
|
|
#define DMA_TCD_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_DOFF_DOFF_SHIFT)) & DMA_TCD_DOFF_DOFF_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of DMA_TCD_DOFF */
|
|
#define DMA_TCD_DOFF_COUNT (4U)
|
|
|
|
/*! @name TCD_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */
|
|
/*! @{ */
|
|
|
|
#define DMA_TCD_CITER_ELINKNO_CITER_MASK (0x7FFFU)
|
|
#define DMA_TCD_CITER_ELINKNO_CITER_SHIFT (0U)
|
|
/*! CITER - Current Major Iteration Count */
|
|
#define DMA_TCD_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_CITER_ELINKNO_CITER_MASK)
|
|
|
|
#define DMA_TCD_CITER_ELINKNO_ELINK_MASK (0x8000U)
|
|
#define DMA_TCD_CITER_ELINKNO_ELINK_SHIFT (15U)
|
|
/*! ELINK - Enable Link
|
|
* 0b0..Channel-to-channel linking disabled
|
|
* 0b1..Channel-to-channel linking enabled
|
|
*/
|
|
#define DMA_TCD_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKNO_ELINK_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of DMA_TCD_CITER_ELINKNO */
|
|
#define DMA_TCD_CITER_ELINKNO_COUNT (4U)
|
|
|
|
/*! @name TCD_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */
|
|
/*! @{ */
|
|
|
|
#define DMA_TCD_CITER_ELINKYES_CITER_MASK (0x1FFU)
|
|
#define DMA_TCD_CITER_ELINKYES_CITER_SHIFT (0U)
|
|
/*! CITER - Current Major Iteration Count */
|
|
#define DMA_TCD_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_CITER_ELINKYES_CITER_MASK)
|
|
|
|
#define DMA_TCD_CITER_ELINKYES_LINKCH_MASK (0x600U)
|
|
#define DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT (9U)
|
|
/*! LINKCH - Minor Loop Link Channel Number */
|
|
#define DMA_TCD_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_CITER_ELINKYES_LINKCH_MASK)
|
|
|
|
#define DMA_TCD_CITER_ELINKYES_ELINK_MASK (0x8000U)
|
|
#define DMA_TCD_CITER_ELINKYES_ELINK_SHIFT (15U)
|
|
/*! ELINK - Enable Link
|
|
* 0b0..Channel-to-channel linking disabled
|
|
* 0b1..Channel-to-channel linking enabled
|
|
*/
|
|
#define DMA_TCD_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKYES_ELINK_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of DMA_TCD_CITER_ELINKYES */
|
|
#define DMA_TCD_CITER_ELINKYES_COUNT (4U)
|
|
|
|
/*! @name TCD_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */
|
|
/*! @{ */
|
|
|
|
#define DMA_TCD_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU)
|
|
#define DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT (0U)
|
|
/*! DLAST_SGA - Last Destination Address Adjustment / Scatter Gather Address */
|
|
#define DMA_TCD_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_DLAST_SGA_DLAST_SGA_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of DMA_TCD_DLAST_SGA */
|
|
#define DMA_TCD_DLAST_SGA_COUNT (4U)
|
|
|
|
/*! @name TCD_CSR - TCD Control and Status */
|
|
/*! @{ */
|
|
|
|
#define DMA_TCD_CSR_START_MASK (0x1U)
|
|
#define DMA_TCD_CSR_START_SHIFT (0U)
|
|
/*! START - Channel Start
|
|
* 0b0..Channel not explicitly started
|
|
* 0b1..Channel explicitly started via a software-initiated service request
|
|
*/
|
|
#define DMA_TCD_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_START_SHIFT)) & DMA_TCD_CSR_START_MASK)
|
|
|
|
#define DMA_TCD_CSR_INTMAJOR_MASK (0x2U)
|
|
#define DMA_TCD_CSR_INTMAJOR_SHIFT (1U)
|
|
/*! INTMAJOR - Enable Interrupt If Major count complete
|
|
* 0b0..End-of-major loop interrupt disabled
|
|
* 0b1..End-of-major loop interrupt enabled
|
|
*/
|
|
#define DMA_TCD_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTMAJOR_SHIFT)) & DMA_TCD_CSR_INTMAJOR_MASK)
|
|
|
|
#define DMA_TCD_CSR_INTHALF_MASK (0x4U)
|
|
#define DMA_TCD_CSR_INTHALF_SHIFT (2U)
|
|
/*! INTHALF - Enable Interrupt If Major Counter Half-complete
|
|
* 0b0..Halfway point interrupt disabled
|
|
* 0b1..Halfway point interrupt enabled
|
|
*/
|
|
#define DMA_TCD_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTHALF_SHIFT)) & DMA_TCD_CSR_INTHALF_MASK)
|
|
|
|
#define DMA_TCD_CSR_DREQ_MASK (0x8U)
|
|
#define DMA_TCD_CSR_DREQ_SHIFT (3U)
|
|
/*! DREQ - Disable Request
|
|
* 0b0..No operation
|
|
* 0b1..Clear the ERQ field to 0 upon major loop completion, thus disabling hardware service requests
|
|
*/
|
|
#define DMA_TCD_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK)
|
|
|
|
#define DMA_TCD_CSR_ESG_MASK (0x10U)
|
|
#define DMA_TCD_CSR_ESG_SHIFT (4U)
|
|
/*! ESG - Enable Scatter/Gather Processing
|
|
* 0b0..Current channel's TCD is normal format
|
|
* 0b1..Current channel's TCD specifies scatter/gather format.
|
|
*/
|
|
#define DMA_TCD_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESG_SHIFT)) & DMA_TCD_CSR_ESG_MASK)
|
|
|
|
#define DMA_TCD_CSR_MAJORELINK_MASK (0x20U)
|
|
#define DMA_TCD_CSR_MAJORELINK_SHIFT (5U)
|
|
/*! MAJORELINK - Enable Link When Major Loop Complete
|
|
* 0b0..Channel-to-channel linking disabled
|
|
* 0b1..Channel-to-channel linking enabled
|
|
*/
|
|
#define DMA_TCD_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORELINK_SHIFT)) & DMA_TCD_CSR_MAJORELINK_MASK)
|
|
|
|
#define DMA_TCD_CSR_EEOP_MASK (0x40U)
|
|
#define DMA_TCD_CSR_EEOP_SHIFT (6U)
|
|
/*! EEOP - Enable End-Of-Packet Processing
|
|
* 0b0..End-of-packet operation disabled
|
|
* 0b1..End-of-packet hardware input signal enabled
|
|
*/
|
|
#define DMA_TCD_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_EEOP_SHIFT)) & DMA_TCD_CSR_EEOP_MASK)
|
|
|
|
#define DMA_TCD_CSR_ESDA_MASK (0x80U)
|
|
#define DMA_TCD_CSR_ESDA_SHIFT (7U)
|
|
/*! ESDA - Enable Store Destination Address
|
|
* 0b0..Ability to store destination address to system memory disabled
|
|
* 0b1..Ability to store destination address to system memory enabled
|
|
*/
|
|
#define DMA_TCD_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESDA_SHIFT)) & DMA_TCD_CSR_ESDA_MASK)
|
|
|
|
#define DMA_TCD_CSR_MAJORLINKCH_MASK (0x300U)
|
|
#define DMA_TCD_CSR_MAJORLINKCH_SHIFT (8U)
|
|
/*! MAJORLINKCH - Major Loop Link Channel Number */
|
|
#define DMA_TCD_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_CSR_MAJORLINKCH_MASK)
|
|
|
|
#define DMA_TCD_CSR_BWC_MASK (0xC000U)
|
|
#define DMA_TCD_CSR_BWC_SHIFT (14U)
|
|
/*! BWC - Bandwidth Control
|
|
* 0b00..No eDMA engine stalls
|
|
* 0b01..
|
|
* 0b10..eDMA engine stalls for 4 cycles after each R/W
|
|
* 0b11..eDMA engine stalls for 8 cycles after each R/W
|
|
*/
|
|
#define DMA_TCD_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_BWC_SHIFT)) & DMA_TCD_CSR_BWC_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of DMA_TCD_CSR */
|
|
#define DMA_TCD_CSR_COUNT (4U)
|
|
|
|
/*! @name TCD_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */
|
|
/*! @{ */
|
|
|
|
#define DMA_TCD_BITER_ELINKNO_BITER_MASK (0x7FFFU)
|
|
#define DMA_TCD_BITER_ELINKNO_BITER_SHIFT (0U)
|
|
/*! BITER - Starting Major Iteration Count */
|
|
#define DMA_TCD_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_BITER_ELINKNO_BITER_MASK)
|
|
|
|
#define DMA_TCD_BITER_ELINKNO_ELINK_MASK (0x8000U)
|
|
#define DMA_TCD_BITER_ELINKNO_ELINK_SHIFT (15U)
|
|
/*! ELINK - Enables Link
|
|
* 0b0..Channel-to-channel linking disabled
|
|
* 0b1..Channel-to-channel linking enabled
|
|
*/
|
|
#define DMA_TCD_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKNO_ELINK_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of DMA_TCD_BITER_ELINKNO */
|
|
#define DMA_TCD_BITER_ELINKNO_COUNT (4U)
|
|
|
|
/*! @name TCD_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */
|
|
/*! @{ */
|
|
|
|
#define DMA_TCD_BITER_ELINKYES_BITER_MASK (0x1FFU)
|
|
#define DMA_TCD_BITER_ELINKYES_BITER_SHIFT (0U)
|
|
/*! BITER - Starting Major Iteration Count */
|
|
#define DMA_TCD_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_BITER_ELINKYES_BITER_MASK)
|
|
|
|
#define DMA_TCD_BITER_ELINKYES_LINKCH_MASK (0x600U)
|
|
#define DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT (9U)
|
|
/*! LINKCH - Link Channel Number */
|
|
#define DMA_TCD_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_BITER_ELINKYES_LINKCH_MASK)
|
|
|
|
#define DMA_TCD_BITER_ELINKYES_ELINK_MASK (0x8000U)
|
|
#define DMA_TCD_BITER_ELINKYES_ELINK_SHIFT (15U)
|
|
/*! ELINK - Enable Link
|
|
* 0b0..Channel-to-channel linking disabled
|
|
* 0b1..Channel-to-channel linking enabled
|
|
*/
|
|
#define DMA_TCD_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKYES_ELINK_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of DMA_TCD_BITER_ELINKYES */
|
|
#define DMA_TCD_BITER_ELINKYES_COUNT (4U)
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group DMA_Register_Masks */
|
|
|
|
|
|
/* DMA - Peripheral instance base addresses */
|
|
/** Peripheral DMA0 base address */
|
|
#define DMA0_BASE (0x40080000u)
|
|
/** Peripheral DMA0 base pointer */
|
|
#define DMA0 ((DMA_Type *)DMA0_BASE)
|
|
/** Array initializer of DMA peripheral base addresses */
|
|
#define DMA_BASE_ADDRS { DMA0_BASE }
|
|
/** Array initializer of DMA peripheral base pointers */
|
|
#define DMA_BASE_PTRS { DMA0 }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group DMA_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- EIM Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup EIM_Peripheral_Access_Layer EIM Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** EIM - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t EIMCR; /**< Error Injection Module Configuration Register, offset: 0x0 */
|
|
__IO uint32_t EICHEN; /**< Error Injection Channel Enable register, offset: 0x4 */
|
|
uint8_t RESERVED_0[248];
|
|
__IO uint32_t EICHD0_WORD0; /**< Error Injection Channel Descriptor 0, Word0, offset: 0x100 */
|
|
__IO uint32_t EICHD0_WORD1; /**< Error Injection Channel Descriptor 0, Word1, offset: 0x104 */
|
|
} EIM_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- EIM Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup EIM_Register_Masks EIM Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name EIMCR - Error Injection Module Configuration Register */
|
|
/*! @{ */
|
|
|
|
#define EIM_EIMCR_GEIEN_MASK (0x1U)
|
|
#define EIM_EIMCR_GEIEN_SHIFT (0U)
|
|
/*! GEIEN - Global Error Injection Enable
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define EIM_EIMCR_GEIEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EIMCR_GEIEN_SHIFT)) & EIM_EIMCR_GEIEN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name EICHEN - Error Injection Channel Enable register */
|
|
/*! @{ */
|
|
|
|
#define EIM_EICHEN_EICH0EN_MASK (0x80000000U)
|
|
#define EIM_EICHEN_EICH0EN_SHIFT (31U)
|
|
/*! EICH0EN - Error Injection Channel 0 Enable
|
|
* 0b0..Error injection is disabled on Error Injection Channel 0
|
|
* 0b1..Error injection is enabled on Error Injection Channel 0
|
|
*/
|
|
#define EIM_EICHEN_EICH0EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH0EN_SHIFT)) & EIM_EICHEN_EICH0EN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name EICHD0_WORD0 - Error Injection Channel Descriptor 0, Word0 */
|
|
/*! @{ */
|
|
|
|
#define EIM_EICHD0_WORD0_CHKBIT_MASK_MASK (0xFE000000U)
|
|
#define EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT (25U)
|
|
/*! CHKBIT_MASK - Checkbit Mask */
|
|
#define EIM_EICHD0_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD0_WORD0_CHKBIT_MASK_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name EICHD0_WORD1 - Error Injection Channel Descriptor 0, Word1 */
|
|
/*! @{ */
|
|
|
|
#define EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU)
|
|
#define EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT (0U)
|
|
/*! B0_3DATA_MASK - Data Mask Bytes 0-3 */
|
|
#define EIM_EICHD0_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group EIM_Register_Masks */
|
|
|
|
|
|
/* EIM - Peripheral instance base addresses */
|
|
/** Peripheral EIM0 base address */
|
|
#define EIM0_BASE (0x4008C000u)
|
|
/** Peripheral EIM0 base pointer */
|
|
#define EIM0 ((EIM_Type *)EIM0_BASE)
|
|
/** Array initializer of EIM peripheral base addresses */
|
|
#define EIM_BASE_ADDRS { EIM0_BASE }
|
|
/** Array initializer of EIM peripheral base pointers */
|
|
#define EIM_BASE_PTRS { EIM0 }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group EIM_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- EQDC Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup EQDC_Peripheral_Access_Layer EQDC Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** EQDC - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint16_t CTRL; /**< Control Register, offset: 0x0 */
|
|
__IO uint16_t CTRL2; /**< Control 2 Register, offset: 0x2 */
|
|
__IO uint16_t FILT; /**< Input Filter Register, offset: 0x4 */
|
|
__I uint16_t LASTEDGE; /**< Last Edge Time Register, offset: 0x6 */
|
|
__I uint16_t POSDPER; /**< Position Difference Period Counter Register, offset: 0x8 */
|
|
__I uint16_t POSDPERBFR; /**< Position Difference Period Buffer Register, offset: 0xA */
|
|
__IO uint16_t UPOS; /**< Upper Position Counter Register, offset: 0xC */
|
|
__IO uint16_t LPOS; /**< Lower Position Counter Register, offset: 0xE */
|
|
__IO uint16_t POSD; /**< Position Difference Counter Register, offset: 0x10 */
|
|
__I uint16_t POSDH; /**< Position Difference Hold Register, offset: 0x12 */
|
|
__I uint16_t UPOSH; /**< Upper Position Hold Register, offset: 0x14 */
|
|
__I uint16_t LPOSH; /**< Lower Position Hold Register, offset: 0x16 */
|
|
__I uint16_t LASTEDGEH; /**< Last Edge Time Hold Register, offset: 0x18 */
|
|
__I uint16_t POSDPERH; /**< Position Difference Period Hold Register, offset: 0x1A */
|
|
__I uint16_t REVH; /**< Revolution Hold Register, offset: 0x1C */
|
|
__IO uint16_t REV; /**< Revolution Counter Register, offset: 0x1E */
|
|
__IO uint16_t UINIT; /**< Upper Initialization Register, offset: 0x20 */
|
|
__IO uint16_t LINIT; /**< Lower Initialization Register, offset: 0x22 */
|
|
__IO uint16_t UMOD; /**< Upper Modulus Register, offset: 0x24 */
|
|
__IO uint16_t LMOD; /**< Lower Modulus Register, offset: 0x26 */
|
|
__IO uint16_t UCOMP0; /**< Upper Position Compare Register 0, offset: 0x28 */
|
|
__IO uint16_t LCOMP0; /**< Lower Position Compare Register 0, offset: 0x2A */
|
|
union { /* offset: 0x2C */
|
|
__O uint16_t UCOMP1; /**< Upper Position Compare 1, offset: 0x2C */
|
|
__I uint16_t UPOSH1; /**< Upper Position Holder Register 1, offset: 0x2C */
|
|
};
|
|
union { /* offset: 0x2E */
|
|
__O uint16_t LCOMP1; /**< Lower Position Compare 1, offset: 0x2E */
|
|
__I uint16_t LPOSH1; /**< Lower Position Holder Register 1, offset: 0x2E */
|
|
};
|
|
union { /* offset: 0x30 */
|
|
__O uint16_t UCOMP2; /**< Upper Position Compare 2, offset: 0x30 */
|
|
__I uint16_t UPOSH2; /**< Upper Position Holder Register 3, offset: 0x30 */
|
|
};
|
|
union { /* offset: 0x32 */
|
|
__O uint16_t LCOMP2; /**< Lower Position Compare 2, offset: 0x32 */
|
|
__I uint16_t LPOSH2; /**< Lower Position Holder Register 2, offset: 0x32 */
|
|
};
|
|
union { /* offset: 0x34 */
|
|
__O uint16_t UCOMP3; /**< Upper Position Compare 3, offset: 0x34 */
|
|
__I uint16_t UPOSH3; /**< Upper Position Holder Register 3, offset: 0x34 */
|
|
};
|
|
union { /* offset: 0x36 */
|
|
__O uint16_t LCOMP3; /**< Lower Position Compare 3, offset: 0x36 */
|
|
__I uint16_t LPOSH3; /**< Lower Position Holder Register 3, offset: 0x36 */
|
|
};
|
|
__IO uint16_t INTCTRL; /**< Interrupt Control Register, offset: 0x38 */
|
|
__IO uint16_t WTR; /**< Watchdog Timeout Register, offset: 0x3A */
|
|
__IO uint16_t IMR; /**< Input Monitor Register, offset: 0x3C */
|
|
__IO uint16_t TST; /**< Test Register, offset: 0x3E */
|
|
uint8_t RESERVED_0[16];
|
|
__I uint16_t UVERID; /**< Upper VERID, offset: 0x50 */
|
|
__I uint16_t LVERID; /**< Lower VERID, offset: 0x52 */
|
|
} EQDC_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- EQDC Register Masks
|
|
---------------------------------------------------------------------------- */
|
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/*!
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* @addtogroup EQDC_Register_Masks EQDC Register Masks
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* @{
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*/
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/*! @name CTRL - Control Register */
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/*! @{ */
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#define EQDC_CTRL_LDOK_MASK (0x1U)
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#define EQDC_CTRL_LDOK_SHIFT (0U)
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/*! LDOK - Load Okay
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* 0b0..No loading action taken. Users can write new values to buffered registers (writing into outer-set of these buffered registers)
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* 0b1..Outer-set values are ready to be loaded into inner-set and take effect. The loading time point depends on CTRL2[LDMOD].
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*/
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#define EQDC_CTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_LDOK_SHIFT)) & EQDC_CTRL_LDOK_MASK)
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#define EQDC_CTRL_DMAEN_MASK (0x2U)
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#define EQDC_CTRL_DMAEN_SHIFT (1U)
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/*! DMAEN - DMA Enable
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* 0b0..DMA is disabled
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* 0b1..DMA is enabled. DMA request asserts automatically when the values in the outer-set of buffered compare
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* registers (UCOMP0/LCOMP0;UCOMP1/LCOMP1;UCOMP2/LCOMP2;UCOMP3/LCOMP3), initial registers(UINIT/LINIT) and
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* modulus registers (UMOD/LMOD) are loaded into the inner-set of buffer and then LDOK is cleared automatically.
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* After the completion of this DMA transfer, LDOK is set automatically, it ensures outer-set values can be
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* loaded into inner-set which in turn triggers DMA again.
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*/
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#define EQDC_CTRL_DMAEN(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_DMAEN_SHIFT)) & EQDC_CTRL_DMAEN_MASK)
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#define EQDC_CTRL_WDE_MASK (0x4U)
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#define EQDC_CTRL_WDE_SHIFT (2U)
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/*! WDE - Watchdog Enable
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* 0b0..Disabled
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* 0b1..Enabled
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*/
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#define EQDC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_WDE_SHIFT)) & EQDC_CTRL_WDE_MASK)
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#define EQDC_CTRL_WDIE_MASK (0x8U)
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#define EQDC_CTRL_WDIE_SHIFT (3U)
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/*! WDIE - Watchdog Timeout Interrupt Enable
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* 0b0..Disabled
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* 0b1..Enabled
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*/
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#define EQDC_CTRL_WDIE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_WDIE_SHIFT)) & EQDC_CTRL_WDIE_MASK)
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#define EQDC_CTRL_WDIRQ_MASK (0x10U)
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#define EQDC_CTRL_WDIRQ_SHIFT (4U)
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/*! WDIRQ - Watchdog Timeout Interrupt Request
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* 0b0..No Watchdog timeout interrupt has occurred
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* 0b1..Watchdog timeout interrupt has occurred
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*/
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#define EQDC_CTRL_WDIRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_WDIRQ_SHIFT)) & EQDC_CTRL_WDIRQ_MASK)
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#define EQDC_CTRL_XNE_MASK (0x20U)
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#define EQDC_CTRL_XNE_SHIFT (5U)
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/*! XNE - Select Positive/Negative Edge of INDEX/PRESET Pulse
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* 0b0..Use positive edge of INDEX/PRESET pulse
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* 0b1..Use negative edge of INDEX/PRESET pulse
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*/
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#define EQDC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_XNE_SHIFT)) & EQDC_CTRL_XNE_MASK)
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#define EQDC_CTRL_XIP_MASK (0x40U)
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#define EQDC_CTRL_XIP_SHIFT (6U)
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/*! XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS
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* 0b0..INDEX pulse does not initialize the position counter
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* 0b1..INDEX pulse initializes the position counter
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*/
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#define EQDC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_XIP_SHIFT)) & EQDC_CTRL_XIP_MASK)
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#define EQDC_CTRL_XIE_MASK (0x80U)
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#define EQDC_CTRL_XIE_SHIFT (7U)
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/*! XIE - INDEX/PRESET Pulse Interrupt Enable
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* 0b0..Disabled
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* 0b1..Enabled
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*/
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#define EQDC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_XIE_SHIFT)) & EQDC_CTRL_XIE_MASK)
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#define EQDC_CTRL_XIRQ_MASK (0x100U)
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#define EQDC_CTRL_XIRQ_SHIFT (8U)
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/*! XIRQ - INDEX/PRESET Pulse Interrupt Request
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* 0b0..INDEX/PRESET pulse has not occurred
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* 0b1..INDEX/PRESET pulse has occurred
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*/
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#define EQDC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_XIRQ_SHIFT)) & EQDC_CTRL_XIRQ_MASK)
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#define EQDC_CTRL_PH1_MASK (0x200U)
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#define EQDC_CTRL_PH1_SHIFT (9U)
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/*! PH1 - Enable Single Phase Mode
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* 0b0..Standard quadrature decoder, where PHASEA and PHASEB represent a two-phase quadrature signal.
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* 0b1..Single phase mode, bypass the quadrature decoder, refer to CTRL2[CMODE] description
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*/
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#define EQDC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_PH1_SHIFT)) & EQDC_CTRL_PH1_MASK)
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#define EQDC_CTRL_REV_MASK (0x400U)
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#define EQDC_CTRL_REV_SHIFT (10U)
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/*! REV - Enable Reverse Direction Counting
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* 0b0..Count normally and the position counter initialization uses upper/lower initialization register UINIT/LINIT
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* 0b1..Count in the reverse direction and the position counter initialization uses upper/lower modulus register UMOD/LMOD
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*/
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#define EQDC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_REV_SHIFT)) & EQDC_CTRL_REV_MASK)
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#define EQDC_CTRL_SWIP_MASK (0x800U)
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#define EQDC_CTRL_SWIP_SHIFT (11U)
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/*! SWIP - Software-Triggered Initialization of Position Counters UPOS and LPOS
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* 0b0..No action
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* 0b1..Initialize position counter
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*/
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#define EQDC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_SWIP_SHIFT)) & EQDC_CTRL_SWIP_MASK)
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#define EQDC_CTRL_HNE_MASK (0x1000U)
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#define EQDC_CTRL_HNE_SHIFT (12U)
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/*! HNE - Use Negative Edge of HOME/ENABLE Input
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* 0b0..When CTRL[OPMODE] = 0,use HOME positive edge to trigger initialization of position counters. When
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* CTRL[OPMODE] = 1,use ENABLE high level to enable POS/POSD/WDG/REV counters
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* 0b1..When CTRL[OPMODE] = 0,use HOME negative edge to trigger initialization of position counters. When
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* CTRL[OPMODE] = 1,use ENABLE low level to enable POS/POSD/WDG/REV counters
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*/
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#define EQDC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_HNE_SHIFT)) & EQDC_CTRL_HNE_MASK)
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#define EQDC_CTRL_HIP_MASK (0x2000U)
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#define EQDC_CTRL_HIP_SHIFT (13U)
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/*! HIP - Enable HOME to Initialize Position Counter UPOS/LPOS
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* 0b0..No action
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* 0b1..HOME signal initializes the position counter
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*/
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#define EQDC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_HIP_SHIFT)) & EQDC_CTRL_HIP_MASK)
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#define EQDC_CTRL_HIE_MASK (0x4000U)
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#define EQDC_CTRL_HIE_SHIFT (14U)
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/*! HIE - HOME/ENABLE Interrupt Enable
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* 0b0..Disabled
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* 0b1..Enabled
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*/
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#define EQDC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_HIE_SHIFT)) & EQDC_CTRL_HIE_MASK)
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#define EQDC_CTRL_HIRQ_MASK (0x8000U)
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#define EQDC_CTRL_HIRQ_SHIFT (15U)
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/*! HIRQ - HOME/ENABLE Signal Transition Interrupt Request
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* 0b0..No transition on the HOME/ENABLE signal has occurred
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* 0b1..A transition on the HOME/ENABLE signal has occurred
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*/
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#define EQDC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_HIRQ_SHIFT)) & EQDC_CTRL_HIRQ_MASK)
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/*! @} */
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/*! @name CTRL2 - Control 2 Register */
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/*! @{ */
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#define EQDC_CTRL2_UPDHLD_MASK (0x1U)
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#define EQDC_CTRL2_UPDHLD_SHIFT (0U)
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/*! UPDHLD - Update Hold Registers */
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#define EQDC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_UPDHLD_SHIFT)) & EQDC_CTRL2_UPDHLD_MASK)
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#define EQDC_CTRL2_UPDPOS_MASK (0x2U)
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#define EQDC_CTRL2_UPDPOS_SHIFT (1U)
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/*! UPDPOS - Update Position Registers */
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#define EQDC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_UPDPOS_SHIFT)) & EQDC_CTRL2_UPDPOS_MASK)
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#define EQDC_CTRL2_OPMODE_MASK (0x4U)
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#define EQDC_CTRL2_OPMODE_SHIFT (2U)
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/*! OPMODE - Operation Mode Select
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* 0b0..Decode Mode: Input nodes INDEX/PRESET and HOME/ENABLE are assigned to function of INDEX and HOME.
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* 0b1..Count Mode: Input nodes INDEX/PRESET and HOME/ENABLE are assigned to functions of PRESET and ENABLE. In
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* this mode: (1)only when ENABLE=1, all counters (position/position difference/revolution/watchdog) can run,
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* when ENABLE=0, all counters (position/position difference/revolution/watchdog) can't run. (2) the rising
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* edge of PRESET input can initialize position/revolution/watchdog counters (position counter initialization
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* also need referring to bit CTRL[REV]).
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*/
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#define EQDC_CTRL2_OPMODE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_OPMODE_SHIFT)) & EQDC_CTRL2_OPMODE_MASK)
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#define EQDC_CTRL2_LDMOD_MASK (0x8U)
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#define EQDC_CTRL2_LDMOD_SHIFT (3U)
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/*! LDMOD - Buffered Register Load (Update) Mode Select
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* 0b0..Buffered registers are loaded and take effect immediately upon CTRL[LDOK] is set.
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* 0b1..Buffered registers are loaded and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.
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*/
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#define EQDC_CTRL2_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_LDMOD_SHIFT)) & EQDC_CTRL2_LDMOD_MASK)
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#define EQDC_CTRL2_REVMOD_MASK (0x100U)
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#define EQDC_CTRL2_REVMOD_SHIFT (8U)
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/*! REVMOD - Revolution Counter Modulus Enable
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* 0b0..Use INDEX pulse to increment/decrement revolution counter (REV)
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* 0b1..Use modulus counting roll-over/under to increment/decrement revolution counter (REV)
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*/
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#define EQDC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_REVMOD_SHIFT)) & EQDC_CTRL2_REVMOD_MASK)
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#define EQDC_CTRL2_OUTCTL_MASK (0x200U)
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#define EQDC_CTRL2_OUTCTL_SHIFT (9U)
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/*! OUTCTL - Output Control
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* 0b0..POS_MATCH[x](x range is 0-3) is asserted when the Position Counter is equal to according compare value
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* (UCOMPx/LCOMPx)(x range is 0-3), and de-asserted when the Position Counter not equal to the compare value
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* (UCOMPx/LCOMPx)(x range is 0-3)
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* 0b1..All POS_MATCH[x](x range is 0-3) are asserted a pulse, when the UPOS, LPOS, REV, or POSD registers are read
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*/
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#define EQDC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_OUTCTL_SHIFT)) & EQDC_CTRL2_OUTCTL_MASK)
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#define EQDC_CTRL2_PMEN_MASK (0x400U)
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#define EQDC_CTRL2_PMEN_SHIFT (10U)
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/*! PMEN - Period measurement function enable
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* 0b0..Period measurement functions are not used. POSD is loaded to POSDH and then cleared whenever POSD, UPOS, LPOS or REV is read.
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* 0b1..Period measurement functions are used. POSD is loaded into POSDH and then cleared only when POSD is read.
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*/
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#define EQDC_CTRL2_PMEN(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_PMEN_SHIFT)) & EQDC_CTRL2_PMEN_MASK)
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#define EQDC_CTRL2_EMIP_MASK (0x800U)
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#define EQDC_CTRL2_EMIP_SHIFT (11U)
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/*! EMIP - Enables/disables the position counter to be initialized by Index Event Edge Mark
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* 0b0..disables the position counter to be initialized by Index Event Edge Mark
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* 0b1..enables the position counter to be initialized by Index Event Edge Mark.
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*/
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#define EQDC_CTRL2_EMIP(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_EMIP_SHIFT)) & EQDC_CTRL2_EMIP_MASK)
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#define EQDC_CTRL2_INITPOS_MASK (0x1000U)
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#define EQDC_CTRL2_INITPOS_SHIFT (12U)
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/*! INITPOS - Initial Position Register
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* 0b0..Don't initialize position counter on rising edge of TRIGGER
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* 0b1..Initialize position counter on rising edge of TRIGGER
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*/
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#define EQDC_CTRL2_INITPOS(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_INITPOS_SHIFT)) & EQDC_CTRL2_INITPOS_MASK)
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#define EQDC_CTRL2_ONCE_MASK (0x2000U)
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#define EQDC_CTRL2_ONCE_SHIFT (13U)
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/*! ONCE - Count Once
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* 0b0..Position counter counts repeatedly
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* 0b1..Position counter counts until roll-over or roll-under, then stop.
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*/
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#define EQDC_CTRL2_ONCE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_ONCE_SHIFT)) & EQDC_CTRL2_ONCE_MASK)
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#define EQDC_CTRL2_CMODE_MASK (0xC000U)
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#define EQDC_CTRL2_CMODE_SHIFT (14U)
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/*! CMODE - Counting Mode */
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#define EQDC_CTRL2_CMODE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_CMODE_SHIFT)) & EQDC_CTRL2_CMODE_MASK)
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/*! @} */
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/*! @name FILT - Input Filter Register */
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/*! @{ */
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#define EQDC_FILT_FILT_PER_MASK (0xFFU)
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#define EQDC_FILT_FILT_PER_SHIFT (0U)
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/*! FILT_PER - Input Filter Sample Period */
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#define EQDC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << EQDC_FILT_FILT_PER_SHIFT)) & EQDC_FILT_FILT_PER_MASK)
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#define EQDC_FILT_FILT_CNT_MASK (0x700U)
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#define EQDC_FILT_FILT_CNT_SHIFT (8U)
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/*! FILT_CNT - Input Filter Sample Count */
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#define EQDC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << EQDC_FILT_FILT_CNT_SHIFT)) & EQDC_FILT_FILT_CNT_MASK)
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#define EQDC_FILT_FILT_CS_MASK (0x800U)
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#define EQDC_FILT_FILT_CS_SHIFT (11U)
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/*! FILT_CS - Filter Clock Source selection
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* 0b0..Peripheral Clock
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* 0b1..Prescaled peripheral clock by PRSC
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*/
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#define EQDC_FILT_FILT_CS(x) (((uint16_t)(((uint16_t)(x)) << EQDC_FILT_FILT_CS_SHIFT)) & EQDC_FILT_FILT_CS_MASK)
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#define EQDC_FILT_PRSC_MASK (0xF000U)
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#define EQDC_FILT_PRSC_SHIFT (12U)
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/*! PRSC - Prescaler */
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#define EQDC_FILT_PRSC(x) (((uint16_t)(((uint16_t)(x)) << EQDC_FILT_PRSC_SHIFT)) & EQDC_FILT_PRSC_MASK)
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/*! @} */
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/*! @name LASTEDGE - Last Edge Time Register */
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/*! @{ */
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#define EQDC_LASTEDGE_LASTEDGE_MASK (0xFFFFU)
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#define EQDC_LASTEDGE_LASTEDGE_SHIFT (0U)
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/*! LASTEDGE - Last Edge Time Counter */
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#define EQDC_LASTEDGE_LASTEDGE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LASTEDGE_LASTEDGE_SHIFT)) & EQDC_LASTEDGE_LASTEDGE_MASK)
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/*! @} */
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/*! @name POSDPER - Position Difference Period Counter Register */
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/*! @{ */
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#define EQDC_POSDPER_POSDPER_MASK (0xFFFFU)
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#define EQDC_POSDPER_POSDPER_SHIFT (0U)
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/*! POSDPER - Position difference period */
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#define EQDC_POSDPER_POSDPER(x) (((uint16_t)(((uint16_t)(x)) << EQDC_POSDPER_POSDPER_SHIFT)) & EQDC_POSDPER_POSDPER_MASK)
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/*! @} */
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/*! @name POSDPERBFR - Position Difference Period Buffer Register */
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/*! @{ */
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#define EQDC_POSDPERBFR_POSDPERBFR_MASK (0xFFFFU)
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#define EQDC_POSDPERBFR_POSDPERBFR_SHIFT (0U)
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/*! POSDPERBFR - Position difference period buffer */
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#define EQDC_POSDPERBFR_POSDPERBFR(x) (((uint16_t)(((uint16_t)(x)) << EQDC_POSDPERBFR_POSDPERBFR_SHIFT)) & EQDC_POSDPERBFR_POSDPERBFR_MASK)
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/*! @} */
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/*! @name UPOS - Upper Position Counter Register */
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/*! @{ */
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#define EQDC_UPOS_POS_MASK (0xFFFFU)
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#define EQDC_UPOS_POS_SHIFT (0U)
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/*! POS - POS */
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#define EQDC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UPOS_POS_SHIFT)) & EQDC_UPOS_POS_MASK)
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/*! @} */
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/*! @name LPOS - Lower Position Counter Register */
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/*! @{ */
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#define EQDC_LPOS_POS_MASK (0xFFFFU)
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#define EQDC_LPOS_POS_SHIFT (0U)
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/*! POS - POS */
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#define EQDC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LPOS_POS_SHIFT)) & EQDC_LPOS_POS_MASK)
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/*! @} */
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/*! @name POSD - Position Difference Counter Register */
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/*! @{ */
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#define EQDC_POSD_POSD_MASK (0xFFFFU)
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#define EQDC_POSD_POSD_SHIFT (0U)
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/*! POSD - POSD */
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#define EQDC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << EQDC_POSD_POSD_SHIFT)) & EQDC_POSD_POSD_MASK)
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/*! @} */
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/*! @name POSDH - Position Difference Hold Register */
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/*! @{ */
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#define EQDC_POSDH_POSDH_MASK (0xFFFFU)
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#define EQDC_POSDH_POSDH_SHIFT (0U)
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/*! POSDH - POSDH */
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#define EQDC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << EQDC_POSDH_POSDH_SHIFT)) & EQDC_POSDH_POSDH_MASK)
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/*! @} */
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/*! @name UPOSH - Upper Position Hold Register */
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/*! @{ */
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#define EQDC_UPOSH_POSH_MASK (0xFFFFU)
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#define EQDC_UPOSH_POSH_SHIFT (0U)
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/*! POSH - POSH */
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#define EQDC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UPOSH_POSH_SHIFT)) & EQDC_UPOSH_POSH_MASK)
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/*! @} */
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/*! @name LPOSH - Lower Position Hold Register */
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/*! @{ */
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#define EQDC_LPOSH_LPOSH_MASK (0xFFFFU)
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#define EQDC_LPOSH_LPOSH_SHIFT (0U)
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/*! LPOSH - POSH */
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#define EQDC_LPOSH_LPOSH(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LPOSH_LPOSH_SHIFT)) & EQDC_LPOSH_LPOSH_MASK)
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/*! @} */
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/*! @name LASTEDGEH - Last Edge Time Hold Register */
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/*! @{ */
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#define EQDC_LASTEDGEH_LASTEDGEH_MASK (0xFFFFU)
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#define EQDC_LASTEDGEH_LASTEDGEH_SHIFT (0U)
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/*! LASTEDGEH - Last Edge Time Hold */
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#define EQDC_LASTEDGEH_LASTEDGEH(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LASTEDGEH_LASTEDGEH_SHIFT)) & EQDC_LASTEDGEH_LASTEDGEH_MASK)
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/*! @} */
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/*! @name POSDPERH - Position Difference Period Hold Register */
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/*! @{ */
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#define EQDC_POSDPERH_POSDPERH_MASK (0xFFFFU)
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#define EQDC_POSDPERH_POSDPERH_SHIFT (0U)
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/*! POSDPERH - Position difference period hold */
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#define EQDC_POSDPERH_POSDPERH(x) (((uint16_t)(((uint16_t)(x)) << EQDC_POSDPERH_POSDPERH_SHIFT)) & EQDC_POSDPERH_POSDPERH_MASK)
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/*! @} */
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/*! @name REVH - Revolution Hold Register */
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/*! @{ */
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#define EQDC_REVH_REVH_MASK (0xFFFFU)
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#define EQDC_REVH_REVH_SHIFT (0U)
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/*! REVH - REVH */
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#define EQDC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << EQDC_REVH_REVH_SHIFT)) & EQDC_REVH_REVH_MASK)
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/*! @} */
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/*! @name REV - Revolution Counter Register */
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/*! @{ */
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#define EQDC_REV_REV_MASK (0xFFFFU)
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#define EQDC_REV_REV_SHIFT (0U)
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/*! REV - REV */
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#define EQDC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << EQDC_REV_REV_SHIFT)) & EQDC_REV_REV_MASK)
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/*! @} */
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/*! @name UINIT - Upper Initialization Register */
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/*! @{ */
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#define EQDC_UINIT_INIT_MASK (0xFFFFU)
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#define EQDC_UINIT_INIT_SHIFT (0U)
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/*! INIT - INIT */
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#define EQDC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UINIT_INIT_SHIFT)) & EQDC_UINIT_INIT_MASK)
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/*! @} */
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/*! @name LINIT - Lower Initialization Register */
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/*! @{ */
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#define EQDC_LINIT_INIT_MASK (0xFFFFU)
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#define EQDC_LINIT_INIT_SHIFT (0U)
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/*! INIT - INIT */
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#define EQDC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LINIT_INIT_SHIFT)) & EQDC_LINIT_INIT_MASK)
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/*! @} */
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/*! @name UMOD - Upper Modulus Register */
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/*! @{ */
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#define EQDC_UMOD_MOD_MASK (0xFFFFU)
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#define EQDC_UMOD_MOD_SHIFT (0U)
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/*! MOD - MOD */
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#define EQDC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UMOD_MOD_SHIFT)) & EQDC_UMOD_MOD_MASK)
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/*! @} */
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/*! @name LMOD - Lower Modulus Register */
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/*! @{ */
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#define EQDC_LMOD_MOD_MASK (0xFFFFU)
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#define EQDC_LMOD_MOD_SHIFT (0U)
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/*! MOD - MOD */
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#define EQDC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LMOD_MOD_SHIFT)) & EQDC_LMOD_MOD_MASK)
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/*! @} */
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/*! @name UCOMP0 - Upper Position Compare Register 0 */
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/*! @{ */
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#define EQDC_UCOMP0_UCOMP0_MASK (0xFFFFU)
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#define EQDC_UCOMP0_UCOMP0_SHIFT (0U)
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/*! UCOMP0 - UCOMP0 */
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#define EQDC_UCOMP0_UCOMP0(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UCOMP0_UCOMP0_SHIFT)) & EQDC_UCOMP0_UCOMP0_MASK)
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/*! @} */
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/*! @name LCOMP0 - Lower Position Compare Register 0 */
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/*! @{ */
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#define EQDC_LCOMP0_LCOMP0_MASK (0xFFFFU)
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#define EQDC_LCOMP0_LCOMP0_SHIFT (0U)
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/*! LCOMP0 - LCOMP0 */
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#define EQDC_LCOMP0_LCOMP0(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LCOMP0_LCOMP0_SHIFT)) & EQDC_LCOMP0_LCOMP0_MASK)
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/*! @} */
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/*! @name UCOMP1 - Upper Position Compare 1 */
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/*! @{ */
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#define EQDC_UCOMP1_UCOMP1_MASK (0xFFFFU)
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#define EQDC_UCOMP1_UCOMP1_SHIFT (0U)
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/*! UCOMP1 - UCOMP1 */
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#define EQDC_UCOMP1_UCOMP1(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UCOMP1_UCOMP1_SHIFT)) & EQDC_UCOMP1_UCOMP1_MASK)
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/*! @} */
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/*! @name UPOSH1 - Upper Position Holder Register 1 */
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/*! @{ */
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#define EQDC_UPOSH1_UPOSH1_MASK (0xFFFFU)
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#define EQDC_UPOSH1_UPOSH1_SHIFT (0U)
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/*! UPOSH1 - UPOSH1 */
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#define EQDC_UPOSH1_UPOSH1(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UPOSH1_UPOSH1_SHIFT)) & EQDC_UPOSH1_UPOSH1_MASK)
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/*! @} */
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/*! @name LCOMP1 - Lower Position Compare 1 */
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/*! @{ */
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#define EQDC_LCOMP1_LCOMP1_MASK (0xFFFFU)
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#define EQDC_LCOMP1_LCOMP1_SHIFT (0U)
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/*! LCOMP1 - LCOMP1 */
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#define EQDC_LCOMP1_LCOMP1(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LCOMP1_LCOMP1_SHIFT)) & EQDC_LCOMP1_LCOMP1_MASK)
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/*! @} */
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/*! @name LPOSH1 - Lower Position Holder Register 1 */
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/*! @{ */
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#define EQDC_LPOSH1_LPOSH1_MASK (0xFFFFU)
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#define EQDC_LPOSH1_LPOSH1_SHIFT (0U)
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/*! LPOSH1 - LPOSH1 */
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#define EQDC_LPOSH1_LPOSH1(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LPOSH1_LPOSH1_SHIFT)) & EQDC_LPOSH1_LPOSH1_MASK)
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/*! @} */
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/*! @name UCOMP2 - Upper Position Compare 2 */
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/*! @{ */
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#define EQDC_UCOMP2_UCOMP2_MASK (0xFFFFU)
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#define EQDC_UCOMP2_UCOMP2_SHIFT (0U)
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/*! UCOMP2 - UCOMP2 */
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#define EQDC_UCOMP2_UCOMP2(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UCOMP2_UCOMP2_SHIFT)) & EQDC_UCOMP2_UCOMP2_MASK)
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/*! @} */
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/*! @name UPOSH2 - Upper Position Holder Register 3 */
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/*! @{ */
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#define EQDC_UPOSH2_UPOSH2_MASK (0xFFFFU)
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#define EQDC_UPOSH2_UPOSH2_SHIFT (0U)
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/*! UPOSH2 - UPOSH2 */
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#define EQDC_UPOSH2_UPOSH2(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UPOSH2_UPOSH2_SHIFT)) & EQDC_UPOSH2_UPOSH2_MASK)
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/*! @} */
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/*! @name LCOMP2 - Lower Position Compare 2 */
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/*! @{ */
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#define EQDC_LCOMP2_LCOMP2_MASK (0xFFFFU)
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#define EQDC_LCOMP2_LCOMP2_SHIFT (0U)
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/*! LCOMP2 - LCOMP2 */
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#define EQDC_LCOMP2_LCOMP2(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LCOMP2_LCOMP2_SHIFT)) & EQDC_LCOMP2_LCOMP2_MASK)
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/*! @} */
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/*! @name LPOSH2 - Lower Position Holder Register 2 */
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/*! @{ */
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#define EQDC_LPOSH2_LPOSH2_MASK (0xFFFFU)
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#define EQDC_LPOSH2_LPOSH2_SHIFT (0U)
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/*! LPOSH2 - LPOSH2 */
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#define EQDC_LPOSH2_LPOSH2(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LPOSH2_LPOSH2_SHIFT)) & EQDC_LPOSH2_LPOSH2_MASK)
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/*! @} */
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/*! @name UCOMP3 - Upper Position Compare 3 */
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/*! @{ */
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#define EQDC_UCOMP3_UCOMP3_MASK (0xFFFFU)
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#define EQDC_UCOMP3_UCOMP3_SHIFT (0U)
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/*! UCOMP3 - UCOMP3 */
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#define EQDC_UCOMP3_UCOMP3(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UCOMP3_UCOMP3_SHIFT)) & EQDC_UCOMP3_UCOMP3_MASK)
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/*! @} */
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/*! @name UPOSH3 - Upper Position Holder Register 3 */
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/*! @{ */
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#define EQDC_UPOSH3_UPOSH3_MASK (0xFFFFU)
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#define EQDC_UPOSH3_UPOSH3_SHIFT (0U)
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/*! UPOSH3 - UPOSH3 */
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#define EQDC_UPOSH3_UPOSH3(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UPOSH3_UPOSH3_SHIFT)) & EQDC_UPOSH3_UPOSH3_MASK)
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/*! @} */
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/*! @name LCOMP3 - Lower Position Compare 3 */
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/*! @{ */
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#define EQDC_LCOMP3_LCOMP3_MASK (0xFFFFU)
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#define EQDC_LCOMP3_LCOMP3_SHIFT (0U)
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/*! LCOMP3 - LCOMP3 */
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#define EQDC_LCOMP3_LCOMP3(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LCOMP3_LCOMP3_SHIFT)) & EQDC_LCOMP3_LCOMP3_MASK)
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/*! @} */
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/*! @name LPOSH3 - Lower Position Holder Register 3 */
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/*! @{ */
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#define EQDC_LPOSH3_LPOSH3_MASK (0xFFFFU)
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#define EQDC_LPOSH3_LPOSH3_SHIFT (0U)
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/*! LPOSH3 - LPOSH3 */
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#define EQDC_LPOSH3_LPOSH3(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LPOSH3_LPOSH3_SHIFT)) & EQDC_LPOSH3_LPOSH3_MASK)
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/*! @} */
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/*! @name INTCTRL - Interrupt Control Register */
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/*! @{ */
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#define EQDC_INTCTRL_SABIE_MASK (0x1U)
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#define EQDC_INTCTRL_SABIE_SHIFT (0U)
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/*! SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable
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* 0b0..Disabled
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* 0b1..Enabled
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*/
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#define EQDC_INTCTRL_SABIE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_SABIE_SHIFT)) & EQDC_INTCTRL_SABIE_MASK)
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#define EQDC_INTCTRL_SABIRQ_MASK (0x2U)
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#define EQDC_INTCTRL_SABIRQ_SHIFT (1U)
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/*! SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request
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* 0b0..No simultaneous change of PHASEA and PHASEB has occurred
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* 0b1..A simultaneous change of PHASEA and PHASEB has occurred
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*/
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#define EQDC_INTCTRL_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_SABIRQ_SHIFT)) & EQDC_INTCTRL_SABIRQ_MASK)
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#define EQDC_INTCTRL_DIRIE_MASK (0x4U)
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#define EQDC_INTCTRL_DIRIE_SHIFT (2U)
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/*! DIRIE - Count direction change interrupt enable
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* 0b0..Disabled
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* 0b1..Enabled
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*/
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#define EQDC_INTCTRL_DIRIE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_DIRIE_SHIFT)) & EQDC_INTCTRL_DIRIE_MASK)
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#define EQDC_INTCTRL_DIRIRQ_MASK (0x8U)
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#define EQDC_INTCTRL_DIRIRQ_SHIFT (3U)
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/*! DIRIRQ - Count direction change interrupt
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* 0b0..Count direction unchanged
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* 0b1..Count direction changed
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*/
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#define EQDC_INTCTRL_DIRIRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_DIRIRQ_SHIFT)) & EQDC_INTCTRL_DIRIRQ_MASK)
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#define EQDC_INTCTRL_RUIE_MASK (0x10U)
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#define EQDC_INTCTRL_RUIE_SHIFT (4U)
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/*! RUIE - Roll-under Interrupt Enable
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* 0b0..Disabled
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* 0b1..Enabled
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*/
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#define EQDC_INTCTRL_RUIE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_RUIE_SHIFT)) & EQDC_INTCTRL_RUIE_MASK)
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#define EQDC_INTCTRL_RUIRQ_MASK (0x20U)
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#define EQDC_INTCTRL_RUIRQ_SHIFT (5U)
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/*! RUIRQ - Roll-under Interrupt Request
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* 0b0..No roll-under has occurred
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* 0b1..Roll-under has occurred
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*/
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#define EQDC_INTCTRL_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_RUIRQ_SHIFT)) & EQDC_INTCTRL_RUIRQ_MASK)
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#define EQDC_INTCTRL_ROIE_MASK (0x40U)
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#define EQDC_INTCTRL_ROIE_SHIFT (6U)
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/*! ROIE - Roll-over Interrupt Enable
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* 0b0..Disabled
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* 0b1..Enabled
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*/
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#define EQDC_INTCTRL_ROIE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_ROIE_SHIFT)) & EQDC_INTCTRL_ROIE_MASK)
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#define EQDC_INTCTRL_ROIRQ_MASK (0x80U)
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#define EQDC_INTCTRL_ROIRQ_SHIFT (7U)
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/*! ROIRQ - Roll-over Interrupt Request
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* 0b0..No roll-over has occurred
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* 0b1..Roll-over has occurred
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*/
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#define EQDC_INTCTRL_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_ROIRQ_SHIFT)) & EQDC_INTCTRL_ROIRQ_MASK)
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#define EQDC_INTCTRL_CMP0IE_MASK (0x100U)
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#define EQDC_INTCTRL_CMP0IE_SHIFT (8U)
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/*! CMP0IE - Compare 0 Interrupt Enable
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* 0b0..Disabled
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* 0b1..Enabled
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*/
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#define EQDC_INTCTRL_CMP0IE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP0IE_SHIFT)) & EQDC_INTCTRL_CMP0IE_MASK)
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#define EQDC_INTCTRL_CMP0IRQ_MASK (0x200U)
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#define EQDC_INTCTRL_CMP0IRQ_SHIFT (9U)
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/*! CMP0IRQ - Compare 0 Interrupt Request
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* 0b0..No match has occurred (the position counter does not match the COMP0 value)
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* 0b1..COMP match has occurred (the position counter matches the COMP0 value)
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*/
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#define EQDC_INTCTRL_CMP0IRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP0IRQ_SHIFT)) & EQDC_INTCTRL_CMP0IRQ_MASK)
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#define EQDC_INTCTRL_CMP1IE_MASK (0x400U)
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#define EQDC_INTCTRL_CMP1IE_SHIFT (10U)
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/*! CMP1IE - Compare1 Interrupt Enable
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* 0b0..Disabled
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* 0b1..Enabled
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*/
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#define EQDC_INTCTRL_CMP1IE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP1IE_SHIFT)) & EQDC_INTCTRL_CMP1IE_MASK)
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#define EQDC_INTCTRL_CMP1IRQ_MASK (0x800U)
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#define EQDC_INTCTRL_CMP1IRQ_SHIFT (11U)
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/*! CMP1IRQ - Compare1 Interrupt Request
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* 0b0..No match has occurred (the position counter does not match the COMP1 value)
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* 0b1..COMP1 match has occurred (the position counter matches the COMP1 value)
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*/
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#define EQDC_INTCTRL_CMP1IRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP1IRQ_SHIFT)) & EQDC_INTCTRL_CMP1IRQ_MASK)
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#define EQDC_INTCTRL_CMP2IE_MASK (0x1000U)
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#define EQDC_INTCTRL_CMP2IE_SHIFT (12U)
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/*! CMP2IE - Compare2 Interrupt Enable
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* 0b0..Disabled
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* 0b1..Enabled
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*/
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#define EQDC_INTCTRL_CMP2IE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP2IE_SHIFT)) & EQDC_INTCTRL_CMP2IE_MASK)
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#define EQDC_INTCTRL_CMP2IRQ_MASK (0x2000U)
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#define EQDC_INTCTRL_CMP2IRQ_SHIFT (13U)
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/*! CMP2IRQ - Compare2 Interrupt Request
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* 0b0..No match has occurred (the position counter does not match the COMP2 value)
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* 0b1..COMP2 match has occurred (the position counter matches the COMP2 value)
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*/
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#define EQDC_INTCTRL_CMP2IRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP2IRQ_SHIFT)) & EQDC_INTCTRL_CMP2IRQ_MASK)
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#define EQDC_INTCTRL_CMP3IE_MASK (0x4000U)
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#define EQDC_INTCTRL_CMP3IE_SHIFT (14U)
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/*! CMP3IE - Compare3 Interrupt Enable
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* 0b0..Disabled
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* 0b1..Enabled
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*/
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#define EQDC_INTCTRL_CMP3IE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP3IE_SHIFT)) & EQDC_INTCTRL_CMP3IE_MASK)
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#define EQDC_INTCTRL_CMP3IRQ_MASK (0x8000U)
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#define EQDC_INTCTRL_CMP3IRQ_SHIFT (15U)
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/*! CMP3IRQ - Compare3 Interrupt Request
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* 0b0..No match has occurred (the position counter does not match the COMP3 value)
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* 0b1..COMP3 match has occurred (the position counter matches the COMP3 value)
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*/
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#define EQDC_INTCTRL_CMP3IRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP3IRQ_SHIFT)) & EQDC_INTCTRL_CMP3IRQ_MASK)
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/*! @} */
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/*! @name WTR - Watchdog Timeout Register */
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/*! @{ */
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#define EQDC_WTR_WDOG_MASK (0xFFFFU)
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#define EQDC_WTR_WDOG_SHIFT (0U)
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/*! WDOG - WDOG */
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#define EQDC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << EQDC_WTR_WDOG_SHIFT)) & EQDC_WTR_WDOG_MASK)
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/*! @} */
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/*! @name IMR - Input Monitor Register */
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/*! @{ */
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#define EQDC_IMR_HOME_ENABLE_MASK (0x1U)
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#define EQDC_IMR_HOME_ENABLE_SHIFT (0U)
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/*! HOME_ENABLE - HOME_ENABLE */
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#define EQDC_IMR_HOME_ENABLE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_HOME_ENABLE_SHIFT)) & EQDC_IMR_HOME_ENABLE_MASK)
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#define EQDC_IMR_INDEX_PRESET_MASK (0x2U)
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#define EQDC_IMR_INDEX_PRESET_SHIFT (1U)
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/*! INDEX_PRESET - INDEX_PRESET */
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#define EQDC_IMR_INDEX_PRESET(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_INDEX_PRESET_SHIFT)) & EQDC_IMR_INDEX_PRESET_MASK)
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#define EQDC_IMR_PHB_MASK (0x4U)
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#define EQDC_IMR_PHB_SHIFT (2U)
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/*! PHB - PHB */
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#define EQDC_IMR_PHB(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_PHB_SHIFT)) & EQDC_IMR_PHB_MASK)
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#define EQDC_IMR_PHA_MASK (0x8U)
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#define EQDC_IMR_PHA_SHIFT (3U)
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/*! PHA - PHA */
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#define EQDC_IMR_PHA(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_PHA_SHIFT)) & EQDC_IMR_PHA_MASK)
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#define EQDC_IMR_FHOM_ENA_MASK (0x10U)
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#define EQDC_IMR_FHOM_ENA_SHIFT (4U)
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/*! FHOM_ENA - filter operation on HOME/ENABLE input */
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#define EQDC_IMR_FHOM_ENA(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_FHOM_ENA_SHIFT)) & EQDC_IMR_FHOM_ENA_MASK)
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#define EQDC_IMR_FIND_PRE_MASK (0x20U)
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#define EQDC_IMR_FIND_PRE_SHIFT (5U)
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/*! FIND_PRE - filter operation on INDEX/PRESET input */
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#define EQDC_IMR_FIND_PRE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_FIND_PRE_SHIFT)) & EQDC_IMR_FIND_PRE_MASK)
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#define EQDC_IMR_FPHB_MASK (0x40U)
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#define EQDC_IMR_FPHB_SHIFT (6U)
|
|
/*! FPHB - filter operation on PHASEB input */
|
|
#define EQDC_IMR_FPHB(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_FPHB_SHIFT)) & EQDC_IMR_FPHB_MASK)
|
|
|
|
#define EQDC_IMR_FPHA_MASK (0x80U)
|
|
#define EQDC_IMR_FPHA_SHIFT (7U)
|
|
/*! FPHA - filter operation on PHASEA input */
|
|
#define EQDC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_FPHA_SHIFT)) & EQDC_IMR_FPHA_MASK)
|
|
|
|
#define EQDC_IMR_CMPF0_MASK (0x100U)
|
|
#define EQDC_IMR_CMPF0_SHIFT (8U)
|
|
/*! CMPF0 - Position Compare 0 Flag Output
|
|
* 0b0..When the position counter is less than value of COMP0 register
|
|
* 0b1..When the position counter is greater or equal than value of COMP0 register
|
|
*/
|
|
#define EQDC_IMR_CMPF0(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_CMPF0_SHIFT)) & EQDC_IMR_CMPF0_MASK)
|
|
|
|
#define EQDC_IMR_CMP1F_MASK (0x200U)
|
|
#define EQDC_IMR_CMP1F_SHIFT (9U)
|
|
/*! CMP1F - Position Compare1 Flag Output
|
|
* 0b0..When the position counter is less than value of COMP1 register
|
|
* 0b1..When the position counter is greater or equal than value of COMP1 register
|
|
*/
|
|
#define EQDC_IMR_CMP1F(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_CMP1F_SHIFT)) & EQDC_IMR_CMP1F_MASK)
|
|
|
|
#define EQDC_IMR_CMP2F_MASK (0x400U)
|
|
#define EQDC_IMR_CMP2F_SHIFT (10U)
|
|
/*! CMP2F - Position Compare2 Flag Output
|
|
* 0b0..When the position counter is less than value of COMP2 register
|
|
* 0b1..When the position counter is greater or equal than value of COMP2 register
|
|
*/
|
|
#define EQDC_IMR_CMP2F(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_CMP2F_SHIFT)) & EQDC_IMR_CMP2F_MASK)
|
|
|
|
#define EQDC_IMR_CMP3F_MASK (0x800U)
|
|
#define EQDC_IMR_CMP3F_SHIFT (11U)
|
|
/*! CMP3F - Position Compare3 Flag Output
|
|
* 0b0..When the position counter value is less than value of COMP3 register
|
|
* 0b1..When the position counter is greater or equal than value of COMP3 register
|
|
*/
|
|
#define EQDC_IMR_CMP3F(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_CMP3F_SHIFT)) & EQDC_IMR_CMP3F_MASK)
|
|
|
|
#define EQDC_IMR_DIRH_MASK (0x4000U)
|
|
#define EQDC_IMR_DIRH_SHIFT (14U)
|
|
/*! DIRH - Count Direction Flag Hold */
|
|
#define EQDC_IMR_DIRH(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_DIRH_SHIFT)) & EQDC_IMR_DIRH_MASK)
|
|
|
|
#define EQDC_IMR_DIR_MASK (0x8000U)
|
|
#define EQDC_IMR_DIR_SHIFT (15U)
|
|
/*! DIR - Count Direction Flag Output
|
|
* 0b0..Current count was in the down direction
|
|
* 0b1..Current count was in the up direction
|
|
*/
|
|
#define EQDC_IMR_DIR(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_DIR_SHIFT)) & EQDC_IMR_DIR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TST - Test Register */
|
|
/*! @{ */
|
|
|
|
#define EQDC_TST_TEST_COUNT_MASK (0xFFU)
|
|
#define EQDC_TST_TEST_COUNT_SHIFT (0U)
|
|
/*! TEST_COUNT - TEST_COUNT */
|
|
#define EQDC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << EQDC_TST_TEST_COUNT_SHIFT)) & EQDC_TST_TEST_COUNT_MASK)
|
|
|
|
#define EQDC_TST_TEST_PERIOD_MASK (0x1F00U)
|
|
#define EQDC_TST_TEST_PERIOD_SHIFT (8U)
|
|
/*! TEST_PERIOD - TEST_PERIOD */
|
|
#define EQDC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << EQDC_TST_TEST_PERIOD_SHIFT)) & EQDC_TST_TEST_PERIOD_MASK)
|
|
|
|
#define EQDC_TST_QDN_MASK (0x2000U)
|
|
#define EQDC_TST_QDN_SHIFT (13U)
|
|
/*! QDN - Quadrature Decoder Negative Signal
|
|
* 0b0..Generates a positive quadrature decoder signal
|
|
* 0b1..Generates a negative quadrature decoder signal
|
|
*/
|
|
#define EQDC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << EQDC_TST_QDN_SHIFT)) & EQDC_TST_QDN_MASK)
|
|
|
|
#define EQDC_TST_TCE_MASK (0x4000U)
|
|
#define EQDC_TST_TCE_SHIFT (14U)
|
|
/*! TCE - Test Counter Enable
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define EQDC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_TST_TCE_SHIFT)) & EQDC_TST_TCE_MASK)
|
|
|
|
#define EQDC_TST_TEN_MASK (0x8000U)
|
|
#define EQDC_TST_TEN_SHIFT (15U)
|
|
/*! TEN - Test Mode Enable
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define EQDC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << EQDC_TST_TEN_SHIFT)) & EQDC_TST_TEN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name UVERID - Upper VERID */
|
|
/*! @{ */
|
|
|
|
#define EQDC_UVERID_UVERID_MASK (0xFFFFU)
|
|
#define EQDC_UVERID_UVERID_SHIFT (0U)
|
|
/*! UVERID - UVERID */
|
|
#define EQDC_UVERID_UVERID(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UVERID_UVERID_SHIFT)) & EQDC_UVERID_UVERID_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name LVERID - Lower VERID */
|
|
/*! @{ */
|
|
|
|
#define EQDC_LVERID_LVERID_MASK (0xFFFFU)
|
|
#define EQDC_LVERID_LVERID_SHIFT (0U)
|
|
/*! LVERID - LVERID */
|
|
#define EQDC_LVERID_LVERID(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LVERID_LVERID_SHIFT)) & EQDC_LVERID_LVERID_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group EQDC_Register_Masks */
|
|
|
|
|
|
/* EQDC - Peripheral instance base addresses */
|
|
/** Peripheral QDC0 base address */
|
|
#define QDC0_BASE (0x400A7000u)
|
|
/** Peripheral QDC0 base pointer */
|
|
#define QDC0 ((EQDC_Type *)QDC0_BASE)
|
|
/** Array initializer of EQDC peripheral base addresses */
|
|
#define EQDC_BASE_ADDRS { QDC0_BASE }
|
|
/** Array initializer of EQDC peripheral base pointers */
|
|
#define EQDC_BASE_PTRS { QDC0 }
|
|
/** Interrupt vectors for the EQDC peripheral type */
|
|
#define EQDC_COMPARE_IRQS { QDC0_COMPARE_IRQn }
|
|
#define EQDC_HOME_IRQS { QDC0_HOME_IRQn }
|
|
#define EQDC_WDOG_IRQS { QDC0_WATCHDOG_IRQn }
|
|
#define EQDC_INDEX_IRQS { QDC0_INDEX_IRQn }
|
|
#define EQDC_INPUT_SWITCH_IRQS { QDC0_WATCHDOG_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group EQDC_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- ERM Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup ERM_Peripheral_Access_Layer ERM Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** ERM - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t CR0; /**< ERM Configuration Register 0, offset: 0x0 */
|
|
uint8_t RESERVED_0[12];
|
|
__IO uint32_t SR0; /**< ERM Status Register 0, offset: 0x10 */
|
|
uint8_t RESERVED_1[236];
|
|
__I uint32_t EAR0; /**< ERM Memory 0 Error Address Register, offset: 0x100 */
|
|
__I uint32_t SYN0; /**< ERM Memory 0 Syndrome Register, offset: 0x104 */
|
|
__IO uint32_t CORR_ERR_CNT0; /**< ERM Memory 0 Correctable Error Count Register, offset: 0x108 */
|
|
uint8_t RESERVED_2[12];
|
|
__IO uint32_t CORR_ERR_CNT1; /**< ERM Memory 1 Correctable Error Count Register, offset: 0x118 */
|
|
} ERM_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- ERM Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup ERM_Register_Masks ERM Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name CR0 - ERM Configuration Register 0 */
|
|
/*! @{ */
|
|
|
|
#define ERM_CR0_ENCIE1_MASK (0x4000000U)
|
|
#define ERM_CR0_ENCIE1_SHIFT (26U)
|
|
/*! ENCIE1 - ENCIE1
|
|
* 0b0..Interrupt notification of Memory 1 non-correctable error events is disabled.
|
|
* 0b1..Interrupt notification of Memory 1 non-correctable error events is enabled.
|
|
*/
|
|
#define ERM_CR0_ENCIE1(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE1_SHIFT)) & ERM_CR0_ENCIE1_MASK)
|
|
|
|
#define ERM_CR0_ESCIE1_MASK (0x8000000U)
|
|
#define ERM_CR0_ESCIE1_SHIFT (27U)
|
|
/*! ESCIE1 - ESCIE1
|
|
* 0b0..Interrupt notification of Memory 1 single-bit correction events is disabled.
|
|
* 0b1..Interrupt notification of Memory 1 single-bit correction events is enabled.
|
|
*/
|
|
#define ERM_CR0_ESCIE1(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE1_SHIFT)) & ERM_CR0_ESCIE1_MASK)
|
|
|
|
#define ERM_CR0_ENCIE0_MASK (0x40000000U)
|
|
#define ERM_CR0_ENCIE0_SHIFT (30U)
|
|
/*! ENCIE0 - ENCIE0
|
|
* 0b0..Interrupt notification of Memory 0 non-correctable error events is disabled.
|
|
* 0b1..Interrupt notification of Memory 0 non-correctable error events is enabled.
|
|
*/
|
|
#define ERM_CR0_ENCIE0(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE0_SHIFT)) & ERM_CR0_ENCIE0_MASK)
|
|
|
|
#define ERM_CR0_ESCIE0_MASK (0x80000000U)
|
|
#define ERM_CR0_ESCIE0_SHIFT (31U)
|
|
/*! ESCIE0 - ESCIE0
|
|
* 0b0..Interrupt notification of Memory 0 single-bit correction events is disabled.
|
|
* 0b1..Interrupt notification of Memory 0 single-bit correction events is enabled.
|
|
*/
|
|
#define ERM_CR0_ESCIE0(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE0_SHIFT)) & ERM_CR0_ESCIE0_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SR0 - ERM Status Register 0 */
|
|
/*! @{ */
|
|
|
|
#define ERM_SR0_NCE1_MASK (0x4000000U)
|
|
#define ERM_SR0_NCE1_SHIFT (26U)
|
|
/*! NCE1 - NCE1
|
|
* 0b0..No non-correctable error event on Memory 1 detected.
|
|
* 0b1..Non-correctable error event on Memory 1 detected.
|
|
*/
|
|
#define ERM_SR0_NCE1(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE1_SHIFT)) & ERM_SR0_NCE1_MASK)
|
|
|
|
#define ERM_SR0_SBC1_MASK (0x8000000U)
|
|
#define ERM_SR0_SBC1_SHIFT (27U)
|
|
/*! SBC1 - SBC1
|
|
* 0b0..No single-bit correction event on Memory 1 detected.
|
|
* 0b1..Single-bit correction event on Memory 1 detected.
|
|
*/
|
|
#define ERM_SR0_SBC1(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC1_SHIFT)) & ERM_SR0_SBC1_MASK)
|
|
|
|
#define ERM_SR0_NCE0_MASK (0x40000000U)
|
|
#define ERM_SR0_NCE0_SHIFT (30U)
|
|
/*! NCE0 - NCE0
|
|
* 0b0..No non-correctable error event on Memory 0 detected.
|
|
* 0b1..Non-correctable error event on Memory 0 detected.
|
|
*/
|
|
#define ERM_SR0_NCE0(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE0_SHIFT)) & ERM_SR0_NCE0_MASK)
|
|
|
|
#define ERM_SR0_SBC0_MASK (0x80000000U)
|
|
#define ERM_SR0_SBC0_SHIFT (31U)
|
|
/*! SBC0 - SBC0
|
|
* 0b0..No single-bit correction event on Memory 0 detected.
|
|
* 0b1..Single-bit correction event on Memory 0 detected.
|
|
*/
|
|
#define ERM_SR0_SBC0(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC0_SHIFT)) & ERM_SR0_SBC0_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name EAR0 - ERM Memory 0 Error Address Register */
|
|
/*! @{ */
|
|
|
|
#define ERM_EAR0_EAR_MASK (0xFFFFFFFFU)
|
|
#define ERM_EAR0_EAR_SHIFT (0U)
|
|
/*! EAR - EAR */
|
|
#define ERM_EAR0_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR0_EAR_SHIFT)) & ERM_EAR0_EAR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SYN0 - ERM Memory 0 Syndrome Register */
|
|
/*! @{ */
|
|
|
|
#define ERM_SYN0_SYNDROME_MASK (0xFF000000U)
|
|
#define ERM_SYN0_SYNDROME_SHIFT (24U)
|
|
/*! SYNDROME - SYNDROME */
|
|
#define ERM_SYN0_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN0_SYNDROME_SHIFT)) & ERM_SYN0_SYNDROME_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CORR_ERR_CNT0 - ERM Memory 0 Correctable Error Count Register */
|
|
/*! @{ */
|
|
|
|
#define ERM_CORR_ERR_CNT0_COUNT_MASK (0xFFU)
|
|
#define ERM_CORR_ERR_CNT0_COUNT_SHIFT (0U)
|
|
/*! COUNT - Memory n Correctable Error Count */
|
|
#define ERM_CORR_ERR_CNT0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT0_COUNT_SHIFT)) & ERM_CORR_ERR_CNT0_COUNT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CORR_ERR_CNT1 - ERM Memory 1 Correctable Error Count Register */
|
|
/*! @{ */
|
|
|
|
#define ERM_CORR_ERR_CNT1_COUNT_MASK (0xFFU)
|
|
#define ERM_CORR_ERR_CNT1_COUNT_SHIFT (0U)
|
|
/*! COUNT - Memory n Correctable Error Count */
|
|
#define ERM_CORR_ERR_CNT1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT1_COUNT_SHIFT)) & ERM_CORR_ERR_CNT1_COUNT_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group ERM_Register_Masks */
|
|
|
|
|
|
/* ERM - Peripheral instance base addresses */
|
|
/** Peripheral ERM0 base address */
|
|
#define ERM0_BASE (0x4008D000u)
|
|
/** Peripheral ERM0 base pointer */
|
|
#define ERM0 ((ERM_Type *)ERM0_BASE)
|
|
/** Array initializer of ERM peripheral base addresses */
|
|
#define ERM_BASE_ADDRS { ERM0_BASE }
|
|
/** Array initializer of ERM peripheral base pointers */
|
|
#define ERM_BASE_PTRS { ERM0 }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group ERM_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- FMC Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** FMC - Register Layout Typedef */
|
|
typedef struct {
|
|
uint8_t RESERVED_0[32];
|
|
__IO uint32_t REMAP; /**< Data Remap, offset: 0x20 */
|
|
} FMC_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- FMC Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup FMC_Register_Masks FMC Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name REMAP - Data Remap */
|
|
/*! @{ */
|
|
|
|
#define FMC_REMAP_REMAPLK_MASK (0x1U)
|
|
#define FMC_REMAP_REMAPLK_SHIFT (0U)
|
|
/*! REMAPLK - Remap Lock Enable
|
|
* 0b1..Lock enabled: cannot write to REMAP
|
|
* 0b0..Lock disabled: can write to REMAP
|
|
*/
|
|
#define FMC_REMAP_REMAPLK(x) (((uint32_t)(((uint32_t)(x)) << FMC_REMAP_REMAPLK_SHIFT)) & FMC_REMAP_REMAPLK_MASK)
|
|
|
|
#define FMC_REMAP_LIM_MASK (0x1F0000U)
|
|
#define FMC_REMAP_LIM_SHIFT (16U)
|
|
/*! LIM - LIM Remapping Address */
|
|
#define FMC_REMAP_LIM(x) (((uint32_t)(((uint32_t)(x)) << FMC_REMAP_LIM_SHIFT)) & FMC_REMAP_LIM_MASK)
|
|
|
|
#define FMC_REMAP_LIMDP_MASK (0x1F000000U)
|
|
#define FMC_REMAP_LIMDP_SHIFT (24U)
|
|
/*! LIMDP - LIMDP Remapping Address */
|
|
#define FMC_REMAP_LIMDP(x) (((uint32_t)(((uint32_t)(x)) << FMC_REMAP_LIMDP_SHIFT)) & FMC_REMAP_LIMDP_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group FMC_Register_Masks */
|
|
|
|
|
|
/* FMC - Peripheral instance base addresses */
|
|
/** Peripheral FMC0 base address */
|
|
#define FMC0_BASE (0x40094000u)
|
|
/** Peripheral FMC0 base pointer */
|
|
#define FMC0 ((FMC_Type *)FMC0_BASE)
|
|
/** Array initializer of FMC peripheral base addresses */
|
|
#define FMC_BASE_ADDRS { FMC0_BASE }
|
|
/** Array initializer of FMC peripheral base pointers */
|
|
#define FMC_BASE_PTRS { FMC0 }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group FMC_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- FMU Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup FMU_Peripheral_Access_Layer FMU Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** FMU - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t FSTAT; /**< Flash Status Register, offset: 0x0 */
|
|
__IO uint32_t FCNFG; /**< Flash Configuration Register, offset: 0x4 */
|
|
__IO uint32_t FCTRL; /**< Flash Control Register, offset: 0x8 */
|
|
uint8_t RESERVED_0[4];
|
|
__IO uint32_t FCCOB[8]; /**< Flash Common Command Object Registers, array offset: 0x10, array step: 0x4 */
|
|
} FMU_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- FMU Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup FMU_Register_Masks FMU Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name FSTAT - Flash Status Register */
|
|
/*! @{ */
|
|
|
|
#define FMU_FSTAT_FAIL_MASK (0x1U)
|
|
#define FMU_FSTAT_FAIL_SHIFT (0U)
|
|
/*! FAIL - Command Fail Flag
|
|
* 0b0..Error not detected
|
|
* 0b1..Error detected
|
|
*/
|
|
#define FMU_FSTAT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_FAIL_SHIFT)) & FMU_FSTAT_FAIL_MASK)
|
|
|
|
#define FMU_FSTAT_CMDABT_MASK (0x4U)
|
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#define FMU_FSTAT_CMDABT_SHIFT (2U)
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/*! CMDABT - Command Abort Flag
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* 0b0..No command abort detected
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* 0b1..Command abort detected
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*/
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#define FMU_FSTAT_CMDABT(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDABT_SHIFT)) & FMU_FSTAT_CMDABT_MASK)
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#define FMU_FSTAT_PVIOL_MASK (0x10U)
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#define FMU_FSTAT_PVIOL_SHIFT (4U)
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/*! PVIOL - Command Protection Violation Flag
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* 0b0..No protection violation detected
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* 0b1..Protection violation detected
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*/
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#define FMU_FSTAT_PVIOL(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_PVIOL_SHIFT)) & FMU_FSTAT_PVIOL_MASK)
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#define FMU_FSTAT_ACCERR_MASK (0x20U)
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#define FMU_FSTAT_ACCERR_SHIFT (5U)
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/*! ACCERR - Command Access Error Flag
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* 0b0..No access error detected
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* 0b1..Access error detected
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*/
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#define FMU_FSTAT_ACCERR(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_ACCERR_SHIFT)) & FMU_FSTAT_ACCERR_MASK)
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#define FMU_FSTAT_CWSABT_MASK (0x40U)
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#define FMU_FSTAT_CWSABT_SHIFT (6U)
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/*! CWSABT - Command Write Sequence Abort Flag
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* 0b0..Command write sequence not aborted
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* 0b1..Command write sequence aborted
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*/
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#define FMU_FSTAT_CWSABT(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CWSABT_SHIFT)) & FMU_FSTAT_CWSABT_MASK)
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#define FMU_FSTAT_CCIF_MASK (0x80U)
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#define FMU_FSTAT_CCIF_SHIFT (7U)
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/*! CCIF - Command Complete Interrupt Flag
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* 0b0..Flash command, initialization, or power mode recovery in progress
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* 0b1..Flash command, initialization, or power mode recovery has completed
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*/
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#define FMU_FSTAT_CCIF(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CCIF_SHIFT)) & FMU_FSTAT_CCIF_MASK)
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#define FMU_FSTAT_CMDPRT_MASK (0x300U)
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#define FMU_FSTAT_CMDPRT_SHIFT (8U)
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/*! CMDPRT - Command protection level
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* 0b00..Secure, normal access
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* 0b01..Secure, privileged access
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* 0b10..Nonsecure, normal access
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* 0b11..Nonsecure, privileged access
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*/
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#define FMU_FSTAT_CMDPRT(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDPRT_SHIFT)) & FMU_FSTAT_CMDPRT_MASK)
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#define FMU_FSTAT_CMDP_MASK (0x800U)
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#define FMU_FSTAT_CMDP_SHIFT (11U)
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/*! CMDP - Command protection status flag
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* 0b0..Command protection level and domain ID are stale
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* 0b1..Command protection level (CMDPRT) and domain ID (CMDDID) are set
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*/
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#define FMU_FSTAT_CMDP(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDP_SHIFT)) & FMU_FSTAT_CMDP_MASK)
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#define FMU_FSTAT_CMDDID_MASK (0xF000U)
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#define FMU_FSTAT_CMDDID_SHIFT (12U)
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/*! CMDDID - Command domain ID */
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#define FMU_FSTAT_CMDDID(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDDID_SHIFT)) & FMU_FSTAT_CMDDID_MASK)
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#define FMU_FSTAT_DFDIF_MASK (0x10000U)
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#define FMU_FSTAT_DFDIF_SHIFT (16U)
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/*! DFDIF - Double Bit Fault Detect Interrupt Flag
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* 0b0..Double bit fault not detected during a valid flash read access
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* 0b1..Double bit fault detected (or FCTRL[FDFD] is set) during a valid flash read access
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*/
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#define FMU_FSTAT_DFDIF(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_DFDIF_SHIFT)) & FMU_FSTAT_DFDIF_MASK)
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#define FMU_FSTAT_SALV_USED_MASK (0x20000U)
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#define FMU_FSTAT_SALV_USED_SHIFT (17U)
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/*! SALV_USED - Salvage Used for Erase operation
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* 0b0..Salvage not used during last operation
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* 0b1..Salvage used during the last erase operation
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*/
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#define FMU_FSTAT_SALV_USED(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_SALV_USED_SHIFT)) & FMU_FSTAT_SALV_USED_MASK)
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#define FMU_FSTAT_PEWEN_MASK (0x3000000U)
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#define FMU_FSTAT_PEWEN_SHIFT (24U)
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/*! PEWEN - Program-Erase Write Enable Control
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* 0b00..Writes are not enabled
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* 0b01..Writes are enabled for one flash or IFR phrase (phrase programming, sector erase)
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* 0b10..Writes are enabled for one flash or IFR page (page programming)
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* 0b11..Reserved
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*/
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#define FMU_FSTAT_PEWEN(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_PEWEN_SHIFT)) & FMU_FSTAT_PEWEN_MASK)
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#define FMU_FSTAT_PERDY_MASK (0x80000000U)
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#define FMU_FSTAT_PERDY_SHIFT (31U)
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/*! PERDY - Program-Erase Ready Control/Status Flag
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* 0b0..Program or sector erase command operation not stalled
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* 0b1..Program or sector erase command operation ready to execute
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*/
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#define FMU_FSTAT_PERDY(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_PERDY_SHIFT)) & FMU_FSTAT_PERDY_MASK)
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/*! @} */
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/*! @name FCNFG - Flash Configuration Register */
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/*! @{ */
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#define FMU_FCNFG_CCIE_MASK (0x80U)
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#define FMU_FCNFG_CCIE_SHIFT (7U)
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/*! CCIE - Command Complete Interrupt Enable
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* 0b0..Command complete interrupt disabled
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* 0b1..Command complete interrupt enabled
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*/
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#define FMU_FCNFG_CCIE(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_CCIE_SHIFT)) & FMU_FCNFG_CCIE_MASK)
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#define FMU_FCNFG_ERSREQ_MASK (0x100U)
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#define FMU_FCNFG_ERSREQ_SHIFT (8U)
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/*! ERSREQ - Mass Erase Request
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* 0b0..No request or request complete
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* 0b1..Request to run the Mass Erase operation
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*/
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#define FMU_FCNFG_ERSREQ(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSREQ_SHIFT)) & FMU_FCNFG_ERSREQ_MASK)
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#define FMU_FCNFG_DFDIE_MASK (0x10000U)
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#define FMU_FCNFG_DFDIE_SHIFT (16U)
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/*! DFDIE - Double Bit Fault Detect Interrupt Enable
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* 0b0..Double bit fault detect interrupt disabled
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* 0b1..Double bit fault detect interrupt enabled
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*/
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#define FMU_FCNFG_DFDIE(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_DFDIE_SHIFT)) & FMU_FCNFG_DFDIE_MASK)
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#define FMU_FCNFG_ERSIEN0_MASK (0xF000000U)
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#define FMU_FCNFG_ERSIEN0_SHIFT (24U)
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/*! ERSIEN0 - Erase IFR Sector Enable - Block 0
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* 0b0000..Block 0 IFR Sector X is protected from erase by ERSSCR command
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* 0b0001..Block 0 IFR Sector X is not protected from erase by ERSSCR command
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*/
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#define FMU_FCNFG_ERSIEN0(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN0_SHIFT)) & FMU_FCNFG_ERSIEN0_MASK)
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#define FMU_FCNFG_ERSIEN1_MASK (0xF0000000U)
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#define FMU_FCNFG_ERSIEN1_SHIFT (28U)
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/*! ERSIEN1 - Erase IFR Sector Enable - Block 1 (for dual block configs)
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* 0b0000..Block 1 IFR Sector X is protected from erase by ERSSCR command
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* 0b0001..Block 1 IFR Sector X is not protected from erase by ERSSCR command
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*/
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#define FMU_FCNFG_ERSIEN1(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN1_SHIFT)) & FMU_FCNFG_ERSIEN1_MASK)
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/*! @} */
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/*! @name FCTRL - Flash Control Register */
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/*! @{ */
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#define FMU_FCTRL_RWSC_MASK (0xFU)
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#define FMU_FCTRL_RWSC_SHIFT (0U)
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/*! RWSC - Read Wait-State Control */
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#define FMU_FCTRL_RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_RWSC_SHIFT)) & FMU_FCTRL_RWSC_MASK)
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#define FMU_FCTRL_LSACTIVE_MASK (0x100U)
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#define FMU_FCTRL_LSACTIVE_SHIFT (8U)
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/*! LSACTIVE - Low speed active mode
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* 0b0..Full speed active mode requested
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* 0b1..Low speed active mode requested
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*/
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#define FMU_FCTRL_LSACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_LSACTIVE_SHIFT)) & FMU_FCTRL_LSACTIVE_MASK)
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#define FMU_FCTRL_FDFD_MASK (0x10000U)
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#define FMU_FCTRL_FDFD_SHIFT (16U)
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/*! FDFD - Force Double Bit Fault Detect
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* 0b0..FSTAT[DFDIF] sets only if a double bit fault is detected during a valid flash read access from the platform flash controller
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* 0b1..FSTAT[DFDIF] sets during any valid flash read access from the platform flash controller. An interrupt
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* request is generated if the DFDIE bit is set.
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*/
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#define FMU_FCTRL_FDFD(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_FDFD_SHIFT)) & FMU_FCTRL_FDFD_MASK)
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#define FMU_FCTRL_ABTREQ_MASK (0x1000000U)
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#define FMU_FCTRL_ABTREQ_SHIFT (24U)
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/*! ABTREQ - Abort Request
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* 0b0..No request to abort a command write sequence
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* 0b1..Request to abort a command write sequence
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*/
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#define FMU_FCTRL_ABTREQ(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_ABTREQ_SHIFT)) & FMU_FCTRL_ABTREQ_MASK)
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/*! @} */
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/*! @name FCCOB - Flash Common Command Object Registers */
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/*! @{ */
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#define FMU_FCCOB_CCOBn_MASK (0xFFFFFFFFU)
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#define FMU_FCCOB_CCOBn_SHIFT (0U)
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/*! CCOBn - CCOBn */
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#define FMU_FCCOB_CCOBn(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCCOB_CCOBn_SHIFT)) & FMU_FCCOB_CCOBn_MASK)
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/*! @} */
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/* The count of FMU_FCCOB */
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#define FMU_FCCOB_COUNT (8U)
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/*!
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* @}
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*/ /* end of group FMU_Register_Masks */
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/* FMU - Peripheral instance base addresses */
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/** Peripheral FMU0 base address */
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#define FMU0_BASE (0x40095000u)
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/** Peripheral FMU0 base pointer */
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#define FMU0 ((FMU_Type *)FMU0_BASE)
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/** Array initializer of FMU peripheral base addresses */
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#define FMU_BASE_ADDRS { FMU0_BASE }
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/** Array initializer of FMU peripheral base pointers */
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#define FMU_BASE_PTRS { FMU0 }
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/*!
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* @}
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*/ /* end of group FMU_Peripheral_Access_Layer */
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/* ----------------------------------------------------------------------------
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-- FMUTEST Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup FMUTEST_Peripheral_Access_Layer FMUTEST Peripheral Access Layer
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* @{
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*/
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/** FMUTEST - Register Layout Typedef */
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typedef struct {
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__IO uint32_t FSTAT; /**< Flash Status Register, offset: 0x0 */
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__IO uint32_t FCNFG; /**< Flash Configuration Register, offset: 0x4 */
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__IO uint32_t FCTRL; /**< Flash Control Register, offset: 0x8 */
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__I uint32_t FTEST; /**< Flash Test Register, offset: 0xC */
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__IO uint32_t FCCOB0; /**< Flash Command Control 0 Register, offset: 0x10 */
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__IO uint32_t FCCOB1; /**< Flash Command Control 1 Register, offset: 0x14 */
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__IO uint32_t FCCOB2; /**< Flash Command Control 2 Register, offset: 0x18 */
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__IO uint32_t FCCOB3; /**< Flash Command Control 3 Register, offset: 0x1C */
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__IO uint32_t FCCOB4; /**< Flash Command Control 4 Register, offset: 0x20 */
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__IO uint32_t FCCOB5; /**< Flash Command Control 5 Register, offset: 0x24 */
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__IO uint32_t FCCOB6; /**< Flash Command Control 6 Register, offset: 0x28 */
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__IO uint32_t FCCOB7; /**< Flash Command Control 7 Register, offset: 0x2C */
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uint8_t RESERVED_0[208];
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__IO uint32_t RESET_STATUS; /**< FMU Initialization Tracking Register, offset: 0x100 */
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__IO uint32_t MCTL; /**< FMU Control Register, offset: 0x104 */
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__I uint32_t BSEL_GEN; /**< FMU Block Select Generation Register, offset: 0x108 */
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__IO uint32_t PWR_OPT; /**< Power Mode Options Register, offset: 0x10C */
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__I uint32_t CMD_CHECK; /**< FMU Command Check Register, offset: 0x110 */
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uint8_t RESERVED_1[12];
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__IO uint32_t BSEL; /**< FMU Block Select Register, offset: 0x120 */
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__IO uint32_t MSIZE; /**< FMU Memory Size Register, offset: 0x124 */
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__IO uint32_t FLASH_RD_ADD; /**< Flash Read Address Register, offset: 0x128 */
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uint8_t RESERVED_2[4];
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__IO uint32_t FLASH_STOP_ADD; /**< Flash Stop Address Register, offset: 0x130 */
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__IO uint32_t FLASH_RD_CTRL; /**< Flash Read Control Register, offset: 0x134 */
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__IO uint32_t MM_ADDR; /**< Memory Map Address Register, offset: 0x138 */
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uint8_t RESERVED_3[4];
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__IO uint32_t MM_WDATA; /**< Memory Map Write Data Register, offset: 0x140 */
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__IO uint32_t MM_CTL; /**< Memory Map Control Register, offset: 0x144 */
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__IO uint32_t UINT_CTL; /**< User Interface Control Register, offset: 0x148 */
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__IO uint32_t RD_DATA0; /**< Read Data 0 Register, offset: 0x14C */
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__IO uint32_t RD_DATA1; /**< Read Data 1 Register, offset: 0x150 */
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__IO uint32_t RD_DATA2; /**< Read Data 2 Register, offset: 0x154 */
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__IO uint32_t RD_DATA3; /**< Read Data 3 Register, offset: 0x158 */
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__IO uint32_t PARITY; /**< Parity Register, offset: 0x15C */
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__IO uint32_t RD_PATH_CTRL_STATUS; /**< Read Path Control and Status Register, offset: 0x160 */
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__IO uint32_t SMW_DIN0; /**< SMW DIN 0 Register, offset: 0x164 */
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__IO uint32_t SMW_DIN1; /**< SMW DIN 1 Register, offset: 0x168 */
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__IO uint32_t SMW_DIN2; /**< SMW DIN 2 Register, offset: 0x16C */
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__IO uint32_t SMW_DIN3; /**< SMW DIN 3 Register, offset: 0x170 */
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__IO uint32_t SMW_ADDR; /**< SMW Address Register, offset: 0x174 */
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__IO uint32_t SMW_CMD_WAIT; /**< SMW Command and Wait Register, offset: 0x178 */
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__I uint32_t SMW_STATUS; /**< SMW Status Register, offset: 0x17C */
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__IO uint32_t SOCTRIM0_0; /**< SoC Trim Phrase 0 Word 0 Register, offset: 0x180 */
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__IO uint32_t SOCTRIM0_1; /**< SoC Trim Phrase 0 Word 1 Register, offset: 0x184 */
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__IO uint32_t SOCTRIM0_2; /**< SoC Trim Phrase 0 Word 2 Register, offset: 0x188 */
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__IO uint32_t SOCTRIM0_3; /**< SoC Trim Phrase 0 Word 3 Register, offset: 0x18C */
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__IO uint32_t SOCTRIM1_0; /**< SoC Trim Phrase 1 Word 0 Register, offset: 0x190 */
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__IO uint32_t SOCTRIM1_1; /**< SoC Trim Phrase 1 Word 1 Register, offset: 0x194 */
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__IO uint32_t SOCTRIM1_2; /**< SoC Trim Phrase 1 Word 2 Register, offset: 0x198 */
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__IO uint32_t SOCTRIM1_3; /**< SoC Trim Phrase 1 Word 3 Register, offset: 0x19C */
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__IO uint32_t SOCTRIM2_0; /**< SoC Trim Phrase 2 Word 0 Register, offset: 0x1A0 */
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__IO uint32_t SOCTRIM2_1; /**< SoC Trim Phrase 2 Word 1 Register, offset: 0x1A4 */
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__IO uint32_t SOCTRIM2_2; /**< SoC Trim Phrase 2 Word 2 Register, offset: 0x1A8 */
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__IO uint32_t SOCTRIM2_3; /**< SoC Trim Phrase 2 Word 3 Register, offset: 0x1AC */
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__IO uint32_t SOCTRIM3_0; /**< SoC Trim Phrase 3 Word 0 Register, offset: 0x1B0 */
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__IO uint32_t SOCTRIM3_1; /**< SoC Trim Phrase 3 Word 1 Register, offset: 0x1B4 */
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__IO uint32_t SOCTRIM3_2; /**< SoC Trim Phrase 3 Word 2 Register, offset: 0x1B8 */
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__IO uint32_t SOCTRIM3_3; /**< SoC Trim Phrase 3 Word 3 Register, offset: 0x1BC */
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__IO uint32_t SOCTRIM4_0; /**< SoC Trim Phrase 4 Word 0 Register, offset: 0x1C0 */
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__IO uint32_t SOCTRIM4_1; /**< SoC Trim Phrase 4 Word 1 Register, offset: 0x1C4 */
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__IO uint32_t SOCTRIM4_2; /**< SoC Trim Phrase 4 Word 2 Register, offset: 0x1C8 */
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__IO uint32_t SOCTRIM4_3; /**< SoC Trim Phrase 4 Word 3 Register, offset: 0x1CC */
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__IO uint32_t SOCTRIM5_0; /**< SoC Trim Phrase 5 Word 0 Register, offset: 0x1D0 */
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__IO uint32_t SOCTRIM5_1; /**< SoC Trim Phrase 5 Word 1 Register, offset: 0x1D4 */
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__IO uint32_t SOCTRIM5_2; /**< SoC Trim Phrase 5 Word 2 Register, offset: 0x1D8 */
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__IO uint32_t SOCTRIM5_3; /**< SoC Trim Phrase 5 Word 3 Register, offset: 0x1DC */
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__IO uint32_t SOCTRIM6_0; /**< SoC Trim Phrase 6 Word 0 Register, offset: 0x1E0 */
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__IO uint32_t SOCTRIM6_1; /**< SoC Trim Phrase 6 Word 1 Register, offset: 0x1E4 */
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__IO uint32_t SOCTRIM6_2; /**< SoC Trim Phrase 6 Word 2 Register, offset: 0x1E8 */
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__IO uint32_t SOCTRIM6_3; /**< SoC Trim Phrase 6 Word 3 Register, offset: 0x1EC */
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__IO uint32_t SOCTRIM7_0; /**< SoC Trim Phrase 7 Word 0 Register, offset: 0x1F0 */
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__IO uint32_t SOCTRIM7_1; /**< SoC Trim Phrase 7 Word 1 Register, offset: 0x1F4 */
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__IO uint32_t SOCTRIM7_2; /**< SoC Trim Phrase 7 Word 2 Register, offset: 0x1F8 */
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__IO uint32_t SOCTRIM7_3; /**< SoC Trim Phrase 7 Word 3 Register, offset: 0x1FC */
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uint8_t RESERVED_4[4];
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|
__IO uint32_t R_IP_CONFIG; /**< BIST Configuration Register, offset: 0x204 */
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|
__IO uint32_t R_TESTCODE; /**< BIST Test Code Register, offset: 0x208 */
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__IO uint32_t R_DFT_CTRL; /**< BIST DFT Control Register, offset: 0x20C */
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__IO uint32_t R_ADR_CTRL; /**< BIST Address Control Register, offset: 0x210 */
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__IO uint32_t R_DATA_CTRL0; /**< BIST Data Control 0 Register, offset: 0x214 */
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__IO uint32_t R_PIN_CTRL; /**< BIST Pin Control Register, offset: 0x218 */
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__IO uint32_t R_CNT_LOOP_CTRL; /**< BIST Loop Count Control Register, offset: 0x21C */
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__IO uint32_t R_TIMER_CTRL; /**< BIST Timer Control Register, offset: 0x220 */
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|
__IO uint32_t R_TEST_CTRL; /**< BIST Test Control Register, offset: 0x224 */
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__O uint32_t R_ABORT_LOOP; /**< BIST Abort Loop Register, offset: 0x228 */
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__I uint32_t R_ADR_QUERY; /**< BIST Address Query Register, offset: 0x22C */
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__I uint32_t R_DOUT_QUERY0; /**< BIST DOUT Query 0 Register, offset: 0x230 */
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uint8_t RESERVED_5[8];
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__I uint32_t R_SMW_QUERY; /**< BIST SMW Query Register, offset: 0x23C */
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__IO uint32_t R_SMW_SETTING0; /**< BIST SMW Setting 0 Register, offset: 0x240 */
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__IO uint32_t R_SMW_SETTING1; /**< BIST SMW Setting 1 Register, offset: 0x244 */
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__IO uint32_t R_SMP_WHV0; /**< BIST SMP WHV Setting 0 Register, offset: 0x248 */
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__IO uint32_t R_SMP_WHV1; /**< BIST SMP WHV Setting 1 Register, offset: 0x24C */
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__IO uint32_t R_SME_WHV0; /**< BIST SME WHV Setting 0 Register, offset: 0x250 */
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__IO uint32_t R_SME_WHV1; /**< BIST SME WHV Setting 1 Register, offset: 0x254 */
|
|
__IO uint32_t R_SMW_SETTING2; /**< BIST SMW Setting 2 Register, offset: 0x258 */
|
|
__I uint32_t R_D_MISR0; /**< BIST DIN MISR 0 Register, offset: 0x25C */
|
|
__I uint32_t R_A_MISR0; /**< BIST Address MISR 0 Register, offset: 0x260 */
|
|
__I uint32_t R_C_MISR0; /**< BIST Control MISR 0 Register, offset: 0x264 */
|
|
__IO uint32_t R_SMW_SETTING3; /**< BIST SMW Setting 3 Register, offset: 0x268 */
|
|
__IO uint32_t R_DATA_CTRL1; /**< BIST Data Control 1 Register, offset: 0x26C */
|
|
__IO uint32_t R_DATA_CTRL2; /**< BIST Data Control 2 Register, offset: 0x270 */
|
|
__IO uint32_t R_DATA_CTRL3; /**< BIST Data Control 3 Register, offset: 0x274 */
|
|
uint8_t RESERVED_6[8];
|
|
__I uint32_t R_REPAIR0_0; /**< BIST Repair 0 for Block 0 Register, offset: 0x280 */
|
|
__I uint32_t R_REPAIR0_1; /**< BIST Repair 1 Block 0 Register, offset: 0x284 */
|
|
__I uint32_t R_REPAIR1_0; /**< BIST Repair 0 Block 1 Register, offset: 0x288 */
|
|
__I uint32_t R_REPAIR1_1; /**< BIST Repair 1 Block 1 Register, offset: 0x28C */
|
|
uint8_t RESERVED_7[132];
|
|
__IO uint32_t R_DATA_CTRL0_EX; /**< BIST Data Control 0 Extension Register, offset: 0x314 */
|
|
uint8_t RESERVED_8[8];
|
|
__IO uint32_t R_TIMER_CTRL_EX; /**< BIST Timer Control Extension Register, offset: 0x320 */
|
|
uint8_t RESERVED_9[12];
|
|
__I uint32_t R_DOUT_QUERY1; /**< BIST DOUT Query 1 Register, offset: 0x330 */
|
|
uint8_t RESERVED_10[40];
|
|
__I uint32_t R_D_MISR1; /**< BIST DIN MISR 1 Register, offset: 0x35C */
|
|
__I uint32_t R_A_MISR1; /**< BIST Address MISR 1 Register, offset: 0x360 */
|
|
__I uint32_t R_C_MISR1; /**< BIST Control MISR 1 Register, offset: 0x364 */
|
|
uint8_t RESERVED_11[4];
|
|
__IO uint32_t R_DATA_CTRL1_EX; /**< BIST Data Control 1 Extension Register, offset: 0x36C */
|
|
__IO uint32_t R_DATA_CTRL2_EX; /**< BIST Data Control 2 Extension Register, offset: 0x370 */
|
|
__IO uint32_t R_DATA_CTRL3_EX; /**< BIST Data Control 3 Extension Register, offset: 0x374 */
|
|
uint8_t RESERVED_12[136];
|
|
__IO uint32_t SMW_TIMER_OPTION; /**< SMW Timer Option Register, offset: 0x400 */
|
|
__IO uint32_t SMW_SETTING_OPTION0; /**< SMW Setting Option 0 Register, offset: 0x404 */
|
|
__IO uint32_t SMW_SETTING_OPTION2; /**< SMW Setting Option 2 Register, offset: 0x408 */
|
|
__IO uint32_t SMW_SETTING_OPTION3; /**< SMW Setting Option 3 Register, offset: 0x40C */
|
|
__IO uint32_t SMW_SMP_WHV_OPTION0; /**< SMW SMP WHV Option 0 Register, offset: 0x410 */
|
|
__IO uint32_t SMW_SME_WHV_OPTION0; /**< SMW SME WHV Option 0 Register, offset: 0x414 */
|
|
__IO uint32_t SMW_SETTING_OPTION1; /**< SMW Setting Option 1 Register, offset: 0x418 */
|
|
__IO uint32_t SMW_SMP_WHV_OPTION1; /**< SMW SMP WHV Option 1 Register, offset: 0x41C */
|
|
__IO uint32_t SMW_SME_WHV_OPTION1; /**< SMW SME WHV Option 1 Register, offset: 0x420 */
|
|
uint8_t RESERVED_13[220];
|
|
__IO uint32_t REPAIR0_0; /**< FMU Repair 0 Block 0 Register, offset: 0x500 */
|
|
__IO uint32_t REPAIR0_1; /**< FMU Repair 1 Block 0 Register, offset: 0x504 */
|
|
__IO uint32_t REPAIR1_0; /**< FMU Repair 0 Block 1 Register, offset: 0x508 */
|
|
__IO uint32_t REPAIR1_1; /**< FMU Repair 1 Block 1 Register, offset: 0x50C */
|
|
uint8_t RESERVED_14[240];
|
|
__IO uint32_t SMW_HB_SIGNALS; /**< SMW HB Signals Register, offset: 0x600 */
|
|
__IO uint32_t BIST_DUMP_CTRL; /**< BIST Datadump Control Register, offset: 0x604 */
|
|
uint8_t RESERVED_15[4];
|
|
__IO uint32_t ATX_PIN_CTRL; /**< ATX Pin Control Register, offset: 0x60C */
|
|
__IO uint32_t FAILCNT; /**< Fail Count Register, offset: 0x610 */
|
|
__IO uint32_t PGM_PULSE_CNT0; /**< Block 0 Program Pulse Count Register, offset: 0x614 */
|
|
__IO uint32_t PGM_PULSE_CNT1; /**< Block 1 Program Pulse Count Register, offset: 0x618 */
|
|
__IO uint32_t ERS_PULSE_CNT; /**< Erase Pulse Count Register, offset: 0x61C */
|
|
__IO uint32_t MAX_PULSE_CNT; /**< Maximum Pulse Count Register, offset: 0x620 */
|
|
__IO uint32_t PORT_CTRL; /**< Port Control Register, offset: 0x624 */
|
|
} FMUTEST_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- FMUTEST Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup FMUTEST_Register_Masks FMUTEST Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name FSTAT - Flash Status Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_FSTAT_FAIL_MASK (0x1U)
|
|
#define FMUTEST_FSTAT_FAIL_SHIFT (0U)
|
|
/*! FAIL - Command Fail Flag
|
|
* 0b0..Error not detected
|
|
* 0b1..Error detected
|
|
*/
|
|
#define FMUTEST_FSTAT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_FAIL_SHIFT)) & FMUTEST_FSTAT_FAIL_MASK)
|
|
|
|
#define FMUTEST_FSTAT_CMDABT_MASK (0x4U)
|
|
#define FMUTEST_FSTAT_CMDABT_SHIFT (2U)
|
|
/*! CMDABT - Command Abort Flag
|
|
* 0b0..No command abort detected
|
|
* 0b1..Command abort detected
|
|
*/
|
|
#define FMUTEST_FSTAT_CMDABT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CMDABT_SHIFT)) & FMUTEST_FSTAT_CMDABT_MASK)
|
|
|
|
#define FMUTEST_FSTAT_PVIOL_MASK (0x10U)
|
|
#define FMUTEST_FSTAT_PVIOL_SHIFT (4U)
|
|
/*! PVIOL - Command Protection Violation Flag
|
|
* 0b0..No protection violation detected
|
|
* 0b1..Protection violation detected
|
|
*/
|
|
#define FMUTEST_FSTAT_PVIOL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_PVIOL_SHIFT)) & FMUTEST_FSTAT_PVIOL_MASK)
|
|
|
|
#define FMUTEST_FSTAT_ACCERR_MASK (0x20U)
|
|
#define FMUTEST_FSTAT_ACCERR_SHIFT (5U)
|
|
/*! ACCERR - Command Access Error Flag
|
|
* 0b0..No access error detected
|
|
* 0b1..Access error detected
|
|
*/
|
|
#define FMUTEST_FSTAT_ACCERR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_ACCERR_SHIFT)) & FMUTEST_FSTAT_ACCERR_MASK)
|
|
|
|
#define FMUTEST_FSTAT_CWSABT_MASK (0x40U)
|
|
#define FMUTEST_FSTAT_CWSABT_SHIFT (6U)
|
|
/*! CWSABT - Command Write Sequence Abort Flag
|
|
* 0b0..Command write sequence not aborted
|
|
* 0b1..Command write sequence aborted
|
|
*/
|
|
#define FMUTEST_FSTAT_CWSABT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CWSABT_SHIFT)) & FMUTEST_FSTAT_CWSABT_MASK)
|
|
|
|
#define FMUTEST_FSTAT_CCIF_MASK (0x80U)
|
|
#define FMUTEST_FSTAT_CCIF_SHIFT (7U)
|
|
/*! CCIF - Command Complete Interrupt Flag
|
|
* 0b0..Flash command or initialization in progress
|
|
* 0b1..Flash command or initialization has completed
|
|
*/
|
|
#define FMUTEST_FSTAT_CCIF(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CCIF_SHIFT)) & FMUTEST_FSTAT_CCIF_MASK)
|
|
|
|
#define FMUTEST_FSTAT_CMDPRT_MASK (0x300U)
|
|
#define FMUTEST_FSTAT_CMDPRT_SHIFT (8U)
|
|
/*! CMDPRT - Command Protection Level
|
|
* 0b00..Secure, normal access
|
|
* 0b01..Secure, privileged access
|
|
* 0b10..Nonsecure, normal access
|
|
* 0b11..Nonsecure, privileged access
|
|
*/
|
|
#define FMUTEST_FSTAT_CMDPRT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CMDPRT_SHIFT)) & FMUTEST_FSTAT_CMDPRT_MASK)
|
|
|
|
#define FMUTEST_FSTAT_CMDP_MASK (0x800U)
|
|
#define FMUTEST_FSTAT_CMDP_SHIFT (11U)
|
|
/*! CMDP - Command Protection Status Flag
|
|
* 0b0..Command protection level and domain ID are stale
|
|
* 0b1..Command protection level (CMDPRT) and domain ID (CMDDID) are set
|
|
*/
|
|
#define FMUTEST_FSTAT_CMDP(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CMDP_SHIFT)) & FMUTEST_FSTAT_CMDP_MASK)
|
|
|
|
#define FMUTEST_FSTAT_CMDDID_MASK (0xF000U)
|
|
#define FMUTEST_FSTAT_CMDDID_SHIFT (12U)
|
|
/*! CMDDID - Command Domain ID */
|
|
#define FMUTEST_FSTAT_CMDDID(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CMDDID_SHIFT)) & FMUTEST_FSTAT_CMDDID_MASK)
|
|
|
|
#define FMUTEST_FSTAT_DFDIF_MASK (0x10000U)
|
|
#define FMUTEST_FSTAT_DFDIF_SHIFT (16U)
|
|
/*! DFDIF - Double Bit Fault Detect Interrupt Flag
|
|
* 0b0..Double bit fault not detected during a valid flash read access from the FMC
|
|
* 0b1..Double bit fault detected (or FCTRL[FDFD] is set) during a valid flash read access from the FMC
|
|
*/
|
|
#define FMUTEST_FSTAT_DFDIF(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_DFDIF_SHIFT)) & FMUTEST_FSTAT_DFDIF_MASK)
|
|
|
|
#define FMUTEST_FSTAT_SALV_USED_MASK (0x20000U)
|
|
#define FMUTEST_FSTAT_SALV_USED_SHIFT (17U)
|
|
/*! SALV_USED - Salvage Used for Erase operation
|
|
* 0b0..Salvage not used during the last operation
|
|
* 0b1..Salvage used during the last erase operation
|
|
*/
|
|
#define FMUTEST_FSTAT_SALV_USED(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_SALV_USED_SHIFT)) & FMUTEST_FSTAT_SALV_USED_MASK)
|
|
|
|
#define FMUTEST_FSTAT_PEWEN_MASK (0x3000000U)
|
|
#define FMUTEST_FSTAT_PEWEN_SHIFT (24U)
|
|
/*! PEWEN - Program-Erase Write Enable Control
|
|
* 0b00..Writes are not enabled
|
|
* 0b01..Writes are enabled for one flash or IFR phrase (phrase programming, sector erase)
|
|
* 0b10..Writes are enabled for one flash or IFR page (page programming)
|
|
* 0b11..Reserved
|
|
*/
|
|
#define FMUTEST_FSTAT_PEWEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_PEWEN_SHIFT)) & FMUTEST_FSTAT_PEWEN_MASK)
|
|
|
|
#define FMUTEST_FSTAT_PERDY_MASK (0x80000000U)
|
|
#define FMUTEST_FSTAT_PERDY_SHIFT (31U)
|
|
/*! PERDY - Program/Erase Ready Control/Status Flag
|
|
* 0b0..Program or sector erase command operation is not stalled
|
|
* 0b1..Program or sector erase command operation is stalled
|
|
*/
|
|
#define FMUTEST_FSTAT_PERDY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_PERDY_SHIFT)) & FMUTEST_FSTAT_PERDY_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FCNFG - Flash Configuration Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_FCNFG_CCIE_MASK (0x80U)
|
|
#define FMUTEST_FCNFG_CCIE_SHIFT (7U)
|
|
/*! CCIE - Command Complete Interrupt Enable
|
|
* 0b0..Command complete interrupt disabled
|
|
* 0b1..Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set.
|
|
*/
|
|
#define FMUTEST_FCNFG_CCIE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCNFG_CCIE_SHIFT)) & FMUTEST_FCNFG_CCIE_MASK)
|
|
|
|
#define FMUTEST_FCNFG_ERSREQ_MASK (0x100U)
|
|
#define FMUTEST_FCNFG_ERSREQ_SHIFT (8U)
|
|
/*! ERSREQ - Mass Erase (Erase All) Request
|
|
* 0b0..No request or request complete
|
|
* 0b1..Request to run the Mass Erase operation
|
|
*/
|
|
#define FMUTEST_FCNFG_ERSREQ(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCNFG_ERSREQ_SHIFT)) & FMUTEST_FCNFG_ERSREQ_MASK)
|
|
|
|
#define FMUTEST_FCNFG_DFDIE_MASK (0x10000U)
|
|
#define FMUTEST_FCNFG_DFDIE_SHIFT (16U)
|
|
/*! DFDIE - Double Bit Fault Detect Interrupt Enable
|
|
* 0b0..Double bit fault detect interrupt disabled
|
|
* 0b1..Double bit fault detect interrupt enabled; an interrupt request is generated whenever the FSTAT[DFDIF] flag is set
|
|
*/
|
|
#define FMUTEST_FCNFG_DFDIE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCNFG_DFDIE_SHIFT)) & FMUTEST_FCNFG_DFDIE_MASK)
|
|
|
|
#define FMUTEST_FCNFG_ERSIEN0_MASK (0xF000000U)
|
|
#define FMUTEST_FCNFG_ERSIEN0_SHIFT (24U)
|
|
/*! ERSIEN0 - Erase IFR Sector Enable - Block 0
|
|
* 0b0000..Block 0 IFR Sector X is protected from erase by ERSSCR command
|
|
* 0b0001..Block 0 IFR Sector X is not protected from erase by ERSSCR command
|
|
*/
|
|
#define FMUTEST_FCNFG_ERSIEN0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCNFG_ERSIEN0_SHIFT)) & FMUTEST_FCNFG_ERSIEN0_MASK)
|
|
|
|
#define FMUTEST_FCNFG_ERSIEN1_MASK (0xF0000000U)
|
|
#define FMUTEST_FCNFG_ERSIEN1_SHIFT (28U)
|
|
/*! ERSIEN1 - Erase IFR Sector Enable - Block 1 (for dual block configs)
|
|
* 0b0000..Block 1 IFR Sector X is protected from erase by ERSSCR command
|
|
* 0b0001..Block 1 IFR Sector X is not protected from erase by ERSSCR command
|
|
*/
|
|
#define FMUTEST_FCNFG_ERSIEN1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCNFG_ERSIEN1_SHIFT)) & FMUTEST_FCNFG_ERSIEN1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FCTRL - Flash Control Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_FCTRL_RWSC_MASK (0xFU)
|
|
#define FMUTEST_FCTRL_RWSC_SHIFT (0U)
|
|
/*! RWSC - Read Wait-State Control
|
|
* 0b0000..no additional wait-states are added (single cycle access)
|
|
* 0b0001..1 additional wait-state is added
|
|
* 0b0010..2 additional wait-states are added
|
|
* 0b0011..3 additional wait-states are added
|
|
* 0b0100..4 additional wait-states are added
|
|
* 0b0101..5 additional wait-states are added
|
|
* 0b0110..6 additional wait-states are added
|
|
* 0b0111..7 additional wait-states are added
|
|
* 0b1000..8 additional wait-states are added
|
|
* 0b1001..9 additional wait-states are added
|
|
* 0b1010..10 additional wait-states are added
|
|
* 0b1011..11 additional wait-states are added
|
|
* 0b1100..12 additional wait-states are added
|
|
* 0b1101..13 additional wait-states are added
|
|
* 0b1110..14 additional wait-states are added
|
|
* 0b1111..15 additional wait-states are added
|
|
*/
|
|
#define FMUTEST_FCTRL_RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCTRL_RWSC_SHIFT)) & FMUTEST_FCTRL_RWSC_MASK)
|
|
|
|
#define FMUTEST_FCTRL_LSACTIVE_MASK (0x100U)
|
|
#define FMUTEST_FCTRL_LSACTIVE_SHIFT (8U)
|
|
/*! LSACTIVE - Low Speed Active Mode
|
|
* 0b0..Full speed active mode requested
|
|
* 0b1..Low speed active mode requested
|
|
*/
|
|
#define FMUTEST_FCTRL_LSACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCTRL_LSACTIVE_SHIFT)) & FMUTEST_FCTRL_LSACTIVE_MASK)
|
|
|
|
#define FMUTEST_FCTRL_FDFD_MASK (0x10000U)
|
|
#define FMUTEST_FCTRL_FDFD_SHIFT (16U)
|
|
/*! FDFD - Force Double Bit Fault Detect
|
|
* 0b0..FSTAT[DFDIF] sets only if a double bit fault is detected during a valid flash read access from the FMC
|
|
* 0b1..FSTAT[DFDIF] sets during any valid flash read access from the FMC; an interrupt request is generated if the DFDIE bit is set
|
|
*/
|
|
#define FMUTEST_FCTRL_FDFD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCTRL_FDFD_SHIFT)) & FMUTEST_FCTRL_FDFD_MASK)
|
|
|
|
#define FMUTEST_FCTRL_ABTREQ_MASK (0x1000000U)
|
|
#define FMUTEST_FCTRL_ABTREQ_SHIFT (24U)
|
|
/*! ABTREQ - Abort Request
|
|
* 0b0..No request to abort a command write sequence
|
|
* 0b1..Request to abort a command write sequence
|
|
*/
|
|
#define FMUTEST_FCTRL_ABTREQ(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCTRL_ABTREQ_SHIFT)) & FMUTEST_FCTRL_ABTREQ_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FTEST - Flash Test Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_FTEST_TMECTL_MASK (0x1U)
|
|
#define FMUTEST_FTEST_TMECTL_SHIFT (0U)
|
|
/*! TMECTL - Test Mode Entry Control
|
|
* 0b0..FTEST register always reads 0 and writes to FTEST are ignored
|
|
* 0b1..FTEST register is readable and can be written to enable writability of TME
|
|
*/
|
|
#define FMUTEST_FTEST_TMECTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FTEST_TMECTL_SHIFT)) & FMUTEST_FTEST_TMECTL_MASK)
|
|
|
|
#define FMUTEST_FTEST_TMEWR_MASK (0x2U)
|
|
#define FMUTEST_FTEST_TMEWR_SHIFT (1U)
|
|
/*! TMEWR - Test Mode Entry Writable
|
|
* 0b0..TME bit is not writable
|
|
* 0b1..TME bit is writable
|
|
*/
|
|
#define FMUTEST_FTEST_TMEWR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FTEST_TMEWR_SHIFT)) & FMUTEST_FTEST_TMEWR_MASK)
|
|
|
|
#define FMUTEST_FTEST_TME_MASK (0x4U)
|
|
#define FMUTEST_FTEST_TME_SHIFT (2U)
|
|
/*! TME - Test Mode Entry
|
|
* 0b0..Test mode entry not requested
|
|
* 0b1..Test mode entry requested
|
|
*/
|
|
#define FMUTEST_FTEST_TME(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FTEST_TME_SHIFT)) & FMUTEST_FTEST_TME_MASK)
|
|
|
|
#define FMUTEST_FTEST_TMODE_MASK (0x8U)
|
|
#define FMUTEST_FTEST_TMODE_SHIFT (3U)
|
|
/*! TMODE - Test Mode Status
|
|
* 0b0..Test mode not active
|
|
* 0b1..Test mode active
|
|
*/
|
|
#define FMUTEST_FTEST_TMODE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FTEST_TMODE_SHIFT)) & FMUTEST_FTEST_TMODE_MASK)
|
|
|
|
#define FMUTEST_FTEST_TMELOCK_MASK (0x10U)
|
|
#define FMUTEST_FTEST_TMELOCK_SHIFT (4U)
|
|
/*! TMELOCK - Test Mode Entry Lock
|
|
* 0b0..FTEST register not locked from accepting writes
|
|
* 0b1..FTEST register locked from accepting writes
|
|
*/
|
|
#define FMUTEST_FTEST_TMELOCK(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FTEST_TMELOCK_SHIFT)) & FMUTEST_FTEST_TMELOCK_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FCCOB0 - Flash Command Control 0 Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_FCCOB0_CMDCODE_MASK (0xFFU)
|
|
#define FMUTEST_FCCOB0_CMDCODE_SHIFT (0U)
|
|
/*! CMDCODE - Command code */
|
|
#define FMUTEST_FCCOB0_CMDCODE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB0_CMDCODE_SHIFT)) & FMUTEST_FCCOB0_CMDCODE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FCCOB1 - Flash Command Control 1 Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_FCCOB1_CMDOPT_MASK (0xFFU)
|
|
#define FMUTEST_FCCOB1_CMDOPT_SHIFT (0U)
|
|
/*! CMDOPT - Command options */
|
|
#define FMUTEST_FCCOB1_CMDOPT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB1_CMDOPT_SHIFT)) & FMUTEST_FCCOB1_CMDOPT_MASK)
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/*! @} */
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/*! @name FCCOB2 - Flash Command Control 2 Register */
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/*! @{ */
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#define FMUTEST_FCCOB2_CMDADDR_MASK (0xFFFFFFFFU)
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#define FMUTEST_FCCOB2_CMDADDR_SHIFT (0U)
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/*! CMDADDR - Command starting address */
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#define FMUTEST_FCCOB2_CMDADDR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB2_CMDADDR_SHIFT)) & FMUTEST_FCCOB2_CMDADDR_MASK)
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/*! @} */
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/*! @name FCCOB3 - Flash Command Control 3 Register */
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/*! @{ */
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#define FMUTEST_FCCOB3_CMDADDRE_MASK (0xFFFFFFFFU)
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#define FMUTEST_FCCOB3_CMDADDRE_SHIFT (0U)
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/*! CMDADDRE - Command ending address */
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#define FMUTEST_FCCOB3_CMDADDRE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB3_CMDADDRE_SHIFT)) & FMUTEST_FCCOB3_CMDADDRE_MASK)
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/*! @} */
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/*! @name FCCOB4 - Flash Command Control 4 Register */
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/*! @{ */
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#define FMUTEST_FCCOB4_CMDDATA0_MASK (0xFFFFFFFFU)
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#define FMUTEST_FCCOB4_CMDDATA0_SHIFT (0U)
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/*! CMDDATA0 - Command data word 0 */
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#define FMUTEST_FCCOB4_CMDDATA0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB4_CMDDATA0_SHIFT)) & FMUTEST_FCCOB4_CMDDATA0_MASK)
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/*! @} */
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/*! @name FCCOB5 - Flash Command Control 5 Register */
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/*! @{ */
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#define FMUTEST_FCCOB5_CMDDATA1_MASK (0xFFFFFFFFU)
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#define FMUTEST_FCCOB5_CMDDATA1_SHIFT (0U)
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/*! CMDDATA1 - Command data word 1 */
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#define FMUTEST_FCCOB5_CMDDATA1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB5_CMDDATA1_SHIFT)) & FMUTEST_FCCOB5_CMDDATA1_MASK)
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/*! @} */
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/*! @name FCCOB6 - Flash Command Control 6 Register */
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/*! @{ */
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#define FMUTEST_FCCOB6_CMDDATA2_MASK (0xFFFFFFFFU)
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#define FMUTEST_FCCOB6_CMDDATA2_SHIFT (0U)
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/*! CMDDATA2 - Command data word 2 */
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#define FMUTEST_FCCOB6_CMDDATA2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB6_CMDDATA2_SHIFT)) & FMUTEST_FCCOB6_CMDDATA2_MASK)
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/*! @} */
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/*! @name FCCOB7 - Flash Command Control 7 Register */
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/*! @{ */
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#define FMUTEST_FCCOB7_CMDDATA3_MASK (0xFFFFFFFFU)
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#define FMUTEST_FCCOB7_CMDDATA3_SHIFT (0U)
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/*! CMDDATA3 - Command data word 3 */
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#define FMUTEST_FCCOB7_CMDDATA3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB7_CMDDATA3_SHIFT)) & FMUTEST_FCCOB7_CMDDATA3_MASK)
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/*! @} */
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/*! @name RESET_STATUS - FMU Initialization Tracking Register */
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/*! @{ */
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#define FMUTEST_RESET_STATUS_ARY_TRIM_DONE_MASK (0x1U)
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#define FMUTEST_RESET_STATUS_ARY_TRIM_DONE_SHIFT (0U)
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/*! ARY_TRIM_DONE - Array Trim Complete
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* 0b0..Recall register load operation has not been completed
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* 0b1..Recall register load operation has completed
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*/
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#define FMUTEST_RESET_STATUS_ARY_TRIM_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_ARY_TRIM_DONE_SHIFT)) & FMUTEST_RESET_STATUS_ARY_TRIM_DONE_MASK)
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#define FMUTEST_RESET_STATUS_FMU_PARM_EN_MASK (0x2U)
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#define FMUTEST_RESET_STATUS_FMU_PARM_EN_SHIFT (1U)
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/*! FMU_PARM_EN - Status of the C0DE_C0DEh check to enable loading of the FMU parameters
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* 0b0..C0DE_C0DEh check not attempted
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* 0b1..C0DE_C0DEh check completed
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*/
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#define FMUTEST_RESET_STATUS_FMU_PARM_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_FMU_PARM_EN_SHIFT)) & FMUTEST_RESET_STATUS_FMU_PARM_EN_MASK)
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#define FMUTEST_RESET_STATUS_FMU_PARM_DONE_MASK (0x4U)
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#define FMUTEST_RESET_STATUS_FMU_PARM_DONE_SHIFT (2U)
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/*! FMU_PARM_DONE - FMU Register Load Complete
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* 0b0..FMU registers have not been loaded
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* 0b1..FMU registers have been loaded
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*/
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#define FMUTEST_RESET_STATUS_FMU_PARM_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_FMU_PARM_DONE_SHIFT)) & FMUTEST_RESET_STATUS_FMU_PARM_DONE_MASK)
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#define FMUTEST_RESET_STATUS_SOC_TRIM_EN_MASK (0x8U)
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#define FMUTEST_RESET_STATUS_SOC_TRIM_EN_SHIFT (3U)
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/*! SOC_TRIM_EN - Status of the C0DE_C0DEh check to enable loading of the SoC trim settings
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* 0b0..C0DE_C0DEh check not attempted
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* 0b1..C0DE_C0DEh check completed
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|
*/
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#define FMUTEST_RESET_STATUS_SOC_TRIM_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_SOC_TRIM_EN_SHIFT)) & FMUTEST_RESET_STATUS_SOC_TRIM_EN_MASK)
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#define FMUTEST_RESET_STATUS_SOC_TRIM_ECC_MASK (0x10U)
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#define FMUTEST_RESET_STATUS_SOC_TRIM_ECC_SHIFT (4U)
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/*! SOC_TRIM_ECC - Status of the C0DE_C0DEh check for enabling ECC decoder during reads of SoC trim settings
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* 0b0..C0DE_C0DEh check failed
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* 0b1..C0DE_C0DEh check passed
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*/
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#define FMUTEST_RESET_STATUS_SOC_TRIM_ECC(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_SOC_TRIM_ECC_SHIFT)) & FMUTEST_RESET_STATUS_SOC_TRIM_ECC_MASK)
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#define FMUTEST_RESET_STATUS_SOC_TRIM_DONE_MASK (0x20U)
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#define FMUTEST_RESET_STATUS_SOC_TRIM_DONE_SHIFT (5U)
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/*! SOC_TRIM_DONE - SoC Trim Complete
|
|
* 0b0..SoC Trim registers have not been updated
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* 0b1..All SoC Trim registers have been updated
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*/
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#define FMUTEST_RESET_STATUS_SOC_TRIM_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_SOC_TRIM_DONE_SHIFT)) & FMUTEST_RESET_STATUS_SOC_TRIM_DONE_MASK)
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#define FMUTEST_RESET_STATUS_RPR_DONE_MASK (0x40U)
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#define FMUTEST_RESET_STATUS_RPR_DONE_SHIFT (6U)
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/*! RPR_DONE - Array Repair Complete
|
|
* 0b0..Repair registers have not been loaded
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* 0b1..Repair registers have been loaded
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|
*/
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#define FMUTEST_RESET_STATUS_RPR_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_RPR_DONE_SHIFT)) & FMUTEST_RESET_STATUS_RPR_DONE_MASK)
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#define FMUTEST_RESET_STATUS_INIT_DONE_MASK (0x80U)
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#define FMUTEST_RESET_STATUS_INIT_DONE_SHIFT (7U)
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/*! INIT_DONE - Initialization Done
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* 0b0..All initialization steps did not complete
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* 0b1..All initialization steps completed
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|
*/
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#define FMUTEST_RESET_STATUS_INIT_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_INIT_DONE_SHIFT)) & FMUTEST_RESET_STATUS_INIT_DONE_MASK)
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#define FMUTEST_RESET_STATUS_RST_SF_ERR_MASK (0x100U)
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#define FMUTEST_RESET_STATUS_RST_SF_ERR_SHIFT (8U)
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/*! RST_SF_ERR - ECC Single Fault during Reset Recovery
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|
* 0b0..No single-bit faults detected during initialization
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|
* 0b1..At least one single ECC fault was detected during initialization
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|
*/
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#define FMUTEST_RESET_STATUS_RST_SF_ERR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_RST_SF_ERR_SHIFT)) & FMUTEST_RESET_STATUS_RST_SF_ERR_MASK)
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#define FMUTEST_RESET_STATUS_RST_DF_ERR_MASK (0x200U)
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#define FMUTEST_RESET_STATUS_RST_DF_ERR_SHIFT (9U)
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/*! RST_DF_ERR - ECC Double Fault during Reset Recovery
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* 0b0..No double-bit faults detected during initialization
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* 0b1..Double-bit ECC fault was detected during initialization
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*/
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#define FMUTEST_RESET_STATUS_RST_DF_ERR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_RST_DF_ERR_SHIFT)) & FMUTEST_RESET_STATUS_RST_DF_ERR_MASK)
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#define FMUTEST_RESET_STATUS_SOC_TRIM_DF_ERR_MASK (0x3FC00U)
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#define FMUTEST_RESET_STATUS_SOC_TRIM_DF_ERR_SHIFT (10U)
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/*! SOC_TRIM_DF_ERR - ECC Double Fault during load of SoC Trim phrases */
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#define FMUTEST_RESET_STATUS_SOC_TRIM_DF_ERR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_SOC_TRIM_DF_ERR_SHIFT)) & FMUTEST_RESET_STATUS_SOC_TRIM_DF_ERR_MASK)
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#define FMUTEST_RESET_STATUS_RST_PATCH_LD_MASK (0x40000U)
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#define FMUTEST_RESET_STATUS_RST_PATCH_LD_SHIFT (18U)
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/*! RST_PATCH_LD - Reset Patch Required
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* 0b0..No patch required to be loaded during reset
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* 0b1..Patch loaded during reset
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*/
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#define FMUTEST_RESET_STATUS_RST_PATCH_LD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_RST_PATCH_LD_SHIFT)) & FMUTEST_RESET_STATUS_RST_PATCH_LD_MASK)
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#define FMUTEST_RESET_STATUS_RECALL_DATA_MISMATCH_MASK (0x80000U)
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#define FMUTEST_RESET_STATUS_RECALL_DATA_MISMATCH_SHIFT (19U)
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|
/*! RECALL_DATA_MISMATCH - Recall Data Mismatch
|
|
* 0b0..Data read towards end of reset matched data read for Recall
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|
* 0b1..Data read towards end of reset did not match data read for recall
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|
*/
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#define FMUTEST_RESET_STATUS_RECALL_DATA_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_RECALL_DATA_MISMATCH_SHIFT)) & FMUTEST_RESET_STATUS_RECALL_DATA_MISMATCH_MASK)
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/*! @} */
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/*! @name MCTL - FMU Control Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_MCTL_COREHLD_MASK (0x1U)
|
|
#define FMUTEST_MCTL_COREHLD_SHIFT (0U)
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|
/*! COREHLD - Core Hold
|
|
* 0b0..CPU access is allowed
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|
* 0b1..CPU access must be blocked
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|
*/
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|
#define FMUTEST_MCTL_COREHLD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_COREHLD_SHIFT)) & FMUTEST_MCTL_COREHLD_MASK)
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#define FMUTEST_MCTL_LSACT_EN_MASK (0x4U)
|
|
#define FMUTEST_MCTL_LSACT_EN_SHIFT (2U)
|
|
/*! LSACT_EN - LSACTIVE Feature Enable
|
|
* 0b0..LSACTIVE feature disabled completely: FCTRL[LSACTIVE] is forced low and no longer writable, LVE cannot assert at the TSMC array interface.
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|
* 0b1..LSACTIVE feature fully enabled and controllable by SoC and internal UINT SM.
|
|
*/
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|
#define FMUTEST_MCTL_LSACT_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_LSACT_EN_SHIFT)) & FMUTEST_MCTL_LSACT_EN_MASK)
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|
|
|
#define FMUTEST_MCTL_LSACTWREN_MASK (0x8U)
|
|
#define FMUTEST_MCTL_LSACTWREN_SHIFT (3U)
|
|
/*! LSACTWREN - LSACTIVE Write Enable
|
|
* 0b0..Unrestricted write access allowed
|
|
* 0b1..Write access while CMP set must match CMDDID and CMDPRT
|
|
*/
|
|
#define FMUTEST_MCTL_LSACTWREN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_LSACTWREN_SHIFT)) & FMUTEST_MCTL_LSACTWREN_MASK)
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|
|
|
#define FMUTEST_MCTL_MASTER_REPAIR_EN_MASK (0x10U)
|
|
#define FMUTEST_MCTL_MASTER_REPAIR_EN_SHIFT (4U)
|
|
/*! MASTER_REPAIR_EN - Master Repair Enable
|
|
* 0b0..Repair disabled
|
|
* 0b1..Repair enable determined by bit 0 of each REPAIR register
|
|
*/
|
|
#define FMUTEST_MCTL_MASTER_REPAIR_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_MASTER_REPAIR_EN_SHIFT)) & FMUTEST_MCTL_MASTER_REPAIR_EN_MASK)
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|
|
|
#define FMUTEST_MCTL_RFCMDEN_MASK (0x20U)
|
|
#define FMUTEST_MCTL_RFCMDEN_SHIFT (5U)
|
|
/*! RFCMDEN - RF Active Command Enable Control
|
|
* 0b0..Flash commands blocked (CCIF not writable)
|
|
* 0b1..Flash commands allowed
|
|
*/
|
|
#define FMUTEST_MCTL_RFCMDEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_RFCMDEN_SHIFT)) & FMUTEST_MCTL_RFCMDEN_MASK)
|
|
|
|
#define FMUTEST_MCTL_CWSABTEN_MASK (0x40U)
|
|
#define FMUTEST_MCTL_CWSABTEN_SHIFT (6U)
|
|
/*! CWSABTEN - Command Write Sequence Abort Enable
|
|
* 0b0..CWS abort feature is disabled
|
|
* 0b1..CWS abort feature is enabled
|
|
*/
|
|
#define FMUTEST_MCTL_CWSABTEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_CWSABTEN_SHIFT)) & FMUTEST_MCTL_CWSABTEN_MASK)
|
|
|
|
#define FMUTEST_MCTL_MRGRDDIS_MASK (0x80U)
|
|
#define FMUTEST_MCTL_MRGRDDIS_SHIFT (7U)
|
|
/*! MRGRDDIS - Margin Read Disable
|
|
* 0b0..Margin Read Settings are enabled
|
|
* 0b1..Margin Read Settings are disabled
|
|
*/
|
|
#define FMUTEST_MCTL_MRGRDDIS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_MRGRDDIS_SHIFT)) & FMUTEST_MCTL_MRGRDDIS_MASK)
|
|
|
|
#define FMUTEST_MCTL_MRGRD0_MASK (0xF00U)
|
|
#define FMUTEST_MCTL_MRGRD0_SHIFT (8U)
|
|
/*! MRGRD0 - Margin Read Setting for Program */
|
|
#define FMUTEST_MCTL_MRGRD0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_MRGRD0_SHIFT)) & FMUTEST_MCTL_MRGRD0_MASK)
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|
|
|
#define FMUTEST_MCTL_MRGRD1_MASK (0xF000U)
|
|
#define FMUTEST_MCTL_MRGRD1_SHIFT (12U)
|
|
/*! MRGRD1 - Margin Read Setting for Erase */
|
|
#define FMUTEST_MCTL_MRGRD1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_MRGRD1_SHIFT)) & FMUTEST_MCTL_MRGRD1_MASK)
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|
|
|
#define FMUTEST_MCTL_ERSAACK_MASK (0x10000U)
|
|
#define FMUTEST_MCTL_ERSAACK_SHIFT (16U)
|
|
/*! ERSAACK - Mass Erase (Erase All) Acknowledge
|
|
* 0b0..Mass Erase operation is not active (operation has completed or has not started)
|
|
* 0b1..Mass Erase operation is active (controller acknowledges that the soc_ersall_req input is asserted and will continue with the operation)
|
|
*/
|
|
#define FMUTEST_MCTL_ERSAACK(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_ERSAACK_SHIFT)) & FMUTEST_MCTL_ERSAACK_MASK)
|
|
|
|
#define FMUTEST_MCTL_SCAN_OBS_MASK (0x80000U)
|
|
#define FMUTEST_MCTL_SCAN_OBS_SHIFT (19U)
|
|
/*! SCAN_OBS - Scan Observability Control
|
|
* 0b0..Normal functional behavior
|
|
* 0b1..Enables observation of signals that may otherwise be ATPG untestable
|
|
*/
|
|
#define FMUTEST_MCTL_SCAN_OBS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_SCAN_OBS_SHIFT)) & FMUTEST_MCTL_SCAN_OBS_MASK)
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|
|
|
#define FMUTEST_MCTL_BIST_CTL_MASK (0x100000U)
|
|
#define FMUTEST_MCTL_BIST_CTL_SHIFT (20U)
|
|
/*! BIST_CTL - BIST IP Control
|
|
* 0b0..BIST IP disabled
|
|
* 0b1..BIST IP enabled
|
|
*/
|
|
#define FMUTEST_MCTL_BIST_CTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_BIST_CTL_SHIFT)) & FMUTEST_MCTL_BIST_CTL_MASK)
|
|
|
|
#define FMUTEST_MCTL_SMWR_CTL_MASK (0x200000U)
|
|
#define FMUTEST_MCTL_SMWR_CTL_SHIFT (21U)
|
|
/*! SMWR_CTL - SMWR IP Control
|
|
* 0b0..SMWR IP disabled
|
|
* 0b1..SMWR IP enabled
|
|
*/
|
|
#define FMUTEST_MCTL_SMWR_CTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_SMWR_CTL_SHIFT)) & FMUTEST_MCTL_SMWR_CTL_MASK)
|
|
|
|
#define FMUTEST_MCTL_SALV_DIS_MASK (0x1000000U)
|
|
#define FMUTEST_MCTL_SALV_DIS_SHIFT (24U)
|
|
/*! SALV_DIS - Salvage Disable
|
|
* 0b0..Salvage enabled (ECC used during erase verify)
|
|
* 0b1..Salvage disabled (ECC not used during erase verify)
|
|
*/
|
|
#define FMUTEST_MCTL_SALV_DIS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_SALV_DIS_SHIFT)) & FMUTEST_MCTL_SALV_DIS_MASK)
|
|
|
|
#define FMUTEST_MCTL_SOC_ECC_CTL_MASK (0x2000000U)
|
|
#define FMUTEST_MCTL_SOC_ECC_CTL_SHIFT (25U)
|
|
/*! SOC_ECC_CTL - SOC ECC Control
|
|
* 0b0..ECC is enabled for SOC read access
|
|
* 0b1..ECC is disabled for SOC read access
|
|
*/
|
|
#define FMUTEST_MCTL_SOC_ECC_CTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_SOC_ECC_CTL_SHIFT)) & FMUTEST_MCTL_SOC_ECC_CTL_MASK)
|
|
|
|
#define FMUTEST_MCTL_FMU_ECC_CTL_MASK (0x4000000U)
|
|
#define FMUTEST_MCTL_FMU_ECC_CTL_SHIFT (26U)
|
|
/*! FMU_ECC_CTL - FMU ECC Control
|
|
* 0b0..ECC is enabled for FMU program operations
|
|
* 0b1..ECC is disabled for FMU program operations
|
|
*/
|
|
#define FMUTEST_MCTL_FMU_ECC_CTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_FMU_ECC_CTL_SHIFT)) & FMUTEST_MCTL_FMU_ECC_CTL_MASK)
|
|
|
|
#define FMUTEST_MCTL_BIST_PWR_DIS_MASK (0x20000000U)
|
|
#define FMUTEST_MCTL_BIST_PWR_DIS_SHIFT (29U)
|
|
/*! BIST_PWR_DIS - BIST Power Mode Disable
|
|
* 0b0..BIST DFT logic has full control of SLM and LVE when BIST is enabled (including during commands)
|
|
* 0b1..BIST DFT logic has no control of SLM and LVE; power mode RTL is in complete control of SLM and LVE values
|
|
*/
|
|
#define FMUTEST_MCTL_BIST_PWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_BIST_PWR_DIS_SHIFT)) & FMUTEST_MCTL_BIST_PWR_DIS_MASK)
|
|
|
|
#define FMUTEST_MCTL_OSC_H_MASK (0x80000000U)
|
|
#define FMUTEST_MCTL_OSC_H_SHIFT (31U)
|
|
/*! OSC_H - Oscillator control
|
|
* 0b0..Use APB clock
|
|
* 0b1..Use a known fixed-frequency clock, e.g. 12 MHz
|
|
*/
|
|
#define FMUTEST_MCTL_OSC_H(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_OSC_H_SHIFT)) & FMUTEST_MCTL_OSC_H_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name BSEL_GEN - FMU Block Select Generation Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_BSEL_GEN_SBSEL_GEN_MASK (0x3U)
|
|
#define FMUTEST_BSEL_GEN_SBSEL_GEN_SHIFT (0U)
|
|
/*! SBSEL_GEN - Generated SBSEL */
|
|
#define FMUTEST_BSEL_GEN_SBSEL_GEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BSEL_GEN_SBSEL_GEN_SHIFT)) & FMUTEST_BSEL_GEN_SBSEL_GEN_MASK)
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#define FMUTEST_BSEL_GEN_MBSEL_GEN_MASK (0x300U)
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#define FMUTEST_BSEL_GEN_MBSEL_GEN_SHIFT (8U)
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/*! MBSEL_GEN - Generated MBSEL */
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#define FMUTEST_BSEL_GEN_MBSEL_GEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BSEL_GEN_MBSEL_GEN_SHIFT)) & FMUTEST_BSEL_GEN_MBSEL_GEN_MASK)
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/*! @} */
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/*! @name PWR_OPT - Power Mode Options Register */
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/*! @{ */
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#define FMUTEST_PWR_OPT_PD_CDIV_MASK (0xFFU)
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#define FMUTEST_PWR_OPT_PD_CDIV_SHIFT (0U)
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/*! PD_CDIV - Power Down Clock Divider Setting */
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#define FMUTEST_PWR_OPT_PD_CDIV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PWR_OPT_PD_CDIV_SHIFT)) & FMUTEST_PWR_OPT_PD_CDIV_MASK)
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#define FMUTEST_PWR_OPT_SLM_COUNT_MASK (0x3FF0000U)
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#define FMUTEST_PWR_OPT_SLM_COUNT_SHIFT (16U)
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/*! SLM_COUNT - Sleep Recovery Timer Count */
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#define FMUTEST_PWR_OPT_SLM_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PWR_OPT_SLM_COUNT_SHIFT)) & FMUTEST_PWR_OPT_SLM_COUNT_MASK)
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#define FMUTEST_PWR_OPT_PD_TIMER_EN_MASK (0x80000000U)
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#define FMUTEST_PWR_OPT_PD_TIMER_EN_SHIFT (31U)
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/*! PD_TIMER_EN - Power Down BIST Timer Enable
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* 0b0..BIST timer is not triggered during Power Down recovery
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* 0b1..BIST timer is triggered during Power Down recovery (default behavior)
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*/
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#define FMUTEST_PWR_OPT_PD_TIMER_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PWR_OPT_PD_TIMER_EN_SHIFT)) & FMUTEST_PWR_OPT_PD_TIMER_EN_MASK)
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/*! @} */
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/*! @name CMD_CHECK - FMU Command Check Register */
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/*! @{ */
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#define FMUTEST_CMD_CHECK_ALIGNFAIL_PHR_MASK (0x1U)
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#define FMUTEST_CMD_CHECK_ALIGNFAIL_PHR_SHIFT (0U)
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/*! ALIGNFAIL_PHR - Phrase Alignment Fail
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* 0b0..The address is phrase-aligned
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* 0b1..The address is not phrase-aligned
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*/
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#define FMUTEST_CMD_CHECK_ALIGNFAIL_PHR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ALIGNFAIL_PHR_SHIFT)) & FMUTEST_CMD_CHECK_ALIGNFAIL_PHR_MASK)
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#define FMUTEST_CMD_CHECK_ALIGNFAIL_PG_MASK (0x2U)
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#define FMUTEST_CMD_CHECK_ALIGNFAIL_PG_SHIFT (1U)
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/*! ALIGNFAIL_PG - Page Alignment Fail
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* 0b0..The address is page-aligned
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* 0b1..The address is not page-aligned
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*/
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#define FMUTEST_CMD_CHECK_ALIGNFAIL_PG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ALIGNFAIL_PG_SHIFT)) & FMUTEST_CMD_CHECK_ALIGNFAIL_PG_MASK)
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#define FMUTEST_CMD_CHECK_ALIGNFAIL_SCR_MASK (0x4U)
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#define FMUTEST_CMD_CHECK_ALIGNFAIL_SCR_SHIFT (2U)
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/*! ALIGNFAIL_SCR - Sector Alignment Fail
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* 0b0..The address is sector-aligned
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* 0b1..The address is not sector-aligned
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*/
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#define FMUTEST_CMD_CHECK_ALIGNFAIL_SCR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ALIGNFAIL_SCR_SHIFT)) & FMUTEST_CMD_CHECK_ALIGNFAIL_SCR_MASK)
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#define FMUTEST_CMD_CHECK_ALIGNFAIL_BLK_MASK (0x8U)
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#define FMUTEST_CMD_CHECK_ALIGNFAIL_BLK_SHIFT (3U)
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/*! ALIGNFAIL_BLK - Block Alignment Fail
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* 0b0..The address is block-aligned
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* 0b1..The address is not block-aligned
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*/
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#define FMUTEST_CMD_CHECK_ALIGNFAIL_BLK(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ALIGNFAIL_BLK_SHIFT)) & FMUTEST_CMD_CHECK_ALIGNFAIL_BLK_MASK)
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#define FMUTEST_CMD_CHECK_ADDR_FAIL_MASK (0x10U)
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#define FMUTEST_CMD_CHECK_ADDR_FAIL_SHIFT (4U)
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/*! ADDR_FAIL - Address Fail
|
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* 0b0..The address is within the flash or IFR address space
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* 0b1..The address is outside the flash or IFR address space
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*/
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#define FMUTEST_CMD_CHECK_ADDR_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ADDR_FAIL_SHIFT)) & FMUTEST_CMD_CHECK_ADDR_FAIL_MASK)
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#define FMUTEST_CMD_CHECK_IFR_CMD_MASK (0x20U)
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#define FMUTEST_CMD_CHECK_IFR_CMD_SHIFT (5U)
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/*! IFR_CMD - IFR Command
|
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* 0b0..The command operates on a main flash address
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* 0b1..The command operates on an IFR address
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*/
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#define FMUTEST_CMD_CHECK_IFR_CMD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_IFR_CMD_SHIFT)) & FMUTEST_CMD_CHECK_IFR_CMD_MASK)
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#define FMUTEST_CMD_CHECK_ALL_CMD_MASK (0x40U)
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#define FMUTEST_CMD_CHECK_ALL_CMD_SHIFT (6U)
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/*! ALL_CMD - All Blocks Command
|
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* 0b0..The command operates on a single flash block
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* 0b1..The command operates on all flash blocks
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*/
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#define FMUTEST_CMD_CHECK_ALL_CMD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ALL_CMD_SHIFT)) & FMUTEST_CMD_CHECK_ALL_CMD_MASK)
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#define FMUTEST_CMD_CHECK_RANGE_FAIL_MASK (0x80U)
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#define FMUTEST_CMD_CHECK_RANGE_FAIL_SHIFT (7U)
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/*! RANGE_FAIL - Address Range Fail
|
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* 0b0..The address range is valid
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* 0b1..The address range is invalid
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|
*/
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#define FMUTEST_CMD_CHECK_RANGE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_RANGE_FAIL_SHIFT)) & FMUTEST_CMD_CHECK_RANGE_FAIL_MASK)
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#define FMUTEST_CMD_CHECK_SCR_ALIGN_CHK_MASK (0x100U)
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#define FMUTEST_CMD_CHECK_SCR_ALIGN_CHK_SHIFT (8U)
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|
/*! SCR_ALIGN_CHK - Sector Alignment Check
|
|
* 0b0..No sector alignment check
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* 0b1..Sector alignment check
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|
*/
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#define FMUTEST_CMD_CHECK_SCR_ALIGN_CHK(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_SCR_ALIGN_CHK_SHIFT)) & FMUTEST_CMD_CHECK_SCR_ALIGN_CHK_MASK)
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#define FMUTEST_CMD_CHECK_OPTION_FAIL_MASK (0x200U)
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#define FMUTEST_CMD_CHECK_OPTION_FAIL_SHIFT (9U)
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/*! OPTION_FAIL - Option Check Fail
|
|
* 0b0..Option check passes for read command or command is not a read command
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|
* 0b1..Option check fails for read command
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|
*/
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#define FMUTEST_CMD_CHECK_OPTION_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_OPTION_FAIL_SHIFT)) & FMUTEST_CMD_CHECK_OPTION_FAIL_MASK)
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#define FMUTEST_CMD_CHECK_ILLEGAL_CMD_MASK (0x400U)
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|
#define FMUTEST_CMD_CHECK_ILLEGAL_CMD_SHIFT (10U)
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|
/*! ILLEGAL_CMD - Illegal Command
|
|
* 0b0..Command is legal
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|
* 0b1..Command is illegal
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|
*/
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#define FMUTEST_CMD_CHECK_ILLEGAL_CMD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ILLEGAL_CMD_SHIFT)) & FMUTEST_CMD_CHECK_ILLEGAL_CMD_MASK)
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/*! @} */
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/*! @name BSEL - FMU Block Select Register */
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|
/*! @{ */
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|
#define FMUTEST_BSEL_SBSEL_MASK (0x3U)
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#define FMUTEST_BSEL_SBSEL_SHIFT (0U)
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|
/*! SBSEL - Slave Block Select */
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|
#define FMUTEST_BSEL_SBSEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BSEL_SBSEL_SHIFT)) & FMUTEST_BSEL_SBSEL_MASK)
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#define FMUTEST_BSEL_MBSEL_MASK (0x300U)
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#define FMUTEST_BSEL_MBSEL_SHIFT (8U)
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|
/*! MBSEL - Master Block Select */
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|
#define FMUTEST_BSEL_MBSEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BSEL_MBSEL_SHIFT)) & FMUTEST_BSEL_MBSEL_MASK)
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/*! @} */
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|
/*! @name MSIZE - FMU Memory Size Register */
|
|
/*! @{ */
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|
#define FMUTEST_MSIZE_MAXADDR0_MASK (0xFFU)
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|
#define FMUTEST_MSIZE_MAXADDR0_SHIFT (0U)
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|
/*! MAXADDR0 - Size of Flash Block 0 */
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|
#define FMUTEST_MSIZE_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MSIZE_MAXADDR0_SHIFT)) & FMUTEST_MSIZE_MAXADDR0_MASK)
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/*! @} */
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/*! @name FLASH_RD_ADD - Flash Read Address Register */
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|
/*! @{ */
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|
#define FMUTEST_FLASH_RD_ADD_FLASH_RD_ADD_MASK (0xFFFFFFFFU)
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|
#define FMUTEST_FLASH_RD_ADD_FLASH_RD_ADD_SHIFT (0U)
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|
/*! FLASH_RD_ADD - Flash Read Address */
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|
#define FMUTEST_FLASH_RD_ADD_FLASH_RD_ADD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FLASH_RD_ADD_FLASH_RD_ADD_SHIFT)) & FMUTEST_FLASH_RD_ADD_FLASH_RD_ADD_MASK)
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/*! @} */
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/*! @name FLASH_STOP_ADD - Flash Stop Address Register */
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|
/*! @{ */
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|
#define FMUTEST_FLASH_STOP_ADD_FLASH_STOP_ADD_MASK (0xFFFFFFFFU)
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|
#define FMUTEST_FLASH_STOP_ADD_FLASH_STOP_ADD_SHIFT (0U)
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|
/*! FLASH_STOP_ADD - Flash Stop Address */
|
|
#define FMUTEST_FLASH_STOP_ADD_FLASH_STOP_ADD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FLASH_STOP_ADD_FLASH_STOP_ADD_SHIFT)) & FMUTEST_FLASH_STOP_ADD_FLASH_STOP_ADD_MASK)
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/*! @} */
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/*! @name FLASH_RD_CTRL - Flash Read Control Register */
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|
/*! @{ */
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|
#define FMUTEST_FLASH_RD_CTRL_FLASH_RD_MASK (0x1U)
|
|
#define FMUTEST_FLASH_RD_CTRL_FLASH_RD_SHIFT (0U)
|
|
/*! FLASH_RD - Flash Read Enable
|
|
* 0b0..Manual flash read not enabled.(default)
|
|
* 0b1..Manual flash read enabled
|
|
*/
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|
#define FMUTEST_FLASH_RD_CTRL_FLASH_RD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FLASH_RD_CTRL_FLASH_RD_SHIFT)) & FMUTEST_FLASH_RD_CTRL_FLASH_RD_MASK)
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|
#define FMUTEST_FLASH_RD_CTRL_WIDE_LOAD_MASK (0x2U)
|
|
#define FMUTEST_FLASH_RD_CTRL_WIDE_LOAD_SHIFT (1U)
|
|
/*! WIDE_LOAD - Wide Load Enable
|
|
* 0b0..Wide load mode disabled (default)
|
|
* 0b1..Wide load mode enabled
|
|
*/
|
|
#define FMUTEST_FLASH_RD_CTRL_WIDE_LOAD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FLASH_RD_CTRL_WIDE_LOAD_SHIFT)) & FMUTEST_FLASH_RD_CTRL_WIDE_LOAD_MASK)
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|
#define FMUTEST_FLASH_RD_CTRL_SINGLE_RD_MASK (0x4U)
|
|
#define FMUTEST_FLASH_RD_CTRL_SINGLE_RD_SHIFT (2U)
|
|
/*! SINGLE_RD - Single Flash Read
|
|
* 0b0..Normal UINT operation
|
|
* 0b1..UINT configured for single cycle reads
|
|
*/
|
|
#define FMUTEST_FLASH_RD_CTRL_SINGLE_RD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FLASH_RD_CTRL_SINGLE_RD_SHIFT)) & FMUTEST_FLASH_RD_CTRL_SINGLE_RD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MM_ADDR - Memory Map Address Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_MM_ADDR_MM_ADDR_MASK (0xFFFFFFFFU)
|
|
#define FMUTEST_MM_ADDR_MM_ADDR_SHIFT (0U)
|
|
/*! MM_ADDR - Memory Map Address */
|
|
#define FMUTEST_MM_ADDR_MM_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_ADDR_MM_ADDR_SHIFT)) & FMUTEST_MM_ADDR_MM_ADDR_MASK)
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|
/*! @} */
|
|
|
|
/*! @name MM_WDATA - Memory Map Write Data Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_MM_WDATA_MM_WDATA_MASK (0xFFFFFFFFU)
|
|
#define FMUTEST_MM_WDATA_MM_WDATA_SHIFT (0U)
|
|
/*! MM_WDATA - Memory Map Write Data */
|
|
#define FMUTEST_MM_WDATA_MM_WDATA(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_WDATA_MM_WDATA_SHIFT)) & FMUTEST_MM_WDATA_MM_WDATA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MM_CTL - Memory Map Control Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_MM_CTL_MM_SEL_MASK (0x1U)
|
|
#define FMUTEST_MM_CTL_MM_SEL_SHIFT (0U)
|
|
/*! MM_SEL - Register Access Enable */
|
|
#define FMUTEST_MM_CTL_MM_SEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_CTL_MM_SEL_SHIFT)) & FMUTEST_MM_CTL_MM_SEL_MASK)
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|
|
|
#define FMUTEST_MM_CTL_MM_RD_MASK (0x2U)
|
|
#define FMUTEST_MM_CTL_MM_RD_SHIFT (1U)
|
|
/*! MM_RD - Register R/W Control
|
|
* 0b0..Write to register
|
|
* 0b1..Read register
|
|
*/
|
|
#define FMUTEST_MM_CTL_MM_RD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_CTL_MM_RD_SHIFT)) & FMUTEST_MM_CTL_MM_RD_MASK)
|
|
|
|
#define FMUTEST_MM_CTL_BIST_ON_MASK (0x4U)
|
|
#define FMUTEST_MM_CTL_BIST_ON_SHIFT (2U)
|
|
/*! BIST_ON - BIST on
|
|
* 0b0..BIST enable not forced by user interface
|
|
* 0b1..BIST enable control by user interface
|
|
*/
|
|
#define FMUTEST_MM_CTL_BIST_ON(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_CTL_BIST_ON_SHIFT)) & FMUTEST_MM_CTL_BIST_ON_MASK)
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|
|
|
#define FMUTEST_MM_CTL_FORCE_SW_CLK_MASK (0x8U)
|
|
#define FMUTEST_MM_CTL_FORCE_SW_CLK_SHIFT (3U)
|
|
/*! FORCE_SW_CLK - Force Switch Clock
|
|
* 0b0..Switch clock not forced on (gated normally)
|
|
* 0b1..Switch clock forced on
|
|
*/
|
|
#define FMUTEST_MM_CTL_FORCE_SW_CLK(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_CTL_FORCE_SW_CLK_SHIFT)) & FMUTEST_MM_CTL_FORCE_SW_CLK_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name UINT_CTL - User Interface Control Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_UINT_CTL_SET_FAIL_MASK (0x1U)
|
|
#define FMUTEST_UINT_CTL_SET_FAIL_SHIFT (0U)
|
|
/*! SET_FAIL - Set Fail On Exit
|
|
* 0b0..FAIL flag should not be set on command exit (no failure detected)
|
|
* 0b1..FAIL flag should be set on command exit
|
|
*/
|
|
#define FMUTEST_UINT_CTL_SET_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_UINT_CTL_SET_FAIL_SHIFT)) & FMUTEST_UINT_CTL_SET_FAIL_MASK)
|
|
|
|
#define FMUTEST_UINT_CTL_DBERR_MASK (0x2U)
|
|
#define FMUTEST_UINT_CTL_DBERR_SHIFT (1U)
|
|
/*! DBERR - Double-Bit ECC Fault Detect
|
|
* 0b0..No double-bit fault detected during UINT-driven read sequence
|
|
* 0b1..Double-bit fault detected during UINT-driven read sequence
|
|
*/
|
|
#define FMUTEST_UINT_CTL_DBERR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_UINT_CTL_DBERR_SHIFT)) & FMUTEST_UINT_CTL_DBERR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RD_DATA0 - Read Data 0 Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_RD_DATA0_RD_DATA0_MASK (0xFFFFFFFFU)
|
|
#define FMUTEST_RD_DATA0_RD_DATA0_SHIFT (0U)
|
|
/*! RD_DATA0 - Read Data 0 */
|
|
#define FMUTEST_RD_DATA0_RD_DATA0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_DATA0_RD_DATA0_SHIFT)) & FMUTEST_RD_DATA0_RD_DATA0_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RD_DATA1 - Read Data 1 Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_RD_DATA1_RD_DATA1_MASK (0xFFFFFFFFU)
|
|
#define FMUTEST_RD_DATA1_RD_DATA1_SHIFT (0U)
|
|
/*! RD_DATA1 - Read Data 1 */
|
|
#define FMUTEST_RD_DATA1_RD_DATA1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_DATA1_RD_DATA1_SHIFT)) & FMUTEST_RD_DATA1_RD_DATA1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RD_DATA2 - Read Data 2 Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_RD_DATA2_RD_DATA2_MASK (0xFFFFFFFFU)
|
|
#define FMUTEST_RD_DATA2_RD_DATA2_SHIFT (0U)
|
|
/*! RD_DATA2 - Read Data 2 */
|
|
#define FMUTEST_RD_DATA2_RD_DATA2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_DATA2_RD_DATA2_SHIFT)) & FMUTEST_RD_DATA2_RD_DATA2_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RD_DATA3 - Read Data 3 Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_RD_DATA3_RD_DATA3_MASK (0xFFFFFFFFU)
|
|
#define FMUTEST_RD_DATA3_RD_DATA3_SHIFT (0U)
|
|
/*! RD_DATA3 - Read Data 3 */
|
|
#define FMUTEST_RD_DATA3_RD_DATA3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_DATA3_RD_DATA3_SHIFT)) & FMUTEST_RD_DATA3_RD_DATA3_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PARITY - Parity Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_PARITY_PARITY_MASK (0x1FFU)
|
|
#define FMUTEST_PARITY_PARITY_SHIFT (0U)
|
|
/*! PARITY - Read data [136:128] */
|
|
#define FMUTEST_PARITY_PARITY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PARITY_PARITY_SHIFT)) & FMUTEST_PARITY_PARITY_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RD_PATH_CTRL_STATUS - Read Path Control and Status Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_RD_PATH_CTRL_STATUS_RD_CAPT_MASK (0xFFU)
|
|
#define FMUTEST_RD_PATH_CTRL_STATUS_RD_CAPT_SHIFT (0U)
|
|
/*! RD_CAPT - Read Capture Clock Periods */
|
|
#define FMUTEST_RD_PATH_CTRL_STATUS_RD_CAPT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_RD_CAPT_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_RD_CAPT_MASK)
|
|
|
|
#define FMUTEST_RD_PATH_CTRL_STATUS_SE_SIZE_MASK (0xFF00U)
|
|
#define FMUTEST_RD_PATH_CTRL_STATUS_SE_SIZE_SHIFT (8U)
|
|
/*! SE_SIZE - SE Clock Periods */
|
|
#define FMUTEST_RD_PATH_CTRL_STATUS_SE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_SE_SIZE_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_SE_SIZE_MASK)
|
|
|
|
#define FMUTEST_RD_PATH_CTRL_STATUS_ECC_ENABLEB_MASK (0x10000U)
|
|
#define FMUTEST_RD_PATH_CTRL_STATUS_ECC_ENABLEB_SHIFT (16U)
|
|
/*! ECC_ENABLEB - ECC Decoder Control
|
|
* 0b0..ECC decoder enabled (default)
|
|
* 0b1..ECC decoder disabled
|
|
*/
|
|
#define FMUTEST_RD_PATH_CTRL_STATUS_ECC_ENABLEB(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_ECC_ENABLEB_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_ECC_ENABLEB_MASK)
|
|
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#define FMUTEST_RD_PATH_CTRL_STATUS_MISR_EN_MASK (0x20000U)
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#define FMUTEST_RD_PATH_CTRL_STATUS_MISR_EN_SHIFT (17U)
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/*! MISR_EN - MISR Enable
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* 0b0..MISR option disabled (default)
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* 0b1..MISR option enabled
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*/
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#define FMUTEST_RD_PATH_CTRL_STATUS_MISR_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_MISR_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_MISR_EN_MASK)
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#define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PAR_EN_MASK (0x40000U)
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#define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PAR_EN_SHIFT (18U)
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/*! CPY_PAR_EN - Copy Parity Enable
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* 0b0..Copy parity disabled
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* 0b1..Copy parity enabled
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*/
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#define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PAR_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_CPY_PAR_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_CPY_PAR_EN_MASK)
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#define FMUTEST_RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW_MASK (0x80000U)
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#define FMUTEST_RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW_SHIFT (19U)
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/*! BIST_MUX_TO_SMW - BIST Mux to SMW
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* 0b0..BIST drives fields
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* 0b1..SMW registers drive fields
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*/
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#define FMUTEST_RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW_MASK)
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#define FMUTEST_RD_PATH_CTRL_STATUS_AD_SET_MASK (0xF00000U)
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#define FMUTEST_RD_PATH_CTRL_STATUS_AD_SET_SHIFT (20U)
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/*! AD_SET - Multi-Cycle Address Setup Time */
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#define FMUTEST_RD_PATH_CTRL_STATUS_AD_SET(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_AD_SET_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_AD_SET_MASK)
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#define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_EN_MASK (0x1000000U)
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#define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_EN_SHIFT (24U)
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/*! WR_PATH_EN - Write Path Enable
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* 0b0..Writes to BIST setting registers driven by MM_WDATA
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* 0b1..Writes to BIST setting registers driven by SMW_DIN
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*/
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#define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_EN_MASK)
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#define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN_MASK (0x2000000U)
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#define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN_SHIFT (25U)
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/*! WR_PATH_ECC_EN - Write Path ECC Enable
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* 0b0..ECC encoding disabled
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* 0b1..ECC encoding enabled
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*/
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#define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN_MASK)
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#define FMUTEST_RD_PATH_CTRL_STATUS_DBERR_REG_MASK (0x4000000U)
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#define FMUTEST_RD_PATH_CTRL_STATUS_DBERR_REG_SHIFT (26U)
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/*! DBERR_REG - Double-Bit Error
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* 0b0..Double-bit fault not detected
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* 0b1..Double-bit fault detected on previous UINT flash read
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*/
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#define FMUTEST_RD_PATH_CTRL_STATUS_DBERR_REG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_DBERR_REG_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_DBERR_REG_MASK)
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#define FMUTEST_RD_PATH_CTRL_STATUS_SBERR_REG_MASK (0x8000000U)
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#define FMUTEST_RD_PATH_CTRL_STATUS_SBERR_REG_SHIFT (27U)
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/*! SBERR_REG - Single-Bit Error
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* 0b0..Single-bit fault not detected
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* 0b1..Single-bit fault detected on previous UINT flash read
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*/
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#define FMUTEST_RD_PATH_CTRL_STATUS_SBERR_REG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_SBERR_REG_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_SBERR_REG_MASK)
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#define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PHRASE_EN_MASK (0x10000000U)
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#define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PHRASE_EN_SHIFT (28U)
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/*! CPY_PHRASE_EN - Copy Phrase Enable
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* 0b0..Copy Flash read data disabled
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* 0b1..Copy Flash read data enabled
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*/
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#define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PHRASE_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_CPY_PHRASE_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_CPY_PHRASE_EN_MASK)
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#define FMUTEST_RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL_MASK (0x20000000U)
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#define FMUTEST_RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL_SHIFT (29U)
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/*! SMW_ARRAY1_SMW0_SEL - SMW_ARRAY1_SMW0_SEL
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* 0b0..Select block 0
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* 0b1..Select block 1
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*/
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#define FMUTEST_RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL_MASK)
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#define FMUTEST_RD_PATH_CTRL_STATUS_BIST_ECC_EN_MASK (0x40000000U)
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#define FMUTEST_RD_PATH_CTRL_STATUS_BIST_ECC_EN_SHIFT (30U)
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/*! BIST_ECC_EN - BIST ECC Enable
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* 0b0..ECC correction disabled
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* 0b1..ECC correction enabled
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*/
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#define FMUTEST_RD_PATH_CTRL_STATUS_BIST_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_BIST_ECC_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_BIST_ECC_EN_MASK)
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#define FMUTEST_RD_PATH_CTRL_STATUS_LAST_READ_MASK (0x80000000U)
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#define FMUTEST_RD_PATH_CTRL_STATUS_LAST_READ_SHIFT (31U)
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/*! LAST_READ - Last Read
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* 0b0..Latest read not last in multi-address operation
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* 0b1..Latest read last in multi-address operation
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*/
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#define FMUTEST_RD_PATH_CTRL_STATUS_LAST_READ(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_LAST_READ_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_LAST_READ_MASK)
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/*! @} */
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/*! @name SMW_DIN0 - SMW DIN 0 Register */
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/*! @{ */
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#define FMUTEST_SMW_DIN0_SMW_DIN0_MASK (0xFFFFFFFFU)
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#define FMUTEST_SMW_DIN0_SMW_DIN0_SHIFT (0U)
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/*! SMW_DIN0 - SMW DIN 0 */
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#define FMUTEST_SMW_DIN0_SMW_DIN0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_DIN0_SMW_DIN0_SHIFT)) & FMUTEST_SMW_DIN0_SMW_DIN0_MASK)
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/*! @} */
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/*! @name SMW_DIN1 - SMW DIN 1 Register */
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/*! @{ */
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#define FMUTEST_SMW_DIN1_SMW_DIN1_MASK (0xFFFFFFFFU)
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#define FMUTEST_SMW_DIN1_SMW_DIN1_SHIFT (0U)
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/*! SMW_DIN1 - SMW DIN 1 */
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#define FMUTEST_SMW_DIN1_SMW_DIN1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_DIN1_SMW_DIN1_SHIFT)) & FMUTEST_SMW_DIN1_SMW_DIN1_MASK)
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/*! @} */
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/*! @name SMW_DIN2 - SMW DIN 2 Register */
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/*! @{ */
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#define FMUTEST_SMW_DIN2_SMW_DIN2_MASK (0xFFFFFFFFU)
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#define FMUTEST_SMW_DIN2_SMW_DIN2_SHIFT (0U)
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/*! SMW_DIN2 - SMW DIN 2 */
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#define FMUTEST_SMW_DIN2_SMW_DIN2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_DIN2_SMW_DIN2_SHIFT)) & FMUTEST_SMW_DIN2_SMW_DIN2_MASK)
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/*! @} */
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/*! @name SMW_DIN3 - SMW DIN 3 Register */
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/*! @{ */
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#define FMUTEST_SMW_DIN3_SMW_DIN3_MASK (0xFFFFFFFFU)
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#define FMUTEST_SMW_DIN3_SMW_DIN3_SHIFT (0U)
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/*! SMW_DIN3 - SMW DIN 3 */
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#define FMUTEST_SMW_DIN3_SMW_DIN3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_DIN3_SMW_DIN3_SHIFT)) & FMUTEST_SMW_DIN3_SMW_DIN3_MASK)
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/*! @} */
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/*! @name SMW_ADDR - SMW Address Register */
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/*! @{ */
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#define FMUTEST_SMW_ADDR_SMW_ADDR_MASK (0xFFFFFFFFU)
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#define FMUTEST_SMW_ADDR_SMW_ADDR_SHIFT (0U)
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/*! SMW_ADDR - SMW Address */
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#define FMUTEST_SMW_ADDR_SMW_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_ADDR_SMW_ADDR_SHIFT)) & FMUTEST_SMW_ADDR_SMW_ADDR_MASK)
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/*! @} */
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/*! @name SMW_CMD_WAIT - SMW Command and Wait Register */
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/*! @{ */
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#define FMUTEST_SMW_CMD_WAIT_CMD_MASK (0x7U)
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#define FMUTEST_SMW_CMD_WAIT_CMD_SHIFT (0U)
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/*! CMD - SMW Command
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* 0b000..IDLE
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|
* 0b001..ABORT
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|
* 0b010..SME2 to one-shot mass erase
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|
* 0b011..SME3 to sector erase on selected array
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|
* 0b100..SMP1 to program phrase or page on selected array with shot disabled on previously programmed bit
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|
* 0b101..Reserved for SME4 (multi-sector erase)
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|
* 0b110..SMP2 to program phrase or page on selected array to repair cells of weak program after power loss
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* 0b111..Reserved
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*/
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#define FMUTEST_SMW_CMD_WAIT_CMD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_CMD_WAIT_CMD_SHIFT)) & FMUTEST_SMW_CMD_WAIT_CMD_MASK)
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#define FMUTEST_SMW_CMD_WAIT_WAIT_EN_MASK (0x8U)
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#define FMUTEST_SMW_CMD_WAIT_WAIT_EN_SHIFT (3U)
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/*! WAIT_EN - SMW Wait Enable
|
|
* 0b0..Wait feature disabled
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|
* 0b1..Wait feature enabled
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*/
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#define FMUTEST_SMW_CMD_WAIT_WAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_CMD_WAIT_WAIT_EN_SHIFT)) & FMUTEST_SMW_CMD_WAIT_WAIT_EN_MASK)
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#define FMUTEST_SMW_CMD_WAIT_WAIT_AUTO_SET_MASK (0x10U)
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#define FMUTEST_SMW_CMD_WAIT_WAIT_AUTO_SET_SHIFT (4U)
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/*! WAIT_AUTO_SET - SMW Wait Auto Set */
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#define FMUTEST_SMW_CMD_WAIT_WAIT_AUTO_SET(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_CMD_WAIT_WAIT_AUTO_SET_SHIFT)) & FMUTEST_SMW_CMD_WAIT_WAIT_AUTO_SET_MASK)
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/*! @} */
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/*! @name SMW_STATUS - SMW Status Register */
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/*! @{ */
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#define FMUTEST_SMW_STATUS_SMW_ERR_MASK (0x1U)
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#define FMUTEST_SMW_STATUS_SMW_ERR_SHIFT (0U)
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/*! SMW_ERR - SMW Error
|
|
* 0b0..Error not detected
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|
* 0b1..Error detected
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|
*/
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#define FMUTEST_SMW_STATUS_SMW_ERR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_STATUS_SMW_ERR_SHIFT)) & FMUTEST_SMW_STATUS_SMW_ERR_MASK)
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#define FMUTEST_SMW_STATUS_SMW_BUSY_MASK (0x2U)
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#define FMUTEST_SMW_STATUS_SMW_BUSY_SHIFT (1U)
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/*! SMW_BUSY - SMW Busy
|
|
* 0b0..SMW command not active
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|
* 0b1..SMW command is active
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|
*/
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#define FMUTEST_SMW_STATUS_SMW_BUSY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_STATUS_SMW_BUSY_SHIFT)) & FMUTEST_SMW_STATUS_SMW_BUSY_MASK)
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#define FMUTEST_SMW_STATUS_BIST_BUSY_MASK (0x4U)
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#define FMUTEST_SMW_STATUS_BIST_BUSY_SHIFT (2U)
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/*! BIST_BUSY - BIST Busy
|
|
* 0b0..BIST Command not active
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|
* 0b1..BIST Command is active
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|
*/
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#define FMUTEST_SMW_STATUS_BIST_BUSY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_STATUS_BIST_BUSY_SHIFT)) & FMUTEST_SMW_STATUS_BIST_BUSY_MASK)
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/*! @} */
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/*! @name SOCTRIM0_0 - SoC Trim Phrase 0 Word 0 Register */
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|
/*! @{ */
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#define FMUTEST_SOCTRIM0_0_TRIM0_0_MASK (0xFFFFFFFFU)
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#define FMUTEST_SOCTRIM0_0_TRIM0_0_SHIFT (0U)
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/*! TRIM0_0 - TRIM0_0 */
|
|
#define FMUTEST_SOCTRIM0_0_TRIM0_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM0_0_TRIM0_0_SHIFT)) & FMUTEST_SOCTRIM0_0_TRIM0_0_MASK)
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/*! @} */
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/*! @name SOCTRIM0_1 - SoC Trim Phrase 0 Word 1 Register */
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|
/*! @{ */
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#define FMUTEST_SOCTRIM0_1_TRIM0_1_MASK (0xFFFFFFFFU)
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#define FMUTEST_SOCTRIM0_1_TRIM0_1_SHIFT (0U)
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/*! TRIM0_1 - TRIM0_1 */
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|
#define FMUTEST_SOCTRIM0_1_TRIM0_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM0_1_TRIM0_1_SHIFT)) & FMUTEST_SOCTRIM0_1_TRIM0_1_MASK)
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/*! @} */
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/*! @name SOCTRIM0_2 - SoC Trim Phrase 0 Word 2 Register */
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|
/*! @{ */
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#define FMUTEST_SOCTRIM0_2_TRIM0_2_MASK (0xFFFFFFFFU)
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#define FMUTEST_SOCTRIM0_2_TRIM0_2_SHIFT (0U)
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/*! TRIM0_2 - TRIM0_2 */
|
|
#define FMUTEST_SOCTRIM0_2_TRIM0_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM0_2_TRIM0_2_SHIFT)) & FMUTEST_SOCTRIM0_2_TRIM0_2_MASK)
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/*! @} */
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/*! @name SOCTRIM0_3 - SoC Trim Phrase 0 Word 3 Register */
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|
/*! @{ */
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#define FMUTEST_SOCTRIM0_3_TRIM0_3_MASK (0xFFFFFFFFU)
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#define FMUTEST_SOCTRIM0_3_TRIM0_3_SHIFT (0U)
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/*! TRIM0_3 - TRIM0_3 */
|
|
#define FMUTEST_SOCTRIM0_3_TRIM0_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM0_3_TRIM0_3_SHIFT)) & FMUTEST_SOCTRIM0_3_TRIM0_3_MASK)
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/*! @} */
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/*! @name SOCTRIM1_0 - SoC Trim Phrase 1 Word 0 Register */
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|
/*! @{ */
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#define FMUTEST_SOCTRIM1_0_TRIM1_0_MASK (0xFFFFFFFFU)
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|
#define FMUTEST_SOCTRIM1_0_TRIM1_0_SHIFT (0U)
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/*! TRIM1_0 - TRIM1_0 */
|
|
#define FMUTEST_SOCTRIM1_0_TRIM1_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM1_0_TRIM1_0_SHIFT)) & FMUTEST_SOCTRIM1_0_TRIM1_0_MASK)
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|
/*! @} */
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/*! @name SOCTRIM1_1 - SoC Trim Phrase 1 Word 1 Register */
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/*! @{ */
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#define FMUTEST_SOCTRIM1_1_TRIM1_1_MASK (0xFFFFFFFFU)
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|
#define FMUTEST_SOCTRIM1_1_TRIM1_1_SHIFT (0U)
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|
/*! TRIM1_1 - TRIM1_1 */
|
|
#define FMUTEST_SOCTRIM1_1_TRIM1_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM1_1_TRIM1_1_SHIFT)) & FMUTEST_SOCTRIM1_1_TRIM1_1_MASK)
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|
/*! @} */
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/*! @name SOCTRIM1_2 - SoC Trim Phrase 1 Word 2 Register */
|
|
/*! @{ */
|
|
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|
#define FMUTEST_SOCTRIM1_2_TRIM1_2_MASK (0xFFFFFFFFU)
|
|
#define FMUTEST_SOCTRIM1_2_TRIM1_2_SHIFT (0U)
|
|
/*! TRIM1_2 - TRIM1_2 */
|
|
#define FMUTEST_SOCTRIM1_2_TRIM1_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM1_2_TRIM1_2_SHIFT)) & FMUTEST_SOCTRIM1_2_TRIM1_2_MASK)
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|
/*! @} */
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|
/*! @name SOCTRIM1_3 - SoC Trim Phrase 1 Word 3 Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_SOCTRIM1_3_TRIM1_3_MASK (0xFFFFFFFFU)
|
|
#define FMUTEST_SOCTRIM1_3_TRIM1_3_SHIFT (0U)
|
|
/*! TRIM1_3 - TRIM1_3 */
|
|
#define FMUTEST_SOCTRIM1_3_TRIM1_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM1_3_TRIM1_3_SHIFT)) & FMUTEST_SOCTRIM1_3_TRIM1_3_MASK)
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|
/*! @} */
|
|
|
|
/*! @name SOCTRIM2_0 - SoC Trim Phrase 2 Word 0 Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_SOCTRIM2_0_TRIM2_0_MASK (0xFFFFFFFFU)
|
|
#define FMUTEST_SOCTRIM2_0_TRIM2_0_SHIFT (0U)
|
|
/*! TRIM2_0 - TRIM2_0 */
|
|
#define FMUTEST_SOCTRIM2_0_TRIM2_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM2_0_TRIM2_0_SHIFT)) & FMUTEST_SOCTRIM2_0_TRIM2_0_MASK)
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|
/*! @} */
|
|
|
|
/*! @name SOCTRIM2_1 - SoC Trim Phrase 2 Word 1 Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_SOCTRIM2_1_TRIM2_1_MASK (0xFFFFFFFFU)
|
|
#define FMUTEST_SOCTRIM2_1_TRIM2_1_SHIFT (0U)
|
|
/*! TRIM2_1 - TRIM2_1 */
|
|
#define FMUTEST_SOCTRIM2_1_TRIM2_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM2_1_TRIM2_1_SHIFT)) & FMUTEST_SOCTRIM2_1_TRIM2_1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SOCTRIM2_2 - SoC Trim Phrase 2 Word 2 Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_SOCTRIM2_2_TRIM2_2_MASK (0xFFFFFFFFU)
|
|
#define FMUTEST_SOCTRIM2_2_TRIM2_2_SHIFT (0U)
|
|
/*! TRIM2_2 - TRIM2_2 */
|
|
#define FMUTEST_SOCTRIM2_2_TRIM2_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM2_2_TRIM2_2_SHIFT)) & FMUTEST_SOCTRIM2_2_TRIM2_2_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SOCTRIM2_3 - SoC Trim Phrase 2 Word 3 Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_SOCTRIM2_3_TRIM2_3_MASK (0xFFFFFFFFU)
|
|
#define FMUTEST_SOCTRIM2_3_TRIM2_3_SHIFT (0U)
|
|
/*! TRIM2_3 - TRIM2_3 */
|
|
#define FMUTEST_SOCTRIM2_3_TRIM2_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM2_3_TRIM2_3_SHIFT)) & FMUTEST_SOCTRIM2_3_TRIM2_3_MASK)
|
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/*! @} */
|
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/*! @name SOCTRIM3_0 - SoC Trim Phrase 3 Word 0 Register */
|
|
/*! @{ */
|
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#define FMUTEST_SOCTRIM3_0_TRIM3_0_MASK (0xFFFFFFFFU)
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#define FMUTEST_SOCTRIM3_0_TRIM3_0_SHIFT (0U)
|
|
/*! TRIM3_0 - TRIM3_0 */
|
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#define FMUTEST_SOCTRIM3_0_TRIM3_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM3_0_TRIM3_0_SHIFT)) & FMUTEST_SOCTRIM3_0_TRIM3_0_MASK)
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/*! @} */
|
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/*! @name SOCTRIM3_1 - SoC Trim Phrase 3 Word 1 Register */
|
|
/*! @{ */
|
|
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#define FMUTEST_SOCTRIM3_1_TRIM3_1_MASK (0xFFFFFFFFU)
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#define FMUTEST_SOCTRIM3_1_TRIM3_1_SHIFT (0U)
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/*! TRIM3_1 - TRIM3_1 */
|
|
#define FMUTEST_SOCTRIM3_1_TRIM3_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM3_1_TRIM3_1_SHIFT)) & FMUTEST_SOCTRIM3_1_TRIM3_1_MASK)
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/*! @} */
|
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/*! @name SOCTRIM3_2 - SoC Trim Phrase 3 Word 2 Register */
|
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/*! @{ */
|
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#define FMUTEST_SOCTRIM3_2_TRIM3_2_MASK (0xFFFFFFFFU)
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#define FMUTEST_SOCTRIM3_2_TRIM3_2_SHIFT (0U)
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/*! TRIM3_2 - TRIM3_2 */
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#define FMUTEST_SOCTRIM3_2_TRIM3_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM3_2_TRIM3_2_SHIFT)) & FMUTEST_SOCTRIM3_2_TRIM3_2_MASK)
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/*! @} */
|
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/*! @name SOCTRIM3_3 - SoC Trim Phrase 3 Word 3 Register */
|
|
/*! @{ */
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|
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#define FMUTEST_SOCTRIM3_3_TRIM3_3_MASK (0xFFFFFFFFU)
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#define FMUTEST_SOCTRIM3_3_TRIM3_3_SHIFT (0U)
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/*! TRIM3_3 - TRIM3_3 */
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#define FMUTEST_SOCTRIM3_3_TRIM3_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM3_3_TRIM3_3_SHIFT)) & FMUTEST_SOCTRIM3_3_TRIM3_3_MASK)
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/*! @} */
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/*! @name SOCTRIM4_0 - SoC Trim Phrase 4 Word 0 Register */
|
|
/*! @{ */
|
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#define FMUTEST_SOCTRIM4_0_TRIM4_0_MASK (0xFFFFFFFFU)
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#define FMUTEST_SOCTRIM4_0_TRIM4_0_SHIFT (0U)
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/*! TRIM4_0 - TRIM4_0 */
|
|
#define FMUTEST_SOCTRIM4_0_TRIM4_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM4_0_TRIM4_0_SHIFT)) & FMUTEST_SOCTRIM4_0_TRIM4_0_MASK)
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/*! @} */
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/*! @name SOCTRIM4_1 - SoC Trim Phrase 4 Word 1 Register */
|
|
/*! @{ */
|
|
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#define FMUTEST_SOCTRIM4_1_TRIM4_1_MASK (0xFFFFFFFFU)
|
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#define FMUTEST_SOCTRIM4_1_TRIM4_1_SHIFT (0U)
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|
/*! TRIM4_1 - TRIM4_1 */
|
|
#define FMUTEST_SOCTRIM4_1_TRIM4_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM4_1_TRIM4_1_SHIFT)) & FMUTEST_SOCTRIM4_1_TRIM4_1_MASK)
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|
/*! @} */
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/*! @name SOCTRIM4_2 - SoC Trim Phrase 4 Word 2 Register */
|
|
/*! @{ */
|
|
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|
#define FMUTEST_SOCTRIM4_2_TRIM4_2_MASK (0xFFFFFFFFU)
|
|
#define FMUTEST_SOCTRIM4_2_TRIM4_2_SHIFT (0U)
|
|
/*! TRIM4_2 - TRIM4_2 */
|
|
#define FMUTEST_SOCTRIM4_2_TRIM4_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM4_2_TRIM4_2_SHIFT)) & FMUTEST_SOCTRIM4_2_TRIM4_2_MASK)
|
|
/*! @} */
|
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/*! @name SOCTRIM4_3 - SoC Trim Phrase 4 Word 3 Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_SOCTRIM4_3_TRIM4_3_MASK (0xFFFFFFFFU)
|
|
#define FMUTEST_SOCTRIM4_3_TRIM4_3_SHIFT (0U)
|
|
/*! TRIM4_3 - TRIM4_3 */
|
|
#define FMUTEST_SOCTRIM4_3_TRIM4_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM4_3_TRIM4_3_SHIFT)) & FMUTEST_SOCTRIM4_3_TRIM4_3_MASK)
|
|
/*! @} */
|
|
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/*! @name SOCTRIM5_0 - SoC Trim Phrase 5 Word 0 Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_SOCTRIM5_0_TRIM5_0_MASK (0xFFFFFFFFU)
|
|
#define FMUTEST_SOCTRIM5_0_TRIM5_0_SHIFT (0U)
|
|
/*! TRIM5_0 - TRIM5_0 */
|
|
#define FMUTEST_SOCTRIM5_0_TRIM5_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM5_0_TRIM5_0_SHIFT)) & FMUTEST_SOCTRIM5_0_TRIM5_0_MASK)
|
|
/*! @} */
|
|
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/*! @name SOCTRIM5_1 - SoC Trim Phrase 5 Word 1 Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_SOCTRIM5_1_TRIM5_1_MASK (0xFFFFFFFFU)
|
|
#define FMUTEST_SOCTRIM5_1_TRIM5_1_SHIFT (0U)
|
|
/*! TRIM5_1 - TRIM5_1 */
|
|
#define FMUTEST_SOCTRIM5_1_TRIM5_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM5_1_TRIM5_1_SHIFT)) & FMUTEST_SOCTRIM5_1_TRIM5_1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SOCTRIM5_2 - SoC Trim Phrase 5 Word 2 Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_SOCTRIM5_2_TRIM5_2_MASK (0xFFFFFFFFU)
|
|
#define FMUTEST_SOCTRIM5_2_TRIM5_2_SHIFT (0U)
|
|
/*! TRIM5_2 - TRIM5_2 */
|
|
#define FMUTEST_SOCTRIM5_2_TRIM5_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM5_2_TRIM5_2_SHIFT)) & FMUTEST_SOCTRIM5_2_TRIM5_2_MASK)
|
|
/*! @} */
|
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|
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/*! @name SOCTRIM5_3 - SoC Trim Phrase 5 Word 3 Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_SOCTRIM5_3_TRIM5_3_MASK (0xFFFFFFFFU)
|
|
#define FMUTEST_SOCTRIM5_3_TRIM5_3_SHIFT (0U)
|
|
/*! TRIM5_3 - TRIM5_3 */
|
|
#define FMUTEST_SOCTRIM5_3_TRIM5_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM5_3_TRIM5_3_SHIFT)) & FMUTEST_SOCTRIM5_3_TRIM5_3_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SOCTRIM6_0 - SoC Trim Phrase 6 Word 0 Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_SOCTRIM6_0_TRIM6_0_MASK (0xFFFFFFFFU)
|
|
#define FMUTEST_SOCTRIM6_0_TRIM6_0_SHIFT (0U)
|
|
/*! TRIM6_0 - TRIM6_0 */
|
|
#define FMUTEST_SOCTRIM6_0_TRIM6_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM6_0_TRIM6_0_SHIFT)) & FMUTEST_SOCTRIM6_0_TRIM6_0_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SOCTRIM6_1 - SoC Trim Phrase 6 Word 1 Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_SOCTRIM6_1_TRIM6_1_MASK (0xFFFFFFFFU)
|
|
#define FMUTEST_SOCTRIM6_1_TRIM6_1_SHIFT (0U)
|
|
/*! TRIM6_1 - TRIM6_1 */
|
|
#define FMUTEST_SOCTRIM6_1_TRIM6_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM6_1_TRIM6_1_SHIFT)) & FMUTEST_SOCTRIM6_1_TRIM6_1_MASK)
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/*! @} */
|
|
|
|
/*! @name SOCTRIM6_2 - SoC Trim Phrase 6 Word 2 Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_SOCTRIM6_2_TRIM6_2_MASK (0xFFFFFFFFU)
|
|
#define FMUTEST_SOCTRIM6_2_TRIM6_2_SHIFT (0U)
|
|
/*! TRIM6_2 - TRIM6_2 */
|
|
#define FMUTEST_SOCTRIM6_2_TRIM6_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM6_2_TRIM6_2_SHIFT)) & FMUTEST_SOCTRIM6_2_TRIM6_2_MASK)
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|
/*! @} */
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|
/*! @name SOCTRIM6_3 - SoC Trim Phrase 6 Word 3 Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_SOCTRIM6_3_TRIM6_3_MASK (0xFFFFFFFFU)
|
|
#define FMUTEST_SOCTRIM6_3_TRIM6_3_SHIFT (0U)
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|
/*! TRIM6_3 - TRIM6_3 */
|
|
#define FMUTEST_SOCTRIM6_3_TRIM6_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM6_3_TRIM6_3_SHIFT)) & FMUTEST_SOCTRIM6_3_TRIM6_3_MASK)
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|
/*! @} */
|
|
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|
/*! @name SOCTRIM7_0 - SoC Trim Phrase 7 Word 0 Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_SOCTRIM7_0_TRIM7_0_MASK (0xFFFFFFFFU)
|
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#define FMUTEST_SOCTRIM7_0_TRIM7_0_SHIFT (0U)
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|
/*! TRIM7_0 - TRIM7_0 */
|
|
#define FMUTEST_SOCTRIM7_0_TRIM7_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM7_0_TRIM7_0_SHIFT)) & FMUTEST_SOCTRIM7_0_TRIM7_0_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SOCTRIM7_1 - SoC Trim Phrase 7 Word 1 Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_SOCTRIM7_1_TRIM7_1_MASK (0xFFFFFFFFU)
|
|
#define FMUTEST_SOCTRIM7_1_TRIM7_1_SHIFT (0U)
|
|
/*! TRIM7_1 - TRIM7_1 */
|
|
#define FMUTEST_SOCTRIM7_1_TRIM7_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM7_1_TRIM7_1_SHIFT)) & FMUTEST_SOCTRIM7_1_TRIM7_1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SOCTRIM7_2 - SoC Trim Phrase 7 Word 2 Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_SOCTRIM7_2_TRIM7_2_MASK (0xFFFFFFFFU)
|
|
#define FMUTEST_SOCTRIM7_2_TRIM7_2_SHIFT (0U)
|
|
/*! TRIM7_2 - TRIM7_2 */
|
|
#define FMUTEST_SOCTRIM7_2_TRIM7_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM7_2_TRIM7_2_SHIFT)) & FMUTEST_SOCTRIM7_2_TRIM7_2_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SOCTRIM7_3 - SoC Trim Phrase 7 Word 3 Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_SOCTRIM7_3_TRIM7_3_MASK (0xFFFFFFFFU)
|
|
#define FMUTEST_SOCTRIM7_3_TRIM7_3_SHIFT (0U)
|
|
/*! TRIM7_3 - TRIM7_3 */
|
|
#define FMUTEST_SOCTRIM7_3_TRIM7_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM7_3_TRIM7_3_SHIFT)) & FMUTEST_SOCTRIM7_3_TRIM7_3_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name R_IP_CONFIG - BIST Configuration Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_R_IP_CONFIG_IPSEL0_MASK (0x3U)
|
|
#define FMUTEST_R_IP_CONFIG_IPSEL0_SHIFT (0U)
|
|
/*! IPSEL0 - Block 0 Select Control
|
|
* 0b00..Unselect block 0
|
|
* 0b01..not used, reserved
|
|
* 0b10..Enable block 0 test, repair off (default)
|
|
* 0b11..Enable block 0 test, repair on
|
|
*/
|
|
#define FMUTEST_R_IP_CONFIG_IPSEL0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_IPSEL0_SHIFT)) & FMUTEST_R_IP_CONFIG_IPSEL0_MASK)
|
|
|
|
#define FMUTEST_R_IP_CONFIG_IPSEL1_MASK (0xCU)
|
|
#define FMUTEST_R_IP_CONFIG_IPSEL1_SHIFT (2U)
|
|
/*! IPSEL1 - Block 1 Select Control
|
|
* 0b00..Unselect block 1
|
|
* 0b01..not used, reserved
|
|
* 0b10..Enable block 1 test, repair off (default)
|
|
* 0b11..Enable block 1 test, repair on
|
|
*/
|
|
#define FMUTEST_R_IP_CONFIG_IPSEL1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_IPSEL1_SHIFT)) & FMUTEST_R_IP_CONFIG_IPSEL1_MASK)
|
|
|
|
#define FMUTEST_R_IP_CONFIG_BIST_CDIVL_MASK (0xFF0U)
|
|
#define FMUTEST_R_IP_CONFIG_BIST_CDIVL_SHIFT (4U)
|
|
/*! BIST_CDIVL - Clock Divide Scalar for Long Pulse */
|
|
#define FMUTEST_R_IP_CONFIG_BIST_CDIVL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_BIST_CDIVL_SHIFT)) & FMUTEST_R_IP_CONFIG_BIST_CDIVL_MASK)
|
|
|
|
#define FMUTEST_R_IP_CONFIG_CDIVS_MASK (0x7000U)
|
|
#define FMUTEST_R_IP_CONFIG_CDIVS_SHIFT (12U)
|
|
/*! CDIVS - Number of clock cycles to generate short pulse */
|
|
#define FMUTEST_R_IP_CONFIG_CDIVS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_CDIVS_SHIFT)) & FMUTEST_R_IP_CONFIG_CDIVS_MASK)
|
|
|
|
#define FMUTEST_R_IP_CONFIG_BIST_TVFY_MASK (0xF8000U)
|
|
#define FMUTEST_R_IP_CONFIG_BIST_TVFY_SHIFT (15U)
|
|
/*! BIST_TVFY - Timer adjust for verify */
|
|
#define FMUTEST_R_IP_CONFIG_BIST_TVFY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_BIST_TVFY_SHIFT)) & FMUTEST_R_IP_CONFIG_BIST_TVFY_MASK)
|
|
|
|
#define FMUTEST_R_IP_CONFIG_TSTCTL_MASK (0x300000U)
|
|
#define FMUTEST_R_IP_CONFIG_TSTCTL_SHIFT (20U)
|
|
/*! TSTCTL - BIST self-test control
|
|
* 0b00..Default, disable both BIST self-test and MISR
|
|
* 0b01..Enable BIST self-test mode DOUT from macro will be forced to '0', and disable MISR.
|
|
* 0b10..Enable MISR
|
|
* 0b11..Enable both BIST self-test mode and MISR
|
|
*/
|
|
#define FMUTEST_R_IP_CONFIG_TSTCTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_TSTCTL_SHIFT)) & FMUTEST_R_IP_CONFIG_TSTCTL_MASK)
|
|
|
|
#define FMUTEST_R_IP_CONFIG_DBGCTL_MASK (0x400000U)
|
|
#define FMUTEST_R_IP_CONFIG_DBGCTL_SHIFT (22U)
|
|
/*! DBGCTL - Debug feature control
|
|
* 0b0..Default
|
|
* 0b1..Enable debug feature to collect failure address and data.
|
|
*/
|
|
#define FMUTEST_R_IP_CONFIG_DBGCTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_DBGCTL_SHIFT)) & FMUTEST_R_IP_CONFIG_DBGCTL_MASK)
|
|
|
|
#define FMUTEST_R_IP_CONFIG_BIST_CLK_SEL_MASK (0x800000U)
|
|
#define FMUTEST_R_IP_CONFIG_BIST_CLK_SEL_SHIFT (23U)
|
|
/*! BIST_CLK_SEL - BIST Clock Select */
|
|
#define FMUTEST_R_IP_CONFIG_BIST_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_BIST_CLK_SEL_SHIFT)) & FMUTEST_R_IP_CONFIG_BIST_CLK_SEL_MASK)
|
|
|
|
#define FMUTEST_R_IP_CONFIG_SMWTST_MASK (0x3000000U)
|
|
#define FMUTEST_R_IP_CONFIG_SMWTST_SHIFT (24U)
|
|
/*! SMWTST - SMWR DOUT Function Control
|
|
* 0b00..Default
|
|
* 0b01..Enable SMWR self-test mode, DOUT from macro will be forced to all 0
|
|
* 0b10..Enable SMWR self-test mode, DOUT from macro will be forced to all 1
|
|
* 0b11..Reserved (unused)
|
|
*/
|
|
#define FMUTEST_R_IP_CONFIG_SMWTST(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_SMWTST_SHIFT)) & FMUTEST_R_IP_CONFIG_SMWTST_MASK)
|
|
|
|
#define FMUTEST_R_IP_CONFIG_ECCEN_MASK (0x4000000U)
|
|
#define FMUTEST_R_IP_CONFIG_ECCEN_SHIFT (26U)
|
|
/*! ECCEN - BIST ECC Control
|
|
* 0b0..Default mode (no ECC encode or decode)
|
|
* 0b1..Enable ECC encode/decode
|
|
*/
|
|
#define FMUTEST_R_IP_CONFIG_ECCEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_ECCEN_SHIFT)) & FMUTEST_R_IP_CONFIG_ECCEN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name R_TESTCODE - BIST Test Code Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_R_TESTCODE_TESTCODE_MASK (0x3FU)
|
|
#define FMUTEST_R_TESTCODE_TESTCODE_SHIFT (0U)
|
|
/*! TESTCODE - Used to store test code information before running TMR-RST/TMRSET BIST command */
|
|
#define FMUTEST_R_TESTCODE_TESTCODE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TESTCODE_TESTCODE_SHIFT)) & FMUTEST_R_TESTCODE_TESTCODE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name R_DFT_CTRL - BIST DFT Control Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_R_DFT_CTRL_DFT_XADR_MASK (0xFU)
|
|
#define FMUTEST_R_DFT_CTRL_DFT_XADR_SHIFT (0U)
|
|
/*! DFT_XADR - DFT XADR Pattern
|
|
* 0b0000..XADR fixed, no change at all
|
|
* 0b0001..XADR increased by 1 after row. For READ operation, XADR increases by 1 after reading the last word of
|
|
* row. For PROG operation, XADR increases by 1 after NVSTR falls.
|
|
* 0b0010..XADR increased for diagonal. For PROG-DIAGONAL operation, XADR is increased to create diagonal pattern.
|
|
* 0b0011..XADR increased by sector. During ERASE operation, XADR increased by number of rows in a sector when NVSTR falls.
|
|
* 0b0100..XADR inversed. XADR is inversed after reading one word or after programming one row when NVSTR falls.
|
|
* 0b0101..XADR increased by 2 after row. For READ operation, XADR is increased by 2 after reading the last word
|
|
* of a row. For PROG operation, XADR is increased by 2 when NVSTR falls.
|
|
* 0b0110..XADR[0] inversed. XADR[0] is inversed after reading one word or after programming one row when NVSTR falls.
|
|
* 0b0111..XADR increased by 1. For READ operations only, XADR increased by 1 after each read cycle.
|
|
* 0b1000..XADR decreased by 1 after row. For READ operations only, XADR is decreased by 1 after YADR decreases to 0.
|
|
* 0b1001..XADR decreased by 1. For READ operations only, XADR is decreased by 1 after each read cycle.
|
|
*/
|
|
#define FMUTEST_R_DFT_CTRL_DFT_XADR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DFT_CTRL_DFT_XADR_SHIFT)) & FMUTEST_R_DFT_CTRL_DFT_XADR_MASK)
|
|
|
|
#define FMUTEST_R_DFT_CTRL_DFT_YADR_MASK (0xF0U)
|
|
#define FMUTEST_R_DFT_CTRL_DFT_YADR_SHIFT (4U)
|
|
/*! DFT_YADR - DFT YADR Pattern
|
|
* 0b0000..YADR fixed, no change at all
|
|
* 0b0001..YADR for ICKBD. For PROG and READ operations, YADR changed to generate inverse checkerboard pattern.
|
|
* 0b0010..YADR for CKBD. For PROG and READ operations, YADR changed to generate checkerboard pattern.
|
|
* 0b0011..YADR increased by 1. For READ operations, YADR increased by 1 after each read cycle. For PROG
|
|
* operations, YADR increased by 1 after YE falls.
|
|
* 0b0100..YADR increased for diagonal. For PROG-DIAGONAL operation, YADR is increased to create diagonal pattern.
|
|
* 0b0101..YADR inversed. YADR is inversed after reading one word or after programming one word when YE falls.
|
|
* 0b0110..YADR[0] inversed. YADR[0] is inversed after reading one word or after programming one word when YE falls.
|
|
* 0b0111..YADR increased by 1 after last row. For READ operations only, YADR is increased by 1 after XADR reaches last row.
|
|
* 0b1000..YADR decreased by 1. For READ operations only, YADR is decreased by 1 after each read cycle.
|
|
* 0b1001..YADR decreased by 1 after first row. For READ operations only, YADR is decreased by 1 after XADR decreases to 0.
|
|
*/
|
|
#define FMUTEST_R_DFT_CTRL_DFT_YADR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DFT_CTRL_DFT_YADR_SHIFT)) & FMUTEST_R_DFT_CTRL_DFT_YADR_MASK)
|
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|
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#define FMUTEST_R_DFT_CTRL_DFT_DATA_MASK (0xF00U)
|
|
#define FMUTEST_R_DFT_CTRL_DFT_DATA_SHIFT (8U)
|
|
/*! DFT_DATA - DFT Data Pattern
|
|
* 0b0000..CKBD pattern. For READ operations only, compare DOUT with checkerboard data pattern for each read cycle.
|
|
* 0b0001..ICKBD pattern. For READ operations only, compare DOUT with inverse checkerboard data pattern for each read cycle.
|
|
* 0b0010..Diagonal pattern. Used for READ operations only, compare DOUT to diagonal pattern.
|
|
* 0b0011..Fixed data pattern. For READ operations, comparison to DOUT for selected groups; refer to
|
|
* R_ADR_CTRL[GRPSEL] for modules with multiple groups.
|
|
* 0b0100..Random data pattern which will be generated based on the initial seed set in R_DATA; for READ
|
|
* operations, used for DOUT comparison of selected groups. For PROG operations, used to control DIN of selected
|
|
* groups.
|
|
* 0b0101..DOUT based pattern. For READ operations only, DOUT of selected group will be latched in R_DATA. If
|
|
* more than one group is selected in R_ADR_CTRL[GRPSEL], the group with the lower index will be latched.
|
|
* 0b0110..R_DATA based pattern. For READ operations, expected DOUT value of selected groups equals to R_DATA
|
|
* when XADR[0]==YADR[0] or ~R_DATA when XADR[0]!=YADR[0]. For PROG operations, DIN of selected groups equals
|
|
* R_DATA when XADR[0]==YADR[0] or ~R_DATA when XADR[0]!=YADR[0].
|
|
* 0b0111..SCAN-IO pattern. For READ operations, control expected DOUT value of selected groups to SCAN-IO data
|
|
* pattern. For PROG operations, control DIN of selected groups to SCAN-IO data pattern.
|
|
* 0b1000..REPAIR set. For PROG operation to IFR1(7,1) and IFR1(7,2), R_REPAIR0_0 and R_REPAIR0_1 or R_REPAIR1_0
|
|
* and R_REPAIR1_1 will control DIN. For READ operation on IFR1(7,1) and IFR1(7,2), DOUT will be compared
|
|
* against R_REPAIR0_0 and R_REPAIR0_1 or R_REPAIR1_0 andR_REPAIR1_1. When this option is selected, only
|
|
* one flash block can be selected.
|
|
* 0b1001..REPAIR load. For READ operation only, DOUT from IFR1(7,1) and IFR1(7,2) is loaded to R_REPAIR0 and R_REPAIR1.
|
|
*/
|
|
#define FMUTEST_R_DFT_CTRL_DFT_DATA(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DFT_CTRL_DFT_DATA_SHIFT)) & FMUTEST_R_DFT_CTRL_DFT_DATA_MASK)
|
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|
|
#define FMUTEST_R_DFT_CTRL_CMP_MASK_MASK (0x3000U)
|
|
#define FMUTEST_R_DFT_CTRL_CMP_MASK_SHIFT (12U)
|
|
/*! CMP_MASK - Data Compare Mask
|
|
* 0b00..Expected data is compared to DOUT
|
|
* 0b01..Expected data (only 0s are considered) are compared to DOUT
|
|
* 0b10..Expected data (only 1s are considered) are compared to DOUT
|
|
*/
|
|
#define FMUTEST_R_DFT_CTRL_CMP_MASK(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DFT_CTRL_CMP_MASK_SHIFT)) & FMUTEST_R_DFT_CTRL_CMP_MASK_MASK)
|
|
|
|
#define FMUTEST_R_DFT_CTRL_DFT_DATA_SRC_MASK (0x4000U)
|
|
#define FMUTEST_R_DFT_CTRL_DFT_DATA_SRC_SHIFT (14U)
|
|
/*! DFT_DATA_SRC - DFT Data Source
|
|
* 0b0..{R_DATA_CTRL0,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0} is used
|
|
* 0b1..{R_DATA_CTRL3,R_DATA_CTRL2_EX[2:0],R_DATA_CTRL2,R_DATA_CTRL1_EX[2:0],R_DATA_CTRL1,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0} is used
|
|
*/
|
|
#define FMUTEST_R_DFT_CTRL_DFT_DATA_SRC(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DFT_CTRL_DFT_DATA_SRC_SHIFT)) & FMUTEST_R_DFT_CTRL_DFT_DATA_SRC_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name R_ADR_CTRL - BIST Address Control Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_R_ADR_CTRL_GRPSEL_MASK (0xFU)
|
|
#define FMUTEST_R_ADR_CTRL_GRPSEL_SHIFT (0U)
|
|
/*! GRPSEL - Data Group Select
|
|
* 0b0000..Select no data
|
|
* 0b0001..Select data slice [34:0]
|
|
* 0b0010..Select data slice [69:35]
|
|
* 0b0100..Select data slice [104:70]
|
|
* 0b1000..Select data slice [136:105]
|
|
* 0b1111..Select data [136:0]
|
|
*/
|
|
#define FMUTEST_R_ADR_CTRL_GRPSEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_CTRL_GRPSEL_SHIFT)) & FMUTEST_R_ADR_CTRL_GRPSEL_MASK)
|
|
|
|
#define FMUTEST_R_ADR_CTRL_XADR_MASK (0xFFF0U)
|
|
#define FMUTEST_R_ADR_CTRL_XADR_SHIFT (4U)
|
|
/*! XADR - BIST XADR */
|
|
#define FMUTEST_R_ADR_CTRL_XADR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_CTRL_XADR_SHIFT)) & FMUTEST_R_ADR_CTRL_XADR_MASK)
|
|
|
|
#define FMUTEST_R_ADR_CTRL_YADR_MASK (0x1F0000U)
|
|
#define FMUTEST_R_ADR_CTRL_YADR_SHIFT (16U)
|
|
/*! YADR - BIST YADR */
|
|
#define FMUTEST_R_ADR_CTRL_YADR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_CTRL_YADR_SHIFT)) & FMUTEST_R_ADR_CTRL_YADR_MASK)
|
|
|
|
#define FMUTEST_R_ADR_CTRL_PROG_ATTR_MASK (0xE00000U)
|
|
#define FMUTEST_R_ADR_CTRL_PROG_ATTR_SHIFT (21U)
|
|
/*! PROG_ATTR - Program Attribute
|
|
* 0b000..One YE pulse will program one data slice group
|
|
* 0b001..One YE pulse will program two data slice groups
|
|
* 0b010..One YE pulse will program three data slice groups (reserved)
|
|
* 0b011..One YE pulse will program four data slice groups
|
|
* 0b100..One YE pulse will program five data slice groups (reserved)
|
|
* 0b101..One YE pulse will program six data slice groups (reserved)
|
|
* 0b110..One YE pulse will program seven data slice groups (reserved)
|
|
* 0b111..One YE pulse will program eight data slice groups (reserved)
|
|
*/
|
|
#define FMUTEST_R_ADR_CTRL_PROG_ATTR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_CTRL_PROG_ATTR_SHIFT)) & FMUTEST_R_ADR_CTRL_PROG_ATTR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name R_DATA_CTRL0 - BIST Data Control 0 Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_R_DATA_CTRL0_DATA0_MASK (0xFFFFFFFFU)
|
|
#define FMUTEST_R_DATA_CTRL0_DATA0_SHIFT (0U)
|
|
/*! DATA0 - BIST Data 0 Low */
|
|
#define FMUTEST_R_DATA_CTRL0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL0_DATA0_SHIFT)) & FMUTEST_R_DATA_CTRL0_DATA0_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name R_PIN_CTRL - BIST Pin Control Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_R_PIN_CTRL_MAS1_MASK (0x1U)
|
|
#define FMUTEST_R_PIN_CTRL_MAS1_SHIFT (0U)
|
|
/*! MAS1 - Mass Erase */
|
|
#define FMUTEST_R_PIN_CTRL_MAS1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_MAS1_SHIFT)) & FMUTEST_R_PIN_CTRL_MAS1_MASK)
|
|
|
|
#define FMUTEST_R_PIN_CTRL_IFREN_MASK (0x2U)
|
|
#define FMUTEST_R_PIN_CTRL_IFREN_SHIFT (1U)
|
|
/*! IFREN - IFR Enable */
|
|
#define FMUTEST_R_PIN_CTRL_IFREN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_IFREN_SHIFT)) & FMUTEST_R_PIN_CTRL_IFREN_MASK)
|
|
|
|
#define FMUTEST_R_PIN_CTRL_IFREN1_MASK (0x4U)
|
|
#define FMUTEST_R_PIN_CTRL_IFREN1_SHIFT (2U)
|
|
/*! IFREN1 - IFR1 Enable */
|
|
#define FMUTEST_R_PIN_CTRL_IFREN1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_IFREN1_SHIFT)) & FMUTEST_R_PIN_CTRL_IFREN1_MASK)
|
|
|
|
#define FMUTEST_R_PIN_CTRL_REDEN_MASK (0x8U)
|
|
#define FMUTEST_R_PIN_CTRL_REDEN_SHIFT (3U)
|
|
/*! REDEN - Redundancy Block Enable */
|
|
#define FMUTEST_R_PIN_CTRL_REDEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_REDEN_SHIFT)) & FMUTEST_R_PIN_CTRL_REDEN_MASK)
|
|
|
|
#define FMUTEST_R_PIN_CTRL_LVE_MASK (0x10U)
|
|
#define FMUTEST_R_PIN_CTRL_LVE_SHIFT (4U)
|
|
/*! LVE - Low Voltage Enable */
|
|
#define FMUTEST_R_PIN_CTRL_LVE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_LVE_SHIFT)) & FMUTEST_R_PIN_CTRL_LVE_MASK)
|
|
|
|
#define FMUTEST_R_PIN_CTRL_PV_MASK (0x20U)
|
|
#define FMUTEST_R_PIN_CTRL_PV_SHIFT (5U)
|
|
/*! PV - Program Verify Enable */
|
|
#define FMUTEST_R_PIN_CTRL_PV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_PV_SHIFT)) & FMUTEST_R_PIN_CTRL_PV_MASK)
|
|
|
|
#define FMUTEST_R_PIN_CTRL_EV_MASK (0x40U)
|
|
#define FMUTEST_R_PIN_CTRL_EV_SHIFT (6U)
|
|
/*! EV - Erase Verify Enable */
|
|
#define FMUTEST_R_PIN_CTRL_EV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_EV_SHIFT)) & FMUTEST_R_PIN_CTRL_EV_MASK)
|
|
|
|
#define FMUTEST_R_PIN_CTRL_WIPGM_MASK (0x180U)
|
|
#define FMUTEST_R_PIN_CTRL_WIPGM_SHIFT (7U)
|
|
/*! WIPGM - Program Current */
|
|
#define FMUTEST_R_PIN_CTRL_WIPGM(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_WIPGM_SHIFT)) & FMUTEST_R_PIN_CTRL_WIPGM_MASK)
|
|
|
|
#define FMUTEST_R_PIN_CTRL_WHV_MASK (0x1E00U)
|
|
#define FMUTEST_R_PIN_CTRL_WHV_SHIFT (9U)
|
|
/*! WHV - High Voltage Level */
|
|
#define FMUTEST_R_PIN_CTRL_WHV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_WHV_SHIFT)) & FMUTEST_R_PIN_CTRL_WHV_MASK)
|
|
|
|
#define FMUTEST_R_PIN_CTRL_WMV_MASK (0xE000U)
|
|
#define FMUTEST_R_PIN_CTRL_WMV_SHIFT (13U)
|
|
/*! WMV - Medium Voltage Level */
|
|
#define FMUTEST_R_PIN_CTRL_WMV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_WMV_SHIFT)) & FMUTEST_R_PIN_CTRL_WMV_MASK)
|
|
|
|
#define FMUTEST_R_PIN_CTRL_XE_MASK (0x10000U)
|
|
#define FMUTEST_R_PIN_CTRL_XE_SHIFT (16U)
|
|
/*! XE - X Address Enable */
|
|
#define FMUTEST_R_PIN_CTRL_XE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_XE_SHIFT)) & FMUTEST_R_PIN_CTRL_XE_MASK)
|
|
|
|
#define FMUTEST_R_PIN_CTRL_YE_MASK (0x20000U)
|
|
#define FMUTEST_R_PIN_CTRL_YE_SHIFT (17U)
|
|
/*! YE - Y Address Enable */
|
|
#define FMUTEST_R_PIN_CTRL_YE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_YE_SHIFT)) & FMUTEST_R_PIN_CTRL_YE_MASK)
|
|
|
|
#define FMUTEST_R_PIN_CTRL_SE_MASK (0x40000U)
|
|
#define FMUTEST_R_PIN_CTRL_SE_SHIFT (18U)
|
|
/*! SE - Sense Amp Enable */
|
|
#define FMUTEST_R_PIN_CTRL_SE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_SE_SHIFT)) & FMUTEST_R_PIN_CTRL_SE_MASK)
|
|
|
|
#define FMUTEST_R_PIN_CTRL_ERASE_MASK (0x80000U)
|
|
#define FMUTEST_R_PIN_CTRL_ERASE_SHIFT (19U)
|
|
/*! ERASE - Erase Mode */
|
|
#define FMUTEST_R_PIN_CTRL_ERASE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_ERASE_SHIFT)) & FMUTEST_R_PIN_CTRL_ERASE_MASK)
|
|
|
|
#define FMUTEST_R_PIN_CTRL_PROG_MASK (0x100000U)
|
|
#define FMUTEST_R_PIN_CTRL_PROG_SHIFT (20U)
|
|
/*! PROG - Program Mode */
|
|
#define FMUTEST_R_PIN_CTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_PROG_SHIFT)) & FMUTEST_R_PIN_CTRL_PROG_MASK)
|
|
|
|
#define FMUTEST_R_PIN_CTRL_NVSTR_MASK (0x200000U)
|
|
#define FMUTEST_R_PIN_CTRL_NVSTR_SHIFT (21U)
|
|
/*! NVSTR - NVM Store */
|
|
#define FMUTEST_R_PIN_CTRL_NVSTR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_NVSTR_SHIFT)) & FMUTEST_R_PIN_CTRL_NVSTR_MASK)
|
|
|
|
#define FMUTEST_R_PIN_CTRL_SLM_MASK (0x400000U)
|
|
#define FMUTEST_R_PIN_CTRL_SLM_SHIFT (22U)
|
|
/*! SLM - Sleep Mode Enable */
|
|
#define FMUTEST_R_PIN_CTRL_SLM(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_SLM_SHIFT)) & FMUTEST_R_PIN_CTRL_SLM_MASK)
|
|
|
|
#define FMUTEST_R_PIN_CTRL_RECALL_MASK (0x800000U)
|
|
#define FMUTEST_R_PIN_CTRL_RECALL_SHIFT (23U)
|
|
/*! RECALL - Recall Trim Code */
|
|
#define FMUTEST_R_PIN_CTRL_RECALL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_RECALL_SHIFT)) & FMUTEST_R_PIN_CTRL_RECALL_MASK)
|
|
|
|
#define FMUTEST_R_PIN_CTRL_HEM_MASK (0x1000000U)
|
|
#define FMUTEST_R_PIN_CTRL_HEM_SHIFT (24U)
|
|
/*! HEM - HEM Control */
|
|
#define FMUTEST_R_PIN_CTRL_HEM(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_HEM_SHIFT)) & FMUTEST_R_PIN_CTRL_HEM_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name R_CNT_LOOP_CTRL - BIST Loop Count Control Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_R_CNT_LOOP_CTRL_LOOPCNT_MASK (0xFFFU)
|
|
#define FMUTEST_R_CNT_LOOP_CTRL_LOOPCNT_SHIFT (0U)
|
|
/*! LOOPCNT - Loop Count Control */
|
|
#define FMUTEST_R_CNT_LOOP_CTRL_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_CNT_LOOP_CTRL_LOOPCNT_SHIFT)) & FMUTEST_R_CNT_LOOP_CTRL_LOOPCNT_MASK)
|
|
|
|
#define FMUTEST_R_CNT_LOOP_CTRL_LOOPOPT_MASK (0x7000U)
|
|
#define FMUTEST_R_CNT_LOOP_CTRL_LOOPOPT_SHIFT (12U)
|
|
/*! LOOPOPT - Loop Option
|
|
* 0b000..Loop is disabled; selected BIST operation is run once
|
|
* 0b001..Loop is enabled; XADR increments by 1 XADR increments by 1 for each new loop. Stops when total loop count meets LOOPCNT+1.
|
|
* 0b010..Loop is enabled; YADR increments by 1 YADR increments by 1 for each new loop. Stops when total loop count meets LOOPCNT+1.
|
|
* 0b011..Loop is enabled; XADR increments by 2 XADR increments by 2 for each new loop. Stops when total loop count meets LOOPCNT+1.
|
|
* 0b100..Loop is enabled; XADR increments by sector XADR increments by 16 for each new loop. Stops when total loop count meets LOOPCNT+1.
|
|
*/
|
|
#define FMUTEST_R_CNT_LOOP_CTRL_LOOPOPT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_CNT_LOOP_CTRL_LOOPOPT_SHIFT)) & FMUTEST_R_CNT_LOOP_CTRL_LOOPOPT_MASK)
|
|
|
|
#define FMUTEST_R_CNT_LOOP_CTRL_LOOPUNIT_MASK (0x38000U)
|
|
#define FMUTEST_R_CNT_LOOP_CTRL_LOOPUNIT_SHIFT (15U)
|
|
/*! LOOPUNIT - Loop Time Unit
|
|
* 0b000..Clock cycles
|
|
* 0b001..0.5 usec
|
|
* 0b010..1 usec
|
|
* 0b011..10 usec
|
|
* 0b100..100 usec
|
|
* 0b101..1 msec
|
|
* 0b110..10 msec
|
|
* 0b111..100 msec
|
|
*/
|
|
#define FMUTEST_R_CNT_LOOP_CTRL_LOOPUNIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_CNT_LOOP_CTRL_LOOPUNIT_SHIFT)) & FMUTEST_R_CNT_LOOP_CTRL_LOOPUNIT_MASK)
|
|
|
|
#define FMUTEST_R_CNT_LOOP_CTRL_LOOPDLY_MASK (0x1FC0000U)
|
|
#define FMUTEST_R_CNT_LOOP_CTRL_LOOPDLY_SHIFT (18U)
|
|
/*! LOOPDLY - Loop Time Delay Scalar */
|
|
#define FMUTEST_R_CNT_LOOP_CTRL_LOOPDLY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_CNT_LOOP_CTRL_LOOPDLY_SHIFT)) & FMUTEST_R_CNT_LOOP_CTRL_LOOPDLY_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name R_TIMER_CTRL - BIST Timer Control Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_R_TIMER_CTRL_TNVSUNIT_MASK (0x7U)
|
|
#define FMUTEST_R_TIMER_CTRL_TNVSUNIT_SHIFT (0U)
|
|
/*! TNVSUNIT - Tnvs Time Unit
|
|
* 0b000..Clock cycles
|
|
* 0b001..0.5 usec
|
|
* 0b010..1 usec
|
|
* 0b011..10 usec
|
|
* 0b100..100 usec
|
|
* 0b101..1 msec
|
|
* 0b110..10 msec
|
|
* 0b111..100 msec
|
|
*/
|
|
#define FMUTEST_R_TIMER_CTRL_TNVSUNIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TNVSUNIT_SHIFT)) & FMUTEST_R_TIMER_CTRL_TNVSUNIT_MASK)
|
|
|
|
#define FMUTEST_R_TIMER_CTRL_TNVSDLY_MASK (0x78U)
|
|
#define FMUTEST_R_TIMER_CTRL_TNVSDLY_SHIFT (3U)
|
|
/*! TNVSDLY - Tnvs Time Delay Scalar */
|
|
#define FMUTEST_R_TIMER_CTRL_TNVSDLY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TNVSDLY_SHIFT)) & FMUTEST_R_TIMER_CTRL_TNVSDLY_MASK)
|
|
|
|
#define FMUTEST_R_TIMER_CTRL_TNVHUNIT_MASK (0x380U)
|
|
#define FMUTEST_R_TIMER_CTRL_TNVHUNIT_SHIFT (7U)
|
|
/*! TNVHUNIT - Tnvh Time Unit
|
|
* 0b000..Clock cycles
|
|
* 0b001..0.5 usec
|
|
* 0b010..1 usec
|
|
* 0b011..10 usec
|
|
* 0b100..100 usec
|
|
* 0b101..1 msec
|
|
* 0b110..10 msec
|
|
* 0b111..100 msec
|
|
*/
|
|
#define FMUTEST_R_TIMER_CTRL_TNVHUNIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TNVHUNIT_SHIFT)) & FMUTEST_R_TIMER_CTRL_TNVHUNIT_MASK)
|
|
|
|
#define FMUTEST_R_TIMER_CTRL_TNVHDLY_MASK (0x3C00U)
|
|
#define FMUTEST_R_TIMER_CTRL_TNVHDLY_SHIFT (10U)
|
|
/*! TNVHDLY - Tnvh Time Delay Scalar */
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#define FMUTEST_R_TIMER_CTRL_TNVHDLY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TNVHDLY_SHIFT)) & FMUTEST_R_TIMER_CTRL_TNVHDLY_MASK)
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#define FMUTEST_R_TIMER_CTRL_TPGSUNIT_MASK (0x1C000U)
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#define FMUTEST_R_TIMER_CTRL_TPGSUNIT_SHIFT (14U)
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/*! TPGSUNIT - Tpgs Time Unit
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* 0b000..Clock cycles
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* 0b001..0.5 usec
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* 0b010..1 usec
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* 0b011..10 usec
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* 0b100..100 usec
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* 0b101..1 msec
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* 0b110..10 msec
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* 0b111..100 msec
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*/
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#define FMUTEST_R_TIMER_CTRL_TPGSUNIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TPGSUNIT_SHIFT)) & FMUTEST_R_TIMER_CTRL_TPGSUNIT_MASK)
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#define FMUTEST_R_TIMER_CTRL_TPGSDLY_MASK (0x1E0000U)
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#define FMUTEST_R_TIMER_CTRL_TPGSDLY_SHIFT (17U)
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/*! TPGSDLY - Tpgs Time Delay Scalar */
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#define FMUTEST_R_TIMER_CTRL_TPGSDLY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TPGSDLY_SHIFT)) & FMUTEST_R_TIMER_CTRL_TPGSDLY_MASK)
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#define FMUTEST_R_TIMER_CTRL_TRCVUNIT_MASK (0xE00000U)
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#define FMUTEST_R_TIMER_CTRL_TRCVUNIT_SHIFT (21U)
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/*! TRCVUNIT - Trcv Time Unit
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* 0b000..Clock cycles
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* 0b001..0.5 usec
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* 0b010..1 usec
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* 0b011..10 usec
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* 0b100..100 usec
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* 0b101..1 msec
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* 0b110..10 msec
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* 0b111..100 msec
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*/
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#define FMUTEST_R_TIMER_CTRL_TRCVUNIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TRCVUNIT_SHIFT)) & FMUTEST_R_TIMER_CTRL_TRCVUNIT_MASK)
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#define FMUTEST_R_TIMER_CTRL_TRCVDLY_MASK (0xF000000U)
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#define FMUTEST_R_TIMER_CTRL_TRCVDLY_SHIFT (24U)
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/*! TRCVDLY - Trcv Time Delay Scalar */
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#define FMUTEST_R_TIMER_CTRL_TRCVDLY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TRCVDLY_SHIFT)) & FMUTEST_R_TIMER_CTRL_TRCVDLY_MASK)
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#define FMUTEST_R_TIMER_CTRL_TLVSUNIT_MASK (0x70000000U)
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#define FMUTEST_R_TIMER_CTRL_TLVSUNIT_SHIFT (28U)
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/*! TLVSUNIT - Tlvs Time Unit
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* 0b000..Clock cycles
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* 0b001..0.5 usec
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* 0b010..1 usec
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* 0b011..10 usec
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* 0b100..100 usec
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* 0b101..1 msec
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* 0b110..10 msec
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* 0b111..100 msec
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*/
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#define FMUTEST_R_TIMER_CTRL_TLVSUNIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TLVSUNIT_SHIFT)) & FMUTEST_R_TIMER_CTRL_TLVSUNIT_MASK)
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#define FMUTEST_R_TIMER_CTRL_TLVSDLY_L_MASK (0x80000000U)
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#define FMUTEST_R_TIMER_CTRL_TLVSDLY_L_SHIFT (31U)
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/*! TLVSDLY_L - Tlvs Time Delay Scalar Low */
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#define FMUTEST_R_TIMER_CTRL_TLVSDLY_L(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TLVSDLY_L_SHIFT)) & FMUTEST_R_TIMER_CTRL_TLVSDLY_L_MASK)
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/*! @} */
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/*! @name R_TEST_CTRL - BIST Test Control Register */
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/*! @{ */
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#define FMUTEST_R_TEST_CTRL_BUSY_MASK (0x1U)
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#define FMUTEST_R_TEST_CTRL_BUSY_SHIFT (0U)
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/*! BUSY - BIST Busy Status
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* 0b0..BIST is idle
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* 0b1..BIST is busy
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*/
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#define FMUTEST_R_TEST_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_BUSY_SHIFT)) & FMUTEST_R_TEST_CTRL_BUSY_MASK)
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#define FMUTEST_R_TEST_CTRL_DEBUG_MASK (0x2U)
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#define FMUTEST_R_TEST_CTRL_DEBUG_SHIFT (1U)
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/*! DEBUG - BIST Debug Status */
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#define FMUTEST_R_TEST_CTRL_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DEBUG_SHIFT)) & FMUTEST_R_TEST_CTRL_DEBUG_MASK)
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#define FMUTEST_R_TEST_CTRL_STATUS0_MASK (0x4U)
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#define FMUTEST_R_TEST_CTRL_STATUS0_SHIFT (2U)
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/*! STATUS0 - BIST Status 0
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* 0b0..BIST test passed on flash block 0
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* 0b1..BIST test failed on flash block 0
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*/
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#define FMUTEST_R_TEST_CTRL_STATUS0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_STATUS0_SHIFT)) & FMUTEST_R_TEST_CTRL_STATUS0_MASK)
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#define FMUTEST_R_TEST_CTRL_STATUS1_MASK (0x8U)
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#define FMUTEST_R_TEST_CTRL_STATUS1_SHIFT (3U)
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/*! STATUS1 - BIST status 1
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* 0b0..BIST test passed on flash block 1
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* 0b1..BIST test failed on flash block 1
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*/
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#define FMUTEST_R_TEST_CTRL_STATUS1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_STATUS1_SHIFT)) & FMUTEST_R_TEST_CTRL_STATUS1_MASK)
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#define FMUTEST_R_TEST_CTRL_DEBUGRUN_MASK (0x10U)
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#define FMUTEST_R_TEST_CTRL_DEBUGRUN_SHIFT (4U)
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/*! DEBUGRUN - BIST Continue Debug Run */
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#define FMUTEST_R_TEST_CTRL_DEBUGRUN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DEBUGRUN_SHIFT)) & FMUTEST_R_TEST_CTRL_DEBUGRUN_MASK)
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#define FMUTEST_R_TEST_CTRL_STARTRUN_MASK (0x20U)
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#define FMUTEST_R_TEST_CTRL_STARTRUN_SHIFT (5U)
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/*! STARTRUN - Run New BIST Operation */
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#define FMUTEST_R_TEST_CTRL_STARTRUN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_STARTRUN_SHIFT)) & FMUTEST_R_TEST_CTRL_STARTRUN_MASK)
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#define FMUTEST_R_TEST_CTRL_CMDINDEX_MASK (0xFFC0U)
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#define FMUTEST_R_TEST_CTRL_CMDINDEX_SHIFT (6U)
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/*! CMDINDEX - BIST Command Index (code) */
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#define FMUTEST_R_TEST_CTRL_CMDINDEX(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_CMDINDEX_SHIFT)) & FMUTEST_R_TEST_CTRL_CMDINDEX_MASK)
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#define FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK (0x10000U)
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#define FMUTEST_R_TEST_CTRL_DISABLE_IP1_SHIFT (16U)
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/*! DISABLE_IP1 - BIST Disable IP1 */
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#define FMUTEST_R_TEST_CTRL_DISABLE_IP1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DISABLE_IP1_SHIFT)) & FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK)
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/*! @} */
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/*! @name R_ABORT_LOOP - BIST Abort Loop Register */
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/*! @{ */
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#define FMUTEST_R_ABORT_LOOP_ABORT_LOOP_MASK (0x1U)
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#define FMUTEST_R_ABORT_LOOP_ABORT_LOOP_SHIFT (0U)
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/*! ABORT_LOOP - Abort Loop
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* 0b0..No effect
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* 0b1..Abort BIST loop commands and force the loop counter to return to 0x0
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*/
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#define FMUTEST_R_ABORT_LOOP_ABORT_LOOP(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ABORT_LOOP_ABORT_LOOP_SHIFT)) & FMUTEST_R_ABORT_LOOP_ABORT_LOOP_MASK)
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/*! @} */
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/*! @name R_ADR_QUERY - BIST Address Query Register */
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/*! @{ */
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#define FMUTEST_R_ADR_QUERY_YADRFAIL_MASK (0x1FU)
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#define FMUTEST_R_ADR_QUERY_YADRFAIL_SHIFT (0U)
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/*! YADRFAIL - Failing YADR */
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#define FMUTEST_R_ADR_QUERY_YADRFAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_QUERY_YADRFAIL_SHIFT)) & FMUTEST_R_ADR_QUERY_YADRFAIL_MASK)
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#define FMUTEST_R_ADR_QUERY_XADRFAIL_MASK (0x1FFE0U)
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#define FMUTEST_R_ADR_QUERY_XADRFAIL_SHIFT (5U)
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/*! XADRFAIL - Failing XADR */
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#define FMUTEST_R_ADR_QUERY_XADRFAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_QUERY_XADRFAIL_SHIFT)) & FMUTEST_R_ADR_QUERY_XADRFAIL_MASK)
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/*! @} */
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/*! @name R_DOUT_QUERY0 - BIST DOUT Query 0 Register */
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/*! @{ */
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#define FMUTEST_R_DOUT_QUERY0_DOUTFAIL_MASK (0xFFFFFFFFU)
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#define FMUTEST_R_DOUT_QUERY0_DOUTFAIL_SHIFT (0U)
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/*! DOUTFAIL - Failing DOUT Low */
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#define FMUTEST_R_DOUT_QUERY0_DOUTFAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DOUT_QUERY0_DOUTFAIL_SHIFT)) & FMUTEST_R_DOUT_QUERY0_DOUTFAIL_MASK)
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/*! @} */
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/*! @name R_SMW_QUERY - BIST SMW Query Register */
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/*! @{ */
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#define FMUTEST_R_SMW_QUERY_SMWLOOP_MASK (0x3FFU)
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#define FMUTEST_R_SMW_QUERY_SMWLOOP_SHIFT (0U)
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/*! SMWLOOP - SMW Total Loop Count */
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#define FMUTEST_R_SMW_QUERY_SMWLOOP(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_QUERY_SMWLOOP_SHIFT)) & FMUTEST_R_SMW_QUERY_SMWLOOP_MASK)
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#define FMUTEST_R_SMW_QUERY_SMWLAST_MASK (0x7FC00U)
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#define FMUTEST_R_SMW_QUERY_SMWLAST_SHIFT (10U)
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/*! SMWLAST - SMW Last Voltage Setting */
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#define FMUTEST_R_SMW_QUERY_SMWLAST(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_QUERY_SMWLAST_SHIFT)) & FMUTEST_R_SMW_QUERY_SMWLAST_MASK)
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/*! @} */
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/*! @name R_SMW_SETTING0 - BIST SMW Setting 0 Register */
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/*! @{ */
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#define FMUTEST_R_SMW_SETTING0_SMWPARM0_MASK (0x7FFFFFFFU)
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#define FMUTEST_R_SMW_SETTING0_SMWPARM0_SHIFT (0U)
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/*! SMWPARM0 - SMW Parameter Set 0 */
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#define FMUTEST_R_SMW_SETTING0_SMWPARM0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING0_SMWPARM0_SHIFT)) & FMUTEST_R_SMW_SETTING0_SMWPARM0_MASK)
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/*! @} */
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/*! @name R_SMW_SETTING1 - BIST SMW Setting 1 Register */
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/*! @{ */
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#define FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK (0xFFFFFFFU)
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#define FMUTEST_R_SMW_SETTING1_SMWPARM1_SHIFT (0U)
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/*! SMWPARM1 - SMW Parameter Set 1 */
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#define FMUTEST_R_SMW_SETTING1_SMWPARM1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING1_SMWPARM1_SHIFT)) & FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK)
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/*! @} */
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/*! @name R_SMP_WHV0 - BIST SMP WHV Setting 0 Register */
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/*! @{ */
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#define FMUTEST_R_SMP_WHV0_SMPWHV0_MASK (0xFFFFFFFFU)
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#define FMUTEST_R_SMP_WHV0_SMPWHV0_SHIFT (0U)
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/*! SMPWHV0 - SMP WHV Parameter Set 0 */
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#define FMUTEST_R_SMP_WHV0_SMPWHV0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMP_WHV0_SMPWHV0_SHIFT)) & FMUTEST_R_SMP_WHV0_SMPWHV0_MASK)
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/*! @} */
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/*! @name R_SMP_WHV1 - BIST SMP WHV Setting 1 Register */
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/*! @{ */
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#define FMUTEST_R_SMP_WHV1_SMPWHV1_MASK (0xFFFFFFFFU)
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#define FMUTEST_R_SMP_WHV1_SMPWHV1_SHIFT (0U)
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/*! SMPWHV1 - SMP WHV Parameter Set 1 */
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#define FMUTEST_R_SMP_WHV1_SMPWHV1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMP_WHV1_SMPWHV1_SHIFT)) & FMUTEST_R_SMP_WHV1_SMPWHV1_MASK)
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/*! @} */
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/*! @name R_SME_WHV0 - BIST SME WHV Setting 0 Register */
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/*! @{ */
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#define FMUTEST_R_SME_WHV0_SMEWHV0_MASK (0xFFFFFFFFU)
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#define FMUTEST_R_SME_WHV0_SMEWHV0_SHIFT (0U)
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/*! SMEWHV0 - SME WHV Parameter Set 0 */
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#define FMUTEST_R_SME_WHV0_SMEWHV0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SME_WHV0_SMEWHV0_SHIFT)) & FMUTEST_R_SME_WHV0_SMEWHV0_MASK)
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/*! @} */
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/*! @name R_SME_WHV1 - BIST SME WHV Setting 1 Register */
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/*! @{ */
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#define FMUTEST_R_SME_WHV1_SMEWHV1_MASK (0xFFFFFFFFU)
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#define FMUTEST_R_SME_WHV1_SMEWHV1_SHIFT (0U)
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/*! SMEWHV1 - SME WHV Parameter Set 1 */
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#define FMUTEST_R_SME_WHV1_SMEWHV1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SME_WHV1_SMEWHV1_SHIFT)) & FMUTEST_R_SME_WHV1_SMEWHV1_MASK)
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/*! @} */
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/*! @name R_SMW_SETTING2 - BIST SMW Setting 2 Register */
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/*! @{ */
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#define FMUTEST_R_SMW_SETTING2_SMWPARM2_MASK (0x1FFFFFFFU)
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#define FMUTEST_R_SMW_SETTING2_SMWPARM2_SHIFT (0U)
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/*! SMWPARM2 - SMW Parameter Set 2 */
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#define FMUTEST_R_SMW_SETTING2_SMWPARM2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING2_SMWPARM2_SHIFT)) & FMUTEST_R_SMW_SETTING2_SMWPARM2_MASK)
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/*! @} */
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/*! @name R_D_MISR0 - BIST DIN MISR 0 Register */
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/*! @{ */
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#define FMUTEST_R_D_MISR0_DATASIG0_MASK (0xFFFFFFFFU)
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#define FMUTEST_R_D_MISR0_DATASIG0_SHIFT (0U)
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/*! DATASIG0 - Data Signature */
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#define FMUTEST_R_D_MISR0_DATASIG0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_D_MISR0_DATASIG0_SHIFT)) & FMUTEST_R_D_MISR0_DATASIG0_MASK)
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/*! @} */
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/*! @name R_A_MISR0 - BIST Address MISR 0 Register */
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/*! @{ */
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#define FMUTEST_R_A_MISR0_ADRSIG0_MASK (0xFFFFFFFFU)
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#define FMUTEST_R_A_MISR0_ADRSIG0_SHIFT (0U)
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/*! ADRSIG0 - Address Signature */
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#define FMUTEST_R_A_MISR0_ADRSIG0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_A_MISR0_ADRSIG0_SHIFT)) & FMUTEST_R_A_MISR0_ADRSIG0_MASK)
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/*! @} */
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/*! @name R_C_MISR0 - BIST Control MISR 0 Register */
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/*! @{ */
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#define FMUTEST_R_C_MISR0_CTRLSIG0_MASK (0xFFFFFFFFU)
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#define FMUTEST_R_C_MISR0_CTRLSIG0_SHIFT (0U)
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/*! CTRLSIG0 - Control Signature */
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#define FMUTEST_R_C_MISR0_CTRLSIG0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_C_MISR0_CTRLSIG0_SHIFT)) & FMUTEST_R_C_MISR0_CTRLSIG0_MASK)
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/*! @} */
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/*! @name R_SMW_SETTING3 - BIST SMW Setting 3 Register */
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/*! @{ */
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#define FMUTEST_R_SMW_SETTING3_SMWPARM3_MASK (0x1FFFFU)
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#define FMUTEST_R_SMW_SETTING3_SMWPARM3_SHIFT (0U)
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/*! SMWPARM3 - SMW Parameter Set 3 */
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#define FMUTEST_R_SMW_SETTING3_SMWPARM3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING3_SMWPARM3_SHIFT)) & FMUTEST_R_SMW_SETTING3_SMWPARM3_MASK)
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/*! @} */
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/*! @name R_DATA_CTRL1 - BIST Data Control 1 Register */
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/*! @{ */
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#define FMUTEST_R_DATA_CTRL1_DATA1_MASK (0xFFFFFFFFU)
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#define FMUTEST_R_DATA_CTRL1_DATA1_SHIFT (0U)
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/*! DATA1 - BIST Data 1 Low */
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#define FMUTEST_R_DATA_CTRL1_DATA1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL1_DATA1_SHIFT)) & FMUTEST_R_DATA_CTRL1_DATA1_MASK)
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/*! @} */
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/*! @name R_DATA_CTRL2 - BIST Data Control 2 Register */
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/*! @{ */
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#define FMUTEST_R_DATA_CTRL2_DATA2_MASK (0xFFFFFFFFU)
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#define FMUTEST_R_DATA_CTRL2_DATA2_SHIFT (0U)
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/*! DATA2 - BIST Data 2 Low */
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#define FMUTEST_R_DATA_CTRL2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL2_DATA2_SHIFT)) & FMUTEST_R_DATA_CTRL2_DATA2_MASK)
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/*! @} */
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/*! @name R_DATA_CTRL3 - BIST Data Control 3 Register */
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/*! @{ */
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#define FMUTEST_R_DATA_CTRL3_DATA3_MASK (0xFFFFFFFFU)
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#define FMUTEST_R_DATA_CTRL3_DATA3_SHIFT (0U)
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/*! DATA3 - BIST Data 3 Low */
|
|
#define FMUTEST_R_DATA_CTRL3_DATA3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL3_DATA3_SHIFT)) & FMUTEST_R_DATA_CTRL3_DATA3_MASK)
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/*! @} */
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/*! @name R_REPAIR0_0 - BIST Repair 0 for Block 0 Register */
|
|
/*! @{ */
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|
|
#define FMUTEST_R_REPAIR0_0_RDIS0_0_MASK (0x1U)
|
|
#define FMUTEST_R_REPAIR0_0_RDIS0_0_SHIFT (0U)
|
|
/*! RDIS0_0 - Control Repair 0 in Block 0.
|
|
* 0b0..Repair address is valid
|
|
* 0b1..Repair address is not valid
|
|
*/
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|
#define FMUTEST_R_REPAIR0_0_RDIS0_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR0_0_RDIS0_0_SHIFT)) & FMUTEST_R_REPAIR0_0_RDIS0_0_MASK)
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#define FMUTEST_R_REPAIR0_0_RADR0_0_MASK (0x1FEU)
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#define FMUTEST_R_REPAIR0_0_RADR0_0_SHIFT (1U)
|
|
/*! RADR0_0 - XADR for Repair 0 in Block 0 */
|
|
#define FMUTEST_R_REPAIR0_0_RADR0_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR0_0_RADR0_0_SHIFT)) & FMUTEST_R_REPAIR0_0_RADR0_0_MASK)
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|
/*! @} */
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/*! @name R_REPAIR0_1 - BIST Repair 1 Block 0 Register */
|
|
/*! @{ */
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#define FMUTEST_R_REPAIR0_1_RDIS0_1_MASK (0x1U)
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#define FMUTEST_R_REPAIR0_1_RDIS0_1_SHIFT (0U)
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/*! RDIS0_1 - Control Repair 1 in Block 0.
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* 0b0..Repair address is valid
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* 0b1..Repair address is not valid
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*/
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#define FMUTEST_R_REPAIR0_1_RDIS0_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR0_1_RDIS0_1_SHIFT)) & FMUTEST_R_REPAIR0_1_RDIS0_1_MASK)
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#define FMUTEST_R_REPAIR0_1_RADR0_1_MASK (0x1FEU)
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#define FMUTEST_R_REPAIR0_1_RADR0_1_SHIFT (1U)
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/*! RADR0_1 - XADR for Repair 1 in Block 0. */
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#define FMUTEST_R_REPAIR0_1_RADR0_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR0_1_RADR0_1_SHIFT)) & FMUTEST_R_REPAIR0_1_RADR0_1_MASK)
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/*! @} */
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/*! @name R_REPAIR1_0 - BIST Repair 0 Block 1 Register */
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/*! @{ */
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#define FMUTEST_R_REPAIR1_0_RDIS1_0_MASK (0x1U)
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#define FMUTEST_R_REPAIR1_0_RDIS1_0_SHIFT (0U)
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/*! RDIS1_0 - Control Repair 0 in Block 1.
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* 0b0..Repair address is valid
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* 0b1..Repair address is not valid
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*/
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#define FMUTEST_R_REPAIR1_0_RDIS1_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR1_0_RDIS1_0_SHIFT)) & FMUTEST_R_REPAIR1_0_RDIS1_0_MASK)
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#define FMUTEST_R_REPAIR1_0_RADR1_0_MASK (0x1FEU)
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#define FMUTEST_R_REPAIR1_0_RADR1_0_SHIFT (1U)
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/*! RADR1_0 - XADR for Repair 0 in Block 1. */
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#define FMUTEST_R_REPAIR1_0_RADR1_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR1_0_RADR1_0_SHIFT)) & FMUTEST_R_REPAIR1_0_RADR1_0_MASK)
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/*! @} */
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/*! @name R_REPAIR1_1 - BIST Repair 1 Block 1 Register */
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/*! @{ */
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#define FMUTEST_R_REPAIR1_1_RDIS1_1_MASK (0x1U)
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#define FMUTEST_R_REPAIR1_1_RDIS1_1_SHIFT (0U)
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/*! RDIS1_1 - Control Repair 1 in Block 1.
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* 0b0..Repair address is valid
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* 0b1..Repair address is not valid
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*/
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#define FMUTEST_R_REPAIR1_1_RDIS1_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR1_1_RDIS1_1_SHIFT)) & FMUTEST_R_REPAIR1_1_RDIS1_1_MASK)
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#define FMUTEST_R_REPAIR1_1_RADR1_1_MASK (0x1FEU)
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#define FMUTEST_R_REPAIR1_1_RADR1_1_SHIFT (1U)
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/*! RADR1_1 - XADR for Repair 1 in Block 1. */
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#define FMUTEST_R_REPAIR1_1_RADR1_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR1_1_RADR1_1_SHIFT)) & FMUTEST_R_REPAIR1_1_RADR1_1_MASK)
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/*! @} */
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/*! @name R_DATA_CTRL0_EX - BIST Data Control 0 Extension Register */
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/*! @{ */
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#define FMUTEST_R_DATA_CTRL0_EX_DATA0X_MASK (0x7U)
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#define FMUTEST_R_DATA_CTRL0_EX_DATA0X_SHIFT (0U)
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/*! DATA0X - BIST Data 0 High */
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#define FMUTEST_R_DATA_CTRL0_EX_DATA0X(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL0_EX_DATA0X_SHIFT)) & FMUTEST_R_DATA_CTRL0_EX_DATA0X_MASK)
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/*! @} */
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/*! @name R_TIMER_CTRL_EX - BIST Timer Control Extension Register */
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/*! @{ */
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#define FMUTEST_R_TIMER_CTRL_EX_TLVSDLY_H_MASK (0x7U)
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#define FMUTEST_R_TIMER_CTRL_EX_TLVSDLY_H_SHIFT (0U)
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/*! TLVSDLY_H - Tlvs Time Delay Scalar High */
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#define FMUTEST_R_TIMER_CTRL_EX_TLVSDLY_H(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_EX_TLVSDLY_H_SHIFT)) & FMUTEST_R_TIMER_CTRL_EX_TLVSDLY_H_MASK)
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/*! @} */
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/*! @name R_DOUT_QUERY1 - BIST DOUT Query 1 Register */
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/*! @{ */
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#define FMUTEST_R_DOUT_QUERY1_DOUT_MASK (0x7U)
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#define FMUTEST_R_DOUT_QUERY1_DOUT_SHIFT (0U)
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/*! DOUT - Failing DOUT High */
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#define FMUTEST_R_DOUT_QUERY1_DOUT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DOUT_QUERY1_DOUT_SHIFT)) & FMUTEST_R_DOUT_QUERY1_DOUT_MASK)
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/*! @} */
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/*! @name R_D_MISR1 - BIST DIN MISR 1 Register */
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/*! @{ */
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#define FMUTEST_R_D_MISR1_DATASIG1_MASK (0xFFU)
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#define FMUTEST_R_D_MISR1_DATASIG1_SHIFT (0U)
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/*! DATASIG1 - MISR Data Signature High */
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#define FMUTEST_R_D_MISR1_DATASIG1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_D_MISR1_DATASIG1_SHIFT)) & FMUTEST_R_D_MISR1_DATASIG1_MASK)
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/*! @} */
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/*! @name R_A_MISR1 - BIST Address MISR 1 Register */
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/*! @{ */
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#define FMUTEST_R_A_MISR1_ADRSIG1_MASK (0xFFU)
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#define FMUTEST_R_A_MISR1_ADRSIG1_SHIFT (0U)
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/*! ADRSIG1 - MISR Address Signature High */
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#define FMUTEST_R_A_MISR1_ADRSIG1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_A_MISR1_ADRSIG1_SHIFT)) & FMUTEST_R_A_MISR1_ADRSIG1_MASK)
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/*! @} */
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/*! @name R_C_MISR1 - BIST Control MISR 1 Register */
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/*! @{ */
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#define FMUTEST_R_C_MISR1_CTRLSIG1_MASK (0xFFU)
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#define FMUTEST_R_C_MISR1_CTRLSIG1_SHIFT (0U)
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/*! CTRLSIG1 - MISR Control Signature High */
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#define FMUTEST_R_C_MISR1_CTRLSIG1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_C_MISR1_CTRLSIG1_SHIFT)) & FMUTEST_R_C_MISR1_CTRLSIG1_MASK)
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/*! @} */
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/*! @name R_DATA_CTRL1_EX - BIST Data Control 1 Extension Register */
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/*! @{ */
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#define FMUTEST_R_DATA_CTRL1_EX_DATA1X_MASK (0x7U)
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#define FMUTEST_R_DATA_CTRL1_EX_DATA1X_SHIFT (0U)
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/*! DATA1X - BIST Data 1 High */
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|
#define FMUTEST_R_DATA_CTRL1_EX_DATA1X(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL1_EX_DATA1X_SHIFT)) & FMUTEST_R_DATA_CTRL1_EX_DATA1X_MASK)
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/*! @} */
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/*! @name R_DATA_CTRL2_EX - BIST Data Control 2 Extension Register */
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/*! @{ */
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#define FMUTEST_R_DATA_CTRL2_EX_DATA2X_MASK (0x7U)
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#define FMUTEST_R_DATA_CTRL2_EX_DATA2X_SHIFT (0U)
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/*! DATA2X - BIST Data 2 High */
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#define FMUTEST_R_DATA_CTRL2_EX_DATA2X(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL2_EX_DATA2X_SHIFT)) & FMUTEST_R_DATA_CTRL2_EX_DATA2X_MASK)
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/*! @} */
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/*! @name R_DATA_CTRL3_EX - BIST Data Control 3 Extension Register */
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/*! @{ */
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#define FMUTEST_R_DATA_CTRL3_EX_DATA3X_MASK (0x7U)
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#define FMUTEST_R_DATA_CTRL3_EX_DATA3X_SHIFT (0U)
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/*! DATA3X - BIST Data 3 High */
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#define FMUTEST_R_DATA_CTRL3_EX_DATA3X(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL3_EX_DATA3X_SHIFT)) & FMUTEST_R_DATA_CTRL3_EX_DATA3X_MASK)
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/*! @} */
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/*! @name SMW_TIMER_OPTION - SMW Timer Option Register */
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/*! @{ */
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#define FMUTEST_SMW_TIMER_OPTION_SMW_CDIVL_MASK (0xFFU)
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#define FMUTEST_SMW_TIMER_OPTION_SMW_CDIVL_SHIFT (0U)
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/*! SMW_CDIVL - Clock Divide Scalar for Long Pulse */
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#define FMUTEST_SMW_TIMER_OPTION_SMW_CDIVL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_TIMER_OPTION_SMW_CDIVL_SHIFT)) & FMUTEST_SMW_TIMER_OPTION_SMW_CDIVL_MASK)
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#define FMUTEST_SMW_TIMER_OPTION_SMW_TVFY_MASK (0x1F00U)
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#define FMUTEST_SMW_TIMER_OPTION_SMW_TVFY_SHIFT (8U)
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/*! SMW_TVFY - Timer Adjust for Verify */
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#define FMUTEST_SMW_TIMER_OPTION_SMW_TVFY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_TIMER_OPTION_SMW_TVFY_SHIFT)) & FMUTEST_SMW_TIMER_OPTION_SMW_TVFY_MASK)
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/*! @} */
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/*! @name SMW_SETTING_OPTION0 - SMW Setting Option 0 Register */
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/*! @{ */
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#define FMUTEST_SMW_SETTING_OPTION0_MV_INIT_MASK (0x1C000U)
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#define FMUTEST_SMW_SETTING_OPTION0_MV_INIT_SHIFT (14U)
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/*! MV_INIT - Medium Voltage Level Select Initial */
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#define FMUTEST_SMW_SETTING_OPTION0_MV_INIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_MV_INIT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_MV_INIT_MASK)
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#define FMUTEST_SMW_SETTING_OPTION0_MV_END_MASK (0xE0000U)
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#define FMUTEST_SMW_SETTING_OPTION0_MV_END_SHIFT (17U)
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/*! MV_END - Medium Voltage Level Select Final */
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#define FMUTEST_SMW_SETTING_OPTION0_MV_END(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_MV_END_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_MV_END_MASK)
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#define FMUTEST_SMW_SETTING_OPTION0_MV_MISC_MASK (0xF00000U)
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#define FMUTEST_SMW_SETTING_OPTION0_MV_MISC_SHIFT (20U)
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/*! MV_MISC - Medium Voltage Control Misc */
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#define FMUTEST_SMW_SETTING_OPTION0_MV_MISC(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_MV_MISC_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_MV_MISC_MASK)
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#define FMUTEST_SMW_SETTING_OPTION0_IPGM_INIT_MASK (0x3000000U)
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#define FMUTEST_SMW_SETTING_OPTION0_IPGM_INIT_SHIFT (24U)
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/*! IPGM_INIT - Program Current Control Initial */
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#define FMUTEST_SMW_SETTING_OPTION0_IPGM_INIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_IPGM_INIT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_IPGM_INIT_MASK)
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#define FMUTEST_SMW_SETTING_OPTION0_IPGM_END_MASK (0xC000000U)
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#define FMUTEST_SMW_SETTING_OPTION0_IPGM_END_SHIFT (26U)
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|
/*! IPGM_END - Program Current Control Final */
|
|
#define FMUTEST_SMW_SETTING_OPTION0_IPGM_END(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_IPGM_END_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_IPGM_END_MASK)
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#define FMUTEST_SMW_SETTING_OPTION0_IPGM_MISC_MASK (0x70000000U)
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#define FMUTEST_SMW_SETTING_OPTION0_IPGM_MISC_SHIFT (28U)
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/*! IPGM_MISC - Program Current Control Misc */
|
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#define FMUTEST_SMW_SETTING_OPTION0_IPGM_MISC(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_IPGM_MISC_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_IPGM_MISC_MASK)
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/*! @} */
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/*! @name SMW_SETTING_OPTION2 - SMW Setting Option 2 Register */
|
|
/*! @{ */
|
|
|
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#define FMUTEST_SMW_SETTING_OPTION2_THVS_CTRL_MASK (0x7U)
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#define FMUTEST_SMW_SETTING_OPTION2_THVS_CTRL_SHIFT (0U)
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/*! THVS_CTRL - Thvs control */
|
|
#define FMUTEST_SMW_SETTING_OPTION2_THVS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_THVS_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_THVS_CTRL_MASK)
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#define FMUTEST_SMW_SETTING_OPTION2_TRCV_CTRL_MASK (0x38U)
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#define FMUTEST_SMW_SETTING_OPTION2_TRCV_CTRL_SHIFT (3U)
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/*! TRCV_CTRL - Trcv Control */
|
|
#define FMUTEST_SMW_SETTING_OPTION2_TRCV_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_TRCV_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_TRCV_CTRL_MASK)
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#define FMUTEST_SMW_SETTING_OPTION2_XTRA_ERS_MASK (0xC0U)
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#define FMUTEST_SMW_SETTING_OPTION2_XTRA_ERS_SHIFT (6U)
|
|
/*! XTRA_ERS - Number of Post Shots for SME */
|
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#define FMUTEST_SMW_SETTING_OPTION2_XTRA_ERS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_XTRA_ERS_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_XTRA_ERS_MASK)
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#define FMUTEST_SMW_SETTING_OPTION2_XTRA_PGM_MASK (0x300U)
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#define FMUTEST_SMW_SETTING_OPTION2_XTRA_PGM_SHIFT (8U)
|
|
/*! XTRA_PGM - Number of Post Shots for SMP */
|
|
#define FMUTEST_SMW_SETTING_OPTION2_XTRA_PGM(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_XTRA_PGM_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_XTRA_PGM_MASK)
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#define FMUTEST_SMW_SETTING_OPTION2_WHV_CNTR_MASK (0x3FC00U)
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#define FMUTEST_SMW_SETTING_OPTION2_WHV_CNTR_SHIFT (10U)
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/*! WHV_CNTR - WHV Counter */
|
|
#define FMUTEST_SMW_SETTING_OPTION2_WHV_CNTR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_WHV_CNTR_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_WHV_CNTR_MASK)
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#define FMUTEST_SMW_SETTING_OPTION2_POST_TERS_MASK (0x1C0000U)
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#define FMUTEST_SMW_SETTING_OPTION2_POST_TERS_SHIFT (18U)
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/*! POST_TERS - Post Ters Time
|
|
* 0b000..50 usec
|
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* 0b001..100 usec
|
|
* 0b010..200 usec
|
|
* 0b011..300 usec
|
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* 0b100..500 usec
|
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* 0b101..1 msec
|
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* 0b110..1.5 msec
|
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* 0b111..2 msec
|
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*/
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#define FMUTEST_SMW_SETTING_OPTION2_POST_TERS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_POST_TERS_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_POST_TERS_MASK)
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#define FMUTEST_SMW_SETTING_OPTION2_POST_TPGM_MASK (0x600000U)
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#define FMUTEST_SMW_SETTING_OPTION2_POST_TPGM_SHIFT (21U)
|
|
/*! POST_TPGM - Post Tpgm Time
|
|
* 0b00..1 usec
|
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* 0b01..2 usec
|
|
* 0b10..4 usec
|
|
* 0b11..8 usec
|
|
*/
|
|
#define FMUTEST_SMW_SETTING_OPTION2_POST_TPGM(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_POST_TPGM_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_POST_TPGM_MASK)
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#define FMUTEST_SMW_SETTING_OPTION2_VFY_OPT_MASK (0x1800000U)
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#define FMUTEST_SMW_SETTING_OPTION2_VFY_OPT_SHIFT (23U)
|
|
/*! VFY_OPT - Verify Option
|
|
* 0b00..Skip verify for post shot only, verify for all other shots
|
|
* 0b01..Skip verify for the 1st and post shots
|
|
* 0b10..Skip the 1st, 2nd, and post shots
|
|
* 0b11..Skip verify for all shots
|
|
*/
|
|
#define FMUTEST_SMW_SETTING_OPTION2_VFY_OPT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_VFY_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_VFY_OPT_MASK)
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#define FMUTEST_SMW_SETTING_OPTION2_TPGM_OPT_MASK (0x6000000U)
|
|
#define FMUTEST_SMW_SETTING_OPTION2_TPGM_OPT_SHIFT (25U)
|
|
/*! TPGM_OPT - Tpgm Option
|
|
* 0b00..Fixed Tpgm for all shots, except post shot
|
|
* 0b01..Increase Tpgm option by 1 for each loop until Tpgm reaches 4 usec
|
|
* 0b10..Increase Tpgm option by 1 for each loop until Tpgm reaches 8 usec
|
|
* 0b11..Unused
|
|
*/
|
|
#define FMUTEST_SMW_SETTING_OPTION2_TPGM_OPT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_TPGM_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_TPGM_OPT_MASK)
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|
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#define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK (0x8000000U)
|
|
#define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_SHIFT (27U)
|
|
/*! MASK0_OPT - MASK0_OPT
|
|
* 0b0..Mask programmed bits passing PV until extra shot
|
|
* 0b1..Always program bits even if they pass PV
|
|
*/
|
|
#define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK)
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#define FMUTEST_SMW_SETTING_OPTION2_DIS_PRER_MASK (0x10000000U)
|
|
#define FMUTEST_SMW_SETTING_OPTION2_DIS_PRER_SHIFT (28U)
|
|
/*! DIS_PRER - Disable pre-PV Read before First Program Shot
|
|
* 0b0..Enable pre-PV read before first program shot
|
|
* 0b1..Disable pre-PV read before first program shot
|
|
*/
|
|
#define FMUTEST_SMW_SETTING_OPTION2_DIS_PRER(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_DIS_PRER_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_DIS_PRER_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SMW_SETTING_OPTION3 - SMW Setting Option 3 Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_SMW_SETTING_OPTION3_HEM_WHV_CNTR_MASK (0xFFU)
|
|
#define FMUTEST_SMW_SETTING_OPTION3_HEM_WHV_CNTR_SHIFT (0U)
|
|
/*! HEM_WHV_CNTR - WHV_COUNTER for HEM-erase Cycle */
|
|
#define FMUTEST_SMW_SETTING_OPTION3_HEM_WHV_CNTR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION3_HEM_WHV_CNTR_SHIFT)) & FMUTEST_SMW_SETTING_OPTION3_HEM_WHV_CNTR_MASK)
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#define FMUTEST_SMW_SETTING_OPTION3_HEM_MAX_ERS_MASK (0x1FF00U)
|
|
#define FMUTEST_SMW_SETTING_OPTION3_HEM_MAX_ERS_SHIFT (8U)
|
|
/*! HEM_MAX_ERS - HEM Max Erase Shot Count */
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#define FMUTEST_SMW_SETTING_OPTION3_HEM_MAX_ERS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION3_HEM_MAX_ERS_SHIFT)) & FMUTEST_SMW_SETTING_OPTION3_HEM_MAX_ERS_MASK)
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/*! @} */
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/*! @name SMW_SMP_WHV_OPTION0 - SMW SMP WHV Option 0 Register */
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/*! @{ */
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#define FMUTEST_SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0_MASK (0xFFFFFFFFU)
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#define FMUTEST_SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0_SHIFT (0U)
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/*! SMP_WHV_OPT0 - Smart Program WHV Option Low */
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#define FMUTEST_SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0_SHIFT)) & FMUTEST_SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0_MASK)
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/*! @} */
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/*! @name SMW_SME_WHV_OPTION0 - SMW SME WHV Option 0 Register */
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/*! @{ */
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#define FMUTEST_SMW_SME_WHV_OPTION0_SME_WHV_OPT0_MASK (0xFFFFFFFFU)
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#define FMUTEST_SMW_SME_WHV_OPTION0_SME_WHV_OPT0_SHIFT (0U)
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/*! SME_WHV_OPT0 - Smart Erase WHV Option Low */
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#define FMUTEST_SMW_SME_WHV_OPTION0_SME_WHV_OPT0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SME_WHV_OPTION0_SME_WHV_OPT0_SHIFT)) & FMUTEST_SMW_SME_WHV_OPTION0_SME_WHV_OPT0_MASK)
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/*! @} */
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/*! @name SMW_SETTING_OPTION1 - SMW Setting Option 1 Register */
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/*! @{ */
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#define FMUTEST_SMW_SETTING_OPTION1_TERS_CTRL0_MASK (0x7U)
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#define FMUTEST_SMW_SETTING_OPTION1_TERS_CTRL0_SHIFT (0U)
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/*! TERS_CTRL0 - Ters Control
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* 0b000..50 usec
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* 0b001..100 usec
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* 0b010..200 usec
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* 0b011..300 usec
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* 0b100..500 usec
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* 0b101..1 msec
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* 0b110..1.5 msec
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* 0b111..2 msec
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*/
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#define FMUTEST_SMW_SETTING_OPTION1_TERS_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_TERS_CTRL0_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_TERS_CTRL0_MASK)
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#define FMUTEST_SMW_SETTING_OPTION1_TPGM_CTRL_MASK (0x18U)
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#define FMUTEST_SMW_SETTING_OPTION1_TPGM_CTRL_SHIFT (3U)
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/*! TPGM_CTRL - Tpgm Control
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* 0b00..1 usec
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* 0b01..2 usec
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* 0b10..4 usec
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* 0b11..8 usec
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*/
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#define FMUTEST_SMW_SETTING_OPTION1_TPGM_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_TPGM_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_TPGM_CTRL_MASK)
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#define FMUTEST_SMW_SETTING_OPTION1_TNVS_CTRL_MASK (0xE0U)
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#define FMUTEST_SMW_SETTING_OPTION1_TNVS_CTRL_SHIFT (5U)
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/*! TNVS_CTRL - Tnvs Control
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* 0b000..5 usec
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* 0b001..8 usec
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* 0b010..11 usec
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* 0b011..14 usec
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* 0b100..17 usec
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* 0b101..20 usec
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* 0b110..23 usec
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* 0b111..26 usec
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*/
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#define FMUTEST_SMW_SETTING_OPTION1_TNVS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_TNVS_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_TNVS_CTRL_MASK)
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#define FMUTEST_SMW_SETTING_OPTION1_TNVH_CTRL_MASK (0x700U)
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#define FMUTEST_SMW_SETTING_OPTION1_TNVH_CTRL_SHIFT (8U)
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/*! TNVH_CTRL - Tnvh Control
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* 0b000..2 usec
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* 0b001..2.5 usec
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* 0b010..3 usec
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* 0b011..3.5 usec
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* 0b100..4 usec
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* 0b101..4.5 usec
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* 0b110..5 usec
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* 0b111..5.5 usec
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*/
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#define FMUTEST_SMW_SETTING_OPTION1_TNVH_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_TNVH_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_TNVH_CTRL_MASK)
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#define FMUTEST_SMW_SETTING_OPTION1_TPGS_CTRL_MASK (0x3800U)
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#define FMUTEST_SMW_SETTING_OPTION1_TPGS_CTRL_SHIFT (11U)
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/*! TPGS_CTRL - Tpgs Control
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* 0b000..1 usec
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* 0b001..2 usec
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* 0b010..3 usec
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* 0b011..4 usec
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* 0b100..5 usec
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* 0b101..6 usec
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* 0b110..7 usec
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* 0b111..8 usec
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*/
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#define FMUTEST_SMW_SETTING_OPTION1_TPGS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_TPGS_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_TPGS_CTRL_MASK)
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#define FMUTEST_SMW_SETTING_OPTION1_MAX_ERASE_MASK (0x7FC000U)
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#define FMUTEST_SMW_SETTING_OPTION1_MAX_ERASE_SHIFT (14U)
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/*! MAX_ERASE - Number of Erase Shots */
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#define FMUTEST_SMW_SETTING_OPTION1_MAX_ERASE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_MAX_ERASE_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_MAX_ERASE_MASK)
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#define FMUTEST_SMW_SETTING_OPTION1_MAX_PROG_MASK (0xF800000U)
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#define FMUTEST_SMW_SETTING_OPTION1_MAX_PROG_SHIFT (23U)
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/*! MAX_PROG - Number of Program Shots */
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#define FMUTEST_SMW_SETTING_OPTION1_MAX_PROG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_MAX_PROG_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_MAX_PROG_MASK)
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/*! @} */
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/*! @name SMW_SMP_WHV_OPTION1 - SMW SMP WHV Option 1 Register */
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/*! @{ */
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#define FMUTEST_SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1_MASK (0xFFFFFFFFU)
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#define FMUTEST_SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1_SHIFT (0U)
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/*! SMP_WHV_OPT1 - Smart Program WHV Option High */
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#define FMUTEST_SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1_SHIFT)) & FMUTEST_SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1_MASK)
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/*! @} */
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/*! @name SMW_SME_WHV_OPTION1 - SMW SME WHV Option 1 Register */
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/*! @{ */
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#define FMUTEST_SMW_SME_WHV_OPTION1_SME_WHV_OPT1_MASK (0xFFFFFFFFU)
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#define FMUTEST_SMW_SME_WHV_OPTION1_SME_WHV_OPT1_SHIFT (0U)
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/*! SME_WHV_OPT1 - Smart Erase WHV Option High */
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#define FMUTEST_SMW_SME_WHV_OPTION1_SME_WHV_OPT1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SME_WHV_OPTION1_SME_WHV_OPT1_SHIFT)) & FMUTEST_SMW_SME_WHV_OPTION1_SME_WHV_OPT1_MASK)
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/*! @} */
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/*! @name REPAIR0_0 - FMU Repair 0 Block 0 Register */
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|
/*! @{ */
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#define FMUTEST_REPAIR0_0_RDIS0_0_MASK (0x1U)
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#define FMUTEST_REPAIR0_0_RDIS0_0_SHIFT (0U)
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/*! RDIS0_0 - RDIS0_0
|
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* 0b0..Repair address is valid
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* 0b1..Repair address is not valid
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*/
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#define FMUTEST_REPAIR0_0_RDIS0_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR0_0_RDIS0_0_SHIFT)) & FMUTEST_REPAIR0_0_RDIS0_0_MASK)
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#define FMUTEST_REPAIR0_0_RADR0_0_MASK (0x1FEU)
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#define FMUTEST_REPAIR0_0_RADR0_0_SHIFT (1U)
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/*! RADR0_0 - RADR0_0 */
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|
#define FMUTEST_REPAIR0_0_RADR0_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR0_0_RADR0_0_SHIFT)) & FMUTEST_REPAIR0_0_RADR0_0_MASK)
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/*! @} */
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/*! @name REPAIR0_1 - FMU Repair 1 Block 0 Register */
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|
/*! @{ */
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#define FMUTEST_REPAIR0_1_RDIS0_1_MASK (0x1U)
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#define FMUTEST_REPAIR0_1_RDIS0_1_SHIFT (0U)
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/*! RDIS0_1 - RDIS0_1
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|
* 0b0..Repair address is valid
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* 0b1..Repair address is not valid
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|
*/
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|
#define FMUTEST_REPAIR0_1_RDIS0_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR0_1_RDIS0_1_SHIFT)) & FMUTEST_REPAIR0_1_RDIS0_1_MASK)
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#define FMUTEST_REPAIR0_1_RADR0_1_MASK (0x1FEU)
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#define FMUTEST_REPAIR0_1_RADR0_1_SHIFT (1U)
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|
/*! RADR0_1 - RADR0_1 */
|
|
#define FMUTEST_REPAIR0_1_RADR0_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR0_1_RADR0_1_SHIFT)) & FMUTEST_REPAIR0_1_RADR0_1_MASK)
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/*! @} */
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|
/*! @name REPAIR1_0 - FMU Repair 0 Block 1 Register */
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|
/*! @{ */
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|
#define FMUTEST_REPAIR1_0_RDIS1_0_MASK (0x1U)
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|
#define FMUTEST_REPAIR1_0_RDIS1_0_SHIFT (0U)
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|
/*! RDIS1_0 - RDIS1_0
|
|
* 0b0..Repair address is valid
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|
* 0b1..Repair address is not valid
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|
*/
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|
#define FMUTEST_REPAIR1_0_RDIS1_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR1_0_RDIS1_0_SHIFT)) & FMUTEST_REPAIR1_0_RDIS1_0_MASK)
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|
#define FMUTEST_REPAIR1_0_RADR1_0_MASK (0x1FEU)
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|
#define FMUTEST_REPAIR1_0_RADR1_0_SHIFT (1U)
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|
/*! RADR1_0 - RADR1_0 */
|
|
#define FMUTEST_REPAIR1_0_RADR1_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR1_0_RADR1_0_SHIFT)) & FMUTEST_REPAIR1_0_RADR1_0_MASK)
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|
/*! @} */
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|
/*! @name REPAIR1_1 - FMU Repair 1 Block 1 Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_REPAIR1_1_RDIS1_1_MASK (0x1U)
|
|
#define FMUTEST_REPAIR1_1_RDIS1_1_SHIFT (0U)
|
|
/*! RDIS1_1 - RDIS1_1
|
|
* 0b0..Repair address is valid
|
|
* 0b1..Repair address is not valid
|
|
*/
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|
#define FMUTEST_REPAIR1_1_RDIS1_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR1_1_RDIS1_1_SHIFT)) & FMUTEST_REPAIR1_1_RDIS1_1_MASK)
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|
#define FMUTEST_REPAIR1_1_RADR1_1_MASK (0x1FEU)
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|
#define FMUTEST_REPAIR1_1_RADR1_1_SHIFT (1U)
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|
/*! RADR1_1 - RADR1_1 */
|
|
#define FMUTEST_REPAIR1_1_RADR1_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR1_1_RADR1_1_SHIFT)) & FMUTEST_REPAIR1_1_RADR1_1_MASK)
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/*! @} */
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/*! @name SMW_HB_SIGNALS - SMW HB Signals Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_SMW_HB_SIGNALS_SMW_ARRAY_MASK (0x7U)
|
|
#define FMUTEST_SMW_HB_SIGNALS_SMW_ARRAY_SHIFT (0U)
|
|
/*! SMW_ARRAY - SMW Region Select
|
|
* 0b000..Main array
|
|
* 0b001..IFR space only or main (and REDEN space) with IFR space for mass erase
|
|
* 0b010..IFR1 space
|
|
* 0b100..REDEN space
|
|
*/
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|
#define FMUTEST_SMW_HB_SIGNALS_SMW_ARRAY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_SMW_ARRAY_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_SMW_ARRAY_MASK)
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#define FMUTEST_SMW_HB_SIGNALS_USER_IFREN1_MASK (0x8U)
|
|
#define FMUTEST_SMW_HB_SIGNALS_USER_IFREN1_SHIFT (3U)
|
|
/*! USER_IFREN1 - IFR1 Enable
|
|
* 0b0..IFREN1 input to the flash array is driven LOW
|
|
* 0b1..IFREN1 input to the flash array is driven HIGH
|
|
*/
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|
#define FMUTEST_SMW_HB_SIGNALS_USER_IFREN1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_IFREN1_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_IFREN1_MASK)
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|
#define FMUTEST_SMW_HB_SIGNALS_USER_PV_MASK (0x10U)
|
|
#define FMUTEST_SMW_HB_SIGNALS_USER_PV_SHIFT (4U)
|
|
/*! USER_PV - Program Verify
|
|
* 0b0..PV input to the flash array is driven LOW
|
|
* 0b1..PV input to the flash array is driven HIGH
|
|
*/
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|
#define FMUTEST_SMW_HB_SIGNALS_USER_PV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_PV_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_PV_MASK)
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|
#define FMUTEST_SMW_HB_SIGNALS_USER_EV_MASK (0x20U)
|
|
#define FMUTEST_SMW_HB_SIGNALS_USER_EV_SHIFT (5U)
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|
/*! USER_EV - Erase Verify
|
|
* 0b0..EV input to the flash array is driven LOW
|
|
* 0b1..EV input to the flash array is driven HIGH
|
|
*/
|
|
#define FMUTEST_SMW_HB_SIGNALS_USER_EV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_EV_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_EV_MASK)
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#define FMUTEST_SMW_HB_SIGNALS_USER_IFREN_MASK (0x40U)
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|
#define FMUTEST_SMW_HB_SIGNALS_USER_IFREN_SHIFT (6U)
|
|
/*! USER_IFREN - IFR Enable
|
|
* 0b0..IFREN input to the flash array is driven LOW
|
|
* 0b1..IFREN input to the flash array is driven HIGH
|
|
*/
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|
#define FMUTEST_SMW_HB_SIGNALS_USER_IFREN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_IFREN_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_IFREN_MASK)
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|
#define FMUTEST_SMW_HB_SIGNALS_USER_REDEN_MASK (0x80U)
|
|
#define FMUTEST_SMW_HB_SIGNALS_USER_REDEN_SHIFT (7U)
|
|
/*! USER_REDEN - Repair Read Enable
|
|
* 0b0..REDEN input to the flash array is driven LOW
|
|
* 0b1..REDEN input to the flash array is driven HIGH
|
|
*/
|
|
#define FMUTEST_SMW_HB_SIGNALS_USER_REDEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_REDEN_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_REDEN_MASK)
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|
#define FMUTEST_SMW_HB_SIGNALS_USER_HEM_MASK (0x100U)
|
|
#define FMUTEST_SMW_HB_SIGNALS_USER_HEM_SHIFT (8U)
|
|
/*! USER_HEM - High Endurance Enable
|
|
* 0b0..HEM input to SMW / BIST PIN_CTRL[24] is driven LOW
|
|
* 0b1..HEM input to SMW / BIST PIN_CTRL[24] is driven HIGH
|
|
*/
|
|
#define FMUTEST_SMW_HB_SIGNALS_USER_HEM(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_HEM_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_HEM_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name BIST_DUMP_CTRL - BIST Datadump Control Register */
|
|
/*! @{ */
|
|
|
|
#define FMUTEST_BIST_DUMP_CTRL_BIST_DONE_MASK (0x10000U)
|
|
#define FMUTEST_BIST_DUMP_CTRL_BIST_DONE_SHIFT (16U)
|
|
/*! BIST_DONE - BIST Done
|
|
* 0b0..The BIST (or data dump) is running
|
|
* 0b1..The BIST (or data dump) has completed
|
|
*/
|
|
#define FMUTEST_BIST_DUMP_CTRL_BIST_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_BIST_DONE_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_BIST_DONE_MASK)
|
|
|
|
#define FMUTEST_BIST_DUMP_CTRL_BIST_FAIL_MASK (0x20000U)
|
|
#define FMUTEST_BIST_DUMP_CTRL_BIST_FAIL_SHIFT (17U)
|
|
/*! BIST_FAIL - BIST Fail
|
|
* 0b0..The last BIST operation completed successfully (or could not fail)
|
|
* 0b1..The last BIST operation failed
|
|
*/
|
|
#define FMUTEST_BIST_DUMP_CTRL_BIST_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_BIST_FAIL_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_BIST_FAIL_MASK)
|
|
|
|
#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MASK (0x40000U)
|
|
#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_SHIFT (18U)
|
|
/*! DATADUMP - Data Dump Enable */
|
|
#define FMUTEST_BIST_DUMP_CTRL_DATADUMP(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_DATADUMP_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_DATADUMP_MASK)
|
|
|
|
#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_TRIG_MASK (0x80000U)
|
|
#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_TRIG_SHIFT (19U)
|
|
/*! DATADUMP_TRIG - Data Dump Trigger */
|
|
#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_TRIG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_DATADUMP_TRIG_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_DATADUMP_TRIG_MASK)
|
|
|
|
#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_PATT_MASK (0x300000U)
|
|
#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_PATT_SHIFT (20U)
|
|
/*! DATADUMP_PATT - Data Dump Pattern Select
|
|
* 0b00..All ones
|
|
* 0b01..All zeroes
|
|
* 0b10..Checkerboard
|
|
* 0b11..Inverse checkerboard
|
|
*/
|
|
#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_PATT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_DATADUMP_PATT_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_DATADUMP_PATT_MASK)
|
|
|
|
#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGEN_MASK (0x400000U)
|
|
#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGEN_SHIFT (22U)
|
|
/*! DATADUMP_MRGEN - Data Dump Margin Enable
|
|
* 0b0..Normal read pulse shape
|
|
* 0b1..Margin read pulse shape
|
|
*/
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#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGEN_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGEN_MASK)
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#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGTYPE_MASK (0x800000U)
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#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGTYPE_SHIFT (23U)
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/*! DATADUMP_MRGTYPE - Data Dump Margin Type
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* 0b0..DIN method used
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* 0b1..TM method used
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*/
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#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGTYPE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGTYPE_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGTYPE_MASK)
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/*! @} */
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/*! @name ATX_PIN_CTRL - ATX Pin Control Register */
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/*! @{ */
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#define FMUTEST_ATX_PIN_CTRL_TM_TO_ATX_MASK (0xFFU)
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#define FMUTEST_ATX_PIN_CTRL_TM_TO_ATX_SHIFT (0U)
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/*! TM_TO_ATX - TM to ATX
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* 0b00000001..TM[0] to ATX0
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* 0b00000010..TM[1] to ATX0
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* 0b00000100..TM[2] to ATX0
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* 0b00001000..TM[3] to ATX0
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* 0b00010000..TM[0] to ATX1
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* 0b00100000..TM[1] to ATX1
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* 0b01000000..TM[2] to ATX1
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* 0b10000000..TM[3] to ATX1
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*/
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#define FMUTEST_ATX_PIN_CTRL_TM_TO_ATX(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_ATX_PIN_CTRL_TM_TO_ATX_SHIFT)) & FMUTEST_ATX_PIN_CTRL_TM_TO_ATX_MASK)
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/*! @} */
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/*! @name FAILCNT - Fail Count Register */
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/*! @{ */
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#define FMUTEST_FAILCNT_FAILCNT_MASK (0xFFFFFFFFU)
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#define FMUTEST_FAILCNT_FAILCNT_SHIFT (0U)
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/*! FAILCNT - Fail Count */
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#define FMUTEST_FAILCNT_FAILCNT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FAILCNT_FAILCNT_SHIFT)) & FMUTEST_FAILCNT_FAILCNT_MASK)
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/*! @} */
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/*! @name PGM_PULSE_CNT0 - Block 0 Program Pulse Count Register */
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/*! @{ */
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#define FMUTEST_PGM_PULSE_CNT0_PGM_CNT0_MASK (0xFFFFFFFFU)
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#define FMUTEST_PGM_PULSE_CNT0_PGM_CNT0_SHIFT (0U)
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/*! PGM_CNT0 - Program Pulse Count */
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#define FMUTEST_PGM_PULSE_CNT0_PGM_CNT0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PGM_PULSE_CNT0_PGM_CNT0_SHIFT)) & FMUTEST_PGM_PULSE_CNT0_PGM_CNT0_MASK)
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/*! @} */
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/*! @name PGM_PULSE_CNT1 - Block 1 Program Pulse Count Register */
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/*! @{ */
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#define FMUTEST_PGM_PULSE_CNT1_PGM_CNT1_MASK (0xFFFFFFFFU)
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#define FMUTEST_PGM_PULSE_CNT1_PGM_CNT1_SHIFT (0U)
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/*! PGM_CNT1 - Program Pulse Count */
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#define FMUTEST_PGM_PULSE_CNT1_PGM_CNT1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PGM_PULSE_CNT1_PGM_CNT1_SHIFT)) & FMUTEST_PGM_PULSE_CNT1_PGM_CNT1_MASK)
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/*! @} */
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/*! @name ERS_PULSE_CNT - Erase Pulse Count Register */
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/*! @{ */
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#define FMUTEST_ERS_PULSE_CNT_ERS_CNT0_MASK (0xFFFFU)
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#define FMUTEST_ERS_PULSE_CNT_ERS_CNT0_SHIFT (0U)
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/*! ERS_CNT0 - Block 0 Erase Pulse Count */
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#define FMUTEST_ERS_PULSE_CNT_ERS_CNT0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_ERS_PULSE_CNT_ERS_CNT0_SHIFT)) & FMUTEST_ERS_PULSE_CNT_ERS_CNT0_MASK)
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#define FMUTEST_ERS_PULSE_CNT_ERS_CNT1_MASK (0xFFFF0000U)
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#define FMUTEST_ERS_PULSE_CNT_ERS_CNT1_SHIFT (16U)
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/*! ERS_CNT1 - Block 1 Erase Pulse Count */
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#define FMUTEST_ERS_PULSE_CNT_ERS_CNT1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_ERS_PULSE_CNT_ERS_CNT1_SHIFT)) & FMUTEST_ERS_PULSE_CNT_ERS_CNT1_MASK)
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/*! @} */
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/*! @name MAX_PULSE_CNT - Maximum Pulse Count Register */
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/*! @{ */
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#define FMUTEST_MAX_PULSE_CNT_LAST_PCNT_MASK (0x1FFU)
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#define FMUTEST_MAX_PULSE_CNT_LAST_PCNT_SHIFT (0U)
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/*! LAST_PCNT - Last SMW Operation's Pulse Count */
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#define FMUTEST_MAX_PULSE_CNT_LAST_PCNT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MAX_PULSE_CNT_LAST_PCNT_SHIFT)) & FMUTEST_MAX_PULSE_CNT_LAST_PCNT_MASK)
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#define FMUTEST_MAX_PULSE_CNT_MAX_ERS_CNT_MASK (0x1FF0000U)
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#define FMUTEST_MAX_PULSE_CNT_MAX_ERS_CNT_SHIFT (16U)
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/*! MAX_ERS_CNT - Maximum Erase Pulse Count */
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#define FMUTEST_MAX_PULSE_CNT_MAX_ERS_CNT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MAX_PULSE_CNT_MAX_ERS_CNT_SHIFT)) & FMUTEST_MAX_PULSE_CNT_MAX_ERS_CNT_MASK)
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#define FMUTEST_MAX_PULSE_CNT_MAX_PGM_CNT_MASK (0xF8000000U)
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#define FMUTEST_MAX_PULSE_CNT_MAX_PGM_CNT_SHIFT (27U)
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/*! MAX_PGM_CNT - Maximum Program Pulse Count */
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|
#define FMUTEST_MAX_PULSE_CNT_MAX_PGM_CNT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MAX_PULSE_CNT_MAX_PGM_CNT_SHIFT)) & FMUTEST_MAX_PULSE_CNT_MAX_PGM_CNT_MASK)
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/*! @} */
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/*! @name PORT_CTRL - Port Control Register */
|
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/*! @{ */
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#define FMUTEST_PORT_CTRL_BDONE_SEL_MASK (0x3U)
|
|
#define FMUTEST_PORT_CTRL_BDONE_SEL_SHIFT (0U)
|
|
/*! BDONE_SEL - BIST Done Select
|
|
* 0b00..Select internal bist_done signal from current module instantiation
|
|
* 0b01..Select ipt_bist_fail signal from current module instantiation
|
|
* 0b10..Select ipt_bist_done signal from other module instantiation
|
|
* 0b11..Select AND of internal bist_done signal from current module instantiation with ipt_bist_done signal from other module instantiation
|
|
*/
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|
#define FMUTEST_PORT_CTRL_BDONE_SEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PORT_CTRL_BDONE_SEL_SHIFT)) & FMUTEST_PORT_CTRL_BDONE_SEL_MASK)
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#define FMUTEST_PORT_CTRL_BSDO_SEL_MASK (0xCU)
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|
#define FMUTEST_PORT_CTRL_BSDO_SEL_SHIFT (2U)
|
|
/*! BSDO_SEL - BIST Serial Data Output Select
|
|
* 0b00..Select internal bist_sdo signal from current module instantiation
|
|
* 0b01..Select ipt_bist_done signal from current module instantiation
|
|
* 0b10..Select ipt_bist_sdo signal from other module instantiation
|
|
* 0b11..Select ipt_bist_done signal from other module instantiation
|
|
*/
|
|
#define FMUTEST_PORT_CTRL_BSDO_SEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PORT_CTRL_BSDO_SEL_SHIFT)) & FMUTEST_PORT_CTRL_BSDO_SEL_MASK)
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|
/*! @} */
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|
/*!
|
|
* @}
|
|
*/ /* end of group FMUTEST_Register_Masks */
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|
|
|
|
|
/* FMUTEST - Peripheral instance base addresses */
|
|
/** Peripheral FMU0TEST base address */
|
|
#define FMU0TEST_BASE (0x40096000u)
|
|
/** Peripheral FMU0TEST base pointer */
|
|
#define FMU0TEST ((FMUTEST_Type *)FMU0TEST_BASE)
|
|
/** Array initializer of FMUTEST peripheral base addresses */
|
|
#define FMUTEST_BASE_ADDRS { FMU0TEST_BASE }
|
|
/** Array initializer of FMUTEST peripheral base pointers */
|
|
#define FMUTEST_BASE_PTRS { FMU0TEST }
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|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group FMUTEST_Peripheral_Access_Layer */
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|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- FREQME Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup FREQME_Peripheral_Access_Layer FREQME Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** FREQME - Register Layout Typedef */
|
|
typedef struct {
|
|
union { /* offset: 0x0 */
|
|
__I uint32_t CTRL_R; /**< Control (in Read mode), offset: 0x0 */
|
|
__O uint32_t CTRL_W; /**< Control (in Write mode), offset: 0x0 */
|
|
};
|
|
__IO uint32_t CTRLSTAT; /**< Control Status, offset: 0x4 */
|
|
__IO uint32_t MIN; /**< Minimum, offset: 0x8 */
|
|
__IO uint32_t MAX; /**< Maximum, offset: 0xC */
|
|
} FREQME_Type;
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|
|
/* ----------------------------------------------------------------------------
|
|
-- FREQME Register Masks
|
|
---------------------------------------------------------------------------- */
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|
|
|
/*!
|
|
* @addtogroup FREQME_Register_Masks FREQME Register Masks
|
|
* @{
|
|
*/
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|
|
|
/*! @name CTRL_R - Control (in Read mode) */
|
|
/*! @{ */
|
|
|
|
#define FREQME_CTRL_R_RESULT_MASK (0x7FFFFFFFU)
|
|
#define FREQME_CTRL_R_RESULT_SHIFT (0U)
|
|
#define FREQME_CTRL_R_RESULT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_R_RESULT_SHIFT)) & FREQME_CTRL_R_RESULT_MASK)
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|
|
#define FREQME_CTRL_R_MEASURE_IN_PROGRESS_MASK (0x80000000U)
|
|
#define FREQME_CTRL_R_MEASURE_IN_PROGRESS_SHIFT (31U)
|
|
/*! MEASURE_IN_PROGRESS - Measurement In Progress
|
|
* 0b0..Complete
|
|
* 0b1..In progress
|
|
*/
|
|
#define FREQME_CTRL_R_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_R_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_CTRL_R_MEASURE_IN_PROGRESS_MASK)
|
|
/*! @} */
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|
|
/*! @name CTRL_W - Control (in Write mode) */
|
|
/*! @{ */
|
|
|
|
#define FREQME_CTRL_W_REF_SCALE_MASK (0x1FU)
|
|
#define FREQME_CTRL_W_REF_SCALE_SHIFT (0U)
|
|
/*! REF_SCALE - Reference Clock Scaling Factor */
|
|
#define FREQME_CTRL_W_REF_SCALE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_REF_SCALE_SHIFT)) & FREQME_CTRL_W_REF_SCALE_MASK)
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|
|
|
#define FREQME_CTRL_W_PULSE_MODE_MASK (0x100U)
|
|
#define FREQME_CTRL_W_PULSE_MODE_SHIFT (8U)
|
|
/*! PULSE_MODE - Pulse Width Measurement Mode Select
|
|
* 0b0..Frequency Measurement mode
|
|
* 0b1..Pulse Width Measurement mode
|
|
*/
|
|
#define FREQME_CTRL_W_PULSE_MODE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_PULSE_MODE_SHIFT)) & FREQME_CTRL_W_PULSE_MODE_MASK)
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|
|
|
#define FREQME_CTRL_W_PULSE_POL_MASK (0x200U)
|
|
#define FREQME_CTRL_W_PULSE_POL_SHIFT (9U)
|
|
/*! PULSE_POL - Pulse Polarity
|
|
* 0b0..High period
|
|
* 0b1..Low period
|
|
*/
|
|
#define FREQME_CTRL_W_PULSE_POL(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_PULSE_POL_SHIFT)) & FREQME_CTRL_W_PULSE_POL_MASK)
|
|
|
|
#define FREQME_CTRL_W_LT_MIN_INT_EN_MASK (0x1000U)
|
|
#define FREQME_CTRL_W_LT_MIN_INT_EN_SHIFT (12U)
|
|
/*! LT_MIN_INT_EN - Less Than Minimum Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define FREQME_CTRL_W_LT_MIN_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_LT_MIN_INT_EN_SHIFT)) & FREQME_CTRL_W_LT_MIN_INT_EN_MASK)
|
|
|
|
#define FREQME_CTRL_W_GT_MAX_INT_EN_MASK (0x2000U)
|
|
#define FREQME_CTRL_W_GT_MAX_INT_EN_SHIFT (13U)
|
|
/*! GT_MAX_INT_EN - Greater Than Maximum Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define FREQME_CTRL_W_GT_MAX_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_GT_MAX_INT_EN_SHIFT)) & FREQME_CTRL_W_GT_MAX_INT_EN_MASK)
|
|
|
|
#define FREQME_CTRL_W_RESULT_READY_INT_EN_MASK (0x4000U)
|
|
#define FREQME_CTRL_W_RESULT_READY_INT_EN_SHIFT (14U)
|
|
/*! RESULT_READY_INT_EN - Result Ready Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define FREQME_CTRL_W_RESULT_READY_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_RESULT_READY_INT_EN_SHIFT)) & FREQME_CTRL_W_RESULT_READY_INT_EN_MASK)
|
|
|
|
#define FREQME_CTRL_W_CONTINUOUS_MODE_EN_MASK (0x40000000U)
|
|
#define FREQME_CTRL_W_CONTINUOUS_MODE_EN_SHIFT (30U)
|
|
/*! CONTINUOUS_MODE_EN - Continuous Mode Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define FREQME_CTRL_W_CONTINUOUS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_CONTINUOUS_MODE_EN_SHIFT)) & FREQME_CTRL_W_CONTINUOUS_MODE_EN_MASK)
|
|
|
|
#define FREQME_CTRL_W_MEASURE_IN_PROGRESS_MASK (0x80000000U)
|
|
#define FREQME_CTRL_W_MEASURE_IN_PROGRESS_SHIFT (31U)
|
|
/*! MEASURE_IN_PROGRESS - Measurement In Progress
|
|
* 0b0..Terminates measurement
|
|
* 0b1..Initiates measurement
|
|
*/
|
|
#define FREQME_CTRL_W_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_CTRL_W_MEASURE_IN_PROGRESS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CTRLSTAT - Control Status */
|
|
/*! @{ */
|
|
|
|
#define FREQME_CTRLSTAT_REF_SCALE_MASK (0x1FU)
|
|
#define FREQME_CTRLSTAT_REF_SCALE_SHIFT (0U)
|
|
/*! REF_SCALE - Reference Scale */
|
|
#define FREQME_CTRLSTAT_REF_SCALE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_REF_SCALE_SHIFT)) & FREQME_CTRLSTAT_REF_SCALE_MASK)
|
|
|
|
#define FREQME_CTRLSTAT_PULSE_MODE_MASK (0x100U)
|
|
#define FREQME_CTRLSTAT_PULSE_MODE_SHIFT (8U)
|
|
/*! PULSE_MODE - Pulse Mode
|
|
* 0b0..Frequency Measurement mode
|
|
* 0b1..Pulse Width Measurement mode
|
|
*/
|
|
#define FREQME_CTRLSTAT_PULSE_MODE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_PULSE_MODE_SHIFT)) & FREQME_CTRLSTAT_PULSE_MODE_MASK)
|
|
|
|
#define FREQME_CTRLSTAT_PULSE_POL_MASK (0x200U)
|
|
#define FREQME_CTRLSTAT_PULSE_POL_SHIFT (9U)
|
|
/*! PULSE_POL - Pulse Polarity
|
|
* 0b0..High period
|
|
* 0b1..Low period
|
|
*/
|
|
#define FREQME_CTRLSTAT_PULSE_POL(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_PULSE_POL_SHIFT)) & FREQME_CTRLSTAT_PULSE_POL_MASK)
|
|
|
|
#define FREQME_CTRLSTAT_LT_MIN_INT_EN_MASK (0x1000U)
|
|
#define FREQME_CTRLSTAT_LT_MIN_INT_EN_SHIFT (12U)
|
|
/*! LT_MIN_INT_EN - Less Than Minimum Interrupt Enable
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define FREQME_CTRLSTAT_LT_MIN_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_LT_MIN_INT_EN_SHIFT)) & FREQME_CTRLSTAT_LT_MIN_INT_EN_MASK)
|
|
|
|
#define FREQME_CTRLSTAT_GT_MAX_INT_EN_MASK (0x2000U)
|
|
#define FREQME_CTRLSTAT_GT_MAX_INT_EN_SHIFT (13U)
|
|
/*! GT_MAX_INT_EN - Greater Than Maximum Interrupt Enable
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define FREQME_CTRLSTAT_GT_MAX_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_GT_MAX_INT_EN_SHIFT)) & FREQME_CTRLSTAT_GT_MAX_INT_EN_MASK)
|
|
|
|
#define FREQME_CTRLSTAT_RESULT_READY_INT_EN_MASK (0x4000U)
|
|
#define FREQME_CTRLSTAT_RESULT_READY_INT_EN_SHIFT (14U)
|
|
/*! RESULT_READY_INT_EN - Result Ready Interrupt Enable
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define FREQME_CTRLSTAT_RESULT_READY_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_RESULT_READY_INT_EN_SHIFT)) & FREQME_CTRLSTAT_RESULT_READY_INT_EN_MASK)
|
|
|
|
#define FREQME_CTRLSTAT_LT_MIN_STAT_MASK (0x1000000U)
|
|
#define FREQME_CTRLSTAT_LT_MIN_STAT_SHIFT (24U)
|
|
/*! LT_MIN_STAT - Less Than Minimum Results Status
|
|
* 0b0..Greater than MIN[MIN_VALUE]
|
|
* 0b1..Less than MIN[MIN_VALUE]
|
|
*/
|
|
#define FREQME_CTRLSTAT_LT_MIN_STAT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_LT_MIN_STAT_SHIFT)) & FREQME_CTRLSTAT_LT_MIN_STAT_MASK)
|
|
|
|
#define FREQME_CTRLSTAT_GT_MAX_STAT_MASK (0x2000000U)
|
|
#define FREQME_CTRLSTAT_GT_MAX_STAT_SHIFT (25U)
|
|
/*! GT_MAX_STAT - Greater Than Maximum Result Status
|
|
* 0b0..Less than MAX[MAX_VALUE]
|
|
* 0b1..Greater than MAX[MAX_VALUE]
|
|
*/
|
|
#define FREQME_CTRLSTAT_GT_MAX_STAT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_GT_MAX_STAT_SHIFT)) & FREQME_CTRLSTAT_GT_MAX_STAT_MASK)
|
|
|
|
#define FREQME_CTRLSTAT_RESULT_READY_STAT_MASK (0x4000000U)
|
|
#define FREQME_CTRLSTAT_RESULT_READY_STAT_SHIFT (26U)
|
|
/*! RESULT_READY_STAT - Result Ready Status
|
|
* 0b0..Not complete
|
|
* 0b1..Complete
|
|
*/
|
|
#define FREQME_CTRLSTAT_RESULT_READY_STAT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_RESULT_READY_STAT_SHIFT)) & FREQME_CTRLSTAT_RESULT_READY_STAT_MASK)
|
|
|
|
#define FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_MASK (0x40000000U)
|
|
#define FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_SHIFT (30U)
|
|
/*! CONTINUOUS_MODE_EN - Continuous Mode Enable Status
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define FREQME_CTRLSTAT_CONTINUOUS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_SHIFT)) & FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_MASK)
|
|
|
|
#define FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_MASK (0x80000000U)
|
|
#define FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_SHIFT (31U)
|
|
/*! MEASURE_IN_PROGRESS - Measurement in Progress Status
|
|
* 0b0..Not in progress
|
|
* 0b1..In progress
|
|
*/
|
|
#define FREQME_CTRLSTAT_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MIN - Minimum */
|
|
/*! @{ */
|
|
|
|
#define FREQME_MIN_MIN_VALUE_MASK (0x7FFFFFFFU)
|
|
#define FREQME_MIN_MIN_VALUE_SHIFT (0U)
|
|
/*! MIN_VALUE - Minimum Value */
|
|
#define FREQME_MIN_MIN_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_MIN_MIN_VALUE_SHIFT)) & FREQME_MIN_MIN_VALUE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MAX - Maximum */
|
|
/*! @{ */
|
|
|
|
#define FREQME_MAX_MAX_VALUE_MASK (0x7FFFFFFFU)
|
|
#define FREQME_MAX_MAX_VALUE_SHIFT (0U)
|
|
/*! MAX_VALUE - Maximum Value */
|
|
#define FREQME_MAX_MAX_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_MAX_MAX_VALUE_SHIFT)) & FREQME_MAX_MAX_VALUE_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group FREQME_Register_Masks */
|
|
|
|
|
|
/* FREQME - Peripheral instance base addresses */
|
|
/** Peripheral FREQME0 base address */
|
|
#define FREQME0_BASE (0x40009000u)
|
|
/** Peripheral FREQME0 base pointer */
|
|
#define FREQME0 ((FREQME_Type *)FREQME0_BASE)
|
|
/** Array initializer of FREQME peripheral base addresses */
|
|
#define FREQME_BASE_ADDRS { FREQME0_BASE }
|
|
/** Array initializer of FREQME peripheral base pointers */
|
|
#define FREQME_BASE_PTRS { FREQME0 }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group FREQME_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- GLIKEY Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup GLIKEY_Peripheral_Access_Layer GLIKEY Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** GLIKEY - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t CTRL_0; /**< Control Register 0 SFR, offset: 0x0 */
|
|
__IO uint32_t CTRL_1; /**< Control Regsiter 1 SFR, offset: 0x4 */
|
|
__IO uint32_t INTR_CTRL; /**< Interrupt Control, offset: 0x8 */
|
|
__I uint32_t STATUS; /**< Status, offset: 0xC */
|
|
uint8_t RESERVED_0[236];
|
|
__I uint32_t VERSION; /**< IP Version, offset: 0xFC */
|
|
} GLIKEY_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- GLIKEY Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup GLIKEY_Register_Masks GLIKEY Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name CTRL_0 - Control Register 0 SFR */
|
|
/*! @{ */
|
|
|
|
#define GLIKEY_CTRL_0_WRITE_INDEX_MASK (0xFFU)
|
|
#define GLIKEY_CTRL_0_WRITE_INDEX_SHIFT (0U)
|
|
/*! WRITE_INDEX - Write Index */
|
|
#define GLIKEY_CTRL_0_WRITE_INDEX(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_0_WRITE_INDEX_SHIFT)) & GLIKEY_CTRL_0_WRITE_INDEX_MASK)
|
|
|
|
#define GLIKEY_CTRL_0_RESERVED15_MASK (0xFF00U)
|
|
#define GLIKEY_CTRL_0_RESERVED15_SHIFT (8U)
|
|
/*! RESERVED15 - Reserved for Future Use */
|
|
#define GLIKEY_CTRL_0_RESERVED15(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_0_RESERVED15_SHIFT)) & GLIKEY_CTRL_0_RESERVED15_MASK)
|
|
|
|
#define GLIKEY_CTRL_0_WR_EN_0_MASK (0x30000U)
|
|
#define GLIKEY_CTRL_0_WR_EN_0_SHIFT (16U)
|
|
/*! WR_EN_0 - Write Enable 0 */
|
|
#define GLIKEY_CTRL_0_WR_EN_0(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_0_WR_EN_0_SHIFT)) & GLIKEY_CTRL_0_WR_EN_0_MASK)
|
|
|
|
#define GLIKEY_CTRL_0_SFT_RST_MASK (0x40000U)
|
|
#define GLIKEY_CTRL_0_SFT_RST_SHIFT (18U)
|
|
/*! SFT_RST - Soft reset for the core reset (SFR configuration will be preseved).This register reads as 0
|
|
* 0b0..No effect
|
|
* 0b1..Triggers the soft reset
|
|
*/
|
|
#define GLIKEY_CTRL_0_SFT_RST(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_0_SFT_RST_SHIFT)) & GLIKEY_CTRL_0_SFT_RST_MASK)
|
|
|
|
#define GLIKEY_CTRL_0_RESERVED31_MASK (0xFFF80000U)
|
|
#define GLIKEY_CTRL_0_RESERVED31_SHIFT (19U)
|
|
/*! RESERVED31 - Reserved for Future Use */
|
|
#define GLIKEY_CTRL_0_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_0_RESERVED31_SHIFT)) & GLIKEY_CTRL_0_RESERVED31_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CTRL_1 - Control Regsiter 1 SFR */
|
|
/*! @{ */
|
|
|
|
#define GLIKEY_CTRL_1_READ_INDEX_MASK (0xFFU)
|
|
#define GLIKEY_CTRL_1_READ_INDEX_SHIFT (0U)
|
|
/*! READ_INDEX - Index status, Writing an index value to this register will request the block to return the lock status of this index. */
|
|
#define GLIKEY_CTRL_1_READ_INDEX(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_1_READ_INDEX_SHIFT)) & GLIKEY_CTRL_1_READ_INDEX_MASK)
|
|
|
|
#define GLIKEY_CTRL_1_RESERVED15_MASK (0xFF00U)
|
|
#define GLIKEY_CTRL_1_RESERVED15_SHIFT (8U)
|
|
/*! RESERVED15 - Reserved for Future Use */
|
|
#define GLIKEY_CTRL_1_RESERVED15(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_1_RESERVED15_SHIFT)) & GLIKEY_CTRL_1_RESERVED15_MASK)
|
|
|
|
#define GLIKEY_CTRL_1_WR_EN_1_MASK (0x30000U)
|
|
#define GLIKEY_CTRL_1_WR_EN_1_SHIFT (16U)
|
|
/*! WR_EN_1 - Write Enable One */
|
|
#define GLIKEY_CTRL_1_WR_EN_1(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_1_WR_EN_1_SHIFT)) & GLIKEY_CTRL_1_WR_EN_1_MASK)
|
|
|
|
#define GLIKEY_CTRL_1_SFR_LOCK_MASK (0x3C0000U)
|
|
#define GLIKEY_CTRL_1_SFR_LOCK_SHIFT (18U)
|
|
/*! SFR_LOCK - LOCK register for GLIKEY */
|
|
#define GLIKEY_CTRL_1_SFR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_1_SFR_LOCK_SHIFT)) & GLIKEY_CTRL_1_SFR_LOCK_MASK)
|
|
|
|
#define GLIKEY_CTRL_1_RESERVED31_MASK (0xFFC00000U)
|
|
#define GLIKEY_CTRL_1_RESERVED31_SHIFT (22U)
|
|
/*! RESERVED31 - Reserved for Future Use */
|
|
#define GLIKEY_CTRL_1_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_1_RESERVED31_SHIFT)) & GLIKEY_CTRL_1_RESERVED31_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name INTR_CTRL - Interrupt Control */
|
|
/*! @{ */
|
|
|
|
#define GLIKEY_INTR_CTRL_INT_EN_MASK (0x1U)
|
|
#define GLIKEY_INTR_CTRL_INT_EN_SHIFT (0U)
|
|
/*! INT_EN - Interrupt Enable. Writing a 1, Interrupt asserts on Interrupt output port */
|
|
#define GLIKEY_INTR_CTRL_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_INTR_CTRL_INT_EN_SHIFT)) & GLIKEY_INTR_CTRL_INT_EN_MASK)
|
|
|
|
#define GLIKEY_INTR_CTRL_INT_CLR_MASK (0x2U)
|
|
#define GLIKEY_INTR_CTRL_INT_CLR_SHIFT (1U)
|
|
/*! INT_CLR - Interrupt Clear. Writing a 1 to this register creates a single interrupt clear pulse. This register reads as 0 */
|
|
#define GLIKEY_INTR_CTRL_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_INTR_CTRL_INT_CLR_SHIFT)) & GLIKEY_INTR_CTRL_INT_CLR_MASK)
|
|
|
|
#define GLIKEY_INTR_CTRL_INT_SET_MASK (0x4U)
|
|
#define GLIKEY_INTR_CTRL_INT_SET_SHIFT (2U)
|
|
/*! INT_SET - Interrupt Set. Writing a 1 to this register asserts the interrupt. This register reads as 0
|
|
* 0b0..No effect
|
|
* 0b1..Triggers interrupt
|
|
*/
|
|
#define GLIKEY_INTR_CTRL_INT_SET(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_INTR_CTRL_INT_SET_SHIFT)) & GLIKEY_INTR_CTRL_INT_SET_MASK)
|
|
|
|
#define GLIKEY_INTR_CTRL_RESERVED31_MASK (0xFFFFFFF8U)
|
|
#define GLIKEY_INTR_CTRL_RESERVED31_SHIFT (3U)
|
|
/*! RESERVED31 - Reserved for Future Use */
|
|
#define GLIKEY_INTR_CTRL_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_INTR_CTRL_RESERVED31_SHIFT)) & GLIKEY_INTR_CTRL_RESERVED31_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name STATUS - Status */
|
|
/*! @{ */
|
|
|
|
#define GLIKEY_STATUS_INT_STATUS_MASK (0x1U)
|
|
#define GLIKEY_STATUS_INT_STATUS_SHIFT (0U)
|
|
/*! INT_STATUS - Interrupt Status.
|
|
* 0b0..No effect
|
|
* 0b1..Triggers interrupt
|
|
*/
|
|
#define GLIKEY_STATUS_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_STATUS_INT_STATUS_SHIFT)) & GLIKEY_STATUS_INT_STATUS_MASK)
|
|
|
|
#define GLIKEY_STATUS_LOCK_STATUS_MASK (0x2U)
|
|
#define GLIKEY_STATUS_LOCK_STATUS_SHIFT (1U)
|
|
/*! LOCK_STATUS - Provides the current lock status of indexes.
|
|
* 0b0..Current read index is not locked
|
|
* 0b1..Current read index is locked
|
|
*/
|
|
#define GLIKEY_STATUS_LOCK_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_STATUS_LOCK_STATUS_SHIFT)) & GLIKEY_STATUS_LOCK_STATUS_MASK)
|
|
|
|
#define GLIKEY_STATUS_ERROR_STATUS_MASK (0x1CU)
|
|
#define GLIKEY_STATUS_ERROR_STATUS_SHIFT (2U)
|
|
/*! ERROR_STATUS - Status of the Error
|
|
* 0b000..No error
|
|
* 0b001..FSM error has occurred
|
|
* 0b010..Write index out of the bound (OOB) error
|
|
* 0b011..Write index OOB and FSM error
|
|
* 0b100..Read index OOB error
|
|
* 0b110..Write index and read index OOB error
|
|
* 0b111..Read index OOB, write index OOB, and FSM error
|
|
*/
|
|
#define GLIKEY_STATUS_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_STATUS_ERROR_STATUS_SHIFT)) & GLIKEY_STATUS_ERROR_STATUS_MASK)
|
|
|
|
#define GLIKEY_STATUS_RESERVED18_MASK (0x7FFE0U)
|
|
#define GLIKEY_STATUS_RESERVED18_SHIFT (5U)
|
|
/*! RESERVED18 - Reserved for Future Use */
|
|
#define GLIKEY_STATUS_RESERVED18(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_STATUS_RESERVED18_SHIFT)) & GLIKEY_STATUS_RESERVED18_MASK)
|
|
|
|
#define GLIKEY_STATUS_FSM_STATE_MASK (0xFFF80000U)
|
|
#define GLIKEY_STATUS_FSM_STATE_SHIFT (19U)
|
|
/*! FSM_STATE - Status of FSM */
|
|
#define GLIKEY_STATUS_FSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_STATUS_FSM_STATE_SHIFT)) & GLIKEY_STATUS_FSM_STATE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name VERSION - IP Version */
|
|
/*! @{ */
|
|
|
|
#define GLIKEY_VERSION_RESERVED3_MASK (0xFU)
|
|
#define GLIKEY_VERSION_RESERVED3_SHIFT (0U)
|
|
/*! Reserved3 - Reserved */
|
|
#define GLIKEY_VERSION_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_RESERVED3_SHIFT)) & GLIKEY_VERSION_RESERVED3_MASK)
|
|
|
|
#define GLIKEY_VERSION_RESERVED7_MASK (0xF0U)
|
|
#define GLIKEY_VERSION_RESERVED7_SHIFT (4U)
|
|
/*! Reserved7 - Reserved */
|
|
#define GLIKEY_VERSION_RESERVED7(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_RESERVED7_SHIFT)) & GLIKEY_VERSION_RESERVED7_MASK)
|
|
|
|
#define GLIKEY_VERSION_RESERVED11_MASK (0xF00U)
|
|
#define GLIKEY_VERSION_RESERVED11_SHIFT (8U)
|
|
/*! Reserved11 - Reserved */
|
|
#define GLIKEY_VERSION_RESERVED11(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_RESERVED11_SHIFT)) & GLIKEY_VERSION_RESERVED11_MASK)
|
|
|
|
#define GLIKEY_VERSION_RESERVED15_MASK (0xF000U)
|
|
#define GLIKEY_VERSION_RESERVED15_SHIFT (12U)
|
|
/*! Reserved15 - Reserved */
|
|
#define GLIKEY_VERSION_RESERVED15(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_RESERVED15_SHIFT)) & GLIKEY_VERSION_RESERVED15_MASK)
|
|
|
|
#define GLIKEY_VERSION_RESERVED16_MASK (0x30000U)
|
|
#define GLIKEY_VERSION_RESERVED16_SHIFT (16U)
|
|
/*! Reserved16 - Reserved */
|
|
#define GLIKEY_VERSION_RESERVED16(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_RESERVED16_SHIFT)) & GLIKEY_VERSION_RESERVED16_MASK)
|
|
|
|
#define GLIKEY_VERSION_FSM_CONFIG_MASK (0x40000U)
|
|
#define GLIKEY_VERSION_FSM_CONFIG_SHIFT (18U)
|
|
/*! FSM_CONFIG - 0:4 step, 1:8 step */
|
|
#define GLIKEY_VERSION_FSM_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_FSM_CONFIG_SHIFT)) & GLIKEY_VERSION_FSM_CONFIG_MASK)
|
|
|
|
#define GLIKEY_VERSION_INDEX_CONFIG_MASK (0x7F80000U)
|
|
#define GLIKEY_VERSION_INDEX_CONFIG_SHIFT (19U)
|
|
/*! INDEX_CONFIG - Configured number of addressable indexes */
|
|
#define GLIKEY_VERSION_INDEX_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_INDEX_CONFIG_SHIFT)) & GLIKEY_VERSION_INDEX_CONFIG_MASK)
|
|
|
|
#define GLIKEY_VERSION_RESERVED31_MASK (0xF8000000U)
|
|
#define GLIKEY_VERSION_RESERVED31_SHIFT (27U)
|
|
/*! Reserved31 - Reserved for Future Use */
|
|
#define GLIKEY_VERSION_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_RESERVED31_SHIFT)) & GLIKEY_VERSION_RESERVED31_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group GLIKEY_Register_Masks */
|
|
|
|
|
|
/* GLIKEY - Peripheral instance base addresses */
|
|
/** Peripheral GLIKEY0 base address */
|
|
#define GLIKEY0_BASE (0x40091D00u)
|
|
/** Peripheral GLIKEY0 base pointer */
|
|
#define GLIKEY0 ((GLIKEY_Type *)GLIKEY0_BASE)
|
|
/** Array initializer of GLIKEY peripheral base addresses */
|
|
#define GLIKEY_BASE_ADDRS { GLIKEY0_BASE }
|
|
/** Array initializer of GLIKEY peripheral base pointers */
|
|
#define GLIKEY_BASE_PTRS { GLIKEY0 }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group GLIKEY_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- GPIO Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** GPIO - Register Layout Typedef */
|
|
typedef struct {
|
|
__I uint32_t VERID; /**< Version ID, offset: 0x0 */
|
|
__I uint32_t PARAM; /**< Parameter, offset: 0x4 */
|
|
uint8_t RESERVED_0[56];
|
|
__IO uint32_t PDOR; /**< Port Data Output, offset: 0x40 */
|
|
__O uint32_t PSOR; /**< Port Set Output, offset: 0x44 */
|
|
__O uint32_t PCOR; /**< Port Clear Output, offset: 0x48 */
|
|
__O uint32_t PTOR; /**< Port Toggle Output, offset: 0x4C */
|
|
__I uint32_t PDIR; /**< Port Data Input, offset: 0x50 */
|
|
__IO uint32_t PDDR; /**< Port Data Direction, offset: 0x54 */
|
|
__IO uint32_t PIDR; /**< Port Input Disable, offset: 0x58 */
|
|
uint8_t RESERVED_1[4];
|
|
__IO uint8_t PDR[32]; /**< Pin Data, array offset: 0x60, array step: 0x1 */
|
|
__IO uint32_t ICR[32]; /**< Interrupt Control 0..Interrupt Control 31, array offset: 0x80, array step: 0x4 */
|
|
__O uint32_t GICLR; /**< Global Interrupt Control Low, offset: 0x100 */
|
|
__O uint32_t GICHR; /**< Global Interrupt Control High, offset: 0x104 */
|
|
uint8_t RESERVED_2[24];
|
|
__IO uint32_t ISFR[1]; /**< Interrupt Status Flag, array offset: 0x120, array step: 0x4 */
|
|
} GPIO_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- GPIO Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup GPIO_Register_Masks GPIO Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name VERID - Version ID */
|
|
/*! @{ */
|
|
|
|
#define GPIO_VERID_FEATURE_MASK (0xFFFFU)
|
|
#define GPIO_VERID_FEATURE_SHIFT (0U)
|
|
/*! FEATURE - Feature Specification Number
|
|
* 0b0000000000000000..Basic implementation
|
|
* 0b0000000000000001..Protection registers implemented
|
|
*/
|
|
#define GPIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_FEATURE_SHIFT)) & GPIO_VERID_FEATURE_MASK)
|
|
|
|
#define GPIO_VERID_MINOR_MASK (0xFF0000U)
|
|
#define GPIO_VERID_MINOR_SHIFT (16U)
|
|
/*! MINOR - Minor Version Number */
|
|
#define GPIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_MINOR_SHIFT)) & GPIO_VERID_MINOR_MASK)
|
|
|
|
#define GPIO_VERID_MAJOR_MASK (0xFF000000U)
|
|
#define GPIO_VERID_MAJOR_SHIFT (24U)
|
|
/*! MAJOR - Major Version Number */
|
|
#define GPIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_MAJOR_SHIFT)) & GPIO_VERID_MAJOR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PARAM - Parameter */
|
|
/*! @{ */
|
|
|
|
#define GPIO_PARAM_IRQNUM_MASK (0xFU)
|
|
#define GPIO_PARAM_IRQNUM_SHIFT (0U)
|
|
/*! IRQNUM - Interrupt Number */
|
|
#define GPIO_PARAM_IRQNUM(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PARAM_IRQNUM_SHIFT)) & GPIO_PARAM_IRQNUM_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PDOR - Port Data Output */
|
|
/*! @{ */
|
|
|
|
#define GPIO_PDOR_PDO0_MASK (0x1U)
|
|
#define GPIO_PDOR_PDO0_SHIFT (0U)
|
|
/*! PDO0 - Port Data Output
|
|
* 0b0..Logic level 0
|
|
* 0b1..Logic level 1
|
|
*/
|
|
#define GPIO_PDOR_PDO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO0_SHIFT)) & GPIO_PDOR_PDO0_MASK)
|
|
|
|
#define GPIO_PDOR_PDO1_MASK (0x2U)
|
|
#define GPIO_PDOR_PDO1_SHIFT (1U)
|
|
/*! PDO1 - Port Data Output
|
|
* 0b0..Logic level 0
|
|
* 0b1..Logic level 1
|
|
*/
|
|
#define GPIO_PDOR_PDO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO1_SHIFT)) & GPIO_PDOR_PDO1_MASK)
|
|
|
|
#define GPIO_PDOR_PDO2_MASK (0x4U)
|
|
#define GPIO_PDOR_PDO2_SHIFT (2U)
|
|
/*! PDO2 - Port Data Output
|
|
* 0b0..Logic level 0
|
|
* 0b1..Logic level 1
|
|
*/
|
|
#define GPIO_PDOR_PDO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO2_SHIFT)) & GPIO_PDOR_PDO2_MASK)
|
|
|
|
#define GPIO_PDOR_PDO3_MASK (0x8U)
|
|
#define GPIO_PDOR_PDO3_SHIFT (3U)
|
|
/*! PDO3 - Port Data Output
|
|
* 0b0..Logic level 0
|
|
* 0b1..Logic level 1
|
|
*/
|
|
#define GPIO_PDOR_PDO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO3_SHIFT)) & GPIO_PDOR_PDO3_MASK)
|
|
|
|
#define GPIO_PDOR_PDO4_MASK (0x10U)
|
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#define GPIO_PDOR_PDO4_SHIFT (4U)
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/*! PDO4 - Port Data Output
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* 0b0..Logic level 0
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* 0b1..Logic level 1
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*/
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#define GPIO_PDOR_PDO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO4_SHIFT)) & GPIO_PDOR_PDO4_MASK)
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#define GPIO_PDOR_PDO5_MASK (0x20U)
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#define GPIO_PDOR_PDO5_SHIFT (5U)
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/*! PDO5 - Port Data Output
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* 0b0..Logic level 0
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* 0b1..Logic level 1
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*/
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#define GPIO_PDOR_PDO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO5_SHIFT)) & GPIO_PDOR_PDO5_MASK)
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#define GPIO_PDOR_PDO6_MASK (0x40U)
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#define GPIO_PDOR_PDO6_SHIFT (6U)
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/*! PDO6 - Port Data Output
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* 0b0..Logic level 0
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* 0b1..Logic level 1
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*/
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#define GPIO_PDOR_PDO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO6_SHIFT)) & GPIO_PDOR_PDO6_MASK)
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#define GPIO_PDOR_PDO7_MASK (0x80U)
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#define GPIO_PDOR_PDO7_SHIFT (7U)
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/*! PDO7 - Port Data Output
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* 0b0..Logic level 0
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* 0b1..Logic level 1
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*/
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#define GPIO_PDOR_PDO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO7_SHIFT)) & GPIO_PDOR_PDO7_MASK)
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#define GPIO_PDOR_PDO8_MASK (0x100U)
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#define GPIO_PDOR_PDO8_SHIFT (8U)
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/*! PDO8 - Port Data Output
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* 0b0..Logic level 0
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* 0b1..Logic level 1
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*/
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#define GPIO_PDOR_PDO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO8_SHIFT)) & GPIO_PDOR_PDO8_MASK)
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#define GPIO_PDOR_PDO9_MASK (0x200U)
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#define GPIO_PDOR_PDO9_SHIFT (9U)
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/*! PDO9 - Port Data Output
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* 0b0..Logic level 0
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* 0b1..Logic level 1
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*/
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#define GPIO_PDOR_PDO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO9_SHIFT)) & GPIO_PDOR_PDO9_MASK)
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#define GPIO_PDOR_PDO10_MASK (0x400U)
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#define GPIO_PDOR_PDO10_SHIFT (10U)
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/*! PDO10 - Port Data Output
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* 0b0..Logic level 0
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* 0b1..Logic level 1
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*/
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#define GPIO_PDOR_PDO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO10_SHIFT)) & GPIO_PDOR_PDO10_MASK)
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#define GPIO_PDOR_PDO11_MASK (0x800U)
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#define GPIO_PDOR_PDO11_SHIFT (11U)
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/*! PDO11 - Port Data Output
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* 0b0..Logic level 0
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* 0b1..Logic level 1
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*/
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#define GPIO_PDOR_PDO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO11_SHIFT)) & GPIO_PDOR_PDO11_MASK)
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#define GPIO_PDOR_PDO12_MASK (0x1000U)
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#define GPIO_PDOR_PDO12_SHIFT (12U)
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/*! PDO12 - Port Data Output
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* 0b0..Logic level 0
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* 0b1..Logic level 1
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*/
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#define GPIO_PDOR_PDO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO12_SHIFT)) & GPIO_PDOR_PDO12_MASK)
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#define GPIO_PDOR_PDO13_MASK (0x2000U)
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#define GPIO_PDOR_PDO13_SHIFT (13U)
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/*! PDO13 - Port Data Output
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* 0b0..Logic level 0
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* 0b1..Logic level 1
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*/
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#define GPIO_PDOR_PDO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO13_SHIFT)) & GPIO_PDOR_PDO13_MASK)
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#define GPIO_PDOR_PDO14_MASK (0x4000U)
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#define GPIO_PDOR_PDO14_SHIFT (14U)
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/*! PDO14 - Port Data Output
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* 0b0..Logic level 0
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* 0b1..Logic level 1
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*/
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#define GPIO_PDOR_PDO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO14_SHIFT)) & GPIO_PDOR_PDO14_MASK)
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#define GPIO_PDOR_PDO15_MASK (0x8000U)
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#define GPIO_PDOR_PDO15_SHIFT (15U)
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/*! PDO15 - Port Data Output
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* 0b0..Logic level 0
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* 0b1..Logic level 1
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*/
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#define GPIO_PDOR_PDO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO15_SHIFT)) & GPIO_PDOR_PDO15_MASK)
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#define GPIO_PDOR_PDO16_MASK (0x10000U)
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#define GPIO_PDOR_PDO16_SHIFT (16U)
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/*! PDO16 - Port Data Output
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* 0b0..Logic level 0
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* 0b1..Logic level 1
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*/
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#define GPIO_PDOR_PDO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO16_SHIFT)) & GPIO_PDOR_PDO16_MASK)
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#define GPIO_PDOR_PDO17_MASK (0x20000U)
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#define GPIO_PDOR_PDO17_SHIFT (17U)
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/*! PDO17 - Port Data Output
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* 0b0..Logic level 0
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* 0b1..Logic level 1
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*/
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#define GPIO_PDOR_PDO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO17_SHIFT)) & GPIO_PDOR_PDO17_MASK)
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#define GPIO_PDOR_PDO18_MASK (0x40000U)
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#define GPIO_PDOR_PDO18_SHIFT (18U)
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/*! PDO18 - Port Data Output
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* 0b0..Logic level 0
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* 0b1..Logic level 1
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*/
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#define GPIO_PDOR_PDO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO18_SHIFT)) & GPIO_PDOR_PDO18_MASK)
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#define GPIO_PDOR_PDO19_MASK (0x80000U)
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#define GPIO_PDOR_PDO19_SHIFT (19U)
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/*! PDO19 - Port Data Output
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* 0b0..Logic level 0
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* 0b1..Logic level 1
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*/
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#define GPIO_PDOR_PDO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO19_SHIFT)) & GPIO_PDOR_PDO19_MASK)
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#define GPIO_PDOR_PDO20_MASK (0x100000U)
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#define GPIO_PDOR_PDO20_SHIFT (20U)
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/*! PDO20 - Port Data Output
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* 0b0..Logic level 0
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* 0b1..Logic level 1
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*/
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#define GPIO_PDOR_PDO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO20_SHIFT)) & GPIO_PDOR_PDO20_MASK)
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#define GPIO_PDOR_PDO21_MASK (0x200000U)
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#define GPIO_PDOR_PDO21_SHIFT (21U)
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/*! PDO21 - Port Data Output
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* 0b0..Logic level 0
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* 0b1..Logic level 1
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*/
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#define GPIO_PDOR_PDO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO21_SHIFT)) & GPIO_PDOR_PDO21_MASK)
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#define GPIO_PDOR_PDO22_MASK (0x400000U)
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#define GPIO_PDOR_PDO22_SHIFT (22U)
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/*! PDO22 - Port Data Output
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* 0b0..Logic level 0
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* 0b1..Logic level 1
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*/
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#define GPIO_PDOR_PDO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO22_SHIFT)) & GPIO_PDOR_PDO22_MASK)
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#define GPIO_PDOR_PDO23_MASK (0x800000U)
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#define GPIO_PDOR_PDO23_SHIFT (23U)
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/*! PDO23 - Port Data Output
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* 0b0..Logic level 0
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* 0b1..Logic level 1
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*/
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#define GPIO_PDOR_PDO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO23_SHIFT)) & GPIO_PDOR_PDO23_MASK)
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#define GPIO_PDOR_PDO24_MASK (0x1000000U)
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#define GPIO_PDOR_PDO24_SHIFT (24U)
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/*! PDO24 - Port Data Output
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* 0b0..Logic level 0
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* 0b1..Logic level 1
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*/
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#define GPIO_PDOR_PDO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO24_SHIFT)) & GPIO_PDOR_PDO24_MASK)
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#define GPIO_PDOR_PDO25_MASK (0x2000000U)
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#define GPIO_PDOR_PDO25_SHIFT (25U)
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/*! PDO25 - Port Data Output
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* 0b0..Logic level 0
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* 0b1..Logic level 1
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*/
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#define GPIO_PDOR_PDO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO25_SHIFT)) & GPIO_PDOR_PDO25_MASK)
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#define GPIO_PDOR_PDO26_MASK (0x4000000U)
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#define GPIO_PDOR_PDO26_SHIFT (26U)
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/*! PDO26 - Port Data Output
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* 0b0..Logic level 0
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* 0b1..Logic level 1
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*/
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#define GPIO_PDOR_PDO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO26_SHIFT)) & GPIO_PDOR_PDO26_MASK)
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#define GPIO_PDOR_PDO27_MASK (0x8000000U)
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#define GPIO_PDOR_PDO27_SHIFT (27U)
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/*! PDO27 - Port Data Output
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* 0b0..Logic level 0
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* 0b1..Logic level 1
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*/
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#define GPIO_PDOR_PDO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO27_SHIFT)) & GPIO_PDOR_PDO27_MASK)
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#define GPIO_PDOR_PDO28_MASK (0x10000000U)
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#define GPIO_PDOR_PDO28_SHIFT (28U)
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/*! PDO28 - Port Data Output
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* 0b0..Logic level 0
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* 0b1..Logic level 1
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*/
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#define GPIO_PDOR_PDO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO28_SHIFT)) & GPIO_PDOR_PDO28_MASK)
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#define GPIO_PDOR_PDO29_MASK (0x20000000U)
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#define GPIO_PDOR_PDO29_SHIFT (29U)
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/*! PDO29 - Port Data Output
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* 0b0..Logic level 0
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* 0b1..Logic level 1
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*/
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#define GPIO_PDOR_PDO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO29_SHIFT)) & GPIO_PDOR_PDO29_MASK)
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#define GPIO_PDOR_PDO30_MASK (0x40000000U)
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#define GPIO_PDOR_PDO30_SHIFT (30U)
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/*! PDO30 - Port Data Output
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* 0b0..Logic level 0
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* 0b1..Logic level 1
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*/
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#define GPIO_PDOR_PDO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO30_SHIFT)) & GPIO_PDOR_PDO30_MASK)
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#define GPIO_PDOR_PDO31_MASK (0x80000000U)
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#define GPIO_PDOR_PDO31_SHIFT (31U)
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/*! PDO31 - Port Data Output
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* 0b0..Logic level 0
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* 0b1..Logic level 1
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*/
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#define GPIO_PDOR_PDO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO31_SHIFT)) & GPIO_PDOR_PDO31_MASK)
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/*! @} */
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/*! @name PSOR - Port Set Output */
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/*! @{ */
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#define GPIO_PSOR_PTSO0_MASK (0x1U)
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#define GPIO_PSOR_PTSO0_SHIFT (0U)
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/*! PTSO0 - Port Set Output
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* 0b0..No change
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* 0b1..Corresponding field in PDOR becomes 1
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*/
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#define GPIO_PSOR_PTSO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO0_SHIFT)) & GPIO_PSOR_PTSO0_MASK)
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#define GPIO_PSOR_PTSO1_MASK (0x2U)
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#define GPIO_PSOR_PTSO1_SHIFT (1U)
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/*! PTSO1 - Port Set Output
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* 0b0..No change
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* 0b1..Corresponding field in PDOR becomes 1
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*/
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#define GPIO_PSOR_PTSO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO1_SHIFT)) & GPIO_PSOR_PTSO1_MASK)
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#define GPIO_PSOR_PTSO2_MASK (0x4U)
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#define GPIO_PSOR_PTSO2_SHIFT (2U)
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/*! PTSO2 - Port Set Output
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* 0b0..No change
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* 0b1..Corresponding field in PDOR becomes 1
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*/
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#define GPIO_PSOR_PTSO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO2_SHIFT)) & GPIO_PSOR_PTSO2_MASK)
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#define GPIO_PSOR_PTSO3_MASK (0x8U)
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#define GPIO_PSOR_PTSO3_SHIFT (3U)
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/*! PTSO3 - Port Set Output
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* 0b0..No change
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* 0b1..Corresponding field in PDOR becomes 1
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*/
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#define GPIO_PSOR_PTSO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO3_SHIFT)) & GPIO_PSOR_PTSO3_MASK)
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#define GPIO_PSOR_PTSO4_MASK (0x10U)
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#define GPIO_PSOR_PTSO4_SHIFT (4U)
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/*! PTSO4 - Port Set Output
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* 0b0..No change
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* 0b1..Corresponding field in PDOR becomes 1
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*/
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#define GPIO_PSOR_PTSO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO4_SHIFT)) & GPIO_PSOR_PTSO4_MASK)
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#define GPIO_PSOR_PTSO5_MASK (0x20U)
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#define GPIO_PSOR_PTSO5_SHIFT (5U)
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/*! PTSO5 - Port Set Output
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* 0b0..No change
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* 0b1..Corresponding field in PDOR becomes 1
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*/
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#define GPIO_PSOR_PTSO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO5_SHIFT)) & GPIO_PSOR_PTSO5_MASK)
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#define GPIO_PSOR_PTSO6_MASK (0x40U)
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#define GPIO_PSOR_PTSO6_SHIFT (6U)
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/*! PTSO6 - Port Set Output
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* 0b0..No change
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* 0b1..Corresponding field in PDOR becomes 1
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*/
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#define GPIO_PSOR_PTSO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO6_SHIFT)) & GPIO_PSOR_PTSO6_MASK)
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#define GPIO_PSOR_PTSO7_MASK (0x80U)
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#define GPIO_PSOR_PTSO7_SHIFT (7U)
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/*! PTSO7 - Port Set Output
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* 0b0..No change
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* 0b1..Corresponding field in PDOR becomes 1
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*/
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#define GPIO_PSOR_PTSO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO7_SHIFT)) & GPIO_PSOR_PTSO7_MASK)
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#define GPIO_PSOR_PTSO8_MASK (0x100U)
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#define GPIO_PSOR_PTSO8_SHIFT (8U)
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/*! PTSO8 - Port Set Output
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* 0b0..No change
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* 0b1..Corresponding field in PDOR becomes 1
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*/
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#define GPIO_PSOR_PTSO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO8_SHIFT)) & GPIO_PSOR_PTSO8_MASK)
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#define GPIO_PSOR_PTSO9_MASK (0x200U)
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#define GPIO_PSOR_PTSO9_SHIFT (9U)
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/*! PTSO9 - Port Set Output
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* 0b0..No change
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* 0b1..Corresponding field in PDOR becomes 1
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*/
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#define GPIO_PSOR_PTSO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO9_SHIFT)) & GPIO_PSOR_PTSO9_MASK)
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#define GPIO_PSOR_PTSO10_MASK (0x400U)
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#define GPIO_PSOR_PTSO10_SHIFT (10U)
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/*! PTSO10 - Port Set Output
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* 0b0..No change
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* 0b1..Corresponding field in PDOR becomes 1
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*/
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#define GPIO_PSOR_PTSO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO10_SHIFT)) & GPIO_PSOR_PTSO10_MASK)
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#define GPIO_PSOR_PTSO11_MASK (0x800U)
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#define GPIO_PSOR_PTSO11_SHIFT (11U)
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/*! PTSO11 - Port Set Output
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* 0b0..No change
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* 0b1..Corresponding field in PDOR becomes 1
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*/
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#define GPIO_PSOR_PTSO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO11_SHIFT)) & GPIO_PSOR_PTSO11_MASK)
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#define GPIO_PSOR_PTSO12_MASK (0x1000U)
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#define GPIO_PSOR_PTSO12_SHIFT (12U)
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/*! PTSO12 - Port Set Output
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* 0b0..No change
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* 0b1..Corresponding field in PDOR becomes 1
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*/
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#define GPIO_PSOR_PTSO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO12_SHIFT)) & GPIO_PSOR_PTSO12_MASK)
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#define GPIO_PSOR_PTSO13_MASK (0x2000U)
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#define GPIO_PSOR_PTSO13_SHIFT (13U)
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/*! PTSO13 - Port Set Output
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|
* 0b0..No change
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|
* 0b1..Corresponding field in PDOR becomes 1
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*/
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#define GPIO_PSOR_PTSO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO13_SHIFT)) & GPIO_PSOR_PTSO13_MASK)
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#define GPIO_PSOR_PTSO14_MASK (0x4000U)
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#define GPIO_PSOR_PTSO14_SHIFT (14U)
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/*! PTSO14 - Port Set Output
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|
* 0b0..No change
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|
* 0b1..Corresponding field in PDOR becomes 1
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*/
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#define GPIO_PSOR_PTSO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO14_SHIFT)) & GPIO_PSOR_PTSO14_MASK)
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#define GPIO_PSOR_PTSO15_MASK (0x8000U)
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#define GPIO_PSOR_PTSO15_SHIFT (15U)
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/*! PTSO15 - Port Set Output
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|
* 0b0..No change
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|
* 0b1..Corresponding field in PDOR becomes 1
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*/
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#define GPIO_PSOR_PTSO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO15_SHIFT)) & GPIO_PSOR_PTSO15_MASK)
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#define GPIO_PSOR_PTSO16_MASK (0x10000U)
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#define GPIO_PSOR_PTSO16_SHIFT (16U)
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/*! PTSO16 - Port Set Output
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|
* 0b0..No change
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* 0b1..Corresponding field in PDOR becomes 1
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*/
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#define GPIO_PSOR_PTSO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO16_SHIFT)) & GPIO_PSOR_PTSO16_MASK)
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#define GPIO_PSOR_PTSO17_MASK (0x20000U)
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#define GPIO_PSOR_PTSO17_SHIFT (17U)
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/*! PTSO17 - Port Set Output
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|
* 0b0..No change
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|
* 0b1..Corresponding field in PDOR becomes 1
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*/
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#define GPIO_PSOR_PTSO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO17_SHIFT)) & GPIO_PSOR_PTSO17_MASK)
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#define GPIO_PSOR_PTSO18_MASK (0x40000U)
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#define GPIO_PSOR_PTSO18_SHIFT (18U)
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/*! PTSO18 - Port Set Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 1
|
|
*/
|
|
#define GPIO_PSOR_PTSO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO18_SHIFT)) & GPIO_PSOR_PTSO18_MASK)
|
|
|
|
#define GPIO_PSOR_PTSO19_MASK (0x80000U)
|
|
#define GPIO_PSOR_PTSO19_SHIFT (19U)
|
|
/*! PTSO19 - Port Set Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 1
|
|
*/
|
|
#define GPIO_PSOR_PTSO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO19_SHIFT)) & GPIO_PSOR_PTSO19_MASK)
|
|
|
|
#define GPIO_PSOR_PTSO20_MASK (0x100000U)
|
|
#define GPIO_PSOR_PTSO20_SHIFT (20U)
|
|
/*! PTSO20 - Port Set Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 1
|
|
*/
|
|
#define GPIO_PSOR_PTSO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO20_SHIFT)) & GPIO_PSOR_PTSO20_MASK)
|
|
|
|
#define GPIO_PSOR_PTSO21_MASK (0x200000U)
|
|
#define GPIO_PSOR_PTSO21_SHIFT (21U)
|
|
/*! PTSO21 - Port Set Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 1
|
|
*/
|
|
#define GPIO_PSOR_PTSO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO21_SHIFT)) & GPIO_PSOR_PTSO21_MASK)
|
|
|
|
#define GPIO_PSOR_PTSO22_MASK (0x400000U)
|
|
#define GPIO_PSOR_PTSO22_SHIFT (22U)
|
|
/*! PTSO22 - Port Set Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 1
|
|
*/
|
|
#define GPIO_PSOR_PTSO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO22_SHIFT)) & GPIO_PSOR_PTSO22_MASK)
|
|
|
|
#define GPIO_PSOR_PTSO23_MASK (0x800000U)
|
|
#define GPIO_PSOR_PTSO23_SHIFT (23U)
|
|
/*! PTSO23 - Port Set Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 1
|
|
*/
|
|
#define GPIO_PSOR_PTSO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO23_SHIFT)) & GPIO_PSOR_PTSO23_MASK)
|
|
|
|
#define GPIO_PSOR_PTSO24_MASK (0x1000000U)
|
|
#define GPIO_PSOR_PTSO24_SHIFT (24U)
|
|
/*! PTSO24 - Port Set Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 1
|
|
*/
|
|
#define GPIO_PSOR_PTSO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO24_SHIFT)) & GPIO_PSOR_PTSO24_MASK)
|
|
|
|
#define GPIO_PSOR_PTSO25_MASK (0x2000000U)
|
|
#define GPIO_PSOR_PTSO25_SHIFT (25U)
|
|
/*! PTSO25 - Port Set Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 1
|
|
*/
|
|
#define GPIO_PSOR_PTSO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO25_SHIFT)) & GPIO_PSOR_PTSO25_MASK)
|
|
|
|
#define GPIO_PSOR_PTSO26_MASK (0x4000000U)
|
|
#define GPIO_PSOR_PTSO26_SHIFT (26U)
|
|
/*! PTSO26 - Port Set Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 1
|
|
*/
|
|
#define GPIO_PSOR_PTSO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO26_SHIFT)) & GPIO_PSOR_PTSO26_MASK)
|
|
|
|
#define GPIO_PSOR_PTSO27_MASK (0x8000000U)
|
|
#define GPIO_PSOR_PTSO27_SHIFT (27U)
|
|
/*! PTSO27 - Port Set Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 1
|
|
*/
|
|
#define GPIO_PSOR_PTSO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO27_SHIFT)) & GPIO_PSOR_PTSO27_MASK)
|
|
|
|
#define GPIO_PSOR_PTSO28_MASK (0x10000000U)
|
|
#define GPIO_PSOR_PTSO28_SHIFT (28U)
|
|
/*! PTSO28 - Port Set Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 1
|
|
*/
|
|
#define GPIO_PSOR_PTSO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO28_SHIFT)) & GPIO_PSOR_PTSO28_MASK)
|
|
|
|
#define GPIO_PSOR_PTSO29_MASK (0x20000000U)
|
|
#define GPIO_PSOR_PTSO29_SHIFT (29U)
|
|
/*! PTSO29 - Port Set Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 1
|
|
*/
|
|
#define GPIO_PSOR_PTSO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO29_SHIFT)) & GPIO_PSOR_PTSO29_MASK)
|
|
|
|
#define GPIO_PSOR_PTSO30_MASK (0x40000000U)
|
|
#define GPIO_PSOR_PTSO30_SHIFT (30U)
|
|
/*! PTSO30 - Port Set Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 1
|
|
*/
|
|
#define GPIO_PSOR_PTSO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO30_SHIFT)) & GPIO_PSOR_PTSO30_MASK)
|
|
|
|
#define GPIO_PSOR_PTSO31_MASK (0x80000000U)
|
|
#define GPIO_PSOR_PTSO31_SHIFT (31U)
|
|
/*! PTSO31 - Port Set Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 1
|
|
*/
|
|
#define GPIO_PSOR_PTSO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO31_SHIFT)) & GPIO_PSOR_PTSO31_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PCOR - Port Clear Output */
|
|
/*! @{ */
|
|
|
|
#define GPIO_PCOR_PTCO0_MASK (0x1U)
|
|
#define GPIO_PCOR_PTCO0_SHIFT (0U)
|
|
/*! PTCO0 - Port Clear Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 0
|
|
*/
|
|
#define GPIO_PCOR_PTCO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO0_SHIFT)) & GPIO_PCOR_PTCO0_MASK)
|
|
|
|
#define GPIO_PCOR_PTCO1_MASK (0x2U)
|
|
#define GPIO_PCOR_PTCO1_SHIFT (1U)
|
|
/*! PTCO1 - Port Clear Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 0
|
|
*/
|
|
#define GPIO_PCOR_PTCO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO1_SHIFT)) & GPIO_PCOR_PTCO1_MASK)
|
|
|
|
#define GPIO_PCOR_PTCO2_MASK (0x4U)
|
|
#define GPIO_PCOR_PTCO2_SHIFT (2U)
|
|
/*! PTCO2 - Port Clear Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 0
|
|
*/
|
|
#define GPIO_PCOR_PTCO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO2_SHIFT)) & GPIO_PCOR_PTCO2_MASK)
|
|
|
|
#define GPIO_PCOR_PTCO3_MASK (0x8U)
|
|
#define GPIO_PCOR_PTCO3_SHIFT (3U)
|
|
/*! PTCO3 - Port Clear Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 0
|
|
*/
|
|
#define GPIO_PCOR_PTCO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO3_SHIFT)) & GPIO_PCOR_PTCO3_MASK)
|
|
|
|
#define GPIO_PCOR_PTCO4_MASK (0x10U)
|
|
#define GPIO_PCOR_PTCO4_SHIFT (4U)
|
|
/*! PTCO4 - Port Clear Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 0
|
|
*/
|
|
#define GPIO_PCOR_PTCO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO4_SHIFT)) & GPIO_PCOR_PTCO4_MASK)
|
|
|
|
#define GPIO_PCOR_PTCO5_MASK (0x20U)
|
|
#define GPIO_PCOR_PTCO5_SHIFT (5U)
|
|
/*! PTCO5 - Port Clear Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 0
|
|
*/
|
|
#define GPIO_PCOR_PTCO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO5_SHIFT)) & GPIO_PCOR_PTCO5_MASK)
|
|
|
|
#define GPIO_PCOR_PTCO6_MASK (0x40U)
|
|
#define GPIO_PCOR_PTCO6_SHIFT (6U)
|
|
/*! PTCO6 - Port Clear Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 0
|
|
*/
|
|
#define GPIO_PCOR_PTCO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO6_SHIFT)) & GPIO_PCOR_PTCO6_MASK)
|
|
|
|
#define GPIO_PCOR_PTCO7_MASK (0x80U)
|
|
#define GPIO_PCOR_PTCO7_SHIFT (7U)
|
|
/*! PTCO7 - Port Clear Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 0
|
|
*/
|
|
#define GPIO_PCOR_PTCO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO7_SHIFT)) & GPIO_PCOR_PTCO7_MASK)
|
|
|
|
#define GPIO_PCOR_PTCO8_MASK (0x100U)
|
|
#define GPIO_PCOR_PTCO8_SHIFT (8U)
|
|
/*! PTCO8 - Port Clear Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 0
|
|
*/
|
|
#define GPIO_PCOR_PTCO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO8_SHIFT)) & GPIO_PCOR_PTCO8_MASK)
|
|
|
|
#define GPIO_PCOR_PTCO9_MASK (0x200U)
|
|
#define GPIO_PCOR_PTCO9_SHIFT (9U)
|
|
/*! PTCO9 - Port Clear Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 0
|
|
*/
|
|
#define GPIO_PCOR_PTCO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO9_SHIFT)) & GPIO_PCOR_PTCO9_MASK)
|
|
|
|
#define GPIO_PCOR_PTCO10_MASK (0x400U)
|
|
#define GPIO_PCOR_PTCO10_SHIFT (10U)
|
|
/*! PTCO10 - Port Clear Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 0
|
|
*/
|
|
#define GPIO_PCOR_PTCO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO10_SHIFT)) & GPIO_PCOR_PTCO10_MASK)
|
|
|
|
#define GPIO_PCOR_PTCO11_MASK (0x800U)
|
|
#define GPIO_PCOR_PTCO11_SHIFT (11U)
|
|
/*! PTCO11 - Port Clear Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 0
|
|
*/
|
|
#define GPIO_PCOR_PTCO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO11_SHIFT)) & GPIO_PCOR_PTCO11_MASK)
|
|
|
|
#define GPIO_PCOR_PTCO12_MASK (0x1000U)
|
|
#define GPIO_PCOR_PTCO12_SHIFT (12U)
|
|
/*! PTCO12 - Port Clear Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 0
|
|
*/
|
|
#define GPIO_PCOR_PTCO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO12_SHIFT)) & GPIO_PCOR_PTCO12_MASK)
|
|
|
|
#define GPIO_PCOR_PTCO13_MASK (0x2000U)
|
|
#define GPIO_PCOR_PTCO13_SHIFT (13U)
|
|
/*! PTCO13 - Port Clear Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 0
|
|
*/
|
|
#define GPIO_PCOR_PTCO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO13_SHIFT)) & GPIO_PCOR_PTCO13_MASK)
|
|
|
|
#define GPIO_PCOR_PTCO14_MASK (0x4000U)
|
|
#define GPIO_PCOR_PTCO14_SHIFT (14U)
|
|
/*! PTCO14 - Port Clear Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 0
|
|
*/
|
|
#define GPIO_PCOR_PTCO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO14_SHIFT)) & GPIO_PCOR_PTCO14_MASK)
|
|
|
|
#define GPIO_PCOR_PTCO15_MASK (0x8000U)
|
|
#define GPIO_PCOR_PTCO15_SHIFT (15U)
|
|
/*! PTCO15 - Port Clear Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 0
|
|
*/
|
|
#define GPIO_PCOR_PTCO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO15_SHIFT)) & GPIO_PCOR_PTCO15_MASK)
|
|
|
|
#define GPIO_PCOR_PTCO16_MASK (0x10000U)
|
|
#define GPIO_PCOR_PTCO16_SHIFT (16U)
|
|
/*! PTCO16 - Port Clear Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 0
|
|
*/
|
|
#define GPIO_PCOR_PTCO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO16_SHIFT)) & GPIO_PCOR_PTCO16_MASK)
|
|
|
|
#define GPIO_PCOR_PTCO17_MASK (0x20000U)
|
|
#define GPIO_PCOR_PTCO17_SHIFT (17U)
|
|
/*! PTCO17 - Port Clear Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 0
|
|
*/
|
|
#define GPIO_PCOR_PTCO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO17_SHIFT)) & GPIO_PCOR_PTCO17_MASK)
|
|
|
|
#define GPIO_PCOR_PTCO18_MASK (0x40000U)
|
|
#define GPIO_PCOR_PTCO18_SHIFT (18U)
|
|
/*! PTCO18 - Port Clear Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 0
|
|
*/
|
|
#define GPIO_PCOR_PTCO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO18_SHIFT)) & GPIO_PCOR_PTCO18_MASK)
|
|
|
|
#define GPIO_PCOR_PTCO19_MASK (0x80000U)
|
|
#define GPIO_PCOR_PTCO19_SHIFT (19U)
|
|
/*! PTCO19 - Port Clear Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 0
|
|
*/
|
|
#define GPIO_PCOR_PTCO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO19_SHIFT)) & GPIO_PCOR_PTCO19_MASK)
|
|
|
|
#define GPIO_PCOR_PTCO20_MASK (0x100000U)
|
|
#define GPIO_PCOR_PTCO20_SHIFT (20U)
|
|
/*! PTCO20 - Port Clear Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 0
|
|
*/
|
|
#define GPIO_PCOR_PTCO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO20_SHIFT)) & GPIO_PCOR_PTCO20_MASK)
|
|
|
|
#define GPIO_PCOR_PTCO21_MASK (0x200000U)
|
|
#define GPIO_PCOR_PTCO21_SHIFT (21U)
|
|
/*! PTCO21 - Port Clear Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 0
|
|
*/
|
|
#define GPIO_PCOR_PTCO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO21_SHIFT)) & GPIO_PCOR_PTCO21_MASK)
|
|
|
|
#define GPIO_PCOR_PTCO22_MASK (0x400000U)
|
|
#define GPIO_PCOR_PTCO22_SHIFT (22U)
|
|
/*! PTCO22 - Port Clear Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 0
|
|
*/
|
|
#define GPIO_PCOR_PTCO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO22_SHIFT)) & GPIO_PCOR_PTCO22_MASK)
|
|
|
|
#define GPIO_PCOR_PTCO23_MASK (0x800000U)
|
|
#define GPIO_PCOR_PTCO23_SHIFT (23U)
|
|
/*! PTCO23 - Port Clear Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 0
|
|
*/
|
|
#define GPIO_PCOR_PTCO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO23_SHIFT)) & GPIO_PCOR_PTCO23_MASK)
|
|
|
|
#define GPIO_PCOR_PTCO24_MASK (0x1000000U)
|
|
#define GPIO_PCOR_PTCO24_SHIFT (24U)
|
|
/*! PTCO24 - Port Clear Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 0
|
|
*/
|
|
#define GPIO_PCOR_PTCO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO24_SHIFT)) & GPIO_PCOR_PTCO24_MASK)
|
|
|
|
#define GPIO_PCOR_PTCO25_MASK (0x2000000U)
|
|
#define GPIO_PCOR_PTCO25_SHIFT (25U)
|
|
/*! PTCO25 - Port Clear Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 0
|
|
*/
|
|
#define GPIO_PCOR_PTCO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO25_SHIFT)) & GPIO_PCOR_PTCO25_MASK)
|
|
|
|
#define GPIO_PCOR_PTCO26_MASK (0x4000000U)
|
|
#define GPIO_PCOR_PTCO26_SHIFT (26U)
|
|
/*! PTCO26 - Port Clear Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 0
|
|
*/
|
|
#define GPIO_PCOR_PTCO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO26_SHIFT)) & GPIO_PCOR_PTCO26_MASK)
|
|
|
|
#define GPIO_PCOR_PTCO27_MASK (0x8000000U)
|
|
#define GPIO_PCOR_PTCO27_SHIFT (27U)
|
|
/*! PTCO27 - Port Clear Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 0
|
|
*/
|
|
#define GPIO_PCOR_PTCO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO27_SHIFT)) & GPIO_PCOR_PTCO27_MASK)
|
|
|
|
#define GPIO_PCOR_PTCO28_MASK (0x10000000U)
|
|
#define GPIO_PCOR_PTCO28_SHIFT (28U)
|
|
/*! PTCO28 - Port Clear Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 0
|
|
*/
|
|
#define GPIO_PCOR_PTCO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO28_SHIFT)) & GPIO_PCOR_PTCO28_MASK)
|
|
|
|
#define GPIO_PCOR_PTCO29_MASK (0x20000000U)
|
|
#define GPIO_PCOR_PTCO29_SHIFT (29U)
|
|
/*! PTCO29 - Port Clear Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 0
|
|
*/
|
|
#define GPIO_PCOR_PTCO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO29_SHIFT)) & GPIO_PCOR_PTCO29_MASK)
|
|
|
|
#define GPIO_PCOR_PTCO30_MASK (0x40000000U)
|
|
#define GPIO_PCOR_PTCO30_SHIFT (30U)
|
|
/*! PTCO30 - Port Clear Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 0
|
|
*/
|
|
#define GPIO_PCOR_PTCO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO30_SHIFT)) & GPIO_PCOR_PTCO30_MASK)
|
|
|
|
#define GPIO_PCOR_PTCO31_MASK (0x80000000U)
|
|
#define GPIO_PCOR_PTCO31_SHIFT (31U)
|
|
/*! PTCO31 - Port Clear Output
|
|
* 0b0..No change
|
|
* 0b1..Corresponding field in PDOR becomes 0
|
|
*/
|
|
#define GPIO_PCOR_PTCO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO31_SHIFT)) & GPIO_PCOR_PTCO31_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PTOR - Port Toggle Output */
|
|
/*! @{ */
|
|
|
|
#define GPIO_PTOR_PTTO0_MASK (0x1U)
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#define GPIO_PTOR_PTTO0_SHIFT (0U)
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/*! PTTO0 - Port Toggle Output
|
|
* 0b0..No change
|
|
* 0b1..Set to the inverse of its current logic state
|
|
*/
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#define GPIO_PTOR_PTTO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO0_SHIFT)) & GPIO_PTOR_PTTO0_MASK)
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#define GPIO_PTOR_PTTO1_MASK (0x2U)
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#define GPIO_PTOR_PTTO1_SHIFT (1U)
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/*! PTTO1 - Port Toggle Output
|
|
* 0b0..No change
|
|
* 0b1..Set to the inverse of its current logic state
|
|
*/
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#define GPIO_PTOR_PTTO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO1_SHIFT)) & GPIO_PTOR_PTTO1_MASK)
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#define GPIO_PTOR_PTTO2_MASK (0x4U)
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#define GPIO_PTOR_PTTO2_SHIFT (2U)
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/*! PTTO2 - Port Toggle Output
|
|
* 0b0..No change
|
|
* 0b1..Set to the inverse of its current logic state
|
|
*/
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#define GPIO_PTOR_PTTO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO2_SHIFT)) & GPIO_PTOR_PTTO2_MASK)
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#define GPIO_PTOR_PTTO3_MASK (0x8U)
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#define GPIO_PTOR_PTTO3_SHIFT (3U)
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/*! PTTO3 - Port Toggle Output
|
|
* 0b0..No change
|
|
* 0b1..Set to the inverse of its current logic state
|
|
*/
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#define GPIO_PTOR_PTTO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO3_SHIFT)) & GPIO_PTOR_PTTO3_MASK)
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#define GPIO_PTOR_PTTO4_MASK (0x10U)
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#define GPIO_PTOR_PTTO4_SHIFT (4U)
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/*! PTTO4 - Port Toggle Output
|
|
* 0b0..No change
|
|
* 0b1..Set to the inverse of its current logic state
|
|
*/
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#define GPIO_PTOR_PTTO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO4_SHIFT)) & GPIO_PTOR_PTTO4_MASK)
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#define GPIO_PTOR_PTTO5_MASK (0x20U)
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#define GPIO_PTOR_PTTO5_SHIFT (5U)
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/*! PTTO5 - Port Toggle Output
|
|
* 0b0..No change
|
|
* 0b1..Set to the inverse of its current logic state
|
|
*/
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#define GPIO_PTOR_PTTO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO5_SHIFT)) & GPIO_PTOR_PTTO5_MASK)
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#define GPIO_PTOR_PTTO6_MASK (0x40U)
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#define GPIO_PTOR_PTTO6_SHIFT (6U)
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/*! PTTO6 - Port Toggle Output
|
|
* 0b0..No change
|
|
* 0b1..Set to the inverse of its current logic state
|
|
*/
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#define GPIO_PTOR_PTTO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO6_SHIFT)) & GPIO_PTOR_PTTO6_MASK)
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#define GPIO_PTOR_PTTO7_MASK (0x80U)
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#define GPIO_PTOR_PTTO7_SHIFT (7U)
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/*! PTTO7 - Port Toggle Output
|
|
* 0b0..No change
|
|
* 0b1..Set to the inverse of its current logic state
|
|
*/
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#define GPIO_PTOR_PTTO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO7_SHIFT)) & GPIO_PTOR_PTTO7_MASK)
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#define GPIO_PTOR_PTTO8_MASK (0x100U)
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#define GPIO_PTOR_PTTO8_SHIFT (8U)
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/*! PTTO8 - Port Toggle Output
|
|
* 0b0..No change
|
|
* 0b1..Set to the inverse of its current logic state
|
|
*/
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#define GPIO_PTOR_PTTO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO8_SHIFT)) & GPIO_PTOR_PTTO8_MASK)
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#define GPIO_PTOR_PTTO9_MASK (0x200U)
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#define GPIO_PTOR_PTTO9_SHIFT (9U)
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/*! PTTO9 - Port Toggle Output
|
|
* 0b0..No change
|
|
* 0b1..Set to the inverse of its current logic state
|
|
*/
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#define GPIO_PTOR_PTTO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO9_SHIFT)) & GPIO_PTOR_PTTO9_MASK)
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#define GPIO_PTOR_PTTO10_MASK (0x400U)
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#define GPIO_PTOR_PTTO10_SHIFT (10U)
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/*! PTTO10 - Port Toggle Output
|
|
* 0b0..No change
|
|
* 0b1..Set to the inverse of its current logic state
|
|
*/
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#define GPIO_PTOR_PTTO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO10_SHIFT)) & GPIO_PTOR_PTTO10_MASK)
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#define GPIO_PTOR_PTTO11_MASK (0x800U)
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#define GPIO_PTOR_PTTO11_SHIFT (11U)
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/*! PTTO11 - Port Toggle Output
|
|
* 0b0..No change
|
|
* 0b1..Set to the inverse of its current logic state
|
|
*/
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|
#define GPIO_PTOR_PTTO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO11_SHIFT)) & GPIO_PTOR_PTTO11_MASK)
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#define GPIO_PTOR_PTTO12_MASK (0x1000U)
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#define GPIO_PTOR_PTTO12_SHIFT (12U)
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/*! PTTO12 - Port Toggle Output
|
|
* 0b0..No change
|
|
* 0b1..Set to the inverse of its current logic state
|
|
*/
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|
#define GPIO_PTOR_PTTO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO12_SHIFT)) & GPIO_PTOR_PTTO12_MASK)
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|
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#define GPIO_PTOR_PTTO13_MASK (0x2000U)
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|
#define GPIO_PTOR_PTTO13_SHIFT (13U)
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|
/*! PTTO13 - Port Toggle Output
|
|
* 0b0..No change
|
|
* 0b1..Set to the inverse of its current logic state
|
|
*/
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|
#define GPIO_PTOR_PTTO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO13_SHIFT)) & GPIO_PTOR_PTTO13_MASK)
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|
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#define GPIO_PTOR_PTTO14_MASK (0x4000U)
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|
#define GPIO_PTOR_PTTO14_SHIFT (14U)
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/*! PTTO14 - Port Toggle Output
|
|
* 0b0..No change
|
|
* 0b1..Set to the inverse of its current logic state
|
|
*/
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|
#define GPIO_PTOR_PTTO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO14_SHIFT)) & GPIO_PTOR_PTTO14_MASK)
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|
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#define GPIO_PTOR_PTTO15_MASK (0x8000U)
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|
#define GPIO_PTOR_PTTO15_SHIFT (15U)
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|
/*! PTTO15 - Port Toggle Output
|
|
* 0b0..No change
|
|
* 0b1..Set to the inverse of its current logic state
|
|
*/
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|
#define GPIO_PTOR_PTTO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO15_SHIFT)) & GPIO_PTOR_PTTO15_MASK)
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|
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#define GPIO_PTOR_PTTO16_MASK (0x10000U)
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|
#define GPIO_PTOR_PTTO16_SHIFT (16U)
|
|
/*! PTTO16 - Port Toggle Output
|
|
* 0b0..No change
|
|
* 0b1..Set to the inverse of its current logic state
|
|
*/
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|
#define GPIO_PTOR_PTTO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO16_SHIFT)) & GPIO_PTOR_PTTO16_MASK)
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|
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|
#define GPIO_PTOR_PTTO17_MASK (0x20000U)
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|
#define GPIO_PTOR_PTTO17_SHIFT (17U)
|
|
/*! PTTO17 - Port Toggle Output
|
|
* 0b0..No change
|
|
* 0b1..Set to the inverse of its current logic state
|
|
*/
|
|
#define GPIO_PTOR_PTTO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO17_SHIFT)) & GPIO_PTOR_PTTO17_MASK)
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|
|
|
#define GPIO_PTOR_PTTO18_MASK (0x40000U)
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|
#define GPIO_PTOR_PTTO18_SHIFT (18U)
|
|
/*! PTTO18 - Port Toggle Output
|
|
* 0b0..No change
|
|
* 0b1..Set to the inverse of its current logic state
|
|
*/
|
|
#define GPIO_PTOR_PTTO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO18_SHIFT)) & GPIO_PTOR_PTTO18_MASK)
|
|
|
|
#define GPIO_PTOR_PTTO19_MASK (0x80000U)
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|
#define GPIO_PTOR_PTTO19_SHIFT (19U)
|
|
/*! PTTO19 - Port Toggle Output
|
|
* 0b0..No change
|
|
* 0b1..Set to the inverse of its current logic state
|
|
*/
|
|
#define GPIO_PTOR_PTTO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO19_SHIFT)) & GPIO_PTOR_PTTO19_MASK)
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|
|
|
#define GPIO_PTOR_PTTO20_MASK (0x100000U)
|
|
#define GPIO_PTOR_PTTO20_SHIFT (20U)
|
|
/*! PTTO20 - Port Toggle Output
|
|
* 0b0..No change
|
|
* 0b1..Set to the inverse of its current logic state
|
|
*/
|
|
#define GPIO_PTOR_PTTO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO20_SHIFT)) & GPIO_PTOR_PTTO20_MASK)
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|
|
|
#define GPIO_PTOR_PTTO21_MASK (0x200000U)
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|
#define GPIO_PTOR_PTTO21_SHIFT (21U)
|
|
/*! PTTO21 - Port Toggle Output
|
|
* 0b0..No change
|
|
* 0b1..Set to the inverse of its current logic state
|
|
*/
|
|
#define GPIO_PTOR_PTTO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO21_SHIFT)) & GPIO_PTOR_PTTO21_MASK)
|
|
|
|
#define GPIO_PTOR_PTTO22_MASK (0x400000U)
|
|
#define GPIO_PTOR_PTTO22_SHIFT (22U)
|
|
/*! PTTO22 - Port Toggle Output
|
|
* 0b0..No change
|
|
* 0b1..Set to the inverse of its current logic state
|
|
*/
|
|
#define GPIO_PTOR_PTTO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO22_SHIFT)) & GPIO_PTOR_PTTO22_MASK)
|
|
|
|
#define GPIO_PTOR_PTTO23_MASK (0x800000U)
|
|
#define GPIO_PTOR_PTTO23_SHIFT (23U)
|
|
/*! PTTO23 - Port Toggle Output
|
|
* 0b0..No change
|
|
* 0b1..Set to the inverse of its current logic state
|
|
*/
|
|
#define GPIO_PTOR_PTTO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO23_SHIFT)) & GPIO_PTOR_PTTO23_MASK)
|
|
|
|
#define GPIO_PTOR_PTTO24_MASK (0x1000000U)
|
|
#define GPIO_PTOR_PTTO24_SHIFT (24U)
|
|
/*! PTTO24 - Port Toggle Output
|
|
* 0b0..No change
|
|
* 0b1..Set to the inverse of its current logic state
|
|
*/
|
|
#define GPIO_PTOR_PTTO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO24_SHIFT)) & GPIO_PTOR_PTTO24_MASK)
|
|
|
|
#define GPIO_PTOR_PTTO25_MASK (0x2000000U)
|
|
#define GPIO_PTOR_PTTO25_SHIFT (25U)
|
|
/*! PTTO25 - Port Toggle Output
|
|
* 0b0..No change
|
|
* 0b1..Set to the inverse of its current logic state
|
|
*/
|
|
#define GPIO_PTOR_PTTO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO25_SHIFT)) & GPIO_PTOR_PTTO25_MASK)
|
|
|
|
#define GPIO_PTOR_PTTO26_MASK (0x4000000U)
|
|
#define GPIO_PTOR_PTTO26_SHIFT (26U)
|
|
/*! PTTO26 - Port Toggle Output
|
|
* 0b0..No change
|
|
* 0b1..Set to the inverse of its current logic state
|
|
*/
|
|
#define GPIO_PTOR_PTTO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO26_SHIFT)) & GPIO_PTOR_PTTO26_MASK)
|
|
|
|
#define GPIO_PTOR_PTTO27_MASK (0x8000000U)
|
|
#define GPIO_PTOR_PTTO27_SHIFT (27U)
|
|
/*! PTTO27 - Port Toggle Output
|
|
* 0b0..No change
|
|
* 0b1..Set to the inverse of its current logic state
|
|
*/
|
|
#define GPIO_PTOR_PTTO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO27_SHIFT)) & GPIO_PTOR_PTTO27_MASK)
|
|
|
|
#define GPIO_PTOR_PTTO28_MASK (0x10000000U)
|
|
#define GPIO_PTOR_PTTO28_SHIFT (28U)
|
|
/*! PTTO28 - Port Toggle Output
|
|
* 0b0..No change
|
|
* 0b1..Set to the inverse of its current logic state
|
|
*/
|
|
#define GPIO_PTOR_PTTO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO28_SHIFT)) & GPIO_PTOR_PTTO28_MASK)
|
|
|
|
#define GPIO_PTOR_PTTO29_MASK (0x20000000U)
|
|
#define GPIO_PTOR_PTTO29_SHIFT (29U)
|
|
/*! PTTO29 - Port Toggle Output
|
|
* 0b0..No change
|
|
* 0b1..Set to the inverse of its current logic state
|
|
*/
|
|
#define GPIO_PTOR_PTTO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO29_SHIFT)) & GPIO_PTOR_PTTO29_MASK)
|
|
|
|
#define GPIO_PTOR_PTTO30_MASK (0x40000000U)
|
|
#define GPIO_PTOR_PTTO30_SHIFT (30U)
|
|
/*! PTTO30 - Port Toggle Output
|
|
* 0b0..No change
|
|
* 0b1..Set to the inverse of its current logic state
|
|
*/
|
|
#define GPIO_PTOR_PTTO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO30_SHIFT)) & GPIO_PTOR_PTTO30_MASK)
|
|
|
|
#define GPIO_PTOR_PTTO31_MASK (0x80000000U)
|
|
#define GPIO_PTOR_PTTO31_SHIFT (31U)
|
|
/*! PTTO31 - Port Toggle Output
|
|
* 0b0..No change
|
|
* 0b1..Set to the inverse of its current logic state
|
|
*/
|
|
#define GPIO_PTOR_PTTO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO31_SHIFT)) & GPIO_PTOR_PTTO31_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PDIR - Port Data Input */
|
|
/*! @{ */
|
|
|
|
#define GPIO_PDIR_PDI0_MASK (0x1U)
|
|
#define GPIO_PDIR_PDI0_SHIFT (0U)
|
|
/*! PDI0 - Port Data Input
|
|
* 0b0..Logic 0
|
|
* 0b1..Logic 1
|
|
*/
|
|
#define GPIO_PDIR_PDI0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI0_SHIFT)) & GPIO_PDIR_PDI0_MASK)
|
|
|
|
#define GPIO_PDIR_PDI1_MASK (0x2U)
|
|
#define GPIO_PDIR_PDI1_SHIFT (1U)
|
|
/*! PDI1 - Port Data Input
|
|
* 0b0..Logic 0
|
|
* 0b1..Logic 1
|
|
*/
|
|
#define GPIO_PDIR_PDI1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI1_SHIFT)) & GPIO_PDIR_PDI1_MASK)
|
|
|
|
#define GPIO_PDIR_PDI2_MASK (0x4U)
|
|
#define GPIO_PDIR_PDI2_SHIFT (2U)
|
|
/*! PDI2 - Port Data Input
|
|
* 0b0..Logic 0
|
|
* 0b1..Logic 1
|
|
*/
|
|
#define GPIO_PDIR_PDI2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI2_SHIFT)) & GPIO_PDIR_PDI2_MASK)
|
|
|
|
#define GPIO_PDIR_PDI3_MASK (0x8U)
|
|
#define GPIO_PDIR_PDI3_SHIFT (3U)
|
|
/*! PDI3 - Port Data Input
|
|
* 0b0..Logic 0
|
|
* 0b1..Logic 1
|
|
*/
|
|
#define GPIO_PDIR_PDI3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI3_SHIFT)) & GPIO_PDIR_PDI3_MASK)
|
|
|
|
#define GPIO_PDIR_PDI4_MASK (0x10U)
|
|
#define GPIO_PDIR_PDI4_SHIFT (4U)
|
|
/*! PDI4 - Port Data Input
|
|
* 0b0..Logic 0
|
|
* 0b1..Logic 1
|
|
*/
|
|
#define GPIO_PDIR_PDI4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI4_SHIFT)) & GPIO_PDIR_PDI4_MASK)
|
|
|
|
#define GPIO_PDIR_PDI5_MASK (0x20U)
|
|
#define GPIO_PDIR_PDI5_SHIFT (5U)
|
|
/*! PDI5 - Port Data Input
|
|
* 0b0..Logic 0
|
|
* 0b1..Logic 1
|
|
*/
|
|
#define GPIO_PDIR_PDI5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI5_SHIFT)) & GPIO_PDIR_PDI5_MASK)
|
|
|
|
#define GPIO_PDIR_PDI6_MASK (0x40U)
|
|
#define GPIO_PDIR_PDI6_SHIFT (6U)
|
|
/*! PDI6 - Port Data Input
|
|
* 0b0..Logic 0
|
|
* 0b1..Logic 1
|
|
*/
|
|
#define GPIO_PDIR_PDI6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI6_SHIFT)) & GPIO_PDIR_PDI6_MASK)
|
|
|
|
#define GPIO_PDIR_PDI7_MASK (0x80U)
|
|
#define GPIO_PDIR_PDI7_SHIFT (7U)
|
|
/*! PDI7 - Port Data Input
|
|
* 0b0..Logic 0
|
|
* 0b1..Logic 1
|
|
*/
|
|
#define GPIO_PDIR_PDI7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI7_SHIFT)) & GPIO_PDIR_PDI7_MASK)
|
|
|
|
#define GPIO_PDIR_PDI8_MASK (0x100U)
|
|
#define GPIO_PDIR_PDI8_SHIFT (8U)
|
|
/*! PDI8 - Port Data Input
|
|
* 0b0..Logic 0
|
|
* 0b1..Logic 1
|
|
*/
|
|
#define GPIO_PDIR_PDI8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI8_SHIFT)) & GPIO_PDIR_PDI8_MASK)
|
|
|
|
#define GPIO_PDIR_PDI9_MASK (0x200U)
|
|
#define GPIO_PDIR_PDI9_SHIFT (9U)
|
|
/*! PDI9 - Port Data Input
|
|
* 0b0..Logic 0
|
|
* 0b1..Logic 1
|
|
*/
|
|
#define GPIO_PDIR_PDI9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI9_SHIFT)) & GPIO_PDIR_PDI9_MASK)
|
|
|
|
#define GPIO_PDIR_PDI10_MASK (0x400U)
|
|
#define GPIO_PDIR_PDI10_SHIFT (10U)
|
|
/*! PDI10 - Port Data Input
|
|
* 0b0..Logic 0
|
|
* 0b1..Logic 1
|
|
*/
|
|
#define GPIO_PDIR_PDI10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI10_SHIFT)) & GPIO_PDIR_PDI10_MASK)
|
|
|
|
#define GPIO_PDIR_PDI11_MASK (0x800U)
|
|
#define GPIO_PDIR_PDI11_SHIFT (11U)
|
|
/*! PDI11 - Port Data Input
|
|
* 0b0..Logic 0
|
|
* 0b1..Logic 1
|
|
*/
|
|
#define GPIO_PDIR_PDI11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI11_SHIFT)) & GPIO_PDIR_PDI11_MASK)
|
|
|
|
#define GPIO_PDIR_PDI12_MASK (0x1000U)
|
|
#define GPIO_PDIR_PDI12_SHIFT (12U)
|
|
/*! PDI12 - Port Data Input
|
|
* 0b0..Logic 0
|
|
* 0b1..Logic 1
|
|
*/
|
|
#define GPIO_PDIR_PDI12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI12_SHIFT)) & GPIO_PDIR_PDI12_MASK)
|
|
|
|
#define GPIO_PDIR_PDI13_MASK (0x2000U)
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#define GPIO_PDIR_PDI13_SHIFT (13U)
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/*! PDI13 - Port Data Input
|
|
* 0b0..Logic 0
|
|
* 0b1..Logic 1
|
|
*/
|
|
#define GPIO_PDIR_PDI13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI13_SHIFT)) & GPIO_PDIR_PDI13_MASK)
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#define GPIO_PDIR_PDI14_MASK (0x4000U)
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#define GPIO_PDIR_PDI14_SHIFT (14U)
|
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/*! PDI14 - Port Data Input
|
|
* 0b0..Logic 0
|
|
* 0b1..Logic 1
|
|
*/
|
|
#define GPIO_PDIR_PDI14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI14_SHIFT)) & GPIO_PDIR_PDI14_MASK)
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#define GPIO_PDIR_PDI15_MASK (0x8000U)
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#define GPIO_PDIR_PDI15_SHIFT (15U)
|
|
/*! PDI15 - Port Data Input
|
|
* 0b0..Logic 0
|
|
* 0b1..Logic 1
|
|
*/
|
|
#define GPIO_PDIR_PDI15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI15_SHIFT)) & GPIO_PDIR_PDI15_MASK)
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#define GPIO_PDIR_PDI16_MASK (0x10000U)
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#define GPIO_PDIR_PDI16_SHIFT (16U)
|
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/*! PDI16 - Port Data Input
|
|
* 0b0..Logic 0
|
|
* 0b1..Logic 1
|
|
*/
|
|
#define GPIO_PDIR_PDI16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI16_SHIFT)) & GPIO_PDIR_PDI16_MASK)
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#define GPIO_PDIR_PDI17_MASK (0x20000U)
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#define GPIO_PDIR_PDI17_SHIFT (17U)
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/*! PDI17 - Port Data Input
|
|
* 0b0..Logic 0
|
|
* 0b1..Logic 1
|
|
*/
|
|
#define GPIO_PDIR_PDI17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI17_SHIFT)) & GPIO_PDIR_PDI17_MASK)
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#define GPIO_PDIR_PDI18_MASK (0x40000U)
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#define GPIO_PDIR_PDI18_SHIFT (18U)
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/*! PDI18 - Port Data Input
|
|
* 0b0..Logic 0
|
|
* 0b1..Logic 1
|
|
*/
|
|
#define GPIO_PDIR_PDI18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI18_SHIFT)) & GPIO_PDIR_PDI18_MASK)
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|
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#define GPIO_PDIR_PDI19_MASK (0x80000U)
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|
#define GPIO_PDIR_PDI19_SHIFT (19U)
|
|
/*! PDI19 - Port Data Input
|
|
* 0b0..Logic 0
|
|
* 0b1..Logic 1
|
|
*/
|
|
#define GPIO_PDIR_PDI19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI19_SHIFT)) & GPIO_PDIR_PDI19_MASK)
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#define GPIO_PDIR_PDI20_MASK (0x100000U)
|
|
#define GPIO_PDIR_PDI20_SHIFT (20U)
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|
/*! PDI20 - Port Data Input
|
|
* 0b0..Logic 0
|
|
* 0b1..Logic 1
|
|
*/
|
|
#define GPIO_PDIR_PDI20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI20_SHIFT)) & GPIO_PDIR_PDI20_MASK)
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|
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#define GPIO_PDIR_PDI21_MASK (0x200000U)
|
|
#define GPIO_PDIR_PDI21_SHIFT (21U)
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|
/*! PDI21 - Port Data Input
|
|
* 0b0..Logic 0
|
|
* 0b1..Logic 1
|
|
*/
|
|
#define GPIO_PDIR_PDI21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI21_SHIFT)) & GPIO_PDIR_PDI21_MASK)
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|
|
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#define GPIO_PDIR_PDI22_MASK (0x400000U)
|
|
#define GPIO_PDIR_PDI22_SHIFT (22U)
|
|
/*! PDI22 - Port Data Input
|
|
* 0b0..Logic 0
|
|
* 0b1..Logic 1
|
|
*/
|
|
#define GPIO_PDIR_PDI22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI22_SHIFT)) & GPIO_PDIR_PDI22_MASK)
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|
|
|
#define GPIO_PDIR_PDI23_MASK (0x800000U)
|
|
#define GPIO_PDIR_PDI23_SHIFT (23U)
|
|
/*! PDI23 - Port Data Input
|
|
* 0b0..Logic 0
|
|
* 0b1..Logic 1
|
|
*/
|
|
#define GPIO_PDIR_PDI23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI23_SHIFT)) & GPIO_PDIR_PDI23_MASK)
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|
|
|
#define GPIO_PDIR_PDI24_MASK (0x1000000U)
|
|
#define GPIO_PDIR_PDI24_SHIFT (24U)
|
|
/*! PDI24 - Port Data Input
|
|
* 0b0..Logic 0
|
|
* 0b1..Logic 1
|
|
*/
|
|
#define GPIO_PDIR_PDI24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI24_SHIFT)) & GPIO_PDIR_PDI24_MASK)
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|
|
|
#define GPIO_PDIR_PDI25_MASK (0x2000000U)
|
|
#define GPIO_PDIR_PDI25_SHIFT (25U)
|
|
/*! PDI25 - Port Data Input
|
|
* 0b0..Logic 0
|
|
* 0b1..Logic 1
|
|
*/
|
|
#define GPIO_PDIR_PDI25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI25_SHIFT)) & GPIO_PDIR_PDI25_MASK)
|
|
|
|
#define GPIO_PDIR_PDI26_MASK (0x4000000U)
|
|
#define GPIO_PDIR_PDI26_SHIFT (26U)
|
|
/*! PDI26 - Port Data Input
|
|
* 0b0..Logic 0
|
|
* 0b1..Logic 1
|
|
*/
|
|
#define GPIO_PDIR_PDI26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI26_SHIFT)) & GPIO_PDIR_PDI26_MASK)
|
|
|
|
#define GPIO_PDIR_PDI27_MASK (0x8000000U)
|
|
#define GPIO_PDIR_PDI27_SHIFT (27U)
|
|
/*! PDI27 - Port Data Input
|
|
* 0b0..Logic 0
|
|
* 0b1..Logic 1
|
|
*/
|
|
#define GPIO_PDIR_PDI27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI27_SHIFT)) & GPIO_PDIR_PDI27_MASK)
|
|
|
|
#define GPIO_PDIR_PDI28_MASK (0x10000000U)
|
|
#define GPIO_PDIR_PDI28_SHIFT (28U)
|
|
/*! PDI28 - Port Data Input
|
|
* 0b0..Logic 0
|
|
* 0b1..Logic 1
|
|
*/
|
|
#define GPIO_PDIR_PDI28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI28_SHIFT)) & GPIO_PDIR_PDI28_MASK)
|
|
|
|
#define GPIO_PDIR_PDI29_MASK (0x20000000U)
|
|
#define GPIO_PDIR_PDI29_SHIFT (29U)
|
|
/*! PDI29 - Port Data Input
|
|
* 0b0..Logic 0
|
|
* 0b1..Logic 1
|
|
*/
|
|
#define GPIO_PDIR_PDI29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI29_SHIFT)) & GPIO_PDIR_PDI29_MASK)
|
|
|
|
#define GPIO_PDIR_PDI30_MASK (0x40000000U)
|
|
#define GPIO_PDIR_PDI30_SHIFT (30U)
|
|
/*! PDI30 - Port Data Input
|
|
* 0b0..Logic 0
|
|
* 0b1..Logic 1
|
|
*/
|
|
#define GPIO_PDIR_PDI30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI30_SHIFT)) & GPIO_PDIR_PDI30_MASK)
|
|
|
|
#define GPIO_PDIR_PDI31_MASK (0x80000000U)
|
|
#define GPIO_PDIR_PDI31_SHIFT (31U)
|
|
/*! PDI31 - Port Data Input
|
|
* 0b0..Logic 0
|
|
* 0b1..Logic 1
|
|
*/
|
|
#define GPIO_PDIR_PDI31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI31_SHIFT)) & GPIO_PDIR_PDI31_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PDDR - Port Data Direction */
|
|
/*! @{ */
|
|
|
|
#define GPIO_PDDR_PDD0_MASK (0x1U)
|
|
#define GPIO_PDDR_PDD0_SHIFT (0U)
|
|
/*! PDD0 - Port Data Direction
|
|
* 0b0..Input
|
|
* 0b1..Output
|
|
*/
|
|
#define GPIO_PDDR_PDD0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD0_SHIFT)) & GPIO_PDDR_PDD0_MASK)
|
|
|
|
#define GPIO_PDDR_PDD1_MASK (0x2U)
|
|
#define GPIO_PDDR_PDD1_SHIFT (1U)
|
|
/*! PDD1 - Port Data Direction
|
|
* 0b0..Input
|
|
* 0b1..Output
|
|
*/
|
|
#define GPIO_PDDR_PDD1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD1_SHIFT)) & GPIO_PDDR_PDD1_MASK)
|
|
|
|
#define GPIO_PDDR_PDD2_MASK (0x4U)
|
|
#define GPIO_PDDR_PDD2_SHIFT (2U)
|
|
/*! PDD2 - Port Data Direction
|
|
* 0b0..Input
|
|
* 0b1..Output
|
|
*/
|
|
#define GPIO_PDDR_PDD2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD2_SHIFT)) & GPIO_PDDR_PDD2_MASK)
|
|
|
|
#define GPIO_PDDR_PDD3_MASK (0x8U)
|
|
#define GPIO_PDDR_PDD3_SHIFT (3U)
|
|
/*! PDD3 - Port Data Direction
|
|
* 0b0..Input
|
|
* 0b1..Output
|
|
*/
|
|
#define GPIO_PDDR_PDD3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD3_SHIFT)) & GPIO_PDDR_PDD3_MASK)
|
|
|
|
#define GPIO_PDDR_PDD4_MASK (0x10U)
|
|
#define GPIO_PDDR_PDD4_SHIFT (4U)
|
|
/*! PDD4 - Port Data Direction
|
|
* 0b0..Input
|
|
* 0b1..Output
|
|
*/
|
|
#define GPIO_PDDR_PDD4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD4_SHIFT)) & GPIO_PDDR_PDD4_MASK)
|
|
|
|
#define GPIO_PDDR_PDD5_MASK (0x20U)
|
|
#define GPIO_PDDR_PDD5_SHIFT (5U)
|
|
/*! PDD5 - Port Data Direction
|
|
* 0b0..Input
|
|
* 0b1..Output
|
|
*/
|
|
#define GPIO_PDDR_PDD5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD5_SHIFT)) & GPIO_PDDR_PDD5_MASK)
|
|
|
|
#define GPIO_PDDR_PDD6_MASK (0x40U)
|
|
#define GPIO_PDDR_PDD6_SHIFT (6U)
|
|
/*! PDD6 - Port Data Direction
|
|
* 0b0..Input
|
|
* 0b1..Output
|
|
*/
|
|
#define GPIO_PDDR_PDD6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD6_SHIFT)) & GPIO_PDDR_PDD6_MASK)
|
|
|
|
#define GPIO_PDDR_PDD7_MASK (0x80U)
|
|
#define GPIO_PDDR_PDD7_SHIFT (7U)
|
|
/*! PDD7 - Port Data Direction
|
|
* 0b0..Input
|
|
* 0b1..Output
|
|
*/
|
|
#define GPIO_PDDR_PDD7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD7_SHIFT)) & GPIO_PDDR_PDD7_MASK)
|
|
|
|
#define GPIO_PDDR_PDD8_MASK (0x100U)
|
|
#define GPIO_PDDR_PDD8_SHIFT (8U)
|
|
/*! PDD8 - Port Data Direction
|
|
* 0b0..Input
|
|
* 0b1..Output
|
|
*/
|
|
#define GPIO_PDDR_PDD8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD8_SHIFT)) & GPIO_PDDR_PDD8_MASK)
|
|
|
|
#define GPIO_PDDR_PDD9_MASK (0x200U)
|
|
#define GPIO_PDDR_PDD9_SHIFT (9U)
|
|
/*! PDD9 - Port Data Direction
|
|
* 0b0..Input
|
|
* 0b1..Output
|
|
*/
|
|
#define GPIO_PDDR_PDD9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD9_SHIFT)) & GPIO_PDDR_PDD9_MASK)
|
|
|
|
#define GPIO_PDDR_PDD10_MASK (0x400U)
|
|
#define GPIO_PDDR_PDD10_SHIFT (10U)
|
|
/*! PDD10 - Port Data Direction
|
|
* 0b0..Input
|
|
* 0b1..Output
|
|
*/
|
|
#define GPIO_PDDR_PDD10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD10_SHIFT)) & GPIO_PDDR_PDD10_MASK)
|
|
|
|
#define GPIO_PDDR_PDD11_MASK (0x800U)
|
|
#define GPIO_PDDR_PDD11_SHIFT (11U)
|
|
/*! PDD11 - Port Data Direction
|
|
* 0b0..Input
|
|
* 0b1..Output
|
|
*/
|
|
#define GPIO_PDDR_PDD11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD11_SHIFT)) & GPIO_PDDR_PDD11_MASK)
|
|
|
|
#define GPIO_PDDR_PDD12_MASK (0x1000U)
|
|
#define GPIO_PDDR_PDD12_SHIFT (12U)
|
|
/*! PDD12 - Port Data Direction
|
|
* 0b0..Input
|
|
* 0b1..Output
|
|
*/
|
|
#define GPIO_PDDR_PDD12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD12_SHIFT)) & GPIO_PDDR_PDD12_MASK)
|
|
|
|
#define GPIO_PDDR_PDD13_MASK (0x2000U)
|
|
#define GPIO_PDDR_PDD13_SHIFT (13U)
|
|
/*! PDD13 - Port Data Direction
|
|
* 0b0..Input
|
|
* 0b1..Output
|
|
*/
|
|
#define GPIO_PDDR_PDD13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD13_SHIFT)) & GPIO_PDDR_PDD13_MASK)
|
|
|
|
#define GPIO_PDDR_PDD14_MASK (0x4000U)
|
|
#define GPIO_PDDR_PDD14_SHIFT (14U)
|
|
/*! PDD14 - Port Data Direction
|
|
* 0b0..Input
|
|
* 0b1..Output
|
|
*/
|
|
#define GPIO_PDDR_PDD14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD14_SHIFT)) & GPIO_PDDR_PDD14_MASK)
|
|
|
|
#define GPIO_PDDR_PDD15_MASK (0x8000U)
|
|
#define GPIO_PDDR_PDD15_SHIFT (15U)
|
|
/*! PDD15 - Port Data Direction
|
|
* 0b0..Input
|
|
* 0b1..Output
|
|
*/
|
|
#define GPIO_PDDR_PDD15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD15_SHIFT)) & GPIO_PDDR_PDD15_MASK)
|
|
|
|
#define GPIO_PDDR_PDD16_MASK (0x10000U)
|
|
#define GPIO_PDDR_PDD16_SHIFT (16U)
|
|
/*! PDD16 - Port Data Direction
|
|
* 0b0..Input
|
|
* 0b1..Output
|
|
*/
|
|
#define GPIO_PDDR_PDD16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD16_SHIFT)) & GPIO_PDDR_PDD16_MASK)
|
|
|
|
#define GPIO_PDDR_PDD17_MASK (0x20000U)
|
|
#define GPIO_PDDR_PDD17_SHIFT (17U)
|
|
/*! PDD17 - Port Data Direction
|
|
* 0b0..Input
|
|
* 0b1..Output
|
|
*/
|
|
#define GPIO_PDDR_PDD17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD17_SHIFT)) & GPIO_PDDR_PDD17_MASK)
|
|
|
|
#define GPIO_PDDR_PDD18_MASK (0x40000U)
|
|
#define GPIO_PDDR_PDD18_SHIFT (18U)
|
|
/*! PDD18 - Port Data Direction
|
|
* 0b0..Input
|
|
* 0b1..Output
|
|
*/
|
|
#define GPIO_PDDR_PDD18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD18_SHIFT)) & GPIO_PDDR_PDD18_MASK)
|
|
|
|
#define GPIO_PDDR_PDD19_MASK (0x80000U)
|
|
#define GPIO_PDDR_PDD19_SHIFT (19U)
|
|
/*! PDD19 - Port Data Direction
|
|
* 0b0..Input
|
|
* 0b1..Output
|
|
*/
|
|
#define GPIO_PDDR_PDD19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD19_SHIFT)) & GPIO_PDDR_PDD19_MASK)
|
|
|
|
#define GPIO_PDDR_PDD20_MASK (0x100000U)
|
|
#define GPIO_PDDR_PDD20_SHIFT (20U)
|
|
/*! PDD20 - Port Data Direction
|
|
* 0b0..Input
|
|
* 0b1..Output
|
|
*/
|
|
#define GPIO_PDDR_PDD20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD20_SHIFT)) & GPIO_PDDR_PDD20_MASK)
|
|
|
|
#define GPIO_PDDR_PDD21_MASK (0x200000U)
|
|
#define GPIO_PDDR_PDD21_SHIFT (21U)
|
|
/*! PDD21 - Port Data Direction
|
|
* 0b0..Input
|
|
* 0b1..Output
|
|
*/
|
|
#define GPIO_PDDR_PDD21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD21_SHIFT)) & GPIO_PDDR_PDD21_MASK)
|
|
|
|
#define GPIO_PDDR_PDD22_MASK (0x400000U)
|
|
#define GPIO_PDDR_PDD22_SHIFT (22U)
|
|
/*! PDD22 - Port Data Direction
|
|
* 0b0..Input
|
|
* 0b1..Output
|
|
*/
|
|
#define GPIO_PDDR_PDD22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD22_SHIFT)) & GPIO_PDDR_PDD22_MASK)
|
|
|
|
#define GPIO_PDDR_PDD23_MASK (0x800000U)
|
|
#define GPIO_PDDR_PDD23_SHIFT (23U)
|
|
/*! PDD23 - Port Data Direction
|
|
* 0b0..Input
|
|
* 0b1..Output
|
|
*/
|
|
#define GPIO_PDDR_PDD23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD23_SHIFT)) & GPIO_PDDR_PDD23_MASK)
|
|
|
|
#define GPIO_PDDR_PDD24_MASK (0x1000000U)
|
|
#define GPIO_PDDR_PDD24_SHIFT (24U)
|
|
/*! PDD24 - Port Data Direction
|
|
* 0b0..Input
|
|
* 0b1..Output
|
|
*/
|
|
#define GPIO_PDDR_PDD24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD24_SHIFT)) & GPIO_PDDR_PDD24_MASK)
|
|
|
|
#define GPIO_PDDR_PDD25_MASK (0x2000000U)
|
|
#define GPIO_PDDR_PDD25_SHIFT (25U)
|
|
/*! PDD25 - Port Data Direction
|
|
* 0b0..Input
|
|
* 0b1..Output
|
|
*/
|
|
#define GPIO_PDDR_PDD25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD25_SHIFT)) & GPIO_PDDR_PDD25_MASK)
|
|
|
|
#define GPIO_PDDR_PDD26_MASK (0x4000000U)
|
|
#define GPIO_PDDR_PDD26_SHIFT (26U)
|
|
/*! PDD26 - Port Data Direction
|
|
* 0b0..Input
|
|
* 0b1..Output
|
|
*/
|
|
#define GPIO_PDDR_PDD26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD26_SHIFT)) & GPIO_PDDR_PDD26_MASK)
|
|
|
|
#define GPIO_PDDR_PDD27_MASK (0x8000000U)
|
|
#define GPIO_PDDR_PDD27_SHIFT (27U)
|
|
/*! PDD27 - Port Data Direction
|
|
* 0b0..Input
|
|
* 0b1..Output
|
|
*/
|
|
#define GPIO_PDDR_PDD27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD27_SHIFT)) & GPIO_PDDR_PDD27_MASK)
|
|
|
|
#define GPIO_PDDR_PDD28_MASK (0x10000000U)
|
|
#define GPIO_PDDR_PDD28_SHIFT (28U)
|
|
/*! PDD28 - Port Data Direction
|
|
* 0b0..Input
|
|
* 0b1..Output
|
|
*/
|
|
#define GPIO_PDDR_PDD28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD28_SHIFT)) & GPIO_PDDR_PDD28_MASK)
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#define GPIO_PDDR_PDD29_MASK (0x20000000U)
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#define GPIO_PDDR_PDD29_SHIFT (29U)
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/*! PDD29 - Port Data Direction
|
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* 0b0..Input
|
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* 0b1..Output
|
|
*/
|
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#define GPIO_PDDR_PDD29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD29_SHIFT)) & GPIO_PDDR_PDD29_MASK)
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#define GPIO_PDDR_PDD30_MASK (0x40000000U)
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#define GPIO_PDDR_PDD30_SHIFT (30U)
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/*! PDD30 - Port Data Direction
|
|
* 0b0..Input
|
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* 0b1..Output
|
|
*/
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#define GPIO_PDDR_PDD30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD30_SHIFT)) & GPIO_PDDR_PDD30_MASK)
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#define GPIO_PDDR_PDD31_MASK (0x80000000U)
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#define GPIO_PDDR_PDD31_SHIFT (31U)
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/*! PDD31 - Port Data Direction
|
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* 0b0..Input
|
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* 0b1..Output
|
|
*/
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#define GPIO_PDDR_PDD31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD31_SHIFT)) & GPIO_PDDR_PDD31_MASK)
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/*! @} */
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/*! @name PIDR - Port Input Disable */
|
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/*! @{ */
|
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#define GPIO_PIDR_PID0_MASK (0x1U)
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#define GPIO_PIDR_PID0_SHIFT (0U)
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/*! PID0 - Port Input Disable
|
|
* 0b0..Configured for general-purpose input
|
|
* 0b1..Disabled for general-purpose input
|
|
*/
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#define GPIO_PIDR_PID0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID0_SHIFT)) & GPIO_PIDR_PID0_MASK)
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#define GPIO_PIDR_PID1_MASK (0x2U)
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#define GPIO_PIDR_PID1_SHIFT (1U)
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/*! PID1 - Port Input Disable
|
|
* 0b0..Configured for general-purpose input
|
|
* 0b1..Disabled for general-purpose input
|
|
*/
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#define GPIO_PIDR_PID1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID1_SHIFT)) & GPIO_PIDR_PID1_MASK)
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#define GPIO_PIDR_PID2_MASK (0x4U)
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#define GPIO_PIDR_PID2_SHIFT (2U)
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/*! PID2 - Port Input Disable
|
|
* 0b0..Configured for general-purpose input
|
|
* 0b1..Disabled for general-purpose input
|
|
*/
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#define GPIO_PIDR_PID2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID2_SHIFT)) & GPIO_PIDR_PID2_MASK)
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#define GPIO_PIDR_PID3_MASK (0x8U)
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#define GPIO_PIDR_PID3_SHIFT (3U)
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/*! PID3 - Port Input Disable
|
|
* 0b0..Configured for general-purpose input
|
|
* 0b1..Disabled for general-purpose input
|
|
*/
|
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#define GPIO_PIDR_PID3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID3_SHIFT)) & GPIO_PIDR_PID3_MASK)
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#define GPIO_PIDR_PID4_MASK (0x10U)
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#define GPIO_PIDR_PID4_SHIFT (4U)
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/*! PID4 - Port Input Disable
|
|
* 0b0..Configured for general-purpose input
|
|
* 0b1..Disabled for general-purpose input
|
|
*/
|
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#define GPIO_PIDR_PID4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID4_SHIFT)) & GPIO_PIDR_PID4_MASK)
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|
|
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#define GPIO_PIDR_PID5_MASK (0x20U)
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#define GPIO_PIDR_PID5_SHIFT (5U)
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|
/*! PID5 - Port Input Disable
|
|
* 0b0..Configured for general-purpose input
|
|
* 0b1..Disabled for general-purpose input
|
|
*/
|
|
#define GPIO_PIDR_PID5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID5_SHIFT)) & GPIO_PIDR_PID5_MASK)
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|
|
|
#define GPIO_PIDR_PID6_MASK (0x40U)
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|
#define GPIO_PIDR_PID6_SHIFT (6U)
|
|
/*! PID6 - Port Input Disable
|
|
* 0b0..Configured for general-purpose input
|
|
* 0b1..Disabled for general-purpose input
|
|
*/
|
|
#define GPIO_PIDR_PID6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID6_SHIFT)) & GPIO_PIDR_PID6_MASK)
|
|
|
|
#define GPIO_PIDR_PID7_MASK (0x80U)
|
|
#define GPIO_PIDR_PID7_SHIFT (7U)
|
|
/*! PID7 - Port Input Disable
|
|
* 0b0..Configured for general-purpose input
|
|
* 0b1..Disabled for general-purpose input
|
|
*/
|
|
#define GPIO_PIDR_PID7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID7_SHIFT)) & GPIO_PIDR_PID7_MASK)
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|
|
|
#define GPIO_PIDR_PID8_MASK (0x100U)
|
|
#define GPIO_PIDR_PID8_SHIFT (8U)
|
|
/*! PID8 - Port Input Disable
|
|
* 0b0..Configured for general-purpose input
|
|
* 0b1..Disabled for general-purpose input
|
|
*/
|
|
#define GPIO_PIDR_PID8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID8_SHIFT)) & GPIO_PIDR_PID8_MASK)
|
|
|
|
#define GPIO_PIDR_PID9_MASK (0x200U)
|
|
#define GPIO_PIDR_PID9_SHIFT (9U)
|
|
/*! PID9 - Port Input Disable
|
|
* 0b0..Configured for general-purpose input
|
|
* 0b1..Disabled for general-purpose input
|
|
*/
|
|
#define GPIO_PIDR_PID9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID9_SHIFT)) & GPIO_PIDR_PID9_MASK)
|
|
|
|
#define GPIO_PIDR_PID10_MASK (0x400U)
|
|
#define GPIO_PIDR_PID10_SHIFT (10U)
|
|
/*! PID10 - Port Input Disable
|
|
* 0b0..Configured for general-purpose input
|
|
* 0b1..Disabled for general-purpose input
|
|
*/
|
|
#define GPIO_PIDR_PID10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID10_SHIFT)) & GPIO_PIDR_PID10_MASK)
|
|
|
|
#define GPIO_PIDR_PID11_MASK (0x800U)
|
|
#define GPIO_PIDR_PID11_SHIFT (11U)
|
|
/*! PID11 - Port Input Disable
|
|
* 0b0..Configured for general-purpose input
|
|
* 0b1..Disabled for general-purpose input
|
|
*/
|
|
#define GPIO_PIDR_PID11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID11_SHIFT)) & GPIO_PIDR_PID11_MASK)
|
|
|
|
#define GPIO_PIDR_PID12_MASK (0x1000U)
|
|
#define GPIO_PIDR_PID12_SHIFT (12U)
|
|
/*! PID12 - Port Input Disable
|
|
* 0b0..Configured for general-purpose input
|
|
* 0b1..Disabled for general-purpose input
|
|
*/
|
|
#define GPIO_PIDR_PID12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID12_SHIFT)) & GPIO_PIDR_PID12_MASK)
|
|
|
|
#define GPIO_PIDR_PID13_MASK (0x2000U)
|
|
#define GPIO_PIDR_PID13_SHIFT (13U)
|
|
/*! PID13 - Port Input Disable
|
|
* 0b0..Configured for general-purpose input
|
|
* 0b1..Disabled for general-purpose input
|
|
*/
|
|
#define GPIO_PIDR_PID13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID13_SHIFT)) & GPIO_PIDR_PID13_MASK)
|
|
|
|
#define GPIO_PIDR_PID14_MASK (0x4000U)
|
|
#define GPIO_PIDR_PID14_SHIFT (14U)
|
|
/*! PID14 - Port Input Disable
|
|
* 0b0..Configured for general-purpose input
|
|
* 0b1..Disabled for general-purpose input
|
|
*/
|
|
#define GPIO_PIDR_PID14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID14_SHIFT)) & GPIO_PIDR_PID14_MASK)
|
|
|
|
#define GPIO_PIDR_PID15_MASK (0x8000U)
|
|
#define GPIO_PIDR_PID15_SHIFT (15U)
|
|
/*! PID15 - Port Input Disable
|
|
* 0b0..Configured for general-purpose input
|
|
* 0b1..Disabled for general-purpose input
|
|
*/
|
|
#define GPIO_PIDR_PID15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID15_SHIFT)) & GPIO_PIDR_PID15_MASK)
|
|
|
|
#define GPIO_PIDR_PID16_MASK (0x10000U)
|
|
#define GPIO_PIDR_PID16_SHIFT (16U)
|
|
/*! PID16 - Port Input Disable
|
|
* 0b0..Configured for general-purpose input
|
|
* 0b1..Disabled for general-purpose input
|
|
*/
|
|
#define GPIO_PIDR_PID16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID16_SHIFT)) & GPIO_PIDR_PID16_MASK)
|
|
|
|
#define GPIO_PIDR_PID17_MASK (0x20000U)
|
|
#define GPIO_PIDR_PID17_SHIFT (17U)
|
|
/*! PID17 - Port Input Disable
|
|
* 0b0..Configured for general-purpose input
|
|
* 0b1..Disabled for general-purpose input
|
|
*/
|
|
#define GPIO_PIDR_PID17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID17_SHIFT)) & GPIO_PIDR_PID17_MASK)
|
|
|
|
#define GPIO_PIDR_PID18_MASK (0x40000U)
|
|
#define GPIO_PIDR_PID18_SHIFT (18U)
|
|
/*! PID18 - Port Input Disable
|
|
* 0b0..Configured for general-purpose input
|
|
* 0b1..Disabled for general-purpose input
|
|
*/
|
|
#define GPIO_PIDR_PID18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID18_SHIFT)) & GPIO_PIDR_PID18_MASK)
|
|
|
|
#define GPIO_PIDR_PID19_MASK (0x80000U)
|
|
#define GPIO_PIDR_PID19_SHIFT (19U)
|
|
/*! PID19 - Port Input Disable
|
|
* 0b0..Configured for general-purpose input
|
|
* 0b1..Disabled for general-purpose input
|
|
*/
|
|
#define GPIO_PIDR_PID19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID19_SHIFT)) & GPIO_PIDR_PID19_MASK)
|
|
|
|
#define GPIO_PIDR_PID20_MASK (0x100000U)
|
|
#define GPIO_PIDR_PID20_SHIFT (20U)
|
|
/*! PID20 - Port Input Disable
|
|
* 0b0..Configured for general-purpose input
|
|
* 0b1..Disabled for general-purpose input
|
|
*/
|
|
#define GPIO_PIDR_PID20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID20_SHIFT)) & GPIO_PIDR_PID20_MASK)
|
|
|
|
#define GPIO_PIDR_PID21_MASK (0x200000U)
|
|
#define GPIO_PIDR_PID21_SHIFT (21U)
|
|
/*! PID21 - Port Input Disable
|
|
* 0b0..Configured for general-purpose input
|
|
* 0b1..Disabled for general-purpose input
|
|
*/
|
|
#define GPIO_PIDR_PID21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID21_SHIFT)) & GPIO_PIDR_PID21_MASK)
|
|
|
|
#define GPIO_PIDR_PID22_MASK (0x400000U)
|
|
#define GPIO_PIDR_PID22_SHIFT (22U)
|
|
/*! PID22 - Port Input Disable
|
|
* 0b0..Configured for general-purpose input
|
|
* 0b1..Disabled for general-purpose input
|
|
*/
|
|
#define GPIO_PIDR_PID22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID22_SHIFT)) & GPIO_PIDR_PID22_MASK)
|
|
|
|
#define GPIO_PIDR_PID23_MASK (0x800000U)
|
|
#define GPIO_PIDR_PID23_SHIFT (23U)
|
|
/*! PID23 - Port Input Disable
|
|
* 0b0..Configured for general-purpose input
|
|
* 0b1..Disabled for general-purpose input
|
|
*/
|
|
#define GPIO_PIDR_PID23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID23_SHIFT)) & GPIO_PIDR_PID23_MASK)
|
|
|
|
#define GPIO_PIDR_PID24_MASK (0x1000000U)
|
|
#define GPIO_PIDR_PID24_SHIFT (24U)
|
|
/*! PID24 - Port Input Disable
|
|
* 0b0..Configured for general-purpose input
|
|
* 0b1..Disabled for general-purpose input
|
|
*/
|
|
#define GPIO_PIDR_PID24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID24_SHIFT)) & GPIO_PIDR_PID24_MASK)
|
|
|
|
#define GPIO_PIDR_PID25_MASK (0x2000000U)
|
|
#define GPIO_PIDR_PID25_SHIFT (25U)
|
|
/*! PID25 - Port Input Disable
|
|
* 0b0..Configured for general-purpose input
|
|
* 0b1..Disabled for general-purpose input
|
|
*/
|
|
#define GPIO_PIDR_PID25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID25_SHIFT)) & GPIO_PIDR_PID25_MASK)
|
|
|
|
#define GPIO_PIDR_PID26_MASK (0x4000000U)
|
|
#define GPIO_PIDR_PID26_SHIFT (26U)
|
|
/*! PID26 - Port Input Disable
|
|
* 0b0..Configured for general-purpose input
|
|
* 0b1..Disabled for general-purpose input
|
|
*/
|
|
#define GPIO_PIDR_PID26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID26_SHIFT)) & GPIO_PIDR_PID26_MASK)
|
|
|
|
#define GPIO_PIDR_PID27_MASK (0x8000000U)
|
|
#define GPIO_PIDR_PID27_SHIFT (27U)
|
|
/*! PID27 - Port Input Disable
|
|
* 0b0..Configured for general-purpose input
|
|
* 0b1..Disabled for general-purpose input
|
|
*/
|
|
#define GPIO_PIDR_PID27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID27_SHIFT)) & GPIO_PIDR_PID27_MASK)
|
|
|
|
#define GPIO_PIDR_PID28_MASK (0x10000000U)
|
|
#define GPIO_PIDR_PID28_SHIFT (28U)
|
|
/*! PID28 - Port Input Disable
|
|
* 0b0..Configured for general-purpose input
|
|
* 0b1..Disabled for general-purpose input
|
|
*/
|
|
#define GPIO_PIDR_PID28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID28_SHIFT)) & GPIO_PIDR_PID28_MASK)
|
|
|
|
#define GPIO_PIDR_PID29_MASK (0x20000000U)
|
|
#define GPIO_PIDR_PID29_SHIFT (29U)
|
|
/*! PID29 - Port Input Disable
|
|
* 0b0..Configured for general-purpose input
|
|
* 0b1..Disabled for general-purpose input
|
|
*/
|
|
#define GPIO_PIDR_PID29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID29_SHIFT)) & GPIO_PIDR_PID29_MASK)
|
|
|
|
#define GPIO_PIDR_PID30_MASK (0x40000000U)
|
|
#define GPIO_PIDR_PID30_SHIFT (30U)
|
|
/*! PID30 - Port Input Disable
|
|
* 0b0..Configured for general-purpose input
|
|
* 0b1..Disabled for general-purpose input
|
|
*/
|
|
#define GPIO_PIDR_PID30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID30_SHIFT)) & GPIO_PIDR_PID30_MASK)
|
|
|
|
#define GPIO_PIDR_PID31_MASK (0x80000000U)
|
|
#define GPIO_PIDR_PID31_SHIFT (31U)
|
|
/*! PID31 - Port Input Disable
|
|
* 0b0..Configured for general-purpose input
|
|
* 0b1..Disabled for general-purpose input
|
|
*/
|
|
#define GPIO_PIDR_PID31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID31_SHIFT)) & GPIO_PIDR_PID31_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PDR - Pin Data */
|
|
/*! @{ */
|
|
|
|
#define GPIO_PDR_PD_MASK (0x1U)
|
|
#define GPIO_PDR_PD_SHIFT (0U)
|
|
/*! PD - Pin Data (I/O)
|
|
* 0b0..Logic zero
|
|
* 0b1..Logic one
|
|
*/
|
|
#define GPIO_PDR_PD(x) (((uint8_t)(((uint8_t)(x)) << GPIO_PDR_PD_SHIFT)) & GPIO_PDR_PD_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of GPIO_PDR */
|
|
#define GPIO_PDR_COUNT (32U)
|
|
|
|
/*! @name ICR - Interrupt Control 0..Interrupt Control 31 */
|
|
/*! @{ */
|
|
|
|
#define GPIO_ICR_IRQC_MASK (0xF0000U)
|
|
#define GPIO_ICR_IRQC_SHIFT (16U)
|
|
/*! IRQC - Interrupt Configuration
|
|
* 0b0000..ISF is disabled
|
|
* 0b0001..ISF and DMA request on rising edge
|
|
* 0b0010..ISF and DMA request on falling edge
|
|
* 0b0011..ISF and DMA request on either edge
|
|
* 0b0100..Reserved
|
|
* 0b0101..ISF sets on rising edge
|
|
* 0b0110..ISF sets on falling edge
|
|
* 0b0111..ISF sets on either edge
|
|
* 0b1000..ISF and interrupt when logic 0
|
|
* 0b1001..ISF and interrupt on rising edge
|
|
* 0b1010..ISF and interrupt on falling edge
|
|
* 0b1011..ISF and Interrupt on either edge
|
|
* 0b1100..ISF and interrupt when logic 1
|
|
* 0b1101..Enable active-high trigger output; ISF on rising edge (pin state is ORed with other enabled triggers
|
|
* to generate the output trigger for use by other peripherals)
|
|
* 0b1110..Enable active-low trigger output; ISF on falling edge (pin state is inverted and ORed with other
|
|
* enabled triggers to generate the output trigger for use by other peripherals)
|
|
* 0b1111..Reserved
|
|
*/
|
|
#define GPIO_ICR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_IRQC_SHIFT)) & GPIO_ICR_IRQC_MASK)
|
|
|
|
#define GPIO_ICR_ISF_MASK (0x1000000U)
|
|
#define GPIO_ICR_ISF_SHIFT (24U)
|
|
/*! ISF - Interrupt Status Flag
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define GPIO_ICR_ISF(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_ISF_SHIFT)) & GPIO_ICR_ISF_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of GPIO_ICR */
|
|
#define GPIO_ICR_COUNT (32U)
|
|
|
|
/*! @name GICLR - Global Interrupt Control Low */
|
|
/*! @{ */
|
|
|
|
#define GPIO_GICLR_GIWE0_MASK (0x1U)
|
|
#define GPIO_GICLR_GIWE0_SHIFT (0U)
|
|
/*! GIWE0 - Global Interrupt Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define GPIO_GICLR_GIWE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE0_SHIFT)) & GPIO_GICLR_GIWE0_MASK)
|
|
|
|
#define GPIO_GICLR_GIWE1_MASK (0x2U)
|
|
#define GPIO_GICLR_GIWE1_SHIFT (1U)
|
|
/*! GIWE1 - Global Interrupt Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define GPIO_GICLR_GIWE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE1_SHIFT)) & GPIO_GICLR_GIWE1_MASK)
|
|
|
|
#define GPIO_GICLR_GIWE2_MASK (0x4U)
|
|
#define GPIO_GICLR_GIWE2_SHIFT (2U)
|
|
/*! GIWE2 - Global Interrupt Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define GPIO_GICLR_GIWE2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE2_SHIFT)) & GPIO_GICLR_GIWE2_MASK)
|
|
|
|
#define GPIO_GICLR_GIWE3_MASK (0x8U)
|
|
#define GPIO_GICLR_GIWE3_SHIFT (3U)
|
|
/*! GIWE3 - Global Interrupt Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define GPIO_GICLR_GIWE3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE3_SHIFT)) & GPIO_GICLR_GIWE3_MASK)
|
|
|
|
#define GPIO_GICLR_GIWE4_MASK (0x10U)
|
|
#define GPIO_GICLR_GIWE4_SHIFT (4U)
|
|
/*! GIWE4 - Global Interrupt Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define GPIO_GICLR_GIWE4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE4_SHIFT)) & GPIO_GICLR_GIWE4_MASK)
|
|
|
|
#define GPIO_GICLR_GIWE5_MASK (0x20U)
|
|
#define GPIO_GICLR_GIWE5_SHIFT (5U)
|
|
/*! GIWE5 - Global Interrupt Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define GPIO_GICLR_GIWE5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE5_SHIFT)) & GPIO_GICLR_GIWE5_MASK)
|
|
|
|
#define GPIO_GICLR_GIWE6_MASK (0x40U)
|
|
#define GPIO_GICLR_GIWE6_SHIFT (6U)
|
|
/*! GIWE6 - Global Interrupt Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define GPIO_GICLR_GIWE6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE6_SHIFT)) & GPIO_GICLR_GIWE6_MASK)
|
|
|
|
#define GPIO_GICLR_GIWE7_MASK (0x80U)
|
|
#define GPIO_GICLR_GIWE7_SHIFT (7U)
|
|
/*! GIWE7 - Global Interrupt Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define GPIO_GICLR_GIWE7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE7_SHIFT)) & GPIO_GICLR_GIWE7_MASK)
|
|
|
|
#define GPIO_GICLR_GIWE8_MASK (0x100U)
|
|
#define GPIO_GICLR_GIWE8_SHIFT (8U)
|
|
/*! GIWE8 - Global Interrupt Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define GPIO_GICLR_GIWE8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE8_SHIFT)) & GPIO_GICLR_GIWE8_MASK)
|
|
|
|
#define GPIO_GICLR_GIWE9_MASK (0x200U)
|
|
#define GPIO_GICLR_GIWE9_SHIFT (9U)
|
|
/*! GIWE9 - Global Interrupt Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define GPIO_GICLR_GIWE9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE9_SHIFT)) & GPIO_GICLR_GIWE9_MASK)
|
|
|
|
#define GPIO_GICLR_GIWE10_MASK (0x400U)
|
|
#define GPIO_GICLR_GIWE10_SHIFT (10U)
|
|
/*! GIWE10 - Global Interrupt Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define GPIO_GICLR_GIWE10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE10_SHIFT)) & GPIO_GICLR_GIWE10_MASK)
|
|
|
|
#define GPIO_GICLR_GIWE11_MASK (0x800U)
|
|
#define GPIO_GICLR_GIWE11_SHIFT (11U)
|
|
/*! GIWE11 - Global Interrupt Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define GPIO_GICLR_GIWE11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE11_SHIFT)) & GPIO_GICLR_GIWE11_MASK)
|
|
|
|
#define GPIO_GICLR_GIWE12_MASK (0x1000U)
|
|
#define GPIO_GICLR_GIWE12_SHIFT (12U)
|
|
/*! GIWE12 - Global Interrupt Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define GPIO_GICLR_GIWE12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE12_SHIFT)) & GPIO_GICLR_GIWE12_MASK)
|
|
|
|
#define GPIO_GICLR_GIWE13_MASK (0x2000U)
|
|
#define GPIO_GICLR_GIWE13_SHIFT (13U)
|
|
/*! GIWE13 - Global Interrupt Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define GPIO_GICLR_GIWE13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE13_SHIFT)) & GPIO_GICLR_GIWE13_MASK)
|
|
|
|
#define GPIO_GICLR_GIWE14_MASK (0x4000U)
|
|
#define GPIO_GICLR_GIWE14_SHIFT (14U)
|
|
/*! GIWE14 - Global Interrupt Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define GPIO_GICLR_GIWE14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE14_SHIFT)) & GPIO_GICLR_GIWE14_MASK)
|
|
|
|
#define GPIO_GICLR_GIWE15_MASK (0x8000U)
|
|
#define GPIO_GICLR_GIWE15_SHIFT (15U)
|
|
/*! GIWE15 - Global Interrupt Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define GPIO_GICLR_GIWE15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE15_SHIFT)) & GPIO_GICLR_GIWE15_MASK)
|
|
|
|
#define GPIO_GICLR_GIWD_MASK (0xFFFF0000U)
|
|
#define GPIO_GICLR_GIWD_SHIFT (16U)
|
|
/*! GIWD - Global Interrupt Write Data */
|
|
#define GPIO_GICLR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWD_SHIFT)) & GPIO_GICLR_GIWD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GICHR - Global Interrupt Control High */
|
|
/*! @{ */
|
|
|
|
#define GPIO_GICHR_GIWE16_MASK (0x1U)
|
|
#define GPIO_GICHR_GIWE16_SHIFT (0U)
|
|
/*! GIWE16 - Global Interrupt Write Enable
|
|
* 0b0..Not updated.
|
|
* 0b1..Updated
|
|
*/
|
|
#define GPIO_GICHR_GIWE16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE16_SHIFT)) & GPIO_GICHR_GIWE16_MASK)
|
|
|
|
#define GPIO_GICHR_GIWE17_MASK (0x2U)
|
|
#define GPIO_GICHR_GIWE17_SHIFT (1U)
|
|
/*! GIWE17 - Global Interrupt Write Enable
|
|
* 0b0..Not updated.
|
|
* 0b1..Updated
|
|
*/
|
|
#define GPIO_GICHR_GIWE17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE17_SHIFT)) & GPIO_GICHR_GIWE17_MASK)
|
|
|
|
#define GPIO_GICHR_GIWE18_MASK (0x4U)
|
|
#define GPIO_GICHR_GIWE18_SHIFT (2U)
|
|
/*! GIWE18 - Global Interrupt Write Enable
|
|
* 0b0..Not updated.
|
|
* 0b1..Updated
|
|
*/
|
|
#define GPIO_GICHR_GIWE18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE18_SHIFT)) & GPIO_GICHR_GIWE18_MASK)
|
|
|
|
#define GPIO_GICHR_GIWE19_MASK (0x8U)
|
|
#define GPIO_GICHR_GIWE19_SHIFT (3U)
|
|
/*! GIWE19 - Global Interrupt Write Enable
|
|
* 0b0..Not updated.
|
|
* 0b1..Updated
|
|
*/
|
|
#define GPIO_GICHR_GIWE19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE19_SHIFT)) & GPIO_GICHR_GIWE19_MASK)
|
|
|
|
#define GPIO_GICHR_GIWE20_MASK (0x10U)
|
|
#define GPIO_GICHR_GIWE20_SHIFT (4U)
|
|
/*! GIWE20 - Global Interrupt Write Enable
|
|
* 0b0..Not updated.
|
|
* 0b1..Updated
|
|
*/
|
|
#define GPIO_GICHR_GIWE20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE20_SHIFT)) & GPIO_GICHR_GIWE20_MASK)
|
|
|
|
#define GPIO_GICHR_GIWE21_MASK (0x20U)
|
|
#define GPIO_GICHR_GIWE21_SHIFT (5U)
|
|
/*! GIWE21 - Global Interrupt Write Enable
|
|
* 0b0..Not updated.
|
|
* 0b1..Updated
|
|
*/
|
|
#define GPIO_GICHR_GIWE21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE21_SHIFT)) & GPIO_GICHR_GIWE21_MASK)
|
|
|
|
#define GPIO_GICHR_GIWE22_MASK (0x40U)
|
|
#define GPIO_GICHR_GIWE22_SHIFT (6U)
|
|
/*! GIWE22 - Global Interrupt Write Enable
|
|
* 0b0..Not updated.
|
|
* 0b1..Updated
|
|
*/
|
|
#define GPIO_GICHR_GIWE22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE22_SHIFT)) & GPIO_GICHR_GIWE22_MASK)
|
|
|
|
#define GPIO_GICHR_GIWE23_MASK (0x80U)
|
|
#define GPIO_GICHR_GIWE23_SHIFT (7U)
|
|
/*! GIWE23 - Global Interrupt Write Enable
|
|
* 0b0..Not updated.
|
|
* 0b1..Updated
|
|
*/
|
|
#define GPIO_GICHR_GIWE23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE23_SHIFT)) & GPIO_GICHR_GIWE23_MASK)
|
|
|
|
#define GPIO_GICHR_GIWE24_MASK (0x100U)
|
|
#define GPIO_GICHR_GIWE24_SHIFT (8U)
|
|
/*! GIWE24 - Global Interrupt Write Enable
|
|
* 0b0..Not updated.
|
|
* 0b1..Updated
|
|
*/
|
|
#define GPIO_GICHR_GIWE24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE24_SHIFT)) & GPIO_GICHR_GIWE24_MASK)
|
|
|
|
#define GPIO_GICHR_GIWE25_MASK (0x200U)
|
|
#define GPIO_GICHR_GIWE25_SHIFT (9U)
|
|
/*! GIWE25 - Global Interrupt Write Enable
|
|
* 0b0..Not updated.
|
|
* 0b1..Updated
|
|
*/
|
|
#define GPIO_GICHR_GIWE25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE25_SHIFT)) & GPIO_GICHR_GIWE25_MASK)
|
|
|
|
#define GPIO_GICHR_GIWE26_MASK (0x400U)
|
|
#define GPIO_GICHR_GIWE26_SHIFT (10U)
|
|
/*! GIWE26 - Global Interrupt Write Enable
|
|
* 0b0..Not updated.
|
|
* 0b1..Updated
|
|
*/
|
|
#define GPIO_GICHR_GIWE26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE26_SHIFT)) & GPIO_GICHR_GIWE26_MASK)
|
|
|
|
#define GPIO_GICHR_GIWE27_MASK (0x800U)
|
|
#define GPIO_GICHR_GIWE27_SHIFT (11U)
|
|
/*! GIWE27 - Global Interrupt Write Enable
|
|
* 0b0..Not updated.
|
|
* 0b1..Updated
|
|
*/
|
|
#define GPIO_GICHR_GIWE27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE27_SHIFT)) & GPIO_GICHR_GIWE27_MASK)
|
|
|
|
#define GPIO_GICHR_GIWE28_MASK (0x1000U)
|
|
#define GPIO_GICHR_GIWE28_SHIFT (12U)
|
|
/*! GIWE28 - Global Interrupt Write Enable
|
|
* 0b0..Not updated.
|
|
* 0b1..Updated
|
|
*/
|
|
#define GPIO_GICHR_GIWE28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE28_SHIFT)) & GPIO_GICHR_GIWE28_MASK)
|
|
|
|
#define GPIO_GICHR_GIWE29_MASK (0x2000U)
|
|
#define GPIO_GICHR_GIWE29_SHIFT (13U)
|
|
/*! GIWE29 - Global Interrupt Write Enable
|
|
* 0b0..Not updated.
|
|
* 0b1..Updated
|
|
*/
|
|
#define GPIO_GICHR_GIWE29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE29_SHIFT)) & GPIO_GICHR_GIWE29_MASK)
|
|
|
|
#define GPIO_GICHR_GIWE30_MASK (0x4000U)
|
|
#define GPIO_GICHR_GIWE30_SHIFT (14U)
|
|
/*! GIWE30 - Global Interrupt Write Enable
|
|
* 0b0..Not updated.
|
|
* 0b1..Updated
|
|
*/
|
|
#define GPIO_GICHR_GIWE30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE30_SHIFT)) & GPIO_GICHR_GIWE30_MASK)
|
|
|
|
#define GPIO_GICHR_GIWE31_MASK (0x8000U)
|
|
#define GPIO_GICHR_GIWE31_SHIFT (15U)
|
|
/*! GIWE31 - Global Interrupt Write Enable
|
|
* 0b0..Not updated.
|
|
* 0b1..Updated
|
|
*/
|
|
#define GPIO_GICHR_GIWE31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE31_SHIFT)) & GPIO_GICHR_GIWE31_MASK)
|
|
|
|
#define GPIO_GICHR_GIWD_MASK (0xFFFF0000U)
|
|
#define GPIO_GICHR_GIWD_SHIFT (16U)
|
|
/*! GIWD - Global Interrupt Write Data */
|
|
#define GPIO_GICHR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWD_SHIFT)) & GPIO_GICHR_GIWD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ISFR - Interrupt Status Flag */
|
|
/*! @{ */
|
|
|
|
#define GPIO_ISFR_ISF0_MASK (0x1U)
|
|
#define GPIO_ISFR_ISF0_SHIFT (0U)
|
|
/*! ISF0 - Interrupt Status Flag
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define GPIO_ISFR_ISF0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF0_SHIFT)) & GPIO_ISFR_ISF0_MASK)
|
|
|
|
#define GPIO_ISFR_ISF1_MASK (0x2U)
|
|
#define GPIO_ISFR_ISF1_SHIFT (1U)
|
|
/*! ISF1 - Interrupt Status Flag
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define GPIO_ISFR_ISF1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF1_SHIFT)) & GPIO_ISFR_ISF1_MASK)
|
|
|
|
#define GPIO_ISFR_ISF2_MASK (0x4U)
|
|
#define GPIO_ISFR_ISF2_SHIFT (2U)
|
|
/*! ISF2 - Interrupt Status Flag
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define GPIO_ISFR_ISF2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF2_SHIFT)) & GPIO_ISFR_ISF2_MASK)
|
|
|
|
#define GPIO_ISFR_ISF3_MASK (0x8U)
|
|
#define GPIO_ISFR_ISF3_SHIFT (3U)
|
|
/*! ISF3 - Interrupt Status Flag
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define GPIO_ISFR_ISF3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF3_SHIFT)) & GPIO_ISFR_ISF3_MASK)
|
|
|
|
#define GPIO_ISFR_ISF4_MASK (0x10U)
|
|
#define GPIO_ISFR_ISF4_SHIFT (4U)
|
|
/*! ISF4 - Interrupt Status Flag
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define GPIO_ISFR_ISF4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF4_SHIFT)) & GPIO_ISFR_ISF4_MASK)
|
|
|
|
#define GPIO_ISFR_ISF5_MASK (0x20U)
|
|
#define GPIO_ISFR_ISF5_SHIFT (5U)
|
|
/*! ISF5 - Interrupt Status Flag
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define GPIO_ISFR_ISF5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF5_SHIFT)) & GPIO_ISFR_ISF5_MASK)
|
|
|
|
#define GPIO_ISFR_ISF6_MASK (0x40U)
|
|
#define GPIO_ISFR_ISF6_SHIFT (6U)
|
|
/*! ISF6 - Interrupt Status Flag
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define GPIO_ISFR_ISF6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF6_SHIFT)) & GPIO_ISFR_ISF6_MASK)
|
|
|
|
#define GPIO_ISFR_ISF7_MASK (0x80U)
|
|
#define GPIO_ISFR_ISF7_SHIFT (7U)
|
|
/*! ISF7 - Interrupt Status Flag
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define GPIO_ISFR_ISF7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF7_SHIFT)) & GPIO_ISFR_ISF7_MASK)
|
|
|
|
#define GPIO_ISFR_ISF8_MASK (0x100U)
|
|
#define GPIO_ISFR_ISF8_SHIFT (8U)
|
|
/*! ISF8 - Interrupt Status Flag
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define GPIO_ISFR_ISF8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF8_SHIFT)) & GPIO_ISFR_ISF8_MASK)
|
|
|
|
#define GPIO_ISFR_ISF9_MASK (0x200U)
|
|
#define GPIO_ISFR_ISF9_SHIFT (9U)
|
|
/*! ISF9 - Interrupt Status Flag
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define GPIO_ISFR_ISF9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF9_SHIFT)) & GPIO_ISFR_ISF9_MASK)
|
|
|
|
#define GPIO_ISFR_ISF10_MASK (0x400U)
|
|
#define GPIO_ISFR_ISF10_SHIFT (10U)
|
|
/*! ISF10 - Interrupt Status Flag
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define GPIO_ISFR_ISF10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF10_SHIFT)) & GPIO_ISFR_ISF10_MASK)
|
|
|
|
#define GPIO_ISFR_ISF11_MASK (0x800U)
|
|
#define GPIO_ISFR_ISF11_SHIFT (11U)
|
|
/*! ISF11 - Interrupt Status Flag
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define GPIO_ISFR_ISF11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF11_SHIFT)) & GPIO_ISFR_ISF11_MASK)
|
|
|
|
#define GPIO_ISFR_ISF12_MASK (0x1000U)
|
|
#define GPIO_ISFR_ISF12_SHIFT (12U)
|
|
/*! ISF12 - Interrupt Status Flag
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define GPIO_ISFR_ISF12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF12_SHIFT)) & GPIO_ISFR_ISF12_MASK)
|
|
|
|
#define GPIO_ISFR_ISF13_MASK (0x2000U)
|
|
#define GPIO_ISFR_ISF13_SHIFT (13U)
|
|
/*! ISF13 - Interrupt Status Flag
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define GPIO_ISFR_ISF13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF13_SHIFT)) & GPIO_ISFR_ISF13_MASK)
|
|
|
|
#define GPIO_ISFR_ISF14_MASK (0x4000U)
|
|
#define GPIO_ISFR_ISF14_SHIFT (14U)
|
|
/*! ISF14 - Interrupt Status Flag
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define GPIO_ISFR_ISF14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF14_SHIFT)) & GPIO_ISFR_ISF14_MASK)
|
|
|
|
#define GPIO_ISFR_ISF15_MASK (0x8000U)
|
|
#define GPIO_ISFR_ISF15_SHIFT (15U)
|
|
/*! ISF15 - Interrupt Status Flag
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define GPIO_ISFR_ISF15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF15_SHIFT)) & GPIO_ISFR_ISF15_MASK)
|
|
|
|
#define GPIO_ISFR_ISF16_MASK (0x10000U)
|
|
#define GPIO_ISFR_ISF16_SHIFT (16U)
|
|
/*! ISF16 - Interrupt Status Flag
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define GPIO_ISFR_ISF16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF16_SHIFT)) & GPIO_ISFR_ISF16_MASK)
|
|
|
|
#define GPIO_ISFR_ISF17_MASK (0x20000U)
|
|
#define GPIO_ISFR_ISF17_SHIFT (17U)
|
|
/*! ISF17 - Interrupt Status Flag
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define GPIO_ISFR_ISF17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF17_SHIFT)) & GPIO_ISFR_ISF17_MASK)
|
|
|
|
#define GPIO_ISFR_ISF18_MASK (0x40000U)
|
|
#define GPIO_ISFR_ISF18_SHIFT (18U)
|
|
/*! ISF18 - Interrupt Status Flag
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define GPIO_ISFR_ISF18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF18_SHIFT)) & GPIO_ISFR_ISF18_MASK)
|
|
|
|
#define GPIO_ISFR_ISF19_MASK (0x80000U)
|
|
#define GPIO_ISFR_ISF19_SHIFT (19U)
|
|
/*! ISF19 - Interrupt Status Flag
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define GPIO_ISFR_ISF19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF19_SHIFT)) & GPIO_ISFR_ISF19_MASK)
|
|
|
|
#define GPIO_ISFR_ISF20_MASK (0x100000U)
|
|
#define GPIO_ISFR_ISF20_SHIFT (20U)
|
|
/*! ISF20 - Interrupt Status Flag
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define GPIO_ISFR_ISF20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF20_SHIFT)) & GPIO_ISFR_ISF20_MASK)
|
|
|
|
#define GPIO_ISFR_ISF21_MASK (0x200000U)
|
|
#define GPIO_ISFR_ISF21_SHIFT (21U)
|
|
/*! ISF21 - Interrupt Status Flag
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define GPIO_ISFR_ISF21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF21_SHIFT)) & GPIO_ISFR_ISF21_MASK)
|
|
|
|
#define GPIO_ISFR_ISF22_MASK (0x400000U)
|
|
#define GPIO_ISFR_ISF22_SHIFT (22U)
|
|
/*! ISF22 - Interrupt Status Flag
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define GPIO_ISFR_ISF22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF22_SHIFT)) & GPIO_ISFR_ISF22_MASK)
|
|
|
|
#define GPIO_ISFR_ISF23_MASK (0x800000U)
|
|
#define GPIO_ISFR_ISF23_SHIFT (23U)
|
|
/*! ISF23 - Interrupt Status Flag
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define GPIO_ISFR_ISF23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF23_SHIFT)) & GPIO_ISFR_ISF23_MASK)
|
|
|
|
#define GPIO_ISFR_ISF24_MASK (0x1000000U)
|
|
#define GPIO_ISFR_ISF24_SHIFT (24U)
|
|
/*! ISF24 - Interrupt Status Flag
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define GPIO_ISFR_ISF24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF24_SHIFT)) & GPIO_ISFR_ISF24_MASK)
|
|
|
|
#define GPIO_ISFR_ISF25_MASK (0x2000000U)
|
|
#define GPIO_ISFR_ISF25_SHIFT (25U)
|
|
/*! ISF25 - Interrupt Status Flag
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define GPIO_ISFR_ISF25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF25_SHIFT)) & GPIO_ISFR_ISF25_MASK)
|
|
|
|
#define GPIO_ISFR_ISF26_MASK (0x4000000U)
|
|
#define GPIO_ISFR_ISF26_SHIFT (26U)
|
|
/*! ISF26 - Interrupt Status Flag
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define GPIO_ISFR_ISF26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF26_SHIFT)) & GPIO_ISFR_ISF26_MASK)
|
|
|
|
#define GPIO_ISFR_ISF27_MASK (0x8000000U)
|
|
#define GPIO_ISFR_ISF27_SHIFT (27U)
|
|
/*! ISF27 - Interrupt Status Flag
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define GPIO_ISFR_ISF27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF27_SHIFT)) & GPIO_ISFR_ISF27_MASK)
|
|
|
|
#define GPIO_ISFR_ISF28_MASK (0x10000000U)
|
|
#define GPIO_ISFR_ISF28_SHIFT (28U)
|
|
/*! ISF28 - Interrupt Status Flag
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define GPIO_ISFR_ISF28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF28_SHIFT)) & GPIO_ISFR_ISF28_MASK)
|
|
|
|
#define GPIO_ISFR_ISF29_MASK (0x20000000U)
|
|
#define GPIO_ISFR_ISF29_SHIFT (29U)
|
|
/*! ISF29 - Interrupt Status Flag
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define GPIO_ISFR_ISF29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF29_SHIFT)) & GPIO_ISFR_ISF29_MASK)
|
|
|
|
#define GPIO_ISFR_ISF30_MASK (0x40000000U)
|
|
#define GPIO_ISFR_ISF30_SHIFT (30U)
|
|
/*! ISF30 - Interrupt Status Flag
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define GPIO_ISFR_ISF30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF30_SHIFT)) & GPIO_ISFR_ISF30_MASK)
|
|
|
|
#define GPIO_ISFR_ISF31_MASK (0x80000000U)
|
|
#define GPIO_ISFR_ISF31_SHIFT (31U)
|
|
/*! ISF31 - Interrupt Status Flag
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define GPIO_ISFR_ISF31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF31_SHIFT)) & GPIO_ISFR_ISF31_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of GPIO_ISFR */
|
|
#define GPIO_ISFR_COUNT (1U)
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group GPIO_Register_Masks */
|
|
|
|
|
|
/* GPIO - Peripheral instance base addresses */
|
|
/** Peripheral GPIO0 base address */
|
|
#define GPIO0_BASE (0x40102000u)
|
|
/** Peripheral GPIO0 base pointer */
|
|
#define GPIO0 ((GPIO_Type *)GPIO0_BASE)
|
|
/** Peripheral GPIO1 base address */
|
|
#define GPIO1_BASE (0x40103000u)
|
|
/** Peripheral GPIO1 base pointer */
|
|
#define GPIO1 ((GPIO_Type *)GPIO1_BASE)
|
|
/** Peripheral GPIO2 base address */
|
|
#define GPIO2_BASE (0x40104000u)
|
|
/** Peripheral GPIO2 base pointer */
|
|
#define GPIO2 ((GPIO_Type *)GPIO2_BASE)
|
|
/** Peripheral GPIO3 base address */
|
|
#define GPIO3_BASE (0x40105000u)
|
|
/** Peripheral GPIO3 base pointer */
|
|
#define GPIO3 ((GPIO_Type *)GPIO3_BASE)
|
|
/** Array initializer of GPIO peripheral base addresses */
|
|
#define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE }
|
|
/** Array initializer of GPIO peripheral base pointers */
|
|
#define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3 }
|
|
/** Interrupt vectors for the GPIO peripheral type */
|
|
#define GPIO_IRQS { GPIO0_IRQn, GPIO1_IRQn, GPIO2_IRQn, GPIO3_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group GPIO_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- I3C Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup I3C_Peripheral_Access_Layer I3C Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** I3C - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t MCONFIG; /**< Controller Configuration, offset: 0x0 */
|
|
__IO uint32_t SCONFIG; /**< Target Configuration, offset: 0x4 */
|
|
__IO uint32_t SSTATUS; /**< Target Status, offset: 0x8 */
|
|
__IO uint32_t SCTRL; /**< Target Control, offset: 0xC */
|
|
__IO uint32_t SINTSET; /**< Target Interrupt Set, offset: 0x10 */
|
|
__IO uint32_t SINTCLR; /**< Target Interrupt Clear, offset: 0x14 */
|
|
__I uint32_t SINTMASKED; /**< Target Interrupt Mask, offset: 0x18 */
|
|
__IO uint32_t SERRWARN; /**< Target Errors and Warnings, offset: 0x1C */
|
|
__IO uint32_t SDMACTRL; /**< Target DMA Control, offset: 0x20 */
|
|
uint8_t RESERVED_0[8];
|
|
__IO uint32_t SDATACTRL; /**< Target Data Control, offset: 0x2C */
|
|
__O uint32_t SWDATAB; /**< Target Write Data Byte, offset: 0x30 */
|
|
__O uint32_t SWDATABE; /**< Target Write Data Byte End, offset: 0x34 */
|
|
__O uint32_t SWDATAH; /**< Target Write Data Half-word, offset: 0x38 */
|
|
__O uint32_t SWDATAHE; /**< Target Write Data Half-word End, offset: 0x3C */
|
|
__I uint32_t SRDATAB; /**< Target Read Data Byte, offset: 0x40 */
|
|
uint8_t RESERVED_1[4];
|
|
__I uint32_t SRDATAH; /**< Target Read Data Halfword, offset: 0x48 */
|
|
uint8_t RESERVED_2[8];
|
|
union { /* offset: 0x54 */
|
|
__O uint32_t SWDATAB1; /**< Target Write Data Byte, offset: 0x54 */
|
|
__O uint32_t SWDATAH1; /**< Target Write Data Halfword, offset: 0x54 */
|
|
};
|
|
uint8_t RESERVED_3[4];
|
|
__I uint32_t SCAPABILITIES2; /**< Target Capabilities 2, offset: 0x5C */
|
|
__I uint32_t SCAPABILITIES; /**< Target Capabilities, offset: 0x60 */
|
|
__IO uint32_t SDYNADDR; /**< Target Dynamic Address, offset: 0x64 */
|
|
__IO uint32_t SMAXLIMITS; /**< Target Maximum Limits, offset: 0x68 */
|
|
__IO uint32_t SIDPARTNO; /**< Target ID Part Number, offset: 0x6C */
|
|
__IO uint32_t SIDEXT; /**< Target ID Extension, offset: 0x70 */
|
|
__IO uint32_t SVENDORID; /**< Target Vendor ID, offset: 0x74 */
|
|
__IO uint32_t STCCLOCK; /**< Target Time Control Clock, offset: 0x78 */
|
|
__I uint32_t SMSGMAPADDR; /**< Target Message Map Address, offset: 0x7C */
|
|
__IO uint32_t MCONFIG_EXT; /**< Controller Extended Configuration, offset: 0x80 */
|
|
__IO uint32_t MCTRL; /**< Controller Control, offset: 0x84 */
|
|
__IO uint32_t MSTATUS; /**< Controller Status, offset: 0x88 */
|
|
__IO uint32_t MIBIRULES; /**< Controller In-band Interrupt Registry and Rules, offset: 0x8C */
|
|
__IO uint32_t MINTSET; /**< Controller Interrupt Set, offset: 0x90 */
|
|
__IO uint32_t MINTCLR; /**< Controller Interrupt Clear, offset: 0x94 */
|
|
__I uint32_t MINTMASKED; /**< Controller Interrupt Mask, offset: 0x98 */
|
|
__IO uint32_t MERRWARN; /**< Controller Errors and Warnings, offset: 0x9C */
|
|
__IO uint32_t MDMACTRL; /**< Controller DMA Control, offset: 0xA0 */
|
|
uint8_t RESERVED_4[8];
|
|
__IO uint32_t MDATACTRL; /**< Controller Data Control, offset: 0xAC */
|
|
__O uint32_t MWDATAB; /**< Controller Write Data Byte, offset: 0xB0 */
|
|
__O uint32_t MWDATABE; /**< Controller Write Data Byte End, offset: 0xB4 */
|
|
__O uint32_t MWDATAH; /**< Controller Write Data Halfword, offset: 0xB8 */
|
|
__O uint32_t MWDATAHE; /**< Controller Write Data Halfword End, offset: 0xBC */
|
|
__I uint32_t MRDATAB; /**< Controller Read Data Byte, offset: 0xC0 */
|
|
uint8_t RESERVED_5[4];
|
|
__I uint32_t MRDATAH; /**< Controller Read Data Halfword, offset: 0xC8 */
|
|
union { /* offset: 0xCC */
|
|
__O uint32_t MWDATAB1; /**< Controller Write Byte Data 1(to bus), offset: 0xCC */
|
|
__O uint32_t MWDATAH1; /**< Controller Write Halfword Data (to bus), offset: 0xCC */
|
|
};
|
|
union { /* offset: 0xD0 */
|
|
__O uint32_t MWMSG_SDR_CONTROL; /**< Controller Write Message Control in SDR mode, offset: 0xD0 */
|
|
__O uint32_t MWMSG_SDR_DATA; /**< Controller Write Message Data in SDR mode, offset: 0xD0 */
|
|
};
|
|
__I uint32_t MRMSG_SDR; /**< Controller Read Message in SDR mode, offset: 0xD4 */
|
|
union { /* offset: 0xD8 */
|
|
__O uint32_t MWMSG_DDR_CONTROL; /**< Controller Write Message in DDR mode: First Control Word, offset: 0xD8 */
|
|
__O uint32_t MWMSG_DDR_CONTROL2; /**< Controller Write Message in DDR mode Control 2, offset: 0xD8 */
|
|
__O uint32_t MWMSG_DDR_DATA; /**< Controller Write Message Data in DDR mode, offset: 0xD8 */
|
|
};
|
|
__I uint32_t MRMSG_DDR; /**< Controller Read Message in DDR mode, offset: 0xDC */
|
|
uint8_t RESERVED_6[4];
|
|
__IO uint32_t MDYNADDR; /**< Controller Dynamic Address, offset: 0xE4 */
|
|
uint8_t RESERVED_7[52];
|
|
__I uint32_t SMAPCTRL0; /**< Map Feature Control 0, offset: 0x11C */
|
|
uint8_t RESERVED_8[32];
|
|
__IO uint32_t IBIEXT1; /**< Extended IBI Data 1, offset: 0x140 */
|
|
__IO uint32_t IBIEXT2; /**< Extended IBI Data 2, offset: 0x144 */
|
|
uint8_t RESERVED_9[3764];
|
|
__I uint32_t SID; /**< Target Module ID, offset: 0xFFC */
|
|
} I3C_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- I3C Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup I3C_Register_Masks I3C Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name MCONFIG - Controller Configuration */
|
|
/*! @{ */
|
|
|
|
#define I3C_MCONFIG_MSTENA_MASK (0x3U)
|
|
#define I3C_MCONFIG_MSTENA_SHIFT (0U)
|
|
/*! MSTENA - Controller Enable
|
|
* 0b00..CONTROLLER_OFF
|
|
* 0b01..CONTROLLER_ON
|
|
* 0b10..CONTROLLER_CAPABLE
|
|
* 0b11..I2C_CONTROLLER_MODE
|
|
*/
|
|
#define I3C_MCONFIG_MSTENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_MSTENA_SHIFT)) & I3C_MCONFIG_MSTENA_MASK)
|
|
|
|
#define I3C_MCONFIG_DISTO_MASK (0x8U)
|
|
#define I3C_MCONFIG_DISTO_SHIFT (3U)
|
|
/*! DISTO - Disable Timeout
|
|
* 0b1..Timeout disabled, if timeout is configured
|
|
* 0b0..Timeout enabled
|
|
*/
|
|
#define I3C_MCONFIG_DISTO(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_DISTO_SHIFT)) & I3C_MCONFIG_DISTO_MASK)
|
|
|
|
#define I3C_MCONFIG_HKEEP_MASK (0x30U)
|
|
#define I3C_MCONFIG_HKEEP_SHIFT (4U)
|
|
/*! HKEEP - High-Keeper
|
|
* 0b00..NONE
|
|
* 0b01..WIRED_IN
|
|
* 0b10..PASSIVE_SDA
|
|
* 0b11..PASSIVE_ON_SDA_SCL
|
|
*/
|
|
#define I3C_MCONFIG_HKEEP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_HKEEP_SHIFT)) & I3C_MCONFIG_HKEEP_MASK)
|
|
|
|
#define I3C_MCONFIG_ODSTOP_MASK (0x40U)
|
|
#define I3C_MCONFIG_ODSTOP_SHIFT (6U)
|
|
/*! ODSTOP - Open Drain Stop
|
|
* 0b1..Enable open-drain stop. STOP is emitted at open-drain speeds even for I3C messages. In legacy devices,
|
|
* this feature can ensure that the legacy devices see the STOP.
|
|
* 0b0..Disable open-drain stop. ODSTOP must be disabled when sending an HDR exit pattern.
|
|
*/
|
|
#define I3C_MCONFIG_ODSTOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODSTOP_SHIFT)) & I3C_MCONFIG_ODSTOP_MASK)
|
|
|
|
#define I3C_MCONFIG_PPBAUD_MASK (0xF00U)
|
|
#define I3C_MCONFIG_PPBAUD_SHIFT (8U)
|
|
/*! PPBAUD - Push-Pull Baud Rate */
|
|
#define I3C_MCONFIG_PPBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPBAUD_SHIFT)) & I3C_MCONFIG_PPBAUD_MASK)
|
|
|
|
#define I3C_MCONFIG_PPLOW_MASK (0xF000U)
|
|
#define I3C_MCONFIG_PPLOW_SHIFT (12U)
|
|
/*! PPLOW - Push-Pull Low */
|
|
#define I3C_MCONFIG_PPLOW(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPLOW_SHIFT)) & I3C_MCONFIG_PPLOW_MASK)
|
|
|
|
#define I3C_MCONFIG_ODBAUD_MASK (0xFF0000U)
|
|
#define I3C_MCONFIG_ODBAUD_SHIFT (16U)
|
|
/*! ODBAUD - Open Drain Baud Rate */
|
|
#define I3C_MCONFIG_ODBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODBAUD_SHIFT)) & I3C_MCONFIG_ODBAUD_MASK)
|
|
|
|
#define I3C_MCONFIG_ODHPP_MASK (0x1000000U)
|
|
#define I3C_MCONFIG_ODHPP_SHIFT (24U)
|
|
/*! ODHPP - Open Drain High Push-Pull
|
|
* 0b1..ODHPP enabled. Open-Drain High SCL half-lock period is one PPBAUD count for I3C messages. This setting is
|
|
* faster (and works for I3C devices). Any legacy I2C devices on the bus will not see the SCL High at all
|
|
* (less than the spike filter period).
|
|
* 0b0..ODHPP disabled. Open-Drain SCL High half-clock period is the same as the Open-Drain Low SCL half-period.
|
|
*/
|
|
#define I3C_MCONFIG_ODHPP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK)
|
|
|
|
#define I3C_MCONFIG_SKEW_MASK (0xE000000U)
|
|
#define I3C_MCONFIG_SKEW_SHIFT (25U)
|
|
/*! SKEW - Skew */
|
|
#define I3C_MCONFIG_SKEW(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_SKEW_SHIFT)) & I3C_MCONFIG_SKEW_MASK)
|
|
|
|
#define I3C_MCONFIG_I2CBAUD_MASK (0xF0000000U)
|
|
#define I3C_MCONFIG_I2CBAUD_SHIFT (28U)
|
|
/*! I2CBAUD - I2C Baud Rate */
|
|
#define I3C_MCONFIG_I2CBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_I2CBAUD_SHIFT)) & I3C_MCONFIG_I2CBAUD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SCONFIG - Target Configuration */
|
|
/*! @{ */
|
|
|
|
#define I3C_SCONFIG_SLVENA_MASK (0x1U)
|
|
#define I3C_SCONFIG_SLVENA_SHIFT (0U)
|
|
/*! SLVENA - Target Enable
|
|
* 0b1..Target can operate on the I2C or I3C bus
|
|
* 0b0..Target ignores the I2C or I3C bus
|
|
*/
|
|
#define I3C_SCONFIG_SLVENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK)
|
|
|
|
#define I3C_SCONFIG_NACK_MASK (0x2U)
|
|
#define I3C_SCONFIG_NACK_SHIFT (1U)
|
|
/*! NACK - Not Acknowledge
|
|
* 0b1..Always NACK enable. The target rejects all requests to it, except for a Common Command Code (CCC)
|
|
* broadcast. NACK = 1 should be used with caution, because the controller may decide that the target is missing, if
|
|
* NACK is overused.
|
|
* 0b0..Always NACK disable
|
|
*/
|
|
#define I3C_SCONFIG_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_NACK_SHIFT)) & I3C_SCONFIG_NACK_MASK)
|
|
|
|
#define I3C_SCONFIG_MATCHSS_MASK (0x4U)
|
|
#define I3C_SCONFIG_MATCHSS_SHIFT (2U)
|
|
/*! MATCHSS - Match START or STOP
|
|
* 0b1..Match START or STOP enable. START and STOP sticky SSTATUS bits only become 1 when SSTATUS[MATCHED] is 1.
|
|
* This setting allows START and STOP to be used to detect the end of a message to/from this target.
|
|
* 0b0..Match START or STOP disable
|
|
*/
|
|
#define I3C_SCONFIG_MATCHSS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_MATCHSS_SHIFT)) & I3C_SCONFIG_MATCHSS_MASK)
|
|
|
|
#define I3C_SCONFIG_S0IGNORE_MASK (0x8U)
|
|
#define I3C_SCONFIG_S0IGNORE_SHIFT (3U)
|
|
/*! S0IGNORE - Ignore TE0/TE1 Errors
|
|
* 0b1..Ignore TE0/TE1 errors. Target does not detect TE0 or TE1 errors, so it does not lock up waiting on an
|
|
* Exit Pattern. This setting should only be used when the bus does not use HDR mode.
|
|
* 0b0..Do not ignore TE0/TE1 errors
|
|
*/
|
|
#define I3C_SCONFIG_S0IGNORE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_S0IGNORE_SHIFT)) & I3C_SCONFIG_S0IGNORE_MASK)
|
|
|
|
#define I3C_SCONFIG_HDROK_MASK (0x10U)
|
|
#define I3C_SCONFIG_HDROK_SHIFT (4U)
|
|
/*! HDROK - HDR OK
|
|
* 0b1..Enable HDR OK. Allow HDR-DDR and/or HDR-BT messaging if available by setting the corresponding
|
|
* SIDEXT[BCR] bit to say HDR is available, and the corresponding GETCAPS bit for DDR and/or BT bit permitting use.
|
|
* 0b0..Disable HDR OK.
|
|
*/
|
|
#define I3C_SCONFIG_HDROK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_HDROK_SHIFT)) & I3C_SCONFIG_HDROK_MASK)
|
|
|
|
#define I3C_SCONFIG_OFFLINE_MASK (0x200U)
|
|
#define I3C_SCONFIG_OFFLINE_SHIFT (9U)
|
|
/*! OFFLINE - Offline
|
|
* 0b1..Enables wait to ensure the bus is not in HDR mode.
|
|
* 0b0..Disable
|
|
*/
|
|
#define I3C_SCONFIG_OFFLINE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_OFFLINE_SHIFT)) & I3C_SCONFIG_OFFLINE_MASK)
|
|
|
|
#define I3C_SCONFIG_BAMATCH_MASK (0xFF0000U)
|
|
#define I3C_SCONFIG_BAMATCH_SHIFT (16U)
|
|
/*! BAMATCH - Bus Available Match */
|
|
#define I3C_SCONFIG_BAMATCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_BAMATCH_SHIFT)) & I3C_SCONFIG_BAMATCH_MASK)
|
|
|
|
#define I3C_SCONFIG_SADDR_MASK (0xFE000000U)
|
|
#define I3C_SCONFIG_SADDR_SHIFT (25U)
|
|
/*! SADDR - Static Address */
|
|
#define I3C_SCONFIG_SADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SADDR_SHIFT)) & I3C_SCONFIG_SADDR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SSTATUS - Target Status */
|
|
/*! @{ */
|
|
|
|
#define I3C_SSTATUS_STNOTSTOP_MASK (0x1U)
|
|
#define I3C_SSTATUS_STNOTSTOP_SHIFT (0U)
|
|
/*! STNOTSTOP - Status Not Stop
|
|
* 0b1..The bus is busy (has activity).
|
|
* 0b0..I3C module is in a STOP condition.
|
|
*/
|
|
#define I3C_SSTATUS_STNOTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STNOTSTOP_SHIFT)) & I3C_SSTATUS_STNOTSTOP_MASK)
|
|
|
|
#define I3C_SSTATUS_STMSG_MASK (0x2U)
|
|
#define I3C_SSTATUS_STMSG_SHIFT (1U)
|
|
/*! STMSG - Status message
|
|
* 0b1..This bus target is listening to the bus traffic or responding.
|
|
* 0b0..Bus target not listening or responding.
|
|
*/
|
|
#define I3C_SSTATUS_STMSG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STMSG_SHIFT)) & I3C_SSTATUS_STMSG_MASK)
|
|
|
|
#define I3C_SSTATUS_STCCCH_MASK (0x4U)
|
|
#define I3C_SSTATUS_STCCCH_SHIFT (2U)
|
|
/*! STCCCH - Status Common Command Code Handler
|
|
* 0b1..A CCC message is being handled automatically.
|
|
* 0b0..No CCC message is being handled.
|
|
*/
|
|
#define I3C_SSTATUS_STCCCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STCCCH_SHIFT)) & I3C_SSTATUS_STCCCH_MASK)
|
|
|
|
#define I3C_SSTATUS_STREQRD_MASK (0x8U)
|
|
#define I3C_SSTATUS_STREQRD_SHIFT (3U)
|
|
/*! STREQRD - Status Request Read
|
|
* 0b1..The REQ in process is an SDR read from this target, or an In-Band Interrupt (IBI) is being pushed out.
|
|
* 0b0..REQ in process is not an SDR read from this target.
|
|
*/
|
|
#define I3C_SSTATUS_STREQRD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQRD_SHIFT)) & I3C_SSTATUS_STREQRD_MASK)
|
|
|
|
#define I3C_SSTATUS_STREQWR_MASK (0x10U)
|
|
#define I3C_SSTATUS_STREQWR_SHIFT (4U)
|
|
/*! STREQWR - Status Request Write
|
|
* 0b1..REQ in process is SDR write data from the controller to this bus target (or all targets), but not in ENTDAA mode.
|
|
* 0b0..REQ in process is not SDR write data from the controller.
|
|
*/
|
|
#define I3C_SSTATUS_STREQWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQWR_SHIFT)) & I3C_SSTATUS_STREQWR_MASK)
|
|
|
|
#define I3C_SSTATUS_STDAA_MASK (0x20U)
|
|
#define I3C_SSTATUS_STDAA_SHIFT (5U)
|
|
/*! STDAA - Status Dynamic Address Assignment
|
|
* 0b1..I3C bus is in Enter Dynamic Address Assignment (ENTDAA) mode, regardless of whether this bus target has a Dynamic Address or not.
|
|
* 0b0..Not in ENTDAA mode.
|
|
*/
|
|
#define I3C_SSTATUS_STDAA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STDAA_SHIFT)) & I3C_SSTATUS_STDAA_MASK)
|
|
|
|
#define I3C_SSTATUS_STHDR_MASK (0x40U)
|
|
#define I3C_SSTATUS_STHDR_SHIFT (6U)
|
|
/*! STHDR - Status High Data Rate
|
|
* 0b1..The I3C bus is in HDR-DDR mode, regardless of whether HDR mode is supported by this module or not, and
|
|
* regardless of whether the message is to this module or to some other module.
|
|
* 0b0..I3C bus not in HDR-DDR mode
|
|
*/
|
|
#define I3C_SSTATUS_STHDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STHDR_SHIFT)) & I3C_SSTATUS_STHDR_MASK)
|
|
|
|
#define I3C_SSTATUS_START_MASK (0x100U)
|
|
#define I3C_SSTATUS_START_SHIFT (8U)
|
|
/*! START - Start
|
|
* 0b1..A START or repeated START was seen after the START bit was last cleared.
|
|
* 0b0..No START seen.
|
|
*/
|
|
#define I3C_SSTATUS_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_START_SHIFT)) & I3C_SSTATUS_START_MASK)
|
|
|
|
#define I3C_SSTATUS_MATCHED_MASK (0x200U)
|
|
#define I3C_SSTATUS_MATCHED_SHIFT (9U)
|
|
/*! MATCHED - Matched
|
|
* 0b1..An incoming header matched the I3C Dynamic or I2C Static address of this device (if any) since the bus was last cleared.
|
|
* 0b0..No header matched.
|
|
*/
|
|
#define I3C_SSTATUS_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MATCHED_SHIFT)) & I3C_SSTATUS_MATCHED_MASK)
|
|
|
|
#define I3C_SSTATUS_STOP_MASK (0x400U)
|
|
#define I3C_SSTATUS_STOP_SHIFT (10U)
|
|
/*! STOP - Stop
|
|
* 0b1..Stopped state detected. A STOP state was present on the bus since the bus was last cleared.
|
|
* 0b0..No STOP detected.
|
|
*/
|
|
#define I3C_SSTATUS_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STOP_SHIFT)) & I3C_SSTATUS_STOP_MASK)
|
|
|
|
#define I3C_SSTATUS_RX_PEND_MASK (0x800U)
|
|
#define I3C_SSTATUS_RX_PEND_SHIFT (11U)
|
|
/*! RX_PEND - Received Message Pending
|
|
* 0b1..Received message is pending.
|
|
* 0b0..No received message is pending.
|
|
*/
|
|
#define I3C_SSTATUS_RX_PEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_RX_PEND_SHIFT)) & I3C_SSTATUS_RX_PEND_MASK)
|
|
|
|
#define I3C_SSTATUS_TXNOTFULL_MASK (0x1000U)
|
|
#define I3C_SSTATUS_TXNOTFULL_SHIFT (12U)
|
|
/*! TXNOTFULL - Transmit Buffer Is Not Full
|
|
* 0b1..Transmit buffer not full
|
|
* 0b0..Transmit buffer full
|
|
*/
|
|
#define I3C_SSTATUS_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TXNOTFULL_SHIFT)) & I3C_SSTATUS_TXNOTFULL_MASK)
|
|
|
|
#define I3C_SSTATUS_DACHG_MASK (0x2000U)
|
|
#define I3C_SSTATUS_DACHG_SHIFT (13U)
|
|
/*! DACHG - Dynamic Address Change
|
|
* 0b1..DA change detected. The target DA has been assigned, re-assigned, or reset (lost) and is now in the state of being valid or none.
|
|
* 0b0..No DA change detected.
|
|
*/
|
|
#define I3C_SSTATUS_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_DACHG_SHIFT)) & I3C_SSTATUS_DACHG_MASK)
|
|
|
|
#define I3C_SSTATUS_CCC_MASK (0x4000U)
|
|
#define I3C_SSTATUS_CCC_SHIFT (14U)
|
|
/*! CCC - Common Command Code
|
|
* 0b1..CCC received.
|
|
* 0b0..No CCC received.
|
|
*/
|
|
#define I3C_SSTATUS_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CCC_SHIFT)) & I3C_SSTATUS_CCC_MASK)
|
|
|
|
#define I3C_SSTATUS_ERRWARN_MASK (0x8000U)
|
|
#define I3C_SSTATUS_ERRWARN_SHIFT (15U)
|
|
/*! ERRWARN - Error Warning */
|
|
#define I3C_SSTATUS_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ERRWARN_SHIFT)) & I3C_SSTATUS_ERRWARN_MASK)
|
|
|
|
#define I3C_SSTATUS_HDRMATCH_MASK (0x10000U)
|
|
#define I3C_SSTATUS_HDRMATCH_SHIFT (16U)
|
|
/*! HDRMATCH - High Data Rate Command Match
|
|
* 0b1..HDR command matched the I3C Dynamic Address of this device.
|
|
* 0b0..HDR command did not match.
|
|
*/
|
|
#define I3C_SSTATUS_HDRMATCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HDRMATCH_SHIFT)) & I3C_SSTATUS_HDRMATCH_MASK)
|
|
|
|
#define I3C_SSTATUS_CHANDLED_MASK (0x20000U)
|
|
#define I3C_SSTATUS_CHANDLED_SHIFT (17U)
|
|
/*! CHANDLED - Common Command Code Handled
|
|
* 0b1..CCC handling in progress.
|
|
* 0b0..CCC handling not in progress.
|
|
*/
|
|
#define I3C_SSTATUS_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CHANDLED_SHIFT)) & I3C_SSTATUS_CHANDLED_MASK)
|
|
|
|
#define I3C_SSTATUS_EVENT_MASK (0x40000U)
|
|
#define I3C_SSTATUS_EVENT_SHIFT (18U)
|
|
/*! EVENT - Event
|
|
* 0b1..An IBI, CR, or HJ has occurred.
|
|
* 0b0..No event has occurred.
|
|
*/
|
|
#define I3C_SSTATUS_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVENT_SHIFT)) & I3C_SSTATUS_EVENT_MASK)
|
|
|
|
#define I3C_SSTATUS_EVDET_MASK (0x300000U)
|
|
#define I3C_SSTATUS_EVDET_SHIFT (20U)
|
|
/*! EVDET - Event Details
|
|
* 0b00..NONE
|
|
* 0b01..NO_REQUEST
|
|
* 0b10..NACKED
|
|
* 0b11..ACKED
|
|
*/
|
|
#define I3C_SSTATUS_EVDET(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVDET_SHIFT)) & I3C_SSTATUS_EVDET_MASK)
|
|
|
|
#define I3C_SSTATUS_IBIDIS_MASK (0x1000000U)
|
|
#define I3C_SSTATUS_IBIDIS_SHIFT (24U)
|
|
/*! IBIDIS - In-Band Interrupts Are Disabled
|
|
* 0b1..In-Band Interrupts disabled
|
|
* 0b0..In-Band Interrupts not disabled
|
|
*/
|
|
#define I3C_SSTATUS_IBIDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_IBIDIS_SHIFT)) & I3C_SSTATUS_IBIDIS_MASK)
|
|
|
|
#define I3C_SSTATUS_MRDIS_MASK (0x2000000U)
|
|
#define I3C_SSTATUS_MRDIS_SHIFT (25U)
|
|
/*! MRDIS - Controller Requests Are Disabled
|
|
* 0b1..Controller Requests disabled
|
|
* 0b0..Controller Requests not disabled
|
|
*/
|
|
#define I3C_SSTATUS_MRDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MRDIS_SHIFT)) & I3C_SSTATUS_MRDIS_MASK)
|
|
|
|
#define I3C_SSTATUS_HJDIS_MASK (0x8000000U)
|
|
#define I3C_SSTATUS_HJDIS_SHIFT (27U)
|
|
/*! HJDIS - Hot-Join Disabled
|
|
* 0b1..Hot-Join disabled
|
|
* 0b0..Hot-Join not disabled
|
|
*/
|
|
#define I3C_SSTATUS_HJDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HJDIS_SHIFT)) & I3C_SSTATUS_HJDIS_MASK)
|
|
|
|
#define I3C_SSTATUS_ACTSTATE_MASK (0x30000000U)
|
|
#define I3C_SSTATUS_ACTSTATE_SHIFT (28U)
|
|
/*! ACTSTATE - Activity State from Common Command Codes (CCC)
|
|
* 0b00..NO_LATENCY
|
|
* 0b01..LATENCY_1MS
|
|
* 0b10..LATENCY_100MS
|
|
* 0b11..LATENCY_10S
|
|
*/
|
|
#define I3C_SSTATUS_ACTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ACTSTATE_SHIFT)) & I3C_SSTATUS_ACTSTATE_MASK)
|
|
|
|
#define I3C_SSTATUS_TIMECTRL_MASK (0xC0000000U)
|
|
#define I3C_SSTATUS_TIMECTRL_SHIFT (30U)
|
|
/*! TIMECTRL - Time Control
|
|
* 0b00..NO_TIME_CONTROL
|
|
* 0b01..SYNC_MODE
|
|
* 0b10..ASYNC_MODE
|
|
* 0b11..BOTHSYNCASYNC
|
|
*/
|
|
#define I3C_SSTATUS_TIMECTRL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TIMECTRL_SHIFT)) & I3C_SSTATUS_TIMECTRL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SCTRL - Target Control */
|
|
/*! @{ */
|
|
|
|
#define I3C_SCTRL_EVENT_MASK (0x3U)
|
|
#define I3C_SCTRL_EVENT_SHIFT (0U)
|
|
/*! EVENT - Event
|
|
* 0b00..NORMAL_MODE
|
|
* 0b01..IBI
|
|
* 0b10..CONTROLLER_REQUEST
|
|
* 0b11..HOT_JOIN_REQUEST
|
|
*/
|
|
#define I3C_SCTRL_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EVENT_SHIFT)) & I3C_SCTRL_EVENT_MASK)
|
|
|
|
#define I3C_SCTRL_EXTDATA_MASK (0x8U)
|
|
#define I3C_SCTRL_EXTDATA_SHIFT (3U)
|
|
/*! EXTDATA - Extended Data
|
|
* 0b1..Extended data enabled. After IBIDATA is emitted, extended data is taken from IBIEXT1 and IBIEXT2 if configured.
|
|
* 0b0..Extended data disabled.
|
|
*/
|
|
#define I3C_SCTRL_EXTDATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EXTDATA_SHIFT)) & I3C_SCTRL_EXTDATA_MASK)
|
|
|
|
#define I3C_SCTRL_IBIDATA_MASK (0xFF00U)
|
|
#define I3C_SCTRL_IBIDATA_SHIFT (8U)
|
|
/*! IBIDATA - In-Band Interrupt Data */
|
|
#define I3C_SCTRL_IBIDATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_IBIDATA_SHIFT)) & I3C_SCTRL_IBIDATA_MASK)
|
|
|
|
#define I3C_SCTRL_PENDINT_MASK (0xF0000U)
|
|
#define I3C_SCTRL_PENDINT_SHIFT (16U)
|
|
/*! PENDINT - Pending Interrupt */
|
|
#define I3C_SCTRL_PENDINT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_PENDINT_SHIFT)) & I3C_SCTRL_PENDINT_MASK)
|
|
|
|
#define I3C_SCTRL_ACTSTATE_MASK (0x300000U)
|
|
#define I3C_SCTRL_ACTSTATE_SHIFT (20U)
|
|
/*! ACTSTATE - Activity State of Target */
|
|
#define I3C_SCTRL_ACTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_ACTSTATE_SHIFT)) & I3C_SCTRL_ACTSTATE_MASK)
|
|
|
|
#define I3C_SCTRL_VENDINFO_MASK (0xFF000000U)
|
|
#define I3C_SCTRL_VENDINFO_SHIFT (24U)
|
|
/*! VENDINFO - Vendor Information */
|
|
#define I3C_SCTRL_VENDINFO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_VENDINFO_SHIFT)) & I3C_SCTRL_VENDINFO_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SINTSET - Target Interrupt Set */
|
|
/*! @{ */
|
|
|
|
#define I3C_SINTSET_START_MASK (0x100U)
|
|
#define I3C_SINTSET_START_SHIFT (8U)
|
|
/*! START - Start Interrupt Enable
|
|
* 0b1..Enable START interrupt
|
|
* 0b0..Disable START interrupt
|
|
*/
|
|
#define I3C_SINTSET_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_START_SHIFT)) & I3C_SINTSET_START_MASK)
|
|
|
|
#define I3C_SINTSET_MATCHED_MASK (0x200U)
|
|
#define I3C_SINTSET_MATCHED_SHIFT (9U)
|
|
/*! MATCHED - Match Interrupt Enable
|
|
* 0b1..Enable match interrupt
|
|
* 0b0..Disable match interrupt
|
|
*/
|
|
#define I3C_SINTSET_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_MATCHED_SHIFT)) & I3C_SINTSET_MATCHED_MASK)
|
|
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#define I3C_SINTSET_STOP_MASK (0x400U)
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#define I3C_SINTSET_STOP_SHIFT (10U)
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/*! STOP - Stop Interrupt Enable
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* 0b1..Enable STOP interrupt
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* 0b0..Disable STOP interrupt
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*/
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#define I3C_SINTSET_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_STOP_SHIFT)) & I3C_SINTSET_STOP_MASK)
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#define I3C_SINTSET_RXPEND_MASK (0x800U)
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#define I3C_SINTSET_RXPEND_SHIFT (11U)
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/*! RXPEND - Receive Interrupt Enable
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* 0b1..Enable Receive interrupt
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* 0b0..Disable Receive interrupt
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*/
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#define I3C_SINTSET_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_RXPEND_SHIFT)) & I3C_SINTSET_RXPEND_MASK)
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#define I3C_SINTSET_TXSEND_MASK (0x1000U)
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#define I3C_SINTSET_TXSEND_SHIFT (12U)
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/*! TXSEND - Transmit Interrupt Enable
|
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* 0b1..Enable Transmit interrupt
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* 0b0..Disable Transmit interrupt
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*/
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#define I3C_SINTSET_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_TXSEND_SHIFT)) & I3C_SINTSET_TXSEND_MASK)
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#define I3C_SINTSET_DACHG_MASK (0x2000U)
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#define I3C_SINTSET_DACHG_SHIFT (13U)
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/*! DACHG - Dynamic Address Change Interrupt Enable
|
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* 0b1..Enable DA Change interrupt
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* 0b0..Disable DA Change interrupt
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*/
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#define I3C_SINTSET_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DACHG_SHIFT)) & I3C_SINTSET_DACHG_MASK)
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#define I3C_SINTSET_CCC_MASK (0x4000U)
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#define I3C_SINTSET_CCC_SHIFT (14U)
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/*! CCC - Common Command Code (CCC) Interrupt Enable
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* 0b1..Enable CCC interrupt
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* 0b0..Disable CCC interrupt
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*/
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#define I3C_SINTSET_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CCC_SHIFT)) & I3C_SINTSET_CCC_MASK)
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#define I3C_SINTSET_ERRWARN_MASK (0x8000U)
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#define I3C_SINTSET_ERRWARN_SHIFT (15U)
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/*! ERRWARN - Error or Warning Interrupt Enable
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* 0b1..Enable error or warning interrupt
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* 0b0..Disable error or warning interrupt
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*/
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#define I3C_SINTSET_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_ERRWARN_SHIFT)) & I3C_SINTSET_ERRWARN_MASK)
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#define I3C_SINTSET_DDRMATCHED_MASK (0x10000U)
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#define I3C_SINTSET_DDRMATCHED_SHIFT (16U)
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/*! DDRMATCHED - Double Data Rate Interrupt Enable
|
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* 0b1..Enable DDR interrupt
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* 0b0..Disable DDR interrupt
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*/
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#define I3C_SINTSET_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DDRMATCHED_SHIFT)) & I3C_SINTSET_DDRMATCHED_MASK)
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#define I3C_SINTSET_CHANDLED_MASK (0x20000U)
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#define I3C_SINTSET_CHANDLED_SHIFT (17U)
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/*! CHANDLED - Common Command Code (CCC) Interrupt Enable
|
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* 0b1..Enable CCC Handled interrupt
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* 0b0..Disable CCC Handled interrupt
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*/
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#define I3C_SINTSET_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CHANDLED_SHIFT)) & I3C_SINTSET_CHANDLED_MASK)
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#define I3C_SINTSET_EVENT_MASK (0x40000U)
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#define I3C_SINTSET_EVENT_SHIFT (18U)
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/*! EVENT - Event Interrupt Enable
|
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* 0b1..Enable Event interrupt
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* 0b0..Disable Event interrupt
|
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*/
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#define I3C_SINTSET_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_EVENT_SHIFT)) & I3C_SINTSET_EVENT_MASK)
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/*! @} */
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/*! @name SINTCLR - Target Interrupt Clear */
|
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/*! @{ */
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#define I3C_SINTCLR_START_MASK (0x100U)
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#define I3C_SINTCLR_START_SHIFT (8U)
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/*! START - START Interrupt Enable Clear */
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#define I3C_SINTCLR_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_START_SHIFT)) & I3C_SINTCLR_START_MASK)
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#define I3C_SINTCLR_MATCHED_MASK (0x200U)
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#define I3C_SINTCLR_MATCHED_SHIFT (9U)
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/*! MATCHED - MATCHED Interrupt Enable Clear */
|
|
#define I3C_SINTCLR_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_MATCHED_SHIFT)) & I3C_SINTCLR_MATCHED_MASK)
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#define I3C_SINTCLR_STOP_MASK (0x400U)
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#define I3C_SINTCLR_STOP_SHIFT (10U)
|
|
/*! STOP - STOP Interrupt Enable Clear */
|
|
#define I3C_SINTCLR_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_STOP_SHIFT)) & I3C_SINTCLR_STOP_MASK)
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|
|
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#define I3C_SINTCLR_RXPEND_MASK (0x800U)
|
|
#define I3C_SINTCLR_RXPEND_SHIFT (11U)
|
|
/*! RXPEND - RXPEND Interrupt Enable Clear */
|
|
#define I3C_SINTCLR_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_RXPEND_SHIFT)) & I3C_SINTCLR_RXPEND_MASK)
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|
|
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#define I3C_SINTCLR_TXSEND_MASK (0x1000U)
|
|
#define I3C_SINTCLR_TXSEND_SHIFT (12U)
|
|
/*! TXSEND - TXSEND Interrupt Enable Clear */
|
|
#define I3C_SINTCLR_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_TXSEND_SHIFT)) & I3C_SINTCLR_TXSEND_MASK)
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|
|
|
#define I3C_SINTCLR_DACHG_MASK (0x2000U)
|
|
#define I3C_SINTCLR_DACHG_SHIFT (13U)
|
|
/*! DACHG - DACHG Interrupt Enable Clear */
|
|
#define I3C_SINTCLR_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DACHG_SHIFT)) & I3C_SINTCLR_DACHG_MASK)
|
|
|
|
#define I3C_SINTCLR_CCC_MASK (0x4000U)
|
|
#define I3C_SINTCLR_CCC_SHIFT (14U)
|
|
/*! CCC - CCC Interrupt Enable Clear */
|
|
#define I3C_SINTCLR_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CCC_SHIFT)) & I3C_SINTCLR_CCC_MASK)
|
|
|
|
#define I3C_SINTCLR_ERRWARN_MASK (0x8000U)
|
|
#define I3C_SINTCLR_ERRWARN_SHIFT (15U)
|
|
/*! ERRWARN - ERRWARN Interrupt Enable Clear */
|
|
#define I3C_SINTCLR_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_ERRWARN_SHIFT)) & I3C_SINTCLR_ERRWARN_MASK)
|
|
|
|
#define I3C_SINTCLR_DDRMATCHED_MASK (0x10000U)
|
|
#define I3C_SINTCLR_DDRMATCHED_SHIFT (16U)
|
|
/*! DDRMATCHED - DDRMATCHED Interrupt Enable Clear */
|
|
#define I3C_SINTCLR_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DDRMATCHED_SHIFT)) & I3C_SINTCLR_DDRMATCHED_MASK)
|
|
|
|
#define I3C_SINTCLR_CHANDLED_MASK (0x20000U)
|
|
#define I3C_SINTCLR_CHANDLED_SHIFT (17U)
|
|
/*! CHANDLED - CHANDLED Interrupt Enable Clear */
|
|
#define I3C_SINTCLR_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CHANDLED_SHIFT)) & I3C_SINTCLR_CHANDLED_MASK)
|
|
|
|
#define I3C_SINTCLR_EVENT_MASK (0x40000U)
|
|
#define I3C_SINTCLR_EVENT_SHIFT (18U)
|
|
/*! EVENT - EVENT Interrupt Enable Clear */
|
|
#define I3C_SINTCLR_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_EVENT_SHIFT)) & I3C_SINTCLR_EVENT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SINTMASKED - Target Interrupt Mask */
|
|
/*! @{ */
|
|
|
|
#define I3C_SINTMASKED_START_MASK (0x100U)
|
|
#define I3C_SINTMASKED_START_SHIFT (8U)
|
|
/*! START - START interrupt mask */
|
|
#define I3C_SINTMASKED_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_START_SHIFT)) & I3C_SINTMASKED_START_MASK)
|
|
|
|
#define I3C_SINTMASKED_MATCHED_MASK (0x200U)
|
|
#define I3C_SINTMASKED_MATCHED_SHIFT (9U)
|
|
/*! MATCHED - MATCHED Interrupt Mask */
|
|
#define I3C_SINTMASKED_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_MATCHED_SHIFT)) & I3C_SINTMASKED_MATCHED_MASK)
|
|
|
|
#define I3C_SINTMASKED_STOP_MASK (0x400U)
|
|
#define I3C_SINTMASKED_STOP_SHIFT (10U)
|
|
/*! STOP - STOP Interrupt Mask */
|
|
#define I3C_SINTMASKED_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_STOP_SHIFT)) & I3C_SINTMASKED_STOP_MASK)
|
|
|
|
#define I3C_SINTMASKED_RXPEND_MASK (0x800U)
|
|
#define I3C_SINTMASKED_RXPEND_SHIFT (11U)
|
|
/*! RXPEND - RXPEND Interrupt Mask */
|
|
#define I3C_SINTMASKED_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_RXPEND_SHIFT)) & I3C_SINTMASKED_RXPEND_MASK)
|
|
|
|
#define I3C_SINTMASKED_TXSEND_MASK (0x1000U)
|
|
#define I3C_SINTMASKED_TXSEND_SHIFT (12U)
|
|
/*! TXSEND - TXSEND Interrupt Mask */
|
|
#define I3C_SINTMASKED_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_TXSEND_SHIFT)) & I3C_SINTMASKED_TXSEND_MASK)
|
|
|
|
#define I3C_SINTMASKED_DACHG_MASK (0x2000U)
|
|
#define I3C_SINTMASKED_DACHG_SHIFT (13U)
|
|
/*! DACHG - DACHG Interrupt Mask */
|
|
#define I3C_SINTMASKED_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DACHG_SHIFT)) & I3C_SINTMASKED_DACHG_MASK)
|
|
|
|
#define I3C_SINTMASKED_CCC_MASK (0x4000U)
|
|
#define I3C_SINTMASKED_CCC_SHIFT (14U)
|
|
/*! CCC - CCC Interrupt Mask */
|
|
#define I3C_SINTMASKED_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CCC_SHIFT)) & I3C_SINTMASKED_CCC_MASK)
|
|
|
|
#define I3C_SINTMASKED_ERRWARN_MASK (0x8000U)
|
|
#define I3C_SINTMASKED_ERRWARN_SHIFT (15U)
|
|
/*! ERRWARN - ERRWARN Interrupt Mask */
|
|
#define I3C_SINTMASKED_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_ERRWARN_SHIFT)) & I3C_SINTMASKED_ERRWARN_MASK)
|
|
|
|
#define I3C_SINTMASKED_DDRMATCHED_MASK (0x10000U)
|
|
#define I3C_SINTMASKED_DDRMATCHED_SHIFT (16U)
|
|
/*! DDRMATCHED - DDRMATCHED Interrupt Mask */
|
|
#define I3C_SINTMASKED_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DDRMATCHED_SHIFT)) & I3C_SINTMASKED_DDRMATCHED_MASK)
|
|
|
|
#define I3C_SINTMASKED_CHANDLED_MASK (0x20000U)
|
|
#define I3C_SINTMASKED_CHANDLED_SHIFT (17U)
|
|
/*! CHANDLED - CHANDLED Interrupt Mask */
|
|
#define I3C_SINTMASKED_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CHANDLED_SHIFT)) & I3C_SINTMASKED_CHANDLED_MASK)
|
|
|
|
#define I3C_SINTMASKED_EVENT_MASK (0x40000U)
|
|
#define I3C_SINTMASKED_EVENT_SHIFT (18U)
|
|
/*! EVENT - EVENT Interrupt Mask */
|
|
#define I3C_SINTMASKED_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_EVENT_SHIFT)) & I3C_SINTMASKED_EVENT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SERRWARN - Target Errors and Warnings */
|
|
/*! @{ */
|
|
|
|
#define I3C_SERRWARN_ORUN_MASK (0x1U)
|
|
#define I3C_SERRWARN_ORUN_SHIFT (0U)
|
|
/*! ORUN - Overrun Error
|
|
* 0b1..Overrun error
|
|
* 0b0..No overrun error
|
|
*/
|
|
#define I3C_SERRWARN_ORUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_ORUN_SHIFT)) & I3C_SERRWARN_ORUN_MASK)
|
|
|
|
#define I3C_SERRWARN_URUN_MASK (0x2U)
|
|
#define I3C_SERRWARN_URUN_SHIFT (1U)
|
|
/*! URUN - Underrun Error
|
|
* 0b1..Underrun error
|
|
* 0b0..No underrun error
|
|
*/
|
|
#define I3C_SERRWARN_URUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUN_SHIFT)) & I3C_SERRWARN_URUN_MASK)
|
|
|
|
#define I3C_SERRWARN_URUNNACK_MASK (0x4U)
|
|
#define I3C_SERRWARN_URUNNACK_SHIFT (2U)
|
|
/*! URUNNACK - Underrun and Not Acknowledged (NACKED) Error
|
|
* 0b1..Underrun and not acknowledged error
|
|
* 0b0..No underrun and not acknowledged error
|
|
*/
|
|
#define I3C_SERRWARN_URUNNACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUNNACK_SHIFT)) & I3C_SERRWARN_URUNNACK_MASK)
|
|
|
|
#define I3C_SERRWARN_TERM_MASK (0x8U)
|
|
#define I3C_SERRWARN_TERM_SHIFT (3U)
|
|
/*! TERM - Terminated Error
|
|
* 0b1..Terminated error
|
|
* 0b0..No terminated error
|
|
*/
|
|
#define I3C_SERRWARN_TERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_TERM_SHIFT)) & I3C_SERRWARN_TERM_MASK)
|
|
|
|
#define I3C_SERRWARN_INVSTART_MASK (0x10U)
|
|
#define I3C_SERRWARN_INVSTART_SHIFT (4U)
|
|
/*! INVSTART - Invalid Start Error
|
|
* 0b1..Invalid start error
|
|
* 0b0..No invalid start error
|
|
*/
|
|
#define I3C_SERRWARN_INVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_INVSTART_SHIFT)) & I3C_SERRWARN_INVSTART_MASK)
|
|
|
|
#define I3C_SERRWARN_SPAR_MASK (0x100U)
|
|
#define I3C_SERRWARN_SPAR_SHIFT (8U)
|
|
/*! SPAR - SDR Parity Error
|
|
* 0b1..SDR Parity error
|
|
* 0b0..No SDR Parity error
|
|
*/
|
|
#define I3C_SERRWARN_SPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_SPAR_SHIFT)) & I3C_SERRWARN_SPAR_MASK)
|
|
|
|
#define I3C_SERRWARN_HPAR_MASK (0x200U)
|
|
#define I3C_SERRWARN_HPAR_SHIFT (9U)
|
|
/*! HPAR - HDR Parity Error
|
|
* 0b1..HDR Parity error
|
|
* 0b0..No HDR Parity error
|
|
*/
|
|
#define I3C_SERRWARN_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HPAR_SHIFT)) & I3C_SERRWARN_HPAR_MASK)
|
|
|
|
#define I3C_SERRWARN_HCRC_MASK (0x400U)
|
|
#define I3C_SERRWARN_HCRC_SHIFT (10U)
|
|
/*! HCRC - HDR-DDR CRC Error
|
|
* 0b1..HDR-DDR CRC error
|
|
* 0b0..No HDR-DDR CRC error
|
|
*/
|
|
#define I3C_SERRWARN_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HCRC_SHIFT)) & I3C_SERRWARN_HCRC_MASK)
|
|
|
|
#define I3C_SERRWARN_S0S1_MASK (0x800U)
|
|
#define I3C_SERRWARN_S0S1_SHIFT (11U)
|
|
/*! S0S1 - TE0 or TE1 Error
|
|
* 0b1..TE0 or TE1 error
|
|
* 0b0..No TE0 or TE1 error
|
|
*/
|
|
#define I3C_SERRWARN_S0S1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_S0S1_SHIFT)) & I3C_SERRWARN_S0S1_MASK)
|
|
|
|
#define I3C_SERRWARN_OREAD_MASK (0x10000U)
|
|
#define I3C_SERRWARN_OREAD_SHIFT (16U)
|
|
/*! OREAD - Over-read Error
|
|
* 0b1..Over-read error
|
|
* 0b0..No Over-read error
|
|
*/
|
|
#define I3C_SERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OREAD_SHIFT)) & I3C_SERRWARN_OREAD_MASK)
|
|
|
|
#define I3C_SERRWARN_OWRITE_MASK (0x20000U)
|
|
#define I3C_SERRWARN_OWRITE_SHIFT (17U)
|
|
/*! OWRITE - Over-write Error
|
|
* 0b1..Overwrite error
|
|
* 0b0..No Overwrite error
|
|
*/
|
|
#define I3C_SERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OWRITE_SHIFT)) & I3C_SERRWARN_OWRITE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SDMACTRL - Target DMA Control */
|
|
/*! @{ */
|
|
|
|
#define I3C_SDMACTRL_DMAFB_MASK (0x3U)
|
|
#define I3C_SDMACTRL_DMAFB_SHIFT (0U)
|
|
/*! DMAFB - DMA Read (From-bus) Trigger
|
|
* 0b00..DMA not used
|
|
* 0b01..DMA is enabled for one frame
|
|
* 0b10..DMA enabled until turned off
|
|
* 0b11..
|
|
*/
|
|
#define I3C_SDMACTRL_DMAFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAFB_SHIFT)) & I3C_SDMACTRL_DMAFB_MASK)
|
|
|
|
#define I3C_SDMACTRL_DMATB_MASK (0xCU)
|
|
#define I3C_SDMACTRL_DMATB_SHIFT (2U)
|
|
/*! DMATB - DMA Write (To-bus) Trigger
|
|
* 0b00..DMA not used
|
|
* 0b01..DMA enabled for one frame (ended by DMA or terminated)
|
|
* 0b10..DMA enabled until turned off
|
|
* 0b11..
|
|
*/
|
|
#define I3C_SDMACTRL_DMATB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMATB_SHIFT)) & I3C_SDMACTRL_DMATB_MASK)
|
|
|
|
#define I3C_SDMACTRL_DMAWIDTH_MASK (0x30U)
|
|
#define I3C_SDMACTRL_DMAWIDTH_SHIFT (4U)
|
|
/*! DMAWIDTH - Width of DMA Operations
|
|
* 0b00, 0b01..Byte
|
|
* 0b10..Half word (16 bits)
|
|
* 0b11..
|
|
*/
|
|
#define I3C_SDMACTRL_DMAWIDTH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAWIDTH_SHIFT)) & I3C_SDMACTRL_DMAWIDTH_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SDATACTRL - Target Data Control */
|
|
/*! @{ */
|
|
|
|
#define I3C_SDATACTRL_FLUSHTB_MASK (0x1U)
|
|
#define I3C_SDATACTRL_FLUSHTB_SHIFT (0U)
|
|
/*! FLUSHTB - Flush the To-bus Buffer or FIFO */
|
|
#define I3C_SDATACTRL_FLUSHTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHTB_SHIFT)) & I3C_SDATACTRL_FLUSHTB_MASK)
|
|
|
|
#define I3C_SDATACTRL_FLUSHFB_MASK (0x2U)
|
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#define I3C_SDATACTRL_FLUSHFB_SHIFT (1U)
|
|
/*! FLUSHFB - Flush the From-bus Buffer or FIFO */
|
|
#define I3C_SDATACTRL_FLUSHFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHFB_SHIFT)) & I3C_SDATACTRL_FLUSHFB_MASK)
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#define I3C_SDATACTRL_UNLOCK_MASK (0x8U)
|
|
#define I3C_SDATACTRL_UNLOCK_SHIFT (3U)
|
|
/*! UNLOCK - Unlock
|
|
* 0b0..RXTRIG and TXTRIG fields cannot be changed on a write.
|
|
* 0b1..RXTRIG and TXTRIG fields can be changed on a write.
|
|
*/
|
|
#define I3C_SDATACTRL_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_UNLOCK_SHIFT)) & I3C_SDATACTRL_UNLOCK_MASK)
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|
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#define I3C_SDATACTRL_TXTRIG_MASK (0x30U)
|
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#define I3C_SDATACTRL_TXTRIG_SHIFT (4U)
|
|
/*! TXTRIG - Transmit Trigger Level
|
|
* 0b00..Trigger when empty
|
|
* 0b01..Trigger when 1/4 full or less
|
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* 0b10..Trigger when 1/2 full or less
|
|
* 0b11..Default. Trigger when 1 less than full or less
|
|
*/
|
|
#define I3C_SDATACTRL_TXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXTRIG_SHIFT)) & I3C_SDATACTRL_TXTRIG_MASK)
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#define I3C_SDATACTRL_RXTRIG_MASK (0xC0U)
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#define I3C_SDATACTRL_RXTRIG_SHIFT (6U)
|
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/*! RXTRIG - Receive Trigger Level
|
|
* 0b00..Trigger when not empty
|
|
* 0b01..Trigger when 1/4 or more full
|
|
* 0b10..Trigger when 1/2 or more full
|
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* 0b11..Trigger when 3/4 or more full
|
|
*/
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|
#define I3C_SDATACTRL_RXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXTRIG_SHIFT)) & I3C_SDATACTRL_RXTRIG_MASK)
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#define I3C_SDATACTRL_TXCOUNT_MASK (0x1F0000U)
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#define I3C_SDATACTRL_TXCOUNT_SHIFT (16U)
|
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/*! TXCOUNT - Count of Bytes in Transmit */
|
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#define I3C_SDATACTRL_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXCOUNT_SHIFT)) & I3C_SDATACTRL_TXCOUNT_MASK)
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#define I3C_SDATACTRL_RXCOUNT_MASK (0x1F000000U)
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#define I3C_SDATACTRL_RXCOUNT_SHIFT (24U)
|
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/*! RXCOUNT - Count of Bytes in Receive */
|
|
#define I3C_SDATACTRL_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXCOUNT_SHIFT)) & I3C_SDATACTRL_RXCOUNT_MASK)
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|
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#define I3C_SDATACTRL_TXFULL_MASK (0x40000000U)
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#define I3C_SDATACTRL_TXFULL_SHIFT (30U)
|
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/*! TXFULL - Transmit Is Full
|
|
* 0b1..Full
|
|
* 0b0..Not full
|
|
*/
|
|
#define I3C_SDATACTRL_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXFULL_SHIFT)) & I3C_SDATACTRL_TXFULL_MASK)
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|
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#define I3C_SDATACTRL_RXEMPTY_MASK (0x80000000U)
|
|
#define I3C_SDATACTRL_RXEMPTY_SHIFT (31U)
|
|
/*! RXEMPTY - Receive Is Empty
|
|
* 0b1..Empty
|
|
* 0b0..Not empty
|
|
*/
|
|
#define I3C_SDATACTRL_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXEMPTY_SHIFT)) & I3C_SDATACTRL_RXEMPTY_MASK)
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/*! @} */
|
|
|
|
/*! @name SWDATAB - Target Write Data Byte */
|
|
/*! @{ */
|
|
|
|
#define I3C_SWDATAB_DATA_MASK (0xFFU)
|
|
#define I3C_SWDATAB_DATA_SHIFT (0U)
|
|
/*! DATA - Data */
|
|
#define I3C_SWDATAB_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_DATA_SHIFT)) & I3C_SWDATAB_DATA_MASK)
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|
|
|
#define I3C_SWDATAB_END_MASK (0x100U)
|
|
#define I3C_SWDATAB_END_SHIFT (8U)
|
|
/*! END - End
|
|
* 0b1..End. This bit marks the last byte of the message.
|
|
* 0b0..Not the end. There are more bytes in the message.
|
|
*/
|
|
#define I3C_SWDATAB_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_SHIFT)) & I3C_SWDATAB_END_MASK)
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|
|
|
#define I3C_SWDATAB_END_ALSO_MASK (0x10000U)
|
|
#define I3C_SWDATAB_END_ALSO_SHIFT (16U)
|
|
/*! END_ALSO - End Also
|
|
* 0b1..End. This bit marks the last byte of the message.
|
|
* 0b0..Not the end. There are more bytes in the message.
|
|
*/
|
|
#define I3C_SWDATAB_END_ALSO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_ALSO_SHIFT)) & I3C_SWDATAB_END_ALSO_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SWDATABE - Target Write Data Byte End */
|
|
/*! @{ */
|
|
|
|
#define I3C_SWDATABE_DATA_MASK (0xFFU)
|
|
#define I3C_SWDATABE_DATA_SHIFT (0U)
|
|
/*! DATA - Data */
|
|
#define I3C_SWDATABE_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATABE_DATA_SHIFT)) & I3C_SWDATABE_DATA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SWDATAH - Target Write Data Half-word */
|
|
/*! @{ */
|
|
|
|
#define I3C_SWDATAH_DATA0_MASK (0xFFU)
|
|
#define I3C_SWDATAH_DATA0_SHIFT (0U)
|
|
/*! DATA0 - Data 0 */
|
|
#define I3C_SWDATAH_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA0_SHIFT)) & I3C_SWDATAH_DATA0_MASK)
|
|
|
|
#define I3C_SWDATAH_DATA1_MASK (0xFF00U)
|
|
#define I3C_SWDATAH_DATA1_SHIFT (8U)
|
|
/*! DATA1 - Data 1 */
|
|
#define I3C_SWDATAH_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA1_SHIFT)) & I3C_SWDATAH_DATA1_MASK)
|
|
|
|
#define I3C_SWDATAH_END_MASK (0x10000U)
|
|
#define I3C_SWDATAH_END_SHIFT (16U)
|
|
/*! END - End of message
|
|
* 0b1..End. This bit marks the last byte of the message.
|
|
* 0b0..Not the end. There are more bytes in the message.
|
|
*/
|
|
#define I3C_SWDATAH_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_END_SHIFT)) & I3C_SWDATAH_END_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SWDATAHE - Target Write Data Half-word End */
|
|
/*! @{ */
|
|
|
|
#define I3C_SWDATAHE_DATA0_MASK (0xFFU)
|
|
#define I3C_SWDATAHE_DATA0_SHIFT (0U)
|
|
/*! DATA0 - Data 0 */
|
|
#define I3C_SWDATAHE_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA0_SHIFT)) & I3C_SWDATAHE_DATA0_MASK)
|
|
|
|
#define I3C_SWDATAHE_DATA1_MASK (0xFF00U)
|
|
#define I3C_SWDATAHE_DATA1_SHIFT (8U)
|
|
/*! DATA1 - Data 1 */
|
|
#define I3C_SWDATAHE_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA1_SHIFT)) & I3C_SWDATAHE_DATA1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SRDATAB - Target Read Data Byte */
|
|
/*! @{ */
|
|
|
|
#define I3C_SRDATAB_DATA0_MASK (0xFFU)
|
|
#define I3C_SRDATAB_DATA0_SHIFT (0U)
|
|
/*! DATA0 - Data 0 */
|
|
#define I3C_SRDATAB_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAB_DATA0_SHIFT)) & I3C_SRDATAB_DATA0_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SRDATAH - Target Read Data Halfword */
|
|
/*! @{ */
|
|
|
|
#define I3C_SRDATAH_LSB_MASK (0xFFU)
|
|
#define I3C_SRDATAH_LSB_SHIFT (0U)
|
|
/*! LSB - The first byte read from the target */
|
|
#define I3C_SRDATAH_LSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_LSB_SHIFT)) & I3C_SRDATAH_LSB_MASK)
|
|
|
|
#define I3C_SRDATAH_MSB_MASK (0xFF00U)
|
|
#define I3C_SRDATAH_MSB_SHIFT (8U)
|
|
/*! MSB - The second byte read from the target */
|
|
#define I3C_SRDATAH_MSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_MSB_SHIFT)) & I3C_SRDATAH_MSB_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SWDATAB1 - Target Write Data Byte */
|
|
/*! @{ */
|
|
|
|
#define I3C_SWDATAB1_DATA_MASK (0xFFU)
|
|
#define I3C_SWDATAB1_DATA_SHIFT (0U)
|
|
/*! DATA - Data */
|
|
#define I3C_SWDATAB1_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB1_DATA_SHIFT)) & I3C_SWDATAB1_DATA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SWDATAH1 - Target Write Data Halfword */
|
|
/*! @{ */
|
|
|
|
#define I3C_SWDATAH1_DATA_MASK (0xFFFFU)
|
|
#define I3C_SWDATAH1_DATA_SHIFT (0U)
|
|
/*! DATA - Data */
|
|
#define I3C_SWDATAH1_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH1_DATA_SHIFT)) & I3C_SWDATAH1_DATA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SCAPABILITIES2 - Target Capabilities 2 */
|
|
/*! @{ */
|
|
|
|
#define I3C_SCAPABILITIES2_MAPCNT_MASK (0xFU)
|
|
#define I3C_SCAPABILITIES2_MAPCNT_SHIFT (0U)
|
|
/*! MAPCNT - Map Count */
|
|
#define I3C_SCAPABILITIES2_MAPCNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_MAPCNT_SHIFT)) & I3C_SCAPABILITIES2_MAPCNT_MASK)
|
|
|
|
#define I3C_SCAPABILITIES2_I2C10B_MASK (0x10U)
|
|
#define I3C_SCAPABILITIES2_I2C10B_SHIFT (4U)
|
|
/*! I2C10B - I2C 10-bit Address
|
|
* 0b0..Does not support 10-bit I2C address
|
|
* 0b1..Supports 10-bit I2C address
|
|
*/
|
|
#define I3C_SCAPABILITIES2_I2C10B(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2C10B_SHIFT)) & I3C_SCAPABILITIES2_I2C10B_MASK)
|
|
|
|
#define I3C_SCAPABILITIES2_I2CRST_MASK (0x20U)
|
|
#define I3C_SCAPABILITIES2_I2CRST_SHIFT (5U)
|
|
/*! I2CRST - I2C Software Reset
|
|
* 0b0..Does not support I2C software reset
|
|
* 0b1..Supports I2C software reset
|
|
*/
|
|
#define I3C_SCAPABILITIES2_I2CRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2CRST_SHIFT)) & I3C_SCAPABILITIES2_I2CRST_MASK)
|
|
|
|
#define I3C_SCAPABILITIES2_I2CDEVID_MASK (0x40U)
|
|
#define I3C_SCAPABILITIES2_I2CDEVID_SHIFT (6U)
|
|
/*! I2CDEVID - I2C Device ID
|
|
* 0b0..Does not support I2C device ID
|
|
* 0b1..Supports I2C device ID
|
|
*/
|
|
#define I3C_SCAPABILITIES2_I2CDEVID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2CDEVID_SHIFT)) & I3C_SCAPABILITIES2_I2CDEVID_MASK)
|
|
|
|
#define I3C_SCAPABILITIES2_IBIEXT_MASK (0x100U)
|
|
#define I3C_SCAPABILITIES2_IBIEXT_SHIFT (8U)
|
|
/*! IBIEXT - In-Band Interrupt EXTDATA
|
|
* 0b0..Does not support IBIEXT
|
|
* 0b1..Supports IBIEXT
|
|
*/
|
|
#define I3C_SCAPABILITIES2_IBIEXT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_IBIEXT_SHIFT)) & I3C_SCAPABILITIES2_IBIEXT_MASK)
|
|
|
|
#define I3C_SCAPABILITIES2_IBIXREG_MASK (0x200U)
|
|
#define I3C_SCAPABILITIES2_IBIXREG_SHIFT (9U)
|
|
/*! IBIXREG - In-Band Interrupt Extended Register
|
|
* 0b0..Does not support extended registers for IBIs
|
|
* 0b1..Supports extended registers for IBIs
|
|
*/
|
|
#define I3C_SCAPABILITIES2_IBIXREG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_IBIXREG_SHIFT)) & I3C_SCAPABILITIES2_IBIXREG_MASK)
|
|
|
|
#define I3C_SCAPABILITIES2_SLVRST_MASK (0x20000U)
|
|
#define I3C_SCAPABILITIES2_SLVRST_SHIFT (17U)
|
|
/*! SLVRST - Target Reset
|
|
* 0b0..Does not support Target Reset
|
|
* 0b1..Supports Target Reset
|
|
*/
|
|
#define I3C_SCAPABILITIES2_SLVRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SLVRST_SHIFT)) & I3C_SCAPABILITIES2_SLVRST_MASK)
|
|
|
|
#define I3C_SCAPABILITIES2_GROUP_MASK (0xC0000U)
|
|
#define I3C_SCAPABILITIES2_GROUP_SHIFT (18U)
|
|
/*! GROUP - Group
|
|
* 0b00..Does not supports v1.1 Group addressing
|
|
* 0b01..Supports one group
|
|
* 0b10..Supports two groups
|
|
* 0b11..Supports three groups
|
|
*/
|
|
#define I3C_SCAPABILITIES2_GROUP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_GROUP_SHIFT)) & I3C_SCAPABILITIES2_GROUP_MASK)
|
|
|
|
#define I3C_SCAPABILITIES2_AASA_MASK (0x200000U)
|
|
#define I3C_SCAPABILITIES2_AASA_SHIFT (21U)
|
|
/*! AASA - Supports SETAASA
|
|
* 0b1..Supports SETAASA
|
|
* 0b0..Does not support SETAASA
|
|
*/
|
|
#define I3C_SCAPABILITIES2_AASA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_AASA_SHIFT)) & I3C_SCAPABILITIES2_AASA_MASK)
|
|
|
|
#define I3C_SCAPABILITIES2_SSTSUB_MASK (0x400000U)
|
|
#define I3C_SCAPABILITIES2_SSTSUB_SHIFT (22U)
|
|
/*! SSTSUB - Target-Target(s)-Tunnel Subscriber Capable
|
|
* 0b1..Subscriber capable
|
|
* 0b0..Not subscriber capable
|
|
*/
|
|
#define I3C_SCAPABILITIES2_SSTSUB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SSTSUB_SHIFT)) & I3C_SCAPABILITIES2_SSTSUB_MASK)
|
|
|
|
#define I3C_SCAPABILITIES2_SSTWR_MASK (0x800000U)
|
|
#define I3C_SCAPABILITIES2_SSTWR_SHIFT (23U)
|
|
/*! SSTWR - Target-Target(s)-Tunnel Write Capable
|
|
* 0b1..Write capable
|
|
* 0b0..Not write capable
|
|
*/
|
|
#define I3C_SCAPABILITIES2_SSTWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SSTWR_SHIFT)) & I3C_SCAPABILITIES2_SSTWR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SCAPABILITIES - Target Capabilities */
|
|
/*! @{ */
|
|
|
|
#define I3C_SCAPABILITIES_IDENA_MASK (0x3U)
|
|
#define I3C_SCAPABILITIES_IDENA_SHIFT (0U)
|
|
/*! IDENA - ID 48b Handler
|
|
* 0b00..Application
|
|
* 0b01..Hardware
|
|
* 0b10..Hardware, but the I3C module instance handles ID 48b
|
|
* 0b11..A part number register (PARTNO)
|
|
*/
|
|
#define I3C_SCAPABILITIES_IDENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDENA_SHIFT)) & I3C_SCAPABILITIES_IDENA_MASK)
|
|
|
|
#define I3C_SCAPABILITIES_IDREG_MASK (0x3CU)
|
|
#define I3C_SCAPABILITIES_IDREG_SHIFT (2U)
|
|
/*! IDREG - ID Register
|
|
* 0b0000..All ID register features below are disabled.
|
|
* 0bxxx1..ID Instance is a register, and is used if there is no PARTNO register.
|
|
* 0bxx1x..An ID Random field is available.
|
|
* 0bx1xx..A Device Characteristic Register (DCR) is available.
|
|
* 0b1xxx..A Bus Characteristics Register (BCR) is available.
|
|
*/
|
|
#define I3C_SCAPABILITIES_IDREG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDREG_SHIFT)) & I3C_SCAPABILITIES_IDREG_MASK)
|
|
|
|
#define I3C_SCAPABILITIES_HDRSUPP_MASK (0xC0U)
|
|
#define I3C_SCAPABILITIES_HDRSUPP_SHIFT (6U)
|
|
/*! HDRSUPP - High Data Rate Support
|
|
* 0b00..No HDR modes supported
|
|
* 0b01..Double Data Rate mode supported
|
|
* *..
|
|
*/
|
|
#define I3C_SCAPABILITIES_HDRSUPP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_HDRSUPP_SHIFT)) & I3C_SCAPABILITIES_HDRSUPP_MASK)
|
|
|
|
#define I3C_SCAPABILITIES_MASTER_MASK (0x200U)
|
|
#define I3C_SCAPABILITIES_MASTER_SHIFT (9U)
|
|
/*! MASTER - Controller
|
|
* 0b0..Not supported
|
|
* 0b1..Supported
|
|
*/
|
|
#define I3C_SCAPABILITIES_MASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_MASTER_SHIFT)) & I3C_SCAPABILITIES_MASTER_MASK)
|
|
|
|
#define I3C_SCAPABILITIES_SADDR_MASK (0xC00U)
|
|
#define I3C_SCAPABILITIES_SADDR_SHIFT (10U)
|
|
/*! SADDR - Static Address
|
|
* 0b00..No static address
|
|
* 0b01..Static address is fixed in hardware
|
|
* 0b10..Hardware controls the static address dynamically (for example, from the pin strap)
|
|
* 0b11..SCONFIG register supplies the static address
|
|
*/
|
|
#define I3C_SCAPABILITIES_SADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_SADDR_SHIFT)) & I3C_SCAPABILITIES_SADDR_MASK)
|
|
|
|
#define I3C_SCAPABILITIES_CCCHANDLE_MASK (0xF000U)
|
|
#define I3C_SCAPABILITIES_CCCHANDLE_SHIFT (12U)
|
|
/*! CCCHANDLE - Common Command Codes Handling
|
|
* 0b0000..All handling features below are disabled.
|
|
* 0bxxx1..The block (I3C module) manages events, activities, status, HDR, and if enabled for it, ID and static-address-related items.
|
|
* 0bxx1x..The block manages maximum read and write lengths, and max data speed.
|
|
* 0bx1xx..GETSTATUS CCC returns SCTRL[PENDINT] and SCTRL[ACTSTATE] values.
|
|
* 0b1xxx..GETSTATUS CCC returns SCTRL[VENDINFO] value.
|
|
*/
|
|
#define I3C_SCAPABILITIES_CCCHANDLE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_CCCHANDLE_SHIFT)) & I3C_SCAPABILITIES_CCCHANDLE_MASK)
|
|
|
|
#define I3C_SCAPABILITIES_IBI_MR_HJ_MASK (0x1F0000U)
|
|
#define I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT (16U)
|
|
/*! IBI_MR_HJ - In-Band Interrupts, Controller Requests, Hot-Join Events
|
|
* 0b00000..Application cannot generate IBI, CR, or HJ.
|
|
* 0bxxxx1..Application can generate an IBI.
|
|
* 0bxxx1x..When bit 0 = 1, the IBI has data from the SCTRL register.
|
|
* 0bxx1xx..Application can generate a Controller Request for a secondary controller.
|
|
* 0bx1xxx..Application can generate a Hot-Join event.
|
|
* 0b1xxxx..Application can use SCONFIG[BAMATCH] for bus-available timing.
|
|
*/
|
|
#define I3C_SCAPABILITIES_IBI_MR_HJ(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT)) & I3C_SCAPABILITIES_IBI_MR_HJ_MASK)
|
|
|
|
#define I3C_SCAPABILITIES_TIMECTRL_MASK (0x200000U)
|
|
#define I3C_SCAPABILITIES_TIMECTRL_SHIFT (21U)
|
|
/*! TIMECTRL - Time Control
|
|
* 0b0..No time control enabled
|
|
* 0b1..At least one time-control type supported
|
|
*/
|
|
#define I3C_SCAPABILITIES_TIMECTRL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_TIMECTRL_SHIFT)) & I3C_SCAPABILITIES_TIMECTRL_MASK)
|
|
|
|
#define I3C_SCAPABILITIES_EXTFIFO_MASK (0x3800000U)
|
|
#define I3C_SCAPABILITIES_EXTFIFO_SHIFT (23U)
|
|
/*! EXTFIFO - External FIFO
|
|
* 0b000..No external FIFO is available
|
|
* 0b001..Standard available or free external FIFO
|
|
* 0b010..Request track external FIFO
|
|
* *..
|
|
*/
|
|
#define I3C_SCAPABILITIES_EXTFIFO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_EXTFIFO_SHIFT)) & I3C_SCAPABILITIES_EXTFIFO_MASK)
|
|
|
|
#define I3C_SCAPABILITIES_FIFOTX_MASK (0xC000000U)
|
|
#define I3C_SCAPABILITIES_FIFOTX_SHIFT (26U)
|
|
/*! FIFOTX - FIFO Transmit
|
|
* 0b00..Two
|
|
* 0b01..Four
|
|
* 0b10..Eight
|
|
* 0b11..16 or larger
|
|
*/
|
|
#define I3C_SCAPABILITIES_FIFOTX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFOTX_SHIFT)) & I3C_SCAPABILITIES_FIFOTX_MASK)
|
|
|
|
#define I3C_SCAPABILITIES_FIFORX_MASK (0x30000000U)
|
|
#define I3C_SCAPABILITIES_FIFORX_SHIFT (28U)
|
|
/*! FIFORX - FIFO Receive
|
|
* 0b00..Two or three
|
|
* 0b01..Four
|
|
* 0b10..Eight
|
|
* 0b11..16 or larger
|
|
*/
|
|
#define I3C_SCAPABILITIES_FIFORX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFORX_SHIFT)) & I3C_SCAPABILITIES_FIFORX_MASK)
|
|
|
|
#define I3C_SCAPABILITIES_INT_MASK (0x40000000U)
|
|
#define I3C_SCAPABILITIES_INT_SHIFT (30U)
|
|
/*! INT - Interrupts
|
|
* 0b1..Supported
|
|
* 0b0..Not supported
|
|
*/
|
|
#define I3C_SCAPABILITIES_INT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_INT_SHIFT)) & I3C_SCAPABILITIES_INT_MASK)
|
|
|
|
#define I3C_SCAPABILITIES_DMA_MASK (0x80000000U)
|
|
#define I3C_SCAPABILITIES_DMA_SHIFT (31U)
|
|
/*! DMA - Direct Memory Access
|
|
* 0b1..Supported
|
|
* 0b0..Not supported
|
|
*/
|
|
#define I3C_SCAPABILITIES_DMA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_DMA_SHIFT)) & I3C_SCAPABILITIES_DMA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SDYNADDR - Target Dynamic Address */
|
|
/*! @{ */
|
|
|
|
#define I3C_SDYNADDR_DAVALID_MASK (0x1U)
|
|
#define I3C_SDYNADDR_DAVALID_SHIFT (0U)
|
|
/*! DAVALID - Dynamic Address Valid
|
|
* 0b0..DANOTASSIGNED: a Dynamic Address is not assigned
|
|
* 0b1..DAASSIGNED: a Dynamic Address is assigned
|
|
*/
|
|
#define I3C_SDYNADDR_DAVALID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_DAVALID_SHIFT)) & I3C_SDYNADDR_DAVALID_MASK)
|
|
|
|
#define I3C_SDYNADDR_DADDR_MASK (0xFEU)
|
|
#define I3C_SDYNADDR_DADDR_SHIFT (1U)
|
|
/*! DADDR - Dynamic Address */
|
|
#define I3C_SDYNADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_DADDR_SHIFT)) & I3C_SDYNADDR_DADDR_MASK)
|
|
|
|
#define I3C_SDYNADDR_MAPSA_MASK (0x1000U)
|
|
#define I3C_SDYNADDR_MAPSA_SHIFT (12U)
|
|
/*! MAPSA - Map a Static Address */
|
|
#define I3C_SDYNADDR_MAPSA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_MAPSA_SHIFT)) & I3C_SDYNADDR_MAPSA_MASK)
|
|
|
|
#define I3C_SDYNADDR_SA10B_MASK (0xE000U)
|
|
#define I3C_SDYNADDR_SA10B_SHIFT (13U)
|
|
/*! SA10B - 10bit Static Address */
|
|
#define I3C_SDYNADDR_SA10B(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_SA10B_SHIFT)) & I3C_SDYNADDR_SA10B_MASK)
|
|
|
|
#define I3C_SDYNADDR_KEY_MASK (0xFFFF0000U)
|
|
#define I3C_SDYNADDR_KEY_SHIFT (16U)
|
|
/*! KEY - Key */
|
|
#define I3C_SDYNADDR_KEY(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_KEY_SHIFT)) & I3C_SDYNADDR_KEY_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SMAXLIMITS - Target Maximum Limits */
|
|
/*! @{ */
|
|
|
|
#define I3C_SMAXLIMITS_MAXRD_MASK (0xFFFU)
|
|
#define I3C_SMAXLIMITS_MAXRD_SHIFT (0U)
|
|
/*! MAXRD - Maximum Read Length */
|
|
#define I3C_SMAXLIMITS_MAXRD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXRD_SHIFT)) & I3C_SMAXLIMITS_MAXRD_MASK)
|
|
|
|
#define I3C_SMAXLIMITS_MAXWR_MASK (0xFFF0000U)
|
|
#define I3C_SMAXLIMITS_MAXWR_SHIFT (16U)
|
|
/*! MAXWR - Maximum Write Length */
|
|
#define I3C_SMAXLIMITS_MAXWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXWR_SHIFT)) & I3C_SMAXLIMITS_MAXWR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SIDPARTNO - Target ID Part Number */
|
|
/*! @{ */
|
|
|
|
#define I3C_SIDPARTNO_PARTNO_MASK (0xFFFFFFFFU)
|
|
#define I3C_SIDPARTNO_PARTNO_SHIFT (0U)
|
|
/*! PARTNO - Part number */
|
|
#define I3C_SIDPARTNO_PARTNO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDPARTNO_PARTNO_SHIFT)) & I3C_SIDPARTNO_PARTNO_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SIDEXT - Target ID Extension */
|
|
/*! @{ */
|
|
|
|
#define I3C_SIDEXT_DCR_MASK (0xFF00U)
|
|
#define I3C_SIDEXT_DCR_SHIFT (8U)
|
|
/*! DCR - Device Characteristic Register */
|
|
#define I3C_SIDEXT_DCR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_DCR_SHIFT)) & I3C_SIDEXT_DCR_MASK)
|
|
|
|
#define I3C_SIDEXT_BCR_MASK (0xFF0000U)
|
|
#define I3C_SIDEXT_BCR_SHIFT (16U)
|
|
/*! BCR - Bus Characteristics Register */
|
|
#define I3C_SIDEXT_BCR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_BCR_SHIFT)) & I3C_SIDEXT_BCR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SVENDORID - Target Vendor ID */
|
|
/*! @{ */
|
|
|
|
#define I3C_SVENDORID_VID_MASK (0x7FFFU)
|
|
#define I3C_SVENDORID_VID_SHIFT (0U)
|
|
/*! VID - Vendor ID */
|
|
#define I3C_SVENDORID_VID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SVENDORID_VID_SHIFT)) & I3C_SVENDORID_VID_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name STCCLOCK - Target Time Control Clock */
|
|
/*! @{ */
|
|
|
|
#define I3C_STCCLOCK_ACCURACY_MASK (0xFFU)
|
|
#define I3C_STCCLOCK_ACCURACY_SHIFT (0U)
|
|
/*! ACCURACY - Clock Accuracy */
|
|
#define I3C_STCCLOCK_ACCURACY(x) (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_ACCURACY_SHIFT)) & I3C_STCCLOCK_ACCURACY_MASK)
|
|
|
|
#define I3C_STCCLOCK_FREQ_MASK (0xFF00U)
|
|
#define I3C_STCCLOCK_FREQ_SHIFT (8U)
|
|
/*! FREQ - Clock Frequency */
|
|
#define I3C_STCCLOCK_FREQ(x) (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_FREQ_SHIFT)) & I3C_STCCLOCK_FREQ_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SMSGMAPADDR - Target Message Map Address */
|
|
/*! @{ */
|
|
|
|
#define I3C_SMSGMAPADDR_MAPLAST_MASK (0xFU)
|
|
#define I3C_SMSGMAPADDR_MAPLAST_SHIFT (0U)
|
|
/*! MAPLAST - Matched Address Index */
|
|
#define I3C_SMSGMAPADDR_MAPLAST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLAST_SHIFT)) & I3C_SMSGMAPADDR_MAPLAST_MASK)
|
|
|
|
#define I3C_SMSGMAPADDR_LASTSTATIC_MASK (0x10U)
|
|
#define I3C_SMSGMAPADDR_LASTSTATIC_SHIFT (4U)
|
|
/*! LASTSTATIC - Last Static Address Matched
|
|
* 0b1..I2C static address
|
|
* 0b0..I3C dynamic address
|
|
*/
|
|
#define I3C_SMSGMAPADDR_LASTSTATIC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_LASTSTATIC_SHIFT)) & I3C_SMSGMAPADDR_LASTSTATIC_MASK)
|
|
|
|
#define I3C_SMSGMAPADDR_MAPLASTM1_MASK (0xF00U)
|
|
#define I3C_SMSGMAPADDR_MAPLASTM1_SHIFT (8U)
|
|
/*! MAPLASTM1 - Matched Previous Address Index 1 */
|
|
#define I3C_SMSGMAPADDR_MAPLASTM1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM1_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM1_MASK)
|
|
|
|
#define I3C_SMSGMAPADDR_MAPLASTM2_MASK (0xF0000U)
|
|
#define I3C_SMSGMAPADDR_MAPLASTM2_SHIFT (16U)
|
|
/*! MAPLASTM2 - Matched Previous Index 2 */
|
|
#define I3C_SMSGMAPADDR_MAPLASTM2(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM2_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM2_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MCONFIG_EXT - Controller Extended Configuration */
|
|
/*! @{ */
|
|
|
|
#define I3C_MCONFIG_EXT_I3C_CAS_DEL_MASK (0x30000U)
|
|
#define I3C_MCONFIG_EXT_I3C_CAS_DEL_SHIFT (16U)
|
|
/*! I3C_CAS_DEL - I3C CAS Delay after START
|
|
* 0b00..No Delay
|
|
* 0b01..Increases SCL clock period by 1/2.
|
|
* 0b10..Increases SCL clock period by 1.
|
|
* 0b11..Increases SCL clock period by 1 1/2.
|
|
*/
|
|
#define I3C_MCONFIG_EXT_I3C_CAS_DEL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_EXT_I3C_CAS_DEL_SHIFT)) & I3C_MCONFIG_EXT_I3C_CAS_DEL_MASK)
|
|
|
|
#define I3C_MCONFIG_EXT_I3C_CASR_DEL_MASK (0xC0000U)
|
|
#define I3C_MCONFIG_EXT_I3C_CASR_DEL_SHIFT (18U)
|
|
/*! I3C_CASR_DEL - I3C CAS Delay After Repeated START
|
|
* 0b00..No Delay
|
|
* 0b01..Increases SCL clock period by 1/2.
|
|
* 0b10..Increases SCL clock period by 1.
|
|
* 0b11..Increases SCL clock period by 1 1/2.
|
|
*/
|
|
#define I3C_MCONFIG_EXT_I3C_CASR_DEL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_EXT_I3C_CASR_DEL_SHIFT)) & I3C_MCONFIG_EXT_I3C_CASR_DEL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MCTRL - Controller Control */
|
|
/*! @{ */
|
|
|
|
#define I3C_MCTRL_REQUEST_MASK (0x7U)
|
|
#define I3C_MCTRL_REQUEST_SHIFT (0U)
|
|
/*! REQUEST - Request
|
|
* 0b000..NONE
|
|
* 0b001..EMITSTARTADDR
|
|
* 0b010..EMITSTOP
|
|
* 0b011..IBIACKNACK
|
|
* 0b100..PROCESSDAA
|
|
* 0b101..
|
|
* 0b110..Force Exit and Target Reset
|
|
* 0b111..AUTOIBI
|
|
*/
|
|
#define I3C_MCTRL_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_REQUEST_SHIFT)) & I3C_MCTRL_REQUEST_MASK)
|
|
|
|
#define I3C_MCTRL_TYPE_MASK (0x30U)
|
|
#define I3C_MCTRL_TYPE_SHIFT (4U)
|
|
/*! TYPE - Bus Type with EmitStartAddr
|
|
* 0b00..I3C
|
|
* 0b01..I2C
|
|
* 0b10..DDR
|
|
* 0b11..
|
|
*/
|
|
#define I3C_MCTRL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_TYPE_SHIFT)) & I3C_MCTRL_TYPE_MASK)
|
|
|
|
#define I3C_MCTRL_IBIRESP_MASK (0xC0U)
|
|
#define I3C_MCTRL_IBIRESP_SHIFT (6U)
|
|
/*! IBIRESP - In-Band Interrupt Response
|
|
* 0b00..ACK (acknowledge)
|
|
* 0b01..NACK (reject)
|
|
* 0b10..Acknowledge with mandatory byte
|
|
* 0b11..Manual
|
|
*/
|
|
#define I3C_MCTRL_IBIRESP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_IBIRESP_SHIFT)) & I3C_MCTRL_IBIRESP_MASK)
|
|
|
|
#define I3C_MCTRL_DIR_MASK (0x100U)
|
|
#define I3C_MCTRL_DIR_SHIFT (8U)
|
|
/*! DIR - Direction
|
|
* 0b0..Write
|
|
* 0b1..Read
|
|
*/
|
|
#define I3C_MCTRL_DIR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_DIR_SHIFT)) & I3C_MCTRL_DIR_MASK)
|
|
|
|
#define I3C_MCTRL_ADDR_MASK (0xFE00U)
|
|
#define I3C_MCTRL_ADDR_SHIFT (9U)
|
|
/*! ADDR - Address */
|
|
#define I3C_MCTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_ADDR_SHIFT)) & I3C_MCTRL_ADDR_MASK)
|
|
|
|
#define I3C_MCTRL_RDTERM_MASK (0xFF0000U)
|
|
#define I3C_MCTRL_RDTERM_SHIFT (16U)
|
|
/*! RDTERM - Read Terminate Counter */
|
|
#define I3C_MCTRL_RDTERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_RDTERM_SHIFT)) & I3C_MCTRL_RDTERM_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MSTATUS - Controller Status */
|
|
/*! @{ */
|
|
|
|
#define I3C_MSTATUS_STATE_MASK (0x7U)
|
|
#define I3C_MSTATUS_STATE_SHIFT (0U)
|
|
/*! STATE - State Of The Controller
|
|
* 0b000..IDLE
|
|
* 0b001..SLVREQ
|
|
* 0b010..MSGSDR
|
|
* 0b011..NORMACT
|
|
* 0b100..MSGDDR
|
|
* 0b101..DAA
|
|
* 0b110..IBIACK
|
|
* 0b111..IBIRCV
|
|
*/
|
|
#define I3C_MSTATUS_STATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_STATE_SHIFT)) & I3C_MSTATUS_STATE_MASK)
|
|
|
|
#define I3C_MSTATUS_BETWEEN_MASK (0x10U)
|
|
#define I3C_MSTATUS_BETWEEN_SHIFT (4U)
|
|
/*! BETWEEN - Between
|
|
* 0b0..Inactive
|
|
* 0b1..Active
|
|
*/
|
|
#define I3C_MSTATUS_BETWEEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_BETWEEN_SHIFT)) & I3C_MSTATUS_BETWEEN_MASK)
|
|
|
|
#define I3C_MSTATUS_NACKED_MASK (0x20U)
|
|
#define I3C_MSTATUS_NACKED_SHIFT (5U)
|
|
/*! NACKED - Not Acknowledged
|
|
* 0b1..NACKed (not acknowledged)
|
|
* 0b0..Not NACKed
|
|
*/
|
|
#define I3C_MSTATUS_NACKED(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NACKED_SHIFT)) & I3C_MSTATUS_NACKED_MASK)
|
|
|
|
#define I3C_MSTATUS_IBITYPE_MASK (0xC0U)
|
|
#define I3C_MSTATUS_IBITYPE_SHIFT (6U)
|
|
/*! IBITYPE - In-Band Interrupt (IBI) Type
|
|
* 0b00..NONE
|
|
* 0b01..In-Band Interrupt
|
|
* 0b10..Controller Request
|
|
* 0b11..Hot-Join
|
|
*/
|
|
#define I3C_MSTATUS_IBITYPE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBITYPE_SHIFT)) & I3C_MSTATUS_IBITYPE_MASK)
|
|
|
|
#define I3C_MSTATUS_SLVSTART_MASK (0x100U)
|
|
#define I3C_MSTATUS_SLVSTART_SHIFT (8U)
|
|
/*! SLVSTART - Target Start
|
|
* 0b1..Target requesting START
|
|
* 0b0..Target not requesting START
|
|
*/
|
|
#define I3C_MSTATUS_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_SLVSTART_SHIFT)) & I3C_MSTATUS_SLVSTART_MASK)
|
|
|
|
#define I3C_MSTATUS_MCTRLDONE_MASK (0x200U)
|
|
#define I3C_MSTATUS_MCTRLDONE_SHIFT (9U)
|
|
/*! MCTRLDONE - Controller Control Done
|
|
* 0b1..Done
|
|
* 0b0..Not done
|
|
*/
|
|
#define I3C_MSTATUS_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_MCTRLDONE_SHIFT)) & I3C_MSTATUS_MCTRLDONE_MASK)
|
|
|
|
#define I3C_MSTATUS_COMPLETE_MASK (0x400U)
|
|
#define I3C_MSTATUS_COMPLETE_SHIFT (10U)
|
|
/*! COMPLETE - Complete
|
|
* 0b1..Complete
|
|
* 0b0..Not complete
|
|
*/
|
|
#define I3C_MSTATUS_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_COMPLETE_SHIFT)) & I3C_MSTATUS_COMPLETE_MASK)
|
|
|
|
#define I3C_MSTATUS_RXPEND_MASK (0x800U)
|
|
#define I3C_MSTATUS_RXPEND_SHIFT (11U)
|
|
/*! RXPEND - RXPEND
|
|
* 0b1..Receive message pending
|
|
* 0b0..No receive message pending
|
|
*/
|
|
#define I3C_MSTATUS_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_RXPEND_SHIFT)) & I3C_MSTATUS_RXPEND_MASK)
|
|
|
|
#define I3C_MSTATUS_TXNOTFULL_MASK (0x1000U)
|
|
#define I3C_MSTATUS_TXNOTFULL_SHIFT (12U)
|
|
/*! TXNOTFULL - TX Buffer or FIFO Not Full
|
|
* 0b1..Receive buffer or FIFO not full
|
|
* 0b0..Receive buffer or FIFO full
|
|
*/
|
|
#define I3C_MSTATUS_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_TXNOTFULL_SHIFT)) & I3C_MSTATUS_TXNOTFULL_MASK)
|
|
|
|
#define I3C_MSTATUS_IBIWON_MASK (0x2000U)
|
|
#define I3C_MSTATUS_IBIWON_SHIFT (13U)
|
|
/*! IBIWON - In-Band Interrupt (IBI) Won
|
|
* 0b1..IBI arbitration won
|
|
* 0b0..No IBI arbitration won
|
|
*/
|
|
#define I3C_MSTATUS_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIWON_SHIFT)) & I3C_MSTATUS_IBIWON_MASK)
|
|
|
|
#define I3C_MSTATUS_ERRWARN_MASK (0x8000U)
|
|
#define I3C_MSTATUS_ERRWARN_SHIFT (15U)
|
|
/*! ERRWARN - Error Or Warning
|
|
* 0b1..Error or warning
|
|
* 0b0..No error or warning
|
|
*/
|
|
#define I3C_MSTATUS_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_ERRWARN_SHIFT)) & I3C_MSTATUS_ERRWARN_MASK)
|
|
|
|
#define I3C_MSTATUS_NOWMASTER_MASK (0x80000U)
|
|
#define I3C_MSTATUS_NOWMASTER_SHIFT (19U)
|
|
/*! NOWMASTER - Module Is Now Controller
|
|
* 0b1..Module has become controller
|
|
* 0b0..Module has not become controller
|
|
*/
|
|
#define I3C_MSTATUS_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NOWMASTER_SHIFT)) & I3C_MSTATUS_NOWMASTER_MASK)
|
|
|
|
#define I3C_MSTATUS_IBIADDR_MASK (0x7F000000U)
|
|
#define I3C_MSTATUS_IBIADDR_SHIFT (24U)
|
|
/*! IBIADDR - IBI Address */
|
|
#define I3C_MSTATUS_IBIADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIADDR_SHIFT)) & I3C_MSTATUS_IBIADDR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MIBIRULES - Controller In-band Interrupt Registry and Rules */
|
|
/*! @{ */
|
|
|
|
#define I3C_MIBIRULES_ADDR0_MASK (0x3FU)
|
|
#define I3C_MIBIRULES_ADDR0_SHIFT (0U)
|
|
/*! ADDR0 - ADDR0 */
|
|
#define I3C_MIBIRULES_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR0_SHIFT)) & I3C_MIBIRULES_ADDR0_MASK)
|
|
|
|
#define I3C_MIBIRULES_ADDR1_MASK (0xFC0U)
|
|
#define I3C_MIBIRULES_ADDR1_SHIFT (6U)
|
|
/*! ADDR1 - ADDR1 */
|
|
#define I3C_MIBIRULES_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR1_SHIFT)) & I3C_MIBIRULES_ADDR1_MASK)
|
|
|
|
#define I3C_MIBIRULES_ADDR2_MASK (0x3F000U)
|
|
#define I3C_MIBIRULES_ADDR2_SHIFT (12U)
|
|
/*! ADDR2 - ADDR2 */
|
|
#define I3C_MIBIRULES_ADDR2(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR2_SHIFT)) & I3C_MIBIRULES_ADDR2_MASK)
|
|
|
|
#define I3C_MIBIRULES_ADDR3_MASK (0xFC0000U)
|
|
#define I3C_MIBIRULES_ADDR3_SHIFT (18U)
|
|
/*! ADDR3 - ADDR3 */
|
|
#define I3C_MIBIRULES_ADDR3(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR3_SHIFT)) & I3C_MIBIRULES_ADDR3_MASK)
|
|
|
|
#define I3C_MIBIRULES_ADDR4_MASK (0x3F000000U)
|
|
#define I3C_MIBIRULES_ADDR4_SHIFT (24U)
|
|
/*! ADDR4 - ADDR4 */
|
|
#define I3C_MIBIRULES_ADDR4(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR4_SHIFT)) & I3C_MIBIRULES_ADDR4_MASK)
|
|
|
|
#define I3C_MIBIRULES_MSB0_MASK (0x40000000U)
|
|
#define I3C_MIBIRULES_MSB0_SHIFT (30U)
|
|
/*! MSB0 - Most Significant Address Bit Is 0
|
|
* 0b1..For all I3C dynamic addresses, MSB is 0.
|
|
* 0b0..MSB is not 0.
|
|
*/
|
|
#define I3C_MIBIRULES_MSB0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_MSB0_SHIFT)) & I3C_MIBIRULES_MSB0_MASK)
|
|
|
|
#define I3C_MIBIRULES_NOBYTE_MASK (0x80000000U)
|
|
#define I3C_MIBIRULES_NOBYTE_SHIFT (31U)
|
|
/*! NOBYTE - No IBI byte
|
|
* 0b1..Without mandatory IBI byte
|
|
* 0b0..With mandatory IBI byte
|
|
*/
|
|
#define I3C_MIBIRULES_NOBYTE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_NOBYTE_SHIFT)) & I3C_MIBIRULES_NOBYTE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MINTSET - Controller Interrupt Set */
|
|
/*! @{ */
|
|
|
|
#define I3C_MINTSET_SLVSTART_MASK (0x100U)
|
|
#define I3C_MINTSET_SLVSTART_SHIFT (8U)
|
|
/*! SLVSTART - Target Start Interrupt Enable
|
|
* 0b1..Enable
|
|
* 0b0..Disable
|
|
*/
|
|
#define I3C_MINTSET_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_SLVSTART_SHIFT)) & I3C_MINTSET_SLVSTART_MASK)
|
|
|
|
#define I3C_MINTSET_MCTRLDONE_MASK (0x200U)
|
|
#define I3C_MINTSET_MCTRLDONE_SHIFT (9U)
|
|
/*! MCTRLDONE - Controller Control Done Interrupt Enable
|
|
* 0b1..Enable
|
|
* 0b0..Disable
|
|
*/
|
|
#define I3C_MINTSET_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_MCTRLDONE_SHIFT)) & I3C_MINTSET_MCTRLDONE_MASK)
|
|
|
|
#define I3C_MINTSET_COMPLETE_MASK (0x400U)
|
|
#define I3C_MINTSET_COMPLETE_SHIFT (10U)
|
|
/*! COMPLETE - Completed Message Interrupt Enable
|
|
* 0b1..Enable
|
|
* 0b0..Disable
|
|
*/
|
|
#define I3C_MINTSET_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_COMPLETE_SHIFT)) & I3C_MINTSET_COMPLETE_MASK)
|
|
|
|
#define I3C_MINTSET_RXPEND_MASK (0x800U)
|
|
#define I3C_MINTSET_RXPEND_SHIFT (11U)
|
|
/*! RXPEND - Receive Pending Interrupt Enable */
|
|
#define I3C_MINTSET_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_RXPEND_SHIFT)) & I3C_MINTSET_RXPEND_MASK)
|
|
|
|
#define I3C_MINTSET_TXNOTFULL_MASK (0x1000U)
|
|
#define I3C_MINTSET_TXNOTFULL_SHIFT (12U)
|
|
/*! TXNOTFULL - Transmit Buffer/FIFO is not full interrupt enable
|
|
* 0b1..Enable
|
|
* 0b0..Disable
|
|
*/
|
|
#define I3C_MINTSET_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_TXNOTFULL_SHIFT)) & I3C_MINTSET_TXNOTFULL_MASK)
|
|
|
|
#define I3C_MINTSET_IBIWON_MASK (0x2000U)
|
|
#define I3C_MINTSET_IBIWON_SHIFT (13U)
|
|
/*! IBIWON - In-Band Interrupt (IBI) Won Interrupt Enable
|
|
* 0b1..Enable
|
|
* 0b0..Disable
|
|
*/
|
|
#define I3C_MINTSET_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_IBIWON_SHIFT)) & I3C_MINTSET_IBIWON_MASK)
|
|
|
|
#define I3C_MINTSET_ERRWARN_MASK (0x8000U)
|
|
#define I3C_MINTSET_ERRWARN_SHIFT (15U)
|
|
/*! ERRWARN - Error or Warning (ERRWARN) Interrupt Enable
|
|
* 0b1..Enable
|
|
* 0b0..Disable
|
|
*/
|
|
#define I3C_MINTSET_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_ERRWARN_SHIFT)) & I3C_MINTSET_ERRWARN_MASK)
|
|
|
|
#define I3C_MINTSET_NOWMASTER_MASK (0x80000U)
|
|
#define I3C_MINTSET_NOWMASTER_SHIFT (19U)
|
|
/*! NOWMASTER - Now Controller (now this I3C module is a controller) Interrupt Enable
|
|
* 0b1..Enable
|
|
* 0b0..Disable
|
|
*/
|
|
#define I3C_MINTSET_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_NOWMASTER_SHIFT)) & I3C_MINTSET_NOWMASTER_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MINTCLR - Controller Interrupt Clear */
|
|
/*! @{ */
|
|
|
|
#define I3C_MINTCLR_SLVSTART_MASK (0x100U)
|
|
#define I3C_MINTCLR_SLVSTART_SHIFT (8U)
|
|
/*! SLVSTART - SLVSTART Interrupt Enable Clear
|
|
* 0b1..Corresponding interrupt enable becomes 0
|
|
* 0b0..No effect
|
|
*/
|
|
#define I3C_MINTCLR_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_SLVSTART_SHIFT)) & I3C_MINTCLR_SLVSTART_MASK)
|
|
|
|
#define I3C_MINTCLR_MCTRLDONE_MASK (0x200U)
|
|
#define I3C_MINTCLR_MCTRLDONE_SHIFT (9U)
|
|
/*! MCTRLDONE - MCTRLDONE Interrupt Enable Clear
|
|
* 0b1..Corresponding interrupt enable becomes 0
|
|
* 0b0..No effect
|
|
*/
|
|
#define I3C_MINTCLR_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_MCTRLDONE_SHIFT)) & I3C_MINTCLR_MCTRLDONE_MASK)
|
|
|
|
#define I3C_MINTCLR_COMPLETE_MASK (0x400U)
|
|
#define I3C_MINTCLR_COMPLETE_SHIFT (10U)
|
|
/*! COMPLETE - COMPLETE Interrupt Enable Clear
|
|
* 0b1..Corresponding interrupt enable becomes 0
|
|
* 0b0..No effect
|
|
*/
|
|
#define I3C_MINTCLR_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_COMPLETE_SHIFT)) & I3C_MINTCLR_COMPLETE_MASK)
|
|
|
|
#define I3C_MINTCLR_RXPEND_MASK (0x800U)
|
|
#define I3C_MINTCLR_RXPEND_SHIFT (11U)
|
|
/*! RXPEND - RXPEND Interrupt Enable Clear
|
|
* 0b1..Corresponding interrupt enable becomes 0
|
|
* 0b0..No effect
|
|
*/
|
|
#define I3C_MINTCLR_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_RXPEND_SHIFT)) & I3C_MINTCLR_RXPEND_MASK)
|
|
|
|
#define I3C_MINTCLR_TXNOTFULL_MASK (0x1000U)
|
|
#define I3C_MINTCLR_TXNOTFULL_SHIFT (12U)
|
|
/*! TXNOTFULL - TXNOTFULL Interrupt Enable Clear
|
|
* 0b1..Corresponding interrupt enable becomes 0
|
|
* 0b0..No effect
|
|
*/
|
|
#define I3C_MINTCLR_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_TXNOTFULL_SHIFT)) & I3C_MINTCLR_TXNOTFULL_MASK)
|
|
|
|
#define I3C_MINTCLR_IBIWON_MASK (0x2000U)
|
|
#define I3C_MINTCLR_IBIWON_SHIFT (13U)
|
|
/*! IBIWON - IBIWON Interrupt Enable Clear
|
|
* 0b1..Corresponding interrupt enable becomes 0
|
|
* 0b0..No effect
|
|
*/
|
|
#define I3C_MINTCLR_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_IBIWON_SHIFT)) & I3C_MINTCLR_IBIWON_MASK)
|
|
|
|
#define I3C_MINTCLR_ERRWARN_MASK (0x8000U)
|
|
#define I3C_MINTCLR_ERRWARN_SHIFT (15U)
|
|
/*! ERRWARN - ERRWARN Interrupt Enable Clear
|
|
* 0b1..Corresponding interrupt enable becomes 0
|
|
* 0b0..No effect
|
|
*/
|
|
#define I3C_MINTCLR_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_ERRWARN_SHIFT)) & I3C_MINTCLR_ERRWARN_MASK)
|
|
|
|
#define I3C_MINTCLR_NOWMASTER_MASK (0x80000U)
|
|
#define I3C_MINTCLR_NOWMASTER_SHIFT (19U)
|
|
/*! NOWMASTER - NOWCONTROLLER Interrupt Enable Clear
|
|
* 0b1..Corresponding interrupt enable becomes 0
|
|
* 0b0..No effect
|
|
*/
|
|
#define I3C_MINTCLR_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_NOWMASTER_SHIFT)) & I3C_MINTCLR_NOWMASTER_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MINTMASKED - Controller Interrupt Mask */
|
|
/*! @{ */
|
|
|
|
#define I3C_MINTMASKED_SLVSTART_MASK (0x100U)
|
|
#define I3C_MINTMASKED_SLVSTART_SHIFT (8U)
|
|
/*! SLVSTART - SLVSTART Interrupt Mask
|
|
* 0b1..Interrupt enabled and active
|
|
* 0b0..Interrupt not enabled and/or not active
|
|
*/
|
|
#define I3C_MINTMASKED_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_SLVSTART_SHIFT)) & I3C_MINTMASKED_SLVSTART_MASK)
|
|
|
|
#define I3C_MINTMASKED_MCTRLDONE_MASK (0x200U)
|
|
#define I3C_MINTMASKED_MCTRLDONE_SHIFT (9U)
|
|
/*! MCTRLDONE - MCTRLDONE Interrupt Mask
|
|
* 0b1..Interrupt enabled and active
|
|
* 0b0..Interrupt not enabled and/or not active
|
|
*/
|
|
#define I3C_MINTMASKED_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_MCTRLDONE_SHIFT)) & I3C_MINTMASKED_MCTRLDONE_MASK)
|
|
|
|
#define I3C_MINTMASKED_COMPLETE_MASK (0x400U)
|
|
#define I3C_MINTMASKED_COMPLETE_SHIFT (10U)
|
|
/*! COMPLETE - COMPLETE Interrupt Mask
|
|
* 0b1..Interrupt enabled and active
|
|
* 0b0..Interrupt not enabled and/or not active
|
|
*/
|
|
#define I3C_MINTMASKED_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_COMPLETE_SHIFT)) & I3C_MINTMASKED_COMPLETE_MASK)
|
|
|
|
#define I3C_MINTMASKED_RXPEND_MASK (0x800U)
|
|
#define I3C_MINTMASKED_RXPEND_SHIFT (11U)
|
|
/*! RXPEND - RXPEND Interrupt Mask */
|
|
#define I3C_MINTMASKED_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_RXPEND_SHIFT)) & I3C_MINTMASKED_RXPEND_MASK)
|
|
|
|
#define I3C_MINTMASKED_TXNOTFULL_MASK (0x1000U)
|
|
#define I3C_MINTMASKED_TXNOTFULL_SHIFT (12U)
|
|
/*! TXNOTFULL - TXNOTFULL Interrupt Mask
|
|
* 0b1..Interrupt enabled and active
|
|
* 0b0..Interrupt not enabled and/or not active
|
|
*/
|
|
#define I3C_MINTMASKED_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_TXNOTFULL_SHIFT)) & I3C_MINTMASKED_TXNOTFULL_MASK)
|
|
|
|
#define I3C_MINTMASKED_IBIWON_MASK (0x2000U)
|
|
#define I3C_MINTMASKED_IBIWON_SHIFT (13U)
|
|
/*! IBIWON - IBIWON Interrupt Mask
|
|
* 0b1..Interrupt enabled and active
|
|
* 0b0..Interrupt not enabled and/or not active
|
|
*/
|
|
#define I3C_MINTMASKED_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_IBIWON_SHIFT)) & I3C_MINTMASKED_IBIWON_MASK)
|
|
|
|
#define I3C_MINTMASKED_ERRWARN_MASK (0x8000U)
|
|
#define I3C_MINTMASKED_ERRWARN_SHIFT (15U)
|
|
/*! ERRWARN - ERRWARN Interrupt Mask
|
|
* 0b1..Interrupt enabled and active
|
|
* 0b0..Interrupt not enabled and/or not active
|
|
*/
|
|
#define I3C_MINTMASKED_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_ERRWARN_SHIFT)) & I3C_MINTMASKED_ERRWARN_MASK)
|
|
|
|
#define I3C_MINTMASKED_NOWMASTER_MASK (0x80000U)
|
|
#define I3C_MINTMASKED_NOWMASTER_SHIFT (19U)
|
|
/*! NOWMASTER - NOWCONTROLLER Interrupt Mask
|
|
* 0b1..Interrupt enabled and active
|
|
* 0b0..Interrupt not enabled and/or not active
|
|
*/
|
|
#define I3C_MINTMASKED_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_NOWMASTER_SHIFT)) & I3C_MINTMASKED_NOWMASTER_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MERRWARN - Controller Errors and Warnings */
|
|
/*! @{ */
|
|
|
|
#define I3C_MERRWARN_URUN_MASK (0x2U)
|
|
#define I3C_MERRWARN_URUN_SHIFT (1U)
|
|
/*! URUN - Underrun error
|
|
* 0b1..Error
|
|
* 0b0..No error
|
|
*/
|
|
#define I3C_MERRWARN_URUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_URUN_SHIFT)) & I3C_MERRWARN_URUN_MASK)
|
|
|
|
#define I3C_MERRWARN_NACK_MASK (0x4U)
|
|
#define I3C_MERRWARN_NACK_SHIFT (2U)
|
|
/*! NACK - Not Acknowledge Error
|
|
* 0b1..Error
|
|
* 0b0..No error
|
|
*/
|
|
#define I3C_MERRWARN_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_NACK_SHIFT)) & I3C_MERRWARN_NACK_MASK)
|
|
|
|
#define I3C_MERRWARN_WRABT_MASK (0x8U)
|
|
#define I3C_MERRWARN_WRABT_SHIFT (3U)
|
|
/*! WRABT - Write Abort Error
|
|
* 0b1..Error
|
|
* 0b0..No error
|
|
*/
|
|
#define I3C_MERRWARN_WRABT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_WRABT_SHIFT)) & I3C_MERRWARN_WRABT_MASK)
|
|
|
|
#define I3C_MERRWARN_TERM_MASK (0x10U)
|
|
#define I3C_MERRWARN_TERM_SHIFT (4U)
|
|
/*! TERM - Terminate Error
|
|
* 0b1..Error
|
|
* 0b0..No error
|
|
*/
|
|
#define I3C_MERRWARN_TERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TERM_SHIFT)) & I3C_MERRWARN_TERM_MASK)
|
|
|
|
#define I3C_MERRWARN_HPAR_MASK (0x200U)
|
|
#define I3C_MERRWARN_HPAR_SHIFT (9U)
|
|
/*! HPAR - High Data Rate Parity
|
|
* 0b1..Error
|
|
* 0b0..No error
|
|
*/
|
|
#define I3C_MERRWARN_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HPAR_SHIFT)) & I3C_MERRWARN_HPAR_MASK)
|
|
|
|
#define I3C_MERRWARN_HCRC_MASK (0x400U)
|
|
#define I3C_MERRWARN_HCRC_SHIFT (10U)
|
|
/*! HCRC - High Data Rate CRC Error
|
|
* 0b1..Error
|
|
* 0b0..No error
|
|
*/
|
|
#define I3C_MERRWARN_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HCRC_SHIFT)) & I3C_MERRWARN_HCRC_MASK)
|
|
|
|
#define I3C_MERRWARN_OREAD_MASK (0x10000U)
|
|
#define I3C_MERRWARN_OREAD_SHIFT (16U)
|
|
/*! OREAD - Over-read Error
|
|
* 0b1..Error
|
|
* 0b0..No error
|
|
*/
|
|
#define I3C_MERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OREAD_SHIFT)) & I3C_MERRWARN_OREAD_MASK)
|
|
|
|
#define I3C_MERRWARN_OWRITE_MASK (0x20000U)
|
|
#define I3C_MERRWARN_OWRITE_SHIFT (17U)
|
|
/*! OWRITE - Over-write Error
|
|
* 0b1..Error
|
|
* 0b0..No error
|
|
*/
|
|
#define I3C_MERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OWRITE_SHIFT)) & I3C_MERRWARN_OWRITE_MASK)
|
|
|
|
#define I3C_MERRWARN_MSGERR_MASK (0x40000U)
|
|
#define I3C_MERRWARN_MSGERR_SHIFT (18U)
|
|
/*! MSGERR - Message Error
|
|
* 0b1..Error
|
|
* 0b0..No error
|
|
*/
|
|
#define I3C_MERRWARN_MSGERR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_MSGERR_SHIFT)) & I3C_MERRWARN_MSGERR_MASK)
|
|
|
|
#define I3C_MERRWARN_INVREQ_MASK (0x80000U)
|
|
#define I3C_MERRWARN_INVREQ_SHIFT (19U)
|
|
/*! INVREQ - Invalid Request Error
|
|
* 0b1..Error
|
|
* 0b0..No error
|
|
*/
|
|
#define I3C_MERRWARN_INVREQ(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_INVREQ_SHIFT)) & I3C_MERRWARN_INVREQ_MASK)
|
|
|
|
#define I3C_MERRWARN_TIMEOUT_MASK (0x100000U)
|
|
#define I3C_MERRWARN_TIMEOUT_SHIFT (20U)
|
|
/*! TIMEOUT - Timeout Error
|
|
* 0b1..Error
|
|
* 0b0..No error
|
|
*/
|
|
#define I3C_MERRWARN_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TIMEOUT_SHIFT)) & I3C_MERRWARN_TIMEOUT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MDMACTRL - Controller DMA Control */
|
|
/*! @{ */
|
|
|
|
#define I3C_MDMACTRL_DMAFB_MASK (0x3U)
|
|
#define I3C_MDMACTRL_DMAFB_SHIFT (0U)
|
|
/*! DMAFB - DMA From Bus
|
|
* 0b00..DMA is not used
|
|
* 0b01..Enable DMA for one frame
|
|
* 0b10..Enable DMA until DMA is turned off
|
|
* 0b11..
|
|
*/
|
|
#define I3C_MDMACTRL_DMAFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAFB_SHIFT)) & I3C_MDMACTRL_DMAFB_MASK)
|
|
|
|
#define I3C_MDMACTRL_DMATB_MASK (0xCU)
|
|
#define I3C_MDMACTRL_DMATB_SHIFT (2U)
|
|
/*! DMATB - DMA To Bus
|
|
* 0b00..DMA is not used
|
|
* 0b01..Enable DMA for one frame (ended by DMA or Terminated)
|
|
* 0b10..Enable DMA until DMA is turned off
|
|
* 0b11..
|
|
*/
|
|
#define I3C_MDMACTRL_DMATB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMATB_SHIFT)) & I3C_MDMACTRL_DMATB_MASK)
|
|
|
|
#define I3C_MDMACTRL_DMAWIDTH_MASK (0x30U)
|
|
#define I3C_MDMACTRL_DMAWIDTH_SHIFT (4U)
|
|
/*! DMAWIDTH - DMA Width
|
|
* 0b00, 0b01..Byte
|
|
* 0b10..Halfword (16 bits)
|
|
* 0b11..
|
|
*/
|
|
#define I3C_MDMACTRL_DMAWIDTH(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAWIDTH_SHIFT)) & I3C_MDMACTRL_DMAWIDTH_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MDATACTRL - Controller Data Control */
|
|
/*! @{ */
|
|
|
|
#define I3C_MDATACTRL_FLUSHTB_MASK (0x1U)
|
|
#define I3C_MDATACTRL_FLUSHTB_SHIFT (0U)
|
|
/*! FLUSHTB - Flush To-bus Buffer or FIFO
|
|
* 0b1..Flush the buffer
|
|
* 0b0..No action
|
|
*/
|
|
#define I3C_MDATACTRL_FLUSHTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHTB_SHIFT)) & I3C_MDATACTRL_FLUSHTB_MASK)
|
|
|
|
#define I3C_MDATACTRL_FLUSHFB_MASK (0x2U)
|
|
#define I3C_MDATACTRL_FLUSHFB_SHIFT (1U)
|
|
/*! FLUSHFB - Flush From-bus Buffer or FIFO
|
|
* 0b1..Flush the buffer
|
|
* 0b0..No action
|
|
*/
|
|
#define I3C_MDATACTRL_FLUSHFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHFB_SHIFT)) & I3C_MDATACTRL_FLUSHFB_MASK)
|
|
|
|
#define I3C_MDATACTRL_UNLOCK_MASK (0x8U)
|
|
#define I3C_MDATACTRL_UNLOCK_SHIFT (3U)
|
|
/*! UNLOCK - Unlock
|
|
* 0b0..Locked. RXTRIG and TXTRIG fields cannot be changed on a write.
|
|
* 0b1..Unlocked. RXTRIG and TXTRIG fields can be changed on a write.
|
|
*/
|
|
#define I3C_MDATACTRL_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_UNLOCK_SHIFT)) & I3C_MDATACTRL_UNLOCK_MASK)
|
|
|
|
#define I3C_MDATACTRL_TXTRIG_MASK (0x30U)
|
|
#define I3C_MDATACTRL_TXTRIG_SHIFT (4U)
|
|
/*! TXTRIG - Transmit Trigger Level
|
|
* 0b00..Trigger when empty
|
|
* 0b01..Trigger when 1/4 full or less
|
|
* 0b10..Trigger when 1/2 full or less
|
|
* 0b11..Default. Trigger when 1 less than full or less
|
|
*/
|
|
#define I3C_MDATACTRL_TXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXTRIG_SHIFT)) & I3C_MDATACTRL_TXTRIG_MASK)
|
|
|
|
#define I3C_MDATACTRL_RXTRIG_MASK (0xC0U)
|
|
#define I3C_MDATACTRL_RXTRIG_SHIFT (6U)
|
|
/*! RXTRIG - Receive Trigger Level
|
|
* 0b00..Trigger when not empty
|
|
* 0b01..Trigger when 1/4 full or more
|
|
* 0b10..Trigger when 1/2 full or more
|
|
* 0b11..Trigger when 3/4 full or more
|
|
*/
|
|
#define I3C_MDATACTRL_RXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXTRIG_SHIFT)) & I3C_MDATACTRL_RXTRIG_MASK)
|
|
|
|
#define I3C_MDATACTRL_TXCOUNT_MASK (0x1F0000U)
|
|
#define I3C_MDATACTRL_TXCOUNT_SHIFT (16U)
|
|
/*! TXCOUNT - Transmit Byte Count */
|
|
#define I3C_MDATACTRL_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXCOUNT_SHIFT)) & I3C_MDATACTRL_TXCOUNT_MASK)
|
|
|
|
#define I3C_MDATACTRL_RXCOUNT_MASK (0x1F000000U)
|
|
#define I3C_MDATACTRL_RXCOUNT_SHIFT (24U)
|
|
/*! RXCOUNT - Receive Byte Count */
|
|
#define I3C_MDATACTRL_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXCOUNT_SHIFT)) & I3C_MDATACTRL_RXCOUNT_MASK)
|
|
|
|
#define I3C_MDATACTRL_TXFULL_MASK (0x40000000U)
|
|
#define I3C_MDATACTRL_TXFULL_SHIFT (30U)
|
|
/*! TXFULL - Transmit Is Full
|
|
* 0b0..Transmit FIFO or buffer is not yet full.
|
|
* 0b1..Transmit FIFO or buffer is full.
|
|
*/
|
|
#define I3C_MDATACTRL_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXFULL_SHIFT)) & I3C_MDATACTRL_TXFULL_MASK)
|
|
|
|
#define I3C_MDATACTRL_RXEMPTY_MASK (0x80000000U)
|
|
#define I3C_MDATACTRL_RXEMPTY_SHIFT (31U)
|
|
/*! RXEMPTY - Receive Is Empty
|
|
* 0b0..Receive FIFO or buffer is not yet empty.
|
|
* 0b1..Receive FIFO or buffer is empty.
|
|
*/
|
|
#define I3C_MDATACTRL_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXEMPTY_SHIFT)) & I3C_MDATACTRL_RXEMPTY_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MWDATAB - Controller Write Data Byte */
|
|
/*! @{ */
|
|
|
|
#define I3C_MWDATAB_VALUE_MASK (0xFFU)
|
|
#define I3C_MWDATAB_VALUE_SHIFT (0U)
|
|
/*! VALUE - Data Byte */
|
|
#define I3C_MWDATAB_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_VALUE_SHIFT)) & I3C_MWDATAB_VALUE_MASK)
|
|
|
|
#define I3C_MWDATAB_END_MASK (0x100U)
|
|
#define I3C_MWDATAB_END_SHIFT (8U)
|
|
/*! END - End of Message
|
|
* 0b0..Not the end. More bytes are assumed to be in the message.
|
|
* 0b1..End. The END bit marks the last byte of the message.
|
|
*/
|
|
#define I3C_MWDATAB_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_SHIFT)) & I3C_MWDATAB_END_MASK)
|
|
|
|
#define I3C_MWDATAB_END_ALSO_MASK (0x10000U)
|
|
#define I3C_MWDATAB_END_ALSO_SHIFT (16U)
|
|
/*! END_ALSO - End of Message Also
|
|
* 0b0..Not the end. More bytes are assumed to be in the message.
|
|
* 0b1..End. The END bit marks the last byte of the message.
|
|
*/
|
|
#define I3C_MWDATAB_END_ALSO(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_ALSO_SHIFT)) & I3C_MWDATAB_END_ALSO_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MWDATABE - Controller Write Data Byte End */
|
|
/*! @{ */
|
|
|
|
#define I3C_MWDATABE_VALUE_MASK (0xFFU)
|
|
#define I3C_MWDATABE_VALUE_SHIFT (0U)
|
|
/*! VALUE - Data */
|
|
#define I3C_MWDATABE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATABE_VALUE_SHIFT)) & I3C_MWDATABE_VALUE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MWDATAH - Controller Write Data Halfword */
|
|
/*! @{ */
|
|
|
|
#define I3C_MWDATAH_DATA0_MASK (0xFFU)
|
|
#define I3C_MWDATAH_DATA0_SHIFT (0U)
|
|
/*! DATA0 - Data Byte 0 */
|
|
#define I3C_MWDATAH_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA0_SHIFT)) & I3C_MWDATAH_DATA0_MASK)
|
|
|
|
#define I3C_MWDATAH_DATA1_MASK (0xFF00U)
|
|
#define I3C_MWDATAH_DATA1_SHIFT (8U)
|
|
/*! DATA1 - Data Byte 1 */
|
|
#define I3C_MWDATAH_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA1_SHIFT)) & I3C_MWDATAH_DATA1_MASK)
|
|
|
|
#define I3C_MWDATAH_END_MASK (0x10000U)
|
|
#define I3C_MWDATAH_END_SHIFT (16U)
|
|
/*! END - End of message
|
|
* 0b0..Not the end. More bytes are assumed to be in the message.
|
|
* 0b1..End. The END bit marks the last byte of the message.
|
|
*/
|
|
#define I3C_MWDATAH_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_END_SHIFT)) & I3C_MWDATAH_END_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MWDATAHE - Controller Write Data Halfword End */
|
|
/*! @{ */
|
|
|
|
#define I3C_MWDATAHE_DATA0_MASK (0xFFU)
|
|
#define I3C_MWDATAHE_DATA0_SHIFT (0U)
|
|
/*! DATA0 - Data Byte 0 */
|
|
#define I3C_MWDATAHE_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA0_SHIFT)) & I3C_MWDATAHE_DATA0_MASK)
|
|
|
|
#define I3C_MWDATAHE_DATA1_MASK (0xFF00U)
|
|
#define I3C_MWDATAHE_DATA1_SHIFT (8U)
|
|
/*! DATA1 - Data Byte 1 */
|
|
#define I3C_MWDATAHE_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA1_SHIFT)) & I3C_MWDATAHE_DATA1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MRDATAB - Controller Read Data Byte */
|
|
/*! @{ */
|
|
|
|
#define I3C_MRDATAB_VALUE_MASK (0xFFU)
|
|
#define I3C_MRDATAB_VALUE_SHIFT (0U)
|
|
/*! VALUE - Value */
|
|
#define I3C_MRDATAB_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAB_VALUE_SHIFT)) & I3C_MRDATAB_VALUE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MRDATAH - Controller Read Data Halfword */
|
|
/*! @{ */
|
|
|
|
#define I3C_MRDATAH_LSB_MASK (0xFFU)
|
|
#define I3C_MRDATAH_LSB_SHIFT (0U)
|
|
/*! LSB - LSB */
|
|
#define I3C_MRDATAH_LSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_LSB_SHIFT)) & I3C_MRDATAH_LSB_MASK)
|
|
|
|
#define I3C_MRDATAH_MSB_MASK (0xFF00U)
|
|
#define I3C_MRDATAH_MSB_SHIFT (8U)
|
|
/*! MSB - MSB */
|
|
#define I3C_MRDATAH_MSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_MSB_SHIFT)) & I3C_MRDATAH_MSB_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MWDATAB1 - Controller Write Byte Data 1(to bus) */
|
|
/*! @{ */
|
|
|
|
#define I3C_MWDATAB1_VALUE_MASK (0xFFU)
|
|
#define I3C_MWDATAB1_VALUE_SHIFT (0U)
|
|
/*! VALUE - Value */
|
|
#define I3C_MWDATAB1_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB1_VALUE_SHIFT)) & I3C_MWDATAB1_VALUE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MWDATAH1 - Controller Write Halfword Data (to bus) */
|
|
/*! @{ */
|
|
|
|
#define I3C_MWDATAH1_VALUE_MASK (0xFFFFU)
|
|
#define I3C_MWDATAH1_VALUE_SHIFT (0U)
|
|
/*! VALUE - Value */
|
|
#define I3C_MWDATAH1_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH1_VALUE_SHIFT)) & I3C_MWDATAH1_VALUE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MWMSG_SDR_CONTROL - Controller Write Message Control in SDR mode */
|
|
/*! @{ */
|
|
|
|
#define I3C_MWMSG_SDR_CONTROL_DIR_MASK (0x1U)
|
|
#define I3C_MWMSG_SDR_CONTROL_DIR_SHIFT (0U)
|
|
/*! DIR - Direction
|
|
* 0b0..Write
|
|
* 0b1..Read
|
|
*/
|
|
#define I3C_MWMSG_SDR_CONTROL_DIR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_DIR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_DIR_MASK)
|
|
|
|
#define I3C_MWMSG_SDR_CONTROL_ADDR_MASK (0xFEU)
|
|
#define I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT (1U)
|
|
/*! ADDR - Address */
|
|
#define I3C_MWMSG_SDR_CONTROL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_ADDR_MASK)
|
|
|
|
#define I3C_MWMSG_SDR_CONTROL_END_MASK (0x100U)
|
|
#define I3C_MWMSG_SDR_CONTROL_END_SHIFT (8U)
|
|
/*! END - End of SDR Message
|
|
* 0b0..Not the end. SDR message ends waiting for a new SDR message (issues a repeated START for a new message).
|
|
* 0b1..End. SDR message ends at the STOP.
|
|
*/
|
|
#define I3C_MWMSG_SDR_CONTROL_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_END_SHIFT)) & I3C_MWMSG_SDR_CONTROL_END_MASK)
|
|
|
|
#define I3C_MWMSG_SDR_CONTROL_I2C_MASK (0x400U)
|
|
#define I3C_MWMSG_SDR_CONTROL_I2C_SHIFT (10U)
|
|
/*! I2C - I2C
|
|
* 0b0..I3C message
|
|
* 0b1..I2C message
|
|
*/
|
|
#define I3C_MWMSG_SDR_CONTROL_I2C(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_I2C_SHIFT)) & I3C_MWMSG_SDR_CONTROL_I2C_MASK)
|
|
|
|
#define I3C_MWMSG_SDR_CONTROL_LEN_MASK (0xF800U)
|
|
#define I3C_MWMSG_SDR_CONTROL_LEN_SHIFT (11U)
|
|
/*! LEN - Length */
|
|
#define I3C_MWMSG_SDR_CONTROL_LEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_LEN_SHIFT)) & I3C_MWMSG_SDR_CONTROL_LEN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MWMSG_SDR_DATA - Controller Write Message Data in SDR mode */
|
|
/*! @{ */
|
|
|
|
#define I3C_MWMSG_SDR_DATA_DATA16B_MASK (0xFFFFU)
|
|
#define I3C_MWMSG_SDR_DATA_DATA16B_SHIFT (0U)
|
|
/*! DATA16B - Data */
|
|
#define I3C_MWMSG_SDR_DATA_DATA16B(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_SDR_DATA_DATA16B_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MRMSG_SDR - Controller Read Message in SDR mode */
|
|
/*! @{ */
|
|
|
|
#define I3C_MRMSG_SDR_DATA_MASK (0xFFFFU)
|
|
#define I3C_MRMSG_SDR_DATA_SHIFT (0U)
|
|
/*! DATA - Data */
|
|
#define I3C_MRMSG_SDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_SDR_DATA_SHIFT)) & I3C_MRMSG_SDR_DATA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MWMSG_DDR_CONTROL - Controller Write Message in DDR mode: First Control Word */
|
|
/*! @{ */
|
|
|
|
#define I3C_MWMSG_DDR_CONTROL_ADDRCMD_MASK (0xFFFFU)
|
|
#define I3C_MWMSG_DDR_CONTROL_ADDRCMD_SHIFT (0U)
|
|
/*! ADDRCMD - Address Command */
|
|
#define I3C_MWMSG_DDR_CONTROL_ADDRCMD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL_ADDRCMD_SHIFT)) & I3C_MWMSG_DDR_CONTROL_ADDRCMD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MWMSG_DDR_CONTROL2 - Controller Write Message in DDR mode Control 2 */
|
|
/*! @{ */
|
|
|
|
#define I3C_MWMSG_DDR_CONTROL2_LEN_MASK (0x3FFU)
|
|
#define I3C_MWMSG_DDR_CONTROL2_LEN_SHIFT (0U)
|
|
/*! LEN - Length of Message */
|
|
#define I3C_MWMSG_DDR_CONTROL2_LEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL2_LEN_SHIFT)) & I3C_MWMSG_DDR_CONTROL2_LEN_MASK)
|
|
|
|
#define I3C_MWMSG_DDR_CONTROL2_END_MASK (0x4000U)
|
|
#define I3C_MWMSG_DDR_CONTROL2_END_SHIFT (14U)
|
|
/*! END - End of message
|
|
* 0b1..End. DDR message ends on HDR Exit.
|
|
* 0b0..Not the end. DDR message ends waiting for a new DDR message (will issue a HDR Restart for the new message).
|
|
*/
|
|
#define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL2_END_SHIFT)) & I3C_MWMSG_DDR_CONTROL2_END_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MWMSG_DDR_DATA - Controller Write Message Data in DDR mode */
|
|
/*! @{ */
|
|
|
|
#define I3C_MWMSG_DDR_DATA_DATA16B_MASK (0xFFFFU)
|
|
#define I3C_MWMSG_DDR_DATA_DATA16B_SHIFT (0U)
|
|
/*! DATA16B - Data */
|
|
#define I3C_MWMSG_DDR_DATA_DATA16B(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_DDR_DATA_DATA16B_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MRMSG_DDR - Controller Read Message in DDR mode */
|
|
/*! @{ */
|
|
|
|
#define I3C_MRMSG_DDR_DATA_MASK (0xFFFFU)
|
|
#define I3C_MRMSG_DDR_DATA_SHIFT (0U)
|
|
/*! DATA - Data */
|
|
#define I3C_MRMSG_DDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_DDR_DATA_SHIFT)) & I3C_MRMSG_DDR_DATA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MDYNADDR - Controller Dynamic Address */
|
|
/*! @{ */
|
|
|
|
#define I3C_MDYNADDR_DAVALID_MASK (0x1U)
|
|
#define I3C_MDYNADDR_DAVALID_SHIFT (0U)
|
|
/*! DAVALID - Dynamic address valid
|
|
* 0b1..Valid DA assigned
|
|
* 0b0..No valid DA assigned
|
|
*/
|
|
#define I3C_MDYNADDR_DAVALID(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DAVALID_SHIFT)) & I3C_MDYNADDR_DAVALID_MASK)
|
|
|
|
#define I3C_MDYNADDR_DADDR_MASK (0xFEU)
|
|
#define I3C_MDYNADDR_DADDR_SHIFT (1U)
|
|
/*! DADDR - Dynamic address */
|
|
#define I3C_MDYNADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DADDR_SHIFT)) & I3C_MDYNADDR_DADDR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SMAPCTRL0 - Map Feature Control 0 */
|
|
/*! @{ */
|
|
|
|
#define I3C_SMAPCTRL0_ENA_MASK (0x1U)
|
|
#define I3C_SMAPCTRL0_ENA_SHIFT (0U)
|
|
/*! ENA - Enable Primary Dynamic Address
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define I3C_SMAPCTRL0_ENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_ENA_SHIFT)) & I3C_SMAPCTRL0_ENA_MASK)
|
|
|
|
#define I3C_SMAPCTRL0_DA_MASK (0xFEU)
|
|
#define I3C_SMAPCTRL0_DA_SHIFT (1U)
|
|
/*! DA - Dynamic Address */
|
|
#define I3C_SMAPCTRL0_DA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_DA_SHIFT)) & I3C_SMAPCTRL0_DA_MASK)
|
|
|
|
#define I3C_SMAPCTRL0_CAUSE_MASK (0x700U)
|
|
#define I3C_SMAPCTRL0_CAUSE_SHIFT (8U)
|
|
/*! CAUSE - Cause
|
|
* 0b000..No information. This value occurs when not configured to write DA.
|
|
* 0b001..Set using ENTDAA
|
|
* 0b010..Set using SETDASA, SETAASA, or SETNEWDA
|
|
* 0b011..Cleared using RSTDAA
|
|
* 0b100..Auto MAP change happened last. The change may have changed this DA as well (for example, ENTDAA, and
|
|
* SETAASA), but at least one MAP entry automatically changed after.
|
|
* *..
|
|
*/
|
|
#define I3C_SMAPCTRL0_CAUSE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_CAUSE_SHIFT)) & I3C_SMAPCTRL0_CAUSE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name IBIEXT1 - Extended IBI Data 1 */
|
|
/*! @{ */
|
|
|
|
#define I3C_IBIEXT1_CNT_MASK (0x7U)
|
|
#define I3C_IBIEXT1_CNT_SHIFT (0U)
|
|
/*! CNT - Count */
|
|
#define I3C_IBIEXT1_CNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_CNT_SHIFT)) & I3C_IBIEXT1_CNT_MASK)
|
|
|
|
#define I3C_IBIEXT1_MAX_MASK (0x70U)
|
|
#define I3C_IBIEXT1_MAX_SHIFT (4U)
|
|
/*! MAX - Maximum */
|
|
#define I3C_IBIEXT1_MAX(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_MAX_SHIFT)) & I3C_IBIEXT1_MAX_MASK)
|
|
|
|
#define I3C_IBIEXT1_EXT1_MASK (0xFF00U)
|
|
#define I3C_IBIEXT1_EXT1_SHIFT (8U)
|
|
/*! EXT1 - Extra byte 1 */
|
|
#define I3C_IBIEXT1_EXT1(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT1_SHIFT)) & I3C_IBIEXT1_EXT1_MASK)
|
|
|
|
#define I3C_IBIEXT1_EXT2_MASK (0xFF0000U)
|
|
#define I3C_IBIEXT1_EXT2_SHIFT (16U)
|
|
/*! EXT2 - Extra byte 2 */
|
|
#define I3C_IBIEXT1_EXT2(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT2_SHIFT)) & I3C_IBIEXT1_EXT2_MASK)
|
|
|
|
#define I3C_IBIEXT1_EXT3_MASK (0xFF000000U)
|
|
#define I3C_IBIEXT1_EXT3_SHIFT (24U)
|
|
/*! EXT3 - Extra byte 3 */
|
|
#define I3C_IBIEXT1_EXT3(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT3_SHIFT)) & I3C_IBIEXT1_EXT3_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name IBIEXT2 - Extended IBI Data 2 */
|
|
/*! @{ */
|
|
|
|
#define I3C_IBIEXT2_EXT4_MASK (0xFFU)
|
|
#define I3C_IBIEXT2_EXT4_SHIFT (0U)
|
|
/*! EXT4 - Extra byte 4 */
|
|
#define I3C_IBIEXT2_EXT4(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT4_SHIFT)) & I3C_IBIEXT2_EXT4_MASK)
|
|
|
|
#define I3C_IBIEXT2_EXT5_MASK (0xFF00U)
|
|
#define I3C_IBIEXT2_EXT5_SHIFT (8U)
|
|
/*! EXT5 - Extra byte 5 */
|
|
#define I3C_IBIEXT2_EXT5(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT5_SHIFT)) & I3C_IBIEXT2_EXT5_MASK)
|
|
|
|
#define I3C_IBIEXT2_EXT6_MASK (0xFF0000U)
|
|
#define I3C_IBIEXT2_EXT6_SHIFT (16U)
|
|
/*! EXT6 - Extra byte 6 */
|
|
#define I3C_IBIEXT2_EXT6(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT6_SHIFT)) & I3C_IBIEXT2_EXT6_MASK)
|
|
|
|
#define I3C_IBIEXT2_EXT7_MASK (0xFF000000U)
|
|
#define I3C_IBIEXT2_EXT7_SHIFT (24U)
|
|
/*! EXT7 - Extra byte 7 */
|
|
#define I3C_IBIEXT2_EXT7(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT7_SHIFT)) & I3C_IBIEXT2_EXT7_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SID - Target Module ID */
|
|
/*! @{ */
|
|
|
|
#define I3C_SID_ID_MASK (0xFFFFFFFFU)
|
|
#define I3C_SID_ID_SHIFT (0U)
|
|
/*! ID - ID */
|
|
#define I3C_SID_ID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SID_ID_SHIFT)) & I3C_SID_ID_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group I3C_Register_Masks */
|
|
|
|
|
|
/* I3C - Peripheral instance base addresses */
|
|
/** Peripheral I3C0 base address */
|
|
#define I3C0_BASE (0x40002000u)
|
|
/** Peripheral I3C0 base pointer */
|
|
#define I3C0 ((I3C_Type *)I3C0_BASE)
|
|
/** Array initializer of I3C peripheral base addresses */
|
|
#define I3C_BASE_ADDRS { I3C0_BASE }
|
|
/** Array initializer of I3C peripheral base pointers */
|
|
#define I3C_BASE_PTRS { I3C0 }
|
|
/** Interrupt vectors for the I3C peripheral type */
|
|
#define I3C_IRQS { I3C0_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group I3C_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- INPUTMUX Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** INPUTMUX - Register Layout Typedef */
|
|
typedef struct {
|
|
uint8_t RESERVED_0[32];
|
|
__IO uint32_t CTIMER0CAP[4]; /**< Capture select register for CTIMER inputs, array offset: 0x20, array step: 0x4 */
|
|
__IO uint32_t TIMER0TRIG; /**< Trigger register for TIMER0, offset: 0x30 */
|
|
uint8_t RESERVED_1[12];
|
|
__IO uint32_t CTIMER1CAP[4]; /**< Capture select register for CTIMER inputs, array offset: 0x40, array step: 0x4 */
|
|
__IO uint32_t TIMER1TRIG; /**< Trigger register for TIMER1, offset: 0x50 */
|
|
uint8_t RESERVED_2[12];
|
|
__IO uint32_t CTIMER2CAP[4]; /**< Capture select register for CTIMER inputs, array offset: 0x60, array step: 0x4 */
|
|
__IO uint32_t TIMER2TRIG; /**< Trigger register for TIMER2 inputs, offset: 0x70 */
|
|
uint8_t RESERVED_3[268];
|
|
__IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */
|
|
__IO uint32_t FREQMEAS_TAR; /**< Selection for frequency measurement reference clock, offset: 0x184 */
|
|
uint8_t RESERVED_4[216];
|
|
__IO uint32_t CMP0_TRIG; /**< CMP0 input connections, offset: 0x260 */
|
|
uint8_t RESERVED_5[28];
|
|
__IO uint32_t ADC0_TRIG[4]; /**< ADC Trigger input connections, array offset: 0x280, array step: 0x4 */
|
|
uint8_t RESERVED_6[208];
|
|
__IO uint32_t QDC0_TRIG; /**< QDC0 Trigger Input Connections, offset: 0x360 */
|
|
__IO uint32_t QDC0_HOME; /**< QDC0 Trigger Input Connections, offset: 0x364 */
|
|
__IO uint32_t QDC0_INDEX; /**< QDC0 Trigger Input Connections, offset: 0x368 */
|
|
__IO uint32_t QDC0_PHASEB; /**< QDC0 Trigger Input Connections, offset: 0x36C */
|
|
__IO uint32_t QDC0_PHASEA; /**< QDC0 Trigger Input Connections, offset: 0x370 */
|
|
__IO uint32_t QDC0_ICAP1; /**< QDC0 Trigger Input Connections, offset: 0x374 */
|
|
__IO uint32_t QDC0_ICAP2; /**< QDC0 Trigger Input Connections, offset: 0x378 */
|
|
__IO uint32_t QDC0_ICAP3; /**< QDC0 Trigger Input Connections, offset: 0x37C */
|
|
uint8_t RESERVED_7[32];
|
|
__IO uint32_t FLEXPWM0_SM0_EXTA0; /**< PWM0 input trigger connections, offset: 0x3A0 */
|
|
__IO uint32_t FLEXPWM0_SM0_EXTSYNC0; /**< PWM0 input trigger connections, offset: 0x3A4 */
|
|
__IO uint32_t FLEXPWM0_SM1_EXTA1; /**< PWM0 input trigger connections, offset: 0x3A8 */
|
|
__IO uint32_t FLEXPWM0_SM1_EXTSYNC1; /**< PWM0 input trigger connections, offset: 0x3AC */
|
|
__IO uint32_t FLEXPWM0_SM2_EXTA2; /**< PWM0 input trigger connections, offset: 0x3B0 */
|
|
__IO uint32_t FLEXPWM0_SM2_EXTSYNC2; /**< PWM0 input trigger connections, offset: 0x3B4 */
|
|
uint8_t RESERVED_8[8];
|
|
__IO uint32_t FLEXPWM0_FAULT0; /**< PWM0 input trigger connections, offset: 0x3C0 */
|
|
__IO uint32_t FLEXPWM0_FAULT1; /**< PWM0 input trigger connections, offset: 0x3C4 */
|
|
__IO uint32_t FLEXPWM0_FAULT2; /**< PWM0 input trigger connections, offset: 0x3C8 */
|
|
__IO uint32_t FLEXPWM0_FAULT3; /**< PWM0 input trigger connections, offset: 0x3CC */
|
|
__IO uint32_t FLEXPWM0_FORCE; /**< PWM0 input trigger connections, offset: 0x3D0 */
|
|
uint8_t RESERVED_9[76];
|
|
__IO uint32_t PWM0_EXT_CLK; /**< PWM0 external clock trigger, offset: 0x420 */
|
|
uint8_t RESERVED_10[28];
|
|
__IO uint32_t AOI0_MUX[16]; /**< AOI0 trigger input connections 0-15, array offset: 0x440, array step: 0x4 */
|
|
__IO uint32_t USBFS_TRIG; /**< USB-FS trigger input connections, offset: 0x480 */
|
|
uint8_t RESERVED_11[60];
|
|
__IO uint32_t EXT_TRIG[5]; /**< EXT trigger connections 0-4, array offset: 0x4C0, array step: 0x4 */
|
|
uint8_t RESERVED_12[4];
|
|
__IO uint32_t EXT_TRIG6[2]; /**< EXT trigger connections 6-7, array offset: 0x4D8, array step: 0x4 */
|
|
__IO uint32_t CMP1_TRIG; /**< CMP1 input connections, offset: 0x4E0 */
|
|
uint8_t RESERVED_13[188];
|
|
__IO uint32_t LPI2C0_TRIG; /**< LPI2C0 trigger input connections, offset: 0x5A0 */
|
|
uint8_t RESERVED_14[60];
|
|
__IO uint32_t LPSPI0_TRIG; /**< LPSPI0 trigger input connections, offset: 0x5E0 */
|
|
uint8_t RESERVED_15[28];
|
|
__IO uint32_t LPSPI1_TRIG; /**< LPSPI1 trigger input connections, offset: 0x600 */
|
|
uint8_t RESERVED_16[28];
|
|
__IO uint32_t LPUART0r; /**< LPUART0 trigger input connections, offset: 0x620, 'r' suffix has been added to avoid a clash with peripheral base pointer macro 'LPUART0' */
|
|
uint8_t RESERVED_17[28];
|
|
__IO uint32_t LPUART1r; /**< LPUART1 trigger input connections, offset: 0x640, 'r' suffix has been added to avoid a clash with peripheral base pointer macro 'LPUART1' */
|
|
uint8_t RESERVED_18[28];
|
|
__IO uint32_t LPUART2r; /**< LPUART2 trigger input connections, offset: 0x660, 'r' suffix has been added to avoid a clash with peripheral base pointer macro 'LPUART2' */
|
|
} INPUTMUX_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- INPUTMUX Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name CTIMERA_CTIMER0CAP - Capture select register for CTIMER inputs */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_CTIMERA_CTIMER0CAP_INP_MASK (0x7FU)
|
|
#define INPUTMUX_CTIMERA_CTIMER0CAP_INP_SHIFT (0U)
|
|
/*! INP - Input number for CTIMER0
|
|
* 0b0000000..Reserved
|
|
* 0b0000001..CT_INP0 input is selected
|
|
* 0b0000010..CT_INP1 input is selected
|
|
* 0b0000011..CT_INP2 input is selected
|
|
* 0b0000100..CT_INP3 input is selected
|
|
* 0b0000101..CT_INP4 input is selected
|
|
* 0b0000110..CT_INP5 input is selected
|
|
* 0b0000111..CT_INP6 input is selected
|
|
* 0b0001000..CT_INP7 input is selected
|
|
* 0b0001001..CT_INP8 input is selected
|
|
* 0b0001010..CT_INP9 input is selected
|
|
* 0b0001011..Reserved
|
|
* 0b0001100..Reserved
|
|
* 0b0001101..CT_INP12 input is selected
|
|
* 0b0001110..CT_INP13 input is selected
|
|
* 0b0001111..CT_INP14 input is selected
|
|
* 0b0010000..CT_INP15 input is selected
|
|
* 0b0010001..CT_INP16 input is selected
|
|
* 0b0010010..CT_INP17 input is selected
|
|
* 0b0010011..CT_INP18 input is selected
|
|
* 0b0010100..CT_INP19 input is selected
|
|
* 0b0010101..USB0 usb0 start of frame input is selected
|
|
* 0b0010110..AOI0_OUT0 input is selected
|
|
* 0b0010111..AOI0_OUT1 input is selected
|
|
* 0b0011000..AOI0_OUT2 input is selected
|
|
* 0b0011001..AOI0_OUT3 input is selected
|
|
* 0b0011010..ADC0_tcomp[0] input is selected
|
|
* 0b0011011..ADC0_tcomp[1] input is selected
|
|
* 0b0011100..ADC0_tcomp[2] input is selected
|
|
* 0b0011101..ADC0_tcomp[3] input is selected
|
|
* 0b0011110..CMP0_OUT input is selected selected
|
|
* 0b0011111..CMP1_OUT input is selected selected
|
|
* 0b0100000..Reserved
|
|
* 0b0100001..CTimer1_MAT1 input is selected
|
|
* 0b0100010..CTimer1_MAT2 input is selected
|
|
* 0b0100011..CTimer1_MAT3 input is selected
|
|
* 0b0100100..CTimer2_MAT1 input is selected
|
|
* 0b0100101..CTimer2_MAT2 input is selected
|
|
* 0b0100110..CTimer2_MAT3 input is selected
|
|
* 0b0100111..QDC0_CMP_FLAG0 input input is selected
|
|
* 0b0101000..QDC0_CMP_FLAG1 input is selected
|
|
* 0b0101001..QDC0_CMP_FLAG2 input is selected
|
|
* 0b0101010..QDC0_CMP_FLAG3 input is selected
|
|
* 0b0101011..QDC0_POS_MATCH0 input is selected
|
|
* 0b0101100..PWM0_SM0_OUT_TRIG0 input is selected
|
|
* 0b0101101..PWM0_SM1_OUT_TRIG0 input is selected
|
|
* 0b0101110..PWM0_SM2_OUT_TRIG0 input is selected
|
|
* 0b0101111..Reserved
|
|
* 0b0110000..LPI2C0 Master End of Packet input is selected
|
|
* 0b0110001..LPI2C0 Slave End of Packet input is selected
|
|
* 0b0110010..Reserved
|
|
* 0b0110011..Reserved
|
|
* 0b0110100..LPSPI0 End of Frame input is selected
|
|
* 0b0110101..LPSPI0 Received Data Word input is selected
|
|
* 0b0110110..LPSPI1 End of Frame input is selected
|
|
* 0b0110111..LPSPI1 Received Data Word input is selected
|
|
* 0b0111000..LPUART0 Received Data Word input is selected
|
|
* 0b0111001..LPUART0 Transmitted Data Word input is selected
|
|
* 0b0111010..LPUART0 Receive Line Idle input is selected
|
|
* 0b0111011..LPUART1 Received Data Word input is selected
|
|
* 0b0111100..LPUART1 Transmitted Data Word input is selected
|
|
* 0b0111101..LPUART1 Receive Line Idle input is selected
|
|
* 0b0111110..LPUART2 Received Data Word input is selected
|
|
* 0b0111111..LPUART2 Transmitted Data Word input is selected
|
|
* 0b1000000..LPUART2 Receive Line Idle input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_CTIMERA_CTIMER0CAP_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMERA_CTIMER0CAP_INP_SHIFT)) & INPUTMUX_CTIMERA_CTIMER0CAP_INP_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of INPUTMUX_CTIMERA_CTIMER0CAP */
|
|
#define INPUTMUX_CTIMERA_CTIMER0CAP_COUNT (4U)
|
|
|
|
/*! @name TIMER0TRIG - Trigger register for TIMER0 */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_TIMER0TRIG_INP_MASK (0x7FU)
|
|
#define INPUTMUX_TIMER0TRIG_INP_SHIFT (0U)
|
|
/*! INP - Input number for CTIMER0
|
|
* 0b0000000..Reserved
|
|
* 0b0000001..CT_INP0 input is selected
|
|
* 0b0000010..CT_INP1 input is selected
|
|
* 0b0000011..CT_INP2 input is selected
|
|
* 0b0000100..CT_INP3 input is selected
|
|
* 0b0000101..CT_INP4 input is selected
|
|
* 0b0000110..CT_INP5 input is selected
|
|
* 0b0000111..CT_INP6 input is selected
|
|
* 0b0001000..CT_INP7 input is selected
|
|
* 0b0001001..CT_INP8 input is selected
|
|
* 0b0001010..CT_INP9 input is selected
|
|
* 0b0001011..Reserved
|
|
* 0b0001100..Reserved
|
|
* 0b0001101..CT_INP12 input is selected
|
|
* 0b0001110..CT_INP13 input is selected
|
|
* 0b0001111..CT_INP14 input is selected
|
|
* 0b0010000..CT_INP15 input is selected
|
|
* 0b0010001..CT_INP16 input is selected
|
|
* 0b0010010..CT_INP17 input is selected
|
|
* 0b0010011..CT_INP18 input is selected
|
|
* 0b0010100..CT_INP19 input is selected
|
|
* 0b0010101..USB0 usb0 start of frame input is selected
|
|
* 0b0010110..AOI0_OUT0 input is selected
|
|
* 0b0010111..AOI0_OUT1 input is selected
|
|
* 0b0011000..AOI0_OUT2 input is selected
|
|
* 0b0011001..AOI0_OUT3 input is selected
|
|
* 0b0011010..ADC0_tcomp[0] input is selected
|
|
* 0b0011011..ADC0_tcomp[1] input is selected
|
|
* 0b0011100..ADC0_tcomp[2] input is selected
|
|
* 0b0011101..ADC0_tcomp[3] input is selected
|
|
* 0b0011110..CMP0_OUT input is selected selected
|
|
* 0b0011111..CMP1_OUT input is selected selected
|
|
* 0b0100000..Reserved
|
|
* 0b0100001..CTimer1_MAT1 input is selected
|
|
* 0b0100010..CTimer1_MAT2 input is selected
|
|
* 0b0100011..CTimer1_MAT3 input is selected
|
|
* 0b0100100..CTimer2_MAT1 input is selected
|
|
* 0b0100101..CTimer2_MAT2 input is selected
|
|
* 0b0100110..CTimer2_MAT3 input is selected
|
|
* 0b0100111..QDC0_CMP_FLAG0 input is selected
|
|
* 0b0101000..QDC0_CMP_FLAG1 input is selected
|
|
* 0b0101001..QDC0_CMP_FLAG2 input is selected
|
|
* 0b0101010..QDC0_CMP_FLAG3 input is selected
|
|
* 0b0101011..QDC0_POS_MATCH0 input is selected
|
|
* 0b0101100..PWM0_SM0_OUT_TRIG0 input is selected
|
|
* 0b0101101..PWM0_SM1_OUT_TRIG0 input is selected
|
|
* 0b0101110..PWM0_SM2_OUT_TRIG0 input is selected
|
|
* 0b0101111..Reserved
|
|
* 0b0110000..LPI2C0 Master End of Packet input is selected
|
|
* 0b0110001..LPI2C0 Slave End of Packet input is selected
|
|
* 0b0110010..Reserved
|
|
* 0b0110011..Reserved
|
|
* 0b0110100..LPSPI0 End of Frame input is selected
|
|
* 0b0110101..LPSPI0 Received Data Word input is selected
|
|
* 0b0110110..LPSPI1 End of Frame input is selected
|
|
* 0b0110111..LPSPI1 Received Data Word input is selected
|
|
* 0b0111000..LPUART0 Received Data Word input is selected
|
|
* 0b0111001..LPUART0 Transmitted Data Word input is selected
|
|
* 0b0111010..LPUART0 Receive Line Idle input is selected
|
|
* 0b0111011..LPUART1 Received Data Word input is selected
|
|
* 0b0111100..LPUART1 Transmitted Data Word input is selected
|
|
* 0b0111101..LPUART1 Receive Line Idle input is selected
|
|
* 0b0111110..LPUART2 Received Data Word input is selected
|
|
* 0b0111111..LPUART2 Transmitted Data Word input is selected
|
|
* 0b1000000..LPUART2 Receive Line Idle input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_TIMER0TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER0TRIG_INP_SHIFT)) & INPUTMUX_TIMER0TRIG_INP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CTIMERB_CTIMER1CAP - Capture select register for CTIMER inputs */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_CTIMERB_CTIMER1CAP_INP_MASK (0x7FU)
|
|
#define INPUTMUX_CTIMERB_CTIMER1CAP_INP_SHIFT (0U)
|
|
/*! INP - Input number for CTIMER0
|
|
* 0b0000000..Reserved
|
|
* 0b0000001..CT_INP0 input is selected
|
|
* 0b0000010..CT_INP1 input is selected
|
|
* 0b0000011..CT_INP2 input is selected
|
|
* 0b0000100..CT_INP3 input is selected
|
|
* 0b0000101..CT_INP4 input is selected
|
|
* 0b0000110..CT_INP5 input is selected
|
|
* 0b0000111..CT_INP6 input is selected
|
|
* 0b0001000..CT_INP7 input is selected
|
|
* 0b0001001..CT_INP8 input is selected
|
|
* 0b0001010..CT_INP9 input is selected
|
|
* 0b0001011..Reserved
|
|
* 0b0001100..Reserved
|
|
* 0b0001101..CT_INP12 input is selected
|
|
* 0b0001110..CT_INP13 input is selected
|
|
* 0b0001111..CT_INP14 input is selected
|
|
* 0b0010000..CT_INP15 input is selected
|
|
* 0b0010001..CT_INP16 input is selected
|
|
* 0b0010010..CT_INP17 input is selected
|
|
* 0b0010011..CT_INP18 input is selected
|
|
* 0b0010100..CT_INP19 input is selected
|
|
* 0b0010101..USB0 usb0 start of frame input is selected
|
|
* 0b0010110..AOI0_OUT0 input is selected
|
|
* 0b0010111..AOI0_OUT1 input is selected
|
|
* 0b0011000..AOI0_OUT2 input is selected
|
|
* 0b0011001..AOI0_OUT3 input is selected
|
|
* 0b0011010..ADC0_tcomp[0] input is selected
|
|
* 0b0011011..ADC0_tcomp[1] input is selected
|
|
* 0b0011100..ADC0_tcomp[2] input is selected
|
|
* 0b0011101..ADC0_tcomp[3] input is selected
|
|
* 0b0011110..CMP0_OUT input is selected
|
|
* 0b0011111..CMP1_OUT input is selected
|
|
* 0b0100000..Reserved
|
|
* 0b0100001..CTimer0_MAT1 input is selected
|
|
* 0b0100010..CTimer0_MAT2 input is selected
|
|
* 0b0100011..CTimer0_MAT3 input is selected
|
|
* 0b0100100..CTimer2_MAT1 input is selected
|
|
* 0b0100101..CTimer2_MAT2 input is selected
|
|
* 0b0100110..CTimer2_MAT3 input is selected
|
|
* 0b0100111..QDC0_CMP_FLAG0 input is selected
|
|
* 0b0101000..QDC0_CMP_FLAG1 input is selected
|
|
* 0b0101001..QDC0_CMP_FLAG2 input is selected
|
|
* 0b0101010..QDC0_CMP_FLAG3 input is selected
|
|
* 0b0101011..QDC0_POS_MATCH0 input is selected
|
|
* 0b0101100..PWM0_SM0_OUT_TRIG0 input is selected
|
|
* 0b0101101..PWM0_SM1_OUT_TRIG0 input is selected
|
|
* 0b0101110..PWM0_SM2_OUT_TRIG0 input is selected
|
|
* 0b0101111..Reserved
|
|
* 0b0110000..LPI2C0 Master End of Packet input is selected
|
|
* 0b0110001..LPI2C0 Slave End of Packet input is selected
|
|
* 0b0110010..Reserved
|
|
* 0b0110011..Reserved
|
|
* 0b0110100..LPSPI0 End of Frame input is selected
|
|
* 0b0110101..LPSPI0 Received Data Word input is selected
|
|
* 0b0110110..LPSPI1 End of Frame input is selected
|
|
* 0b0110111..LPSPI1 Received Data Word input is selected
|
|
* 0b0111000..LPUART0 Received Data Word input is selected
|
|
* 0b0111001..LPUART0 Transmitted Data Word input is selected
|
|
* 0b0111010..LPUART0 Receive Line Idle input is selected
|
|
* 0b0111011..LPUART1 Received Data Word input is selected
|
|
* 0b0111100..LPUART1 Transmitted Data Word input is selected
|
|
* 0b0111101..LPUART1 Receive Line Idle input is selected
|
|
* 0b0111110..LPUART2 Received Data Word input is selected
|
|
* 0b0111111..LPUART2 Transmitted Data Word input is selected
|
|
* 0b1000000..LPUART2 Receive Line Idle input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_CTIMERB_CTIMER1CAP_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMERB_CTIMER1CAP_INP_SHIFT)) & INPUTMUX_CTIMERB_CTIMER1CAP_INP_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of INPUTMUX_CTIMERB_CTIMER1CAP */
|
|
#define INPUTMUX_CTIMERB_CTIMER1CAP_COUNT (4U)
|
|
|
|
/*! @name TIMER1TRIG - Trigger register for TIMER1 */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_TIMER1TRIG_INP_MASK (0x7FU)
|
|
#define INPUTMUX_TIMER1TRIG_INP_SHIFT (0U)
|
|
/*! INP - Input number for CTIMER0
|
|
* 0b0000000..Reserved
|
|
* 0b0000001..CT_INP0 input is selected
|
|
* 0b0000010..CT_INP1 input is selected
|
|
* 0b0000011..CT_INP2 input is selected
|
|
* 0b0000100..CT_INP3 input is selected
|
|
* 0b0000101..CT_INP4 input is selected
|
|
* 0b0000110..CT_INP5 input is selected
|
|
* 0b0000111..CT_INP6 input is selected
|
|
* 0b0001000..CT_INP7 input is selected
|
|
* 0b0001001..CT_INP8 input is selected
|
|
* 0b0001010..CT_INP9 input is selected
|
|
* 0b0001011..Reserved
|
|
* 0b0001100..Reserved
|
|
* 0b0001101..CT_INP12 input is selected
|
|
* 0b0001110..CT_INP13 input is selected
|
|
* 0b0001111..CT_INP14 input is selected
|
|
* 0b0010000..CT_INP15 input is selected
|
|
* 0b0010001..CT_INP16 input is selected
|
|
* 0b0010010..CT_INP17 input is selected
|
|
* 0b0010011..CT_INP18 input is selected
|
|
* 0b0010100..CT_INP19 input is selected
|
|
* 0b0010101..USB0 usb0 start of frame input is selected
|
|
* 0b0010110..AOI0_OUT0 input is selected
|
|
* 0b0010111..AOI0_OUT1 input is selected
|
|
* 0b0011000..AOI0_OUT2 input is selected
|
|
* 0b0011001..AOI0_OUT3 input is selected
|
|
* 0b0011010..ADC0_tcomp[0] input is selected
|
|
* 0b0011011..ADC0_tcomp[1] input is selected
|
|
* 0b0011100..ADC0_tcomp[2] input is selected
|
|
* 0b0011101..ADC0_tcomp[3] input is selected
|
|
* 0b0011110..CMP0_OUT input is selected
|
|
* 0b0011111..CMP1_OUT input is selected
|
|
* 0b0100000..Reserved
|
|
* 0b0100001..CTimer0_MAT1 input is selected
|
|
* 0b0100010..CTimer0_MAT2 input is selected
|
|
* 0b0100011..CTimer0_MAT3 input is selected
|
|
* 0b0100100..CTimer2_MAT1 input is selected
|
|
* 0b0100101..CTimer2_MAT2 input is selected
|
|
* 0b0100110..CTimer2_MAT3 input is selected
|
|
* 0b0100111..QDC0_CMP_FLAG0 input is selected
|
|
* 0b0101000..QDC0_CMP_FLAG1 input is selected
|
|
* 0b0101001..QDC0_CMP_FLAG2 input is selected
|
|
* 0b0101010..QDC0_CMP_FLAG3 input is selected
|
|
* 0b0101011..QDC0_POS_MATCH0 input is selected
|
|
* 0b0101100..PWM0_SM0_OUT_TRIG0 input is selected
|
|
* 0b0101101..PWM0_SM1_OUT_TRIG0 input is selected
|
|
* 0b0101110..PWM0_SM2_OUT_TRIG0 input is selected
|
|
* 0b0101111..Reserved
|
|
* 0b0110000..LPI2C0 Master End of Packet input is selected
|
|
* 0b0110001..LPI2C0 Slave End of Packet input is selected
|
|
* 0b0110010..Reserved
|
|
* 0b0110011..Reserved
|
|
* 0b0110100..LPSPI0 End of Frame input is selected
|
|
* 0b0110101..LPSPI0 Received Data Word input is selected
|
|
* 0b0110110..LPSPI1 End of Frame input is selected
|
|
* 0b0110111..LPSPI1 Received Data Word input is selected
|
|
* 0b0111000..LPUART0 Received Data Word input is selected
|
|
* 0b0111001..LPUART0 Transmitted Data Word input is selected
|
|
* 0b0111010..LPUART0 Receive Line Idle input is selected
|
|
* 0b0111011..LPUART1 Received Data Word input is selected
|
|
* 0b0111100..LPUART1 Transmitted Data Word input is selected
|
|
* 0b0111101..LPUART1 Receive Line Idle input is selected
|
|
* 0b0111110..LPUART2 Received Data Word input is selected
|
|
* 0b0111111..LPUART2 Transmitted Data Word input is selected
|
|
* 0b1000000..LPUART2 Receive Line Idle input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_TIMER1TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER1TRIG_INP_SHIFT)) & INPUTMUX_TIMER1TRIG_INP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CTIMERC_CTIMER2CAP - Capture select register for CTIMER inputs */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_CTIMERC_CTIMER2CAP_INP_MASK (0x7FU)
|
|
#define INPUTMUX_CTIMERC_CTIMER2CAP_INP_SHIFT (0U)
|
|
/*! INP - Input number for CTIMER0
|
|
* 0b0000000..Reserved
|
|
* 0b0000001..CT_INP0 input is selected
|
|
* 0b0000010..CT_INP1 input is selected
|
|
* 0b0000011..CT_INP2 input is selected
|
|
* 0b0000100..CT_INP3 input is selected
|
|
* 0b0000101..CT_INP4 input is selected
|
|
* 0b0000110..CT_INP5 input is selected
|
|
* 0b0000111..CT_INP6 input is selected
|
|
* 0b0001000..CT_INP7 input is selected
|
|
* 0b0001001..CT_INP8 input is selected
|
|
* 0b0001010..CT_INP9 input is selected
|
|
* 0b0001011..Reserved
|
|
* 0b0001100..Reserved
|
|
* 0b0001101..CT_INP12 input is selected
|
|
* 0b0001110..CT_INP13 input is selected
|
|
* 0b0001111..CT_INP14 input is selected
|
|
* 0b0010000..CT_INP15 input is selected
|
|
* 0b0010001..CT_INP16 input is selected
|
|
* 0b0010010..CT_INP17 input is selected
|
|
* 0b0010011..CT_INP18 input is selected
|
|
* 0b0010100..CT_INP19 input is selected
|
|
* 0b0010101..USB0 usb0 start of frame input is selected
|
|
* 0b0010110..AOI0_OUT0 input is selected
|
|
* 0b0010111..AOI0_OUT1 input is selected
|
|
* 0b0011000..AOI0_OUT2 input is selected
|
|
* 0b0011001..AOI0_OUT3 input is selected
|
|
* 0b0011010..ADC0_tcomp[0] input is selected
|
|
* 0b0011011..ADC0_tcomp[1] input is selected
|
|
* 0b0011100..ADC0_tcomp[2] input is selected
|
|
* 0b0011101..ADC0_tcomp[3] input is selected
|
|
* 0b0011110..CMP0_OUT input is selected
|
|
* 0b0011111..CMP1_OUT input is selected
|
|
* 0b0100000..Reserved
|
|
* 0b0100001..CTimer0_MAT1 input is selected
|
|
* 0b0100010..CTimer0_MAT2 input is selected
|
|
* 0b0100011..CTimer0_MAT3 input is selected
|
|
* 0b0100100..CTimer1_MAT1 input is selected
|
|
* 0b0100101..CTimer1_MAT2 input is selected
|
|
* 0b0100110..CTimer1_MAT3 input is selected
|
|
* 0b0100111..QDC0_CMP_FLAG0 input is selected
|
|
* 0b0101000..QDC0_CMP_FLAG1 input is selected
|
|
* 0b0101001..QDC0_CMP_FLAG2 input is selected
|
|
* 0b0101010..QDC0_CMP_FLAG3 input is selected
|
|
* 0b0101011..QDC0_POS_MATCH0 input is selected
|
|
* 0b0101100..PWM0_SM0_OUT_TRIG0 input is selected
|
|
* 0b0101101..PWM0_SM1_OUT_TRIG0 input is selected
|
|
* 0b0101110..PWM0_SM2_OUT_TRIG0 input is selected
|
|
* 0b0101111..Reserved
|
|
* 0b0110000..LPI2C0 Master End of Packet input is selected
|
|
* 0b0110001..LPI2C0 Slave End of Packet input is selected
|
|
* 0b0110010..Reserved
|
|
* 0b0110011..Reserved
|
|
* 0b0110100..LPSPI0 End of Frame input is selected
|
|
* 0b0110101..LPSPI0 Received Data Word input is selected
|
|
* 0b0110110..LPSPI1 End of Frame input is selected
|
|
* 0b0110111..LPSPI1 Received Data Word input is selected
|
|
* 0b0111000..LPUART0 Received Data Word input is selected
|
|
* 0b0111001..LPUART0 Transmitted Data Word input is selected
|
|
* 0b0111010..LPUART0 Receive Line Idle input is selected
|
|
* 0b0111011..LPUART1 Received Data Word input is selected
|
|
* 0b0111100..LPUART1 Transmitted Data Word input is selected
|
|
* 0b0111101..LPUART1 Receive Line Idle input is selected
|
|
* 0b0111110..LPUART2 Received Data Word input is selected
|
|
* 0b0111111..LPUART2 Transmitted Data Word input is selected
|
|
* 0b1000000..LPUART2 Receive Line Idle input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_CTIMERC_CTIMER2CAP_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMERC_CTIMER2CAP_INP_SHIFT)) & INPUTMUX_CTIMERC_CTIMER2CAP_INP_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of INPUTMUX_CTIMERC_CTIMER2CAP */
|
|
#define INPUTMUX_CTIMERC_CTIMER2CAP_COUNT (4U)
|
|
|
|
/*! @name TIMER2TRIG - Trigger register for TIMER2 inputs */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_TIMER2TRIG_INP_MASK (0x7FU)
|
|
#define INPUTMUX_TIMER2TRIG_INP_SHIFT (0U)
|
|
/*! INP - Input number for CTIMER0
|
|
* 0b0000000..Reserved
|
|
* 0b0000001..CT_INP0 input is selected
|
|
* 0b0000010..CT_INP1 input is selected
|
|
* 0b0000011..CT_INP2 input is selected
|
|
* 0b0000100..CT_INP3 input is selected
|
|
* 0b0000101..CT_INP4 input is selected
|
|
* 0b0000110..CT_INP5 input is selected
|
|
* 0b0000111..CT_INP6 input is selected
|
|
* 0b0001000..CT_INP7 input is selected
|
|
* 0b0001001..CT_INP8 input is selected
|
|
* 0b0001010..CT_INP9 input is selected
|
|
* 0b0001011..Reserved
|
|
* 0b0001100..Reserved
|
|
* 0b0001101..CT_INP12 input is selected
|
|
* 0b0001110..CT_INP13 input is selected
|
|
* 0b0001111..CT_INP14 input is selected
|
|
* 0b0010000..CT_INP15 input is selected
|
|
* 0b0010001..CT_INP16 input is selected
|
|
* 0b0010010..CT_INP17 input is selected
|
|
* 0b0010011..CT_INP18 input is selected
|
|
* 0b0010100..CT_INP19 input is selected
|
|
* 0b0010101..USB0 usb0 start of frame input is selected
|
|
* 0b0010110..AOI0_OUT0 input is selected
|
|
* 0b0010111..AOI0_OUT1 input is selected
|
|
* 0b0011000..AOI0_OUT2 input is selected
|
|
* 0b0011001..AOI0_OUT3 input is selected
|
|
* 0b0011010..ADC0_tcomp[0] input is selected
|
|
* 0b0011011..ADC0_tcomp[1] input is selected
|
|
* 0b0011100..ADC0_tcomp[2] input is selected
|
|
* 0b0011101..ADC0_tcomp[3] input is selected
|
|
* 0b0011110..CMP0_OUT input is selected selected
|
|
* 0b0011111..CMP1_OUT input is selected selected
|
|
* 0b0100000..Reserved
|
|
* 0b0100001..CTimer0_MAT1 input is selected
|
|
* 0b0100010..CTimer0_MAT2 input is selected
|
|
* 0b0100011..CTimer0_MAT3 input is selected
|
|
* 0b0100100..CTimer1_MAT1 input is selected
|
|
* 0b0100101..CTimer1_MAT2 input is selected
|
|
* 0b0100110..CTimer1_MAT3 input is selected
|
|
* 0b0100111..QDC0_CMP_FLAG0 input is selected
|
|
* 0b0101000..QDC0_CMP_FLAG1 input is selected
|
|
* 0b0101001..QDC0_CMP_FLAG2 input is selected
|
|
* 0b0101010..QDC0_CMP_FLAG3 input is selected
|
|
* 0b0101011..QDC0_POS_MATCH0 input is selected
|
|
* 0b0101100..PWM0_SM0_OUT_TRIG0 input is selected
|
|
* 0b0101101..PWM0_SM1_OUT_TRIG0 input is selected
|
|
* 0b0101110..PWM0_SM2_OUT_TRIG0 input is selected
|
|
* 0b0101111..Reserved
|
|
* 0b0110000..LPI2C0 Master End of Packet input is selected
|
|
* 0b0110001..LPI2C0 Slave End of Packet input is selected
|
|
* 0b0110010..Reserved
|
|
* 0b0110011..Reserved
|
|
* 0b0110100..LPSPI0 End of Frame input is selected
|
|
* 0b0110101..LPSPI0 Received Data Word input is selected
|
|
* 0b0110110..LPSPI1 End of Frame input is selected
|
|
* 0b0110111..LPSPI1 Received Data Word input is selected
|
|
* 0b0111000..LPUART0 Received Data Word input is selected
|
|
* 0b0111001..LPUART0 Transmitted Data Word input is selected
|
|
* 0b0111010..LPUART0 Receive Line Idle input is selected
|
|
* 0b0111011..LPUART1 Received Data Word input is selected
|
|
* 0b0111100..LPUART1 Transmitted Data Word input is selected
|
|
* 0b0111101..LPUART1 Receive Line Idle input is selected
|
|
* 0b0111110..LPUART2 Received Data Word input is selected
|
|
* 0b0111111..LPUART2 Transmitted Data Word input is selected
|
|
* 0b1000000..LPUART2 Receive Line Idle input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_TIMER2TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER2TRIG_INP_SHIFT)) & INPUTMUX_TIMER2TRIG_INP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_FREQMEAS_REF_INP_MASK (0x1FU)
|
|
#define INPUTMUX_FREQMEAS_REF_INP_SHIFT (0U)
|
|
/*! INP - Clock source number (binary value) for frequency measure function target clock.
|
|
* 0b00000..Reserved
|
|
* 0b00001..clk_in input is selected
|
|
* 0b00010..FRO_OSC_12M input is selected
|
|
* 0b00011..fro_hf_div input is selected
|
|
* 0b00100..Reserved
|
|
* 0b00101..clk_16k[1] input is selected
|
|
* 0b00110..SLOW_CLK input is selected
|
|
* 0b00111..FREQME_CLK_IN0 input is selected
|
|
* 0b01000..FREQME_CLK_IN1 input is selected
|
|
* 0b01001..AOI0_OUT0 input is selected
|
|
* 0b01010..AOI0_OUT1 input is selected
|
|
* 0b01011..PWM0_SM0_OUT_TRIG0 input is selected
|
|
* 0b01100..PWM0_SM0_OUT_TRIG1 input is selected
|
|
* 0b01101..PWM0_SM1_OUT_TRIG0 input is selected
|
|
* 0b01110..PWM0_SM1_OUT_TRIG1 input is selected
|
|
* 0b01111..PWM0_SM2_OUT_TRIG0 input is selected
|
|
* 0b10000..PWM0_SM2_OUT_TRIG1 input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_FREQMEAS_REF_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_INP_SHIFT)) & INPUTMUX_FREQMEAS_REF_INP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FREQMEAS_TAR - Selection for frequency measurement reference clock */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_FREQMEAS_TAR_INP_MASK (0x1FU)
|
|
#define INPUTMUX_FREQMEAS_TAR_INP_SHIFT (0U)
|
|
/*! INP - Clock source number (binary value) for frequency measure function target clock.
|
|
* 0b00000..Reserved
|
|
* 0b00001..clk_in input is selected
|
|
* 0b00010..FRO_OSC_12M input is selected
|
|
* 0b00011..fro_hf_div input is selected
|
|
* 0b00100..Reserved
|
|
* 0b00101..clk_16k[1] input is selected
|
|
* 0b00110..SLOW_CLK input is selected
|
|
* 0b00111..FREQME_CLK_IN0 input is selected
|
|
* 0b01000..FREQME_CLK_IN1 input is selected
|
|
* 0b01001..AOI0_OUT0 input is selected
|
|
* 0b01010..AOI0_OUT1 input is selected
|
|
* 0b01011..PWM0_SM0_OUT_TRIG0 input is selected
|
|
* 0b01100..PWM0_SM0_OUT_TRIG1 input is selected
|
|
* 0b01101..PWM0_SM1_OUT_TRIG0 input is selected
|
|
* 0b01110..PWM0_SM1_OUT_TRIG1 input is selected
|
|
* 0b01111..PWM0_SM2_OUT_TRIG0 input is selected
|
|
* 0b10000..PWM0_SM2_OUT_TRIG1 input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_FREQMEAS_TAR_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TAR_INP_SHIFT)) & INPUTMUX_FREQMEAS_TAR_INP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CMP0_TRIG - CMP0 input connections */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_CMP0_TRIG_TRIGIN_MASK (0x3FU)
|
|
#define INPUTMUX_CMP0_TRIG_TRIGIN_SHIFT (0U)
|
|
/*! TRIGIN - CMP0 input trigger
|
|
* 0b000000..Reserved
|
|
* 0b000001..ARM_TXEV input is selected
|
|
* 0b000010..AOI0_OUT0 input is selected
|
|
* 0b000011..AOI0_OUT1 input is selected
|
|
* 0b000100..AOI0_OUT2 input is selected
|
|
* 0b000101..AOI0_OUT3 input is selected
|
|
* 0b000110..CMP1_OUT input is selected
|
|
* 0b000111..Reserved
|
|
* 0b001000..CTimer0_MAT0 input is selected
|
|
* 0b001001..CTimer0_MAT2 input is selected
|
|
* 0b001010..CTimer1_MAT0 input is selected
|
|
* 0b001011..CTimer1_MAT2 input is selected
|
|
* 0b001100..CTimer2_MAT0 input is selected
|
|
* 0b001101..CTimer2_MAT2 input is selected
|
|
* 0b001110..LPTMR0 input is selected
|
|
* 0b001111..Reserved
|
|
* 0b010000..QDC0_POS_MATCH0
|
|
* 0b010001..PWM0_SM0_OUT_TRIG0 input is selected
|
|
* 0b010010..PWM0_SM0_OUT_TRIG1 input is selected
|
|
* 0b010011..PWM0_SM1_OUT_TRIG0 input is selected
|
|
* 0b010100..PWM0_SM1_OUT_TRIG1 input is selected
|
|
* 0b010101..PWM0_SM2_OUT_TRIG0 input is selected
|
|
* 0b010110..PWM0_SM2_OUT_TRIG1 input is selected
|
|
* 0b010111..Reserved
|
|
* 0b011000..Reserved
|
|
* 0b011001..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b011010..GPIO1 Pin Event Trig 0 input is selected
|
|
* 0b011011..GPIO2 Pin Event Trig 0 input is selected
|
|
* 0b011100..GPIO3 Pin Event Trig 0 input is selected
|
|
* 0b011101..Reserved
|
|
* 0b011110..WUU input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_CMP0_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CMP0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_CMP0_TRIG_TRIGIN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ADC0_TRIGM_ADC0_TRIG - ADC Trigger input connections */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_MASK (0x3FU)
|
|
#define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_SHIFT (0U)
|
|
/*! TRIGIN - ADC0 trigger inputs
|
|
* 0b000000..Reserved
|
|
* 0b000001..ARM_TXEV input is selected
|
|
* 0b000010..AOI0_OUT0 input is selected
|
|
* 0b000011..AOI0_OUT1 input is selected
|
|
* 0b000100..AOI0_OUT2 input is selected
|
|
* 0b000101..AOI0_OUT3 input is selected
|
|
* 0b000110..CMP0_OUT input is selected
|
|
* 0b000111..CMP1_OUT input is selected
|
|
* 0b001000..Reserved
|
|
* 0b001001..CTimer0_MAT0 input is selected
|
|
* 0b001010..CTimer0_MAT1 input is selected
|
|
* 0b001011..CTimer1_MAT0 input is selected
|
|
* 0b001100..CTimer1_MAT1 input is selected
|
|
* 0b001101..CTimer2_MAT0 input is selected
|
|
* 0b001110..CTimer2_MAT1 input is selected
|
|
* 0b001111..LPTMR0 input is selected
|
|
* 0b010000..Reserved
|
|
* 0b010001..QDC0_POS_MATCH0 input is selected
|
|
* 0b010010..PWM0_SM0_OUT_TRIG0 input is selected
|
|
* 0b010011..PWM0_SM0_OUT_TRIG1 input is selected
|
|
* 0b010100..PWM0_SM1_OUT_TRIG0 input is selected
|
|
* 0b010101..PWM0_SM1_OUT_TRIG1 input is selected
|
|
* 0b010110..PWM0_SM2_OUT_TRIG0 input is selected
|
|
* 0b010111..PWM0_SM2_OUT_TRIG1 input is selected
|
|
* 0b011000..Reserved
|
|
* 0b011001..Reserved
|
|
* 0b011010..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b011011..GPIO1 Pin Event Trig 0 input is selected
|
|
* 0b011100..GPIO2 Pin Event Trig 0 input is selected
|
|
* 0b011101..GPIO3 Pin Event Trig 0 input is selected
|
|
* 0b011110..Reserved
|
|
* 0b011111..WUU
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of INPUTMUX_ADC0_TRIGM_ADC0_TRIG */
|
|
#define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_COUNT (4U)
|
|
|
|
/*! @name QDC0_TRIG - QDC0 Trigger Input Connections */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_QDC0_TRIG_INP_MASK (0x3FU)
|
|
#define INPUTMUX_QDC0_TRIG_INP_SHIFT (0U)
|
|
/*! INP - QDC0 input connections
|
|
* 0b000000..Reserved
|
|
* 0b000001..ARM_TXEV input is selected
|
|
* 0b000010..AOI0_OUT0 input is selected
|
|
* 0b000011..AOI0_OUT1 input is selected
|
|
* 0b000100..AOI0_OUT2 input is selected
|
|
* 0b000101..AOI0_OUT3 input is selected
|
|
* 0b000110..CMP0_OUT input is selected
|
|
* 0b000111..CMP1_OUT input is selected
|
|
* 0b001000..Reserved
|
|
* 0b001001..CTimer0_MAT2 input is selected
|
|
* 0b001010..CTimer0_MAT3 input is selected
|
|
* 0b001011..CTimer1_MAT2 input is selected
|
|
* 0b001100..CTimer1_MAT3 input is selected
|
|
* 0b001101..CTimer2_MAT2 input is selected
|
|
* 0b001110..CTimer2_MAT3 input is selected
|
|
* 0b001111..QDC0_POS_MATCH0 input is selected
|
|
* 0b010000..PWM0_SM0_OUT_TRIG0 input is selected
|
|
* 0b010001..PWM0_SM0_OUT_TRIG1 input is selected
|
|
* 0b010010..PWM0_SM1_OUT_TRIG0 input is selected
|
|
* 0b010011..PWM0_SM1_OUT_TRIG1 input is selected
|
|
* 0b010100..PWM0_SM2_OUT_TRIG0 input is selected
|
|
* 0b010101..PWM0_SM2_OUT_TRIG1 input is selected
|
|
* 0b010110..Reserved
|
|
* 0b010111..Reserved
|
|
* 0b011000..TRIG_IN0 input is selected
|
|
* 0b011001..TRIG_IN1 input is selected
|
|
* 0b011010..TRIG_IN2 input is selected
|
|
* 0b011011..TRIG_IN3 input is selected
|
|
* 0b011100..TRIG_IN4 input is selected
|
|
* 0b011101..TRIG_IN5 input is selected
|
|
* 0b011110..TRIG_IN6 input is selected
|
|
* 0b011111..TRIG_IN7 input is selected
|
|
* 0b100000..TRIG_IN8 input is selected
|
|
* 0b100001..TRIG_IN9 input is selected
|
|
* 0b100010..TRIG_IN10 input is selected
|
|
* 0b100011..TRIG_IN11 input is selected
|
|
* 0b100100..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b100101..GPIO1 Pin Event Trig 0 input is selected
|
|
* 0b100110..GPIO2 Pin Event Trig 0 input is selected
|
|
* 0b100111..GPIO3 Pin Event Trig 0 input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_QDC0_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_TRIG_INP_SHIFT)) & INPUTMUX_QDC0_TRIG_INP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name QDC0_HOME - QDC0 Trigger Input Connections */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_QDC0_HOME_INP_MASK (0x3FU)
|
|
#define INPUTMUX_QDC0_HOME_INP_SHIFT (0U)
|
|
/*! INP - QDC0 input connections
|
|
* 0b000000..Reserved
|
|
* 0b000001..ARM_TXEV input is selected
|
|
* 0b000010..AOI0_OUT0 input is selected
|
|
* 0b000011..AOI0_OUT1 input is selected
|
|
* 0b000100..AOI0_OUT2 input is selected
|
|
* 0b000101..AOI0_OUT3 input is selected
|
|
* 0b000110..CMP0_OUT input is selected
|
|
* 0b000111..CMP1_OUT input is selected
|
|
* 0b001000..Reserved
|
|
* 0b001001..CTimer0_MAT2 input is selected
|
|
* 0b001010..CTimer0_MAT3 input is selected
|
|
* 0b001011..CTimer1_MAT2 input is selected
|
|
* 0b001100..CTimer1_MAT3 input is selected
|
|
* 0b001101..CTimer2_MAT2 input is selected
|
|
* 0b001110..CTimer2_MAT3 input is selected
|
|
* 0b001111..QDC0_POS_MATCH0 input is selected
|
|
* 0b010000..PWM0_SM0_OUT_TRIG0 input is selected
|
|
* 0b010001..PWM0_SM0_OUT_TRIG1 input is selected
|
|
* 0b010010..PWM0_SM1_OUT_TRIG0 input is selected
|
|
* 0b010011..PWM0_SM1_OUT_TRIG1 input is selected
|
|
* 0b010100..PWM0_SM2_OUT_TRIG0 input is selected
|
|
* 0b010101..PWM0_SM2_OUT_TRIG1 input is selected
|
|
* 0b010110..Reserved
|
|
* 0b010111..Reserved
|
|
* 0b011000..TRIG_IN0 input is selected
|
|
* 0b011001..TRIG_IN1 input is selected
|
|
* 0b011010..TRIG_IN2 input is selected
|
|
* 0b011011..TRIG_IN3 input is selected
|
|
* 0b011100..TRIG_IN4 input is selected
|
|
* 0b011101..TRIG_IN5 input is selected
|
|
* 0b011110..TRIG_IN6 input is selected
|
|
* 0b011111..TRIG_IN7 input is selected
|
|
* 0b100000..TRIG_IN8 input is selected
|
|
* 0b100001..TRIG_IN9 input is selected
|
|
* 0b100010..TRIG_IN10 input is selected
|
|
* 0b100011..TRIG_IN11 input is selected
|
|
* 0b100100..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b100101..GPIO1 Pin Event Trig 0 input is selected
|
|
* 0b100110..GPIO2 Pin Event Trig 0 input is selected
|
|
* 0b100111..GPIO3 Pin Event Trig 0 input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_QDC0_HOME_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_HOME_INP_SHIFT)) & INPUTMUX_QDC0_HOME_INP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name QDC0_INDEX - QDC0 Trigger Input Connections */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_QDC0_INDEX_INP_MASK (0x3FU)
|
|
#define INPUTMUX_QDC0_INDEX_INP_SHIFT (0U)
|
|
/*! INP - QDC0 input connections
|
|
* 0b000000..Reserved
|
|
* 0b000001..ARM_TXEV input is selected
|
|
* 0b000010..AOI0_OUT0 input is selected
|
|
* 0b000011..AOI0_OUT1 input is selected
|
|
* 0b000100..AOI0_OUT2 input is selected
|
|
* 0b000101..AOI0_OUT3 input is selected
|
|
* 0b000110..CMP0_OUT input is selected
|
|
* 0b000111..CMP1_OUT input is selected
|
|
* 0b001000..Reserved
|
|
* 0b001001..CTimer0_MAT2 input is selected
|
|
* 0b001010..CTimer0_MAT3 input is selected
|
|
* 0b001011..CTimer1_MAT2 input is selected
|
|
* 0b001100..CTimer1_MAT3 input is selected
|
|
* 0b001101..CTimer2_MAT2 input is selected
|
|
* 0b001110..CTimer2_MAT3 input is selected
|
|
* 0b001111..QDC0_POS_MATCH0 input is selected
|
|
* 0b010000..PWM0_SM0_OUT_TRIG0 input is selected
|
|
* 0b010001..PWM0_SM0_OUT_TRIG1 input is selected
|
|
* 0b010010..PWM0_SM1_OUT_TRIG0 input is selected
|
|
* 0b010011..PWM0_SM1_OUT_TRIG1 input is selected
|
|
* 0b010100..PWM0_SM2_OUT_TRIG0 input is selected
|
|
* 0b010101..PWM0_SM2_OUT_TRIG1 input is selected
|
|
* 0b010110..Reserved
|
|
* 0b010111..Reserved
|
|
* 0b011000..TRIG_IN0 input is selected
|
|
* 0b011001..TRIG_IN1 input is selected
|
|
* 0b011010..TRIG_IN2 input is selected
|
|
* 0b011011..TRIG_IN3 input is selected
|
|
* 0b011100..TRIG_IN4 input is selected
|
|
* 0b011101..TRIG_IN5 input is selected
|
|
* 0b011110..TRIG_IN6 input is selected
|
|
* 0b011111..TRIG_IN7 input is selected
|
|
* 0b100000..TRIG_IN8 input is selected
|
|
* 0b100001..TRIG_IN9 input is selected
|
|
* 0b100010..TRIG_IN10 input is selected
|
|
* 0b100011..TRIG_IN11 input is selected
|
|
* 0b100100..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b100101..GPIO1 Pin Event Trig 0 input is selected
|
|
* 0b100110..GPIO2 Pin Event Trig 0 input is selected
|
|
* 0b100111..GPIO3 Pin Event Trig 0 input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_QDC0_INDEX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_INDEX_INP_SHIFT)) & INPUTMUX_QDC0_INDEX_INP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name QDC0_PHASEB - QDC0 Trigger Input Connections */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_QDC0_PHASEB_INP_MASK (0x3FU)
|
|
#define INPUTMUX_QDC0_PHASEB_INP_SHIFT (0U)
|
|
/*! INP - QDC0 input connections
|
|
* 0b000000..Reserved
|
|
* 0b000001..ARM_TXEV input is selected
|
|
* 0b000010..AOI0_OUT0 input is selected
|
|
* 0b000011..AOI0_OUT1 input is selected
|
|
* 0b000100..AOI0_OUT2 input is selected
|
|
* 0b000101..AOI0_OUT3 input is selected
|
|
* 0b000110..CMP0_OUT input is selected
|
|
* 0b000111..CMP1_OUT input is selected
|
|
* 0b001000..Reserved
|
|
* 0b001001..CTimer0_MAT2 input is selected
|
|
* 0b001010..CTimer0_MAT3 input is selected
|
|
* 0b001011..CTimer1_MAT2 input is selected
|
|
* 0b001100..CTimer1_MAT3 input is selected
|
|
* 0b001101..CTimer2_MAT2 input is selected
|
|
* 0b001110..CTimer2_MAT3 input is selected
|
|
* 0b001111..QDC0_POS_MATCH0 input is selected
|
|
* 0b010000..PWM0_SM0_OUT_TRIG0 input is selected
|
|
* 0b010001..PWM0_SM0_OUT_TRIG1 input is selected
|
|
* 0b010010..PWM0_SM1_OUT_TRIG0 input is selected
|
|
* 0b010011..PWM0_SM1_OUT_TRIG1 input is selected
|
|
* 0b010100..PWM0_SM2_OUT_TRIG0 input is selected
|
|
* 0b010101..PWM0_SM2_OUT_TRIG1 input is selected
|
|
* 0b010110..Reserved
|
|
* 0b010111..Reserved
|
|
* 0b011000..TRIG_IN0 input is selected
|
|
* 0b011001..TRIG_IN1 input is selected
|
|
* 0b011010..TRIG_IN2 input is selected
|
|
* 0b011011..TRIG_IN3 input is selected
|
|
* 0b011100..TRIG_IN4 input is selected
|
|
* 0b011101..TRIG_IN5 input is selected
|
|
* 0b011110..TRIG_IN6 input is selected
|
|
* 0b011111..TRIG_IN7 input is selected
|
|
* 0b100000..TRIG_IN8 input is selected
|
|
* 0b100001..TRIG_IN9 input is selected
|
|
* 0b100010..TRIG_IN10 input is selected
|
|
* 0b100011..TRIG_IN11 input is selected
|
|
* 0b100100..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b100101..GPIO1 Pin Event Trig 0 input is selected
|
|
* 0b100110..GPIO2 Pin Event Trig 0 input is selected
|
|
* 0b100111..GPIO3 Pin Event Trig 0 input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_QDC0_PHASEB_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_PHASEB_INP_SHIFT)) & INPUTMUX_QDC0_PHASEB_INP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name QDC0_PHASEA - QDC0 Trigger Input Connections */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_QDC0_PHASEA_INP_MASK (0x3FU)
|
|
#define INPUTMUX_QDC0_PHASEA_INP_SHIFT (0U)
|
|
/*! INP - QDC0 input connections
|
|
* 0b000000..Reserved
|
|
* 0b000001..ARM_TXEV input is selected
|
|
* 0b000010..AOI0_OUT0 input is selected
|
|
* 0b000011..AOI0_OUT1 input is selected
|
|
* 0b000100..AOI0_OUT2 input is selected
|
|
* 0b000101..AOI0_OUT3 input is selected
|
|
* 0b000110..CMP0_OUT input is selected
|
|
* 0b000111..CMP1_OUT input is selected
|
|
* 0b001000..Reserved
|
|
* 0b001001..CTimer0_MAT2 input is selected
|
|
* 0b001010..CTimer0_MAT3 input is selected
|
|
* 0b001011..CTimer1_MAT2 input is selected
|
|
* 0b001100..CTimer1_MAT3 input is selected
|
|
* 0b001101..CTimer2_MAT2 input is selected
|
|
* 0b001110..CTimer2_MAT3 input is selected
|
|
* 0b001111..QDC0_POS_MATCH0 input is selected
|
|
* 0b010000..PWM0_SM0_OUT_TRIG0 input is selected
|
|
* 0b010001..PWM0_SM0_OUT_TRIG1 input is selected
|
|
* 0b010010..PWM0_SM1_OUT_TRIG0 input is selected
|
|
* 0b010011..PWM0_SM1_OUT_TRIG1 input is selected
|
|
* 0b010100..PWM0_SM2_OUT_TRIG0 input is selected
|
|
* 0b010101..PWM0_SM2_OUT_TRIG1 input is selected
|
|
* 0b010110..Reserved
|
|
* 0b010111..Reserved
|
|
* 0b011000..TRIG_IN0 input is selected
|
|
* 0b011001..TRIG_IN1 input is selected
|
|
* 0b011010..TRIG_IN2 input is selected
|
|
* 0b011011..TRIG_IN3 input is selected
|
|
* 0b011100..TRIG_IN4 input is selected
|
|
* 0b011101..TRIG_IN5 input is selected
|
|
* 0b011110..TRIG_IN6 input is selected
|
|
* 0b011111..TRIG_IN7 input is selected
|
|
* 0b100000..TRIG_IN8 input is selected
|
|
* 0b100001..TRIG_IN9 input is selected
|
|
* 0b100010..TRIG_IN10 input is selected
|
|
* 0b100011..TRIG_IN11 input is selected
|
|
* 0b100100..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b100101..GPIO1 Pin Event Trig 0 input is selected
|
|
* 0b100110..GPIO2 Pin Event Trig 0 input is selected
|
|
* 0b100111..GPIO3 Pin Event Trig 0 input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_QDC0_PHASEA_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_PHASEA_INP_SHIFT)) & INPUTMUX_QDC0_PHASEA_INP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name QDC0_ICAP1 - QDC0 Trigger Input Connections */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_QDC0_ICAP1_INP_MASK (0x3FU)
|
|
#define INPUTMUX_QDC0_ICAP1_INP_SHIFT (0U)
|
|
/*! INP - QDC0 input connections
|
|
* 0b000000..Reserved
|
|
* 0b000001..ARM_TXEV input is selected
|
|
* 0b000010..AOI0_OUT0 input is selected
|
|
* 0b000011..AOI0_OUT1 input is selected
|
|
* 0b000100..AOI0_OUT2 input is selected
|
|
* 0b000101..AOI0_OUT3 input is selected
|
|
* 0b000110..CMP0_OUT input is selected
|
|
* 0b000111..CMP1_OUT input is selected
|
|
* 0b001000..Reserved
|
|
* 0b001001..CTimer0_MAT2 input is selected
|
|
* 0b001010..CTimer0_MAT3 input is selected
|
|
* 0b001011..CTimer1_MAT2 input is selected
|
|
* 0b001100..CTimer1_MAT3 input is selected
|
|
* 0b001101..CTimer2_MAT2 input is selected
|
|
* 0b001110..CTimer2_MAT3 input is selected
|
|
* 0b001111..QDC0_POS_MATCH0 input is selected
|
|
* 0b010000..PWM0_SM0_OUT_TRIG0 input is selected
|
|
* 0b010001..PWM0_SM0_OUT_TRIG1 input is selected
|
|
* 0b010010..PWM0_SM1_OUT_TRIG0 input is selected
|
|
* 0b010011..PWM0_SM1_OUT_TRIG1 input is selected
|
|
* 0b010100..PWM0_SM2_OUT_TRIG0 input is selected
|
|
* 0b010101..PWM0_SM2_OUT_TRIG1 input is selected
|
|
* 0b010110..Reserved
|
|
* 0b010111..Reserved
|
|
* 0b011000..TRIG_IN0 input is selected
|
|
* 0b011001..TRIG_IN1 input is selected
|
|
* 0b011010..TRIG_IN2 input is selected
|
|
* 0b011011..TRIG_IN3 input is selected
|
|
* 0b011100..TRIG_IN4 input is selected
|
|
* 0b011101..TRIG_IN5 input is selected
|
|
* 0b011110..TRIG_IN6 input is selected
|
|
* 0b011111..TRIG_IN7 input is selected
|
|
* 0b100000..TRIG_IN8 input is selected
|
|
* 0b100001..TRIG_IN9 input is selected
|
|
* 0b100010..TRIG_IN10 input is selected
|
|
* 0b100011..TRIG_IN11 input is selected
|
|
* 0b100100..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b100101..GPIO1 Pin Event Trig 0 input is selected
|
|
* 0b100110..GPIO2 Pin Event Trig 0 input is selected
|
|
* 0b100111..GPIO3 Pin Event Trig 0 input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_QDC0_ICAP1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_ICAP1_INP_SHIFT)) & INPUTMUX_QDC0_ICAP1_INP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name QDC0_ICAP2 - QDC0 Trigger Input Connections */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_QDC0_ICAP2_INP_MASK (0x3FU)
|
|
#define INPUTMUX_QDC0_ICAP2_INP_SHIFT (0U)
|
|
/*! INP - QDC0 input connections
|
|
* 0b000000..Reserved
|
|
* 0b000001..ARM_TXEV input is selected
|
|
* 0b000010..AOI0_OUT0 input is selected
|
|
* 0b000011..AOI0_OUT1 input is selected
|
|
* 0b000100..AOI0_OUT2 input is selected
|
|
* 0b000101..AOI0_OUT3 input is selected
|
|
* 0b000110..CMP0_OUT input is selected
|
|
* 0b000111..CMP1_OUT input is selected
|
|
* 0b001000..Reserved
|
|
* 0b001001..CTimer0_MAT2 input is selected
|
|
* 0b001010..CTimer0_MAT3 input is selected
|
|
* 0b001011..CTimer1_MAT2 input is selected
|
|
* 0b001100..CTimer1_MAT3 input is selected
|
|
* 0b001101..CTimer2_MAT2 input is selected
|
|
* 0b001110..CTimer2_MAT3 input is selected
|
|
* 0b001111..QDC0_POS_MATCH0 input is selected
|
|
* 0b010000..PWM0_SM0_OUT_TRIG0 input is selected
|
|
* 0b010001..PWM0_SM0_OUT_TRIG1 input is selected
|
|
* 0b010010..PWM0_SM1_OUT_TRIG0 input is selected
|
|
* 0b010011..PWM0_SM1_OUT_TRIG1 input is selected
|
|
* 0b010100..PWM0_SM2_OUT_TRIG0 input is selected
|
|
* 0b010101..PWM0_SM2_OUT_TRIG1 input is selected
|
|
* 0b010110..Reserved
|
|
* 0b010111..Reserved
|
|
* 0b011000..TRIG_IN0 input is selected
|
|
* 0b011001..TRIG_IN1 input is selected
|
|
* 0b011010..TRIG_IN2 input is selected
|
|
* 0b011011..TRIG_IN3 input is selected
|
|
* 0b011100..TRIG_IN4 input is selected
|
|
* 0b011101..TRIG_IN5 input is selected
|
|
* 0b011110..TRIG_IN6 input is selected
|
|
* 0b011111..TRIG_IN7 input is selected
|
|
* 0b100000..TRIG_IN8 input is selected
|
|
* 0b100001..TRIG_IN9 input is selected
|
|
* 0b100010..TRIG_IN10 input is selected
|
|
* 0b100011..TRIG_IN11 input is selected
|
|
* 0b100100..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b100101..GPIO1 Pin Event Trig 0 input is selected
|
|
* 0b100110..GPIO2 Pin Event Trig 0 input is selected
|
|
* 0b100111..GPIO3 Pin Event Trig 0 input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_QDC0_ICAP2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_ICAP2_INP_SHIFT)) & INPUTMUX_QDC0_ICAP2_INP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name QDC0_ICAP3 - QDC0 Trigger Input Connections */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_QDC0_ICAP3_INP_MASK (0x3FU)
|
|
#define INPUTMUX_QDC0_ICAP3_INP_SHIFT (0U)
|
|
/*! INP - QDC0 input connections
|
|
* 0b000000..Reserved
|
|
* 0b000001..ARM_TXEV input is selected
|
|
* 0b000010..AOI0_OUT0 input is selected
|
|
* 0b000011..AOI0_OUT1 input is selected
|
|
* 0b000100..AOI0_OUT2 input is selected
|
|
* 0b000101..AOI0_OUT3 input is selected
|
|
* 0b000110..CMP0_OUT input is selected
|
|
* 0b000111..CMP1_OUT input is selected
|
|
* 0b001000..Reserved
|
|
* 0b001001..CTimer0_MAT2 input is selected
|
|
* 0b001010..CTimer0_MAT3 input is selected
|
|
* 0b001011..CTimer1_MAT2 input is selected
|
|
* 0b001100..CTimer1_MAT3 input is selected
|
|
* 0b001101..CTimer2_MAT2 input is selected
|
|
* 0b001110..CTimer2_MAT3 input is selected
|
|
* 0b001111..QDC0_POS_MATCH0 input is selected
|
|
* 0b010000..PWM0_SM0_OUT_TRIG0 input is selected
|
|
* 0b010001..PWM0_SM0_OUT_TRIG1 input is selected
|
|
* 0b010010..PWM0_SM1_OUT_TRIG0 input is selected
|
|
* 0b010011..PWM0_SM1_OUT_TRIG1 input is selected
|
|
* 0b010100..PWM0_SM2_OUT_TRIG0 input is selected
|
|
* 0b010101..PWM0_SM2_OUT_TRIG1 input is selected
|
|
* 0b010110..Reserved
|
|
* 0b010111..Reserved
|
|
* 0b011000..TRIG_IN0 input is selected
|
|
* 0b011001..TRIG_IN1 input is selected
|
|
* 0b011010..TRIG_IN2 input is selected
|
|
* 0b011011..TRIG_IN3 input is selected
|
|
* 0b011100..TRIG_IN4 input is selected
|
|
* 0b011101..TRIG_IN5 input is selected
|
|
* 0b011110..TRIG_IN6 input is selected
|
|
* 0b011111..TRIG_IN7 input is selected
|
|
* 0b100000..TRIG_IN8 input is selected
|
|
* 0b100001..TRIG_IN9 input is selected
|
|
* 0b100010..TRIG_IN10 input is selected
|
|
* 0b100011..TRIG_IN11 input is selected
|
|
* 0b100100..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b100101..GPIO1 Pin Event Trig 0 input is selected
|
|
* 0b100110..GPIO2 Pin Event Trig 0 input is selected
|
|
* 0b100111..GPIO3 Pin Event Trig 0 input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_QDC0_ICAP3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_ICAP3_INP_SHIFT)) & INPUTMUX_QDC0_ICAP3_INP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FLEXPWM0_SM0_EXTA0 - PWM0 input trigger connections */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_FLEXPWM0_SM0_EXTA0_TRIGIN_MASK (0x3FU)
|
|
#define INPUTMUX_FLEXPWM0_SM0_EXTA0_TRIGIN_SHIFT (0U)
|
|
/*! TRIGIN - Trigger input connections for PWM0
|
|
* 0b000000..Reserved
|
|
* 0b000001..ARM_TXEV input is selected
|
|
* 0b000010..AOI0_OUT0 input is selected
|
|
* 0b000011..AOI0_OUT1 input is selected
|
|
* 0b000100..AOI0_OUT2 input is selected
|
|
* 0b000101..AOI0_OUT3 input is selected
|
|
* 0b000110..CMP0_OUT input is selected
|
|
* 0b000111..CMP1_OUT input is selected
|
|
* 0b001000..Reserved
|
|
* 0b001001..CTimer0_MAT2 input is selected
|
|
* 0b001010..CTimer0_MAT3 input is selected
|
|
* 0b001011..CTimer1_MAT2 input is selected
|
|
* 0b001100..CTimer1_MAT3 input is selected
|
|
* 0b001101..CTimer2_MAT2 input is selected
|
|
* 0b001110..CTimer2_MAT3 input is selected
|
|
* 0b001111..QDC0_CMP_FLAG0 input is selected
|
|
* 0b010000..QDC0_CMP_FLAG1 input is selected
|
|
* 0b010001..QDC0_CMP_FLAG2 input is selected
|
|
* 0b010010..QDC0_CMP_FLAG3 input is selected
|
|
* 0b010011..QDC0_POS_MATCH0 input is selected
|
|
* 0b010100..TRIG_IN0 input is selected
|
|
* 0b010101..TRIG_IN1 input is selected
|
|
* 0b010110..TRIG_IN2 input is selected
|
|
* 0b010111..TRIG_IN3 input is selected
|
|
* 0b011000..TRIG_IN4 input is selected
|
|
* 0b011001..TRIG_IN5 input is selected
|
|
* 0b011010..TRIG_IN6 input is selected
|
|
* 0b011011..TRIG_IN7 input is selected
|
|
* 0b011100..TRIG_IN8 input is selected
|
|
* 0b011101..TRIG_IN9 input is selected
|
|
* 0b011110..TRIG_IN10 input is selected
|
|
* 0b011111..TRIG_IN11 input is selected
|
|
* 0b100000..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b100001..GPIO1 Pin Event Trig 0 input is selected
|
|
* 0b100010..GPIO2 Pin Event Trig 0 input is selected
|
|
* 0b100011..GPIO3 Pin Event Trig 0 input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_FLEXPWM0_SM0_EXTA0_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_SM0_EXTA0_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_SM0_EXTA0_TRIGIN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FLEXPWM0_SM0_EXTSYNC0 - PWM0 input trigger connections */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_FLEXPWM0_SM0_EXTSYNC0_TRIGIN_MASK (0x3FU)
|
|
#define INPUTMUX_FLEXPWM0_SM0_EXTSYNC0_TRIGIN_SHIFT (0U)
|
|
/*! TRIGIN - Trigger input connections for PWM0
|
|
* 0b000000..Reserved
|
|
* 0b000001..ARM_TXEV input is selected
|
|
* 0b000010..AOI0_OUT0 input is selected
|
|
* 0b000011..AOI0_OUT1 input is selected
|
|
* 0b000100..AOI0_OUT2 input is selected
|
|
* 0b000101..AOI0_OUT3 input is selected
|
|
* 0b000110..CMP0_OUT input is selected
|
|
* 0b000111..CMP1_OUT input is selected
|
|
* 0b001000..Reserved
|
|
* 0b001001..CTimer0_MAT2 input is selected
|
|
* 0b001010..CTimer0_MAT3 input is selected
|
|
* 0b001011..CTimer1_MAT2 input is selected
|
|
* 0b001100..CTimer1_MAT3 input is selected
|
|
* 0b001101..CTimer2_MAT2 input is selected
|
|
* 0b001110..CTimer2_MAT3 input is selected
|
|
* 0b001111..QDC0_CMP_FLAG0 input is selected
|
|
* 0b010000..QDC0_CMP_FLAG1 input is selected
|
|
* 0b010001..QDC0_CMP_FLAG2 input is selected
|
|
* 0b010010..QDC0_CMP_FLAG3 input is selected
|
|
* 0b010011..QDC0_POS_MATCH0 input is selected
|
|
* 0b010100..TRIG_IN0 input is selected
|
|
* 0b010101..TRIG_IN1 input is selected
|
|
* 0b010110..TRIG_IN2 input is selected
|
|
* 0b010111..TRIG_IN3 input is selected
|
|
* 0b011000..TRIG_IN4 input is selected
|
|
* 0b011001..TRIG_IN5 input is selected
|
|
* 0b011010..TRIG_IN6 input is selected
|
|
* 0b011011..TRIG_IN7 input is selected
|
|
* 0b011100..TRIG_IN8 input is selected
|
|
* 0b011101..TRIG_IN9 input is selected
|
|
* 0b011110..TRIG_IN10 input is selected
|
|
* 0b011111..TRIG_IN11 input is selected
|
|
* 0b100000..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b100001..GPIO1 Pin Event Trig 0 input is selected
|
|
* 0b100010..GPIO2 Pin Event Trig 0 input is selected
|
|
* 0b100011..GPIO3 Pin Event Trig 0 input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_FLEXPWM0_SM0_EXTSYNC0_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_SM0_EXTSYNC0_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_SM0_EXTSYNC0_TRIGIN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FLEXPWM0_SM1_EXTA1 - PWM0 input trigger connections */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_FLEXPWM0_SM1_EXTA1_TRIGIN_MASK (0x3FU)
|
|
#define INPUTMUX_FLEXPWM0_SM1_EXTA1_TRIGIN_SHIFT (0U)
|
|
/*! TRIGIN - Trigger input connections for PWM0
|
|
* 0b000000..Reserved
|
|
* 0b000001..ARM_TXEV input is selected
|
|
* 0b000010..AOI0_OUT0 input is selected
|
|
* 0b000011..AOI0_OUT1 input is selected
|
|
* 0b000100..AOI0_OUT2 input is selected
|
|
* 0b000101..AOI0_OUT3 input is selected
|
|
* 0b000110..CMP0_OUT input is selected
|
|
* 0b000111..CMP1_OUT input is selected
|
|
* 0b001000..Reserved
|
|
* 0b001001..CTimer0_MAT2 input is selected
|
|
* 0b001010..CTimer0_MAT3 input is selected
|
|
* 0b001011..CTimer1_MAT2 input is selected
|
|
* 0b001100..CTimer1_MAT3 input is selected
|
|
* 0b001101..CTimer2_MAT2 input is selected
|
|
* 0b001110..CTimer2_MAT3 input is selected
|
|
* 0b001111..QDC0_CMP_FLAG0 input is selected
|
|
* 0b010000..QDC0_CMP_FLAG1 input is selected
|
|
* 0b010001..QDC0_CMP_FLAG2 input is selected
|
|
* 0b010010..QDC0_CMP_FLAG3 input is selected
|
|
* 0b010011..QDC0_POS_MATCH0 input is selected
|
|
* 0b010100..TRIG_IN0 input is selected
|
|
* 0b010101..TRIG_IN1 input is selected
|
|
* 0b010110..TRIG_IN2 input is selected
|
|
* 0b010111..TRIG_IN3 input is selected
|
|
* 0b011000..TRIG_IN4 input is selected
|
|
* 0b011001..TRIG_IN5 input is selected
|
|
* 0b011010..TRIG_IN6 input is selected
|
|
* 0b011011..TRIG_IN7 input is selected
|
|
* 0b011100..TRIG_IN8 input is selected
|
|
* 0b011101..TRIG_IN9 input is selected
|
|
* 0b011110..TRIG_IN10 input is selected
|
|
* 0b011111..TRIG_IN11 input is selected
|
|
* 0b100000..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b100001..GPIO1 Pin Event Trig 0 input is selected
|
|
* 0b100010..GPIO2 Pin Event Trig 0 input is selected
|
|
* 0b100011..GPIO3 Pin Event Trig 0 input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_FLEXPWM0_SM1_EXTA1_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_SM1_EXTA1_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_SM1_EXTA1_TRIGIN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FLEXPWM0_SM1_EXTSYNC1 - PWM0 input trigger connections */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_FLEXPWM0_SM1_EXTSYNC1_TRIGIN_MASK (0x3FU)
|
|
#define INPUTMUX_FLEXPWM0_SM1_EXTSYNC1_TRIGIN_SHIFT (0U)
|
|
/*! TRIGIN - Trigger input connections for PWM0
|
|
* 0b000000..Reserved
|
|
* 0b000001..ARM_TXEV input is selected
|
|
* 0b000010..AOI0_OUT0 input is selected
|
|
* 0b000011..AOI0_OUT1 input is selected
|
|
* 0b000100..AOI0_OUT2 input is selected
|
|
* 0b000101..AOI0_OUT3 input is selected
|
|
* 0b000110..CMP0_OUT input is selected
|
|
* 0b000111..CMP1_OUT input is selected
|
|
* 0b001000..Reserved
|
|
* 0b001001..CTimer0_MAT2 input is selected
|
|
* 0b001010..CTimer0_MAT3 input is selected
|
|
* 0b001011..CTimer1_MAT2 input is selected
|
|
* 0b001100..CTimer1_MAT3 input is selected
|
|
* 0b001101..CTimer2_MAT2 input is selected
|
|
* 0b001110..CTimer2_MAT3 input is selected
|
|
* 0b001111..QDC0_CMP_FLAG0 input is selected
|
|
* 0b010000..QDC0_CMP_FLAG1 input is selected
|
|
* 0b010001..QDC0_CMP_FLAG2 input is selected
|
|
* 0b010010..QDC0_CMP_FLAG3 input is selected
|
|
* 0b010011..QDC0_POS_MATCH0 input is selected
|
|
* 0b010100..TRIG_IN0 input is selected
|
|
* 0b010101..TRIG_IN1 input is selected
|
|
* 0b010110..TRIG_IN2 input is selected
|
|
* 0b010111..TRIG_IN3 input is selected
|
|
* 0b011000..TRIG_IN4 input is selected
|
|
* 0b011001..TRIG_IN5 input is selected
|
|
* 0b011010..TRIG_IN6 input is selected
|
|
* 0b011011..TRIG_IN7 input is selected
|
|
* 0b011100..TRIG_IN8 input is selected
|
|
* 0b011101..TRIG_IN9 input is selected
|
|
* 0b011110..TRIG_IN10 input is selected
|
|
* 0b011111..TRIG_IN11 input is selected
|
|
* 0b100000..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b100001..GPIO1 Pin Event Trig 0 input is selected
|
|
* 0b100010..GPIO2 Pin Event Trig 0 input is selected
|
|
* 0b100011..GPIO3 Pin Event Trig 0 input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_FLEXPWM0_SM1_EXTSYNC1_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_SM1_EXTSYNC1_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_SM1_EXTSYNC1_TRIGIN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FLEXPWM0_SM2_EXTA2 - PWM0 input trigger connections */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_FLEXPWM0_SM2_EXTA2_TRIGIN_MASK (0x3FU)
|
|
#define INPUTMUX_FLEXPWM0_SM2_EXTA2_TRIGIN_SHIFT (0U)
|
|
/*! TRIGIN - Trigger input connections for PWM0
|
|
* 0b000000..Reserved
|
|
* 0b000001..ARM_TXEV input is selected
|
|
* 0b000010..AOI0_OUT0 input is selected
|
|
* 0b000011..AOI0_OUT1 input is selected
|
|
* 0b000100..AOI0_OUT2 input is selected
|
|
* 0b000101..AOI0_OUT3 input is selected
|
|
* 0b000110..CMP0_OUT input is selected
|
|
* 0b000111..CMP1_OUT input is selected
|
|
* 0b001000..Reserved
|
|
* 0b001001..CTimer0_MAT2 input is selected
|
|
* 0b001010..CTimer0_MAT3 input is selected
|
|
* 0b001011..CTimer1_MAT2 input is selected
|
|
* 0b001100..CTimer1_MAT3 input is selected
|
|
* 0b001101..CTimer2_MAT2 input is selected
|
|
* 0b001110..CTimer2_MAT3 input is selected
|
|
* 0b001111..QDC0_CMP_FLAG0 input is selected
|
|
* 0b010000..QDC0_CMP_FLAG1 input is selected
|
|
* 0b010001..QDC0_CMP_FLAG2 input is selected
|
|
* 0b010010..QDC0_CMP_FLAG3 input is selected
|
|
* 0b010011..QDC0_POS_MATCH0 input is selected
|
|
* 0b010100..TRIG_IN0 input is selected
|
|
* 0b010101..TRIG_IN1 input is selected
|
|
* 0b010110..TRIG_IN2 input is selected
|
|
* 0b010111..TRIG_IN3 input is selected
|
|
* 0b011000..TRIG_IN4 input is selected
|
|
* 0b011001..TRIG_IN5 input is selected
|
|
* 0b011010..TRIG_IN6 input is selected
|
|
* 0b011011..TRIG_IN7 input is selected
|
|
* 0b011100..TRIG_IN8 input is selected
|
|
* 0b011101..TRIG_IN9 input is selected
|
|
* 0b011110..TRIG_IN10 input is selected
|
|
* 0b011111..TRIG_IN11 input is selected
|
|
* 0b100000..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b100001..GPIO1 Pin Event Trig 0 input is selected
|
|
* 0b100010..GPIO2 Pin Event Trig 0 input is selected
|
|
* 0b100011..GPIO3 Pin Event Trig 0 input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_FLEXPWM0_SM2_EXTA2_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_SM2_EXTA2_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_SM2_EXTA2_TRIGIN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FLEXPWM0_SM2_EXTSYNC2 - PWM0 input trigger connections */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_FLEXPWM0_SM2_EXTSYNC2_TRIGIN_MASK (0x3FU)
|
|
#define INPUTMUX_FLEXPWM0_SM2_EXTSYNC2_TRIGIN_SHIFT (0U)
|
|
/*! TRIGIN - Trigger input connections for PWM0
|
|
* 0b000000..Reserved
|
|
* 0b000001..ARM_TXEV input is selected
|
|
* 0b000010..AOI0_OUT0 input is selected
|
|
* 0b000011..AOI0_OUT1 input is selected
|
|
* 0b000100..AOI0_OUT2 input is selected
|
|
* 0b000101..AOI0_OUT3 input is selected
|
|
* 0b000110..CMP0_OUT input is selected
|
|
* 0b000111..CMP1_OUT input is selected
|
|
* 0b001000..Reserved
|
|
* 0b001001..CTimer0_MAT2 input is selected
|
|
* 0b001010..CTimer0_MAT3 input is selected
|
|
* 0b001011..CTimer1_MAT2 input is selected
|
|
* 0b001100..CTimer1_MAT3 input is selected
|
|
* 0b001101..CTimer2_MAT2 input is selected
|
|
* 0b001110..CTimer2_MAT3 input is selected
|
|
* 0b001111..QDC0_CMP_FLAG0 input is selected
|
|
* 0b010000..QDC0_CMP_FLAG1 input is selected
|
|
* 0b010001..QDC0_CMP_FLAG2 input is selected
|
|
* 0b010010..QDC0_CMP_FLAG3 input is selected
|
|
* 0b010011..QDC0_POS_MATCH0 input is selected
|
|
* 0b010100..TRIG_IN0 input is selected
|
|
* 0b010101..TRIG_IN1 input is selected
|
|
* 0b010110..TRIG_IN2 input is selected
|
|
* 0b010111..TRIG_IN3 input is selected
|
|
* 0b011000..TRIG_IN4 input is selected
|
|
* 0b011001..TRIG_IN5 input is selected
|
|
* 0b011010..TRIG_IN6 input is selected
|
|
* 0b011011..TRIG_IN7 input is selected
|
|
* 0b011100..TRIG_IN8 input is selected
|
|
* 0b011101..TRIG_IN9 input is selected
|
|
* 0b011110..TRIG_IN10 input is selected
|
|
* 0b011111..TRIG_IN11 input is selected
|
|
* 0b100000..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b100001..GPIO1 Pin Event Trig 0 input is selected
|
|
* 0b100010..GPIO2 Pin Event Trig 0 input is selected
|
|
* 0b100011..GPIO3 Pin Event Trig 0 input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_FLEXPWM0_SM2_EXTSYNC2_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_SM2_EXTSYNC2_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_SM2_EXTSYNC2_TRIGIN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FLEXPWM0_FAULT0 - PWM0 input trigger connections */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_FLEXPWM0_FAULT0_TRIGIN_MASK (0x3FU)
|
|
#define INPUTMUX_FLEXPWM0_FAULT0_TRIGIN_SHIFT (0U)
|
|
/*! TRIGIN - Trigger input connections for PWM0
|
|
* 0b000000..Reserved
|
|
* 0b000001..ARM_TXEV input is selected
|
|
* 0b000010..AOI0_OUT0 input is selected
|
|
* 0b000011..AOI0_OUT1 input is selected
|
|
* 0b000100..AOI0_OUT2 input is selected
|
|
* 0b000101..AOI0_OUT3 input is selected
|
|
* 0b000110..CMP0_OUT input is selected
|
|
* 0b000111..CMP1_OUT input is selected
|
|
* 0b001000..Reserved
|
|
* 0b001001..CTimer0_MAT2 input is selected
|
|
* 0b001010..CTimer0_MAT3 input is selected
|
|
* 0b001011..CTimer1_MAT2 input is selected
|
|
* 0b001100..CTimer1_MAT3 input is selected
|
|
* 0b001101..CTimer2_MAT2 input is selected
|
|
* 0b001110..CTimer2_MAT3 input is selected
|
|
* 0b001111..QDC0_CMP_FLAG0 input is selected
|
|
* 0b010000..QDC0_CMP_FLAG1 input is selected
|
|
* 0b010001..QDC0_CMP_FLAG2 input is selected
|
|
* 0b010010..QDC0_CMP_FLAG3 input is selected
|
|
* 0b010011..QDC0_POS_MATCH0 input is selected
|
|
* 0b010100..TRIG_IN0 input is selected
|
|
* 0b010101..TRIG_IN1 input is selected
|
|
* 0b010110..TRIG_IN2 input is selected
|
|
* 0b010111..TRIG_IN3 input is selected
|
|
* 0b011000..TRIG_IN4 input is selected
|
|
* 0b011001..TRIG_IN5 input is selected
|
|
* 0b011010..TRIG_IN6 input is selected
|
|
* 0b011011..TRIG_IN7 input is selected
|
|
* 0b011100..TRIG_IN8 input is selected
|
|
* 0b011101..TRIG_IN9 input is selected
|
|
* 0b011110..TRIG_IN10 input is selected
|
|
* 0b011111..TRIG_IN11 input is selected
|
|
* 0b100000..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b100001..GPIO1 Pin Event Trig 0 input is selected
|
|
* 0b100010..GPIO2 Pin Event Trig 0 input is selected
|
|
* 0b100011..GPIO3 Pin Event Trig 0 input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_FLEXPWM0_FAULT0_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_FAULT0_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_FAULT0_TRIGIN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FLEXPWM0_FAULT1 - PWM0 input trigger connections */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_FLEXPWM0_FAULT1_TRIGIN_MASK (0x3FU)
|
|
#define INPUTMUX_FLEXPWM0_FAULT1_TRIGIN_SHIFT (0U)
|
|
/*! TRIGIN - Trigger input connections for PWM0
|
|
* 0b000000..Reserved
|
|
* 0b000001..ARM_TXEV input is selected
|
|
* 0b000010..AOI0_OUT0 input is selected
|
|
* 0b000011..AOI0_OUT1 input is selected
|
|
* 0b000100..AOI0_OUT2 input is selected
|
|
* 0b000101..AOI0_OUT3 input is selected
|
|
* 0b000110..CMP0_OUT input is selected
|
|
* 0b000111..CMP1_OUT input is selected
|
|
* 0b001000..Reserved
|
|
* 0b001001..CTimer0_MAT2 input is selected
|
|
* 0b001010..CTimer0_MAT3 input is selected
|
|
* 0b001011..CTimer1_MAT2 input is selected
|
|
* 0b001100..CTimer1_MAT3 input is selected
|
|
* 0b001101..CTimer2_MAT2 input is selected
|
|
* 0b001110..CTimer2_MAT3 input is selected
|
|
* 0b001111..QDC0_CMP_FLAG0 input is selected
|
|
* 0b010000..QDC0_CMP_FLAG1 input is selected
|
|
* 0b010001..QDC0_CMP_FLAG2 input is selected
|
|
* 0b010010..QDC0_CMP_FLAG3 input is selected
|
|
* 0b010011..QDC0_POS_MATCH0 input is selected
|
|
* 0b010100..TRIG_IN0 input is selected
|
|
* 0b010101..TRIG_IN1 input is selected
|
|
* 0b010110..TRIG_IN2 input is selected
|
|
* 0b010111..TRIG_IN3 input is selected
|
|
* 0b011000..TRIG_IN4 input is selected
|
|
* 0b011001..TRIG_IN5 input is selected
|
|
* 0b011010..TRIG_IN6 input is selected
|
|
* 0b011011..TRIG_IN7 input is selected
|
|
* 0b011100..TRIG_IN8 input is selected
|
|
* 0b011101..TRIG_IN9 input is selected
|
|
* 0b011110..TRIG_IN10 input is selected
|
|
* 0b011111..TRIG_IN11 input is selected
|
|
* 0b100000..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b100001..GPIO1 Pin Event Trig 0 input is selected
|
|
* 0b100010..GPIO2 Pin Event Trig 0 input is selected
|
|
* 0b100011..GPIO3 Pin Event Trig 0 input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_FLEXPWM0_FAULT1_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_FAULT1_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_FAULT1_TRIGIN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FLEXPWM0_FAULT2 - PWM0 input trigger connections */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_FLEXPWM0_FAULT2_TRIGIN_MASK (0x3FU)
|
|
#define INPUTMUX_FLEXPWM0_FAULT2_TRIGIN_SHIFT (0U)
|
|
/*! TRIGIN - Trigger input connections for PWM0
|
|
* 0b000000..Reserved
|
|
* 0b000001..ARM_TXEV input is selected
|
|
* 0b000010..AOI0_OUT0 input is selected
|
|
* 0b000011..AOI0_OUT1 input is selected
|
|
* 0b000100..AOI0_OUT2 input is selected
|
|
* 0b000101..AOI0_OUT3 input is selected
|
|
* 0b000110..CMP0_OUT input is selected
|
|
* 0b000111..CMP1_OUT input is selected
|
|
* 0b001000..Reserved
|
|
* 0b001001..CTimer0_MAT2 input is selected
|
|
* 0b001010..CTimer0_MAT3 input is selected
|
|
* 0b001011..CTimer1_MAT2 input is selected
|
|
* 0b001100..CTimer1_MAT3 input is selected
|
|
* 0b001101..CTimer2_MAT2 input is selected
|
|
* 0b001110..CTimer2_MAT3 input is selected
|
|
* 0b001111..QDC0_CMP_FLAG0 input is selected
|
|
* 0b010000..QDC0_CMP_FLAG1 input is selected
|
|
* 0b010001..QDC0_CMP_FLAG2 input is selected
|
|
* 0b010010..QDC0_CMP_FLAG3 input is selected
|
|
* 0b010011..QDC0_POS_MATCH0 input is selected
|
|
* 0b010100..TRIG_IN0 input is selected
|
|
* 0b010101..TRIG_IN1 input is selected
|
|
* 0b010110..TRIG_IN2 input is selected
|
|
* 0b010111..TRIG_IN3 input is selected
|
|
* 0b011000..TRIG_IN4 input is selected
|
|
* 0b011001..TRIG_IN5 input is selected
|
|
* 0b011010..TRIG_IN6 input is selected
|
|
* 0b011011..TRIG_IN7 input is selected
|
|
* 0b011100..TRIG_IN8 input is selected
|
|
* 0b011101..TRIG_IN9 input is selected
|
|
* 0b011110..TRIG_IN10 input is selected
|
|
* 0b011111..TRIG_IN11 input is selected
|
|
* 0b100000..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b100001..GPIO1 Pin Event Trig 0 input is selected
|
|
* 0b100010..GPIO2 Pin Event Trig 0 input is selected
|
|
* 0b100011..GPIO3 Pin Event Trig 0 input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_FLEXPWM0_FAULT2_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_FAULT2_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_FAULT2_TRIGIN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FLEXPWM0_FAULT3 - PWM0 input trigger connections */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_FLEXPWM0_FAULT3_TRIGIN_MASK (0x3FU)
|
|
#define INPUTMUX_FLEXPWM0_FAULT3_TRIGIN_SHIFT (0U)
|
|
/*! TRIGIN - Trigger input connections for PWM0
|
|
* 0b000000..Reserved
|
|
* 0b000001..ARM_TXEV input is selected
|
|
* 0b000010..AOI0_OUT0 input is selected
|
|
* 0b000011..AOI0_OUT1 input is selected
|
|
* 0b000100..AOI0_OUT2 input is selected
|
|
* 0b000101..AOI0_OUT3 input is selected
|
|
* 0b000110..CMP0_OUT input is selected
|
|
* 0b000111..CMP1_OUT input is selected
|
|
* 0b001000..Reserved
|
|
* 0b001001..CTimer0_MAT2 input is selected
|
|
* 0b001010..CTimer0_MAT3 input is selected
|
|
* 0b001011..CTimer1_MAT2 input is selected
|
|
* 0b001100..CTimer1_MAT3 input is selected
|
|
* 0b001101..CTimer2_MAT2 input is selected
|
|
* 0b001110..CTimer2_MAT3 input is selected
|
|
* 0b001111..QDC0_CMP_FLAG0 input is selected
|
|
* 0b010000..QDC0_CMP_FLAG1 input is selected
|
|
* 0b010001..QDC0_CMP_FLAG2 input is selected
|
|
* 0b010010..QDC0_CMP_FLAG3 input is selected
|
|
* 0b010011..QDC0_POS_MATCH0 input is selected
|
|
* 0b010100..TRIG_IN0 input is selected
|
|
* 0b010101..TRIG_IN1 input is selected
|
|
* 0b010110..TRIG_IN2 input is selected
|
|
* 0b010111..TRIG_IN3 input is selected
|
|
* 0b011000..TRIG_IN4 input is selected
|
|
* 0b011001..TRIG_IN5 input is selected
|
|
* 0b011010..TRIG_IN6 input is selected
|
|
* 0b011011..TRIG_IN7 input is selected
|
|
* 0b011100..TRIG_IN8 input is selected
|
|
* 0b011101..TRIG_IN9 input is selected
|
|
* 0b011110..TRIG_IN10 input is selected
|
|
* 0b011111..TRIG_IN11 input is selected
|
|
* 0b100000..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b100001..GPIO1 Pin Event Trig 0 input is selected
|
|
* 0b100010..GPIO2 Pin Event Trig 0 input is selected
|
|
* 0b100011..GPIO3 Pin Event Trig 0 input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_FLEXPWM0_FAULT3_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_FAULT3_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_FAULT3_TRIGIN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FLEXPWM0_FORCE - PWM0 input trigger connections */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_FLEXPWM0_FORCE_TRIGIN_MASK (0x3FU)
|
|
#define INPUTMUX_FLEXPWM0_FORCE_TRIGIN_SHIFT (0U)
|
|
/*! TRIGIN - Trigger input connections for PWM0
|
|
* 0b000000..Reserved
|
|
* 0b000001..ARM_TXEV input is selected
|
|
* 0b000010..AOI0_OUT0 input is selected
|
|
* 0b000011..AOI0_OUT1 input is selected
|
|
* 0b000100..AOI0_OUT2 input is selected
|
|
* 0b000101..AOI0_OUT3 input is selected
|
|
* 0b000110..CMP0_OUT input is selected
|
|
* 0b000111..CMP1_OUT input is selected
|
|
* 0b001000..Reserved
|
|
* 0b001001..CTimer0_MAT2 input is selected
|
|
* 0b001010..CTimer0_MAT3 input is selected
|
|
* 0b001011..CTimer1_MAT2 input is selected
|
|
* 0b001100..CTimer1_MAT3 input is selected
|
|
* 0b001101..CTimer2_MAT2 input is selected
|
|
* 0b001110..CTimer2_MAT3 input is selected
|
|
* 0b001111..QDC0_CMP_FLAG0 input is selected
|
|
* 0b010000..QDC0_CMP_FLAG1 input is selected
|
|
* 0b010001..QDC0_CMP_FLAG2 input is selected
|
|
* 0b010010..QDC0_CMP_FLAG3 input is selected
|
|
* 0b010011..QDC0_POS_MATCH0 input is selected
|
|
* 0b010100..TRIG_IN0 input is selected
|
|
* 0b010101..TRIG_IN1 input is selected
|
|
* 0b010110..TRIG_IN2 input is selected
|
|
* 0b010111..TRIG_IN3 input is selected
|
|
* 0b011000..TRIG_IN4 input is selected
|
|
* 0b011001..TRIG_IN5 input is selected
|
|
* 0b011010..TRIG_IN6 input is selected
|
|
* 0b011011..TRIG_IN7 input is selected
|
|
* 0b011100..TRIG_IN8 input is selected
|
|
* 0b011101..TRIG_IN9 input is selected
|
|
* 0b011110..TRIG_IN10 input is selected
|
|
* 0b011111..TRIG_IN11 input is selected
|
|
* 0b100000..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b100001..GPIO1 Pin Event Trig 0 input is selected
|
|
* 0b100010..GPIO2 Pin Event Trig 0 input is selected
|
|
* 0b100011..GPIO3 Pin Event Trig 0 input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_FLEXPWM0_FORCE_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_FORCE_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_FORCE_TRIGIN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PWM0_EXT_CLK - PWM0 external clock trigger */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_PWM0_EXT_CLK_TRIGIN_MASK (0x7U)
|
|
#define INPUTMUX_PWM0_EXT_CLK_TRIGIN_SHIFT (0U)
|
|
/*! TRIGIN - Trigger input connections for PWM
|
|
* 0b000..Reserved
|
|
* 0b001..clk_16k[1] input is selected
|
|
* 0b010..clk_in input is selected
|
|
* 0b011..AOI0_OUT0 input is selected
|
|
* 0b100..AOI0_OUT1 input is selected
|
|
* 0b101..EXTTRIG_IN0 input is selected
|
|
* 0b110..EXTTRIG_IN7 input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_PWM0_EXT_CLK_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM0_EXT_CLK_TRIGIN_SHIFT)) & INPUTMUX_PWM0_EXT_CLK_TRIGIN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name AOI0_MUXA_AOI0_MUX - AOI0 trigger input connections 0-15 */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_AOI0_MUXA_AOI0_MUX_INP_MASK (0x3FU)
|
|
#define INPUTMUX_AOI0_MUXA_AOI0_MUX_INP_SHIFT (0U)
|
|
/*! INP - AOI0 trigger input connections
|
|
* 0b000000..Reserved
|
|
* 0b000001..ADC0_tcomp[0] input is selected input is selected input is selected
|
|
* 0b000010..ADC0_tcomp[1] input is selected input is selected
|
|
* 0b000011..ADC0_tcomp[2] input is selected input is selected
|
|
* 0b000100..ADC0_tcomp[3] input is selected input is selected
|
|
* 0b000101..CMP0_OUT input is selected
|
|
* 0b000110..CMP1_OUT input is selected
|
|
* 0b000111..Reserved
|
|
* 0b001000..CTimer0_MAT0 input is selected
|
|
* 0b001001..CTimer0_MAT1 input is selected
|
|
* 0b001010..CTimer0_MAT2 input is selected
|
|
* 0b001011..CTimer0_MAT3 input is selected
|
|
* 0b001100..CTimer1_MAT0 input is selected
|
|
* 0b001101..CTimer1_MAT1 input is selected
|
|
* 0b001110..CTimer1_MAT2 input is selected
|
|
* 0b001111..CTimer1_MAT3 input is selected
|
|
* 0b010000..CTimer2_MAT0 input is selected
|
|
* 0b010001..CTimer2_MAT1 input is selected
|
|
* 0b010010..CTimer2_MAT2 input is selected
|
|
* 0b010011..CTimer2_MAT3 input is selected
|
|
* 0b010100..LPTMR0 input is selected
|
|
* 0b010101..Reserved
|
|
* 0b010110..QDC0_CMP_FLAG0 input input is selected
|
|
* 0b010111..QDC0_CMP_FLAG1 input is selected
|
|
* 0b011000..QDC0_CMP_FLAG2 input is selected
|
|
* 0b011001..QDC0_CMP_FLAG3 input is selected
|
|
* 0b011010..QDC0_POS_MATCH input is selected
|
|
* 0b011011..PWM0_SM0_OUT_TRIG0 0 input is selected
|
|
* 0b011100..PWM0_SM0_OUT_TRIG1 input is selected
|
|
* 0b011101..PWM0_SM1_OUT_TRIG0 input is selected
|
|
* 0b011110..PWM0_SM1_OUT_TRIG1 input is selected
|
|
* 0b011111..PWM0_SM2_OUT_TRIG0 input is selected
|
|
* 0b100000..PWM0_SM2_OUT_TRIG1 input is selected
|
|
* 0b100001..Reserved
|
|
* 0b100010..Reserved
|
|
* 0b100011..TRIG_IN0 input is selected
|
|
* 0b100100..TRIG_IN1 input is selected
|
|
* 0b100101..TRIG_IN2 input is selected
|
|
* 0b100110..TRIG_IN3 input is selected
|
|
* 0b100111..TRIG_IN4 input is selected
|
|
* 0b101000..TRIG_IN5 input is selected
|
|
* 0b101001..TRIG_IN6 input is selected
|
|
* 0b101010..TRIG_IN7 input is selected
|
|
* 0b101011..TRIG_IN8 input is selected
|
|
* 0b101100..TRIG_IN9 input is selected
|
|
* 0b101101..TRIG_IN10 input is selected
|
|
* 0b101110..TRIG_IN11 input is selected
|
|
* 0b101111..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b110000..GPIO1 Pin Event Trig 0 input is selected
|
|
* 0b110001..GPIO2 Pin Event Trig 0 input is selected
|
|
* 0b110010..GPIO3 Pin Event Trig 0 input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_AOI0_MUXA_AOI0_MUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_AOI0_MUXA_AOI0_MUX_INP_SHIFT)) & INPUTMUX_AOI0_MUXA_AOI0_MUX_INP_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of INPUTMUX_AOI0_MUXA_AOI0_MUX */
|
|
#define INPUTMUX_AOI0_MUXA_AOI0_MUX_COUNT (16U)
|
|
|
|
/*! @name USBFS_TRIG - USB-FS trigger input connections */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_USBFS_TRIG_INP_MASK (0x7U)
|
|
#define INPUTMUX_USBFS_TRIG_INP_SHIFT (0U)
|
|
/*! INP - USB-FS trigger input connections.
|
|
* 0b000..Reserved
|
|
* 0b001..LPUART0 lpuart_trg_txdata input is selected
|
|
* 0b010..LPUART1 lpuart_trg_txdata input is selected
|
|
* 0b011..LPUART2 lpuart_trg_txdata input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_USBFS_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_USBFS_TRIG_INP_SHIFT)) & INPUTMUX_USBFS_TRIG_INP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name EXT_TRIGA_EXT_TRIG - EXT trigger connections 0-4 */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_EXT_TRIGA_EXT_TRIG_INP_MASK (0x1FU)
|
|
#define INPUTMUX_EXT_TRIGA_EXT_TRIG_INP_SHIFT (0U)
|
|
/*! INP - EXT trigger input connections
|
|
* 0b00000..Reserved
|
|
* 0b00001..ARM_TXEV input is selected
|
|
* 0b00010..AOI0_OUT0 input is selected
|
|
* 0b00011..AOI0_OUT1 input is selected
|
|
* 0b00100..AOI0_OUT2 input is selected
|
|
* 0b00101..AOI0_OUT3 input is selected
|
|
* 0b00110..CMP0_OUT input is selected
|
|
* 0b00111..CMP1_OUT input is selected
|
|
* 0b01000..Reserved
|
|
* 0b01001..LPUART0 input is selected
|
|
* 0b01010..LPUART1 input is selected
|
|
* 0b01011..LPUART2 input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_EXT_TRIGA_EXT_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EXT_TRIGA_EXT_TRIG_INP_SHIFT)) & INPUTMUX_EXT_TRIGA_EXT_TRIG_INP_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of INPUTMUX_EXT_TRIGA_EXT_TRIG */
|
|
#define INPUTMUX_EXT_TRIGA_EXT_TRIG_COUNT (5U)
|
|
|
|
/*! @name EXT_TRIGB_EXT_TRIG6 - EXT trigger connections 6-7 */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_EXT_TRIGB_EXT_TRIG6_INP_MASK (0x1FU)
|
|
#define INPUTMUX_EXT_TRIGB_EXT_TRIG6_INP_SHIFT (0U)
|
|
/*! INP - EXT trigger input connections
|
|
* 0b00000..Reserved
|
|
* 0b00001..ARM_TXEV input is selected
|
|
* 0b00010..AOI0_OUT0 input is selected
|
|
* 0b00011..AOI0_OUT1 input is selected
|
|
* 0b00100..AOI0_OUT2 input is selected
|
|
* 0b00101..AOI0_OUT3 input is selected
|
|
* 0b00110..CMP0_OUT input is selected
|
|
* 0b00111..CMP1_OUT input is selected
|
|
* 0b01000..Reserved
|
|
* 0b01001..LPUART0 input is selected
|
|
* 0b01010..LPUART1 input is selected
|
|
* 0b01011..LPUART2 input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_EXT_TRIGB_EXT_TRIG6_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EXT_TRIGB_EXT_TRIG6_INP_SHIFT)) & INPUTMUX_EXT_TRIGB_EXT_TRIG6_INP_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of INPUTMUX_EXT_TRIGB_EXT_TRIG6 */
|
|
#define INPUTMUX_EXT_TRIGB_EXT_TRIG6_COUNT (2U)
|
|
|
|
/*! @name CMP1_TRIG - CMP1 input connections */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_CMP1_TRIG_TRIGIN_MASK (0x3FU)
|
|
#define INPUTMUX_CMP1_TRIG_TRIGIN_SHIFT (0U)
|
|
/*! TRIGIN - CMP0 input trigger
|
|
* 0b000000..Reserved
|
|
* 0b000001..ARM_TXEV input is selected
|
|
* 0b000010..AOI0_OUT0 input is selected
|
|
* 0b000011..AOI0_OUT1 input is selected
|
|
* 0b000100..AOI0_OUT2 input is selected
|
|
* 0b000101..AOI0_OUT3 input is selected
|
|
* 0b000110..CMP0_OUT input is selected
|
|
* 0b000111..Reserved
|
|
* 0b001000..CTimer0_MAT0 input is selected
|
|
* 0b001001..CTimer0_MAT2 input is selected
|
|
* 0b001010..CTimer1_MAT0 input is selected
|
|
* 0b001011..CTimer1_MAT2 input is selected
|
|
* 0b001100..CTimer2_MAT0 input is selected
|
|
* 0b001101..CTimer2_MAT2 input is selected
|
|
* 0b001110..LPTMR0 input is selected
|
|
* 0b001111..Reserved
|
|
* 0b010000..QDC0_CMP/POS_MATCH0
|
|
* 0b010001..PWM0_SM0_OUT_TRIG0 input is selected
|
|
* 0b010010..PWM0_SM0_OUT_TRIG1 input is selected
|
|
* 0b010011..PWM0_SM1_OUT_TRIG0 input is selected
|
|
* 0b010100..PWM0_SM1_OUT_TRIG1 input is selected
|
|
* 0b010101..PWM0_SM2_OUT_TRIG0 input is selected
|
|
* 0b010110..PWM0_SM2_OUT_TRIG1 input is selected
|
|
* 0b010111..Reserved
|
|
* 0b011000..Reserved
|
|
* 0b011001..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b011010..GPIO1 Pin Event Trig 0 input is selected
|
|
* 0b011011..GPIO2 Pin Event Trig 0 input is selected
|
|
* 0b011100..GPIO3 Pin Event Trig 0 input is selected
|
|
* 0b011101..Reserved
|
|
* 0b011110..WUU input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_CMP1_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CMP1_TRIG_TRIGIN_SHIFT)) & INPUTMUX_CMP1_TRIG_TRIGIN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name LPI2C0_TRIG - LPI2C0 trigger input connections */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_LPI2C0_TRIG_INP_MASK (0x3FU)
|
|
#define INPUTMUX_LPI2C0_TRIG_INP_SHIFT (0U)
|
|
/*! INP - LPI2C0 trigger input connections
|
|
* 0b000000..Reserved
|
|
* 0b000001..ARM_TXEV
|
|
* 0b000010..AOI0_OUT0 input is selected
|
|
* 0b000011..AOI0_OUT1 input is selected
|
|
* 0b000100..AOI0_OUT2 input is selected
|
|
* 0b000101..AOI0_OUT3 input is selected
|
|
* 0b000110..CMP0_OUT input is selected
|
|
* 0b000111..CMP1_OUT input is selected
|
|
* 0b001000..Reserved
|
|
* 0b001001..CTimer0_MAT0 input is selected
|
|
* 0b001010..CTimer0_MAT1 input is selected
|
|
* 0b001011..CTimer1_MAT0 input is selected
|
|
* 0b001100..CTimer1_MAT1 input is selected
|
|
* 0b001101..CTimer2_MAT0 input is selected
|
|
* 0b001110..CTimer2_MAT1 input is selected
|
|
* 0b001111..LPTMR0 input is selected
|
|
* 0b010000..Reserved
|
|
* 0b010001..TRIG_IN0 input is selected
|
|
* 0b010010..TRIG_IN1 input is selected
|
|
* 0b010011..TRIG_IN2 input is selected
|
|
* 0b010100..TRIG_IN3 input is selected
|
|
* 0b010101..TRIG_IN4 input is selected
|
|
* 0b010110..TRIG_IN5 input is selected
|
|
* 0b010111..TRIG_IN6 input is selected
|
|
* 0b011000..TRIG_IN7 input is selected
|
|
* 0b011001..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b011010..GPIO1 Pin Event Trig 0 input is selected
|
|
* 0b011011..GPIO2 Pin Event Trig 0 input is selected
|
|
* 0b011100..GPIO3 Pin Event Trig 0 input is selected
|
|
* 0b101010..WUU input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_LPI2C0_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPI2C0_TRIG_INP_SHIFT)) & INPUTMUX_LPI2C0_TRIG_INP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name LPSPI0_TRIG - LPSPI0 trigger input connections */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_LPSPI0_TRIG_INP_MASK (0x3FU)
|
|
#define INPUTMUX_LPSPI0_TRIG_INP_SHIFT (0U)
|
|
/*! INP - LPSPI0 trigger input connections
|
|
* 0b000000..Reserved
|
|
* 0b000001..ARM_TXEV
|
|
* 0b000010..AOI0_OUT0 input is selected
|
|
* 0b000011..AOI0_OUT1 input is selected
|
|
* 0b000100..AOI0_OUT2 input is selected
|
|
* 0b000101..AOI0_OUT3 input is selected
|
|
* 0b000110..CMP0_OUT input is selected
|
|
* 0b000111..CMP1_OUT input is selected
|
|
* 0b001000..Reserved
|
|
* 0b001001..CTimer0_MAT1 input is selected
|
|
* 0b001010..CTimer0_MAT2 input is selected
|
|
* 0b001011..CTimer1_MAT1 input is selected
|
|
* 0b001100..CTimer1_MAT2 input is selected
|
|
* 0b001101..CTimer2_MAT1 input is selected
|
|
* 0b001110..CTimer2_MAT2 input is selected
|
|
* 0b001111..LPTMR0 input is selected
|
|
* 0b010000..Reserved
|
|
* 0b010001..TRIG_IN0 input is selected
|
|
* 0b010010..TRIG_IN1 input is selected
|
|
* 0b010011..TRIG_IN2 input is selected
|
|
* 0b010100..TRIG_IN3 input is selected
|
|
* 0b010101..TRIG_IN4 input is selected
|
|
* 0b010110..TRIG_IN5 input is selected
|
|
* 0b010111..TRIG_IN6 input is selected
|
|
* 0b011000..TRIG_IN7 input is selected
|
|
* 0b011001..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b011010..GPIO1 Pin Event Trig 0 input is selected
|
|
* 0b011011..GPIO2 Pin Event Trig 0 input is selected
|
|
* 0b011100..GPIO3 Pin Event Trig 0 input is selected
|
|
* 0b101010..WUU input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_LPSPI0_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPSPI0_TRIG_INP_SHIFT)) & INPUTMUX_LPSPI0_TRIG_INP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name LPSPI1_TRIG - LPSPI1 trigger input connections */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_LPSPI1_TRIG_INP_MASK (0x3FU)
|
|
#define INPUTMUX_LPSPI1_TRIG_INP_SHIFT (0U)
|
|
/*! INP - LPSPI1 trigger input connections
|
|
* 0b000000..Reserved
|
|
* 0b000001..ARM_TXEV
|
|
* 0b000010..AOI0_OUT0 input is selected
|
|
* 0b000011..AOI0_OUT1 input is selected
|
|
* 0b000100..AOI0_OUT2 input is selected
|
|
* 0b000101..AOI0_OUT3 input is selected
|
|
* 0b000110..CMP0_OUT input is selected
|
|
* 0b000111..CMP1_OUT input is selected
|
|
* 0b001000..Reserved
|
|
* 0b001001..CTimer0_MAT1 input is selected
|
|
* 0b001010..CTimer0_MAT2 input is selected
|
|
* 0b001011..CTimer1_MAT1 input is selected
|
|
* 0b001100..CTimer1_MAT2 input is selected
|
|
* 0b001101..CTimer2_MAT1 input is selected
|
|
* 0b001110..CTimer2_MAT2 input is selected
|
|
* 0b001111..LPTMR0 input is selected
|
|
* 0b010000..Reserved
|
|
* 0b010001..TRIG_IN0 input is selected
|
|
* 0b010010..TRIG_IN1 input is selected
|
|
* 0b010011..TRIG_IN2 input is selected
|
|
* 0b010100..TRIG_IN3 input is selected
|
|
* 0b010101..TRIG_IN4 input is selected
|
|
* 0b010110..TRIG_IN5 input is selected
|
|
* 0b010111..TRIG_IN6 input is selected
|
|
* 0b011000..TRIG_IN7 input is selected
|
|
* 0b011001..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b011010..GPIO1 Pin Event Trig 0 input is selected
|
|
* 0b011011..GPIO2 Pin Event Trig 0 input is selected
|
|
* 0b011100..GPIO3 Pin Event Trig 0 input is selected
|
|
* 0b101010..WUU input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_LPSPI1_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPSPI1_TRIG_INP_SHIFT)) & INPUTMUX_LPSPI1_TRIG_INP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name LPUART0 - LPUART0 trigger input connections */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_LPUART0_INP_MASK (0x3FU)
|
|
#define INPUTMUX_LPUART0_INP_SHIFT (0U)
|
|
/*! INP - LPUART0 trigger input connections
|
|
* 0b000000..Reserved
|
|
* 0b000001..ARM_TXEV
|
|
* 0b000010..AOI0_OUT0 input is selected
|
|
* 0b000011..AOI0_OUT1 input is selected
|
|
* 0b000100..AOI0_OUT2 input is selected
|
|
* 0b000101..AOI0_OUT3 input is selected
|
|
* 0b000110..CMP0_OUT input is selected
|
|
* 0b000111..CMP1_OUT input is selected
|
|
* 0b001000..Reserved
|
|
* 0b001001..CTimer0_MAT2 input is selected
|
|
* 0b001010..CTimer0_MAT3 input is selected
|
|
* 0b001011..CTimer1_MAT2 input is selected
|
|
* 0b001100..CTimer1_MAT3 input is selected
|
|
* 0b001101..CTimer2_MAT2 input is selected
|
|
* 0b001110..CTimer2_MAT3 input is selected
|
|
* 0b001111..LPTMR0 input is selected
|
|
* 0b010000..Reserved
|
|
* 0b010001..TRIG_IN0 input is selected
|
|
* 0b010010..TRIG_IN1 input is selected
|
|
* 0b010011..TRIG_IN2 input is selected
|
|
* 0b010100..TRIG_IN3 input is selected
|
|
* 0b010101..TRIG_IN4 input is selected
|
|
* 0b010110..TRIG_IN5 input is selected
|
|
* 0b010111..TRIG_IN6 input is selected
|
|
* 0b011000..TRIG_IN7 input is selected
|
|
* 0b011001..TRIG_IN8 input is selected
|
|
* 0b011010..TRIG_IN9 input is selected
|
|
* 0b011011..TRIG_IN10 input is selected
|
|
* 0b011100..TRIG_IN11 input is selected
|
|
* 0b011101..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b011110..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b011111..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b100000..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b100001..Reserved
|
|
* 0b100010..WUU input is selected
|
|
* 0b100011..USB0 ipp_ind_uart_rxd_usbmux input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_LPUART0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPUART0_INP_SHIFT)) & INPUTMUX_LPUART0_INP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name LPUART1 - LPUART1 trigger input connections */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_LPUART1_INP_MASK (0x3FU)
|
|
#define INPUTMUX_LPUART1_INP_SHIFT (0U)
|
|
/*! INP - LPUART1 trigger input connections
|
|
* 0b000000..Reserved
|
|
* 0b000001..ARM_TXEV
|
|
* 0b000010..AOI0_OUT0 input is selected
|
|
* 0b000011..AOI0_OUT1 input is selected
|
|
* 0b000100..AOI0_OUT2 input is selected
|
|
* 0b000101..AOI0_OUT3 input is selected
|
|
* 0b000110..CMP0_OUT input is selected
|
|
* 0b000111..CMP1_OUT input is selected
|
|
* 0b001000..Reserved
|
|
* 0b001001..CTimer0_MAT2 input is selected
|
|
* 0b001010..CTimer0_MAT3 input is selected
|
|
* 0b001011..CTimer1_MAT2 input is selected
|
|
* 0b001100..CTimer1_MAT3 input is selected
|
|
* 0b001101..CTimer2_MAT2 input is selected
|
|
* 0b001110..CTimer2_MAT3 input is selected
|
|
* 0b001111..LPTMR0 input is selected
|
|
* 0b010000..Reserved
|
|
* 0b010001..TRIG_IN0 input is selected
|
|
* 0b010010..TRIG_IN1 input is selected
|
|
* 0b010011..TRIG_IN2 input is selected
|
|
* 0b010100..TRIG_IN3 input is selected
|
|
* 0b010101..TRIG_IN4 input is selected
|
|
* 0b010110..TRIG_IN5 input is selected
|
|
* 0b010111..TRIG_IN6 input is selected
|
|
* 0b011000..TRIG_IN7 input is selected
|
|
* 0b011001..TRIG_IN8 input is selected
|
|
* 0b011010..TRIG_IN9 input is selected
|
|
* 0b011011..TRIG_IN10 input is selected
|
|
* 0b011100..TRIG_IN11 input is selected
|
|
* 0b011101..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b011110..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b011111..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b100000..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b100001..Reserved
|
|
* 0b100010..WUU input is selected
|
|
* 0b100011..USB0 ipp_ind_uart_rxd_usbmux input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_LPUART1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPUART1_INP_SHIFT)) & INPUTMUX_LPUART1_INP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name LPUART2 - LPUART2 trigger input connections */
|
|
/*! @{ */
|
|
|
|
#define INPUTMUX_LPUART2_INP_MASK (0x3FU)
|
|
#define INPUTMUX_LPUART2_INP_SHIFT (0U)
|
|
/*! INP - LPUART2 trigger input connections
|
|
* 0b000000..Reserved
|
|
* 0b000001..ARM_TXEV
|
|
* 0b000010..AOI0_OUT0 input is selected
|
|
* 0b000011..AOI0_OUT1 input is selected
|
|
* 0b000100..AOI0_OUT2 input is selected
|
|
* 0b000101..AOI0_OUT3 input is selected
|
|
* 0b000110..CMP0_OUT input is selected
|
|
* 0b000111..CMP1_OUT input is selected
|
|
* 0b001000..Reserved
|
|
* 0b001001..CTimer0_MAT2 input is selected
|
|
* 0b001010..CTimer0_MAT3 input is selected
|
|
* 0b001011..CTimer1_MAT2 input is selected
|
|
* 0b001100..CTimer1_MAT3 input is selected
|
|
* 0b001101..CTimer2_MAT2 input is selected
|
|
* 0b001110..CTimer2_MAT3 input is selected
|
|
* 0b001111..LPTMR0 input is selected
|
|
* 0b010000..Reserved
|
|
* 0b010001..TRIG_IN0 input is selected
|
|
* 0b010010..TRIG_IN1 input is selected
|
|
* 0b010011..TRIG_IN2 input is selected
|
|
* 0b010100..TRIG_IN3 input is selected
|
|
* 0b010101..TRIG_IN4 input is selected
|
|
* 0b010110..TRIG_IN5 input is selected
|
|
* 0b010111..TRIG_IN6 input is selected
|
|
* 0b011000..TRIG_IN7 input is selected
|
|
* 0b011001..TRIG_IN8 input is selected
|
|
* 0b011010..TRIG_IN9 input is selected
|
|
* 0b011011..TRIG_IN10 input is selected
|
|
* 0b011100..TRIG_IN11 input is selected
|
|
* 0b011101..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b011110..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b011111..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b100000..GPIO0 Pin Event Trig 0 input is selected
|
|
* 0b100001..Reserved
|
|
* 0b100010..WUU input is selected
|
|
* 0b100011..USB0 ipp_ind_uart_rxd_usbmux input is selected
|
|
* *..
|
|
*/
|
|
#define INPUTMUX_LPUART2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPUART2_INP_SHIFT)) & INPUTMUX_LPUART2_INP_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group INPUTMUX_Register_Masks */
|
|
|
|
|
|
/* INPUTMUX - Peripheral instance base addresses */
|
|
/** Peripheral INPUTMUX0 base address */
|
|
#define INPUTMUX0_BASE (0x40001000u)
|
|
/** Peripheral INPUTMUX0 base pointer */
|
|
#define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE)
|
|
/** Array initializer of INPUTMUX peripheral base addresses */
|
|
#define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE }
|
|
/** Array initializer of INPUTMUX peripheral base pointers */
|
|
#define INPUTMUX_BASE_PTRS { INPUTMUX0 }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group INPUTMUX_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- LPCMP Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup LPCMP_Peripheral_Access_Layer LPCMP Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** LPCMP - Register Layout Typedef */
|
|
typedef struct {
|
|
__I uint32_t VERID; /**< Version ID, offset: 0x0 */
|
|
__I uint32_t PARAM; /**< Parameter, offset: 0x4 */
|
|
__IO uint32_t CCR0; /**< Comparator Control Register 0, offset: 0x8 */
|
|
__IO uint32_t CCR1; /**< Comparator Control Register 1, offset: 0xC */
|
|
__IO uint32_t CCR2; /**< Comparator Control Register 2, offset: 0x10 */
|
|
uint8_t RESERVED_0[4];
|
|
__IO uint32_t DCR; /**< DAC Control, offset: 0x18 */
|
|
__IO uint32_t IER; /**< Interrupt Enable, offset: 0x1C */
|
|
__IO uint32_t CSR; /**< Comparator Status, offset: 0x20 */
|
|
__IO uint32_t RRCR0; /**< Round Robin Control Register 0, offset: 0x24 */
|
|
__IO uint32_t RRCR1; /**< Round Robin Control Register 1, offset: 0x28 */
|
|
__IO uint32_t RRCSR; /**< Round Robin Control and Status, offset: 0x2C */
|
|
__IO uint32_t RRSR; /**< Round Robin Status, offset: 0x30 */
|
|
uint8_t RESERVED_1[4];
|
|
__IO uint32_t RRCR2; /**< Round Robin Control Register 2, offset: 0x38 */
|
|
} LPCMP_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- LPCMP Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup LPCMP_Register_Masks LPCMP Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name VERID - Version ID */
|
|
/*! @{ */
|
|
|
|
#define LPCMP_VERID_FEATURE_MASK (0xFFFFU)
|
|
#define LPCMP_VERID_FEATURE_SHIFT (0U)
|
|
/*! FEATURE - Feature Specification Number
|
|
* 0b0000000000000001..Round robin feature
|
|
*/
|
|
#define LPCMP_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_FEATURE_SHIFT)) & LPCMP_VERID_FEATURE_MASK)
|
|
|
|
#define LPCMP_VERID_MINOR_MASK (0xFF0000U)
|
|
#define LPCMP_VERID_MINOR_SHIFT (16U)
|
|
/*! MINOR - Minor Version Number */
|
|
#define LPCMP_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_MINOR_SHIFT)) & LPCMP_VERID_MINOR_MASK)
|
|
|
|
#define LPCMP_VERID_MAJOR_MASK (0xFF000000U)
|
|
#define LPCMP_VERID_MAJOR_SHIFT (24U)
|
|
/*! MAJOR - Major Version Number */
|
|
#define LPCMP_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_MAJOR_SHIFT)) & LPCMP_VERID_MAJOR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PARAM - Parameter */
|
|
/*! @{ */
|
|
|
|
#define LPCMP_PARAM_DAC_RES_MASK (0xFU)
|
|
#define LPCMP_PARAM_DAC_RES_SHIFT (0U)
|
|
/*! DAC_RES - DAC Resolution
|
|
* 0b0000..4-bit DAC
|
|
* 0b0001..6-bit DAC
|
|
* 0b0010..8-bit DAC
|
|
* 0b0011..10-bit DAC
|
|
* 0b0100..12-bit DAC
|
|
* 0b0101..14-bit DAC
|
|
* 0b0110..16-bit DAC
|
|
*/
|
|
#define LPCMP_PARAM_DAC_RES(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_PARAM_DAC_RES_SHIFT)) & LPCMP_PARAM_DAC_RES_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CCR0 - Comparator Control Register 0 */
|
|
/*! @{ */
|
|
|
|
#define LPCMP_CCR0_CMP_EN_MASK (0x1U)
|
|
#define LPCMP_CCR0_CMP_EN_SHIFT (0U)
|
|
/*! CMP_EN - Comparator Enable
|
|
* 0b0..Disables (The analog logic remains off and consumes no power.)
|
|
* 0b1..Enables
|
|
*/
|
|
#define LPCMP_CCR0_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR0_CMP_EN_SHIFT)) & LPCMP_CCR0_CMP_EN_MASK)
|
|
|
|
#define LPCMP_CCR0_CMP_STOP_EN_MASK (0x2U)
|
|
#define LPCMP_CCR0_CMP_STOP_EN_SHIFT (1U)
|
|
/*! CMP_STOP_EN - Comparator Deep sleep Mode Enable
|
|
* 0b0..Disable the analog comparator regardless of CMP_EN.
|
|
* 0b1..Allows CMP_EN to enable the analog comparator.
|
|
*/
|
|
#define LPCMP_CCR0_CMP_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR0_CMP_STOP_EN_SHIFT)) & LPCMP_CCR0_CMP_STOP_EN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CCR1 - Comparator Control Register 1 */
|
|
/*! @{ */
|
|
|
|
#define LPCMP_CCR1_WINDOW_EN_MASK (0x1U)
|
|
#define LPCMP_CCR1_WINDOW_EN_SHIFT (0U)
|
|
/*! WINDOW_EN - Windowing Enable
|
|
* 0b0..Disables
|
|
* 0b1..Enables
|
|
*/
|
|
#define LPCMP_CCR1_WINDOW_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_EN_SHIFT)) & LPCMP_CCR1_WINDOW_EN_MASK)
|
|
|
|
#define LPCMP_CCR1_SAMPLE_EN_MASK (0x2U)
|
|
#define LPCMP_CCR1_SAMPLE_EN_SHIFT (1U)
|
|
/*! SAMPLE_EN - Sampling Enable
|
|
* 0b0..Disables
|
|
* 0b1..Enables
|
|
*/
|
|
#define LPCMP_CCR1_SAMPLE_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_SAMPLE_EN_SHIFT)) & LPCMP_CCR1_SAMPLE_EN_MASK)
|
|
|
|
#define LPCMP_CCR1_DMA_EN_MASK (0x4U)
|
|
#define LPCMP_CCR1_DMA_EN_SHIFT (2U)
|
|
/*! DMA_EN - DMA Enable
|
|
* 0b0..Disables
|
|
* 0b1..Enables
|
|
*/
|
|
#define LPCMP_CCR1_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_DMA_EN_SHIFT)) & LPCMP_CCR1_DMA_EN_MASK)
|
|
|
|
#define LPCMP_CCR1_COUT_INV_MASK (0x8U)
|
|
#define LPCMP_CCR1_COUT_INV_SHIFT (3U)
|
|
/*! COUT_INV - Comparator Invert
|
|
* 0b0..Do not invert
|
|
* 0b1..Invert
|
|
*/
|
|
#define LPCMP_CCR1_COUT_INV(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_INV_SHIFT)) & LPCMP_CCR1_COUT_INV_MASK)
|
|
|
|
#define LPCMP_CCR1_COUT_SEL_MASK (0x10U)
|
|
#define LPCMP_CCR1_COUT_SEL_SHIFT (4U)
|
|
/*! COUT_SEL - Comparator Output Select
|
|
* 0b0..Use COUT (filtered)
|
|
* 0b1..Use COUTA (unfiltered)
|
|
*/
|
|
#define LPCMP_CCR1_COUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_SEL_SHIFT)) & LPCMP_CCR1_COUT_SEL_MASK)
|
|
|
|
#define LPCMP_CCR1_COUT_PEN_MASK (0x20U)
|
|
#define LPCMP_CCR1_COUT_PEN_SHIFT (5U)
|
|
/*! COUT_PEN - Comparator Output Pin Enable
|
|
* 0b0..Not available
|
|
* 0b1..Available
|
|
*/
|
|
#define LPCMP_CCR1_COUT_PEN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_PEN_SHIFT)) & LPCMP_CCR1_COUT_PEN_MASK)
|
|
|
|
#define LPCMP_CCR1_COUTA_OWEN_MASK (0x40U)
|
|
#define LPCMP_CCR1_COUTA_OWEN_SHIFT (6U)
|
|
/*! COUTA_OWEN - COUTA_OW Enable
|
|
* 0b0..COUTA holds the last sampled value.
|
|
* 0b1..Enables the COUTA signal value to be defined by COUTA_OW.
|
|
*/
|
|
#define LPCMP_CCR1_COUTA_OWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUTA_OWEN_SHIFT)) & LPCMP_CCR1_COUTA_OWEN_MASK)
|
|
|
|
#define LPCMP_CCR1_COUTA_OW_MASK (0x80U)
|
|
#define LPCMP_CCR1_COUTA_OW_SHIFT (7U)
|
|
/*! COUTA_OW - COUTA Output Level for Closed Window
|
|
* 0b0..COUTA is 0
|
|
* 0b1..COUTA is 1
|
|
*/
|
|
#define LPCMP_CCR1_COUTA_OW(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUTA_OW_SHIFT)) & LPCMP_CCR1_COUTA_OW_MASK)
|
|
|
|
#define LPCMP_CCR1_WINDOW_INV_MASK (0x100U)
|
|
#define LPCMP_CCR1_WINDOW_INV_SHIFT (8U)
|
|
/*! WINDOW_INV - WINDOW/SAMPLE Signal Invert
|
|
* 0b0..Do not invert
|
|
* 0b1..Invert
|
|
*/
|
|
#define LPCMP_CCR1_WINDOW_INV(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_INV_SHIFT)) & LPCMP_CCR1_WINDOW_INV_MASK)
|
|
|
|
#define LPCMP_CCR1_WINDOW_CLS_MASK (0x200U)
|
|
#define LPCMP_CCR1_WINDOW_CLS_SHIFT (9U)
|
|
/*! WINDOW_CLS - COUT Event Window Close
|
|
* 0b0..COUT event cannot close the window
|
|
* 0b1..COUT event can close the window
|
|
*/
|
|
#define LPCMP_CCR1_WINDOW_CLS(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_CLS_SHIFT)) & LPCMP_CCR1_WINDOW_CLS_MASK)
|
|
|
|
#define LPCMP_CCR1_EVT_SEL_MASK (0xC00U)
|
|
#define LPCMP_CCR1_EVT_SEL_SHIFT (10U)
|
|
/*! EVT_SEL - COUT Event Select
|
|
* 0b00..Rising edge
|
|
* 0b01..Falling edge
|
|
* 0b1x..Both edges
|
|
*/
|
|
#define LPCMP_CCR1_EVT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_EVT_SEL_SHIFT)) & LPCMP_CCR1_EVT_SEL_MASK)
|
|
|
|
#define LPCMP_CCR1_FUNC_CLK_SEL_MASK (0x3000U)
|
|
#define LPCMP_CCR1_FUNC_CLK_SEL_SHIFT (12U)
|
|
/*! FUNC_CLK_SEL - Functional Clock Source Select
|
|
* 0b00..Select functional clock source 0
|
|
* 0b01..Select functional clock source 1
|
|
* 0b10..Select functional clock source 2
|
|
* 0b11..Select functional clock source 3
|
|
*/
|
|
#define LPCMP_CCR1_FUNC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FUNC_CLK_SEL_SHIFT)) & LPCMP_CCR1_FUNC_CLK_SEL_MASK)
|
|
|
|
#define LPCMP_CCR1_FILT_CNT_MASK (0x70000U)
|
|
#define LPCMP_CCR1_FILT_CNT_SHIFT (16U)
|
|
/*! FILT_CNT - Filter Sample Count
|
|
* 0b000..Filter is bypassed: COUT = COUTA
|
|
* 0b001..1 consecutive sample (Comparator output is simply sampled.)
|
|
* 0b010..2 consecutive samples
|
|
* 0b011..3 consecutive samples
|
|
* 0b100..4 consecutive samples
|
|
* 0b101..5 consecutive samples
|
|
* 0b110..6 consecutive samples
|
|
* 0b111..7 consecutive samples
|
|
*/
|
|
#define LPCMP_CCR1_FILT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FILT_CNT_SHIFT)) & LPCMP_CCR1_FILT_CNT_MASK)
|
|
|
|
#define LPCMP_CCR1_FILT_PER_MASK (0xFF000000U)
|
|
#define LPCMP_CCR1_FILT_PER_SHIFT (24U)
|
|
/*! FILT_PER - Filter Sample Period */
|
|
#define LPCMP_CCR1_FILT_PER(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FILT_PER_SHIFT)) & LPCMP_CCR1_FILT_PER_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CCR2 - Comparator Control Register 2 */
|
|
/*! @{ */
|
|
|
|
#define LPCMP_CCR2_CMP_HPMD_MASK (0x1U)
|
|
#define LPCMP_CCR2_CMP_HPMD_SHIFT (0U)
|
|
/*! CMP_HPMD - CMP High Power Mode Select
|
|
* 0b0..Low power (speed) comparison mode
|
|
* 0b1..High power (speed) comparison mode
|
|
*/
|
|
#define LPCMP_CCR2_CMP_HPMD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_CMP_HPMD_SHIFT)) & LPCMP_CCR2_CMP_HPMD_MASK)
|
|
|
|
#define LPCMP_CCR2_CMP_NPMD_MASK (0x2U)
|
|
#define LPCMP_CCR2_CMP_NPMD_SHIFT (1U)
|
|
/*! CMP_NPMD - CMP Nano Power Mode Select
|
|
* 0b0..Disables CMP Nano power mode. CCR2[CMP_HPMD] determines the mode for the comparator.
|
|
* 0b1..Enables CMP Nano power mode.
|
|
*/
|
|
#define LPCMP_CCR2_CMP_NPMD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_CMP_NPMD_SHIFT)) & LPCMP_CCR2_CMP_NPMD_MASK)
|
|
|
|
#define LPCMP_CCR2_HYSTCTR_MASK (0x30U)
|
|
#define LPCMP_CCR2_HYSTCTR_SHIFT (4U)
|
|
/*! HYSTCTR - Comparator Hysteresis Control
|
|
* 0b00..Level 0
|
|
* 0b01..Level 1
|
|
* 0b10..Level 2
|
|
* 0b11..Level 3
|
|
*/
|
|
#define LPCMP_CCR2_HYSTCTR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_HYSTCTR_SHIFT)) & LPCMP_CCR2_HYSTCTR_MASK)
|
|
|
|
#define LPCMP_CCR2_PSEL_MASK (0x70000U)
|
|
#define LPCMP_CCR2_PSEL_SHIFT (16U)
|
|
/*! PSEL - Plus Input MUX Select
|
|
* 0b000..Input 0p
|
|
* 0b001..Input 1p
|
|
* 0b010..Input 2p
|
|
* 0b011..Input 3p
|
|
* 0b100..Input 4p
|
|
* 0b101..Input 5p
|
|
* 0b110..Reserved
|
|
* 0b111..Internal DAC output
|
|
*/
|
|
#define LPCMP_CCR2_PSEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_PSEL_SHIFT)) & LPCMP_CCR2_PSEL_MASK)
|
|
|
|
#define LPCMP_CCR2_MSEL_MASK (0x700000U)
|
|
#define LPCMP_CCR2_MSEL_SHIFT (20U)
|
|
/*! MSEL - Minus Input MUX Select
|
|
* 0b000..Input 0m
|
|
* 0b001..Input 1m
|
|
* 0b010..Input 2m
|
|
* 0b011..Input 3m
|
|
* 0b100..Input 4m
|
|
* 0b101..Input 5m
|
|
* 0b110..Reserved
|
|
* 0b111..Internal DAC output
|
|
*/
|
|
#define LPCMP_CCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_MSEL_SHIFT)) & LPCMP_CCR2_MSEL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DCR - DAC Control */
|
|
/*! @{ */
|
|
|
|
#define LPCMP_DCR_DAC_EN_MASK (0x1U)
|
|
#define LPCMP_DCR_DAC_EN_SHIFT (0U)
|
|
/*! DAC_EN - DAC Enable
|
|
* 0b0..Disables
|
|
* 0b1..Enables
|
|
*/
|
|
#define LPCMP_DCR_DAC_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_EN_SHIFT)) & LPCMP_DCR_DAC_EN_MASK)
|
|
|
|
#define LPCMP_DCR_DAC_HPMD_MASK (0x2U)
|
|
#define LPCMP_DCR_DAC_HPMD_SHIFT (1U)
|
|
/*! DAC_HPMD - DAC High Power Mode Select
|
|
* 0b0..Disables
|
|
* 0b1..Enables
|
|
*/
|
|
#define LPCMP_DCR_DAC_HPMD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_HPMD_SHIFT)) & LPCMP_DCR_DAC_HPMD_MASK)
|
|
|
|
#define LPCMP_DCR_VRSEL_MASK (0x100U)
|
|
#define LPCMP_DCR_VRSEL_SHIFT (8U)
|
|
/*! VRSEL - DAC Reference High Voltage Source Select
|
|
* 0b0..vrefh0
|
|
* 0b1..vrefh1
|
|
*/
|
|
#define LPCMP_DCR_VRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_VRSEL_SHIFT)) & LPCMP_DCR_VRSEL_MASK)
|
|
|
|
#define LPCMP_DCR_DAC_DATA_MASK (0xFF0000U)
|
|
#define LPCMP_DCR_DAC_DATA_SHIFT (16U)
|
|
/*! DAC_DATA - DAC Output Voltage Select */
|
|
#define LPCMP_DCR_DAC_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_DATA_SHIFT)) & LPCMP_DCR_DAC_DATA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name IER - Interrupt Enable */
|
|
/*! @{ */
|
|
|
|
#define LPCMP_IER_CFR_IE_MASK (0x1U)
|
|
#define LPCMP_IER_CFR_IE_SHIFT (0U)
|
|
/*! CFR_IE - Comparator Flag Rising Interrupt Enable
|
|
* 0b0..Disables the comparator flag rising interrupt.
|
|
* 0b1..Enables the comparator flag rising interrupt when CFR is set.
|
|
*/
|
|
#define LPCMP_IER_CFR_IE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_CFR_IE_SHIFT)) & LPCMP_IER_CFR_IE_MASK)
|
|
|
|
#define LPCMP_IER_CFF_IE_MASK (0x2U)
|
|
#define LPCMP_IER_CFF_IE_SHIFT (1U)
|
|
/*! CFF_IE - Comparator Flag Falling Interrupt Enable
|
|
* 0b0..Disables the comparator flag falling interrupt.
|
|
* 0b1..Enables the comparator flag falling interrupt when CFF is set.
|
|
*/
|
|
#define LPCMP_IER_CFF_IE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_CFF_IE_SHIFT)) & LPCMP_IER_CFF_IE_MASK)
|
|
|
|
#define LPCMP_IER_RRF_IE_MASK (0x4U)
|
|
#define LPCMP_IER_RRF_IE_SHIFT (2U)
|
|
/*! RRF_IE - Round-Robin Flag Interrupt Enable
|
|
* 0b0..Disables the round-robin flag interrupt.
|
|
* 0b1..Enables the round-robin flag interrupt when the comparison result changes for a given channel.
|
|
*/
|
|
#define LPCMP_IER_RRF_IE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_RRF_IE_SHIFT)) & LPCMP_IER_RRF_IE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CSR - Comparator Status */
|
|
/*! @{ */
|
|
|
|
#define LPCMP_CSR_CFR_MASK (0x1U)
|
|
#define LPCMP_CSR_CFR_SHIFT (0U)
|
|
/*! CFR - Analog Comparator Flag Rising
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
*/
|
|
#define LPCMP_CSR_CFR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_CFR_SHIFT)) & LPCMP_CSR_CFR_MASK)
|
|
|
|
#define LPCMP_CSR_CFF_MASK (0x2U)
|
|
#define LPCMP_CSR_CFF_SHIFT (1U)
|
|
/*! CFF - Analog Comparator Flag Falling
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
*/
|
|
#define LPCMP_CSR_CFF(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_CFF_SHIFT)) & LPCMP_CSR_CFF_MASK)
|
|
|
|
#define LPCMP_CSR_RRF_MASK (0x4U)
|
|
#define LPCMP_CSR_RRF_SHIFT (2U)
|
|
/*! RRF - Round-Robin Flag
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
*/
|
|
#define LPCMP_CSR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_RRF_SHIFT)) & LPCMP_CSR_RRF_MASK)
|
|
|
|
#define LPCMP_CSR_COUT_MASK (0x100U)
|
|
#define LPCMP_CSR_COUT_SHIFT (8U)
|
|
/*! COUT - Analog Comparator Output */
|
|
#define LPCMP_CSR_COUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_COUT_SHIFT)) & LPCMP_CSR_COUT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RRCR0 - Round Robin Control Register 0 */
|
|
/*! @{ */
|
|
|
|
#define LPCMP_RRCR0_RR_EN_MASK (0x1U)
|
|
#define LPCMP_RRCR0_RR_EN_SHIFT (0U)
|
|
/*! RR_EN - Round-Robin Enable
|
|
* 0b1..Enables
|
|
* 0b0..Disables
|
|
*/
|
|
#define LPCMP_RRCR0_RR_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EN_SHIFT)) & LPCMP_RRCR0_RR_EN_MASK)
|
|
|
|
#define LPCMP_RRCR0_RR_TRG_SEL_MASK (0x2U)
|
|
#define LPCMP_RRCR0_RR_TRG_SEL_SHIFT (1U)
|
|
/*! RR_TRG_SEL - Round-Robin Trigger Select
|
|
* 0b0..External trigger
|
|
* 0b1..Internal trigger
|
|
*/
|
|
#define LPCMP_RRCR0_RR_TRG_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_TRG_SEL_SHIFT)) & LPCMP_RRCR0_RR_TRG_SEL_MASK)
|
|
|
|
#define LPCMP_RRCR0_RR_EXTTRG_SEL_MASK (0x3CU)
|
|
#define LPCMP_RRCR0_RR_EXTTRG_SEL_SHIFT (2U)
|
|
/*! RR_EXTTRG_SEL - Select the External Trigger Source
|
|
* 0b0000..Select external trigger source 0
|
|
* 0b0001..Select external trigger source 1
|
|
* 0b0010..Select external trigger source 2
|
|
* 0b0011..Select external trigger source 3
|
|
* 0b0100..Select external trigger source 4
|
|
* 0b0101..Select external trigger source 5
|
|
* 0b0110..Select external trigger source 6
|
|
* 0b0111..Select external trigger source 7
|
|
* 0b1000..Select external trigger source 8
|
|
* 0b1001..Select external trigger source 9
|
|
* 0b1010..Select external trigger source 10
|
|
* 0b1011..Select external trigger source 11
|
|
* 0b1100..Select external trigger source 12
|
|
* 0b1101..Select external trigger source 13
|
|
* 0b1110..Select external trigger source 14
|
|
* 0b1111..Select external trigger source 15
|
|
*/
|
|
#define LPCMP_RRCR0_RR_EXTTRG_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EXTTRG_SEL_SHIFT)) & LPCMP_RRCR0_RR_EXTTRG_SEL_MASK)
|
|
|
|
#define LPCMP_RRCR0_RR_NSAM_MASK (0x300U)
|
|
#define LPCMP_RRCR0_RR_NSAM_SHIFT (8U)
|
|
/*! RR_NSAM - Number of Sample Clocks
|
|
* 0b00..0 clock
|
|
* 0b01..1 clock
|
|
* 0b10..2 clocks
|
|
* 0b11..3 clocks
|
|
*/
|
|
#define LPCMP_RRCR0_RR_NSAM(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_NSAM_SHIFT)) & LPCMP_RRCR0_RR_NSAM_MASK)
|
|
|
|
#define LPCMP_RRCR0_RR_CLK_SEL_MASK (0x3000U)
|
|
#define LPCMP_RRCR0_RR_CLK_SEL_SHIFT (12U)
|
|
/*! RR_CLK_SEL - Round Robin Clock Source Select
|
|
* 0b00..Select Round Robin clock Source 0
|
|
* 0b01..Select Round Robin clock Source 1
|
|
* 0b10..Select Round Robin clock Source 2
|
|
* 0b11..Select Round Robin clock Source 3
|
|
*/
|
|
#define LPCMP_RRCR0_RR_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_CLK_SEL_SHIFT)) & LPCMP_RRCR0_RR_CLK_SEL_MASK)
|
|
|
|
#define LPCMP_RRCR0_RR_INITMOD_MASK (0x3F0000U)
|
|
#define LPCMP_RRCR0_RR_INITMOD_SHIFT (16U)
|
|
/*! RR_INITMOD - Initialization Delay Modulus
|
|
* 0b000000..63 cycles (same as 111111b)
|
|
* 0b000001-0b111111..1 to 63 cycles
|
|
*/
|
|
#define LPCMP_RRCR0_RR_INITMOD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_INITMOD_SHIFT)) & LPCMP_RRCR0_RR_INITMOD_MASK)
|
|
|
|
#define LPCMP_RRCR0_RR_SAMPLE_CNT_MASK (0xF000000U)
|
|
#define LPCMP_RRCR0_RR_SAMPLE_CNT_SHIFT (24U)
|
|
/*! RR_SAMPLE_CNT - Number of Sample for One Channel
|
|
* 0b0000..1 samples
|
|
* 0b0001..2 samples
|
|
* 0b0010..3 samples
|
|
* 0b0011..4 samples
|
|
* 0b0100..5 samples
|
|
* 0b0101..6 samples
|
|
* 0b0110..7 samples
|
|
* 0b0111..8 samples
|
|
* 0b1000..9 samples
|
|
* 0b1001..10 samples
|
|
* 0b1010..11 samples
|
|
* 0b1011..12 samples
|
|
* 0b1100..13 samples
|
|
* 0b1101..14 samples
|
|
* 0b1110..15 samples
|
|
* 0b1111..16 samples
|
|
*/
|
|
#define LPCMP_RRCR0_RR_SAMPLE_CNT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_SAMPLE_CNT_SHIFT)) & LPCMP_RRCR0_RR_SAMPLE_CNT_MASK)
|
|
|
|
#define LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_MASK (0xF0000000U)
|
|
#define LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_SHIFT (28U)
|
|
/*! RR_SAMPLE_THRESHOLD - Sample Time Threshold
|
|
* 0b0000..At least 1 sampled "1", the final result is "1"
|
|
* 0b0001..At least 2 sampled "1", the final result is "1"
|
|
* 0b0010..At least 3 sampled "1", the final result is "1"
|
|
* 0b0011..At least 4 sampled "1", the final result is "1"
|
|
* 0b0100..At least 5 sampled "1", the final result is "1"
|
|
* 0b0101..At least 6 sampled "1", the final result is "1"
|
|
* 0b0110..At least 7 sampled "1", the final result is "1"
|
|
* 0b0111..At least 8 sampled "1", the final result is "1"
|
|
* 0b1000..At least 9 sampled "1", the final result is "1"
|
|
* 0b1001..At least 10 sampled "1", the final result is "1"
|
|
* 0b1010..At least 11 sampled "1", the final result is "1"
|
|
* 0b1011..At least 12 sampled "1", the final result is "1"
|
|
* 0b1100..At least 13 sampled "1", the final result is "1"
|
|
* 0b1101..At least 14 sampled "1", the final result is "1"
|
|
* 0b1110..At least 15 sampled "1", the final result is "1"
|
|
* 0b1111..At least 16 sampled "1", the final result is "1"
|
|
*/
|
|
#define LPCMP_RRCR0_RR_SAMPLE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_SHIFT)) & LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RRCR1 - Round Robin Control Register 1 */
|
|
/*! @{ */
|
|
|
|
#define LPCMP_RRCR1_RR_CH0EN_MASK (0x1U)
|
|
#define LPCMP_RRCR1_RR_CH0EN_SHIFT (0U)
|
|
/*! RR_CH0EN - Channel 0 Input Enable in Trigger Mode
|
|
* 0b1..Enables
|
|
* 0b0..Disables
|
|
*/
|
|
#define LPCMP_RRCR1_RR_CH0EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH0EN_SHIFT)) & LPCMP_RRCR1_RR_CH0EN_MASK)
|
|
|
|
#define LPCMP_RRCR1_RR_CH1EN_MASK (0x2U)
|
|
#define LPCMP_RRCR1_RR_CH1EN_SHIFT (1U)
|
|
/*! RR_CH1EN - Channel 1 Input Enable in Trigger Mode
|
|
* 0b1..Enables
|
|
* 0b0..Disables
|
|
*/
|
|
#define LPCMP_RRCR1_RR_CH1EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH1EN_SHIFT)) & LPCMP_RRCR1_RR_CH1EN_MASK)
|
|
|
|
#define LPCMP_RRCR1_RR_CH2EN_MASK (0x4U)
|
|
#define LPCMP_RRCR1_RR_CH2EN_SHIFT (2U)
|
|
/*! RR_CH2EN - Channel 2 Input Enable in Trigger Mode
|
|
* 0b1..Enables
|
|
* 0b0..Disables
|
|
*/
|
|
#define LPCMP_RRCR1_RR_CH2EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH2EN_SHIFT)) & LPCMP_RRCR1_RR_CH2EN_MASK)
|
|
|
|
#define LPCMP_RRCR1_RR_CH3EN_MASK (0x8U)
|
|
#define LPCMP_RRCR1_RR_CH3EN_SHIFT (3U)
|
|
/*! RR_CH3EN - Channel 3 Input Enable in Trigger Mode
|
|
* 0b1..Enables
|
|
* 0b0..Disables
|
|
*/
|
|
#define LPCMP_RRCR1_RR_CH3EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH3EN_SHIFT)) & LPCMP_RRCR1_RR_CH3EN_MASK)
|
|
|
|
#define LPCMP_RRCR1_RR_CH4EN_MASK (0x10U)
|
|
#define LPCMP_RRCR1_RR_CH4EN_SHIFT (4U)
|
|
/*! RR_CH4EN - Channel 4 Input Enable in Trigger Mode
|
|
* 0b1..Enables
|
|
* 0b0..Disables
|
|
*/
|
|
#define LPCMP_RRCR1_RR_CH4EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH4EN_SHIFT)) & LPCMP_RRCR1_RR_CH4EN_MASK)
|
|
|
|
#define LPCMP_RRCR1_RR_CH5EN_MASK (0x20U)
|
|
#define LPCMP_RRCR1_RR_CH5EN_SHIFT (5U)
|
|
/*! RR_CH5EN - Channel 5 Input Enable in Trigger Mode
|
|
* 0b1..Enables
|
|
* 0b0..Disables
|
|
*/
|
|
#define LPCMP_RRCR1_RR_CH5EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH5EN_SHIFT)) & LPCMP_RRCR1_RR_CH5EN_MASK)
|
|
|
|
#define LPCMP_RRCR1_RR_CH6EN_MASK (0x40U)
|
|
#define LPCMP_RRCR1_RR_CH6EN_SHIFT (6U)
|
|
/*! RR_CH6EN - Channel 6 Input Enable in Trigger Mode
|
|
* 0b1..Enables
|
|
* 0b0..Disables
|
|
*/
|
|
#define LPCMP_RRCR1_RR_CH6EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH6EN_SHIFT)) & LPCMP_RRCR1_RR_CH6EN_MASK)
|
|
|
|
#define LPCMP_RRCR1_RR_CH7EN_MASK (0x80U)
|
|
#define LPCMP_RRCR1_RR_CH7EN_SHIFT (7U)
|
|
/*! RR_CH7EN - Channel 7 Input Enable in Trigger Mode
|
|
* 0b1..Enables
|
|
* 0b0..Disables
|
|
*/
|
|
#define LPCMP_RRCR1_RR_CH7EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH7EN_SHIFT)) & LPCMP_RRCR1_RR_CH7EN_MASK)
|
|
|
|
#define LPCMP_RRCR1_FIXP_MASK (0x10000U)
|
|
#define LPCMP_RRCR1_FIXP_SHIFT (16U)
|
|
/*! FIXP - Fixed Port
|
|
* 0b0..Fix the plus port. Sweep only the inputs to the minus port.
|
|
* 0b1..Fix the minus port. Sweep only the inputs to the plus port.
|
|
*/
|
|
#define LPCMP_RRCR1_FIXP(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_FIXP_SHIFT)) & LPCMP_RRCR1_FIXP_MASK)
|
|
|
|
#define LPCMP_RRCR1_FIXCH_MASK (0x700000U)
|
|
#define LPCMP_RRCR1_FIXCH_SHIFT (20U)
|
|
/*! FIXCH - Fixed Channel Select
|
|
* 0b000..Channel 0
|
|
* 0b001..Channel 1
|
|
* 0b010..Channel 2
|
|
* 0b011..Channel 3
|
|
* 0b100..Channel 4
|
|
* 0b101..Channel 5
|
|
* 0b110..Channel 6
|
|
* 0b111..Channel 7
|
|
*/
|
|
#define LPCMP_RRCR1_FIXCH(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_FIXCH_SHIFT)) & LPCMP_RRCR1_FIXCH_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RRCSR - Round Robin Control and Status */
|
|
/*! @{ */
|
|
|
|
#define LPCMP_RRCSR_RR_CH0OUT_MASK (0x1U)
|
|
#define LPCMP_RRCSR_RR_CH0OUT_SHIFT (0U)
|
|
/*! RR_CH0OUT - Comparison Result for Channel 0 */
|
|
#define LPCMP_RRCSR_RR_CH0OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH0OUT_SHIFT)) & LPCMP_RRCSR_RR_CH0OUT_MASK)
|
|
|
|
#define LPCMP_RRCSR_RR_CH1OUT_MASK (0x2U)
|
|
#define LPCMP_RRCSR_RR_CH1OUT_SHIFT (1U)
|
|
/*! RR_CH1OUT - Comparison Result for Channel 1 */
|
|
#define LPCMP_RRCSR_RR_CH1OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH1OUT_SHIFT)) & LPCMP_RRCSR_RR_CH1OUT_MASK)
|
|
|
|
#define LPCMP_RRCSR_RR_CH2OUT_MASK (0x4U)
|
|
#define LPCMP_RRCSR_RR_CH2OUT_SHIFT (2U)
|
|
/*! RR_CH2OUT - Comparison Result for Channel 2 */
|
|
#define LPCMP_RRCSR_RR_CH2OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH2OUT_SHIFT)) & LPCMP_RRCSR_RR_CH2OUT_MASK)
|
|
|
|
#define LPCMP_RRCSR_RR_CH3OUT_MASK (0x8U)
|
|
#define LPCMP_RRCSR_RR_CH3OUT_SHIFT (3U)
|
|
/*! RR_CH3OUT - Comparison Result for Channel 3 */
|
|
#define LPCMP_RRCSR_RR_CH3OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH3OUT_SHIFT)) & LPCMP_RRCSR_RR_CH3OUT_MASK)
|
|
|
|
#define LPCMP_RRCSR_RR_CH4OUT_MASK (0x10U)
|
|
#define LPCMP_RRCSR_RR_CH4OUT_SHIFT (4U)
|
|
/*! RR_CH4OUT - Comparison Result for Channel 4 */
|
|
#define LPCMP_RRCSR_RR_CH4OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH4OUT_SHIFT)) & LPCMP_RRCSR_RR_CH4OUT_MASK)
|
|
|
|
#define LPCMP_RRCSR_RR_CH5OUT_MASK (0x20U)
|
|
#define LPCMP_RRCSR_RR_CH5OUT_SHIFT (5U)
|
|
/*! RR_CH5OUT - Comparison Result for Channel 5 */
|
|
#define LPCMP_RRCSR_RR_CH5OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH5OUT_SHIFT)) & LPCMP_RRCSR_RR_CH5OUT_MASK)
|
|
|
|
#define LPCMP_RRCSR_RR_CH6OUT_MASK (0x40U)
|
|
#define LPCMP_RRCSR_RR_CH6OUT_SHIFT (6U)
|
|
/*! RR_CH6OUT - Comparison Result for Channel 6 */
|
|
#define LPCMP_RRCSR_RR_CH6OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH6OUT_SHIFT)) & LPCMP_RRCSR_RR_CH6OUT_MASK)
|
|
|
|
#define LPCMP_RRCSR_RR_CH7OUT_MASK (0x80U)
|
|
#define LPCMP_RRCSR_RR_CH7OUT_SHIFT (7U)
|
|
/*! RR_CH7OUT - Comparison Result for Channel 7 */
|
|
#define LPCMP_RRCSR_RR_CH7OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH7OUT_SHIFT)) & LPCMP_RRCSR_RR_CH7OUT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RRSR - Round Robin Status */
|
|
/*! @{ */
|
|
|
|
#define LPCMP_RRSR_RR_CH0F_MASK (0x1U)
|
|
#define LPCMP_RRSR_RR_CH0F_SHIFT (0U)
|
|
/*! RR_CH0F - Channel 0 Input Changed Flag
|
|
* 0b0..Not different
|
|
* 0b1..Different
|
|
*/
|
|
#define LPCMP_RRSR_RR_CH0F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH0F_SHIFT)) & LPCMP_RRSR_RR_CH0F_MASK)
|
|
|
|
#define LPCMP_RRSR_RR_CH1F_MASK (0x2U)
|
|
#define LPCMP_RRSR_RR_CH1F_SHIFT (1U)
|
|
/*! RR_CH1F - Channel 1 Input Changed Flag
|
|
* 0b0..Not different
|
|
* 0b1..Different
|
|
*/
|
|
#define LPCMP_RRSR_RR_CH1F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH1F_SHIFT)) & LPCMP_RRSR_RR_CH1F_MASK)
|
|
|
|
#define LPCMP_RRSR_RR_CH2F_MASK (0x4U)
|
|
#define LPCMP_RRSR_RR_CH2F_SHIFT (2U)
|
|
/*! RR_CH2F - Channel 2 Input Changed Flag
|
|
* 0b0..Not different
|
|
* 0b1..Different
|
|
*/
|
|
#define LPCMP_RRSR_RR_CH2F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH2F_SHIFT)) & LPCMP_RRSR_RR_CH2F_MASK)
|
|
|
|
#define LPCMP_RRSR_RR_CH3F_MASK (0x8U)
|
|
#define LPCMP_RRSR_RR_CH3F_SHIFT (3U)
|
|
/*! RR_CH3F - Channel 3 Input Changed Flag
|
|
* 0b0..Not different
|
|
* 0b1..Different
|
|
*/
|
|
#define LPCMP_RRSR_RR_CH3F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH3F_SHIFT)) & LPCMP_RRSR_RR_CH3F_MASK)
|
|
|
|
#define LPCMP_RRSR_RR_CH4F_MASK (0x10U)
|
|
#define LPCMP_RRSR_RR_CH4F_SHIFT (4U)
|
|
/*! RR_CH4F - Channel 4 Input Changed Flag
|
|
* 0b0..Not different
|
|
* 0b1..Different
|
|
*/
|
|
#define LPCMP_RRSR_RR_CH4F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH4F_SHIFT)) & LPCMP_RRSR_RR_CH4F_MASK)
|
|
|
|
#define LPCMP_RRSR_RR_CH5F_MASK (0x20U)
|
|
#define LPCMP_RRSR_RR_CH5F_SHIFT (5U)
|
|
/*! RR_CH5F - Channel 5 Input Changed Flag
|
|
* 0b0..Not different
|
|
* 0b1..Different
|
|
*/
|
|
#define LPCMP_RRSR_RR_CH5F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH5F_SHIFT)) & LPCMP_RRSR_RR_CH5F_MASK)
|
|
|
|
#define LPCMP_RRSR_RR_CH6F_MASK (0x40U)
|
|
#define LPCMP_RRSR_RR_CH6F_SHIFT (6U)
|
|
/*! RR_CH6F - Channel 6 Input Changed Flag
|
|
* 0b0..Not different
|
|
* 0b1..Different
|
|
*/
|
|
#define LPCMP_RRSR_RR_CH6F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH6F_SHIFT)) & LPCMP_RRSR_RR_CH6F_MASK)
|
|
|
|
#define LPCMP_RRSR_RR_CH7F_MASK (0x80U)
|
|
#define LPCMP_RRSR_RR_CH7F_SHIFT (7U)
|
|
/*! RR_CH7F - Channel 7 Input Changed Flag
|
|
* 0b0..Not different
|
|
* 0b1..Different
|
|
*/
|
|
#define LPCMP_RRSR_RR_CH7F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH7F_SHIFT)) & LPCMP_RRSR_RR_CH7F_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RRCR2 - Round Robin Control Register 2 */
|
|
/*! @{ */
|
|
|
|
#define LPCMP_RRCR2_RR_TIMER_RELOAD_MASK (0xFFFFFFFU)
|
|
#define LPCMP_RRCR2_RR_TIMER_RELOAD_SHIFT (0U)
|
|
/*! RR_TIMER_RELOAD - Number of Sample Clocks */
|
|
#define LPCMP_RRCR2_RR_TIMER_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR2_RR_TIMER_RELOAD_SHIFT)) & LPCMP_RRCR2_RR_TIMER_RELOAD_MASK)
|
|
|
|
#define LPCMP_RRCR2_RR_TIMER_EN_MASK (0x80000000U)
|
|
#define LPCMP_RRCR2_RR_TIMER_EN_SHIFT (31U)
|
|
/*! RR_TIMER_EN - Round-Robin Internal Timer Enable
|
|
* 0b0..Disables
|
|
* 0b1..Enables
|
|
*/
|
|
#define LPCMP_RRCR2_RR_TIMER_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR2_RR_TIMER_EN_SHIFT)) & LPCMP_RRCR2_RR_TIMER_EN_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group LPCMP_Register_Masks */
|
|
|
|
|
|
/* LPCMP - Peripheral instance base addresses */
|
|
/** Peripheral CMP0 base address */
|
|
#define CMP0_BASE (0x400B1000u)
|
|
/** Peripheral CMP0 base pointer */
|
|
#define CMP0 ((LPCMP_Type *)CMP0_BASE)
|
|
/** Peripheral CMP1 base address */
|
|
#define CMP1_BASE (0x400B2000u)
|
|
/** Peripheral CMP1 base pointer */
|
|
#define CMP1 ((LPCMP_Type *)CMP1_BASE)
|
|
/** Array initializer of LPCMP peripheral base addresses */
|
|
#define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE }
|
|
/** Array initializer of LPCMP peripheral base pointers */
|
|
#define LPCMP_BASE_PTRS { CMP0, CMP1 }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group LPCMP_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- LPI2C Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** LPI2C - Register Layout Typedef */
|
|
typedef struct {
|
|
__I uint32_t VERID; /**< Version ID, offset: 0x0 */
|
|
__I uint32_t PARAM; /**< Parameter, offset: 0x4 */
|
|
uint8_t RESERVED_0[8];
|
|
__IO uint32_t MCR; /**< Controller Control, offset: 0x10 */
|
|
__IO uint32_t MSR; /**< Controller Status, offset: 0x14 */
|
|
__IO uint32_t MIER; /**< Controller Interrupt Enable, offset: 0x18 */
|
|
__IO uint32_t MDER; /**< Controller DMA Enable, offset: 0x1C */
|
|
__IO uint32_t MCFGR0; /**< Controller Configuration 0, offset: 0x20 */
|
|
__IO uint32_t MCFGR1; /**< Controller Configuration 1, offset: 0x24 */
|
|
__IO uint32_t MCFGR2; /**< Controller Configuration 2, offset: 0x28 */
|
|
__IO uint32_t MCFGR3; /**< Controller Configuration 3, offset: 0x2C */
|
|
uint8_t RESERVED_1[16];
|
|
__IO uint32_t MDMR; /**< Controller Data Match, offset: 0x40 */
|
|
uint8_t RESERVED_2[4];
|
|
__IO uint32_t MCCR0; /**< Controller Clock Configuration 0, offset: 0x48 */
|
|
uint8_t RESERVED_3[4];
|
|
__IO uint32_t MCCR1; /**< Controller Clock Configuration 1, offset: 0x50 */
|
|
uint8_t RESERVED_4[4];
|
|
__IO uint32_t MFCR; /**< Controller FIFO Control, offset: 0x58 */
|
|
__I uint32_t MFSR; /**< Controller FIFO Status, offset: 0x5C */
|
|
__O uint32_t MTDR; /**< Controller Transmit Data, offset: 0x60 */
|
|
uint8_t RESERVED_5[12];
|
|
__I uint32_t MRDR; /**< Controller Receive Data, offset: 0x70 */
|
|
uint8_t RESERVED_6[4];
|
|
__I uint32_t MRDROR; /**< Controller Receive Data Read Only, offset: 0x78 */
|
|
uint8_t RESERVED_7[148];
|
|
__IO uint32_t SCR; /**< Target Control, offset: 0x110 */
|
|
__IO uint32_t SSR; /**< Target Status, offset: 0x114 */
|
|
__IO uint32_t SIER; /**< Target Interrupt Enable, offset: 0x118 */
|
|
__IO uint32_t SDER; /**< Target DMA Enable, offset: 0x11C */
|
|
__IO uint32_t SCFGR0; /**< Target Configuration 0, offset: 0x120 */
|
|
__IO uint32_t SCFGR1; /**< Target Configuration 1, offset: 0x124 */
|
|
__IO uint32_t SCFGR2; /**< Target Configuration 2, offset: 0x128 */
|
|
uint8_t RESERVED_8[20];
|
|
__IO uint32_t SAMR; /**< Target Address Match, offset: 0x140 */
|
|
uint8_t RESERVED_9[12];
|
|
__I uint32_t SASR; /**< Target Address Status, offset: 0x150 */
|
|
__IO uint32_t STAR; /**< Target Transmit ACK, offset: 0x154 */
|
|
uint8_t RESERVED_10[8];
|
|
__O uint32_t STDR; /**< Target Transmit Data, offset: 0x160 */
|
|
uint8_t RESERVED_11[12];
|
|
__I uint32_t SRDR; /**< Target Receive Data, offset: 0x170 */
|
|
uint8_t RESERVED_12[4];
|
|
__I uint32_t SRDROR; /**< Target Receive Data Read Only, offset: 0x178 */
|
|
} LPI2C_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- LPI2C Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup LPI2C_Register_Masks LPI2C Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name VERID - Version ID */
|
|
/*! @{ */
|
|
|
|
#define LPI2C_VERID_FEATURE_MASK (0xFFFFU)
|
|
#define LPI2C_VERID_FEATURE_SHIFT (0U)
|
|
/*! FEATURE - Feature Specification Number
|
|
* 0b0000000000000010..Controller only, with standard feature set
|
|
* 0b0000000000000011..Controller and target, with standard feature set
|
|
*/
|
|
#define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)
|
|
|
|
#define LPI2C_VERID_MINOR_MASK (0xFF0000U)
|
|
#define LPI2C_VERID_MINOR_SHIFT (16U)
|
|
/*! MINOR - Minor Version Number */
|
|
#define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)
|
|
|
|
#define LPI2C_VERID_MAJOR_MASK (0xFF000000U)
|
|
#define LPI2C_VERID_MAJOR_SHIFT (24U)
|
|
/*! MAJOR - Major Version Number */
|
|
#define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PARAM - Parameter */
|
|
/*! @{ */
|
|
|
|
#define LPI2C_PARAM_MTXFIFO_MASK (0xFU)
|
|
#define LPI2C_PARAM_MTXFIFO_SHIFT (0U)
|
|
/*! MTXFIFO - Controller Transmit FIFO Size */
|
|
#define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)
|
|
|
|
#define LPI2C_PARAM_MRXFIFO_MASK (0xF00U)
|
|
#define LPI2C_PARAM_MRXFIFO_SHIFT (8U)
|
|
/*! MRXFIFO - Controller Receive FIFO Size */
|
|
#define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MCR - Controller Control */
|
|
/*! @{ */
|
|
|
|
#define LPI2C_MCR_MEN_MASK (0x1U)
|
|
#define LPI2C_MCR_MEN_SHIFT (0U)
|
|
/*! MEN - Controller Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)
|
|
|
|
#define LPI2C_MCR_RST_MASK (0x2U)
|
|
#define LPI2C_MCR_RST_SHIFT (1U)
|
|
/*! RST - Software Reset
|
|
* 0b0..No effect
|
|
* 0b1..Reset
|
|
*/
|
|
#define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)
|
|
|
|
#define LPI2C_MCR_DOZEN_MASK (0x4U)
|
|
#define LPI2C_MCR_DOZEN_SHIFT (2U)
|
|
/*! DOZEN - Doze Mode Enable
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)
|
|
|
|
#define LPI2C_MCR_DBGEN_MASK (0x8U)
|
|
#define LPI2C_MCR_DBGEN_SHIFT (3U)
|
|
/*! DBGEN - Debug Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)
|
|
|
|
#define LPI2C_MCR_RTF_MASK (0x100U)
|
|
#define LPI2C_MCR_RTF_SHIFT (8U)
|
|
/*! RTF - Reset Transmit FIFO
|
|
* 0b0..No effect
|
|
* 0b1..Reset transmit FIFO
|
|
*/
|
|
#define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)
|
|
|
|
#define LPI2C_MCR_RRF_MASK (0x200U)
|
|
#define LPI2C_MCR_RRF_SHIFT (9U)
|
|
/*! RRF - Reset Receive FIFO
|
|
* 0b0..No effect
|
|
* 0b1..Reset receive FIFO
|
|
*/
|
|
#define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MSR - Controller Status */
|
|
/*! @{ */
|
|
|
|
#define LPI2C_MSR_TDF_MASK (0x1U)
|
|
#define LPI2C_MSR_TDF_SHIFT (0U)
|
|
/*! TDF - Transmit Data Flag
|
|
* 0b0..Transmit data not requested
|
|
* 0b1..Transmit data requested
|
|
*/
|
|
#define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)
|
|
|
|
#define LPI2C_MSR_RDF_MASK (0x2U)
|
|
#define LPI2C_MSR_RDF_SHIFT (1U)
|
|
/*! RDF - Receive Data Flag
|
|
* 0b0..Receive data not ready
|
|
* 0b1..Receive data ready
|
|
*/
|
|
#define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)
|
|
|
|
#define LPI2C_MSR_EPF_MASK (0x100U)
|
|
#define LPI2C_MSR_EPF_SHIFT (8U)
|
|
/*! EPF - End Packet Flag
|
|
* 0b0..No Stop or repeated Start generated
|
|
* 0b1..Stop or repeated Start generated
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)
|
|
|
|
#define LPI2C_MSR_SDF_MASK (0x200U)
|
|
#define LPI2C_MSR_SDF_SHIFT (9U)
|
|
/*! SDF - Stop Detect Flag
|
|
* 0b0..No Stop condition generated
|
|
* 0b1..Stop condition generated
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)
|
|
|
|
#define LPI2C_MSR_NDF_MASK (0x400U)
|
|
#define LPI2C_MSR_NDF_SHIFT (10U)
|
|
/*! NDF - NACK Detect Flag
|
|
* 0b0..No unexpected NACK detected
|
|
* 0b1..Unexpected NACK detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)
|
|
|
|
#define LPI2C_MSR_ALF_MASK (0x800U)
|
|
#define LPI2C_MSR_ALF_SHIFT (11U)
|
|
/*! ALF - Arbitration Lost Flag
|
|
* 0b0..Controller did not lose arbitration
|
|
* 0b1..Controller lost arbitration
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)
|
|
|
|
#define LPI2C_MSR_FEF_MASK (0x1000U)
|
|
#define LPI2C_MSR_FEF_SHIFT (12U)
|
|
/*! FEF - FIFO Error Flag
|
|
* 0b0..No FIFO error
|
|
* 0b1..FIFO error
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)
|
|
|
|
#define LPI2C_MSR_PLTF_MASK (0x2000U)
|
|
#define LPI2C_MSR_PLTF_SHIFT (13U)
|
|
/*! PLTF - Pin Low Timeout Flag
|
|
* 0b0..Pin low timeout did not occur
|
|
* 0b1..Pin low timeout occurred
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)
|
|
|
|
#define LPI2C_MSR_DMF_MASK (0x4000U)
|
|
#define LPI2C_MSR_DMF_SHIFT (14U)
|
|
/*! DMF - Data Match Flag
|
|
* 0b0..Matching data not received
|
|
* 0b1..Matching data received
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)
|
|
|
|
#define LPI2C_MSR_STF_MASK (0x8000U)
|
|
#define LPI2C_MSR_STF_SHIFT (15U)
|
|
/*! STF - Start Flag
|
|
* 0b0..Start condition not detected
|
|
* 0b1..Start condition detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define LPI2C_MSR_STF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_STF_SHIFT)) & LPI2C_MSR_STF_MASK)
|
|
|
|
#define LPI2C_MSR_MBF_MASK (0x1000000U)
|
|
#define LPI2C_MSR_MBF_SHIFT (24U)
|
|
/*! MBF - Controller Busy Flag
|
|
* 0b0..Idle
|
|
* 0b1..Busy
|
|
*/
|
|
#define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)
|
|
|
|
#define LPI2C_MSR_BBF_MASK (0x2000000U)
|
|
#define LPI2C_MSR_BBF_SHIFT (25U)
|
|
/*! BBF - Bus Busy Flag
|
|
* 0b0..Idle
|
|
* 0b1..Busy
|
|
*/
|
|
#define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MIER - Controller Interrupt Enable */
|
|
/*! @{ */
|
|
|
|
#define LPI2C_MIER_TDIE_MASK (0x1U)
|
|
#define LPI2C_MIER_TDIE_SHIFT (0U)
|
|
/*! TDIE - Transmit Data Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)
|
|
|
|
#define LPI2C_MIER_RDIE_MASK (0x2U)
|
|
#define LPI2C_MIER_RDIE_SHIFT (1U)
|
|
/*! RDIE - Receive Data Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)
|
|
|
|
#define LPI2C_MIER_EPIE_MASK (0x100U)
|
|
#define LPI2C_MIER_EPIE_SHIFT (8U)
|
|
/*! EPIE - End Packet Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)
|
|
|
|
#define LPI2C_MIER_SDIE_MASK (0x200U)
|
|
#define LPI2C_MIER_SDIE_SHIFT (9U)
|
|
/*! SDIE - Stop Detect Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)
|
|
|
|
#define LPI2C_MIER_NDIE_MASK (0x400U)
|
|
#define LPI2C_MIER_NDIE_SHIFT (10U)
|
|
/*! NDIE - NACK Detect Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)
|
|
|
|
#define LPI2C_MIER_ALIE_MASK (0x800U)
|
|
#define LPI2C_MIER_ALIE_SHIFT (11U)
|
|
/*! ALIE - Arbitration Lost Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)
|
|
|
|
#define LPI2C_MIER_FEIE_MASK (0x1000U)
|
|
#define LPI2C_MIER_FEIE_SHIFT (12U)
|
|
/*! FEIE - FIFO Error Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)
|
|
|
|
#define LPI2C_MIER_PLTIE_MASK (0x2000U)
|
|
#define LPI2C_MIER_PLTIE_SHIFT (13U)
|
|
/*! PLTIE - Pin Low Timeout Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)
|
|
|
|
#define LPI2C_MIER_DMIE_MASK (0x4000U)
|
|
#define LPI2C_MIER_DMIE_SHIFT (14U)
|
|
/*! DMIE - Data Match Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)
|
|
|
|
#define LPI2C_MIER_STIE_MASK (0x8000U)
|
|
#define LPI2C_MIER_STIE_SHIFT (15U)
|
|
/*! STIE - Start Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPI2C_MIER_STIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_STIE_SHIFT)) & LPI2C_MIER_STIE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MDER - Controller DMA Enable */
|
|
/*! @{ */
|
|
|
|
#define LPI2C_MDER_TDDE_MASK (0x1U)
|
|
#define LPI2C_MDER_TDDE_SHIFT (0U)
|
|
/*! TDDE - Transmit Data DMA Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)
|
|
|
|
#define LPI2C_MDER_RDDE_MASK (0x2U)
|
|
#define LPI2C_MDER_RDDE_SHIFT (1U)
|
|
/*! RDDE - Receive Data DMA Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MCFGR0 - Controller Configuration 0 */
|
|
/*! @{ */
|
|
|
|
#define LPI2C_MCFGR0_HREN_MASK (0x1U)
|
|
#define LPI2C_MCFGR0_HREN_SHIFT (0U)
|
|
/*! HREN - Host Request Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)
|
|
|
|
#define LPI2C_MCFGR0_HRPOL_MASK (0x2U)
|
|
#define LPI2C_MCFGR0_HRPOL_SHIFT (1U)
|
|
/*! HRPOL - Host Request Polarity
|
|
* 0b0..Active low
|
|
* 0b1..Active high
|
|
*/
|
|
#define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)
|
|
|
|
#define LPI2C_MCFGR0_HRSEL_MASK (0x4U)
|
|
#define LPI2C_MCFGR0_HRSEL_SHIFT (2U)
|
|
/*! HRSEL - Host Request Select
|
|
* 0b0..Host request input is pin HREQ
|
|
* 0b1..Host request input is input trigger
|
|
*/
|
|
#define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)
|
|
|
|
#define LPI2C_MCFGR0_HRDIR_MASK (0x8U)
|
|
#define LPI2C_MCFGR0_HRDIR_SHIFT (3U)
|
|
/*! HRDIR - Host Request Direction
|
|
* 0b0..HREQ pin is input (for LPI2C controller)
|
|
* 0b1..HREQ pin is output (for LPI2C target)
|
|
*/
|
|
#define LPI2C_MCFGR0_HRDIR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRDIR_SHIFT)) & LPI2C_MCFGR0_HRDIR_MASK)
|
|
|
|
#define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U)
|
|
#define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U)
|
|
/*! CIRFIFO - Circular FIFO Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)
|
|
|
|
#define LPI2C_MCFGR0_RDMO_MASK (0x200U)
|
|
#define LPI2C_MCFGR0_RDMO_SHIFT (9U)
|
|
/*! RDMO - Receive Data Match Only
|
|
* 0b0..Received data is stored in the receive FIFO
|
|
* 0b1..Received data is discarded unless MSR[DMF] is set
|
|
*/
|
|
#define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)
|
|
|
|
#define LPI2C_MCFGR0_RELAX_MASK (0x10000U)
|
|
#define LPI2C_MCFGR0_RELAX_SHIFT (16U)
|
|
/*! RELAX - Relaxed Mode
|
|
* 0b0..Normal transfer
|
|
* 0b1..Relaxed transfer
|
|
*/
|
|
#define LPI2C_MCFGR0_RELAX(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RELAX_SHIFT)) & LPI2C_MCFGR0_RELAX_MASK)
|
|
|
|
#define LPI2C_MCFGR0_ABORT_MASK (0x20000U)
|
|
#define LPI2C_MCFGR0_ABORT_SHIFT (17U)
|
|
/*! ABORT - Abort Transfer
|
|
* 0b0..Normal transfer
|
|
* 0b1..Abort existing transfer and do not start a new one
|
|
*/
|
|
#define LPI2C_MCFGR0_ABORT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_ABORT_SHIFT)) & LPI2C_MCFGR0_ABORT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MCFGR1 - Controller Configuration 1 */
|
|
/*! @{ */
|
|
|
|
#define LPI2C_MCFGR1_PRESCALE_MASK (0x7U)
|
|
#define LPI2C_MCFGR1_PRESCALE_SHIFT (0U)
|
|
/*! PRESCALE - Prescaler
|
|
* 0b000..Divide by 1
|
|
* 0b001..Divide by 2
|
|
* 0b010..Divide by 4
|
|
* 0b011..Divide by 8
|
|
* 0b100..Divide by 16
|
|
* 0b101..Divide by 32
|
|
* 0b110..Divide by 64
|
|
* 0b111..Divide by 128
|
|
*/
|
|
#define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)
|
|
|
|
#define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U)
|
|
#define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U)
|
|
/*! AUTOSTOP - Automatic Stop Generation
|
|
* 0b0..No effect
|
|
* 0b1..Stop automatically generated
|
|
*/
|
|
#define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)
|
|
|
|
#define LPI2C_MCFGR1_IGNACK_MASK (0x200U)
|
|
#define LPI2C_MCFGR1_IGNACK_SHIFT (9U)
|
|
/*! IGNACK - Ignore NACK
|
|
* 0b0..No effect
|
|
* 0b1..Treat a received NACK as an ACK
|
|
*/
|
|
#define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)
|
|
|
|
#define LPI2C_MCFGR1_TIMECFG_MASK (0x400U)
|
|
#define LPI2C_MCFGR1_TIMECFG_SHIFT (10U)
|
|
/*! TIMECFG - Timeout Configuration
|
|
* 0b0..SCL
|
|
* 0b1..SCL or SDA
|
|
*/
|
|
#define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)
|
|
|
|
#define LPI2C_MCFGR1_STOPCFG_MASK (0x800U)
|
|
#define LPI2C_MCFGR1_STOPCFG_SHIFT (11U)
|
|
/*! STOPCFG - Stop Configuration
|
|
* 0b0..Any Stop condition
|
|
* 0b1..Last Stop condition
|
|
*/
|
|
#define LPI2C_MCFGR1_STOPCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STOPCFG_SHIFT)) & LPI2C_MCFGR1_STOPCFG_MASK)
|
|
|
|
#define LPI2C_MCFGR1_STARTCFG_MASK (0x1000U)
|
|
#define LPI2C_MCFGR1_STARTCFG_SHIFT (12U)
|
|
/*! STARTCFG - Start Configuration
|
|
* 0b0..Sets when both I2C bus and LPI2C controller are idle
|
|
* 0b1..Sets when I2C bus is idle
|
|
*/
|
|
#define LPI2C_MCFGR1_STARTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STARTCFG_SHIFT)) & LPI2C_MCFGR1_STARTCFG_MASK)
|
|
|
|
#define LPI2C_MCFGR1_MATCFG_MASK (0x70000U)
|
|
#define LPI2C_MCFGR1_MATCFG_SHIFT (16U)
|
|
/*! MATCFG - Match Configuration
|
|
* 0b000..Match is disabled
|
|
* 0b001..Reserved
|
|
* 0b010..Match is enabled: first data word equals MDMR[MATCH0] OR MDMR[MATCH1]
|
|
* 0b011..Match is enabled: any data word equals MDMR[MATCH0] OR MDMR[MATCH1]
|
|
* 0b100..Match is enabled: (first data word equals MDMR[MATCH0]) AND (second data word equals MDMR[MATCH1)
|
|
* 0b101..Match is enabled: (any data word equals MDMR[MATCH0]) AND (next data word equals MDMR[MATCH1)
|
|
* 0b110..Match is enabled: (first data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1])
|
|
* 0b111..Match is enabled: (any data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1])
|
|
*/
|
|
#define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)
|
|
|
|
#define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U)
|
|
#define LPI2C_MCFGR1_PINCFG_SHIFT (24U)
|
|
/*! PINCFG - Pin Configuration
|
|
* 0b000..Two-pin open drain mode
|
|
* 0b001..Two-pin output only mode (Ultra-Fast mode)
|
|
* 0b010..Two-pin push-pull mode
|
|
* 0b011..Four-pin push-pull mode
|
|
* 0b100..Two-pin open-drain mode with separate LPI2C target
|
|
* 0b101..Two-pin output only mode (Ultra-Fast mode) with separate LPI2C target
|
|
* 0b110..Two-pin push-pull mode with separate LPI2C target
|
|
* 0b111..Four-pin push-pull mode (inverted outputs)
|
|
*/
|
|
#define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MCFGR2 - Controller Configuration 2 */
|
|
/*! @{ */
|
|
|
|
#define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU)
|
|
#define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U)
|
|
/*! BUSIDLE - Bus Idle Timeout */
|
|
#define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)
|
|
|
|
#define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U)
|
|
#define LPI2C_MCFGR2_FILTSCL_SHIFT (16U)
|
|
/*! FILTSCL - Glitch Filter SCL */
|
|
#define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)
|
|
|
|
#define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U)
|
|
#define LPI2C_MCFGR2_FILTSDA_SHIFT (24U)
|
|
/*! FILTSDA - Glitch Filter SDA */
|
|
#define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MCFGR3 - Controller Configuration 3 */
|
|
/*! @{ */
|
|
|
|
#define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U)
|
|
#define LPI2C_MCFGR3_PINLOW_SHIFT (8U)
|
|
/*! PINLOW - Pin Low Timeout */
|
|
#define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MDMR - Controller Data Match */
|
|
/*! @{ */
|
|
|
|
#define LPI2C_MDMR_MATCH0_MASK (0xFFU)
|
|
#define LPI2C_MDMR_MATCH0_SHIFT (0U)
|
|
/*! MATCH0 - Match 0 Value */
|
|
#define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)
|
|
|
|
#define LPI2C_MDMR_MATCH1_MASK (0xFF0000U)
|
|
#define LPI2C_MDMR_MATCH1_SHIFT (16U)
|
|
/*! MATCH1 - Match 1 Value */
|
|
#define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MCCR0 - Controller Clock Configuration 0 */
|
|
/*! @{ */
|
|
|
|
#define LPI2C_MCCR0_CLKLO_MASK (0x3FU)
|
|
#define LPI2C_MCCR0_CLKLO_SHIFT (0U)
|
|
/*! CLKLO - Clock Low Period */
|
|
#define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)
|
|
|
|
#define LPI2C_MCCR0_CLKHI_MASK (0x3F00U)
|
|
#define LPI2C_MCCR0_CLKHI_SHIFT (8U)
|
|
/*! CLKHI - Clock High Period */
|
|
#define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)
|
|
|
|
#define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U)
|
|
#define LPI2C_MCCR0_SETHOLD_SHIFT (16U)
|
|
/*! SETHOLD - Setup Hold Delay */
|
|
#define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)
|
|
|
|
#define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U)
|
|
#define LPI2C_MCCR0_DATAVD_SHIFT (24U)
|
|
/*! DATAVD - Data Valid Delay */
|
|
#define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)
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/*! @} */
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/*! @name MCCR1 - Controller Clock Configuration 1 */
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/*! @{ */
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#define LPI2C_MCCR1_CLKLO_MASK (0x3FU)
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#define LPI2C_MCCR1_CLKLO_SHIFT (0U)
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/*! CLKLO - Clock Low Period */
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#define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)
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#define LPI2C_MCCR1_CLKHI_MASK (0x3F00U)
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#define LPI2C_MCCR1_CLKHI_SHIFT (8U)
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/*! CLKHI - Clock High Period */
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#define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)
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#define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U)
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#define LPI2C_MCCR1_SETHOLD_SHIFT (16U)
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/*! SETHOLD - Setup Hold Delay */
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#define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)
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#define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U)
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#define LPI2C_MCCR1_DATAVD_SHIFT (24U)
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/*! DATAVD - Data Valid Delay */
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#define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)
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/*! @} */
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/*! @name MFCR - Controller FIFO Control */
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/*! @{ */
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#define LPI2C_MFCR_TXWATER_MASK (0x3U)
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#define LPI2C_MFCR_TXWATER_SHIFT (0U)
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/*! TXWATER - Transmit FIFO Watermark */
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#define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)
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#define LPI2C_MFCR_RXWATER_MASK (0x30000U)
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#define LPI2C_MFCR_RXWATER_SHIFT (16U)
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/*! RXWATER - Receive FIFO Watermark */
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#define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)
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/*! @} */
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/*! @name MFSR - Controller FIFO Status */
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/*! @{ */
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#define LPI2C_MFSR_TXCOUNT_MASK (0x7U)
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#define LPI2C_MFSR_TXCOUNT_SHIFT (0U)
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/*! TXCOUNT - Transmit FIFO Count */
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#define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)
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#define LPI2C_MFSR_RXCOUNT_MASK (0x70000U)
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#define LPI2C_MFSR_RXCOUNT_SHIFT (16U)
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/*! RXCOUNT - Receive FIFO Count */
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#define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)
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/*! @} */
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/*! @name MTDR - Controller Transmit Data */
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/*! @{ */
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#define LPI2C_MTDR_DATA_MASK (0xFFU)
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#define LPI2C_MTDR_DATA_SHIFT (0U)
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/*! DATA - Transmit Data */
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#define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)
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#define LPI2C_MTDR_CMD_MASK (0x700U)
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#define LPI2C_MTDR_CMD_SHIFT (8U)
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/*! CMD - Command Data
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* 0b000..Transmit the value in DATA[7:0]
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* 0b001..Receive (DATA[7:0] + 1) bytes
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* 0b010..Generate Stop condition on I2C bus
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* 0b011..Receive and discard (DATA[7:0] + 1) bytes
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* 0b100..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0]
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* 0b101..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] (this transfer expects a NACK to be returned)
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* 0b110..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode
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* 0b111..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode (this transfer expects a NACK to be returned)
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*/
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#define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)
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/*! @} */
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/*! @name MRDR - Controller Receive Data */
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/*! @{ */
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#define LPI2C_MRDR_DATA_MASK (0xFFU)
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#define LPI2C_MRDR_DATA_SHIFT (0U)
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/*! DATA - Receive Data */
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#define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)
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#define LPI2C_MRDR_RXEMPTY_MASK (0x4000U)
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#define LPI2C_MRDR_RXEMPTY_SHIFT (14U)
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/*! RXEMPTY - Receive Empty
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* 0b0..Not empty
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* 0b1..Empty
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*/
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#define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)
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/*! @} */
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/*! @name MRDROR - Controller Receive Data Read Only */
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/*! @{ */
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#define LPI2C_MRDROR_DATA_MASK (0xFFU)
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#define LPI2C_MRDROR_DATA_SHIFT (0U)
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/*! DATA - Receive Data */
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#define LPI2C_MRDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDROR_DATA_SHIFT)) & LPI2C_MRDROR_DATA_MASK)
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#define LPI2C_MRDROR_RXEMPTY_MASK (0x4000U)
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#define LPI2C_MRDROR_RXEMPTY_SHIFT (14U)
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/*! RXEMPTY - RX Empty
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* 0b0..Not empty
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* 0b1..Empty
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*/
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#define LPI2C_MRDROR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDROR_RXEMPTY_SHIFT)) & LPI2C_MRDROR_RXEMPTY_MASK)
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/*! @} */
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/*! @name SCR - Target Control */
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/*! @{ */
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#define LPI2C_SCR_SEN_MASK (0x1U)
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#define LPI2C_SCR_SEN_SHIFT (0U)
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/*! SEN - Target Enable
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* 0b0..Disable
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* 0b1..Enable
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*/
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#define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)
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#define LPI2C_SCR_RST_MASK (0x2U)
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#define LPI2C_SCR_RST_SHIFT (1U)
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/*! RST - Software Reset
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* 0b0..Not reset
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* 0b1..Reset
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*/
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#define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)
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#define LPI2C_SCR_FILTEN_MASK (0x10U)
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#define LPI2C_SCR_FILTEN_SHIFT (4U)
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/*! FILTEN - Filter Enable
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* 0b0..Disable
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* 0b1..Enable
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*/
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#define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)
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#define LPI2C_SCR_FILTDZ_MASK (0x20U)
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#define LPI2C_SCR_FILTDZ_SHIFT (5U)
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/*! FILTDZ - Filter Doze Enable
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* 0b0..Enable
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* 0b1..Disable
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*/
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#define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)
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#define LPI2C_SCR_RTF_MASK (0x100U)
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#define LPI2C_SCR_RTF_SHIFT (8U)
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/*! RTF - Reset Transmit FIFO
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* 0b0..No effect
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* 0b1..STDR is now empty
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*/
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#define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)
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#define LPI2C_SCR_RRF_MASK (0x200U)
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#define LPI2C_SCR_RRF_SHIFT (9U)
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/*! RRF - Reset Receive FIFO
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* 0b0..No effect
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* 0b1..SRDR is now empty
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*/
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#define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)
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/*! @} */
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/*! @name SSR - Target Status */
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/*! @{ */
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#define LPI2C_SSR_TDF_MASK (0x1U)
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#define LPI2C_SSR_TDF_SHIFT (0U)
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/*! TDF - Transmit Data Flag
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* 0b0..Transmit data not requested
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* 0b1..Transmit data is requested
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*/
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#define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)
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#define LPI2C_SSR_RDF_MASK (0x2U)
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#define LPI2C_SSR_RDF_SHIFT (1U)
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/*! RDF - Receive Data Flag
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* 0b0..Not ready
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* 0b1..Ready
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*/
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#define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)
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#define LPI2C_SSR_AVF_MASK (0x4U)
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#define LPI2C_SSR_AVF_SHIFT (2U)
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/*! AVF - Address Valid Flag
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* 0b0..Not valid
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* 0b1..Valid
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*/
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#define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)
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#define LPI2C_SSR_TAF_MASK (0x8U)
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#define LPI2C_SSR_TAF_SHIFT (3U)
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/*! TAF - Transmit ACK Flag
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|
* 0b0..Not required
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|
* 0b1..Required
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*/
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#define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)
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#define LPI2C_SSR_RSF_MASK (0x100U)
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#define LPI2C_SSR_RSF_SHIFT (8U)
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/*! RSF - Repeated Start Flag
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|
* 0b0..No repeated Start detected
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* 0b1..Repeated Start detected
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|
* 0b0..No effect
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|
* 0b1..Clear the flag
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*/
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#define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)
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#define LPI2C_SSR_SDF_MASK (0x200U)
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#define LPI2C_SSR_SDF_SHIFT (9U)
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|
/*! SDF - Stop Detect Flag
|
|
* 0b0..No Stop detected
|
|
* 0b1..Stop detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
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|
*/
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|
#define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)
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|
#define LPI2C_SSR_BEF_MASK (0x400U)
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|
#define LPI2C_SSR_BEF_SHIFT (10U)
|
|
/*! BEF - Bit Error Flag
|
|
* 0b0..No bit error occurred
|
|
* 0b1..Bit error occurred
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
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|
#define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)
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|
#define LPI2C_SSR_FEF_MASK (0x800U)
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|
#define LPI2C_SSR_FEF_SHIFT (11U)
|
|
/*! FEF - FIFO Error Flag
|
|
* 0b0..No FIFO error
|
|
* 0b1..FIFO error
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)
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|
|
|
#define LPI2C_SSR_AM0F_MASK (0x1000U)
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|
#define LPI2C_SSR_AM0F_SHIFT (12U)
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|
/*! AM0F - Address Match 0 Flag
|
|
* 0b0..ADDR0 matching address not received
|
|
* 0b1..ADDR0 matching address received
|
|
*/
|
|
#define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)
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|
|
|
#define LPI2C_SSR_AM1F_MASK (0x2000U)
|
|
#define LPI2C_SSR_AM1F_SHIFT (13U)
|
|
/*! AM1F - Address Match 1 Flag
|
|
* 0b0..Matching address not received
|
|
* 0b1..Matching address received
|
|
*/
|
|
#define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)
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|
|
|
#define LPI2C_SSR_GCF_MASK (0x4000U)
|
|
#define LPI2C_SSR_GCF_SHIFT (14U)
|
|
/*! GCF - General Call Flag
|
|
* 0b0..General call address disabled or not detected
|
|
* 0b1..General call address detected
|
|
*/
|
|
#define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)
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|
|
|
#define LPI2C_SSR_SARF_MASK (0x8000U)
|
|
#define LPI2C_SSR_SARF_SHIFT (15U)
|
|
/*! SARF - SMBus Alert Response Flag
|
|
* 0b0..Disabled or not detected
|
|
* 0b1..Enabled and detected
|
|
*/
|
|
#define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)
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|
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|
#define LPI2C_SSR_SBF_MASK (0x1000000U)
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|
#define LPI2C_SSR_SBF_SHIFT (24U)
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|
/*! SBF - Target Busy Flag
|
|
* 0b0..Idle
|
|
* 0b1..Busy
|
|
*/
|
|
#define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)
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|
|
|
#define LPI2C_SSR_BBF_MASK (0x2000000U)
|
|
#define LPI2C_SSR_BBF_SHIFT (25U)
|
|
/*! BBF - Bus Busy Flag
|
|
* 0b0..Idle
|
|
* 0b1..Busy
|
|
*/
|
|
#define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SIER - Target Interrupt Enable */
|
|
/*! @{ */
|
|
|
|
#define LPI2C_SIER_TDIE_MASK (0x1U)
|
|
#define LPI2C_SIER_TDIE_SHIFT (0U)
|
|
/*! TDIE - Transmit Data Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)
|
|
|
|
#define LPI2C_SIER_RDIE_MASK (0x2U)
|
|
#define LPI2C_SIER_RDIE_SHIFT (1U)
|
|
/*! RDIE - Receive Data Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)
|
|
|
|
#define LPI2C_SIER_AVIE_MASK (0x4U)
|
|
#define LPI2C_SIER_AVIE_SHIFT (2U)
|
|
/*! AVIE - Address Valid Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)
|
|
|
|
#define LPI2C_SIER_TAIE_MASK (0x8U)
|
|
#define LPI2C_SIER_TAIE_SHIFT (3U)
|
|
/*! TAIE - Transmit ACK Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)
|
|
|
|
#define LPI2C_SIER_RSIE_MASK (0x100U)
|
|
#define LPI2C_SIER_RSIE_SHIFT (8U)
|
|
/*! RSIE - Repeated Start Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)
|
|
|
|
#define LPI2C_SIER_SDIE_MASK (0x200U)
|
|
#define LPI2C_SIER_SDIE_SHIFT (9U)
|
|
/*! SDIE - Stop Detect Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)
|
|
|
|
#define LPI2C_SIER_BEIE_MASK (0x400U)
|
|
#define LPI2C_SIER_BEIE_SHIFT (10U)
|
|
/*! BEIE - Bit Error Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)
|
|
|
|
#define LPI2C_SIER_FEIE_MASK (0x800U)
|
|
#define LPI2C_SIER_FEIE_SHIFT (11U)
|
|
/*! FEIE - FIFO Error Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)
|
|
|
|
#define LPI2C_SIER_AM0IE_MASK (0x1000U)
|
|
#define LPI2C_SIER_AM0IE_SHIFT (12U)
|
|
/*! AM0IE - Address Match 0 Interrupt Enable
|
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* 0b0..Disable
|
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* 0b1..Enable
|
|
*/
|
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#define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)
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#define LPI2C_SIER_AM1IE_MASK (0x2000U)
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#define LPI2C_SIER_AM1IE_SHIFT (13U)
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/*! AM1IE - Address Match 1 Interrupt Enable
|
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* 0b0..Disable
|
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* 0b1..Enable
|
|
*/
|
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#define LPI2C_SIER_AM1IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1IE_SHIFT)) & LPI2C_SIER_AM1IE_MASK)
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#define LPI2C_SIER_GCIE_MASK (0x4000U)
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#define LPI2C_SIER_GCIE_SHIFT (14U)
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/*! GCIE - General Call Interrupt Enable
|
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* 0b0..Disabled
|
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* 0b1..Enabled
|
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*/
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#define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)
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#define LPI2C_SIER_SARIE_MASK (0x8000U)
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#define LPI2C_SIER_SARIE_SHIFT (15U)
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/*! SARIE - SMBus Alert Response Interrupt Enable
|
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* 0b0..Disable
|
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* 0b1..Enable
|
|
*/
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#define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)
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/*! @} */
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/*! @name SDER - Target DMA Enable */
|
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/*! @{ */
|
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|
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#define LPI2C_SDER_TDDE_MASK (0x1U)
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#define LPI2C_SDER_TDDE_SHIFT (0U)
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/*! TDDE - Transmit Data DMA Enable
|
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* 0b0..Disable
|
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* 0b1..Enable
|
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*/
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#define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)
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#define LPI2C_SDER_RDDE_MASK (0x2U)
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#define LPI2C_SDER_RDDE_SHIFT (1U)
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/*! RDDE - Receive Data DMA Enable
|
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* 0b0..Disable DMA request
|
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* 0b1..Enable DMA request
|
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*/
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#define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)
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#define LPI2C_SDER_AVDE_MASK (0x4U)
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#define LPI2C_SDER_AVDE_SHIFT (2U)
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/*! AVDE - Address Valid DMA Enable
|
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* 0b0..Disable
|
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* 0b1..Enable
|
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*/
|
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#define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)
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#define LPI2C_SDER_RSDE_MASK (0x100U)
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#define LPI2C_SDER_RSDE_SHIFT (8U)
|
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/*! RSDE - Repeated Start DMA Enable
|
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* 0b0..Disable
|
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* 0b1..Enable
|
|
*/
|
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#define LPI2C_SDER_RSDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RSDE_SHIFT)) & LPI2C_SDER_RSDE_MASK)
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|
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#define LPI2C_SDER_SDDE_MASK (0x200U)
|
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#define LPI2C_SDER_SDDE_SHIFT (9U)
|
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/*! SDDE - Stop Detect DMA Enable
|
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* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPI2C_SDER_SDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_SDDE_SHIFT)) & LPI2C_SDER_SDDE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SCFGR0 - Target Configuration 0 */
|
|
/*! @{ */
|
|
|
|
#define LPI2C_SCFGR0_RDREQ_MASK (0x1U)
|
|
#define LPI2C_SCFGR0_RDREQ_SHIFT (0U)
|
|
/*! RDREQ - Read Request
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPI2C_SCFGR0_RDREQ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR0_RDREQ_SHIFT)) & LPI2C_SCFGR0_RDREQ_MASK)
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|
|
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#define LPI2C_SCFGR0_RDACK_MASK (0x2U)
|
|
#define LPI2C_SCFGR0_RDACK_SHIFT (1U)
|
|
/*! RDACK - Read Acknowledge Flag
|
|
* 0b0..Read Request not acknowledged
|
|
* 0b1..Read Request acknowledged
|
|
*/
|
|
#define LPI2C_SCFGR0_RDACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR0_RDACK_SHIFT)) & LPI2C_SCFGR0_RDACK_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SCFGR1 - Target Configuration 1 */
|
|
/*! @{ */
|
|
|
|
#define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U)
|
|
#define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U)
|
|
/*! ADRSTALL - Address SCL Stall
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)
|
|
|
|
#define LPI2C_SCFGR1_RXSTALL_MASK (0x2U)
|
|
#define LPI2C_SCFGR1_RXSTALL_SHIFT (1U)
|
|
/*! RXSTALL - RX SCL Stall
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)
|
|
|
|
#define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U)
|
|
#define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U)
|
|
/*! TXDSTALL - Transmit Data SCL Stall
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)
|
|
|
|
#define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U)
|
|
#define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U)
|
|
/*! ACKSTALL - ACK SCL Stall
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)
|
|
|
|
#define LPI2C_SCFGR1_RXNACK_MASK (0x10U)
|
|
#define LPI2C_SCFGR1_RXNACK_SHIFT (4U)
|
|
/*! RXNACK - Receive NACK
|
|
* 0b0..ACK or NACK always determined by STAR[TXNACK]
|
|
* 0b1..NACK always generated on address overrun or receive data overrun, otherwise ACK or NACK is determined by STAR[TXNACK]
|
|
*/
|
|
#define LPI2C_SCFGR1_RXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXNACK_SHIFT)) & LPI2C_SCFGR1_RXNACK_MASK)
|
|
|
|
#define LPI2C_SCFGR1_GCEN_MASK (0x100U)
|
|
#define LPI2C_SCFGR1_GCEN_SHIFT (8U)
|
|
/*! GCEN - General Call Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)
|
|
|
|
#define LPI2C_SCFGR1_SAEN_MASK (0x200U)
|
|
#define LPI2C_SCFGR1_SAEN_SHIFT (9U)
|
|
/*! SAEN - SMBus Alert Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)
|
|
|
|
#define LPI2C_SCFGR1_TXCFG_MASK (0x400U)
|
|
#define LPI2C_SCFGR1_TXCFG_SHIFT (10U)
|
|
/*! TXCFG - Transmit Flag Configuration
|
|
* 0b0..MSR[TDF] is set only during a target-transmit transfer when STDR is empty
|
|
* 0b1..MSR[TDF] is set whenever STDR is empty
|
|
*/
|
|
#define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)
|
|
|
|
#define LPI2C_SCFGR1_RXCFG_MASK (0x800U)
|
|
#define LPI2C_SCFGR1_RXCFG_SHIFT (11U)
|
|
/*! RXCFG - Receive Data Configuration
|
|
* 0b0..Return received data, clear MSR[RDF]
|
|
* 0b1..Return SASR and clear SSR[AVF] when SSR[AVF] is set, return received data and clear MSR[RDF] when SSR[AFV] is not set
|
|
*/
|
|
#define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)
|
|
|
|
#define LPI2C_SCFGR1_IGNACK_MASK (0x1000U)
|
|
#define LPI2C_SCFGR1_IGNACK_SHIFT (12U)
|
|
/*! IGNACK - Ignore NACK
|
|
* 0b0..End transfer on NACK
|
|
* 0b1..Do not end transfer on NACK
|
|
*/
|
|
#define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)
|
|
|
|
#define LPI2C_SCFGR1_HSMEN_MASK (0x2000U)
|
|
#define LPI2C_SCFGR1_HSMEN_SHIFT (13U)
|
|
/*! HSMEN - HS Mode Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)
|
|
|
|
#define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U)
|
|
#define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U)
|
|
/*! ADDRCFG - Address Configuration
|
|
* 0b000..Address match 0 (7-bit)
|
|
* 0b001..Address match 0 (10-bit)
|
|
* 0b010..Address match 0 (7-bit) or address match 1 (7-bit)
|
|
* 0b011..Address match 0 (10-bit) or address match 1 (10-bit)
|
|
* 0b100..Address match 0 (7-bit) or address match 1 (10-bit)
|
|
* 0b101..Address match 0 (10-bit) or address match 1 (7-bit)
|
|
* 0b110..From address match 0 (7-bit) to address match 1 (7-bit)
|
|
* 0b111..From address match 0 (10-bit) to address match 1 (10-bit)
|
|
*/
|
|
#define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)
|
|
|
|
#define LPI2C_SCFGR1_RXALL_MASK (0x1000000U)
|
|
#define LPI2C_SCFGR1_RXALL_SHIFT (24U)
|
|
/*! RXALL - Receive All
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPI2C_SCFGR1_RXALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXALL_SHIFT)) & LPI2C_SCFGR1_RXALL_MASK)
|
|
|
|
#define LPI2C_SCFGR1_RSCFG_MASK (0x2000000U)
|
|
#define LPI2C_SCFGR1_RSCFG_SHIFT (25U)
|
|
/*! RSCFG - Repeated Start Configuration
|
|
* 0b0..Any repeated Start condition following an address match
|
|
* 0b1..Any repeated Start condition
|
|
*/
|
|
#define LPI2C_SCFGR1_RSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RSCFG_SHIFT)) & LPI2C_SCFGR1_RSCFG_MASK)
|
|
|
|
#define LPI2C_SCFGR1_SDCFG_MASK (0x4000000U)
|
|
#define LPI2C_SCFGR1_SDCFG_SHIFT (26U)
|
|
/*! SDCFG - Stop Detect Configuration
|
|
* 0b0..Any Stop condition following an address match
|
|
* 0b1..Any Stop condition
|
|
*/
|
|
#define LPI2C_SCFGR1_SDCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SDCFG_SHIFT)) & LPI2C_SCFGR1_SDCFG_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SCFGR2 - Target Configuration 2 */
|
|
/*! @{ */
|
|
|
|
#define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU)
|
|
#define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U)
|
|
/*! CLKHOLD - Clock Hold Time */
|
|
#define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)
|
|
|
|
#define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U)
|
|
#define LPI2C_SCFGR2_DATAVD_SHIFT (8U)
|
|
/*! DATAVD - Data Valid Delay */
|
|
#define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)
|
|
|
|
#define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U)
|
|
#define LPI2C_SCFGR2_FILTSCL_SHIFT (16U)
|
|
/*! FILTSCL - Glitch Filter SCL */
|
|
#define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)
|
|
|
|
#define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U)
|
|
#define LPI2C_SCFGR2_FILTSDA_SHIFT (24U)
|
|
/*! FILTSDA - Glitch Filter SDA */
|
|
#define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SAMR - Target Address Match */
|
|
/*! @{ */
|
|
|
|
#define LPI2C_SAMR_ADDR0_MASK (0x7FEU)
|
|
#define LPI2C_SAMR_ADDR0_SHIFT (1U)
|
|
/*! ADDR0 - Address 0 Value */
|
|
#define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)
|
|
|
|
#define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U)
|
|
#define LPI2C_SAMR_ADDR1_SHIFT (17U)
|
|
/*! ADDR1 - Address 1 Value */
|
|
#define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SASR - Target Address Status */
|
|
/*! @{ */
|
|
|
|
#define LPI2C_SASR_RADDR_MASK (0x7FFU)
|
|
#define LPI2C_SASR_RADDR_SHIFT (0U)
|
|
/*! RADDR - Received Address */
|
|
#define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)
|
|
|
|
#define LPI2C_SASR_ANV_MASK (0x4000U)
|
|
#define LPI2C_SASR_ANV_SHIFT (14U)
|
|
/*! ANV - Address Not Valid
|
|
* 0b0..Valid
|
|
* 0b1..Not valid
|
|
*/
|
|
#define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name STAR - Target Transmit ACK */
|
|
/*! @{ */
|
|
|
|
#define LPI2C_STAR_TXNACK_MASK (0x1U)
|
|
#define LPI2C_STAR_TXNACK_SHIFT (0U)
|
|
/*! TXNACK - Transmit NACK
|
|
* 0b0..Transmit ACK
|
|
* 0b1..Transmit NACK
|
|
*/
|
|
#define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name STDR - Target Transmit Data */
|
|
/*! @{ */
|
|
|
|
#define LPI2C_STDR_DATA_MASK (0xFFU)
|
|
#define LPI2C_STDR_DATA_SHIFT (0U)
|
|
/*! DATA - Transmit Data */
|
|
#define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SRDR - Target Receive Data */
|
|
/*! @{ */
|
|
|
|
#define LPI2C_SRDR_DATA_MASK (0xFFU)
|
|
#define LPI2C_SRDR_DATA_SHIFT (0U)
|
|
/*! DATA - Received Data */
|
|
#define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)
|
|
|
|
#define LPI2C_SRDR_RADDR_MASK (0x700U)
|
|
#define LPI2C_SRDR_RADDR_SHIFT (8U)
|
|
/*! RADDR - Received Address */
|
|
#define LPI2C_SRDR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RADDR_SHIFT)) & LPI2C_SRDR_RADDR_MASK)
|
|
|
|
#define LPI2C_SRDR_RXEMPTY_MASK (0x4000U)
|
|
#define LPI2C_SRDR_RXEMPTY_SHIFT (14U)
|
|
/*! RXEMPTY - Receive Empty
|
|
* 0b0..Not empty
|
|
* 0b1..Empty
|
|
*/
|
|
#define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)
|
|
|
|
#define LPI2C_SRDR_SOF_MASK (0x8000U)
|
|
#define LPI2C_SRDR_SOF_SHIFT (15U)
|
|
/*! SOF - Start of Frame
|
|
* 0b0..Not first
|
|
* 0b1..First
|
|
*/
|
|
#define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SRDROR - Target Receive Data Read Only */
|
|
/*! @{ */
|
|
|
|
#define LPI2C_SRDROR_DATA_MASK (0xFFU)
|
|
#define LPI2C_SRDROR_DATA_SHIFT (0U)
|
|
/*! DATA - Receive Data */
|
|
#define LPI2C_SRDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_DATA_SHIFT)) & LPI2C_SRDROR_DATA_MASK)
|
|
|
|
#define LPI2C_SRDROR_RADDR_MASK (0x700U)
|
|
#define LPI2C_SRDROR_RADDR_SHIFT (8U)
|
|
/*! RADDR - Received Address */
|
|
#define LPI2C_SRDROR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RADDR_SHIFT)) & LPI2C_SRDROR_RADDR_MASK)
|
|
|
|
#define LPI2C_SRDROR_RXEMPTY_MASK (0x4000U)
|
|
#define LPI2C_SRDROR_RXEMPTY_SHIFT (14U)
|
|
/*! RXEMPTY - Receive Empty
|
|
* 0b0..Not empty
|
|
* 0b1..Empty
|
|
*/
|
|
#define LPI2C_SRDROR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RXEMPTY_SHIFT)) & LPI2C_SRDROR_RXEMPTY_MASK)
|
|
|
|
#define LPI2C_SRDROR_SOF_MASK (0x8000U)
|
|
#define LPI2C_SRDROR_SOF_SHIFT (15U)
|
|
/*! SOF - Start of Frame
|
|
* 0b0..Not the first
|
|
* 0b1..First
|
|
*/
|
|
#define LPI2C_SRDROR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_SOF_SHIFT)) & LPI2C_SRDROR_SOF_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group LPI2C_Register_Masks */
|
|
|
|
|
|
/* LPI2C - Peripheral instance base addresses */
|
|
/** Peripheral LPI2C0 base address */
|
|
#define LPI2C0_BASE (0x4009A000u)
|
|
/** Peripheral LPI2C0 base pointer */
|
|
#define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE)
|
|
/** Array initializer of LPI2C peripheral base addresses */
|
|
#define LPI2C_BASE_ADDRS { LPI2C0_BASE }
|
|
/** Array initializer of LPI2C peripheral base pointers */
|
|
#define LPI2C_BASE_PTRS { LPI2C0 }
|
|
/** Interrupt vectors for the LPI2C peripheral type */
|
|
#define LPI2C_IRQS { LPI2C0_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group LPI2C_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- LPSPI Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** LPSPI - Register Layout Typedef */
|
|
typedef struct {
|
|
__I uint32_t VERID; /**< Version ID, offset: 0x0 */
|
|
__I uint32_t PARAM; /**< Parameter, offset: 0x4 */
|
|
uint8_t RESERVED_0[8];
|
|
__IO uint32_t CR; /**< Control, offset: 0x10 */
|
|
__IO uint32_t SR; /**< Status, offset: 0x14 */
|
|
__IO uint32_t IER; /**< Interrupt Enable, offset: 0x18 */
|
|
__IO uint32_t DER; /**< DMA Enable, offset: 0x1C */
|
|
__IO uint32_t CFGR0; /**< Configuration 0, offset: 0x20 */
|
|
__IO uint32_t CFGR1; /**< Configuration 1, offset: 0x24 */
|
|
uint8_t RESERVED_1[8];
|
|
__IO uint32_t DMR0; /**< Data Match 0, offset: 0x30 */
|
|
__IO uint32_t DMR1; /**< Data Match 1, offset: 0x34 */
|
|
uint8_t RESERVED_2[8];
|
|
__IO uint32_t CCR; /**< Clock Configuration, offset: 0x40 */
|
|
__IO uint32_t CCR1; /**< Clock Configuration 1, offset: 0x44 */
|
|
uint8_t RESERVED_3[16];
|
|
__IO uint32_t FCR; /**< FIFO Control, offset: 0x58 */
|
|
__I uint32_t FSR; /**< FIFO Status, offset: 0x5C */
|
|
__IO uint32_t TCR; /**< Transmit Command, offset: 0x60 */
|
|
__O uint32_t TDR; /**< Transmit Data, offset: 0x64 */
|
|
uint8_t RESERVED_4[8];
|
|
__I uint32_t RSR; /**< Receive Status, offset: 0x70 */
|
|
__I uint32_t RDR; /**< Receive Data, offset: 0x74 */
|
|
__I uint32_t RDROR; /**< Receive Data Read Only, offset: 0x78 */
|
|
uint8_t RESERVED_5[896];
|
|
__O uint32_t TCBR; /**< Transmit Command Burst, offset: 0x3FC */
|
|
__O uint32_t TDBR[128]; /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */
|
|
__I uint32_t RDBR[128]; /**< Receive Data Burst, array offset: 0x600, array step: 0x4 */
|
|
} LPSPI_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- LPSPI Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup LPSPI_Register_Masks LPSPI Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name VERID - Version ID */
|
|
/*! @{ */
|
|
|
|
#define LPSPI_VERID_FEATURE_MASK (0xFFFFU)
|
|
#define LPSPI_VERID_FEATURE_SHIFT (0U)
|
|
/*! FEATURE - Module Identification Number
|
|
* 0b0000000000000100..Standard feature set supporting a 32-bit shift register.
|
|
* *..
|
|
*/
|
|
#define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)
|
|
|
|
#define LPSPI_VERID_MINOR_MASK (0xFF0000U)
|
|
#define LPSPI_VERID_MINOR_SHIFT (16U)
|
|
/*! MINOR - Minor Version Number */
|
|
#define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)
|
|
|
|
#define LPSPI_VERID_MAJOR_MASK (0xFF000000U)
|
|
#define LPSPI_VERID_MAJOR_SHIFT (24U)
|
|
/*! MAJOR - Major Version Number */
|
|
#define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PARAM - Parameter */
|
|
/*! @{ */
|
|
|
|
#define LPSPI_PARAM_TXFIFO_MASK (0xFFU)
|
|
#define LPSPI_PARAM_TXFIFO_SHIFT (0U)
|
|
/*! TXFIFO - Transmit FIFO Size */
|
|
#define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)
|
|
|
|
#define LPSPI_PARAM_RXFIFO_MASK (0xFF00U)
|
|
#define LPSPI_PARAM_RXFIFO_SHIFT (8U)
|
|
/*! RXFIFO - Receive FIFO Size */
|
|
#define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)
|
|
|
|
#define LPSPI_PARAM_PCSNUM_MASK (0xFF0000U)
|
|
#define LPSPI_PARAM_PCSNUM_SHIFT (16U)
|
|
/*! PCSNUM - PCS Number */
|
|
#define LPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CR - Control */
|
|
/*! @{ */
|
|
|
|
#define LPSPI_CR_MEN_MASK (0x1U)
|
|
#define LPSPI_CR_MEN_SHIFT (0U)
|
|
/*! MEN - Module Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)
|
|
|
|
#define LPSPI_CR_RST_MASK (0x2U)
|
|
#define LPSPI_CR_RST_SHIFT (1U)
|
|
/*! RST - Software Reset
|
|
* 0b0..Not reset
|
|
* 0b1..Reset
|
|
*/
|
|
#define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)
|
|
|
|
#define LPSPI_CR_DBGEN_MASK (0x8U)
|
|
#define LPSPI_CR_DBGEN_SHIFT (3U)
|
|
/*! DBGEN - Debug Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)
|
|
|
|
#define LPSPI_CR_RTF_MASK (0x100U)
|
|
#define LPSPI_CR_RTF_SHIFT (8U)
|
|
/*! RTF - Reset Transmit FIFO
|
|
* 0b0..No effect
|
|
* 0b1..Reset
|
|
*/
|
|
#define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)
|
|
|
|
#define LPSPI_CR_RRF_MASK (0x200U)
|
|
#define LPSPI_CR_RRF_SHIFT (9U)
|
|
/*! RRF - Reset Receive FIFO
|
|
* 0b0..No effect
|
|
* 0b1..Reset
|
|
*/
|
|
#define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SR - Status */
|
|
/*! @{ */
|
|
|
|
#define LPSPI_SR_TDF_MASK (0x1U)
|
|
#define LPSPI_SR_TDF_SHIFT (0U)
|
|
/*! TDF - Transmit Data Flag
|
|
* 0b0..Transmit data not requested
|
|
* 0b1..Transmit data requested
|
|
*/
|
|
#define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK)
|
|
|
|
#define LPSPI_SR_RDF_MASK (0x2U)
|
|
#define LPSPI_SR_RDF_SHIFT (1U)
|
|
/*! RDF - Receive Data Flag
|
|
* 0b0..Receive data not ready
|
|
* 0b1..Receive data ready
|
|
*/
|
|
#define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK)
|
|
|
|
#define LPSPI_SR_WCF_MASK (0x100U)
|
|
#define LPSPI_SR_WCF_SHIFT (8U)
|
|
/*! WCF - Word Complete Flag
|
|
* 0b0..Not complete
|
|
* 0b1..Complete
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK)
|
|
|
|
#define LPSPI_SR_FCF_MASK (0x200U)
|
|
#define LPSPI_SR_FCF_SHIFT (9U)
|
|
/*! FCF - Frame Complete Flag
|
|
* 0b0..Not complete
|
|
* 0b1..Complete
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK)
|
|
|
|
#define LPSPI_SR_TCF_MASK (0x400U)
|
|
#define LPSPI_SR_TCF_SHIFT (10U)
|
|
/*! TCF - Transfer Complete Flag
|
|
* 0b0..Not complete
|
|
* 0b1..Complete
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK)
|
|
|
|
#define LPSPI_SR_TEF_MASK (0x800U)
|
|
#define LPSPI_SR_TEF_SHIFT (11U)
|
|
/*! TEF - Transmit Error Flag
|
|
* 0b0..No underrun
|
|
* 0b1..Underrun
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK)
|
|
|
|
#define LPSPI_SR_REF_MASK (0x1000U)
|
|
#define LPSPI_SR_REF_SHIFT (12U)
|
|
/*! REF - Receive Error Flag
|
|
* 0b0..No overflow
|
|
* 0b1..Overflow
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK)
|
|
|
|
#define LPSPI_SR_DMF_MASK (0x2000U)
|
|
#define LPSPI_SR_DMF_SHIFT (13U)
|
|
/*! DMF - Data Match Flag
|
|
* 0b0..No match
|
|
* 0b1..Match
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK)
|
|
|
|
#define LPSPI_SR_MBF_MASK (0x1000000U)
|
|
#define LPSPI_SR_MBF_SHIFT (24U)
|
|
/*! MBF - Module Busy Flag
|
|
* 0b0..LPSPI is idle
|
|
* 0b1..LPSPI is busy
|
|
*/
|
|
#define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name IER - Interrupt Enable */
|
|
/*! @{ */
|
|
|
|
#define LPSPI_IER_TDIE_MASK (0x1U)
|
|
#define LPSPI_IER_TDIE_SHIFT (0U)
|
|
/*! TDIE - Transmit Data Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK)
|
|
|
|
#define LPSPI_IER_RDIE_MASK (0x2U)
|
|
#define LPSPI_IER_RDIE_SHIFT (1U)
|
|
/*! RDIE - Receive Data Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK)
|
|
|
|
#define LPSPI_IER_WCIE_MASK (0x100U)
|
|
#define LPSPI_IER_WCIE_SHIFT (8U)
|
|
/*! WCIE - Word Complete Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK)
|
|
|
|
#define LPSPI_IER_FCIE_MASK (0x200U)
|
|
#define LPSPI_IER_FCIE_SHIFT (9U)
|
|
/*! FCIE - Frame Complete Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK)
|
|
|
|
#define LPSPI_IER_TCIE_MASK (0x400U)
|
|
#define LPSPI_IER_TCIE_SHIFT (10U)
|
|
/*! TCIE - Transfer Complete Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK)
|
|
|
|
#define LPSPI_IER_TEIE_MASK (0x800U)
|
|
#define LPSPI_IER_TEIE_SHIFT (11U)
|
|
/*! TEIE - Transmit Error Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK)
|
|
|
|
#define LPSPI_IER_REIE_MASK (0x1000U)
|
|
#define LPSPI_IER_REIE_SHIFT (12U)
|
|
/*! REIE - Receive Error Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK)
|
|
|
|
#define LPSPI_IER_DMIE_MASK (0x2000U)
|
|
#define LPSPI_IER_DMIE_SHIFT (13U)
|
|
/*! DMIE - Data Match Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DER - DMA Enable */
|
|
/*! @{ */
|
|
|
|
#define LPSPI_DER_TDDE_MASK (0x1U)
|
|
#define LPSPI_DER_TDDE_SHIFT (0U)
|
|
/*! TDDE - Transmit Data DMA Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK)
|
|
|
|
#define LPSPI_DER_RDDE_MASK (0x2U)
|
|
#define LPSPI_DER_RDDE_SHIFT (1U)
|
|
/*! RDDE - Receive Data DMA Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK)
|
|
|
|
#define LPSPI_DER_FCDE_MASK (0x200U)
|
|
#define LPSPI_DER_FCDE_SHIFT (9U)
|
|
/*! FCDE - Frame Complete DMA Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPSPI_DER_FCDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_FCDE_SHIFT)) & LPSPI_DER_FCDE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CFGR0 - Configuration 0 */
|
|
/*! @{ */
|
|
|
|
#define LPSPI_CFGR0_HREN_MASK (0x1U)
|
|
#define LPSPI_CFGR0_HREN_SHIFT (0U)
|
|
/*! HREN - Host Request Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK)
|
|
|
|
#define LPSPI_CFGR0_HRPOL_MASK (0x2U)
|
|
#define LPSPI_CFGR0_HRPOL_SHIFT (1U)
|
|
/*! HRPOL - Host Request Polarity
|
|
* 0b0..Active high
|
|
* 0b1..Active low
|
|
*/
|
|
#define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
|
|
|
|
#define LPSPI_CFGR0_HRSEL_MASK (0x4U)
|
|
#define LPSPI_CFGR0_HRSEL_SHIFT (2U)
|
|
/*! HRSEL - Host Request Select
|
|
* 0b0..HREQ pin
|
|
* 0b1..Input trigger
|
|
*/
|
|
#define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK)
|
|
|
|
#define LPSPI_CFGR0_HRDIR_MASK (0x8U)
|
|
#define LPSPI_CFGR0_HRDIR_SHIFT (3U)
|
|
/*! HRDIR - Host Request Direction
|
|
* 0b0..Input
|
|
* 0b1..Output
|
|
*/
|
|
#define LPSPI_CFGR0_HRDIR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRDIR_SHIFT)) & LPSPI_CFGR0_HRDIR_MASK)
|
|
|
|
#define LPSPI_CFGR0_CIRFIFO_MASK (0x100U)
|
|
#define LPSPI_CFGR0_CIRFIFO_SHIFT (8U)
|
|
/*! CIRFIFO - Circular FIFO Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK)
|
|
|
|
#define LPSPI_CFGR0_RDMO_MASK (0x200U)
|
|
#define LPSPI_CFGR0_RDMO_SHIFT (9U)
|
|
/*! RDMO - Receive Data Match Only
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CFGR1 - Configuration 1 */
|
|
/*! @{ */
|
|
|
|
#define LPSPI_CFGR1_MASTER_MASK (0x1U)
|
|
#define LPSPI_CFGR1_MASTER_SHIFT (0U)
|
|
/*! MASTER - Master Mode
|
|
* 0b0..Slave mode
|
|
* 0b1..Master mode
|
|
*/
|
|
#define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
|
|
|
|
#define LPSPI_CFGR1_SAMPLE_MASK (0x2U)
|
|
#define LPSPI_CFGR1_SAMPLE_SHIFT (1U)
|
|
/*! SAMPLE - Sample Point
|
|
* 0b0..SCK edge
|
|
* 0b1..Delayed SCK edge
|
|
*/
|
|
#define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK)
|
|
|
|
#define LPSPI_CFGR1_AUTOPCS_MASK (0x4U)
|
|
#define LPSPI_CFGR1_AUTOPCS_SHIFT (2U)
|
|
/*! AUTOPCS - Automatic PCS
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK)
|
|
|
|
#define LPSPI_CFGR1_NOSTALL_MASK (0x8U)
|
|
#define LPSPI_CFGR1_NOSTALL_SHIFT (3U)
|
|
/*! NOSTALL - No Stall
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK)
|
|
|
|
#define LPSPI_CFGR1_PARTIAL_MASK (0x10U)
|
|
#define LPSPI_CFGR1_PARTIAL_SHIFT (4U)
|
|
/*! PARTIAL - Partial Enable
|
|
* 0b0..Discard
|
|
* 0b1..Store
|
|
*/
|
|
#define LPSPI_CFGR1_PARTIAL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PARTIAL_SHIFT)) & LPSPI_CFGR1_PARTIAL_MASK)
|
|
|
|
#define LPSPI_CFGR1_PCSPOL_MASK (0xF00U)
|
|
#define LPSPI_CFGR1_PCSPOL_SHIFT (8U)
|
|
/*! PCSPOL - Peripheral Chip Select Polarity
|
|
* 0b0000..Active low
|
|
* 0b0001..Active high
|
|
*/
|
|
#define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
|
|
|
|
#define LPSPI_CFGR1_MATCFG_MASK (0x70000U)
|
|
#define LPSPI_CFGR1_MATCFG_SHIFT (16U)
|
|
/*! MATCFG - Match Configuration
|
|
* 0b000..Match is disabled
|
|
* 0b001..
|
|
* 0b010..Match first data word with compare word
|
|
* 0b011..Match any data word with compare word
|
|
* 0b100..Sequential match, first data word
|
|
* 0b101..Sequential match, any data word
|
|
* 0b110..Match first data word (masked) with compare word (masked)
|
|
* 0b111..Match any data word (masked) with compare word (masked)
|
|
*/
|
|
#define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
|
|
|
|
#define LPSPI_CFGR1_PINCFG_MASK (0x3000000U)
|
|
#define LPSPI_CFGR1_PINCFG_SHIFT (24U)
|
|
/*! PINCFG - Pin Configuration
|
|
* 0b00..SIN is used for input data; SOUT is used for output data
|
|
* 0b01..SIN is used for both input and output data; only half-duplex serial transfers are supported
|
|
* 0b10..SOUT is used for both input and output data; only half-duplex serial transfers are supported
|
|
* 0b11..SOUT is used for input data; SIN is used for output data
|
|
*/
|
|
#define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK)
|
|
|
|
#define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U)
|
|
#define LPSPI_CFGR1_OUTCFG_SHIFT (26U)
|
|
/*! OUTCFG - Output Configuration
|
|
* 0b0..Retain last value
|
|
* 0b1..3-stated
|
|
*/
|
|
#define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK)
|
|
|
|
#define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U)
|
|
#define LPSPI_CFGR1_PCSCFG_SHIFT (27U)
|
|
/*! PCSCFG - Peripheral Chip Select Configuration
|
|
* 0b0..PCS[3:2] configured for chip select function
|
|
* 0b1..PCS[3:2] configured for half-duplex 4-bit transfers (PCS[3:2] = DATA[3:2])
|
|
*/
|
|
#define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DMR0 - Data Match 0 */
|
|
/*! @{ */
|
|
|
|
#define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU)
|
|
#define LPSPI_DMR0_MATCH0_SHIFT (0U)
|
|
/*! MATCH0 - Match 0 Value */
|
|
#define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DMR1 - Data Match 1 */
|
|
/*! @{ */
|
|
|
|
#define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU)
|
|
#define LPSPI_DMR1_MATCH1_SHIFT (0U)
|
|
/*! MATCH1 - Match 1 Value */
|
|
#define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CCR - Clock Configuration */
|
|
/*! @{ */
|
|
|
|
#define LPSPI_CCR_SCKDIV_MASK (0xFFU)
|
|
#define LPSPI_CCR_SCKDIV_SHIFT (0U)
|
|
/*! SCKDIV - SCK Divider */
|
|
#define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK)
|
|
|
|
#define LPSPI_CCR_DBT_MASK (0xFF00U)
|
|
#define LPSPI_CCR_DBT_SHIFT (8U)
|
|
/*! DBT - Delay Between Transfers */
|
|
#define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK)
|
|
|
|
#define LPSPI_CCR_PCSSCK_MASK (0xFF0000U)
|
|
#define LPSPI_CCR_PCSSCK_SHIFT (16U)
|
|
/*! PCSSCK - PCS-to-SCK Delay */
|
|
#define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK)
|
|
|
|
#define LPSPI_CCR_SCKPCS_MASK (0xFF000000U)
|
|
#define LPSPI_CCR_SCKPCS_SHIFT (24U)
|
|
/*! SCKPCS - SCK-to-PCS Delay */
|
|
#define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CCR1 - Clock Configuration 1 */
|
|
/*! @{ */
|
|
|
|
#define LPSPI_CCR1_SCKSET_MASK (0xFFU)
|
|
#define LPSPI_CCR1_SCKSET_SHIFT (0U)
|
|
/*! SCKSET - SCK Setup */
|
|
#define LPSPI_CCR1_SCKSET(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKSET_SHIFT)) & LPSPI_CCR1_SCKSET_MASK)
|
|
|
|
#define LPSPI_CCR1_SCKHLD_MASK (0xFF00U)
|
|
#define LPSPI_CCR1_SCKHLD_SHIFT (8U)
|
|
/*! SCKHLD - SCK Hold */
|
|
#define LPSPI_CCR1_SCKHLD(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKHLD_SHIFT)) & LPSPI_CCR1_SCKHLD_MASK)
|
|
|
|
#define LPSPI_CCR1_PCSPCS_MASK (0xFF0000U)
|
|
#define LPSPI_CCR1_PCSPCS_SHIFT (16U)
|
|
/*! PCSPCS - PCS to PCS Delay */
|
|
#define LPSPI_CCR1_PCSPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_PCSPCS_SHIFT)) & LPSPI_CCR1_PCSPCS_MASK)
|
|
|
|
#define LPSPI_CCR1_SCKSCK_MASK (0xFF000000U)
|
|
#define LPSPI_CCR1_SCKSCK_SHIFT (24U)
|
|
/*! SCKSCK - SCK Inter-Frame Delay */
|
|
#define LPSPI_CCR1_SCKSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKSCK_SHIFT)) & LPSPI_CCR1_SCKSCK_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FCR - FIFO Control */
|
|
/*! @{ */
|
|
|
|
#define LPSPI_FCR_TXWATER_MASK (0x3U)
|
|
#define LPSPI_FCR_TXWATER_SHIFT (0U)
|
|
/*! TXWATER - Transmit FIFO Watermark */
|
|
#define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK)
|
|
|
|
#define LPSPI_FCR_RXWATER_MASK (0x30000U)
|
|
#define LPSPI_FCR_RXWATER_SHIFT (16U)
|
|
/*! RXWATER - Receive FIFO Watermark */
|
|
#define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FSR - FIFO Status */
|
|
/*! @{ */
|
|
|
|
#define LPSPI_FSR_TXCOUNT_MASK (0x7U)
|
|
#define LPSPI_FSR_TXCOUNT_SHIFT (0U)
|
|
/*! TXCOUNT - Transmit FIFO Count */
|
|
#define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK)
|
|
|
|
#define LPSPI_FSR_RXCOUNT_MASK (0x70000U)
|
|
#define LPSPI_FSR_RXCOUNT_SHIFT (16U)
|
|
/*! RXCOUNT - Receive FIFO Count */
|
|
#define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TCR - Transmit Command */
|
|
/*! @{ */
|
|
|
|
#define LPSPI_TCR_FRAMESZ_MASK (0xFFFU)
|
|
#define LPSPI_TCR_FRAMESZ_SHIFT (0U)
|
|
/*! FRAMESZ - Frame Size */
|
|
#define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK)
|
|
|
|
#define LPSPI_TCR_WIDTH_MASK (0x30000U)
|
|
#define LPSPI_TCR_WIDTH_SHIFT (16U)
|
|
/*! WIDTH - Transfer Width
|
|
* 0b00..1-bit transfer
|
|
* 0b01..2-bit transfer
|
|
* 0b10..4-bit transfer
|
|
* 0b11..Reserved
|
|
*/
|
|
#define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK)
|
|
|
|
#define LPSPI_TCR_TXMSK_MASK (0x40000U)
|
|
#define LPSPI_TCR_TXMSK_SHIFT (18U)
|
|
/*! TXMSK - Transmit Data Mask
|
|
* 0b0..Normal transfer
|
|
* 0b1..Mask transmit data
|
|
*/
|
|
#define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK)
|
|
|
|
#define LPSPI_TCR_RXMSK_MASK (0x80000U)
|
|
#define LPSPI_TCR_RXMSK_SHIFT (19U)
|
|
/*! RXMSK - Receive Data Mask
|
|
* 0b0..Normal transfer
|
|
* 0b1..Mask receive data
|
|
*/
|
|
#define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK)
|
|
|
|
#define LPSPI_TCR_CONTC_MASK (0x100000U)
|
|
#define LPSPI_TCR_CONTC_SHIFT (20U)
|
|
/*! CONTC - Continuing Command
|
|
* 0b0..Command word for start of new transfer
|
|
* 0b1..Command word for continuing transfer
|
|
*/
|
|
#define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK)
|
|
|
|
#define LPSPI_TCR_CONT_MASK (0x200000U)
|
|
#define LPSPI_TCR_CONT_SHIFT (21U)
|
|
/*! CONT - Continuous Transfer
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK)
|
|
|
|
#define LPSPI_TCR_BYSW_MASK (0x400000U)
|
|
#define LPSPI_TCR_BYSW_SHIFT (22U)
|
|
/*! BYSW - Byte Swap
|
|
* 0b0..Disable byte swap
|
|
* 0b1..Enable byte swap
|
|
*/
|
|
#define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK)
|
|
|
|
#define LPSPI_TCR_LSBF_MASK (0x800000U)
|
|
#define LPSPI_TCR_LSBF_SHIFT (23U)
|
|
/*! LSBF - LSB First
|
|
* 0b0..MSB first
|
|
* 0b1..LSB first
|
|
*/
|
|
#define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK)
|
|
|
|
#define LPSPI_TCR_PCS_MASK (0x3000000U)
|
|
#define LPSPI_TCR_PCS_SHIFT (24U)
|
|
/*! PCS - Peripheral Chip Select
|
|
* 0b00..Transfer using PCS[0]
|
|
* 0b01..Transfer using PCS[1]
|
|
* 0b10..Transfer using PCS[2]
|
|
* 0b11..Transfer using PCS[3]
|
|
*/
|
|
#define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK)
|
|
|
|
#define LPSPI_TCR_PRESCALE_MASK (0x38000000U)
|
|
#define LPSPI_TCR_PRESCALE_SHIFT (27U)
|
|
/*! PRESCALE - Prescaler Value
|
|
* 0b000..Divide by 1
|
|
* 0b001..Divide by 2
|
|
* 0b010..Divide by 4
|
|
* 0b011..Divide by 8
|
|
* 0b100..Divide by 16
|
|
* 0b101..Divide by 32
|
|
* 0b110..Divide by 64
|
|
* 0b111..Divide by 128
|
|
*/
|
|
#define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK)
|
|
|
|
#define LPSPI_TCR_CPHA_MASK (0x40000000U)
|
|
#define LPSPI_TCR_CPHA_SHIFT (30U)
|
|
/*! CPHA - Clock Phase
|
|
* 0b0..Captured
|
|
* 0b1..Changed
|
|
*/
|
|
#define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK)
|
|
|
|
#define LPSPI_TCR_CPOL_MASK (0x80000000U)
|
|
#define LPSPI_TCR_CPOL_SHIFT (31U)
|
|
/*! CPOL - Clock Polarity
|
|
* 0b0..Inactive low
|
|
* 0b1..Inactive high
|
|
*/
|
|
#define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TDR - Transmit Data */
|
|
/*! @{ */
|
|
|
|
#define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU)
|
|
#define LPSPI_TDR_DATA_SHIFT (0U)
|
|
/*! DATA - Transmit Data */
|
|
#define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RSR - Receive Status */
|
|
/*! @{ */
|
|
|
|
#define LPSPI_RSR_SOF_MASK (0x1U)
|
|
#define LPSPI_RSR_SOF_SHIFT (0U)
|
|
/*! SOF - Start of Frame
|
|
* 0b0..Subsequent data word
|
|
* 0b1..First data word
|
|
*/
|
|
#define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK)
|
|
|
|
#define LPSPI_RSR_RXEMPTY_MASK (0x2U)
|
|
#define LPSPI_RSR_RXEMPTY_SHIFT (1U)
|
|
/*! RXEMPTY - RX FIFO Empty
|
|
* 0b0..Not empty
|
|
* 0b1..Empty
|
|
*/
|
|
#define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RDR - Receive Data */
|
|
/*! @{ */
|
|
|
|
#define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU)
|
|
#define LPSPI_RDR_DATA_SHIFT (0U)
|
|
/*! DATA - Receive Data */
|
|
#define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RDROR - Receive Data Read Only */
|
|
/*! @{ */
|
|
|
|
#define LPSPI_RDROR_DATA_MASK (0xFFFFFFFFU)
|
|
#define LPSPI_RDROR_DATA_SHIFT (0U)
|
|
/*! DATA - Receive Data */
|
|
#define LPSPI_RDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDROR_DATA_SHIFT)) & LPSPI_RDROR_DATA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TCBR - Transmit Command Burst */
|
|
/*! @{ */
|
|
|
|
#define LPSPI_TCBR_DATA_MASK (0xFFFFFFFFU)
|
|
#define LPSPI_TCBR_DATA_SHIFT (0U)
|
|
/*! DATA - Command Data */
|
|
#define LPSPI_TCBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCBR_DATA_SHIFT)) & LPSPI_TCBR_DATA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TDBR - Transmit Data Burst */
|
|
/*! @{ */
|
|
|
|
#define LPSPI_TDBR_DATA_MASK (0xFFFFFFFFU)
|
|
#define LPSPI_TDBR_DATA_SHIFT (0U)
|
|
/*! DATA - Data */
|
|
#define LPSPI_TDBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDBR_DATA_SHIFT)) & LPSPI_TDBR_DATA_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of LPSPI_TDBR */
|
|
#define LPSPI_TDBR_COUNT (128U)
|
|
|
|
/*! @name RDBR - Receive Data Burst */
|
|
/*! @{ */
|
|
|
|
#define LPSPI_RDBR_DATA_MASK (0xFFFFFFFFU)
|
|
#define LPSPI_RDBR_DATA_SHIFT (0U)
|
|
/*! DATA - Data */
|
|
#define LPSPI_RDBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDBR_DATA_SHIFT)) & LPSPI_RDBR_DATA_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of LPSPI_RDBR */
|
|
#define LPSPI_RDBR_COUNT (128U)
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group LPSPI_Register_Masks */
|
|
|
|
|
|
/* LPSPI - Peripheral instance base addresses */
|
|
/** Peripheral LPSPI0 base address */
|
|
#define LPSPI0_BASE (0x4009C000u)
|
|
/** Peripheral LPSPI0 base pointer */
|
|
#define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE)
|
|
/** Peripheral LPSPI1 base address */
|
|
#define LPSPI1_BASE (0x4009D000u)
|
|
/** Peripheral LPSPI1 base pointer */
|
|
#define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE)
|
|
/** Array initializer of LPSPI peripheral base addresses */
|
|
#define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE }
|
|
/** Array initializer of LPSPI peripheral base pointers */
|
|
#define LPSPI_BASE_PTRS { LPSPI0, LPSPI1 }
|
|
/** Interrupt vectors for the LPSPI peripheral type */
|
|
#define LPSPI_IRQS { LPSPI0_IRQn, LPSPI1_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group LPSPI_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- LPTMR Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** LPTMR - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t CSR; /**< Control Status, offset: 0x0 */
|
|
__IO uint32_t PSR; /**< Prescaler and Glitch Filter, offset: 0x4 */
|
|
__IO uint32_t CMR; /**< Compare, offset: 0x8 */
|
|
__IO uint32_t CNR; /**< Counter, offset: 0xC */
|
|
} LPTMR_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- LPTMR Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup LPTMR_Register_Masks LPTMR Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name CSR - Control Status */
|
|
/*! @{ */
|
|
|
|
#define LPTMR_CSR_TEN_MASK (0x1U)
|
|
#define LPTMR_CSR_TEN_SHIFT (0U)
|
|
/*! TEN - Timer Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
|
|
|
|
#define LPTMR_CSR_TMS_MASK (0x2U)
|
|
#define LPTMR_CSR_TMS_SHIFT (1U)
|
|
/*! TMS - Timer Mode Select
|
|
* 0b0..Time Counter
|
|
* 0b1..Pulse Counter
|
|
*/
|
|
#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
|
|
|
|
#define LPTMR_CSR_TFC_MASK (0x4U)
|
|
#define LPTMR_CSR_TFC_SHIFT (2U)
|
|
/*! TFC - Timer Free-Running Counter
|
|
* 0b0..Reset when TCF asserts
|
|
* 0b1..Reset on overflow
|
|
*/
|
|
#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
|
|
|
|
#define LPTMR_CSR_TPP_MASK (0x8U)
|
|
#define LPTMR_CSR_TPP_SHIFT (3U)
|
|
/*! TPP - Timer Pin Polarity
|
|
* 0b0..Active-high
|
|
* 0b1..Active-low
|
|
*/
|
|
#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
|
|
|
|
#define LPTMR_CSR_TPS_MASK (0x30U)
|
|
#define LPTMR_CSR_TPS_SHIFT (4U)
|
|
/*! TPS - Timer Pin Select
|
|
* 0b00..Input 0
|
|
* 0b01..Input 1
|
|
* 0b10..Input 2
|
|
* 0b11..Input 3
|
|
*/
|
|
#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
|
|
|
|
#define LPTMR_CSR_TIE_MASK (0x40U)
|
|
#define LPTMR_CSR_TIE_SHIFT (6U)
|
|
/*! TIE - Timer Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
|
|
|
|
#define LPTMR_CSR_TCF_MASK (0x80U)
|
|
#define LPTMR_CSR_TCF_SHIFT (7U)
|
|
/*! TCF - Timer Compare Flag
|
|
* 0b0..CNR != (CMR + 1)
|
|
* 0b1..CNR = (CMR + 1)
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
|
|
|
|
#define LPTMR_CSR_TDRE_MASK (0x100U)
|
|
#define LPTMR_CSR_TDRE_SHIFT (8U)
|
|
/*! TDRE - Timer DMA Request Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPTMR_CSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TDRE_SHIFT)) & LPTMR_CSR_TDRE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PSR - Prescaler and Glitch Filter */
|
|
/*! @{ */
|
|
|
|
#define LPTMR_PSR_PCS_MASK (0x3U)
|
|
#define LPTMR_PSR_PCS_SHIFT (0U)
|
|
/*! PCS - Prescaler and Glitch Filter Clock Select
|
|
* 0b00..Clock 0
|
|
* 0b01..Clock 1
|
|
* 0b10..Clock 2
|
|
* 0b11..Clock 3
|
|
*/
|
|
#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
|
|
|
|
#define LPTMR_PSR_PBYP_MASK (0x4U)
|
|
#define LPTMR_PSR_PBYP_SHIFT (2U)
|
|
/*! PBYP - Prescaler and Glitch Filter Bypass
|
|
* 0b0..Prescaler and glitch filter enable
|
|
* 0b1..Prescaler and glitch filter bypass
|
|
*/
|
|
#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
|
|
|
|
#define LPTMR_PSR_PRESCALE_MASK (0x78U)
|
|
#define LPTMR_PSR_PRESCALE_SHIFT (3U)
|
|
/*! PRESCALE - Prescaler and Glitch Filter Value
|
|
* 0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration
|
|
* 0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after two rising clock edges
|
|
* 0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after four rising clock edges
|
|
* 0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after eight rising clock edges
|
|
* 0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges
|
|
* 0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges
|
|
* 0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges
|
|
* 0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges
|
|
* 0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges
|
|
* 0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges
|
|
* 0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges
|
|
* 0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges
|
|
* 0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges
|
|
* 0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges
|
|
* 0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges
|
|
* 0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges
|
|
*/
|
|
#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CMR - Compare */
|
|
/*! @{ */
|
|
|
|
#define LPTMR_CMR_COMPARE_MASK (0xFFFFFFFFU)
|
|
#define LPTMR_CMR_COMPARE_SHIFT (0U)
|
|
/*! COMPARE - Compare Value */
|
|
#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CNR - Counter */
|
|
/*! @{ */
|
|
|
|
#define LPTMR_CNR_COUNTER_MASK (0xFFFFFFFFU)
|
|
#define LPTMR_CNR_COUNTER_SHIFT (0U)
|
|
/*! COUNTER - Counter Value */
|
|
#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group LPTMR_Register_Masks */
|
|
|
|
|
|
/* LPTMR - Peripheral instance base addresses */
|
|
/** Peripheral LPTMR0 base address */
|
|
#define LPTMR0_BASE (0x400AB000u)
|
|
/** Peripheral LPTMR0 base pointer */
|
|
#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
|
|
/** Array initializer of LPTMR peripheral base addresses */
|
|
#define LPTMR_BASE_ADDRS { LPTMR0_BASE }
|
|
/** Array initializer of LPTMR peripheral base pointers */
|
|
#define LPTMR_BASE_PTRS { LPTMR0 }
|
|
/** Interrupt vectors for the LPTMR peripheral type */
|
|
#define LPTMR_IRQS { LPTMR0_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group LPTMR_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- LPUART Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** LPUART - Register Layout Typedef */
|
|
typedef struct {
|
|
__I uint32_t VERID; /**< Version ID, offset: 0x0 */
|
|
__I uint32_t PARAM; /**< Parameter, offset: 0x4 */
|
|
__IO uint32_t GLOBAL; /**< Global, offset: 0x8 */
|
|
__IO uint32_t PINCFG; /**< Pin Configuration, offset: 0xC */
|
|
__IO uint32_t BAUD; /**< Baud Rate, offset: 0x10 */
|
|
__IO uint32_t STAT; /**< Status, offset: 0x14 */
|
|
__IO uint32_t CTRL; /**< Control, offset: 0x18 */
|
|
__IO uint32_t DATA; /**< Data, offset: 0x1C */
|
|
__IO uint32_t MATCH; /**< Match Address, offset: 0x20 */
|
|
__IO uint32_t MODIR; /**< MODEM IrDA, offset: 0x24 */
|
|
__IO uint32_t FIFO; /**< FIFO, offset: 0x28 */
|
|
__IO uint32_t WATER; /**< Watermark, offset: 0x2C */
|
|
__I uint32_t DATARO; /**< Data Read-Only, offset: 0x30 */
|
|
} LPUART_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- LPUART Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup LPUART_Register_Masks LPUART Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name VERID - Version ID */
|
|
/*! @{ */
|
|
|
|
#define LPUART_VERID_FEATURE_MASK (0xFFFFU)
|
|
#define LPUART_VERID_FEATURE_SHIFT (0U)
|
|
/*! FEATURE - Feature Identification Number
|
|
* 0b0000000000000001..Standard feature set
|
|
* 0b0000000000000011..Standard feature set with MODEM and IrDA support
|
|
*/
|
|
#define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)
|
|
|
|
#define LPUART_VERID_MINOR_MASK (0xFF0000U)
|
|
#define LPUART_VERID_MINOR_SHIFT (16U)
|
|
/*! MINOR - Minor Version Number */
|
|
#define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)
|
|
|
|
#define LPUART_VERID_MAJOR_MASK (0xFF000000U)
|
|
#define LPUART_VERID_MAJOR_SHIFT (24U)
|
|
/*! MAJOR - Major Version Number */
|
|
#define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PARAM - Parameter */
|
|
/*! @{ */
|
|
|
|
#define LPUART_PARAM_TXFIFO_MASK (0xFFU)
|
|
#define LPUART_PARAM_TXFIFO_SHIFT (0U)
|
|
/*! TXFIFO - Transmit FIFO Size */
|
|
#define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)
|
|
|
|
#define LPUART_PARAM_RXFIFO_MASK (0xFF00U)
|
|
#define LPUART_PARAM_RXFIFO_SHIFT (8U)
|
|
/*! RXFIFO - Receive FIFO Size */
|
|
#define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GLOBAL - Global */
|
|
/*! @{ */
|
|
|
|
#define LPUART_GLOBAL_RST_MASK (0x2U)
|
|
#define LPUART_GLOBAL_RST_SHIFT (1U)
|
|
/*! RST - Software Reset
|
|
* 0b0..Not reset
|
|
* 0b1..Reset
|
|
*/
|
|
#define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PINCFG - Pin Configuration */
|
|
/*! @{ */
|
|
|
|
#define LPUART_PINCFG_TRGSEL_MASK (0x3U)
|
|
#define LPUART_PINCFG_TRGSEL_SHIFT (0U)
|
|
/*! TRGSEL - Trigger Select
|
|
* 0b00..Input trigger disabled
|
|
* 0b01..Input trigger used instead of the RXD pin input
|
|
* 0b10..Input trigger used instead of the CTS_B pin input
|
|
* 0b11..Input trigger used to modulate the TXD pin output, which (after TXINV configuration) is internally ANDed with the input trigger
|
|
*/
|
|
#define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name BAUD - Baud Rate */
|
|
/*! @{ */
|
|
|
|
#define LPUART_BAUD_SBR_MASK (0x1FFFU)
|
|
#define LPUART_BAUD_SBR_SHIFT (0U)
|
|
/*! SBR - Baud Rate Modulo Divisor */
|
|
#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
|
|
|
|
#define LPUART_BAUD_SBNS_MASK (0x2000U)
|
|
#define LPUART_BAUD_SBNS_SHIFT (13U)
|
|
/*! SBNS - Stop Bit Number Select
|
|
* 0b0..One stop bit
|
|
* 0b1..Two stop bits
|
|
*/
|
|
#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
|
|
|
|
#define LPUART_BAUD_RXEDGIE_MASK (0x4000U)
|
|
#define LPUART_BAUD_RXEDGIE_SHIFT (14U)
|
|
/*! RXEDGIE - RX Input Active Edge Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
|
|
|
|
#define LPUART_BAUD_LBKDIE_MASK (0x8000U)
|
|
#define LPUART_BAUD_LBKDIE_SHIFT (15U)
|
|
/*! LBKDIE - LIN Break Detect Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
|
|
|
|
#define LPUART_BAUD_RESYNCDIS_MASK (0x10000U)
|
|
#define LPUART_BAUD_RESYNCDIS_SHIFT (16U)
|
|
/*! RESYNCDIS - Resynchronization Disable
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
|
|
|
|
#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U)
|
|
#define LPUART_BAUD_BOTHEDGE_SHIFT (17U)
|
|
/*! BOTHEDGE - Both Edge Sampling
|
|
* 0b0..Rising edge
|
|
* 0b1..Both rising and falling edges
|
|
*/
|
|
#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
|
|
|
|
#define LPUART_BAUD_MATCFG_MASK (0xC0000U)
|
|
#define LPUART_BAUD_MATCFG_SHIFT (18U)
|
|
/*! MATCFG - Match Configuration
|
|
* 0b00..Address match wake-up
|
|
* 0b01..Idle match wake-up
|
|
* 0b10..Match on and match off
|
|
* 0b11..Enables RWU on data match and match on or off for the transmitter CTS input
|
|
*/
|
|
#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
|
|
|
|
#define LPUART_BAUD_RIDMAE_MASK (0x100000U)
|
|
#define LPUART_BAUD_RIDMAE_SHIFT (20U)
|
|
/*! RIDMAE - Receiver Idle DMA Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK)
|
|
|
|
#define LPUART_BAUD_RDMAE_MASK (0x200000U)
|
|
#define LPUART_BAUD_RDMAE_SHIFT (21U)
|
|
/*! RDMAE - Receiver Full DMA Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
|
|
|
|
#define LPUART_BAUD_TDMAE_MASK (0x800000U)
|
|
#define LPUART_BAUD_TDMAE_SHIFT (23U)
|
|
/*! TDMAE - Transmitter DMA Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
|
|
|
|
#define LPUART_BAUD_OSR_MASK (0x1F000000U)
|
|
#define LPUART_BAUD_OSR_SHIFT (24U)
|
|
/*! OSR - Oversampling Ratio
|
|
* 0b00000..Results in an OSR of 16
|
|
* 0b00001..Reserved
|
|
* 0b00010..Reserved
|
|
* 0b00011..Results in an OSR of 4 (requires BAUD[BOTHEDGE] to be 1)
|
|
* 0b00100..Results in an OSR of 5 (requires BAUD[BOTHEDGE] to be 1)
|
|
* 0b00101..Results in an OSR of 6 (requires BAUD[BOTHEDGE] to be 1)
|
|
* 0b00110..Results in an OSR of 7 (requires BAUD[BOTHEDGE] to be 1)
|
|
* 0b00111..Results in an OSR of 8
|
|
* 0b01000..Results in an OSR of 9
|
|
* 0b01001..Results in an OSR of 10
|
|
* 0b01010..Results in an OSR of 11
|
|
* 0b01011..Results in an OSR of 12
|
|
* 0b01100..Results in an OSR of 13
|
|
* 0b01101..Results in an OSR of 14
|
|
* 0b01110..Results in an OSR of 15
|
|
* 0b01111..Results in an OSR of 16
|
|
* 0b10000..Results in an OSR of 17
|
|
* 0b10001..Results in an OSR of 18
|
|
* 0b10010..Results in an OSR of 19
|
|
* 0b10011..Results in an OSR of 20
|
|
* 0b10100..Results in an OSR of 21
|
|
* 0b10101..Results in an OSR of 22
|
|
* 0b10110..Results in an OSR of 23
|
|
* 0b10111..Results in an OSR of 24
|
|
* 0b11000..Results in an OSR of 25
|
|
* 0b11001..Results in an OSR of 26
|
|
* 0b11010..Results in an OSR of 27
|
|
* 0b11011..Results in an OSR of 28
|
|
* 0b11100..Results in an OSR of 29
|
|
* 0b11101..Results in an OSR of 30
|
|
* 0b11110..Results in an OSR of 31
|
|
* 0b11111..Results in an OSR of 32
|
|
*/
|
|
#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
|
|
|
|
#define LPUART_BAUD_M10_MASK (0x20000000U)
|
|
#define LPUART_BAUD_M10_SHIFT (29U)
|
|
/*! M10 - 10-Bit Mode Select
|
|
* 0b0..Receiver and transmitter use 7-bit to 9-bit data characters
|
|
* 0b1..Receiver and transmitter use 10-bit data characters
|
|
*/
|
|
#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
|
|
|
|
#define LPUART_BAUD_MAEN2_MASK (0x40000000U)
|
|
#define LPUART_BAUD_MAEN2_SHIFT (30U)
|
|
/*! MAEN2 - Match Address Mode Enable 2
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
|
|
|
|
#define LPUART_BAUD_MAEN1_MASK (0x80000000U)
|
|
#define LPUART_BAUD_MAEN1_SHIFT (31U)
|
|
/*! MAEN1 - Match Address Mode Enable 1
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name STAT - Status */
|
|
/*! @{ */
|
|
|
|
#define LPUART_STAT_LBKFE_MASK (0x1U)
|
|
#define LPUART_STAT_LBKFE_SHIFT (0U)
|
|
/*! LBKFE - LIN Break Flag Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPUART_STAT_LBKFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKFE_SHIFT)) & LPUART_STAT_LBKFE_MASK)
|
|
|
|
#define LPUART_STAT_AME_MASK (0x2U)
|
|
#define LPUART_STAT_AME_SHIFT (1U)
|
|
/*! AME - Address Mark Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPUART_STAT_AME(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_AME_SHIFT)) & LPUART_STAT_AME_MASK)
|
|
|
|
#define LPUART_STAT_MA2F_MASK (0x4000U)
|
|
#define LPUART_STAT_MA2F_SHIFT (14U)
|
|
/*! MA2F - Match 2 Flag
|
|
* 0b0..Not equal to MA2
|
|
* 0b1..Equal to MA2
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
|
|
|
|
#define LPUART_STAT_MA1F_MASK (0x8000U)
|
|
#define LPUART_STAT_MA1F_SHIFT (15U)
|
|
/*! MA1F - Match 1 Flag
|
|
* 0b0..Not equal to MA1
|
|
* 0b1..Equal to MA1
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
|
|
|
|
#define LPUART_STAT_PF_MASK (0x10000U)
|
|
#define LPUART_STAT_PF_SHIFT (16U)
|
|
/*! PF - Parity Error Flag
|
|
* 0b0..No parity error detected
|
|
* 0b1..Parity error detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
|
|
|
|
#define LPUART_STAT_FE_MASK (0x20000U)
|
|
#define LPUART_STAT_FE_SHIFT (17U)
|
|
/*! FE - Framing Error Flag
|
|
* 0b0..No framing error detected (this does not guarantee that the framing is correct)
|
|
* 0b1..Framing error detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
|
|
|
|
#define LPUART_STAT_NF_MASK (0x40000U)
|
|
#define LPUART_STAT_NF_SHIFT (18U)
|
|
/*! NF - Noise Flag
|
|
* 0b0..No noise detected
|
|
* 0b1..Noise detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
|
|
|
|
#define LPUART_STAT_OR_MASK (0x80000U)
|
|
#define LPUART_STAT_OR_SHIFT (19U)
|
|
/*! OR - Receiver Overrun Flag
|
|
* 0b0..No overrun
|
|
* 0b1..Receive overrun (new LPUART data is lost)
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
|
|
|
|
#define LPUART_STAT_IDLE_MASK (0x100000U)
|
|
#define LPUART_STAT_IDLE_SHIFT (20U)
|
|
/*! IDLE - Idle Line Flag
|
|
* 0b0..Idle line detected
|
|
* 0b1..Idle line not detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
|
|
|
|
#define LPUART_STAT_RDRF_MASK (0x200000U)
|
|
#define LPUART_STAT_RDRF_SHIFT (21U)
|
|
/*! RDRF - Receive Data Register Full Flag
|
|
* 0b0..Equal to or less than watermark
|
|
* 0b1..Greater than watermark
|
|
*/
|
|
#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
|
|
|
|
#define LPUART_STAT_TC_MASK (0x400000U)
|
|
#define LPUART_STAT_TC_SHIFT (22U)
|
|
/*! TC - Transmission Complete Flag
|
|
* 0b0..Transmitter active
|
|
* 0b1..Transmitter idle
|
|
*/
|
|
#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
|
|
|
|
#define LPUART_STAT_TDRE_MASK (0x800000U)
|
|
#define LPUART_STAT_TDRE_SHIFT (23U)
|
|
/*! TDRE - Transmit Data Register Empty Flag
|
|
* 0b0..Greater than watermark
|
|
* 0b1..Equal to or less than watermark
|
|
*/
|
|
#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
|
|
|
|
#define LPUART_STAT_RAF_MASK (0x1000000U)
|
|
#define LPUART_STAT_RAF_SHIFT (24U)
|
|
/*! RAF - Receiver Active Flag
|
|
* 0b0..Idle, waiting for a start bit
|
|
* 0b1..Receiver active (RXD pin input not idle)
|
|
*/
|
|
#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
|
|
|
|
#define LPUART_STAT_LBKDE_MASK (0x2000000U)
|
|
#define LPUART_STAT_LBKDE_SHIFT (25U)
|
|
/*! LBKDE - LIN Break Detection Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
|
|
|
|
#define LPUART_STAT_BRK13_MASK (0x4000000U)
|
|
#define LPUART_STAT_BRK13_SHIFT (26U)
|
|
/*! BRK13 - Break Character Generation Length
|
|
* 0b0..9 to 13 bit times
|
|
* 0b1..12 to 15 bit times
|
|
*/
|
|
#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
|
|
|
|
#define LPUART_STAT_RWUID_MASK (0x8000000U)
|
|
#define LPUART_STAT_RWUID_SHIFT (27U)
|
|
/*! RWUID - Receive Wake Up Idle Detect
|
|
* 0b0..STAT[IDLE] does not become 1
|
|
* 0b1..STAT[IDLE] becomes 1
|
|
*/
|
|
#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
|
|
|
|
#define LPUART_STAT_RXINV_MASK (0x10000000U)
|
|
#define LPUART_STAT_RXINV_SHIFT (28U)
|
|
/*! RXINV - Receive Data Inversion
|
|
* 0b0..Inverted
|
|
* 0b1..Not inverted
|
|
*/
|
|
#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
|
|
|
|
#define LPUART_STAT_MSBF_MASK (0x20000000U)
|
|
#define LPUART_STAT_MSBF_SHIFT (29U)
|
|
/*! MSBF - MSB First
|
|
* 0b0..LSB
|
|
* 0b1..MSB
|
|
*/
|
|
#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
|
|
|
|
#define LPUART_STAT_RXEDGIF_MASK (0x40000000U)
|
|
#define LPUART_STAT_RXEDGIF_SHIFT (30U)
|
|
/*! RXEDGIF - RXD Pin Active Edge Interrupt Flag
|
|
* 0b0..Not occurred
|
|
* 0b1..Occurred
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
|
|
|
|
#define LPUART_STAT_LBKDIF_MASK (0x80000000U)
|
|
#define LPUART_STAT_LBKDIF_SHIFT (31U)
|
|
/*! LBKDIF - LIN Break Detect Interrupt Flag
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CTRL - Control */
|
|
/*! @{ */
|
|
|
|
#define LPUART_CTRL_PT_MASK (0x1U)
|
|
#define LPUART_CTRL_PT_SHIFT (0U)
|
|
/*! PT - Parity Type
|
|
* 0b0..Even parity
|
|
* 0b1..Odd parity
|
|
*/
|
|
#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
|
|
|
|
#define LPUART_CTRL_PE_MASK (0x2U)
|
|
#define LPUART_CTRL_PE_SHIFT (1U)
|
|
/*! PE - Parity Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
|
|
|
|
#define LPUART_CTRL_ILT_MASK (0x4U)
|
|
#define LPUART_CTRL_ILT_SHIFT (2U)
|
|
/*! ILT - Idle Line Type Select
|
|
* 0b0..After the start bit
|
|
* 0b1..After the stop bit
|
|
*/
|
|
#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
|
|
|
|
#define LPUART_CTRL_WAKE_MASK (0x8U)
|
|
#define LPUART_CTRL_WAKE_SHIFT (3U)
|
|
/*! WAKE - Receiver Wake-Up Method Select
|
|
* 0b0..Idle
|
|
* 0b1..Mark
|
|
*/
|
|
#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
|
|
|
|
#define LPUART_CTRL_M_MASK (0x10U)
|
|
#define LPUART_CTRL_M_SHIFT (4U)
|
|
/*! M - 9-Bit Or 8-Bit Mode Select
|
|
* 0b0..8-bit
|
|
* 0b1..9-bit
|
|
*/
|
|
#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
|
|
|
|
#define LPUART_CTRL_RSRC_MASK (0x20U)
|
|
#define LPUART_CTRL_RSRC_SHIFT (5U)
|
|
/*! RSRC - Receiver Source Select
|
|
* 0b0..Internal Loopback mode
|
|
* 0b1..Single-wire mode
|
|
*/
|
|
#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
|
|
|
|
#define LPUART_CTRL_DOZEEN_MASK (0x40U)
|
|
#define LPUART_CTRL_DOZEEN_SHIFT (6U)
|
|
/*! DOZEEN - Doze Mode
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
|
|
|
|
#define LPUART_CTRL_LOOPS_MASK (0x80U)
|
|
#define LPUART_CTRL_LOOPS_SHIFT (7U)
|
|
/*! LOOPS - Loop Mode Select
|
|
* 0b0..Normal operation: RXD and TXD use separate pins
|
|
* 0b1..Loop mode or Single-Wire mode
|
|
*/
|
|
#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
|
|
|
|
#define LPUART_CTRL_IDLECFG_MASK (0x700U)
|
|
#define LPUART_CTRL_IDLECFG_SHIFT (8U)
|
|
/*! IDLECFG - Idle Configuration
|
|
* 0b000..1
|
|
* 0b001..2
|
|
* 0b010..4
|
|
* 0b011..8
|
|
* 0b100..16
|
|
* 0b101..32
|
|
* 0b110..64
|
|
* 0b111..128
|
|
*/
|
|
#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
|
|
|
|
#define LPUART_CTRL_M7_MASK (0x800U)
|
|
#define LPUART_CTRL_M7_SHIFT (11U)
|
|
/*! M7 - 7-Bit Mode Select
|
|
* 0b0..8-bit to 10-bit
|
|
* 0b1..7-bit
|
|
*/
|
|
#define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK)
|
|
|
|
#define LPUART_CTRL_MA2IE_MASK (0x4000U)
|
|
#define LPUART_CTRL_MA2IE_SHIFT (14U)
|
|
/*! MA2IE - Match 2 (MA2F) Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
|
|
|
|
#define LPUART_CTRL_MA1IE_MASK (0x8000U)
|
|
#define LPUART_CTRL_MA1IE_SHIFT (15U)
|
|
/*! MA1IE - Match 1 (MA1F) Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
|
|
|
|
#define LPUART_CTRL_SBK_MASK (0x10000U)
|
|
#define LPUART_CTRL_SBK_SHIFT (16U)
|
|
/*! SBK - Send Break
|
|
* 0b0..Normal transmitter operation
|
|
* 0b1..Queue break character(s) to be sent
|
|
*/
|
|
#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
|
|
|
|
#define LPUART_CTRL_RWU_MASK (0x20000U)
|
|
#define LPUART_CTRL_RWU_SHIFT (17U)
|
|
/*! RWU - Receiver Wake-Up Control
|
|
* 0b0..Normal receiver operation
|
|
* 0b1..LPUART receiver in standby, waiting for a wake-up condition
|
|
*/
|
|
#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
|
|
|
|
#define LPUART_CTRL_RE_MASK (0x40000U)
|
|
#define LPUART_CTRL_RE_SHIFT (18U)
|
|
/*! RE - Receiver Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
|
|
|
|
#define LPUART_CTRL_TE_MASK (0x80000U)
|
|
#define LPUART_CTRL_TE_SHIFT (19U)
|
|
/*! TE - Transmitter Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
|
|
|
|
#define LPUART_CTRL_ILIE_MASK (0x100000U)
|
|
#define LPUART_CTRL_ILIE_SHIFT (20U)
|
|
/*! ILIE - Idle Line Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
|
|
|
|
#define LPUART_CTRL_RIE_MASK (0x200000U)
|
|
#define LPUART_CTRL_RIE_SHIFT (21U)
|
|
/*! RIE - Receiver Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
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|
|
|
#define LPUART_CTRL_TCIE_MASK (0x400000U)
|
|
#define LPUART_CTRL_TCIE_SHIFT (22U)
|
|
/*! TCIE - Transmission Complete Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
|
|
|
|
#define LPUART_CTRL_TIE_MASK (0x800000U)
|
|
#define LPUART_CTRL_TIE_SHIFT (23U)
|
|
/*! TIE - Transmit Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
|
|
|
|
#define LPUART_CTRL_PEIE_MASK (0x1000000U)
|
|
#define LPUART_CTRL_PEIE_SHIFT (24U)
|
|
/*! PEIE - Parity Error Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
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|
|
|
#define LPUART_CTRL_FEIE_MASK (0x2000000U)
|
|
#define LPUART_CTRL_FEIE_SHIFT (25U)
|
|
/*! FEIE - Framing Error Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
|
|
|
|
#define LPUART_CTRL_NEIE_MASK (0x4000000U)
|
|
#define LPUART_CTRL_NEIE_SHIFT (26U)
|
|
/*! NEIE - Noise Error Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
|
|
|
|
#define LPUART_CTRL_ORIE_MASK (0x8000000U)
|
|
#define LPUART_CTRL_ORIE_SHIFT (27U)
|
|
/*! ORIE - Overrun Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
|
|
|
|
#define LPUART_CTRL_TXINV_MASK (0x10000000U)
|
|
#define LPUART_CTRL_TXINV_SHIFT (28U)
|
|
/*! TXINV - Transmit Data Inversion
|
|
* 0b0..Not inverted
|
|
* 0b1..Inverted
|
|
*/
|
|
#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
|
|
|
|
#define LPUART_CTRL_TXDIR_MASK (0x20000000U)
|
|
#define LPUART_CTRL_TXDIR_SHIFT (29U)
|
|
/*! TXDIR - TXD Pin Direction in Single-Wire Mode
|
|
* 0b0..Input
|
|
* 0b1..Output
|
|
*/
|
|
#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
|
|
|
|
#define LPUART_CTRL_R9T8_MASK (0x40000000U)
|
|
#define LPUART_CTRL_R9T8_SHIFT (30U)
|
|
/*! R9T8 - Receive Bit 9 Transmit Bit 8 */
|
|
#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
|
|
|
|
#define LPUART_CTRL_R8T9_MASK (0x80000000U)
|
|
#define LPUART_CTRL_R8T9_SHIFT (31U)
|
|
/*! R8T9 - Receive Bit 8 Transmit Bit 9 */
|
|
#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DATA - Data */
|
|
/*! @{ */
|
|
|
|
#define LPUART_DATA_R0T0_MASK (0x1U)
|
|
#define LPUART_DATA_R0T0_SHIFT (0U)
|
|
/*! R0T0 - Read receive FIFO bit 0 or write transmit FIFO bit 0 */
|
|
#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
|
|
|
|
#define LPUART_DATA_R1T1_MASK (0x2U)
|
|
#define LPUART_DATA_R1T1_SHIFT (1U)
|
|
/*! R1T1 - Read receive FIFO bit 1 or write transmit FIFO bit 1 */
|
|
#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
|
|
|
|
#define LPUART_DATA_R2T2_MASK (0x4U)
|
|
#define LPUART_DATA_R2T2_SHIFT (2U)
|
|
/*! R2T2 - Read receive FIFO bit 2 or write transmit FIFO bit 2 */
|
|
#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
|
|
|
|
#define LPUART_DATA_R3T3_MASK (0x8U)
|
|
#define LPUART_DATA_R3T3_SHIFT (3U)
|
|
/*! R3T3 - Read receive FIFO bit 3 or write transmit FIFO bit 3 */
|
|
#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
|
|
|
|
#define LPUART_DATA_R4T4_MASK (0x10U)
|
|
#define LPUART_DATA_R4T4_SHIFT (4U)
|
|
/*! R4T4 - Read receive FIFO bit 4 or write transmit FIFO bit 4 */
|
|
#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
|
|
|
|
#define LPUART_DATA_R5T5_MASK (0x20U)
|
|
#define LPUART_DATA_R5T5_SHIFT (5U)
|
|
/*! R5T5 - Read receive FIFO bit 5 or write transmit FIFO bit 5 */
|
|
#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
|
|
|
|
#define LPUART_DATA_R6T6_MASK (0x40U)
|
|
#define LPUART_DATA_R6T6_SHIFT (6U)
|
|
/*! R6T6 - Read receive FIFO bit 6 or write transmit FIFO bit 6 */
|
|
#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
|
|
|
|
#define LPUART_DATA_R7T7_MASK (0x80U)
|
|
#define LPUART_DATA_R7T7_SHIFT (7U)
|
|
/*! R7T7 - Read receive FIFO bit 7 or write transmit FIFO bit 7 */
|
|
#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
|
|
|
|
#define LPUART_DATA_R8T8_MASK (0x100U)
|
|
#define LPUART_DATA_R8T8_SHIFT (8U)
|
|
/*! R8T8 - Read receive FIFO bit 8 or write transmit FIFO bit 8 */
|
|
#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
|
|
|
|
#define LPUART_DATA_R9T9_MASK (0x200U)
|
|
#define LPUART_DATA_R9T9_SHIFT (9U)
|
|
/*! R9T9 - Read receive FIFO bit 9 or write transmit FIFO bit 9 */
|
|
#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
|
|
|
|
#define LPUART_DATA_LINBRK_MASK (0x400U)
|
|
#define LPUART_DATA_LINBRK_SHIFT (10U)
|
|
/*! LINBRK - LIN Break
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
*/
|
|
#define LPUART_DATA_LINBRK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_LINBRK_SHIFT)) & LPUART_DATA_LINBRK_MASK)
|
|
|
|
#define LPUART_DATA_IDLINE_MASK (0x800U)
|
|
#define LPUART_DATA_IDLINE_SHIFT (11U)
|
|
/*! IDLINE - Idle Line
|
|
* 0b0..Not idle
|
|
* 0b1..Idle
|
|
*/
|
|
#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
|
|
|
|
#define LPUART_DATA_RXEMPT_MASK (0x1000U)
|
|
#define LPUART_DATA_RXEMPT_SHIFT (12U)
|
|
/*! RXEMPT - Receive Buffer Empty
|
|
* 0b0..Valid data
|
|
* 0b1..Invalid data and empty
|
|
*/
|
|
#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
|
|
|
|
#define LPUART_DATA_FRETSC_MASK (0x2000U)
|
|
#define LPUART_DATA_FRETSC_SHIFT (13U)
|
|
/*! FRETSC - Frame Error Transmit Special Character
|
|
* 0b0..Received without a frame error on reads or transmits a normal character on writes
|
|
* 0b1..Received with a frame error on reads or transmits an idle or break character on writes
|
|
*/
|
|
#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
|
|
|
|
#define LPUART_DATA_PARITYE_MASK (0x4000U)
|
|
#define LPUART_DATA_PARITYE_SHIFT (14U)
|
|
/*! PARITYE - Parity Error
|
|
* 0b0..Received without a parity error
|
|
* 0b1..Received with a parity error
|
|
*/
|
|
#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
|
|
|
|
#define LPUART_DATA_NOISY_MASK (0x8000U)
|
|
#define LPUART_DATA_NOISY_SHIFT (15U)
|
|
/*! NOISY - Noisy Data Received
|
|
* 0b0..Received without noise
|
|
* 0b1..Received with noise
|
|
*/
|
|
#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MATCH - Match Address */
|
|
/*! @{ */
|
|
|
|
#define LPUART_MATCH_MA1_MASK (0x3FFU)
|
|
#define LPUART_MATCH_MA1_SHIFT (0U)
|
|
/*! MA1 - Match Address 1 */
|
|
#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
|
|
|
|
#define LPUART_MATCH_MA2_MASK (0x3FF0000U)
|
|
#define LPUART_MATCH_MA2_SHIFT (16U)
|
|
/*! MA2 - Match Address 2 */
|
|
#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MODIR - MODEM IrDA */
|
|
/*! @{ */
|
|
|
|
#define LPUART_MODIR_TXCTSE_MASK (0x1U)
|
|
#define LPUART_MODIR_TXCTSE_SHIFT (0U)
|
|
/*! TXCTSE - Transmitter CTS Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
|
|
|
|
#define LPUART_MODIR_TXRTSE_MASK (0x2U)
|
|
#define LPUART_MODIR_TXRTSE_SHIFT (1U)
|
|
/*! TXRTSE - Transmitter RTS Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
|
|
|
|
#define LPUART_MODIR_TXRTSPOL_MASK (0x4U)
|
|
#define LPUART_MODIR_TXRTSPOL_SHIFT (2U)
|
|
/*! TXRTSPOL - Transmitter RTS Polarity
|
|
* 0b0..Active low
|
|
* 0b1..Active high
|
|
*/
|
|
#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
|
|
|
|
#define LPUART_MODIR_RXRTSE_MASK (0x8U)
|
|
#define LPUART_MODIR_RXRTSE_SHIFT (3U)
|
|
/*! RXRTSE - Receiver RTS Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
|
|
|
|
#define LPUART_MODIR_TXCTSC_MASK (0x10U)
|
|
#define LPUART_MODIR_TXCTSC_SHIFT (4U)
|
|
/*! TXCTSC - Transmit CTS Configuration
|
|
* 0b0..Sampled at the start of each character
|
|
* 0b1..Sampled when the transmitter is idle
|
|
*/
|
|
#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
|
|
|
|
#define LPUART_MODIR_TXCTSSRC_MASK (0x20U)
|
|
#define LPUART_MODIR_TXCTSSRC_SHIFT (5U)
|
|
/*! TXCTSSRC - Transmit CTS Source
|
|
* 0b0..The CTS_B pin
|
|
* 0b1..An internal connection to the receiver address match result
|
|
*/
|
|
#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
|
|
|
|
#define LPUART_MODIR_RTSWATER_MASK (0x300U)
|
|
#define LPUART_MODIR_RTSWATER_SHIFT (8U)
|
|
/*! RTSWATER - Receive RTS Configuration */
|
|
#define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)
|
|
|
|
#define LPUART_MODIR_TNP_MASK (0x30000U)
|
|
#define LPUART_MODIR_TNP_SHIFT (16U)
|
|
/*! TNP - Transmitter Narrow Pulse
|
|
* 0b00..1 / OSR
|
|
* 0b01..2 / OSR
|
|
* 0b10..3 / OSR
|
|
* 0b11..4 / OSR
|
|
*/
|
|
#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
|
|
|
|
#define LPUART_MODIR_IREN_MASK (0x40000U)
|
|
#define LPUART_MODIR_IREN_SHIFT (18U)
|
|
/*! IREN - IR Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FIFO - FIFO */
|
|
/*! @{ */
|
|
|
|
#define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U)
|
|
#define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U)
|
|
/*! RXFIFOSIZE - Receive FIFO Buffer Depth
|
|
* 0b000..1
|
|
* 0b001..4
|
|
* 0b010..8
|
|
* 0b011..16
|
|
* 0b100..32
|
|
* 0b101..64
|
|
* 0b110..128
|
|
* 0b111..256
|
|
*/
|
|
#define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)
|
|
|
|
#define LPUART_FIFO_RXFE_MASK (0x8U)
|
|
#define LPUART_FIFO_RXFE_SHIFT (3U)
|
|
/*! RXFE - Receive FIFO Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)
|
|
|
|
#define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U)
|
|
#define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U)
|
|
/*! TXFIFOSIZE - Transmit FIFO Buffer Depth
|
|
* 0b000..1
|
|
* 0b001..4
|
|
* 0b010..8
|
|
* 0b011..16
|
|
* 0b100..32
|
|
* 0b101..64
|
|
* 0b110..128
|
|
* 0b111..256
|
|
*/
|
|
#define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)
|
|
|
|
#define LPUART_FIFO_TXFE_MASK (0x80U)
|
|
#define LPUART_FIFO_TXFE_SHIFT (7U)
|
|
/*! TXFE - Transmit FIFO Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)
|
|
|
|
#define LPUART_FIFO_RXUFE_MASK (0x100U)
|
|
#define LPUART_FIFO_RXUFE_SHIFT (8U)
|
|
/*! RXUFE - Receive FIFO Underflow Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)
|
|
|
|
#define LPUART_FIFO_TXOFE_MASK (0x200U)
|
|
#define LPUART_FIFO_TXOFE_SHIFT (9U)
|
|
/*! TXOFE - Transmit FIFO Overflow Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)
|
|
|
|
#define LPUART_FIFO_RXIDEN_MASK (0x1C00U)
|
|
#define LPUART_FIFO_RXIDEN_SHIFT (10U)
|
|
/*! RXIDEN - Receiver Idle Empty Enable
|
|
* 0b000..Disable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle
|
|
* 0b001..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for one character
|
|
* 0b010..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for two characters
|
|
* 0b011..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for four characters
|
|
* 0b100..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for eight characters
|
|
* 0b101..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 16 characters
|
|
* 0b110..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 32 characters
|
|
* 0b111..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 64 characters
|
|
*/
|
|
#define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)
|
|
|
|
#define LPUART_FIFO_RXFLUSH_MASK (0x4000U)
|
|
#define LPUART_FIFO_RXFLUSH_SHIFT (14U)
|
|
/*! RXFLUSH - Receive FIFO Flush
|
|
* 0b0..No effect
|
|
* 0b1..All data flushed out
|
|
*/
|
|
#define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)
|
|
|
|
#define LPUART_FIFO_TXFLUSH_MASK (0x8000U)
|
|
#define LPUART_FIFO_TXFLUSH_SHIFT (15U)
|
|
/*! TXFLUSH - Transmit FIFO Flush
|
|
* 0b0..No effect
|
|
* 0b1..All data flushed out
|
|
*/
|
|
#define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)
|
|
|
|
#define LPUART_FIFO_RXUF_MASK (0x10000U)
|
|
#define LPUART_FIFO_RXUF_SHIFT (16U)
|
|
/*! RXUF - Receiver FIFO Underflow Flag
|
|
* 0b0..No underflow
|
|
* 0b1..Underflow
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)
|
|
|
|
#define LPUART_FIFO_TXOF_MASK (0x20000U)
|
|
#define LPUART_FIFO_TXOF_SHIFT (17U)
|
|
/*! TXOF - Transmitter FIFO Overflow Flag
|
|
* 0b0..No overflow
|
|
* 0b1..Overflow
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)
|
|
|
|
#define LPUART_FIFO_RXEMPT_MASK (0x400000U)
|
|
#define LPUART_FIFO_RXEMPT_SHIFT (22U)
|
|
/*! RXEMPT - Receive FIFO Or Buffer Empty
|
|
* 0b0..Not empty
|
|
* 0b1..Empty
|
|
*/
|
|
#define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)
|
|
|
|
#define LPUART_FIFO_TXEMPT_MASK (0x800000U)
|
|
#define LPUART_FIFO_TXEMPT_SHIFT (23U)
|
|
/*! TXEMPT - Transmit FIFO Or Buffer Empty
|
|
* 0b0..Not empty
|
|
* 0b1..Empty
|
|
*/
|
|
#define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name WATER - Watermark */
|
|
/*! @{ */
|
|
|
|
#define LPUART_WATER_TXWATER_MASK (0x3U)
|
|
#define LPUART_WATER_TXWATER_SHIFT (0U)
|
|
/*! TXWATER - Transmit Watermark */
|
|
#define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)
|
|
|
|
#define LPUART_WATER_TXCOUNT_MASK (0x700U)
|
|
#define LPUART_WATER_TXCOUNT_SHIFT (8U)
|
|
/*! TXCOUNT - Transmit Counter */
|
|
#define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)
|
|
|
|
#define LPUART_WATER_RXWATER_MASK (0x30000U)
|
|
#define LPUART_WATER_RXWATER_SHIFT (16U)
|
|
/*! RXWATER - Receive Watermark */
|
|
#define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)
|
|
|
|
#define LPUART_WATER_RXCOUNT_MASK (0x7000000U)
|
|
#define LPUART_WATER_RXCOUNT_SHIFT (24U)
|
|
/*! RXCOUNT - Receive Counter */
|
|
#define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DATARO - Data Read-Only */
|
|
/*! @{ */
|
|
|
|
#define LPUART_DATARO_DATA_MASK (0xFFFFU)
|
|
#define LPUART_DATARO_DATA_SHIFT (0U)
|
|
/*! DATA - Receive Data */
|
|
#define LPUART_DATARO_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATARO_DATA_SHIFT)) & LPUART_DATARO_DATA_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group LPUART_Register_Masks */
|
|
|
|
|
|
/* LPUART - Peripheral instance base addresses */
|
|
/** Peripheral LPUART0 base address */
|
|
#define LPUART0_BASE (0x4009F000u)
|
|
/** Peripheral LPUART0 base pointer */
|
|
#define LPUART0 ((LPUART_Type *)LPUART0_BASE)
|
|
/** Peripheral LPUART1 base address */
|
|
#define LPUART1_BASE (0x400A0000u)
|
|
/** Peripheral LPUART1 base pointer */
|
|
#define LPUART1 ((LPUART_Type *)LPUART1_BASE)
|
|
/** Peripheral LPUART2 base address */
|
|
#define LPUART2_BASE (0x400A1000u)
|
|
/** Peripheral LPUART2 base pointer */
|
|
#define LPUART2 ((LPUART_Type *)LPUART2_BASE)
|
|
/** Array initializer of LPUART peripheral base addresses */
|
|
#define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE }
|
|
/** Array initializer of LPUART peripheral base pointers */
|
|
#define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2 }
|
|
/** Interrupt vectors for the LPUART peripheral type */
|
|
#define LPUART_RX_TX_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn }
|
|
#define LPUART_ERR_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group LPUART_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- MBC Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup MBC_Peripheral_Access_Layer MBC Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** MBC - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t MBC0_MEM_GLBCFG[4]; /**< MBC Global Configuration Register, array offset: 0x0, array step: 0x4 */
|
|
__IO uint32_t MBC0_NSE_BLK_INDEX; /**< MBC NonSecure Enable Block Index, offset: 0x10 */
|
|
__O uint32_t MBC0_NSE_BLK_SET; /**< MBC NonSecure Enable Block Set, offset: 0x14 */
|
|
__O uint32_t MBC0_NSE_BLK_CLR; /**< MBC NonSecure Enable Block Clear, offset: 0x18 */
|
|
__O uint32_t MBC0_NSE_BLK_CLR_ALL; /**< MBC NonSecure Enable Block Clear All, offset: 0x1C */
|
|
__IO uint32_t MBC0_MEMN_GLBAC[8]; /**< MBC Global Access Control, array offset: 0x20, array step: 0x4 */
|
|
struct { /* offset: 0x40, array step: 0x18C */
|
|
__IO uint32_t MBC0_DOM_MEM0_BLK_CFG_W0; /**< MBC Memory Block Configuration Word, array offset: 0x40, array step: 0x18C */
|
|
__IO uint32_t MBC0_DOM_MEM0_BLK_CFG_W1; /**< MBC Memory Block Configuration Word, array offset: 0x44, array step: 0x18C */
|
|
uint8_t RESERVED_0[248];
|
|
__IO uint32_t MBC0_DOM_MEM0_BLK_NSE_W0; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x140, array step: 0x18C */
|
|
uint8_t RESERVED_1[60];
|
|
__IO uint32_t MBC0_DOM_MEM1_BLK_CFG_W0; /**< MBC Memory Block Configuration Word, array offset: 0x180, array step: 0x18C */
|
|
uint8_t RESERVED_2[28];
|
|
__IO uint32_t MBC0_DOM_MEM1_BLK_NSE_W0; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1A0, array step: 0x18C */
|
|
uint8_t RESERVED_3[4];
|
|
__IO uint32_t MBC0_DOM_MEM2_BLK_CFG_W0; /**< MBC Memory Block Configuration Word, array offset: 0x1A8, array step: 0x18C */
|
|
uint8_t RESERVED_4[28];
|
|
__IO uint32_t MBC0_DOM_MEM2_BLK_NSE_W0; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1C8, array step: 0x18C */
|
|
} MBC_DOM0[1];
|
|
} MBC_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- MBC Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup MBC_Register_Masks MBC Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG - MBC Global Configuration Register */
|
|
/*! @{ */
|
|
|
|
#define MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_NBLKS_MASK (0x3FFU)
|
|
#define MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_NBLKS_SHIFT (0U)
|
|
/*! NBLKS - Number of blocks in this memory */
|
|
#define MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_NBLKS(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_NBLKS_SHIFT)) & MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_NBLKS_MASK)
|
|
|
|
#define MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_SIZE_LOG2_MASK (0x1F0000U)
|
|
#define MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_SIZE_LOG2_SHIFT (16U)
|
|
/*! SIZE_LOG2 - Log2 size per block */
|
|
#define MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_SIZE_LOG2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_SIZE_LOG2_SHIFT)) & MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_SIZE_LOG2_MASK)
|
|
|
|
#define MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_CLRE_MASK (0xC0000000U)
|
|
#define MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_CLRE_SHIFT (30U)
|
|
/*! CLRE - Clear Error */
|
|
#define MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_CLRE(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_CLRE_SHIFT)) & MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_CLRE_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG */
|
|
#define MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_COUNT (4U)
|
|
|
|
/*! @name MBC0_NSE_BLK_INDEX - MBC NonSecure Enable Block Index */
|
|
/*! @{ */
|
|
|
|
#define MBC_MBC0_NSE_BLK_INDEX_WNDX_MASK (0x3CU)
|
|
#define MBC_MBC0_NSE_BLK_INDEX_WNDX_SHIFT (2U)
|
|
/*! WNDX - Word index into the block NSE bitmap. It selects the BLK_NSE_Wn register, where WNDX determines the value of n. */
|
|
#define MBC_MBC0_NSE_BLK_INDEX_WNDX(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC0_NSE_BLK_INDEX_WNDX_SHIFT)) & MBC_MBC0_NSE_BLK_INDEX_WNDX_MASK)
|
|
|
|
#define MBC_MBC0_NSE_BLK_INDEX_MEM_SEL_MASK (0xF00U)
|
|
#define MBC_MBC0_NSE_BLK_INDEX_MEM_SEL_SHIFT (8U)
|
|
/*! MEM_SEL - Memory Select */
|
|
#define MBC_MBC0_NSE_BLK_INDEX_MEM_SEL(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC0_NSE_BLK_INDEX_MEM_SEL_SHIFT)) & MBC_MBC0_NSE_BLK_INDEX_MEM_SEL_MASK)
|
|
|
|
#define MBC_MBC0_NSE_BLK_INDEX_DID_SEL0_MASK (0x10000U)
|
|
#define MBC_MBC0_NSE_BLK_INDEX_DID_SEL0_SHIFT (16U)
|
|
/*! DID_SEL0 - DID Select
|
|
* 0b0..No effect.
|
|
* 0b1..Selects NSE bits for this domain.
|
|
*/
|
|
#define MBC_MBC0_NSE_BLK_INDEX_DID_SEL0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC0_NSE_BLK_INDEX_DID_SEL0_SHIFT)) & MBC_MBC0_NSE_BLK_INDEX_DID_SEL0_MASK)
|
|
|
|
#define MBC_MBC0_NSE_BLK_INDEX_AI_MASK (0x80000000U)
|
|
#define MBC_MBC0_NSE_BLK_INDEX_AI_SHIFT (31U)
|
|
/*! AI - Auto Increment
|
|
* 0b0..No effect.
|
|
* 0b1..Add 1 to the WNDX field after the register write.
|
|
*/
|
|
#define MBC_MBC0_NSE_BLK_INDEX_AI(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC0_NSE_BLK_INDEX_AI_SHIFT)) & MBC_MBC0_NSE_BLK_INDEX_AI_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MBC0_NSE_BLK_SET - MBC NonSecure Enable Block Set */
|
|
/*! @{ */
|
|
|
|
#define MBC_MBC0_NSE_BLK_SET_W1SET_MASK (0xFFFFFFFFU)
|
|
#define MBC_MBC0_NSE_BLK_SET_W1SET_SHIFT (0U)
|
|
/*! W1SET - Write-1 Set */
|
|
#define MBC_MBC0_NSE_BLK_SET_W1SET(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC0_NSE_BLK_SET_W1SET_SHIFT)) & MBC_MBC0_NSE_BLK_SET_W1SET_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MBC0_NSE_BLK_CLR - MBC NonSecure Enable Block Clear */
|
|
/*! @{ */
|
|
|
|
#define MBC_MBC0_NSE_BLK_CLR_W1CLR_MASK (0xFFFFFFFFU)
|
|
#define MBC_MBC0_NSE_BLK_CLR_W1CLR_SHIFT (0U)
|
|
/*! W1CLR - Write-1 Clear */
|
|
#define MBC_MBC0_NSE_BLK_CLR_W1CLR(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC0_NSE_BLK_CLR_W1CLR_SHIFT)) & MBC_MBC0_NSE_BLK_CLR_W1CLR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MBC0_NSE_BLK_CLR_ALL - MBC NonSecure Enable Block Clear All */
|
|
/*! @{ */
|
|
|
|
#define MBC_MBC0_NSE_BLK_CLR_ALL_MEMSEL_MASK (0xF00U)
|
|
#define MBC_MBC0_NSE_BLK_CLR_ALL_MEMSEL_SHIFT (8U)
|
|
/*! MEMSEL - Memory Select */
|
|
#define MBC_MBC0_NSE_BLK_CLR_ALL_MEMSEL(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC0_NSE_BLK_CLR_ALL_MEMSEL_SHIFT)) & MBC_MBC0_NSE_BLK_CLR_ALL_MEMSEL_MASK)
|
|
|
|
#define MBC_MBC0_NSE_BLK_CLR_ALL_DID_SEL0_MASK (0x10000U)
|
|
#define MBC_MBC0_NSE_BLK_CLR_ALL_DID_SEL0_SHIFT (16U)
|
|
/*! DID_SEL0 - DID Select
|
|
* 0b0..No effect.
|
|
* 0b1..Clear all NSE bits for this domain.
|
|
*/
|
|
#define MBC_MBC0_NSE_BLK_CLR_ALL_DID_SEL0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC0_NSE_BLK_CLR_ALL_DID_SEL0_SHIFT)) & MBC_MBC0_NSE_BLK_CLR_ALL_DID_SEL0_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC - MBC Global Access Control */
|
|
/*! @{ */
|
|
|
|
#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUX_MASK (0x1U)
|
|
#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUX_SHIFT (0U)
|
|
/*! NUX - NonsecureUser Execute
|
|
* 0b0..Execute access is not allowed in Nonsecure User mode.
|
|
* 0b1..Execute access is allowed in Nonsecure User mode.
|
|
*/
|
|
#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUX(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUX_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUX_MASK)
|
|
|
|
#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUW_MASK (0x2U)
|
|
#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUW_SHIFT (1U)
|
|
/*! NUW - NonsecureUser Write
|
|
* 0b0..Write access is not allowed in Nonsecure User mode.
|
|
* 0b1..Write access is allowed in Nonsecure User mode.
|
|
*/
|
|
#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUW(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUW_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUW_MASK)
|
|
|
|
#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUR_MASK (0x4U)
|
|
#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUR_SHIFT (2U)
|
|
/*! NUR - NonsecureUser Read
|
|
* 0b0..Read access is not allowed in Nonsecure User mode.
|
|
* 0b1..Read access is allowed in Nonsecure User mode.
|
|
*/
|
|
#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUR(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUR_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUR_MASK)
|
|
|
|
#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPX_MASK (0x10U)
|
|
#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPX_SHIFT (4U)
|
|
/*! NPX - NonsecurePriv Execute
|
|
* 0b0..Execute access is not allowed in Nonsecure Privilege mode.
|
|
* 0b1..Execute access is allowed in Nonsecure Privilege mode.
|
|
*/
|
|
#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPX(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPX_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPX_MASK)
|
|
|
|
#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPW_MASK (0x20U)
|
|
#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPW_SHIFT (5U)
|
|
/*! NPW - NonsecurePriv Write
|
|
* 0b0..Write access is not allowed in Nonsecure Privilege mode.
|
|
* 0b1..Write access is allowed in Nonsecure Privilege mode.
|
|
*/
|
|
#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPW(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPW_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPW_MASK)
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#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPR_MASK (0x40U)
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#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPR_SHIFT (6U)
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/*! NPR - NonsecurePriv Read
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* 0b0..Read access is not allowed in Nonsecure Privilege mode.
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* 0b1..Read access is allowed in Nonsecure Privilege mode.
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*/
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#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPR(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPR_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPR_MASK)
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#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUX_MASK (0x100U)
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#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUX_SHIFT (8U)
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/*! SUX - SecureUser Execute
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* 0b0..Execute access is not allowed in Secure User mode.
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* 0b1..Execute access is allowed in Secure User mode.
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*/
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#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUX(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUX_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUX_MASK)
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#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUW_MASK (0x200U)
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#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUW_SHIFT (9U)
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/*! SUW - SecureUser Write
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* 0b0..Write access is not allowed in Secure User mode.
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* 0b1..Write access is allowed in Secure User mode.
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*/
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#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUW(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUW_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUW_MASK)
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#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUR_MASK (0x400U)
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#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUR_SHIFT (10U)
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/*! SUR - SecureUser Read
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* 0b0..Read access is not allowed in Secure User mode.
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* 0b1..Read access is allowed in Secure User mode.
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*/
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#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUR(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUR_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUR_MASK)
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#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPX_MASK (0x1000U)
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#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPX_SHIFT (12U)
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/*! SPX - SecurePriv Execute
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* 0b0..Execute access is not allowed in Secure Privilege mode.
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* 0b1..Execute access is allowed in Secure Privilege mode.
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*/
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#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPX(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPX_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPX_MASK)
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#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPW_MASK (0x2000U)
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#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPW_SHIFT (13U)
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/*! SPW - SecurePriv Write
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* 0b0..Write access is not allowed in Secure Privilege mode.
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* 0b1..Write access is allowed in Secure Privilege mode.
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*/
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#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPW(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPW_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPW_MASK)
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#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPR_MASK (0x4000U)
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#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPR_SHIFT (14U)
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/*! SPR - SecurePriv Read
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* 0b0..Read access is not allowed in Secure Privilege mode.
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* 0b1..Read access is allowed in Secure Privilege mode.
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*/
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#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPR(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPR_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPR_MASK)
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#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_LK_MASK (0x80000000U)
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#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_LK_SHIFT (31U)
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/*! LK - LOCK
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* 0b0..This register is not locked and can be altered.
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* 0b1..This register is locked and cannot be altered.
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*/
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#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_LK(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_LK_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_LK_MASK)
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/*! @} */
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/* The count of MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC */
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#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_COUNT (8U)
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/*! @name MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0 - MBC Memory Block Configuration Word */
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/*! @{ */
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL0_MASK (0x7U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL0_SHIFT (0U)
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/*! MBACSEL0 - Memory Block Access Control Select for block B
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* 0b000..select MBC_MEMN_GLBAC0 access control policy for block B
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* 0b001..select MBC_MEMN_GLBAC1 access control policy for block B
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* 0b010..select MBC_MEMN_GLBAC2 access control policy for block B
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* 0b011..select MBC_MEMN_GLBAC3 access control policy for block B
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* 0b100..select MBC_MEMN_GLBAC4 access control policy for block B
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* 0b101..select MBC_MEMN_GLBAC5 access control policy for block B
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* 0b110..select MBC_MEMN_GLBAC6 access control policy for block B
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* 0b111..select MBC_MEMN_GLBAC7 access control policy for block B
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL0_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE0_MASK (0x8U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE0_SHIFT (3U)
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/*! NSE0 - NonSecure Enable for block B
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE0_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL1_MASK (0x70U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL1_SHIFT (4U)
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/*! MBACSEL1 - Memory Block Access Control Select for block B
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* 0b000..select MBC_MEMN_GLBAC0 access control policy for block B
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* 0b001..select MBC_MEMN_GLBAC1 access control policy for block B
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* 0b010..select MBC_MEMN_GLBAC2 access control policy for block B
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* 0b011..select MBC_MEMN_GLBAC3 access control policy for block B
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* 0b100..select MBC_MEMN_GLBAC4 access control policy for block B
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* 0b101..select MBC_MEMN_GLBAC5 access control policy for block B
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* 0b110..select MBC_MEMN_GLBAC6 access control policy for block B
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* 0b111..select MBC_MEMN_GLBAC7 access control policy for block B
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL1_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE1_MASK (0x80U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE1_SHIFT (7U)
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/*! NSE1 - NonSecure Enable for block B
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE1_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL2_MASK (0x700U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL2_SHIFT (8U)
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/*! MBACSEL2 - Memory Block Access Control Select for block B
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* 0b000..select MBC_MEMN_GLBAC0 access control policy for block B
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* 0b001..select MBC_MEMN_GLBAC1 access control policy for block B
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* 0b010..select MBC_MEMN_GLBAC2 access control policy for block B
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* 0b011..select MBC_MEMN_GLBAC3 access control policy for block B
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* 0b100..select MBC_MEMN_GLBAC4 access control policy for block B
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* 0b101..select MBC_MEMN_GLBAC5 access control policy for block B
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* 0b110..select MBC_MEMN_GLBAC6 access control policy for block B
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* 0b111..select MBC_MEMN_GLBAC7 access control policy for block B
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL2_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE2_MASK (0x800U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE2_SHIFT (11U)
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/*! NSE2 - NonSecure Enable for block B
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
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* MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE2_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL3_MASK (0x7000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL3_SHIFT (12U)
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/*! MBACSEL3 - Memory Block Access Control Select for block B
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* 0b000..select MBC_MEMN_GLBAC0 access control policy for block B
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* 0b001..select MBC_MEMN_GLBAC1 access control policy for block B
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* 0b010..select MBC_MEMN_GLBAC2 access control policy for block B
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* 0b011..select MBC_MEMN_GLBAC3 access control policy for block B
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* 0b100..select MBC_MEMN_GLBAC4 access control policy for block B
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* 0b101..select MBC_MEMN_GLBAC5 access control policy for block B
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* 0b110..select MBC_MEMN_GLBAC6 access control policy for block B
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* 0b111..select MBC_MEMN_GLBAC7 access control policy for block B
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL3_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE3_MASK (0x8000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE3_SHIFT (15U)
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/*! NSE3 - NonSecure Enable for block B
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
|
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
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* MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE3_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL4_MASK (0x70000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL4_SHIFT (16U)
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/*! MBACSEL4 - Memory Block Access Control Select for block B
|
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* 0b000..select MBC_MEMN_GLBAC0 access control policy for block B
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* 0b001..select MBC_MEMN_GLBAC1 access control policy for block B
|
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* 0b010..select MBC_MEMN_GLBAC2 access control policy for block B
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* 0b011..select MBC_MEMN_GLBAC3 access control policy for block B
|
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* 0b100..select MBC_MEMN_GLBAC4 access control policy for block B
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* 0b101..select MBC_MEMN_GLBAC5 access control policy for block B
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* 0b110..select MBC_MEMN_GLBAC6 access control policy for block B
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* 0b111..select MBC_MEMN_GLBAC7 access control policy for block B
|
|
*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL4_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE4_MASK (0x80000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE4_SHIFT (19U)
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/*! NSE4 - NonSecure Enable for block B
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE4_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL5_MASK (0x700000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL5_SHIFT (20U)
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/*! MBACSEL5 - Memory Block Access Control Select for block B
|
|
* 0b000..select MBC_MEMN_GLBAC0 access control policy for block B
|
|
* 0b001..select MBC_MEMN_GLBAC1 access control policy for block B
|
|
* 0b010..select MBC_MEMN_GLBAC2 access control policy for block B
|
|
* 0b011..select MBC_MEMN_GLBAC3 access control policy for block B
|
|
* 0b100..select MBC_MEMN_GLBAC4 access control policy for block B
|
|
* 0b101..select MBC_MEMN_GLBAC5 access control policy for block B
|
|
* 0b110..select MBC_MEMN_GLBAC6 access control policy for block B
|
|
* 0b111..select MBC_MEMN_GLBAC7 access control policy for block B
|
|
*/
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|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL5_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE5_MASK (0x800000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE5_SHIFT (23U)
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|
/*! NSE5 - NonSecure Enable for block B
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE5_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL6_MASK (0x7000000U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL6_SHIFT (24U)
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/*! MBACSEL6 - Memory Block Access Control Select for block B
|
|
* 0b000..select MBC_MEMN_GLBAC0 access control policy for block B
|
|
* 0b001..select MBC_MEMN_GLBAC1 access control policy for block B
|
|
* 0b010..select MBC_MEMN_GLBAC2 access control policy for block B
|
|
* 0b011..select MBC_MEMN_GLBAC3 access control policy for block B
|
|
* 0b100..select MBC_MEMN_GLBAC4 access control policy for block B
|
|
* 0b101..select MBC_MEMN_GLBAC5 access control policy for block B
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|
* 0b110..select MBC_MEMN_GLBAC6 access control policy for block B
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* 0b111..select MBC_MEMN_GLBAC7 access control policy for block B
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|
*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL6_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE6_MASK (0x8000000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE6_SHIFT (27U)
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/*! NSE6 - NonSecure Enable for block B
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
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|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE6_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL7_MASK (0x70000000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL7_SHIFT (28U)
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/*! MBACSEL7 - Memory Block Access Control Select for block B
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* 0b000..select MBC_MEMN_GLBAC0 access control policy for block B
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* 0b001..select MBC_MEMN_GLBAC1 access control policy for block B
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* 0b010..select MBC_MEMN_GLBAC2 access control policy for block B
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* 0b011..select MBC_MEMN_GLBAC3 access control policy for block B
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* 0b100..select MBC_MEMN_GLBAC4 access control policy for block B
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* 0b101..select MBC_MEMN_GLBAC5 access control policy for block B
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* 0b110..select MBC_MEMN_GLBAC6 access control policy for block B
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* 0b111..select MBC_MEMN_GLBAC7 access control policy for block B
|
|
*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL7_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE7_MASK (0x80000000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE7_SHIFT (31U)
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/*! NSE7 - NonSecure Enable for block B
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
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* MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE7_MASK)
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/*! @} */
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/* The count of MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0 */
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_COUNT (1U)
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/*! @name MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1 - MBC Memory Block Configuration Word */
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/*! @{ */
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL0_MASK (0x7U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL0_SHIFT (0U)
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/*! MBACSEL0 - Memory Block Access Control Select for block B
|
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* 0b000..select MBC_MEMN_GLBAC0 access control policy for block B
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* 0b001..select MBC_MEMN_GLBAC1 access control policy for block B
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* 0b010..select MBC_MEMN_GLBAC2 access control policy for block B
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* 0b011..select MBC_MEMN_GLBAC3 access control policy for block B
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* 0b100..select MBC_MEMN_GLBAC4 access control policy for block B
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* 0b101..select MBC_MEMN_GLBAC5 access control policy for block B
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* 0b110..select MBC_MEMN_GLBAC6 access control policy for block B
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* 0b111..select MBC_MEMN_GLBAC7 access control policy for block B
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL0_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE0_MASK (0x8U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE0_SHIFT (3U)
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/*! NSE0 - NonSecure Enable for block B
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
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* MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE0_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL1_MASK (0x70U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL1_SHIFT (4U)
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/*! MBACSEL1 - Memory Block Access Control Select for block B
|
|
* 0b000..select MBC_MEMN_GLBAC0 access control policy for block B
|
|
* 0b001..select MBC_MEMN_GLBAC1 access control policy for block B
|
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* 0b010..select MBC_MEMN_GLBAC2 access control policy for block B
|
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* 0b011..select MBC_MEMN_GLBAC3 access control policy for block B
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* 0b100..select MBC_MEMN_GLBAC4 access control policy for block B
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* 0b101..select MBC_MEMN_GLBAC5 access control policy for block B
|
|
* 0b110..select MBC_MEMN_GLBAC6 access control policy for block B
|
|
* 0b111..select MBC_MEMN_GLBAC7 access control policy for block B
|
|
*/
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|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL1_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE1_MASK (0x80U)
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|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE1_SHIFT (7U)
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/*! NSE1 - NonSecure Enable for block B
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE1_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL2_MASK (0x700U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL2_SHIFT (8U)
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/*! MBACSEL2 - Memory Block Access Control Select for block B
|
|
* 0b000..select MBC_MEMN_GLBAC0 access control policy for block B
|
|
* 0b001..select MBC_MEMN_GLBAC1 access control policy for block B
|
|
* 0b010..select MBC_MEMN_GLBAC2 access control policy for block B
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* 0b011..select MBC_MEMN_GLBAC3 access control policy for block B
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|
* 0b100..select MBC_MEMN_GLBAC4 access control policy for block B
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* 0b101..select MBC_MEMN_GLBAC5 access control policy for block B
|
|
* 0b110..select MBC_MEMN_GLBAC6 access control policy for block B
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|
* 0b111..select MBC_MEMN_GLBAC7 access control policy for block B
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|
*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL2_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE2_MASK (0x800U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE2_SHIFT (11U)
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/*! NSE2 - NonSecure Enable for block B
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE2_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL3_MASK (0x7000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL3_SHIFT (12U)
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/*! MBACSEL3 - Memory Block Access Control Select for block B
|
|
* 0b000..select MBC_MEMN_GLBAC0 access control policy for block B
|
|
* 0b001..select MBC_MEMN_GLBAC1 access control policy for block B
|
|
* 0b010..select MBC_MEMN_GLBAC2 access control policy for block B
|
|
* 0b011..select MBC_MEMN_GLBAC3 access control policy for block B
|
|
* 0b100..select MBC_MEMN_GLBAC4 access control policy for block B
|
|
* 0b101..select MBC_MEMN_GLBAC5 access control policy for block B
|
|
* 0b110..select MBC_MEMN_GLBAC6 access control policy for block B
|
|
* 0b111..select MBC_MEMN_GLBAC7 access control policy for block B
|
|
*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL3_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE3_MASK (0x8000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE3_SHIFT (15U)
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/*! NSE3 - NonSecure Enable for block B
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
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|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE3_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL4_MASK (0x70000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL4_SHIFT (16U)
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/*! MBACSEL4 - Memory Block Access Control Select for block B
|
|
* 0b000..select MBC_MEMN_GLBAC0 access control policy for block B
|
|
* 0b001..select MBC_MEMN_GLBAC1 access control policy for block B
|
|
* 0b010..select MBC_MEMN_GLBAC2 access control policy for block B
|
|
* 0b011..select MBC_MEMN_GLBAC3 access control policy for block B
|
|
* 0b100..select MBC_MEMN_GLBAC4 access control policy for block B
|
|
* 0b101..select MBC_MEMN_GLBAC5 access control policy for block B
|
|
* 0b110..select MBC_MEMN_GLBAC6 access control policy for block B
|
|
* 0b111..select MBC_MEMN_GLBAC7 access control policy for block B
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL4_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE4_MASK (0x80000U)
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|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE4_SHIFT (19U)
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|
/*! NSE4 - NonSecure Enable for block B
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE4_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL5_MASK (0x700000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL5_SHIFT (20U)
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/*! MBACSEL5 - Memory Block Access Control Select for block B
|
|
* 0b000..select MBC_MEMN_GLBAC0 access control policy for block B
|
|
* 0b001..select MBC_MEMN_GLBAC1 access control policy for block B
|
|
* 0b010..select MBC_MEMN_GLBAC2 access control policy for block B
|
|
* 0b011..select MBC_MEMN_GLBAC3 access control policy for block B
|
|
* 0b100..select MBC_MEMN_GLBAC4 access control policy for block B
|
|
* 0b101..select MBC_MEMN_GLBAC5 access control policy for block B
|
|
* 0b110..select MBC_MEMN_GLBAC6 access control policy for block B
|
|
* 0b111..select MBC_MEMN_GLBAC7 access control policy for block B
|
|
*/
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|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL5_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE5_MASK (0x800000U)
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|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE5_SHIFT (23U)
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|
/*! NSE5 - NonSecure Enable for block B
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE5_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL6_MASK (0x7000000U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL6_SHIFT (24U)
|
|
/*! MBACSEL6 - Memory Block Access Control Select for block B
|
|
* 0b000..select MBC_MEMN_GLBAC0 access control policy for block B
|
|
* 0b001..select MBC_MEMN_GLBAC1 access control policy for block B
|
|
* 0b010..select MBC_MEMN_GLBAC2 access control policy for block B
|
|
* 0b011..select MBC_MEMN_GLBAC3 access control policy for block B
|
|
* 0b100..select MBC_MEMN_GLBAC4 access control policy for block B
|
|
* 0b101..select MBC_MEMN_GLBAC5 access control policy for block B
|
|
* 0b110..select MBC_MEMN_GLBAC6 access control policy for block B
|
|
* 0b111..select MBC_MEMN_GLBAC7 access control policy for block B
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL6_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE6_MASK (0x8000000U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE6_SHIFT (27U)
|
|
/*! NSE6 - NonSecure Enable for block B
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE6_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL7_MASK (0x70000000U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL7_SHIFT (28U)
|
|
/*! MBACSEL7 - Memory Block Access Control Select for block B
|
|
* 0b000..select MBC_MEMN_GLBAC0 access control policy for block B
|
|
* 0b001..select MBC_MEMN_GLBAC1 access control policy for block B
|
|
* 0b010..select MBC_MEMN_GLBAC2 access control policy for block B
|
|
* 0b011..select MBC_MEMN_GLBAC3 access control policy for block B
|
|
* 0b100..select MBC_MEMN_GLBAC4 access control policy for block B
|
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* 0b101..select MBC_MEMN_GLBAC5 access control policy for block B
|
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* 0b110..select MBC_MEMN_GLBAC6 access control policy for block B
|
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* 0b111..select MBC_MEMN_GLBAC7 access control policy for block B
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL7_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE7_MASK (0x80000000U)
|
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE7_SHIFT (31U)
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/*! NSE7 - NonSecure Enable for block B
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE7_MASK)
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/*! @} */
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/* The count of MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1 */
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_COUNT (1U)
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/*! @name MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0 - MBC Memory Block NonSecure Enable Word */
|
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/*! @{ */
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT0_MASK (0x1U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT0_SHIFT (0U)
|
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/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT0_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT1_MASK (0x2U)
|
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT1_SHIFT (1U)
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/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT1_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT2_MASK (0x4U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT2_SHIFT (2U)
|
|
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT2_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT3_MASK (0x8U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT3_SHIFT (3U)
|
|
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT3_MASK)
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|
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT4_MASK (0x10U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT4_SHIFT (4U)
|
|
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT4_MASK)
|
|
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT5_MASK (0x20U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT5_SHIFT (5U)
|
|
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT5_MASK)
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|
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT6_MASK (0x40U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT6_SHIFT (6U)
|
|
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT6_MASK)
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|
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT7_MASK (0x80U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT7_SHIFT (7U)
|
|
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT7_MASK)
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|
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT8_MASK (0x100U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT8_SHIFT (8U)
|
|
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT8(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT8_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT8_MASK)
|
|
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT9_MASK (0x200U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT9_SHIFT (9U)
|
|
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT9(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT9_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT9_MASK)
|
|
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT10_MASK (0x400U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT10_SHIFT (10U)
|
|
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT10(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT10_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT10_MASK)
|
|
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT11_MASK (0x800U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT11_SHIFT (11U)
|
|
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT11(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT11_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT11_MASK)
|
|
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT12_MASK (0x1000U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT12_SHIFT (12U)
|
|
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT12(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT12_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT12_MASK)
|
|
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT13_MASK (0x2000U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT13_SHIFT (13U)
|
|
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT13(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT13_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT13_MASK)
|
|
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|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT14_MASK (0x4000U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT14_SHIFT (14U)
|
|
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT14(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT14_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT14_MASK)
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|
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|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT15_MASK (0x8000U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT15_SHIFT (15U)
|
|
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT15(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT15_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT15_MASK)
|
|
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT16_MASK (0x10000U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT16_SHIFT (16U)
|
|
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT16(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT16_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT16_MASK)
|
|
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT17_MASK (0x20000U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT17_SHIFT (17U)
|
|
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT17(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT17_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT17_MASK)
|
|
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT18_MASK (0x40000U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT18_SHIFT (18U)
|
|
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT18(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT18_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT18_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT19_MASK (0x80000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT19_SHIFT (19U)
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/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT19(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT19_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT19_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT20_MASK (0x100000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT20_SHIFT (20U)
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/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT20(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT20_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT20_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT21_MASK (0x200000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT21_SHIFT (21U)
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/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT21(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT21_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT21_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT22_MASK (0x400000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT22_SHIFT (22U)
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/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
|
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT22(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT22_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT22_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT23_MASK (0x800000U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT23_SHIFT (23U)
|
|
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
|
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT23(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT23_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT23_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT24_MASK (0x1000000U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT24_SHIFT (24U)
|
|
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT24(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT24_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT24_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT25_MASK (0x2000000U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT25_SHIFT (25U)
|
|
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT25(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT25_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT25_MASK)
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|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT26_MASK (0x4000000U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT26_SHIFT (26U)
|
|
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT26(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT26_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT26_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT27_MASK (0x8000000U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT27_SHIFT (27U)
|
|
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT27(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT27_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT27_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT28_MASK (0x10000000U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT28_SHIFT (28U)
|
|
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT28(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT28_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT28_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT29_MASK (0x20000000U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT29_SHIFT (29U)
|
|
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT29(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT29_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT29_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT30_MASK (0x40000000U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT30_SHIFT (30U)
|
|
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT30(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT30_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT30_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT31_MASK (0x80000000U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT31_SHIFT (31U)
|
|
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT31(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT31_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT31_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0 */
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_COUNT (1U)
|
|
|
|
/*! @name MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0 - MBC Memory Block Configuration Word */
|
|
/*! @{ */
|
|
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL0_MASK (0x7U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL0_SHIFT (0U)
|
|
/*! MBACSEL0 - Memory Block Access Control Select for block B
|
|
* 0b000..select MBC_MEMN_GLBAC0 access control policy for block B
|
|
* 0b001..select MBC_MEMN_GLBAC1 access control policy for block B
|
|
* 0b010..select MBC_MEMN_GLBAC2 access control policy for block B
|
|
* 0b011..select MBC_MEMN_GLBAC3 access control policy for block B
|
|
* 0b100..select MBC_MEMN_GLBAC4 access control policy for block B
|
|
* 0b101..select MBC_MEMN_GLBAC5 access control policy for block B
|
|
* 0b110..select MBC_MEMN_GLBAC6 access control policy for block B
|
|
* 0b111..select MBC_MEMN_GLBAC7 access control policy for block B
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL0_MASK)
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|
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE0_MASK (0x8U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE0_SHIFT (3U)
|
|
/*! NSE0 - NonSecure Enable for block B
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE0_MASK)
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|
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|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL1_MASK (0x70U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL1_SHIFT (4U)
|
|
/*! MBACSEL1 - Memory Block Access Control Select for block B
|
|
* 0b000..select MBC_MEMN_GLBAC0 access control policy for block B
|
|
* 0b001..select MBC_MEMN_GLBAC1 access control policy for block B
|
|
* 0b010..select MBC_MEMN_GLBAC2 access control policy for block B
|
|
* 0b011..select MBC_MEMN_GLBAC3 access control policy for block B
|
|
* 0b100..select MBC_MEMN_GLBAC4 access control policy for block B
|
|
* 0b101..select MBC_MEMN_GLBAC5 access control policy for block B
|
|
* 0b110..select MBC_MEMN_GLBAC6 access control policy for block B
|
|
* 0b111..select MBC_MEMN_GLBAC7 access control policy for block B
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL1_MASK)
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|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE1_MASK (0x80U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE1_SHIFT (7U)
|
|
/*! NSE1 - NonSecure Enable for block B
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE1_MASK)
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|
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL2_MASK (0x700U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL2_SHIFT (8U)
|
|
/*! MBACSEL2 - Memory Block Access Control Select for block B
|
|
* 0b000..select MBC_MEMN_GLBAC0 access control policy for block B
|
|
* 0b001..select MBC_MEMN_GLBAC1 access control policy for block B
|
|
* 0b010..select MBC_MEMN_GLBAC2 access control policy for block B
|
|
* 0b011..select MBC_MEMN_GLBAC3 access control policy for block B
|
|
* 0b100..select MBC_MEMN_GLBAC4 access control policy for block B
|
|
* 0b101..select MBC_MEMN_GLBAC5 access control policy for block B
|
|
* 0b110..select MBC_MEMN_GLBAC6 access control policy for block B
|
|
* 0b111..select MBC_MEMN_GLBAC7 access control policy for block B
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL2_MASK)
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|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE2_MASK (0x800U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE2_SHIFT (11U)
|
|
/*! NSE2 - NonSecure Enable for block B
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE2_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL3_MASK (0x7000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL3_SHIFT (12U)
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/*! MBACSEL3 - Memory Block Access Control Select for block B
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* 0b000..select MBC_MEMN_GLBAC0 access control policy for block B
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* 0b001..select MBC_MEMN_GLBAC1 access control policy for block B
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* 0b010..select MBC_MEMN_GLBAC2 access control policy for block B
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* 0b011..select MBC_MEMN_GLBAC3 access control policy for block B
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* 0b100..select MBC_MEMN_GLBAC4 access control policy for block B
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* 0b101..select MBC_MEMN_GLBAC5 access control policy for block B
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* 0b110..select MBC_MEMN_GLBAC6 access control policy for block B
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* 0b111..select MBC_MEMN_GLBAC7 access control policy for block B
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL3_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE3_MASK (0x8000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE3_SHIFT (15U)
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/*! NSE3 - NonSecure Enable for block B
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE3_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL4_MASK (0x70000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL4_SHIFT (16U)
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/*! MBACSEL4 - Memory Block Access Control Select for block B
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* 0b000..select MBC_MEMN_GLBAC0 access control policy for block B
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* 0b001..select MBC_MEMN_GLBAC1 access control policy for block B
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* 0b010..select MBC_MEMN_GLBAC2 access control policy for block B
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* 0b011..select MBC_MEMN_GLBAC3 access control policy for block B
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* 0b100..select MBC_MEMN_GLBAC4 access control policy for block B
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* 0b101..select MBC_MEMN_GLBAC5 access control policy for block B
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* 0b110..select MBC_MEMN_GLBAC6 access control policy for block B
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* 0b111..select MBC_MEMN_GLBAC7 access control policy for block B
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL4_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE4_MASK (0x80000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE4_SHIFT (19U)
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/*! NSE4 - NonSecure Enable for block B
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE4_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL5_MASK (0x700000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL5_SHIFT (20U)
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/*! MBACSEL5 - Memory Block Access Control Select for block B
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* 0b000..select MBC_MEMN_GLBAC0 access control policy for block B
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* 0b001..select MBC_MEMN_GLBAC1 access control policy for block B
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* 0b010..select MBC_MEMN_GLBAC2 access control policy for block B
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* 0b011..select MBC_MEMN_GLBAC3 access control policy for block B
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* 0b100..select MBC_MEMN_GLBAC4 access control policy for block B
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* 0b101..select MBC_MEMN_GLBAC5 access control policy for block B
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* 0b110..select MBC_MEMN_GLBAC6 access control policy for block B
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* 0b111..select MBC_MEMN_GLBAC7 access control policy for block B
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL5_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE5_MASK (0x800000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE5_SHIFT (23U)
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/*! NSE5 - NonSecure Enable for block B
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE5_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL6_MASK (0x7000000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL6_SHIFT (24U)
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/*! MBACSEL6 - Memory Block Access Control Select for block B
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* 0b000..select MBC_MEMN_GLBAC0 access control policy for block B
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* 0b001..select MBC_MEMN_GLBAC1 access control policy for block B
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* 0b010..select MBC_MEMN_GLBAC2 access control policy for block B
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* 0b011..select MBC_MEMN_GLBAC3 access control policy for block B
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* 0b100..select MBC_MEMN_GLBAC4 access control policy for block B
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* 0b101..select MBC_MEMN_GLBAC5 access control policy for block B
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* 0b110..select MBC_MEMN_GLBAC6 access control policy for block B
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* 0b111..select MBC_MEMN_GLBAC7 access control policy for block B
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL6_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE6_MASK (0x8000000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE6_SHIFT (27U)
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/*! NSE6 - NonSecure Enable for block B
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE6_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL7_MASK (0x70000000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL7_SHIFT (28U)
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/*! MBACSEL7 - Memory Block Access Control Select for block B
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* 0b000..select MBC_MEMN_GLBAC0 access control policy for block B
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* 0b001..select MBC_MEMN_GLBAC1 access control policy for block B
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* 0b010..select MBC_MEMN_GLBAC2 access control policy for block B
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* 0b011..select MBC_MEMN_GLBAC3 access control policy for block B
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* 0b100..select MBC_MEMN_GLBAC4 access control policy for block B
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* 0b101..select MBC_MEMN_GLBAC5 access control policy for block B
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* 0b110..select MBC_MEMN_GLBAC6 access control policy for block B
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* 0b111..select MBC_MEMN_GLBAC7 access control policy for block B
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL7_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE7_MASK (0x80000000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE7_SHIFT (31U)
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/*! NSE7 - NonSecure Enable for block B
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE7_MASK)
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/*! @} */
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/* The count of MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0 */
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_COUNT (1U)
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/*! @name MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0 - MBC Memory Block NonSecure Enable Word */
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/*! @{ */
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT0_MASK (0x1U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT0_SHIFT (0U)
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/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT0_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT1_MASK (0x2U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT1_SHIFT (1U)
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/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT1_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT2_MASK (0x4U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT2_SHIFT (2U)
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/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT2_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT3_MASK (0x8U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT3_SHIFT (3U)
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/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT3_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT4_MASK (0x10U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT4_SHIFT (4U)
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/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT4_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT5_MASK (0x20U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT5_SHIFT (5U)
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/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT5_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT6_MASK (0x40U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT6_SHIFT (6U)
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/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT6_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT7_MASK (0x80U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT7_SHIFT (7U)
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/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
|
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT7_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT8_MASK (0x100U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT8_SHIFT (8U)
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/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
|
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT8(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT8_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT8_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT9_MASK (0x200U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT9_SHIFT (9U)
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/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT9(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT9_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT9_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT10_MASK (0x400U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT10_SHIFT (10U)
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/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT10(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT10_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT10_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT11_MASK (0x800U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT11_SHIFT (11U)
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/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT11(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT11_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT11_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT12_MASK (0x1000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT12_SHIFT (12U)
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/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT12(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT12_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT12_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT13_MASK (0x2000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT13_SHIFT (13U)
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/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT13(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT13_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT13_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT14_MASK (0x4000U)
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|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT14_SHIFT (14U)
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|
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
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|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
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|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT14(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT14_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT14_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT15_MASK (0x8000U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT15_SHIFT (15U)
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|
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT15(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT15_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT15_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT16_MASK (0x10000U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT16_SHIFT (16U)
|
|
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT16(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT16_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT16_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT17_MASK (0x20000U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT17_SHIFT (17U)
|
|
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT17(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT17_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT17_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT18_MASK (0x40000U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT18_SHIFT (18U)
|
|
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT18(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT18_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT18_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT19_MASK (0x80000U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT19_SHIFT (19U)
|
|
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT19(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT19_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT19_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT20_MASK (0x100000U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT20_SHIFT (20U)
|
|
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT20(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT20_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT20_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT21_MASK (0x200000U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT21_SHIFT (21U)
|
|
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT21(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT21_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT21_MASK)
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|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT22_MASK (0x400000U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT22_SHIFT (22U)
|
|
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT22(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT22_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT22_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT23_MASK (0x800000U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT23_SHIFT (23U)
|
|
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT23(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT23_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT23_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT24_MASK (0x1000000U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT24_SHIFT (24U)
|
|
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT24(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT24_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT24_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT25_MASK (0x2000000U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT25_SHIFT (25U)
|
|
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT25(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT25_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT25_MASK)
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|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT26_MASK (0x4000000U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT26_SHIFT (26U)
|
|
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT26(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT26_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT26_MASK)
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|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT27_MASK (0x8000000U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT27_SHIFT (27U)
|
|
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT27(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT27_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT27_MASK)
|
|
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|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT28_MASK (0x10000000U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT28_SHIFT (28U)
|
|
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT28(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT28_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT28_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT29_MASK (0x20000000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT29_SHIFT (29U)
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/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT29(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT29_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT29_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT30_MASK (0x40000000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT30_SHIFT (30U)
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/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT30(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT30_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT30_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT31_MASK (0x80000000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT31_SHIFT (31U)
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/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT31(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT31_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT31_MASK)
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/*! @} */
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/* The count of MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0 */
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#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_COUNT (1U)
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/*! @name MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0 - MBC Memory Block Configuration Word */
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/*! @{ */
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL0_MASK (0x7U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL0_SHIFT (0U)
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/*! MBACSEL0 - Memory Block Access Control Select for block B
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* 0b000..select MBC_MEMN_GLBAC0 access control policy for block B
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* 0b001..select MBC_MEMN_GLBAC1 access control policy for block B
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* 0b010..select MBC_MEMN_GLBAC2 access control policy for block B
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* 0b011..select MBC_MEMN_GLBAC3 access control policy for block B
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* 0b100..select MBC_MEMN_GLBAC4 access control policy for block B
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* 0b101..select MBC_MEMN_GLBAC5 access control policy for block B
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* 0b110..select MBC_MEMN_GLBAC6 access control policy for block B
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* 0b111..select MBC_MEMN_GLBAC7 access control policy for block B
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL0_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE0_MASK (0x8U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE0_SHIFT (3U)
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/*! NSE0 - NonSecure Enable for block B
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE0_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL1_MASK (0x70U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL1_SHIFT (4U)
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/*! MBACSEL1 - Memory Block Access Control Select for block B
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* 0b000..select MBC_MEMN_GLBAC0 access control policy for block B
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* 0b001..select MBC_MEMN_GLBAC1 access control policy for block B
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* 0b010..select MBC_MEMN_GLBAC2 access control policy for block B
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* 0b011..select MBC_MEMN_GLBAC3 access control policy for block B
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* 0b100..select MBC_MEMN_GLBAC4 access control policy for block B
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* 0b101..select MBC_MEMN_GLBAC5 access control policy for block B
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* 0b110..select MBC_MEMN_GLBAC6 access control policy for block B
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* 0b111..select MBC_MEMN_GLBAC7 access control policy for block B
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL1_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE1_MASK (0x80U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE1_SHIFT (7U)
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/*! NSE1 - NonSecure Enable for block B
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE1_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL2_MASK (0x700U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL2_SHIFT (8U)
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/*! MBACSEL2 - Memory Block Access Control Select for block B
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* 0b000..select MBC_MEMN_GLBAC0 access control policy for block B
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* 0b001..select MBC_MEMN_GLBAC1 access control policy for block B
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* 0b010..select MBC_MEMN_GLBAC2 access control policy for block B
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* 0b011..select MBC_MEMN_GLBAC3 access control policy for block B
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* 0b100..select MBC_MEMN_GLBAC4 access control policy for block B
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* 0b101..select MBC_MEMN_GLBAC5 access control policy for block B
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* 0b110..select MBC_MEMN_GLBAC6 access control policy for block B
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* 0b111..select MBC_MEMN_GLBAC7 access control policy for block B
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL2_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE2_MASK (0x800U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE2_SHIFT (11U)
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/*! NSE2 - NonSecure Enable for block B
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE2_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL3_MASK (0x7000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL3_SHIFT (12U)
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/*! MBACSEL3 - Memory Block Access Control Select for block B
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* 0b000..select MBC_MEMN_GLBAC0 access control policy for block B
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* 0b001..select MBC_MEMN_GLBAC1 access control policy for block B
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* 0b010..select MBC_MEMN_GLBAC2 access control policy for block B
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* 0b011..select MBC_MEMN_GLBAC3 access control policy for block B
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* 0b100..select MBC_MEMN_GLBAC4 access control policy for block B
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* 0b101..select MBC_MEMN_GLBAC5 access control policy for block B
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* 0b110..select MBC_MEMN_GLBAC6 access control policy for block B
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* 0b111..select MBC_MEMN_GLBAC7 access control policy for block B
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL3_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE3_MASK (0x8000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE3_SHIFT (15U)
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/*! NSE3 - NonSecure Enable for block B
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE3_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL4_MASK (0x70000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL4_SHIFT (16U)
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/*! MBACSEL4 - Memory Block Access Control Select for block B
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* 0b000..select MBC_MEMN_GLBAC0 access control policy for block B
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* 0b001..select MBC_MEMN_GLBAC1 access control policy for block B
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* 0b010..select MBC_MEMN_GLBAC2 access control policy for block B
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* 0b011..select MBC_MEMN_GLBAC3 access control policy for block B
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* 0b100..select MBC_MEMN_GLBAC4 access control policy for block B
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* 0b101..select MBC_MEMN_GLBAC5 access control policy for block B
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* 0b110..select MBC_MEMN_GLBAC6 access control policy for block B
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* 0b111..select MBC_MEMN_GLBAC7 access control policy for block B
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL4_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE4_MASK (0x80000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE4_SHIFT (19U)
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/*! NSE4 - NonSecure Enable for block B
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
|
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
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* MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE4_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL5_MASK (0x700000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL5_SHIFT (20U)
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/*! MBACSEL5 - Memory Block Access Control Select for block B
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* 0b000..select MBC_MEMN_GLBAC0 access control policy for block B
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* 0b001..select MBC_MEMN_GLBAC1 access control policy for block B
|
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* 0b010..select MBC_MEMN_GLBAC2 access control policy for block B
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* 0b011..select MBC_MEMN_GLBAC3 access control policy for block B
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* 0b100..select MBC_MEMN_GLBAC4 access control policy for block B
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* 0b101..select MBC_MEMN_GLBAC5 access control policy for block B
|
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* 0b110..select MBC_MEMN_GLBAC6 access control policy for block B
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* 0b111..select MBC_MEMN_GLBAC7 access control policy for block B
|
|
*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL5_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE5_MASK (0x800000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE5_SHIFT (23U)
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/*! NSE5 - NonSecure Enable for block B
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE5_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL6_MASK (0x7000000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL6_SHIFT (24U)
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/*! MBACSEL6 - Memory Block Access Control Select for block B
|
|
* 0b000..select MBC_MEMN_GLBAC0 access control policy for block B
|
|
* 0b001..select MBC_MEMN_GLBAC1 access control policy for block B
|
|
* 0b010..select MBC_MEMN_GLBAC2 access control policy for block B
|
|
* 0b011..select MBC_MEMN_GLBAC3 access control policy for block B
|
|
* 0b100..select MBC_MEMN_GLBAC4 access control policy for block B
|
|
* 0b101..select MBC_MEMN_GLBAC5 access control policy for block B
|
|
* 0b110..select MBC_MEMN_GLBAC6 access control policy for block B
|
|
* 0b111..select MBC_MEMN_GLBAC7 access control policy for block B
|
|
*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL6_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE6_MASK (0x8000000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE6_SHIFT (27U)
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/*! NSE6 - NonSecure Enable for block B
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE6_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL7_MASK (0x70000000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL7_SHIFT (28U)
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/*! MBACSEL7 - Memory Block Access Control Select for block B
|
|
* 0b000..select MBC_MEMN_GLBAC0 access control policy for block B
|
|
* 0b001..select MBC_MEMN_GLBAC1 access control policy for block B
|
|
* 0b010..select MBC_MEMN_GLBAC2 access control policy for block B
|
|
* 0b011..select MBC_MEMN_GLBAC3 access control policy for block B
|
|
* 0b100..select MBC_MEMN_GLBAC4 access control policy for block B
|
|
* 0b101..select MBC_MEMN_GLBAC5 access control policy for block B
|
|
* 0b110..select MBC_MEMN_GLBAC6 access control policy for block B
|
|
* 0b111..select MBC_MEMN_GLBAC7 access control policy for block B
|
|
*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL7_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE7_MASK (0x80000000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE7_SHIFT (31U)
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/*! NSE7 - NonSecure Enable for block B
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE7_MASK)
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/*! @} */
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/* The count of MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0 */
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_COUNT (1U)
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/*! @name MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0 - MBC Memory Block NonSecure Enable Word */
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/*! @{ */
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT0_MASK (0x1U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT0_SHIFT (0U)
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/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT0_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT1_MASK (0x2U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT1_SHIFT (1U)
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/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT1_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT2_MASK (0x4U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT2_SHIFT (2U)
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/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT2_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT3_MASK (0x8U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT3_SHIFT (3U)
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/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT3_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT4_MASK (0x10U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT4_SHIFT (4U)
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/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT4_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT5_MASK (0x20U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT5_SHIFT (5U)
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/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT5_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT6_MASK (0x40U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT6_SHIFT (6U)
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/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT6_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT7_MASK (0x80U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT7_SHIFT (7U)
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/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT7_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT8_MASK (0x100U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT8_SHIFT (8U)
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/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT8(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT8_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT8_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT9_MASK (0x200U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT9_SHIFT (9U)
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/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT9(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT9_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT9_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT10_MASK (0x400U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT10_SHIFT (10U)
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/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT10(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT10_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT10_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT11_MASK (0x800U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT11_SHIFT (11U)
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/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT11(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT11_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT11_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT12_MASK (0x1000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT12_SHIFT (12U)
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/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT12(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT12_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT12_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT13_MASK (0x2000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT13_SHIFT (13U)
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/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
|
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT13(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT13_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT13_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT14_MASK (0x4000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT14_SHIFT (14U)
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/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT14(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT14_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT14_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT15_MASK (0x8000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT15_SHIFT (15U)
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/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT15(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT15_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT15_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT16_MASK (0x10000U)
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|
#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT16_SHIFT (16U)
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|
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
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|
#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT16(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT16_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT16_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT17_MASK (0x20000U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT17_SHIFT (17U)
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|
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
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|
#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT17(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT17_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT17_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT18_MASK (0x40000U)
|
|
#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT18_SHIFT (18U)
|
|
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
|
|
*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT18(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT18_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT18_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT19_MASK (0x80000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT19_SHIFT (19U)
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/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT19(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT19_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT19_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT20_MASK (0x100000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT20_SHIFT (20U)
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/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT20(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT20_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT20_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT21_MASK (0x200000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT21_SHIFT (21U)
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/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT21(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT21_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT21_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT22_MASK (0x400000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT22_SHIFT (22U)
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/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT22(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT22_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT22_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT23_MASK (0x800000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT23_SHIFT (23U)
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/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
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|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT23(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT23_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT23_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT24_MASK (0x1000000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT24_SHIFT (24U)
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/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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|
*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT24(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT24_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT24_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT25_MASK (0x2000000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT25_SHIFT (25U)
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/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
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|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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|
*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT25(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT25_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT25_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT26_MASK (0x4000000U)
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|
#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT26_SHIFT (26U)
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/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
|
|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
|
|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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|
*/
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|
#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT26(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT26_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT26_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT27_MASK (0x8000000U)
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|
#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT27_SHIFT (27U)
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|
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
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|
* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
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|
* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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|
* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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|
*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT27(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT27_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT27_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT28_MASK (0x10000000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT28_SHIFT (28U)
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/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT28(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT28_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT28_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT29_MASK (0x20000000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT29_SHIFT (29U)
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/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT29(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT29_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT29_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT30_MASK (0x40000000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT30_SHIFT (30U)
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/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
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* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT30(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT30_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT30_MASK)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT31_MASK (0x80000000U)
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT31_SHIFT (31U)
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/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
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* 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
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* (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
|
|
* 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
|
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* MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
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*/
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT31(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT31_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT31_MASK)
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/*! @} */
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/* The count of MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0 */
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#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_COUNT (1U)
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/*!
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* @}
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*/ /* end of group MBC_Register_Masks */
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/* MBC - Peripheral instance base addresses */
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/** Peripheral MBC0 base address */
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#define MBC0_BASE (0x4008E000u)
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/** Peripheral MBC0 base pointer */
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#define MBC0 ((MBC_Type *)MBC0_BASE)
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/** Array initializer of MBC peripheral base addresses */
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#define MBC_BASE_ADDRS { MBC0_BASE }
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/** Array initializer of MBC peripheral base pointers */
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#define MBC_BASE_PTRS { MBC0 }
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/*!
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* @}
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*/ /* end of group MBC_Peripheral_Access_Layer */
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/* ----------------------------------------------------------------------------
|
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-- MRCC Peripheral Access Layer
|
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---------------------------------------------------------------------------- */
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/*!
|
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* @addtogroup MRCC_Peripheral_Access_Layer MRCC Peripheral Access Layer
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* @{
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*/
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|
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/** MRCC - Register Layout Typedef */
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typedef struct {
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__IO uint32_t MRCC_GLB_RST0; /**< Peripheral Reset Control 0, offset: 0x0 */
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__O uint32_t MRCC_GLB_RST0_SET; /**< Peripheral Reset Control Set 0, offset: 0x4 */
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__O uint32_t MRCC_GLB_RST0_CLR; /**< Peripheral Reset Control Clear 0, offset: 0x8 */
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uint8_t RESERVED_0[4];
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__IO uint32_t MRCC_GLB_RST1; /**< Peripheral Reset Control 1, offset: 0x10 */
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__O uint32_t MRCC_GLB_RST1_SET; /**< Peripheral Reset Control Set 1, offset: 0x14 */
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__O uint32_t MRCC_GLB_RST1_CLR; /**< Peripheral Reset Control Clear 1, offset: 0x18 */
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uint8_t RESERVED_1[36];
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__IO uint32_t MRCC_GLB_CC0; /**< AHB Clock Control 0, offset: 0x40 */
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__O uint32_t MRCC_GLB_CC0_SET; /**< AHB Clock Control Set 0, offset: 0x44 */
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__O uint32_t MRCC_GLB_CC0_CLR; /**< AHB Clock Control Clear 0, offset: 0x48 */
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uint8_t RESERVED_2[4];
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__IO uint32_t MRCC_GLB_CC1; /**< AHB Clock Control 1, offset: 0x50 */
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__O uint32_t MRCC_GLB_CC1_SET; /**< AHB Clock Control Set 1, offset: 0x54 */
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__O uint32_t MRCC_GLB_CC1_CLR; /**< AHB Clock Control Clear 1, offset: 0x58 */
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uint8_t RESERVED_3[36];
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__IO uint32_t MRCC_GLB_ACC0; /**< Control Automatic Clock Gating 0, offset: 0x80 */
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__IO uint32_t MRCC_GLB_ACC1; /**< Control Automatic Clock Gating 1, offset: 0x84 */
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uint8_t RESERVED_4[24];
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__IO uint32_t MRCC_I3C0_FCLK_CLKSEL; /**< I3C0_FCLK clock selection control, offset: 0xA0 */
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__IO uint32_t MRCC_I3C0_FCLK_CLKDIV; /**< I3C0_FCLK clock divider control, offset: 0xA4 */
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__IO uint32_t MRCC_CTIMER0_CLKSEL; /**< CTIMER0 clock selection control, offset: 0xA8 */
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__IO uint32_t MRCC_CTIMER0_CLKDIV; /**< CTIMER0 clock divider control, offset: 0xAC */
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__IO uint32_t MRCC_CTIMER1_CLKSEL; /**< CTIMER1 clock selection control, offset: 0xB0 */
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__IO uint32_t MRCC_CTIMER1_CLKDIV; /**< CTIMER1 clock divider control, offset: 0xB4 */
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__IO uint32_t MRCC_CTIMER2_CLKSEL; /**< CTIMER2 clock selection control, offset: 0xB8 */
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__IO uint32_t MRCC_CTIMER2_CLKDIV; /**< CTIMER2 clock divider control, offset: 0xBC */
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uint8_t RESERVED_5[4];
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__IO uint32_t MRCC_WWDT0_CLKDIV; /**< WWDT0 clock divider control, offset: 0xC4 */
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__IO uint32_t MRCC_LPI2C0_CLKSEL; /**< LPI2C0 clock selection control, offset: 0xC8 */
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__IO uint32_t MRCC_LPI2C0_CLKDIV; /**< LPI2C0 clock divider control, offset: 0xCC */
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__IO uint32_t MRCC_LPSPI0_CLKSEL; /**< LPSPI0 clock selection control, offset: 0xD0 */
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__IO uint32_t MRCC_LPSPI0_CLKDIV; /**< LPSPI0 clock divider control, offset: 0xD4 */
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__IO uint32_t MRCC_LPSPI1_CLKSEL; /**< LPSPI1 clock selection control, offset: 0xD8 */
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|
__IO uint32_t MRCC_LPSPI1_CLKDIV; /**< LPSPI1 clock divider control, offset: 0xDC */
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__IO uint32_t MRCC_LPUART0_CLKSEL; /**< LPUART0 clock selection control, offset: 0xE0 */
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|
__IO uint32_t MRCC_LPUART0_CLKDIV; /**< LPUART0 clock divider control, offset: 0xE4 */
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__IO uint32_t MRCC_LPUART1_CLKSEL; /**< LPUART1 clock selection control, offset: 0xE8 */
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__IO uint32_t MRCC_LPUART1_CLKDIV; /**< LPUART1 clock divider control, offset: 0xEC */
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|
__IO uint32_t MRCC_LPUART2_CLKSEL; /**< LPUART2 clock selection control, offset: 0xF0 */
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|
__IO uint32_t MRCC_LPUART2_CLKDIV; /**< LPUART2 clock divider control, offset: 0xF4 */
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|
__IO uint32_t MRCC_USB0_CLKSEL; /**< USB0 clock selection control, offset: 0xF8 */
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|
uint8_t RESERVED_6[4];
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|
__IO uint32_t MRCC_LPTMR0_CLKSEL; /**< LPTMR0 clock selection control, offset: 0x100 */
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|
__IO uint32_t MRCC_LPTMR0_CLKDIV; /**< LPTMR0 clock divider control, offset: 0x104 */
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|
__IO uint32_t MRCC_OSTIMER0_CLKSEL; /**< OSTIMER0 clock selection control, offset: 0x108 */
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|
uint8_t RESERVED_7[4];
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|
__IO uint32_t MRCC_ADC0_CLKSEL; /**< ADC0 clock selection control, offset: 0x110 */
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|
__IO uint32_t MRCC_ADC0_CLKDIV; /**< ADC0 clock divider control, offset: 0x114 */
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|
uint8_t RESERVED_8[4];
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|
__IO uint32_t MRCC_CMP0_FUNC_CLKDIV; /**< CMP0_FUNC clock divider control, offset: 0x11C */
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|
__IO uint32_t MRCC_CMP0_RR_CLKSEL; /**< CMP0_RR clock selection control, offset: 0x120 */
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|
__IO uint32_t MRCC_CMP0_RR_CLKDIV; /**< CMP0_RR clock divider control, offset: 0x124 */
|
|
uint8_t RESERVED_9[4];
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|
__IO uint32_t MRCC_CMP1_FUNC_CLKDIV; /**< CMP1_FUNC clock divider control, offset: 0x12C */
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|
__IO uint32_t MRCC_CMP1_RR_CLKSEL; /**< CMP1_RR clock selection control, offset: 0x130 */
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|
__IO uint32_t MRCC_CMP1_RR_CLKDIV; /**< CMP1_RR clock divider control, offset: 0x134 */
|
|
__IO uint32_t MRCC_DBG_TRACE_CLKSEL; /**< DBG_TRACE clock selection control, offset: 0x138 */
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|
__IO uint32_t MRCC_DBG_TRACE_CLKDIV; /**< DBG_TRACE clock divider control, offset: 0x13C */
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|
__IO uint32_t MRCC_CLKOUT_CLKSEL; /**< CLKOUT clock selection control, offset: 0x140 */
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|
__IO uint32_t MRCC_CLKOUT_CLKDIV; /**< CLKOUT clock divider control, offset: 0x144 */
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|
__IO uint32_t MRCC_SYSTICK_CLKSEL; /**< SYSTICK clock selection control, offset: 0x148 */
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__IO uint32_t MRCC_SYSTICK_CLKDIV; /**< SYSTICK clock divider control, offset: 0x14C */
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uint8_t RESERVED_10[4];
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__IO uint32_t MRCC_FRO_HF_DIV_CLKDIV; /**< FRO_HF_DIV clock divider control, offset: 0x154 */
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} MRCC_Type;
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/* ----------------------------------------------------------------------------
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-- MRCC Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup MRCC_Register_Masks MRCC Register Masks
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* @{
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*/
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/*! @name MRCC_GLB_RST0 - Peripheral Reset Control 0 */
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/*! @{ */
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#define MRCC_MRCC_GLB_RST0_INPUTMUX0_MASK (0x1U)
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#define MRCC_MRCC_GLB_RST0_INPUTMUX0_SHIFT (0U)
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/*! INPUTMUX0 - Write to INPUTMUX0
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* 0b0..Peripheral is held in reset
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* 0b1..Peripheral is released from reset
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*/
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#define MRCC_MRCC_GLB_RST0_INPUTMUX0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_INPUTMUX0_SHIFT)) & MRCC_MRCC_GLB_RST0_INPUTMUX0_MASK)
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#define MRCC_MRCC_GLB_RST0_I3C0_MASK (0x2U)
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#define MRCC_MRCC_GLB_RST0_I3C0_SHIFT (1U)
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/*! I3C0 - Write to I3C0
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* 0b0..Peripheral is held in reset
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* 0b1..Peripheral is released from reset
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*/
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#define MRCC_MRCC_GLB_RST0_I3C0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_I3C0_SHIFT)) & MRCC_MRCC_GLB_RST0_I3C0_MASK)
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#define MRCC_MRCC_GLB_RST0_CTIMER0_MASK (0x4U)
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#define MRCC_MRCC_GLB_RST0_CTIMER0_SHIFT (2U)
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/*! CTIMER0 - Write to CTIMER0
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* 0b0..Peripheral is held in reset
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* 0b1..Peripheral is released from reset
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*/
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#define MRCC_MRCC_GLB_RST0_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_CTIMER0_SHIFT)) & MRCC_MRCC_GLB_RST0_CTIMER0_MASK)
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#define MRCC_MRCC_GLB_RST0_CTIMER1_MASK (0x8U)
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#define MRCC_MRCC_GLB_RST0_CTIMER1_SHIFT (3U)
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/*! CTIMER1 - Write to CTIMER1
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* 0b0..Peripheral is held in reset
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* 0b1..Peripheral is released from reset
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*/
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#define MRCC_MRCC_GLB_RST0_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_CTIMER1_SHIFT)) & MRCC_MRCC_GLB_RST0_CTIMER1_MASK)
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#define MRCC_MRCC_GLB_RST0_CTIMER2_MASK (0x10U)
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#define MRCC_MRCC_GLB_RST0_CTIMER2_SHIFT (4U)
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/*! CTIMER2 - Write to CTIMER2
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* 0b0..Peripheral is held in reset
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* 0b1..Peripheral is released from reset
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*/
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#define MRCC_MRCC_GLB_RST0_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_CTIMER2_SHIFT)) & MRCC_MRCC_GLB_RST0_CTIMER2_MASK)
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#define MRCC_MRCC_GLB_RST0_FREQME_MASK (0x20U)
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#define MRCC_MRCC_GLB_RST0_FREQME_SHIFT (5U)
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/*! FREQME - Write to FREQME
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* 0b0..Peripheral is held in reset
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* 0b1..Peripheral is released from reset
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*/
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#define MRCC_MRCC_GLB_RST0_FREQME(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_FREQME_SHIFT)) & MRCC_MRCC_GLB_RST0_FREQME_MASK)
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#define MRCC_MRCC_GLB_RST0_UTICK0_MASK (0x40U)
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#define MRCC_MRCC_GLB_RST0_UTICK0_SHIFT (6U)
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/*! UTICK0 - Write to UTICK0
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* 0b0..Peripheral is held in reset
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* 0b1..Peripheral is released from reset
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*/
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#define MRCC_MRCC_GLB_RST0_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_UTICK0_SHIFT)) & MRCC_MRCC_GLB_RST0_UTICK0_MASK)
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#define MRCC_MRCC_GLB_RST0_DMA_MASK (0x100U)
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#define MRCC_MRCC_GLB_RST0_DMA_SHIFT (8U)
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/*! DMA - Write to DMA
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* 0b0..Peripheral is held in reset
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* 0b1..Peripheral is released from reset
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*/
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#define MRCC_MRCC_GLB_RST0_DMA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_DMA_SHIFT)) & MRCC_MRCC_GLB_RST0_DMA_MASK)
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#define MRCC_MRCC_GLB_RST0_AOI0_MASK (0x200U)
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#define MRCC_MRCC_GLB_RST0_AOI0_SHIFT (9U)
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/*! AOI0 - Write to AOI0
|
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* 0b0..Peripheral is held in reset
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* 0b1..Peripheral is released from reset
|
|
*/
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#define MRCC_MRCC_GLB_RST0_AOI0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_AOI0_SHIFT)) & MRCC_MRCC_GLB_RST0_AOI0_MASK)
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#define MRCC_MRCC_GLB_RST0_CRC_MASK (0x400U)
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#define MRCC_MRCC_GLB_RST0_CRC_SHIFT (10U)
|
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/*! CRC - Write to CRC
|
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* 0b0..Peripheral is held in reset
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* 0b1..Peripheral is released from reset
|
|
*/
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#define MRCC_MRCC_GLB_RST0_CRC(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_CRC_SHIFT)) & MRCC_MRCC_GLB_RST0_CRC_MASK)
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#define MRCC_MRCC_GLB_RST0_EIM_MASK (0x800U)
|
|
#define MRCC_MRCC_GLB_RST0_EIM_SHIFT (11U)
|
|
/*! EIM - Write to EIM
|
|
* 0b0..Peripheral is held in reset
|
|
* 0b1..Peripheral is released from reset
|
|
*/
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#define MRCC_MRCC_GLB_RST0_EIM(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_EIM_SHIFT)) & MRCC_MRCC_GLB_RST0_EIM_MASK)
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#define MRCC_MRCC_GLB_RST0_ERM_MASK (0x1000U)
|
|
#define MRCC_MRCC_GLB_RST0_ERM_SHIFT (12U)
|
|
/*! ERM - Write to ERM
|
|
* 0b0..Peripheral is held in reset
|
|
* 0b1..Peripheral is released from reset
|
|
*/
|
|
#define MRCC_MRCC_GLB_RST0_ERM(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_ERM_SHIFT)) & MRCC_MRCC_GLB_RST0_ERM_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_RST0_LPI2C0_MASK (0x10000U)
|
|
#define MRCC_MRCC_GLB_RST0_LPI2C0_SHIFT (16U)
|
|
/*! LPI2C0 - Write to LPI2C0
|
|
* 0b0..Peripheral is held in reset
|
|
* 0b1..Peripheral is released from reset
|
|
*/
|
|
#define MRCC_MRCC_GLB_RST0_LPI2C0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPI2C0_SHIFT)) & MRCC_MRCC_GLB_RST0_LPI2C0_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_RST0_LPSPI0_MASK (0x20000U)
|
|
#define MRCC_MRCC_GLB_RST0_LPSPI0_SHIFT (17U)
|
|
/*! LPSPI0 - Write to LPSPI0
|
|
* 0b0..Peripheral is held in reset
|
|
* 0b1..Peripheral is released from reset
|
|
*/
|
|
#define MRCC_MRCC_GLB_RST0_LPSPI0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPSPI0_SHIFT)) & MRCC_MRCC_GLB_RST0_LPSPI0_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_RST0_LPSPI1_MASK (0x40000U)
|
|
#define MRCC_MRCC_GLB_RST0_LPSPI1_SHIFT (18U)
|
|
/*! LPSPI1 - Write to LPSPI1
|
|
* 0b0..Peripheral is held in reset
|
|
* 0b1..Peripheral is released from reset
|
|
*/
|
|
#define MRCC_MRCC_GLB_RST0_LPSPI1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPSPI1_SHIFT)) & MRCC_MRCC_GLB_RST0_LPSPI1_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_RST0_LPUART0_MASK (0x80000U)
|
|
#define MRCC_MRCC_GLB_RST0_LPUART0_SHIFT (19U)
|
|
/*! LPUART0 - Write to LPUART0
|
|
* 0b0..Peripheral is held in reset
|
|
* 0b1..Peripheral is released from reset
|
|
*/
|
|
#define MRCC_MRCC_GLB_RST0_LPUART0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPUART0_SHIFT)) & MRCC_MRCC_GLB_RST0_LPUART0_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_RST0_LPUART1_MASK (0x100000U)
|
|
#define MRCC_MRCC_GLB_RST0_LPUART1_SHIFT (20U)
|
|
/*! LPUART1 - Write to LPUART1
|
|
* 0b0..Peripheral is held in reset
|
|
* 0b1..Peripheral is released from reset
|
|
*/
|
|
#define MRCC_MRCC_GLB_RST0_LPUART1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPUART1_SHIFT)) & MRCC_MRCC_GLB_RST0_LPUART1_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_RST0_LPUART2_MASK (0x200000U)
|
|
#define MRCC_MRCC_GLB_RST0_LPUART2_SHIFT (21U)
|
|
/*! LPUART2 - Write to LPUART2
|
|
* 0b0..Peripheral is held in reset
|
|
* 0b1..Peripheral is released from reset
|
|
*/
|
|
#define MRCC_MRCC_GLB_RST0_LPUART2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPUART2_SHIFT)) & MRCC_MRCC_GLB_RST0_LPUART2_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_RST0_USB0_MASK (0x400000U)
|
|
#define MRCC_MRCC_GLB_RST0_USB0_SHIFT (22U)
|
|
/*! USB0 - Write to USB0
|
|
* 0b0..Peripheral is held in reset
|
|
* 0b1..Peripheral is released from reset
|
|
*/
|
|
#define MRCC_MRCC_GLB_RST0_USB0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_USB0_SHIFT)) & MRCC_MRCC_GLB_RST0_USB0_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_RST0_QDC0_MASK (0x800000U)
|
|
#define MRCC_MRCC_GLB_RST0_QDC0_SHIFT (23U)
|
|
/*! QDC0 - Write to QDC0
|
|
* 0b0..Peripheral is held in reset
|
|
* 0b1..Peripheral is released from reset
|
|
*/
|
|
#define MRCC_MRCC_GLB_RST0_QDC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_QDC0_SHIFT)) & MRCC_MRCC_GLB_RST0_QDC0_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_RST0_FLEXPWM0_MASK (0x1000000U)
|
|
#define MRCC_MRCC_GLB_RST0_FLEXPWM0_SHIFT (24U)
|
|
/*! FLEXPWM0 - Write to FLEXPWM0
|
|
* 0b0..Peripheral is held in reset
|
|
* 0b1..Peripheral is released from reset
|
|
*/
|
|
#define MRCC_MRCC_GLB_RST0_FLEXPWM0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_FLEXPWM0_SHIFT)) & MRCC_MRCC_GLB_RST0_FLEXPWM0_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_RST0_OSTIMER0_MASK (0x2000000U)
|
|
#define MRCC_MRCC_GLB_RST0_OSTIMER0_SHIFT (25U)
|
|
/*! OSTIMER0 - Write to OSTIMER0
|
|
* 0b0..Peripheral is held in reset
|
|
* 0b1..Peripheral is released from reset
|
|
*/
|
|
#define MRCC_MRCC_GLB_RST0_OSTIMER0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_OSTIMER0_SHIFT)) & MRCC_MRCC_GLB_RST0_OSTIMER0_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_RST0_ADC0_MASK (0x4000000U)
|
|
#define MRCC_MRCC_GLB_RST0_ADC0_SHIFT (26U)
|
|
/*! ADC0 - Write to ADC0
|
|
* 0b0..Peripheral is held in reset
|
|
* 0b1..Peripheral is released from reset
|
|
*/
|
|
#define MRCC_MRCC_GLB_RST0_ADC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_ADC0_SHIFT)) & MRCC_MRCC_GLB_RST0_ADC0_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_RST0_CMP1_MASK (0x10000000U)
|
|
#define MRCC_MRCC_GLB_RST0_CMP1_SHIFT (28U)
|
|
/*! CMP1 - Write to CMP1
|
|
* 0b0..Peripheral is held in reset
|
|
* 0b1..Peripheral is released from reset
|
|
*/
|
|
#define MRCC_MRCC_GLB_RST0_CMP1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_CMP1_SHIFT)) & MRCC_MRCC_GLB_RST0_CMP1_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_RST0_PORT0_MASK (0x20000000U)
|
|
#define MRCC_MRCC_GLB_RST0_PORT0_SHIFT (29U)
|
|
/*! PORT0 - Write to PORT0
|
|
* 0b0..Peripheral is held in reset
|
|
* 0b1..Peripheral is released from reset
|
|
*/
|
|
#define MRCC_MRCC_GLB_RST0_PORT0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_PORT0_SHIFT)) & MRCC_MRCC_GLB_RST0_PORT0_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_RST0_PORT1_MASK (0x40000000U)
|
|
#define MRCC_MRCC_GLB_RST0_PORT1_SHIFT (30U)
|
|
/*! PORT1 - Write to PORT1
|
|
* 0b0..Peripheral is held in reset
|
|
* 0b1..Peripheral is released from reset
|
|
*/
|
|
#define MRCC_MRCC_GLB_RST0_PORT1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_PORT1_SHIFT)) & MRCC_MRCC_GLB_RST0_PORT1_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_RST0_PORT2_MASK (0x80000000U)
|
|
#define MRCC_MRCC_GLB_RST0_PORT2_SHIFT (31U)
|
|
/*! PORT2 - Write to PORT2
|
|
* 0b0..Peripheral is held in reset
|
|
* 0b1..Peripheral is released from reset
|
|
*/
|
|
#define MRCC_MRCC_GLB_RST0_PORT2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_PORT2_SHIFT)) & MRCC_MRCC_GLB_RST0_PORT2_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MRCC_GLB_RST0_SET - Peripheral Reset Control Set 0 */
|
|
/*! @{ */
|
|
|
|
#define MRCC_MRCC_GLB_RST0_SET_DATA_MASK (0xFFFFFFFFU)
|
|
#define MRCC_MRCC_GLB_RST0_SET_DATA_SHIFT (0U)
|
|
/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_RSTn. */
|
|
#define MRCC_MRCC_GLB_RST0_SET_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_SET_DATA_SHIFT)) & MRCC_MRCC_GLB_RST0_SET_DATA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MRCC_GLB_RST0_CLR - Peripheral Reset Control Clear 0 */
|
|
/*! @{ */
|
|
|
|
#define MRCC_MRCC_GLB_RST0_CLR_DATA_MASK (0xFFFFFFFFU)
|
|
#define MRCC_MRCC_GLB_RST0_CLR_DATA_SHIFT (0U)
|
|
/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_RSTn. */
|
|
#define MRCC_MRCC_GLB_RST0_CLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_CLR_DATA_SHIFT)) & MRCC_MRCC_GLB_RST0_CLR_DATA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MRCC_GLB_RST1 - Peripheral Reset Control 1 */
|
|
/*! @{ */
|
|
|
|
#define MRCC_MRCC_GLB_RST1_PORT3_MASK (0x1U)
|
|
#define MRCC_MRCC_GLB_RST1_PORT3_SHIFT (0U)
|
|
/*! PORT3 - Write to PORT3
|
|
* 0b0..Peripheral is held in reset
|
|
* 0b1..Peripheral is released from reset
|
|
*/
|
|
#define MRCC_MRCC_GLB_RST1_PORT3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_PORT3_SHIFT)) & MRCC_MRCC_GLB_RST1_PORT3_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_RST1_GPIO0_MASK (0x20U)
|
|
#define MRCC_MRCC_GLB_RST1_GPIO0_SHIFT (5U)
|
|
/*! GPIO0 - Write to GPIO0
|
|
* 0b0..Peripheral is held in reset
|
|
* 0b1..Peripheral is released from reset
|
|
*/
|
|
#define MRCC_MRCC_GLB_RST1_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_GPIO0_SHIFT)) & MRCC_MRCC_GLB_RST1_GPIO0_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_RST1_GPIO1_MASK (0x40U)
|
|
#define MRCC_MRCC_GLB_RST1_GPIO1_SHIFT (6U)
|
|
/*! GPIO1 - Write to GPIO1
|
|
* 0b0..Peripheral is held in reset
|
|
* 0b1..Peripheral is released from reset
|
|
*/
|
|
#define MRCC_MRCC_GLB_RST1_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_GPIO1_SHIFT)) & MRCC_MRCC_GLB_RST1_GPIO1_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_RST1_GPIO2_MASK (0x80U)
|
|
#define MRCC_MRCC_GLB_RST1_GPIO2_SHIFT (7U)
|
|
/*! GPIO2 - Write to GPIO2
|
|
* 0b0..Peripheral is held in reset
|
|
* 0b1..Peripheral is released from reset
|
|
*/
|
|
#define MRCC_MRCC_GLB_RST1_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_GPIO2_SHIFT)) & MRCC_MRCC_GLB_RST1_GPIO2_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_RST1_GPIO3_MASK (0x100U)
|
|
#define MRCC_MRCC_GLB_RST1_GPIO3_SHIFT (8U)
|
|
/*! GPIO3 - Write to GPIO3
|
|
* 0b0..Peripheral is held in reset
|
|
* 0b1..Peripheral is released from reset
|
|
*/
|
|
#define MRCC_MRCC_GLB_RST1_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_GPIO3_SHIFT)) & MRCC_MRCC_GLB_RST1_GPIO3_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MRCC_GLB_RST1_SET - Peripheral Reset Control Set 1 */
|
|
/*! @{ */
|
|
|
|
#define MRCC_MRCC_GLB_RST1_SET_DATA_MASK (0xFFFFFFFFU)
|
|
#define MRCC_MRCC_GLB_RST1_SET_DATA_SHIFT (0U)
|
|
/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_RSTn. */
|
|
#define MRCC_MRCC_GLB_RST1_SET_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_SET_DATA_SHIFT)) & MRCC_MRCC_GLB_RST1_SET_DATA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MRCC_GLB_RST1_CLR - Peripheral Reset Control Clear 1 */
|
|
/*! @{ */
|
|
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#define MRCC_MRCC_GLB_RST1_CLR_DATA_MASK (0xFFFFFFFFU)
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#define MRCC_MRCC_GLB_RST1_CLR_DATA_SHIFT (0U)
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/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_RSTn. */
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#define MRCC_MRCC_GLB_RST1_CLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_CLR_DATA_SHIFT)) & MRCC_MRCC_GLB_RST1_CLR_DATA_MASK)
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/*! @} */
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/*! @name MRCC_GLB_CC0 - AHB Clock Control 0 */
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/*! @{ */
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#define MRCC_MRCC_GLB_CC0_INPUTMUX0_MASK (0x1U)
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#define MRCC_MRCC_GLB_CC0_INPUTMUX0_SHIFT (0U)
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/*! INPUTMUX0 - write to INPUTMUX0
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* 0b0..Peripheral clock is disabled
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* 0b1..Peripheral clock is enabled
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*/
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#define MRCC_MRCC_GLB_CC0_INPUTMUX0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_INPUTMUX0_SHIFT)) & MRCC_MRCC_GLB_CC0_INPUTMUX0_MASK)
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#define MRCC_MRCC_GLB_CC0_I3C0_MASK (0x2U)
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#define MRCC_MRCC_GLB_CC0_I3C0_SHIFT (1U)
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/*! I3C0 - Write to I3C0
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* 0b0..Peripheral clock is disabled
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* 0b1..Peripheral clock is enabled
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*/
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#define MRCC_MRCC_GLB_CC0_I3C0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_I3C0_SHIFT)) & MRCC_MRCC_GLB_CC0_I3C0_MASK)
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#define MRCC_MRCC_GLB_CC0_CTIMER0_MASK (0x4U)
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#define MRCC_MRCC_GLB_CC0_CTIMER0_SHIFT (2U)
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/*! CTIMER0 - Write to CTIMER0
|
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* 0b0..Peripheral clock is disabled
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* 0b1..Peripheral clock is enabled
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*/
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#define MRCC_MRCC_GLB_CC0_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_CTIMER0_SHIFT)) & MRCC_MRCC_GLB_CC0_CTIMER0_MASK)
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#define MRCC_MRCC_GLB_CC0_CTIMER1_MASK (0x8U)
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#define MRCC_MRCC_GLB_CC0_CTIMER1_SHIFT (3U)
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/*! CTIMER1 - Write to CTIMER1
|
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* 0b0..Peripheral clock is disabled
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* 0b1..Peripheral clock is enabled
|
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*/
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#define MRCC_MRCC_GLB_CC0_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_CTIMER1_SHIFT)) & MRCC_MRCC_GLB_CC0_CTIMER1_MASK)
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#define MRCC_MRCC_GLB_CC0_CTIMER2_MASK (0x10U)
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#define MRCC_MRCC_GLB_CC0_CTIMER2_SHIFT (4U)
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/*! CTIMER2 - Write to CTIMER2
|
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* 0b0..Peripheral clock is disabled
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* 0b1..Peripheral clock is enabled
|
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*/
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#define MRCC_MRCC_GLB_CC0_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_CTIMER2_SHIFT)) & MRCC_MRCC_GLB_CC0_CTIMER2_MASK)
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#define MRCC_MRCC_GLB_CC0_FREQME_MASK (0x20U)
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#define MRCC_MRCC_GLB_CC0_FREQME_SHIFT (5U)
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/*! FREQME - Write to FREQME
|
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* 0b0..Peripheral clock is disabled
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* 0b1..Peripheral clock is enabled
|
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*/
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#define MRCC_MRCC_GLB_CC0_FREQME(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_FREQME_SHIFT)) & MRCC_MRCC_GLB_CC0_FREQME_MASK)
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#define MRCC_MRCC_GLB_CC0_UTICK0_MASK (0x40U)
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#define MRCC_MRCC_GLB_CC0_UTICK0_SHIFT (6U)
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/*! UTICK0 - Write to UTICK0
|
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* 0b0..Peripheral clock is disabled
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* 0b1..Peripheral clock is enabled
|
|
*/
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#define MRCC_MRCC_GLB_CC0_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_UTICK0_SHIFT)) & MRCC_MRCC_GLB_CC0_UTICK0_MASK)
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#define MRCC_MRCC_GLB_CC0_WWDT0_MASK (0x80U)
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#define MRCC_MRCC_GLB_CC0_WWDT0_SHIFT (7U)
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/*! WWDT0 - Write to WWDT0
|
|
* 0b0..Peripheral clock is disabled
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|
* 0b1..Peripheral clock is enabled
|
|
*/
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#define MRCC_MRCC_GLB_CC0_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_WWDT0_SHIFT)) & MRCC_MRCC_GLB_CC0_WWDT0_MASK)
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#define MRCC_MRCC_GLB_CC0_DMA_MASK (0x100U)
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#define MRCC_MRCC_GLB_CC0_DMA_SHIFT (8U)
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/*! DMA - Write to DMA
|
|
* 0b0..Peripheral clock is disabled
|
|
* 0b1..Peripheral clock is enabled
|
|
*/
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|
#define MRCC_MRCC_GLB_CC0_DMA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_DMA_SHIFT)) & MRCC_MRCC_GLB_CC0_DMA_MASK)
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#define MRCC_MRCC_GLB_CC0_AOI0_MASK (0x200U)
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|
#define MRCC_MRCC_GLB_CC0_AOI0_SHIFT (9U)
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|
/*! AOI0 - Write to AOI0
|
|
* 0b0..Peripheral clock is disabled
|
|
* 0b1..Peripheral clock is enabled
|
|
*/
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|
#define MRCC_MRCC_GLB_CC0_AOI0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_AOI0_SHIFT)) & MRCC_MRCC_GLB_CC0_AOI0_MASK)
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#define MRCC_MRCC_GLB_CC0_CRC_MASK (0x400U)
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|
#define MRCC_MRCC_GLB_CC0_CRC_SHIFT (10U)
|
|
/*! CRC - Write to CRC
|
|
* 0b0..Peripheral clock is disabled
|
|
* 0b1..Peripheral clock is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_CC0_CRC(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_CRC_SHIFT)) & MRCC_MRCC_GLB_CC0_CRC_MASK)
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|
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#define MRCC_MRCC_GLB_CC0_EIM_MASK (0x800U)
|
|
#define MRCC_MRCC_GLB_CC0_EIM_SHIFT (11U)
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|
/*! EIM - Write to EIM
|
|
* 0b0..Peripheral clock is disabled
|
|
* 0b1..Peripheral clock is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_CC0_EIM(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_EIM_SHIFT)) & MRCC_MRCC_GLB_CC0_EIM_MASK)
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#define MRCC_MRCC_GLB_CC0_ERM_MASK (0x1000U)
|
|
#define MRCC_MRCC_GLB_CC0_ERM_SHIFT (12U)
|
|
/*! ERM - Write to ERM
|
|
* 0b0..Peripheral clock is disabled
|
|
* 0b1..Peripheral clock is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_CC0_ERM(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_ERM_SHIFT)) & MRCC_MRCC_GLB_CC0_ERM_MASK)
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|
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|
#define MRCC_MRCC_GLB_CC0_LPI2C0_MASK (0x10000U)
|
|
#define MRCC_MRCC_GLB_CC0_LPI2C0_SHIFT (16U)
|
|
/*! LPI2C0 - Write to LPI2C0
|
|
* 0b0..Peripheral clock is disabled
|
|
* 0b1..Peripheral clock is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_CC0_LPI2C0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPI2C0_SHIFT)) & MRCC_MRCC_GLB_CC0_LPI2C0_MASK)
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|
|
|
#define MRCC_MRCC_GLB_CC0_LPSPI0_MASK (0x20000U)
|
|
#define MRCC_MRCC_GLB_CC0_LPSPI0_SHIFT (17U)
|
|
/*! LPSPI0 - Write to LPSPI0
|
|
* 0b0..Peripheral clock is disabled
|
|
* 0b1..Peripheral clock is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_CC0_LPSPI0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPSPI0_SHIFT)) & MRCC_MRCC_GLB_CC0_LPSPI0_MASK)
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|
|
|
#define MRCC_MRCC_GLB_CC0_LPSPI1_MASK (0x40000U)
|
|
#define MRCC_MRCC_GLB_CC0_LPSPI1_SHIFT (18U)
|
|
/*! LPSPI1 - write to LPSPI1
|
|
* 0b0..Peripheral clock is disabled
|
|
* 0b1..Peripheral clock is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_CC0_LPSPI1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPSPI1_SHIFT)) & MRCC_MRCC_GLB_CC0_LPSPI1_MASK)
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|
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|
#define MRCC_MRCC_GLB_CC0_LPUART0_MASK (0x80000U)
|
|
#define MRCC_MRCC_GLB_CC0_LPUART0_SHIFT (19U)
|
|
/*! LPUART0 - Write to LPUART0
|
|
* 0b0..Peripheral clock is disabled
|
|
* 0b1..Peripheral clock is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_CC0_LPUART0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPUART0_SHIFT)) & MRCC_MRCC_GLB_CC0_LPUART0_MASK)
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|
|
|
#define MRCC_MRCC_GLB_CC0_LPUART1_MASK (0x100000U)
|
|
#define MRCC_MRCC_GLB_CC0_LPUART1_SHIFT (20U)
|
|
/*! LPUART1 - Write to LPUART1
|
|
* 0b0..Peripheral clock is disabled
|
|
* 0b1..Peripheral clock is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_CC0_LPUART1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPUART1_SHIFT)) & MRCC_MRCC_GLB_CC0_LPUART1_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_CC0_LPUART2_MASK (0x200000U)
|
|
#define MRCC_MRCC_GLB_CC0_LPUART2_SHIFT (21U)
|
|
/*! LPUART2 - Write to LPUART2
|
|
* 0b0..Peripheral clock is disabled
|
|
* 0b1..Peripheral clock is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_CC0_LPUART2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPUART2_SHIFT)) & MRCC_MRCC_GLB_CC0_LPUART2_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_CC0_USB0_MASK (0x400000U)
|
|
#define MRCC_MRCC_GLB_CC0_USB0_SHIFT (22U)
|
|
/*! USB0 - Write to USB0
|
|
* 0b0..Peripheral clock is disabled
|
|
* 0b1..Peripheral clock is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_CC0_USB0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_USB0_SHIFT)) & MRCC_MRCC_GLB_CC0_USB0_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_CC0_QDC0_MASK (0x800000U)
|
|
#define MRCC_MRCC_GLB_CC0_QDC0_SHIFT (23U)
|
|
/*! QDC0 - Write to QDC0
|
|
* 0b0..Peripheral clock is disabled
|
|
* 0b1..Peripheral clock is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_CC0_QDC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_QDC0_SHIFT)) & MRCC_MRCC_GLB_CC0_QDC0_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_CC0_FLEXPWM0_MASK (0x1000000U)
|
|
#define MRCC_MRCC_GLB_CC0_FLEXPWM0_SHIFT (24U)
|
|
/*! FLEXPWM0 - Write to FLEXPWM0
|
|
* 0b0..Peripheral clock is disabled
|
|
* 0b1..Peripheral clock is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_CC0_FLEXPWM0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_FLEXPWM0_SHIFT)) & MRCC_MRCC_GLB_CC0_FLEXPWM0_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_CC0_OSTIMER0_MASK (0x2000000U)
|
|
#define MRCC_MRCC_GLB_CC0_OSTIMER0_SHIFT (25U)
|
|
/*! OSTIMER0 - Write to OSTIMER0
|
|
* 0b0..Peripheral clock is disabled
|
|
* 0b1..Peripheral clock is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_CC0_OSTIMER0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_OSTIMER0_SHIFT)) & MRCC_MRCC_GLB_CC0_OSTIMER0_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_CC0_ADC0_MASK (0x4000000U)
|
|
#define MRCC_MRCC_GLB_CC0_ADC0_SHIFT (26U)
|
|
/*! ADC0 - Write to ADC0
|
|
* 0b0..Peripheral clock is disabled
|
|
* 0b1..Peripheral clock is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_CC0_ADC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_ADC0_SHIFT)) & MRCC_MRCC_GLB_CC0_ADC0_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_CC0_CMP0_MASK (0x8000000U)
|
|
#define MRCC_MRCC_GLB_CC0_CMP0_SHIFT (27U)
|
|
/*! CMP0 - Write to CMP0
|
|
* 0b0..Peripheral clock is disabled
|
|
* 0b1..Peripheral clock is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_CC0_CMP0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_CMP0_SHIFT)) & MRCC_MRCC_GLB_CC0_CMP0_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_CC0_CMP1_MASK (0x10000000U)
|
|
#define MRCC_MRCC_GLB_CC0_CMP1_SHIFT (28U)
|
|
/*! CMP1 - Write to CMP1
|
|
* 0b0..Peripheral clock is disabled
|
|
* 0b1..Peripheral clock is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_CC0_CMP1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_CMP1_SHIFT)) & MRCC_MRCC_GLB_CC0_CMP1_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_CC0_PORT0_MASK (0x20000000U)
|
|
#define MRCC_MRCC_GLB_CC0_PORT0_SHIFT (29U)
|
|
/*! PORT0 - Write to PORT0
|
|
* 0b0..Peripheral clock is disabled
|
|
* 0b1..Peripheral clock is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_CC0_PORT0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_PORT0_SHIFT)) & MRCC_MRCC_GLB_CC0_PORT0_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_CC0_PORT1_MASK (0x40000000U)
|
|
#define MRCC_MRCC_GLB_CC0_PORT1_SHIFT (30U)
|
|
/*! PORT1 - Write to PORT1
|
|
* 0b0..Peripheral clock is disabled
|
|
* 0b1..Peripheral clock is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_CC0_PORT1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_PORT1_SHIFT)) & MRCC_MRCC_GLB_CC0_PORT1_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_CC0_PORT2_MASK (0x80000000U)
|
|
#define MRCC_MRCC_GLB_CC0_PORT2_SHIFT (31U)
|
|
/*! PORT2 - Write to PORT2
|
|
* 0b0..Peripheral clock is disabled
|
|
* 0b1..Peripheral clock is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_CC0_PORT2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_PORT2_SHIFT)) & MRCC_MRCC_GLB_CC0_PORT2_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MRCC_GLB_CC0_SET - AHB Clock Control Set 0 */
|
|
/*! @{ */
|
|
|
|
#define MRCC_MRCC_GLB_CC0_SET_DATA_MASK (0xFFFFFFFFU)
|
|
#define MRCC_MRCC_GLB_CC0_SET_DATA_SHIFT (0U)
|
|
/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_CCn. */
|
|
#define MRCC_MRCC_GLB_CC0_SET_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_SET_DATA_SHIFT)) & MRCC_MRCC_GLB_CC0_SET_DATA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MRCC_GLB_CC0_CLR - AHB Clock Control Clear 0 */
|
|
/*! @{ */
|
|
|
|
#define MRCC_MRCC_GLB_CC0_CLR_DATA_MASK (0xFFFFFFFFU)
|
|
#define MRCC_MRCC_GLB_CC0_CLR_DATA_SHIFT (0U)
|
|
/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_CCn. */
|
|
#define MRCC_MRCC_GLB_CC0_CLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_CLR_DATA_SHIFT)) & MRCC_MRCC_GLB_CC0_CLR_DATA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MRCC_GLB_CC1 - AHB Clock Control 1 */
|
|
/*! @{ */
|
|
|
|
#define MRCC_MRCC_GLB_CC1_PORT3_MASK (0x1U)
|
|
#define MRCC_MRCC_GLB_CC1_PORT3_SHIFT (0U)
|
|
/*! PORT3 - Write to PORT3
|
|
* 0b0..Peripheral clock is disabled
|
|
* 0b1..Peripheral clock is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_CC1_PORT3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_PORT3_SHIFT)) & MRCC_MRCC_GLB_CC1_PORT3_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_CC1_MTR_MASK (0x4U)
|
|
#define MRCC_MRCC_GLB_CC1_MTR_SHIFT (2U)
|
|
/*! MTR - Write to MTR
|
|
* 0b0..Peripheral clock is disabled
|
|
* 0b1..Peripheral clock is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_CC1_MTR(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_MTR_SHIFT)) & MRCC_MRCC_GLB_CC1_MTR_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_CC1_TCU_MASK (0x8U)
|
|
#define MRCC_MRCC_GLB_CC1_TCU_SHIFT (3U)
|
|
/*! TCU - Write to TCU
|
|
* 0b0..Peripheral clock is disabled
|
|
* 0b1..Peripheral clock is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_CC1_TCU(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_TCU_SHIFT)) & MRCC_MRCC_GLB_CC1_TCU_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_CC1_EZRAMC_RAMA_MASK (0x10U)
|
|
#define MRCC_MRCC_GLB_CC1_EZRAMC_RAMA_SHIFT (4U)
|
|
/*! EZRAMC_RAMA - Write to EZRAMC_RAMA
|
|
* 0b0..Peripheral clock is disabled
|
|
* 0b1..Peripheral clock is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_CC1_EZRAMC_RAMA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_EZRAMC_RAMA_SHIFT)) & MRCC_MRCC_GLB_CC1_EZRAMC_RAMA_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_CC1_GPIO0_MASK (0x20U)
|
|
#define MRCC_MRCC_GLB_CC1_GPIO0_SHIFT (5U)
|
|
/*! GPIO0 - Write to GPIO0
|
|
* 0b0..Peripheral clock is disabled
|
|
* 0b1..Peripheral clock is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_CC1_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_GPIO0_SHIFT)) & MRCC_MRCC_GLB_CC1_GPIO0_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_CC1_GPIO1_MASK (0x40U)
|
|
#define MRCC_MRCC_GLB_CC1_GPIO1_SHIFT (6U)
|
|
/*! GPIO1 - Write to GPIO1
|
|
* 0b0..Peripheral clock is disabled
|
|
* 0b1..Peripheral clock is enabled
|
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*/
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#define MRCC_MRCC_GLB_CC1_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_GPIO1_SHIFT)) & MRCC_MRCC_GLB_CC1_GPIO1_MASK)
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#define MRCC_MRCC_GLB_CC1_GPIO2_MASK (0x80U)
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#define MRCC_MRCC_GLB_CC1_GPIO2_SHIFT (7U)
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/*! GPIO2 - Write to GPIO2
|
|
* 0b0..Peripheral clock is disabled
|
|
* 0b1..Peripheral clock is enabled
|
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*/
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#define MRCC_MRCC_GLB_CC1_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_GPIO2_SHIFT)) & MRCC_MRCC_GLB_CC1_GPIO2_MASK)
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#define MRCC_MRCC_GLB_CC1_GPIO3_MASK (0x100U)
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#define MRCC_MRCC_GLB_CC1_GPIO3_SHIFT (8U)
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/*! GPIO3 - Write to GPIO3
|
|
* 0b0..Peripheral clock is disabled
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* 0b1..Peripheral clock is enabled
|
|
*/
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#define MRCC_MRCC_GLB_CC1_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_GPIO3_SHIFT)) & MRCC_MRCC_GLB_CC1_GPIO3_MASK)
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#define MRCC_MRCC_GLB_CC1_ROMCP_MASK (0x200U)
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#define MRCC_MRCC_GLB_CC1_ROMCP_SHIFT (9U)
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/*! ROMCP - Write to ROMCP
|
|
* 0b0..Peripheral clock is disabled
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* 0b1..Peripheral clock is enabled
|
|
*/
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#define MRCC_MRCC_GLB_CC1_ROMCP(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_ROMCP_SHIFT)) & MRCC_MRCC_GLB_CC1_ROMCP_MASK)
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/*! @} */
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/*! @name MRCC_GLB_CC1_SET - AHB Clock Control Set 1 */
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/*! @{ */
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#define MRCC_MRCC_GLB_CC1_SET_DATA_MASK (0xFFFFFFFFU)
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#define MRCC_MRCC_GLB_CC1_SET_DATA_SHIFT (0U)
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/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_CCn. */
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#define MRCC_MRCC_GLB_CC1_SET_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_SET_DATA_SHIFT)) & MRCC_MRCC_GLB_CC1_SET_DATA_MASK)
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/*! @} */
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/*! @name MRCC_GLB_CC1_CLR - AHB Clock Control Clear 1 */
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/*! @{ */
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#define MRCC_MRCC_GLB_CC1_CLR_DATA_MASK (0xFFFFFFFFU)
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#define MRCC_MRCC_GLB_CC1_CLR_DATA_SHIFT (0U)
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/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_CCn. */
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#define MRCC_MRCC_GLB_CC1_CLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_CLR_DATA_SHIFT)) & MRCC_MRCC_GLB_CC1_CLR_DATA_MASK)
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/*! @} */
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/*! @name MRCC_GLB_ACC0 - Control Automatic Clock Gating 0 */
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/*! @{ */
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#define MRCC_MRCC_GLB_ACC0_INPUTMUX0_MASK (0x1U)
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#define MRCC_MRCC_GLB_ACC0_INPUTMUX0_SHIFT (0U)
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/*! INPUTMUX0 - Write to INPUTMUX0
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* 0b0..Automatic clock gating is disabled
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* 0b1..Automatic clock gating is enabled
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*/
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#define MRCC_MRCC_GLB_ACC0_INPUTMUX0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_INPUTMUX0_SHIFT)) & MRCC_MRCC_GLB_ACC0_INPUTMUX0_MASK)
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#define MRCC_MRCC_GLB_ACC0_I3C0_MASK (0x2U)
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#define MRCC_MRCC_GLB_ACC0_I3C0_SHIFT (1U)
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/*! I3C0 - Write to I3C0
|
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* 0b0..Automatic clock gating is disabled
|
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* 0b1..Automatic clock gating is enabled
|
|
*/
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#define MRCC_MRCC_GLB_ACC0_I3C0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_I3C0_SHIFT)) & MRCC_MRCC_GLB_ACC0_I3C0_MASK)
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#define MRCC_MRCC_GLB_ACC0_CTIMER0_MASK (0x4U)
|
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#define MRCC_MRCC_GLB_ACC0_CTIMER0_SHIFT (2U)
|
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/*! CTIMER0 - Write to CTIMER0
|
|
* 0b0..Automatic clock gating is disabled
|
|
* 0b1..Automatic clock gating is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_ACC0_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_CTIMER0_SHIFT)) & MRCC_MRCC_GLB_ACC0_CTIMER0_MASK)
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|
#define MRCC_MRCC_GLB_ACC0_CTIMER1_MASK (0x8U)
|
|
#define MRCC_MRCC_GLB_ACC0_CTIMER1_SHIFT (3U)
|
|
/*! CTIMER1 - Write to CTIMER1
|
|
* 0b0..Automatic clock gating is disabled
|
|
* 0b1..Automatic clock gating is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_ACC0_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_CTIMER1_SHIFT)) & MRCC_MRCC_GLB_ACC0_CTIMER1_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_ACC0_CTIMER2_MASK (0x10U)
|
|
#define MRCC_MRCC_GLB_ACC0_CTIMER2_SHIFT (4U)
|
|
/*! CTIMER2 - Write to CTIMER2
|
|
* 0b0..Automatic clock gating is disabled
|
|
* 0b1..Automatic clock gating is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_ACC0_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_CTIMER2_SHIFT)) & MRCC_MRCC_GLB_ACC0_CTIMER2_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_ACC0_FREQME_MASK (0x20U)
|
|
#define MRCC_MRCC_GLB_ACC0_FREQME_SHIFT (5U)
|
|
/*! FREQME - Write to FREQME
|
|
* 0b0..Automatic clock gating is disabled
|
|
* 0b1..Automatic clock gating is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_ACC0_FREQME(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_FREQME_SHIFT)) & MRCC_MRCC_GLB_ACC0_FREQME_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_ACC0_UTICK0_MASK (0x40U)
|
|
#define MRCC_MRCC_GLB_ACC0_UTICK0_SHIFT (6U)
|
|
/*! UTICK0 - Write to UTICK0
|
|
* 0b0..Automatic clock gating is disabled
|
|
* 0b1..Automatic clock gating is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_ACC0_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_UTICK0_SHIFT)) & MRCC_MRCC_GLB_ACC0_UTICK0_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_ACC0_WWDT0_MASK (0x80U)
|
|
#define MRCC_MRCC_GLB_ACC0_WWDT0_SHIFT (7U)
|
|
/*! WWDT0 - Write to WWDT0
|
|
* 0b0..Automatic clock gating is disabled
|
|
* 0b1..Automatic clock gating is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_ACC0_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_WWDT0_SHIFT)) & MRCC_MRCC_GLB_ACC0_WWDT0_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_ACC0_DMA_MASK (0x100U)
|
|
#define MRCC_MRCC_GLB_ACC0_DMA_SHIFT (8U)
|
|
/*! DMA - Write to DMA
|
|
* 0b0..Automatic clock gating is disabled
|
|
* 0b1..Automatic clock gating is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_ACC0_DMA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_DMA_SHIFT)) & MRCC_MRCC_GLB_ACC0_DMA_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_ACC0_AOI0_MASK (0x200U)
|
|
#define MRCC_MRCC_GLB_ACC0_AOI0_SHIFT (9U)
|
|
/*! AOI0 - Write to AOI0
|
|
* 0b0..Automatic clock gating is disabled
|
|
* 0b1..Automatic clock gating is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_ACC0_AOI0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_AOI0_SHIFT)) & MRCC_MRCC_GLB_ACC0_AOI0_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_ACC0_CRC_MASK (0x400U)
|
|
#define MRCC_MRCC_GLB_ACC0_CRC_SHIFT (10U)
|
|
/*! CRC - Write to CRC
|
|
* 0b0..Automatic clock gating is disabled
|
|
* 0b1..Automatic clock gating is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_ACC0_CRC(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_CRC_SHIFT)) & MRCC_MRCC_GLB_ACC0_CRC_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_ACC0_EIM_MASK (0x800U)
|
|
#define MRCC_MRCC_GLB_ACC0_EIM_SHIFT (11U)
|
|
/*! EIM - Write to EIM
|
|
* 0b0..Automatic clock gating is disabled
|
|
* 0b1..Automatic clock gating is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_ACC0_EIM(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_EIM_SHIFT)) & MRCC_MRCC_GLB_ACC0_EIM_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_ACC0_ERM_MASK (0x1000U)
|
|
#define MRCC_MRCC_GLB_ACC0_ERM_SHIFT (12U)
|
|
/*! ERM - Write to ERM
|
|
* 0b0..Automatic clock gating is disabled
|
|
* 0b1..Automatic clock gating is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_ACC0_ERM(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_ERM_SHIFT)) & MRCC_MRCC_GLB_ACC0_ERM_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_ACC0_LPI2C0_MASK (0x10000U)
|
|
#define MRCC_MRCC_GLB_ACC0_LPI2C0_SHIFT (16U)
|
|
/*! LPI2C0 - Write to LPI2C0
|
|
* 0b0..Automatic clock gating is disabled
|
|
* 0b1..Automatic clock gating is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_ACC0_LPI2C0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPI2C0_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPI2C0_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_ACC0_LPSPI0_MASK (0x20000U)
|
|
#define MRCC_MRCC_GLB_ACC0_LPSPI0_SHIFT (17U)
|
|
/*! LPSPI0 - Write to LPSPI0
|
|
* 0b0..Automatic clock gating is disabled
|
|
* 0b1..Automatic clock gating is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_ACC0_LPSPI0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPSPI0_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPSPI0_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_ACC0_LPSPI1_MASK (0x40000U)
|
|
#define MRCC_MRCC_GLB_ACC0_LPSPI1_SHIFT (18U)
|
|
/*! LPSPI1 - Write to LPSPI1
|
|
* 0b0..Automatic clock gating is disabled
|
|
* 0b1..Automatic clock gating is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_ACC0_LPSPI1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPSPI1_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPSPI1_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_ACC0_LPUART0_MASK (0x80000U)
|
|
#define MRCC_MRCC_GLB_ACC0_LPUART0_SHIFT (19U)
|
|
/*! LPUART0 - Write to LPUART0
|
|
* 0b0..Automatic clock gating is disabled
|
|
* 0b1..Automatic clock gating is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_ACC0_LPUART0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPUART0_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPUART0_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_ACC0_LPUART1_MASK (0x100000U)
|
|
#define MRCC_MRCC_GLB_ACC0_LPUART1_SHIFT (20U)
|
|
/*! LPUART1 - Write to LPUART1
|
|
* 0b0..Automatic clock gating is disabled
|
|
* 0b1..Automatic clock gating is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_ACC0_LPUART1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPUART1_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPUART1_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_ACC0_LPUART2_MASK (0x200000U)
|
|
#define MRCC_MRCC_GLB_ACC0_LPUART2_SHIFT (21U)
|
|
/*! LPUART2 - Write to LPUART2
|
|
* 0b0..Automatic clock gating is disabled
|
|
* 0b1..Automatic clock gating is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_ACC0_LPUART2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPUART2_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPUART2_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_ACC0_USB0_MASK (0x400000U)
|
|
#define MRCC_MRCC_GLB_ACC0_USB0_SHIFT (22U)
|
|
/*! USB0 - Write to USB0
|
|
* 0b0..Automatic clock gating is disabled
|
|
* 0b1..Automatic clock gating is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_ACC0_USB0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_USB0_SHIFT)) & MRCC_MRCC_GLB_ACC0_USB0_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_ACC0_QDC0_MASK (0x800000U)
|
|
#define MRCC_MRCC_GLB_ACC0_QDC0_SHIFT (23U)
|
|
/*! QDC0 - Write to QDC0
|
|
* 0b0..Automatic clock gating is disabled
|
|
* 0b1..Automatic clock gating is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_ACC0_QDC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_QDC0_SHIFT)) & MRCC_MRCC_GLB_ACC0_QDC0_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_ACC0_FLEXPWM0_MASK (0x1000000U)
|
|
#define MRCC_MRCC_GLB_ACC0_FLEXPWM0_SHIFT (24U)
|
|
/*! FLEXPWM0 - Write to FLEXPWM0
|
|
* 0b0..Automatic clock gating is disabled
|
|
* 0b1..Automatic clock gating is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_ACC0_FLEXPWM0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_FLEXPWM0_SHIFT)) & MRCC_MRCC_GLB_ACC0_FLEXPWM0_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_ACC0_OSTIMER0_MASK (0x2000000U)
|
|
#define MRCC_MRCC_GLB_ACC0_OSTIMER0_SHIFT (25U)
|
|
/*! OSTIMER0 - Write to OSTIMER0
|
|
* 0b0..Automatic clock gating is disabled
|
|
* 0b1..Automatic clock gating is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_ACC0_OSTIMER0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_OSTIMER0_SHIFT)) & MRCC_MRCC_GLB_ACC0_OSTIMER0_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_ACC0_ADC0_MASK (0x4000000U)
|
|
#define MRCC_MRCC_GLB_ACC0_ADC0_SHIFT (26U)
|
|
/*! ADC0 - Write to ADC0
|
|
* 0b0..Automatic clock gating is disabled
|
|
* 0b1..Automatic clock gating is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_ACC0_ADC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_ADC0_SHIFT)) & MRCC_MRCC_GLB_ACC0_ADC0_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_ACC0_CMP0_MASK (0x8000000U)
|
|
#define MRCC_MRCC_GLB_ACC0_CMP0_SHIFT (27U)
|
|
/*! CMP0 - Write to CMP0
|
|
* 0b0..Automatic clock gating is disabled
|
|
* 0b1..Automatic clock gating is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_ACC0_CMP0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_CMP0_SHIFT)) & MRCC_MRCC_GLB_ACC0_CMP0_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_ACC0_CMP1_MASK (0x10000000U)
|
|
#define MRCC_MRCC_GLB_ACC0_CMP1_SHIFT (28U)
|
|
/*! CMP1 - Write to CMP1
|
|
* 0b0..Automatic clock gating is disabled
|
|
* 0b1..Automatic clock gating is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_ACC0_CMP1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_CMP1_SHIFT)) & MRCC_MRCC_GLB_ACC0_CMP1_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_ACC0_PORT0_MASK (0x20000000U)
|
|
#define MRCC_MRCC_GLB_ACC0_PORT0_SHIFT (29U)
|
|
/*! PORT0 - Write to PORT0
|
|
* 0b0..Automatic clock gating is disabled
|
|
* 0b1..Automatic clock gating is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_ACC0_PORT0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_PORT0_SHIFT)) & MRCC_MRCC_GLB_ACC0_PORT0_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_ACC0_PORT1_MASK (0x40000000U)
|
|
#define MRCC_MRCC_GLB_ACC0_PORT1_SHIFT (30U)
|
|
/*! PORT1 - Write to PORT1
|
|
* 0b0..Automatic clock gating is disabled
|
|
* 0b1..Automatic clock gating is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_ACC0_PORT1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_PORT1_SHIFT)) & MRCC_MRCC_GLB_ACC0_PORT1_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_ACC0_PORT2_MASK (0x80000000U)
|
|
#define MRCC_MRCC_GLB_ACC0_PORT2_SHIFT (31U)
|
|
/*! PORT2 - Write to PORT2
|
|
* 0b0..Automatic clock gating is disabled
|
|
* 0b1..Automatic clock gating is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_ACC0_PORT2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_PORT2_SHIFT)) & MRCC_MRCC_GLB_ACC0_PORT2_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MRCC_GLB_ACC1 - Control Automatic Clock Gating 1 */
|
|
/*! @{ */
|
|
|
|
#define MRCC_MRCC_GLB_ACC1_PORT3_MASK (0x1U)
|
|
#define MRCC_MRCC_GLB_ACC1_PORT3_SHIFT (0U)
|
|
/*! PORT3 - Write to PORT3
|
|
* 0b0..Automatic clock gating is disabled
|
|
* 0b1..Automatic clock gating is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_ACC1_PORT3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_PORT3_SHIFT)) & MRCC_MRCC_GLB_ACC1_PORT3_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_ACC1_EZRAMC_RAMA_MASK (0x10U)
|
|
#define MRCC_MRCC_GLB_ACC1_EZRAMC_RAMA_SHIFT (4U)
|
|
/*! EZRAMC_RAMA - Write to EZRAMC_RAMA
|
|
* 0b0..Automatic clock gating is disabled
|
|
* 0b1..Automatic clock gating is enabled
|
|
*/
|
|
#define MRCC_MRCC_GLB_ACC1_EZRAMC_RAMA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_EZRAMC_RAMA_SHIFT)) & MRCC_MRCC_GLB_ACC1_EZRAMC_RAMA_MASK)
|
|
|
|
#define MRCC_MRCC_GLB_ACC1_GPIO0_MASK (0x20U)
|
|
#define MRCC_MRCC_GLB_ACC1_GPIO0_SHIFT (5U)
|
|
/*! GPIO0 - Write to GPIO0
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* 0b0..Automatic clock gating is disabled
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* 0b1..Automatic clock gating is enabled
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*/
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#define MRCC_MRCC_GLB_ACC1_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_GPIO0_SHIFT)) & MRCC_MRCC_GLB_ACC1_GPIO0_MASK)
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#define MRCC_MRCC_GLB_ACC1_GPIO1_MASK (0x40U)
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#define MRCC_MRCC_GLB_ACC1_GPIO1_SHIFT (6U)
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/*! GPIO1 - Write to GPIO1
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* 0b0..Automatic clock gating is disabled
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* 0b1..Automatic clock gating is enabled
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*/
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#define MRCC_MRCC_GLB_ACC1_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_GPIO1_SHIFT)) & MRCC_MRCC_GLB_ACC1_GPIO1_MASK)
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#define MRCC_MRCC_GLB_ACC1_GPIO2_MASK (0x80U)
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#define MRCC_MRCC_GLB_ACC1_GPIO2_SHIFT (7U)
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/*! GPIO2 - Write to GPIO2
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* 0b0..Automatic clock gating is disabled
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* 0b1..Automatic clock gating is enabled
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*/
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#define MRCC_MRCC_GLB_ACC1_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_GPIO2_SHIFT)) & MRCC_MRCC_GLB_ACC1_GPIO2_MASK)
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#define MRCC_MRCC_GLB_ACC1_GPIO3_MASK (0x100U)
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#define MRCC_MRCC_GLB_ACC1_GPIO3_SHIFT (8U)
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/*! GPIO3 - Write to GPIO3
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* 0b0..Automatic clock gating is disabled
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* 0b1..Automatic clock gating is enabled
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*/
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#define MRCC_MRCC_GLB_ACC1_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_GPIO3_SHIFT)) & MRCC_MRCC_GLB_ACC1_GPIO3_MASK)
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#define MRCC_MRCC_GLB_ACC1_ROMCP_MASK (0x200U)
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#define MRCC_MRCC_GLB_ACC1_ROMCP_SHIFT (9U)
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/*! ROMCP - Write to ROMCP
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* 0b0..Automatic clock gating is disabled
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* 0b1..Automatic clock gating is enabled
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*/
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#define MRCC_MRCC_GLB_ACC1_ROMCP(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_ROMCP_SHIFT)) & MRCC_MRCC_GLB_ACC1_ROMCP_MASK)
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/*! @} */
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/*! @name MRCC_I3C0_FCLK_CLKSEL - I3C0_FCLK clock selection control */
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/*! @{ */
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#define MRCC_MRCC_I3C0_FCLK_CLKSEL_MUX_MASK (0x7U)
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#define MRCC_MRCC_I3C0_FCLK_CLKSEL_MUX_SHIFT (0U)
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/*! MUX - Functional Clock Mux Select
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* 0b101..CLK_1M
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* 0b011..CLK_IN
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* 0b010..FRO_HF_DIV
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* 0b000..FRO_12M
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*/
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#define MRCC_MRCC_I3C0_FCLK_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_I3C0_FCLK_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_I3C0_FCLK_CLKSEL_MUX_MASK)
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/*! @} */
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/*! @name MRCC_I3C0_FCLK_CLKDIV - I3C0_FCLK clock divider control */
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/*! @{ */
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#define MRCC_MRCC_I3C0_FCLK_CLKDIV_DIV_MASK (0xFU)
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#define MRCC_MRCC_I3C0_FCLK_CLKDIV_DIV_SHIFT (0U)
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/*! DIV - Functional Clock Divider */
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#define MRCC_MRCC_I3C0_FCLK_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_I3C0_FCLK_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_I3C0_FCLK_CLKDIV_DIV_MASK)
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#define MRCC_MRCC_I3C0_FCLK_CLKDIV_RESET_MASK (0x20000000U)
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#define MRCC_MRCC_I3C0_FCLK_CLKDIV_RESET_SHIFT (29U)
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/*! RESET - Reset divider counter
|
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* 0b0..Divider isn't reset
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* 0b1..Divider is reset
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*/
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#define MRCC_MRCC_I3C0_FCLK_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_I3C0_FCLK_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_I3C0_FCLK_CLKDIV_RESET_MASK)
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#define MRCC_MRCC_I3C0_FCLK_CLKDIV_HALT_MASK (0x40000000U)
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#define MRCC_MRCC_I3C0_FCLK_CLKDIV_HALT_SHIFT (30U)
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/*! HALT - Halt divider counter
|
|
* 0b0..Divider clock is running
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* 0b1..Divider clock is stopped
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*/
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#define MRCC_MRCC_I3C0_FCLK_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_I3C0_FCLK_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_I3C0_FCLK_CLKDIV_HALT_MASK)
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#define MRCC_MRCC_I3C0_FCLK_CLKDIV_UNSTAB_MASK (0x80000000U)
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#define MRCC_MRCC_I3C0_FCLK_CLKDIV_UNSTAB_SHIFT (31U)
|
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/*! UNSTAB - Divider status flag
|
|
* 0b0..Divider clock is stable
|
|
* 0b1..Clock frequency isn't stable
|
|
*/
|
|
#define MRCC_MRCC_I3C0_FCLK_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_I3C0_FCLK_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_I3C0_FCLK_CLKDIV_UNSTAB_MASK)
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/*! @} */
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/*! @name MRCC_CTIMER0_CLKSEL - CTIMER0 clock selection control */
|
|
/*! @{ */
|
|
|
|
#define MRCC_MRCC_CTIMER0_CLKSEL_MUX_MASK (0x7U)
|
|
#define MRCC_MRCC_CTIMER0_CLKSEL_MUX_SHIFT (0U)
|
|
/*! MUX - Functional Clock Mux Select
|
|
* 0b101..CLK_1M
|
|
* 0b100..CLK_16K
|
|
* 0b011..CLK_IN
|
|
* 0b001..FRO_HF_GATED
|
|
* 0b000..FRO_12M
|
|
*/
|
|
#define MRCC_MRCC_CTIMER0_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_CTIMER0_CLKSEL_MUX_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MRCC_CTIMER0_CLKDIV - CTIMER0 clock divider control */
|
|
/*! @{ */
|
|
|
|
#define MRCC_MRCC_CTIMER0_CLKDIV_DIV_MASK (0xFU)
|
|
#define MRCC_MRCC_CTIMER0_CLKDIV_DIV_SHIFT (0U)
|
|
/*! DIV - Functional Clock Divider */
|
|
#define MRCC_MRCC_CTIMER0_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CTIMER0_CLKDIV_DIV_MASK)
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|
|
#define MRCC_MRCC_CTIMER0_CLKDIV_RESET_MASK (0x20000000U)
|
|
#define MRCC_MRCC_CTIMER0_CLKDIV_RESET_SHIFT (29U)
|
|
/*! RESET - Reset divider counter
|
|
* 0b0..Divider isn't reset
|
|
* 0b1..Divider is reset
|
|
*/
|
|
#define MRCC_MRCC_CTIMER0_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CTIMER0_CLKDIV_RESET_MASK)
|
|
|
|
#define MRCC_MRCC_CTIMER0_CLKDIV_HALT_MASK (0x40000000U)
|
|
#define MRCC_MRCC_CTIMER0_CLKDIV_HALT_SHIFT (30U)
|
|
/*! HALT - Halt divider counter
|
|
* 0b0..Divider clock is running
|
|
* 0b1..Divider clock is stopped
|
|
*/
|
|
#define MRCC_MRCC_CTIMER0_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CTIMER0_CLKDIV_HALT_MASK)
|
|
|
|
#define MRCC_MRCC_CTIMER0_CLKDIV_UNSTAB_MASK (0x80000000U)
|
|
#define MRCC_MRCC_CTIMER0_CLKDIV_UNSTAB_SHIFT (31U)
|
|
/*! UNSTAB - Divider status flag
|
|
* 0b0..Divider clock is stable
|
|
* 0b1..Clock frequency isn't stable
|
|
*/
|
|
#define MRCC_MRCC_CTIMER0_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CTIMER0_CLKDIV_UNSTAB_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MRCC_CTIMER1_CLKSEL - CTIMER1 clock selection control */
|
|
/*! @{ */
|
|
|
|
#define MRCC_MRCC_CTIMER1_CLKSEL_MUX_MASK (0x7U)
|
|
#define MRCC_MRCC_CTIMER1_CLKSEL_MUX_SHIFT (0U)
|
|
/*! MUX - Functional Clock Mux Select
|
|
* 0b101..CLK_1M
|
|
* 0b100..CLK_16K
|
|
* 0b011..CLK_IN
|
|
* 0b001..FRO_HF_GATED
|
|
* 0b000..FRO_12M
|
|
*/
|
|
#define MRCC_MRCC_CTIMER1_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER1_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_CTIMER1_CLKSEL_MUX_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MRCC_CTIMER1_CLKDIV - CTIMER1 clock divider control */
|
|
/*! @{ */
|
|
|
|
#define MRCC_MRCC_CTIMER1_CLKDIV_DIV_MASK (0xFU)
|
|
#define MRCC_MRCC_CTIMER1_CLKDIV_DIV_SHIFT (0U)
|
|
/*! DIV - Functional Clock Divider */
|
|
#define MRCC_MRCC_CTIMER1_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER1_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CTIMER1_CLKDIV_DIV_MASK)
|
|
|
|
#define MRCC_MRCC_CTIMER1_CLKDIV_RESET_MASK (0x20000000U)
|
|
#define MRCC_MRCC_CTIMER1_CLKDIV_RESET_SHIFT (29U)
|
|
/*! RESET - Reset divider counter
|
|
* 0b0..Divider isn't reset
|
|
* 0b1..Divider is reset
|
|
*/
|
|
#define MRCC_MRCC_CTIMER1_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER1_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CTIMER1_CLKDIV_RESET_MASK)
|
|
|
|
#define MRCC_MRCC_CTIMER1_CLKDIV_HALT_MASK (0x40000000U)
|
|
#define MRCC_MRCC_CTIMER1_CLKDIV_HALT_SHIFT (30U)
|
|
/*! HALT - Halt divider counter
|
|
* 0b0..Divider clock is running
|
|
* 0b1..Divider clock is stopped
|
|
*/
|
|
#define MRCC_MRCC_CTIMER1_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER1_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CTIMER1_CLKDIV_HALT_MASK)
|
|
|
|
#define MRCC_MRCC_CTIMER1_CLKDIV_UNSTAB_MASK (0x80000000U)
|
|
#define MRCC_MRCC_CTIMER1_CLKDIV_UNSTAB_SHIFT (31U)
|
|
/*! UNSTAB - Divider status flag
|
|
* 0b0..Divider clock is stable
|
|
* 0b1..Clock frequency isn't stable
|
|
*/
|
|
#define MRCC_MRCC_CTIMER1_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER1_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CTIMER1_CLKDIV_UNSTAB_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MRCC_CTIMER2_CLKSEL - CTIMER2 clock selection control */
|
|
/*! @{ */
|
|
|
|
#define MRCC_MRCC_CTIMER2_CLKSEL_MUX_MASK (0x7U)
|
|
#define MRCC_MRCC_CTIMER2_CLKSEL_MUX_SHIFT (0U)
|
|
/*! MUX - Functional Clock Mux Select
|
|
* 0b101..CLK_1M
|
|
* 0b100..CLK_16K
|
|
* 0b011..CLK_IN
|
|
* 0b001..FRO_HF_GATED
|
|
* 0b000..FRO_12M
|
|
*/
|
|
#define MRCC_MRCC_CTIMER2_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER2_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_CTIMER2_CLKSEL_MUX_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MRCC_CTIMER2_CLKDIV - CTIMER2 clock divider control */
|
|
/*! @{ */
|
|
|
|
#define MRCC_MRCC_CTIMER2_CLKDIV_DIV_MASK (0xFU)
|
|
#define MRCC_MRCC_CTIMER2_CLKDIV_DIV_SHIFT (0U)
|
|
/*! DIV - Functional Clock Divider */
|
|
#define MRCC_MRCC_CTIMER2_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER2_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CTIMER2_CLKDIV_DIV_MASK)
|
|
|
|
#define MRCC_MRCC_CTIMER2_CLKDIV_RESET_MASK (0x20000000U)
|
|
#define MRCC_MRCC_CTIMER2_CLKDIV_RESET_SHIFT (29U)
|
|
/*! RESET - Reset divider counter
|
|
* 0b0..Divider isn't reset
|
|
* 0b1..Divider is reset
|
|
*/
|
|
#define MRCC_MRCC_CTIMER2_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER2_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CTIMER2_CLKDIV_RESET_MASK)
|
|
|
|
#define MRCC_MRCC_CTIMER2_CLKDIV_HALT_MASK (0x40000000U)
|
|
#define MRCC_MRCC_CTIMER2_CLKDIV_HALT_SHIFT (30U)
|
|
/*! HALT - Halt divider counter
|
|
* 0b0..Divider clock is running
|
|
* 0b1..Divider clock is stopped
|
|
*/
|
|
#define MRCC_MRCC_CTIMER2_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER2_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CTIMER2_CLKDIV_HALT_MASK)
|
|
|
|
#define MRCC_MRCC_CTIMER2_CLKDIV_UNSTAB_MASK (0x80000000U)
|
|
#define MRCC_MRCC_CTIMER2_CLKDIV_UNSTAB_SHIFT (31U)
|
|
/*! UNSTAB - Divider status flag
|
|
* 0b0..Divider clock is stable
|
|
* 0b1..Clock frequency isn't stable
|
|
*/
|
|
#define MRCC_MRCC_CTIMER2_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER2_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CTIMER2_CLKDIV_UNSTAB_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MRCC_WWDT0_CLKDIV - WWDT0 clock divider control */
|
|
/*! @{ */
|
|
|
|
#define MRCC_MRCC_WWDT0_CLKDIV_DIV_MASK (0xFU)
|
|
#define MRCC_MRCC_WWDT0_CLKDIV_DIV_SHIFT (0U)
|
|
/*! DIV - Functional Clock Divider */
|
|
#define MRCC_MRCC_WWDT0_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_WWDT0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_WWDT0_CLKDIV_DIV_MASK)
|
|
|
|
#define MRCC_MRCC_WWDT0_CLKDIV_RESET_MASK (0x20000000U)
|
|
#define MRCC_MRCC_WWDT0_CLKDIV_RESET_SHIFT (29U)
|
|
/*! RESET - Reset divider counter
|
|
* 0b0..Divider isn't reset
|
|
* 0b1..Divider is reset
|
|
*/
|
|
#define MRCC_MRCC_WWDT0_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_WWDT0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_WWDT0_CLKDIV_RESET_MASK)
|
|
|
|
#define MRCC_MRCC_WWDT0_CLKDIV_HALT_MASK (0x40000000U)
|
|
#define MRCC_MRCC_WWDT0_CLKDIV_HALT_SHIFT (30U)
|
|
/*! HALT - Halt divider counter
|
|
* 0b0..Divider clock is running
|
|
* 0b1..Divider clock is stopped
|
|
*/
|
|
#define MRCC_MRCC_WWDT0_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_WWDT0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_WWDT0_CLKDIV_HALT_MASK)
|
|
|
|
#define MRCC_MRCC_WWDT0_CLKDIV_UNSTAB_MASK (0x80000000U)
|
|
#define MRCC_MRCC_WWDT0_CLKDIV_UNSTAB_SHIFT (31U)
|
|
/*! UNSTAB - Divider status flag
|
|
* 0b0..Divider clock is stable
|
|
* 0b1..Clock frequency isn't stable
|
|
*/
|
|
#define MRCC_MRCC_WWDT0_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_WWDT0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_WWDT0_CLKDIV_UNSTAB_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MRCC_LPI2C0_CLKSEL - LPI2C0 clock selection control */
|
|
/*! @{ */
|
|
|
|
#define MRCC_MRCC_LPI2C0_CLKSEL_MUX_MASK (0x7U)
|
|
#define MRCC_MRCC_LPI2C0_CLKSEL_MUX_SHIFT (0U)
|
|
/*! MUX - Functional Clock Mux Select
|
|
* 0b101..CLK_1M
|
|
* 0b011..CLK_IN
|
|
* 0b010..FRO_HF_DIV
|
|
* 0b000..FRO_12M
|
|
*/
|
|
#define MRCC_MRCC_LPI2C0_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPI2C0_CLKSEL_MUX_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MRCC_LPI2C0_CLKDIV - LPI2C0 clock divider control */
|
|
/*! @{ */
|
|
|
|
#define MRCC_MRCC_LPI2C0_CLKDIV_DIV_MASK (0xFU)
|
|
#define MRCC_MRCC_LPI2C0_CLKDIV_DIV_SHIFT (0U)
|
|
/*! DIV - Functional Clock Divider */
|
|
#define MRCC_MRCC_LPI2C0_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPI2C0_CLKDIV_DIV_MASK)
|
|
|
|
#define MRCC_MRCC_LPI2C0_CLKDIV_RESET_MASK (0x20000000U)
|
|
#define MRCC_MRCC_LPI2C0_CLKDIV_RESET_SHIFT (29U)
|
|
/*! RESET - Reset divider counter
|
|
* 0b0..Divider isn't reset
|
|
* 0b1..Divider is reset
|
|
*/
|
|
#define MRCC_MRCC_LPI2C0_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPI2C0_CLKDIV_RESET_MASK)
|
|
|
|
#define MRCC_MRCC_LPI2C0_CLKDIV_HALT_MASK (0x40000000U)
|
|
#define MRCC_MRCC_LPI2C0_CLKDIV_HALT_SHIFT (30U)
|
|
/*! HALT - Halt divider counter
|
|
* 0b0..Divider clock is running
|
|
* 0b1..Divider clock is stopped
|
|
*/
|
|
#define MRCC_MRCC_LPI2C0_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPI2C0_CLKDIV_HALT_MASK)
|
|
|
|
#define MRCC_MRCC_LPI2C0_CLKDIV_UNSTAB_MASK (0x80000000U)
|
|
#define MRCC_MRCC_LPI2C0_CLKDIV_UNSTAB_SHIFT (31U)
|
|
/*! UNSTAB - Divider status flag
|
|
* 0b0..Divider clock is stable
|
|
* 0b1..Clock frequency isn't stable
|
|
*/
|
|
#define MRCC_MRCC_LPI2C0_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPI2C0_CLKDIV_UNSTAB_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MRCC_LPSPI0_CLKSEL - LPSPI0 clock selection control */
|
|
/*! @{ */
|
|
|
|
#define MRCC_MRCC_LPSPI0_CLKSEL_MUX_MASK (0x7U)
|
|
#define MRCC_MRCC_LPSPI0_CLKSEL_MUX_SHIFT (0U)
|
|
/*! MUX - Functional Clock Mux Select
|
|
* 0b101..CLK_1M
|
|
* 0b011..CLK_IN
|
|
* 0b010..FRO_HF_DIV
|
|
* 0b000..FRO_12M
|
|
*/
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#define MRCC_MRCC_LPSPI0_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPSPI0_CLKSEL_MUX_MASK)
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/*! @} */
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/*! @name MRCC_LPSPI0_CLKDIV - LPSPI0 clock divider control */
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/*! @{ */
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#define MRCC_MRCC_LPSPI0_CLKDIV_DIV_MASK (0xFU)
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#define MRCC_MRCC_LPSPI0_CLKDIV_DIV_SHIFT (0U)
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/*! DIV - Functional Clock Divider */
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#define MRCC_MRCC_LPSPI0_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPSPI0_CLKDIV_DIV_MASK)
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#define MRCC_MRCC_LPSPI0_CLKDIV_RESET_MASK (0x20000000U)
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#define MRCC_MRCC_LPSPI0_CLKDIV_RESET_SHIFT (29U)
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/*! RESET - Reset divider counter
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* 0b0..Divider isn't reset
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* 0b1..Divider is reset
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*/
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#define MRCC_MRCC_LPSPI0_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPSPI0_CLKDIV_RESET_MASK)
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#define MRCC_MRCC_LPSPI0_CLKDIV_HALT_MASK (0x40000000U)
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#define MRCC_MRCC_LPSPI0_CLKDIV_HALT_SHIFT (30U)
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/*! HALT - Halt divider counter
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* 0b0..Divider clock is running
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* 0b1..Divider clock is stopped
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*/
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#define MRCC_MRCC_LPSPI0_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPSPI0_CLKDIV_HALT_MASK)
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#define MRCC_MRCC_LPSPI0_CLKDIV_UNSTAB_MASK (0x80000000U)
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#define MRCC_MRCC_LPSPI0_CLKDIV_UNSTAB_SHIFT (31U)
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/*! UNSTAB - Divider status flag
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* 0b0..Divider clock is stable
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* 0b1..Clock frequency isn't stable
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*/
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#define MRCC_MRCC_LPSPI0_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPSPI0_CLKDIV_UNSTAB_MASK)
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/*! @} */
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/*! @name MRCC_LPSPI1_CLKSEL - LPSPI1 clock selection control */
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/*! @{ */
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#define MRCC_MRCC_LPSPI1_CLKSEL_MUX_MASK (0x7U)
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#define MRCC_MRCC_LPSPI1_CLKSEL_MUX_SHIFT (0U)
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/*! MUX - Functional Clock Mux Select
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* 0b101..CLK_1M
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* 0b011..CLK_IN
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* 0b010..FRO_HF_DIV
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* 0b000..FRO_12M
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*/
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#define MRCC_MRCC_LPSPI1_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI1_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPSPI1_CLKSEL_MUX_MASK)
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/*! @} */
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/*! @name MRCC_LPSPI1_CLKDIV - LPSPI1 clock divider control */
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/*! @{ */
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#define MRCC_MRCC_LPSPI1_CLKDIV_DIV_MASK (0xFU)
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#define MRCC_MRCC_LPSPI1_CLKDIV_DIV_SHIFT (0U)
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/*! DIV - Functional Clock Divider */
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#define MRCC_MRCC_LPSPI1_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI1_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPSPI1_CLKDIV_DIV_MASK)
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#define MRCC_MRCC_LPSPI1_CLKDIV_RESET_MASK (0x20000000U)
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#define MRCC_MRCC_LPSPI1_CLKDIV_RESET_SHIFT (29U)
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/*! RESET - Reset divider counter
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* 0b0..Divider isn't reset
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* 0b1..Divider is reset
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*/
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#define MRCC_MRCC_LPSPI1_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI1_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPSPI1_CLKDIV_RESET_MASK)
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#define MRCC_MRCC_LPSPI1_CLKDIV_HALT_MASK (0x40000000U)
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#define MRCC_MRCC_LPSPI1_CLKDIV_HALT_SHIFT (30U)
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/*! HALT - Halt divider counter
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* 0b0..Divider clock is running
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* 0b1..Divider clock is stopped
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*/
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#define MRCC_MRCC_LPSPI1_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI1_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPSPI1_CLKDIV_HALT_MASK)
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#define MRCC_MRCC_LPSPI1_CLKDIV_UNSTAB_MASK (0x80000000U)
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#define MRCC_MRCC_LPSPI1_CLKDIV_UNSTAB_SHIFT (31U)
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/*! UNSTAB - Divider status flag
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* 0b0..Divider clock is stable
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* 0b1..Clock frequency isn't stable
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*/
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#define MRCC_MRCC_LPSPI1_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI1_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPSPI1_CLKDIV_UNSTAB_MASK)
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/*! @} */
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/*! @name MRCC_LPUART0_CLKSEL - LPUART0 clock selection control */
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/*! @{ */
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#define MRCC_MRCC_LPUART0_CLKSEL_MUX_MASK (0x7U)
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#define MRCC_MRCC_LPUART0_CLKSEL_MUX_SHIFT (0U)
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/*! MUX - Functional Clock Mux Select
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* 0b101..CLK_1M
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* 0b100..CLK_16K
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* 0b011..CLK_IN
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* 0b010..FRO_HF_DIV
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* 0b000..FRO_12M
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*/
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#define MRCC_MRCC_LPUART0_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPUART0_CLKSEL_MUX_MASK)
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/*! @} */
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/*! @name MRCC_LPUART0_CLKDIV - LPUART0 clock divider control */
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/*! @{ */
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#define MRCC_MRCC_LPUART0_CLKDIV_DIV_MASK (0xFU)
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#define MRCC_MRCC_LPUART0_CLKDIV_DIV_SHIFT (0U)
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/*! DIV - Functional Clock Divider */
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#define MRCC_MRCC_LPUART0_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPUART0_CLKDIV_DIV_MASK)
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#define MRCC_MRCC_LPUART0_CLKDIV_RESET_MASK (0x20000000U)
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#define MRCC_MRCC_LPUART0_CLKDIV_RESET_SHIFT (29U)
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/*! RESET - Reset divider counter
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* 0b0..Divider isn't reset
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* 0b1..Divider is reset
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*/
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#define MRCC_MRCC_LPUART0_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPUART0_CLKDIV_RESET_MASK)
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#define MRCC_MRCC_LPUART0_CLKDIV_HALT_MASK (0x40000000U)
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#define MRCC_MRCC_LPUART0_CLKDIV_HALT_SHIFT (30U)
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/*! HALT - Halt divider counter
|
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* 0b0..Divider clock is running
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* 0b1..Divider clock is stopped
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*/
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#define MRCC_MRCC_LPUART0_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPUART0_CLKDIV_HALT_MASK)
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#define MRCC_MRCC_LPUART0_CLKDIV_UNSTAB_MASK (0x80000000U)
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#define MRCC_MRCC_LPUART0_CLKDIV_UNSTAB_SHIFT (31U)
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/*! UNSTAB - Divider status flag
|
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* 0b0..Divider clock is stable
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* 0b1..Clock frequency isn't stable
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*/
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#define MRCC_MRCC_LPUART0_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPUART0_CLKDIV_UNSTAB_MASK)
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/*! @} */
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/*! @name MRCC_LPUART1_CLKSEL - LPUART1 clock selection control */
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/*! @{ */
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#define MRCC_MRCC_LPUART1_CLKSEL_MUX_MASK (0x7U)
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#define MRCC_MRCC_LPUART1_CLKSEL_MUX_SHIFT (0U)
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/*! MUX - Functional Clock Mux Select
|
|
* 0b101..CLK_1M
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|
* 0b100..CLK_16K
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|
* 0b011..CLK_IN
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* 0b010..FRO_HF_DIV
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* 0b000..FRO_12M
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*/
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#define MRCC_MRCC_LPUART1_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART1_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPUART1_CLKSEL_MUX_MASK)
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/*! @} */
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/*! @name MRCC_LPUART1_CLKDIV - LPUART1 clock divider control */
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/*! @{ */
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#define MRCC_MRCC_LPUART1_CLKDIV_DIV_MASK (0xFU)
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#define MRCC_MRCC_LPUART1_CLKDIV_DIV_SHIFT (0U)
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/*! DIV - Functional Clock Divider */
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#define MRCC_MRCC_LPUART1_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART1_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPUART1_CLKDIV_DIV_MASK)
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#define MRCC_MRCC_LPUART1_CLKDIV_RESET_MASK (0x20000000U)
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#define MRCC_MRCC_LPUART1_CLKDIV_RESET_SHIFT (29U)
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/*! RESET - Reset divider counter
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|
* 0b0..Divider isn't reset
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* 0b1..Divider is reset
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*/
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#define MRCC_MRCC_LPUART1_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART1_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPUART1_CLKDIV_RESET_MASK)
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#define MRCC_MRCC_LPUART1_CLKDIV_HALT_MASK (0x40000000U)
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#define MRCC_MRCC_LPUART1_CLKDIV_HALT_SHIFT (30U)
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/*! HALT - Halt divider counter
|
|
* 0b0..Divider clock is running
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|
* 0b1..Divider clock is stopped
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|
*/
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#define MRCC_MRCC_LPUART1_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART1_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPUART1_CLKDIV_HALT_MASK)
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#define MRCC_MRCC_LPUART1_CLKDIV_UNSTAB_MASK (0x80000000U)
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#define MRCC_MRCC_LPUART1_CLKDIV_UNSTAB_SHIFT (31U)
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/*! UNSTAB - Divider status flag
|
|
* 0b0..Divider clock is stable
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* 0b1..Clock frequency isn't stable
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|
*/
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#define MRCC_MRCC_LPUART1_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART1_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPUART1_CLKDIV_UNSTAB_MASK)
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/*! @} */
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/*! @name MRCC_LPUART2_CLKSEL - LPUART2 clock selection control */
|
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/*! @{ */
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|
#define MRCC_MRCC_LPUART2_CLKSEL_MUX_MASK (0x7U)
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#define MRCC_MRCC_LPUART2_CLKSEL_MUX_SHIFT (0U)
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|
/*! MUX - Functional Clock Mux Select
|
|
* 0b101..CLK_1M
|
|
* 0b100..CLK_16K
|
|
* 0b011..CLK_IN
|
|
* 0b010..FRO_HF_DIV
|
|
* 0b000..FRO_12M
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|
*/
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#define MRCC_MRCC_LPUART2_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART2_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPUART2_CLKSEL_MUX_MASK)
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/*! @} */
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/*! @name MRCC_LPUART2_CLKDIV - LPUART2 clock divider control */
|
|
/*! @{ */
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|
|
|
#define MRCC_MRCC_LPUART2_CLKDIV_DIV_MASK (0xFU)
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|
#define MRCC_MRCC_LPUART2_CLKDIV_DIV_SHIFT (0U)
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/*! DIV - Functional Clock Divider */
|
|
#define MRCC_MRCC_LPUART2_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART2_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPUART2_CLKDIV_DIV_MASK)
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#define MRCC_MRCC_LPUART2_CLKDIV_RESET_MASK (0x20000000U)
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|
#define MRCC_MRCC_LPUART2_CLKDIV_RESET_SHIFT (29U)
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|
/*! RESET - Reset divider counter
|
|
* 0b0..Divider isn't reset
|
|
* 0b1..Divider is reset
|
|
*/
|
|
#define MRCC_MRCC_LPUART2_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART2_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPUART2_CLKDIV_RESET_MASK)
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|
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|
#define MRCC_MRCC_LPUART2_CLKDIV_HALT_MASK (0x40000000U)
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|
#define MRCC_MRCC_LPUART2_CLKDIV_HALT_SHIFT (30U)
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|
/*! HALT - Halt divider counter
|
|
* 0b0..Divider clock is running
|
|
* 0b1..Divider clock is stopped
|
|
*/
|
|
#define MRCC_MRCC_LPUART2_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART2_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPUART2_CLKDIV_HALT_MASK)
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|
|
#define MRCC_MRCC_LPUART2_CLKDIV_UNSTAB_MASK (0x80000000U)
|
|
#define MRCC_MRCC_LPUART2_CLKDIV_UNSTAB_SHIFT (31U)
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|
/*! UNSTAB - Divider status flag
|
|
* 0b0..Divider clock is stable
|
|
* 0b1..Clock frequency isn't stable
|
|
*/
|
|
#define MRCC_MRCC_LPUART2_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART2_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPUART2_CLKDIV_UNSTAB_MASK)
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|
/*! @} */
|
|
|
|
/*! @name MRCC_USB0_CLKSEL - USB0 clock selection control */
|
|
/*! @{ */
|
|
|
|
#define MRCC_MRCC_USB0_CLKSEL_MUX_MASK (0x3U)
|
|
#define MRCC_MRCC_USB0_CLKSEL_MUX_SHIFT (0U)
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|
/*! MUX - Functional Clock Mux Select
|
|
* 0b10..clkroot_sosc
|
|
* 0b01..scg_scg_firc_48mhz_clk
|
|
*/
|
|
#define MRCC_MRCC_USB0_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_USB0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_USB0_CLKSEL_MUX_MASK)
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/*! @} */
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/*! @name MRCC_LPTMR0_CLKSEL - LPTMR0 clock selection control */
|
|
/*! @{ */
|
|
|
|
#define MRCC_MRCC_LPTMR0_CLKSEL_MUX_MASK (0x7U)
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|
#define MRCC_MRCC_LPTMR0_CLKSEL_MUX_SHIFT (0U)
|
|
/*! MUX - Functional Clock Mux Select
|
|
* 0b101..CLK_1M
|
|
* 0b011..CLK_IN
|
|
* 0b010..FRO_HF_DIV
|
|
* 0b000..FRO_12M
|
|
*/
|
|
#define MRCC_MRCC_LPTMR0_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPTMR0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPTMR0_CLKSEL_MUX_MASK)
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/*! @} */
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/*! @name MRCC_LPTMR0_CLKDIV - LPTMR0 clock divider control */
|
|
/*! @{ */
|
|
|
|
#define MRCC_MRCC_LPTMR0_CLKDIV_DIV_MASK (0xFU)
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|
#define MRCC_MRCC_LPTMR0_CLKDIV_DIV_SHIFT (0U)
|
|
/*! DIV - Functional Clock Divider */
|
|
#define MRCC_MRCC_LPTMR0_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPTMR0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPTMR0_CLKDIV_DIV_MASK)
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|
#define MRCC_MRCC_LPTMR0_CLKDIV_RESET_MASK (0x20000000U)
|
|
#define MRCC_MRCC_LPTMR0_CLKDIV_RESET_SHIFT (29U)
|
|
/*! RESET - Reset divider counter
|
|
* 0b0..Divider isn't reset
|
|
* 0b1..Divider is reset
|
|
*/
|
|
#define MRCC_MRCC_LPTMR0_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPTMR0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPTMR0_CLKDIV_RESET_MASK)
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|
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|
#define MRCC_MRCC_LPTMR0_CLKDIV_HALT_MASK (0x40000000U)
|
|
#define MRCC_MRCC_LPTMR0_CLKDIV_HALT_SHIFT (30U)
|
|
/*! HALT - Halt divider counter
|
|
* 0b0..Divider clock is running
|
|
* 0b1..Divider clock is stopped
|
|
*/
|
|
#define MRCC_MRCC_LPTMR0_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPTMR0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPTMR0_CLKDIV_HALT_MASK)
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|
|
|
#define MRCC_MRCC_LPTMR0_CLKDIV_UNSTAB_MASK (0x80000000U)
|
|
#define MRCC_MRCC_LPTMR0_CLKDIV_UNSTAB_SHIFT (31U)
|
|
/*! UNSTAB - Divider status flag
|
|
* 0b0..Divider clock is stable
|
|
* 0b1..Clock frequency isn't stable
|
|
*/
|
|
#define MRCC_MRCC_LPTMR0_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPTMR0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPTMR0_CLKDIV_UNSTAB_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MRCC_OSTIMER0_CLKSEL - OSTIMER0 clock selection control */
|
|
/*! @{ */
|
|
|
|
#define MRCC_MRCC_OSTIMER0_CLKSEL_MUX_MASK (0x3U)
|
|
#define MRCC_MRCC_OSTIMER0_CLKSEL_MUX_SHIFT (0U)
|
|
/*! MUX - Functional Clock Mux Select
|
|
* 0b10..clkroot_1m
|
|
* 0b00..clkroot_16k
|
|
*/
|
|
#define MRCC_MRCC_OSTIMER0_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_OSTIMER0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_OSTIMER0_CLKSEL_MUX_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MRCC_ADC0_CLKSEL - ADC0 clock selection control */
|
|
/*! @{ */
|
|
|
|
#define MRCC_MRCC_ADC0_CLKSEL_MUX_MASK (0x7U)
|
|
#define MRCC_MRCC_ADC0_CLKSEL_MUX_SHIFT (0U)
|
|
/*! MUX - Functional Clock Mux Select
|
|
* 0b101..CLK_1M
|
|
* 0b011..CLK_IN
|
|
* 0b001..FRO_HF_GATED
|
|
* 0b000..FRO_12M
|
|
*/
|
|
#define MRCC_MRCC_ADC0_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_ADC0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_ADC0_CLKSEL_MUX_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MRCC_ADC0_CLKDIV - ADC0 clock divider control */
|
|
/*! @{ */
|
|
|
|
#define MRCC_MRCC_ADC0_CLKDIV_DIV_MASK (0xFU)
|
|
#define MRCC_MRCC_ADC0_CLKDIV_DIV_SHIFT (0U)
|
|
/*! DIV - Functional Clock Divider */
|
|
#define MRCC_MRCC_ADC0_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_ADC0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_ADC0_CLKDIV_DIV_MASK)
|
|
|
|
#define MRCC_MRCC_ADC0_CLKDIV_RESET_MASK (0x20000000U)
|
|
#define MRCC_MRCC_ADC0_CLKDIV_RESET_SHIFT (29U)
|
|
/*! RESET - Reset divider counter
|
|
* 0b0..Divider isn't reset
|
|
* 0b1..Divider is reset
|
|
*/
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#define MRCC_MRCC_ADC0_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_ADC0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_ADC0_CLKDIV_RESET_MASK)
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#define MRCC_MRCC_ADC0_CLKDIV_HALT_MASK (0x40000000U)
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#define MRCC_MRCC_ADC0_CLKDIV_HALT_SHIFT (30U)
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/*! HALT - Halt divider counter
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* 0b0..Divider clock is running
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* 0b1..Divider clock is stopped
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*/
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#define MRCC_MRCC_ADC0_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_ADC0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_ADC0_CLKDIV_HALT_MASK)
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#define MRCC_MRCC_ADC0_CLKDIV_UNSTAB_MASK (0x80000000U)
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#define MRCC_MRCC_ADC0_CLKDIV_UNSTAB_SHIFT (31U)
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/*! UNSTAB - Divider status flag
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* 0b0..Divider clock is stable
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* 0b1..Clock frequency isn't stable
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*/
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#define MRCC_MRCC_ADC0_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_ADC0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_ADC0_CLKDIV_UNSTAB_MASK)
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/*! @} */
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/*! @name MRCC_CMP0_FUNC_CLKDIV - CMP0_FUNC clock divider control */
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/*! @{ */
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#define MRCC_MRCC_CMP0_FUNC_CLKDIV_DIV_MASK (0xFU)
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#define MRCC_MRCC_CMP0_FUNC_CLKDIV_DIV_SHIFT (0U)
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/*! DIV - Functional Clock Divider */
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#define MRCC_MRCC_CMP0_FUNC_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_FUNC_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CMP0_FUNC_CLKDIV_DIV_MASK)
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#define MRCC_MRCC_CMP0_FUNC_CLKDIV_RESET_MASK (0x20000000U)
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#define MRCC_MRCC_CMP0_FUNC_CLKDIV_RESET_SHIFT (29U)
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/*! RESET - Reset divider counter
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* 0b0..Divider isn't reset
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* 0b1..Divider is reset
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*/
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#define MRCC_MRCC_CMP0_FUNC_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_FUNC_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CMP0_FUNC_CLKDIV_RESET_MASK)
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#define MRCC_MRCC_CMP0_FUNC_CLKDIV_HALT_MASK (0x40000000U)
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#define MRCC_MRCC_CMP0_FUNC_CLKDIV_HALT_SHIFT (30U)
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/*! HALT - Halt divider counter
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* 0b0..Divider clock is running
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* 0b1..Divider clock is stopped
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*/
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#define MRCC_MRCC_CMP0_FUNC_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_FUNC_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CMP0_FUNC_CLKDIV_HALT_MASK)
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#define MRCC_MRCC_CMP0_FUNC_CLKDIV_UNSTAB_MASK (0x80000000U)
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#define MRCC_MRCC_CMP0_FUNC_CLKDIV_UNSTAB_SHIFT (31U)
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/*! UNSTAB - Divider status flag
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* 0b0..Divider clock is stable
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* 0b1..Clock frequency isn't stable
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*/
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#define MRCC_MRCC_CMP0_FUNC_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_FUNC_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CMP0_FUNC_CLKDIV_UNSTAB_MASK)
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/*! @} */
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/*! @name MRCC_CMP0_RR_CLKSEL - CMP0_RR clock selection control */
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/*! @{ */
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#define MRCC_MRCC_CMP0_RR_CLKSEL_MUX_MASK (0x7U)
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#define MRCC_MRCC_CMP0_RR_CLKSEL_MUX_SHIFT (0U)
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/*! MUX - Functional Clock Mux Select
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* 0b101..CLK_1M
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* 0b011..CLK_IN
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* 0b010..FRO_HF_DIV
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* 0b000..FRO_12M
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*/
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#define MRCC_MRCC_CMP0_RR_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_RR_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_CMP0_RR_CLKSEL_MUX_MASK)
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/*! @} */
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/*! @name MRCC_CMP0_RR_CLKDIV - CMP0_RR clock divider control */
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/*! @{ */
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#define MRCC_MRCC_CMP0_RR_CLKDIV_DIV_MASK (0x3U)
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#define MRCC_MRCC_CMP0_RR_CLKDIV_DIV_SHIFT (0U)
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/*! DIV - Functional Clock Divider */
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#define MRCC_MRCC_CMP0_RR_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_RR_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CMP0_RR_CLKDIV_DIV_MASK)
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#define MRCC_MRCC_CMP0_RR_CLKDIV_RESET_MASK (0x20000000U)
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#define MRCC_MRCC_CMP0_RR_CLKDIV_RESET_SHIFT (29U)
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/*! RESET - Reset divider counter
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* 0b0..Divider isn't reset
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* 0b1..Divider is reset
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*/
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#define MRCC_MRCC_CMP0_RR_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_RR_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CMP0_RR_CLKDIV_RESET_MASK)
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#define MRCC_MRCC_CMP0_RR_CLKDIV_HALT_MASK (0x40000000U)
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#define MRCC_MRCC_CMP0_RR_CLKDIV_HALT_SHIFT (30U)
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/*! HALT - Halt divider counter
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* 0b0..Divider clock is running
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* 0b1..Divider clock is stopped
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*/
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#define MRCC_MRCC_CMP0_RR_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_RR_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CMP0_RR_CLKDIV_HALT_MASK)
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#define MRCC_MRCC_CMP0_RR_CLKDIV_UNSTAB_MASK (0x80000000U)
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#define MRCC_MRCC_CMP0_RR_CLKDIV_UNSTAB_SHIFT (31U)
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/*! UNSTAB - Divider status flag
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* 0b0..Divider clock is stable
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* 0b1..Clock frequency isn't stable
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*/
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#define MRCC_MRCC_CMP0_RR_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_RR_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CMP0_RR_CLKDIV_UNSTAB_MASK)
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/*! @} */
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/*! @name MRCC_CMP1_FUNC_CLKDIV - CMP1_FUNC clock divider control */
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/*! @{ */
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#define MRCC_MRCC_CMP1_FUNC_CLKDIV_DIV_MASK (0xFU)
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#define MRCC_MRCC_CMP1_FUNC_CLKDIV_DIV_SHIFT (0U)
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/*! DIV - Functional Clock Divider */
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#define MRCC_MRCC_CMP1_FUNC_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_FUNC_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CMP1_FUNC_CLKDIV_DIV_MASK)
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#define MRCC_MRCC_CMP1_FUNC_CLKDIV_RESET_MASK (0x20000000U)
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#define MRCC_MRCC_CMP1_FUNC_CLKDIV_RESET_SHIFT (29U)
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/*! RESET - Reset divider counter
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* 0b0..Divider isn't reset
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* 0b1..Divider is reset
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*/
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#define MRCC_MRCC_CMP1_FUNC_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_FUNC_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CMP1_FUNC_CLKDIV_RESET_MASK)
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#define MRCC_MRCC_CMP1_FUNC_CLKDIV_HALT_MASK (0x40000000U)
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#define MRCC_MRCC_CMP1_FUNC_CLKDIV_HALT_SHIFT (30U)
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/*! HALT - Halt divider counter
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* 0b0..Divider clock is running
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* 0b1..Divider clock is stopped
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*/
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#define MRCC_MRCC_CMP1_FUNC_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_FUNC_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CMP1_FUNC_CLKDIV_HALT_MASK)
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#define MRCC_MRCC_CMP1_FUNC_CLKDIV_UNSTAB_MASK (0x80000000U)
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#define MRCC_MRCC_CMP1_FUNC_CLKDIV_UNSTAB_SHIFT (31U)
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/*! UNSTAB - Divider status flag
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* 0b0..Divider clock is stable
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* 0b1..Clock frequency isn't stable
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*/
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#define MRCC_MRCC_CMP1_FUNC_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_FUNC_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CMP1_FUNC_CLKDIV_UNSTAB_MASK)
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/*! @} */
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/*! @name MRCC_CMP1_RR_CLKSEL - CMP1_RR clock selection control */
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/*! @{ */
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#define MRCC_MRCC_CMP1_RR_CLKSEL_MUX_MASK (0x7U)
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#define MRCC_MRCC_CMP1_RR_CLKSEL_MUX_SHIFT (0U)
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/*! MUX - Functional Clock Mux Select
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* 0b101..CLK_1M
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* 0b011..CLK_IN
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* 0b010..FRO_HF_DIV
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* 0b000..FRO_12M
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*/
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#define MRCC_MRCC_CMP1_RR_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_RR_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_CMP1_RR_CLKSEL_MUX_MASK)
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/*! @} */
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/*! @name MRCC_CMP1_RR_CLKDIV - CMP1_RR clock divider control */
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/*! @{ */
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#define MRCC_MRCC_CMP1_RR_CLKDIV_DIV_MASK (0x3U)
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#define MRCC_MRCC_CMP1_RR_CLKDIV_DIV_SHIFT (0U)
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/*! DIV - Functional Clock Divider */
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#define MRCC_MRCC_CMP1_RR_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_RR_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CMP1_RR_CLKDIV_DIV_MASK)
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#define MRCC_MRCC_CMP1_RR_CLKDIV_RESET_MASK (0x20000000U)
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#define MRCC_MRCC_CMP1_RR_CLKDIV_RESET_SHIFT (29U)
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/*! RESET - Reset divider counter
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* 0b0..Divider isn't reset
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* 0b1..Divider is reset
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*/
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#define MRCC_MRCC_CMP1_RR_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_RR_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CMP1_RR_CLKDIV_RESET_MASK)
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#define MRCC_MRCC_CMP1_RR_CLKDIV_HALT_MASK (0x40000000U)
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#define MRCC_MRCC_CMP1_RR_CLKDIV_HALT_SHIFT (30U)
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/*! HALT - Halt divider counter
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* 0b0..Divider clock is running
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* 0b1..Divider clock is stopped
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*/
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#define MRCC_MRCC_CMP1_RR_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_RR_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CMP1_RR_CLKDIV_HALT_MASK)
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#define MRCC_MRCC_CMP1_RR_CLKDIV_UNSTAB_MASK (0x80000000U)
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#define MRCC_MRCC_CMP1_RR_CLKDIV_UNSTAB_SHIFT (31U)
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/*! UNSTAB - Divider status flag
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* 0b0..Divider clock is stable
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* 0b1..Clock frequency isn't stable
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*/
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#define MRCC_MRCC_CMP1_RR_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_RR_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CMP1_RR_CLKDIV_UNSTAB_MASK)
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/*! @} */
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/*! @name MRCC_DBG_TRACE_CLKSEL - DBG_TRACE clock selection control */
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/*! @{ */
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#define MRCC_MRCC_DBG_TRACE_CLKSEL_MUX_MASK (0x3U)
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#define MRCC_MRCC_DBG_TRACE_CLKSEL_MUX_SHIFT (0U)
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/*! MUX - Functional Clock Mux Select
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* 0b10..clkroot_16k
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* 0b01..clkroot_1m
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* 0b00..clkroot_cpu
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*/
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#define MRCC_MRCC_DBG_TRACE_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DBG_TRACE_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_DBG_TRACE_CLKSEL_MUX_MASK)
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/*! @} */
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/*! @name MRCC_DBG_TRACE_CLKDIV - DBG_TRACE clock divider control */
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/*! @{ */
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#define MRCC_MRCC_DBG_TRACE_CLKDIV_DIV_MASK (0xFU)
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#define MRCC_MRCC_DBG_TRACE_CLKDIV_DIV_SHIFT (0U)
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/*! DIV - Functional Clock Divider */
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#define MRCC_MRCC_DBG_TRACE_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DBG_TRACE_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_DBG_TRACE_CLKDIV_DIV_MASK)
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#define MRCC_MRCC_DBG_TRACE_CLKDIV_RESET_MASK (0x20000000U)
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#define MRCC_MRCC_DBG_TRACE_CLKDIV_RESET_SHIFT (29U)
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/*! RESET - Reset divider counter
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* 0b0..Divider isn't reset
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* 0b1..Divider is reset
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*/
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#define MRCC_MRCC_DBG_TRACE_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DBG_TRACE_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_DBG_TRACE_CLKDIV_RESET_MASK)
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#define MRCC_MRCC_DBG_TRACE_CLKDIV_HALT_MASK (0x40000000U)
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#define MRCC_MRCC_DBG_TRACE_CLKDIV_HALT_SHIFT (30U)
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/*! HALT - Halt divider counter
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* 0b0..Divider clock is running
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* 0b1..Divider clock is stopped
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*/
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#define MRCC_MRCC_DBG_TRACE_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DBG_TRACE_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_DBG_TRACE_CLKDIV_HALT_MASK)
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#define MRCC_MRCC_DBG_TRACE_CLKDIV_UNSTAB_MASK (0x80000000U)
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#define MRCC_MRCC_DBG_TRACE_CLKDIV_UNSTAB_SHIFT (31U)
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/*! UNSTAB - Divider status flag
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* 0b0..Divider clock is stable
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* 0b1..Clock frequency isn't stable
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*/
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#define MRCC_MRCC_DBG_TRACE_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DBG_TRACE_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_DBG_TRACE_CLKDIV_UNSTAB_MASK)
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/*! @} */
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/*! @name MRCC_CLKOUT_CLKSEL - CLKOUT clock selection control */
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/*! @{ */
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#define MRCC_MRCC_CLKOUT_CLKSEL_MUX_MASK (0x7U)
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#define MRCC_MRCC_CLKOUT_CLKSEL_MUX_SHIFT (0U)
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/*! MUX - Functional Clock Mux Select
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* 0b110..clkroot_slow
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* 0b011..clkroot_16k
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* 0b010..clkroot_sosc
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* 0b001..clkroot_firc_div
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* 0b000..clkroot_12m
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*/
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#define MRCC_MRCC_CLKOUT_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CLKOUT_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_CLKOUT_CLKSEL_MUX_MASK)
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/*! @} */
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/*! @name MRCC_CLKOUT_CLKDIV - CLKOUT clock divider control */
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/*! @{ */
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#define MRCC_MRCC_CLKOUT_CLKDIV_DIV_MASK (0xFU)
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#define MRCC_MRCC_CLKOUT_CLKDIV_DIV_SHIFT (0U)
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/*! DIV - Functional Clock Divider */
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#define MRCC_MRCC_CLKOUT_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CLKOUT_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CLKOUT_CLKDIV_DIV_MASK)
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#define MRCC_MRCC_CLKOUT_CLKDIV_RESET_MASK (0x20000000U)
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#define MRCC_MRCC_CLKOUT_CLKDIV_RESET_SHIFT (29U)
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/*! RESET - Reset divider counter
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* 0b0..Divider isn't reset
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* 0b1..Divider is reset
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*/
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#define MRCC_MRCC_CLKOUT_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CLKOUT_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CLKOUT_CLKDIV_RESET_MASK)
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#define MRCC_MRCC_CLKOUT_CLKDIV_HALT_MASK (0x40000000U)
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#define MRCC_MRCC_CLKOUT_CLKDIV_HALT_SHIFT (30U)
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/*! HALT - Halt divider counter
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* 0b0..Divider clock is running
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* 0b1..Divider clock is stopped
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*/
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#define MRCC_MRCC_CLKOUT_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CLKOUT_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CLKOUT_CLKDIV_HALT_MASK)
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#define MRCC_MRCC_CLKOUT_CLKDIV_UNSTAB_MASK (0x80000000U)
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#define MRCC_MRCC_CLKOUT_CLKDIV_UNSTAB_SHIFT (31U)
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/*! UNSTAB - Divider status flag
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* 0b0..Divider clock is stable
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* 0b1..Clock frequency is not stable
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*/
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#define MRCC_MRCC_CLKOUT_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CLKOUT_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CLKOUT_CLKDIV_UNSTAB_MASK)
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/*! @} */
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/*! @name MRCC_SYSTICK_CLKSEL - SYSTICK clock selection control */
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/*! @{ */
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#define MRCC_MRCC_SYSTICK_CLKSEL_MUX_MASK (0x3U)
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#define MRCC_MRCC_SYSTICK_CLKSEL_MUX_SHIFT (0U)
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/*! MUX - Functional Clock Mux Select
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* 0b10..clkroot_16k
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* 0b01..clkroot_1m
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* 0b00..clkroot_cpu
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*/
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#define MRCC_MRCC_SYSTICK_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_SYSTICK_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_SYSTICK_CLKSEL_MUX_MASK)
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/*! @} */
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/*! @name MRCC_SYSTICK_CLKDIV - SYSTICK clock divider control */
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/*! @{ */
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#define MRCC_MRCC_SYSTICK_CLKDIV_DIV_MASK (0xFU)
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#define MRCC_MRCC_SYSTICK_CLKDIV_DIV_SHIFT (0U)
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/*! DIV - Functional Clock Divider */
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#define MRCC_MRCC_SYSTICK_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_SYSTICK_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_SYSTICK_CLKDIV_DIV_MASK)
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#define MRCC_MRCC_SYSTICK_CLKDIV_RESET_MASK (0x20000000U)
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#define MRCC_MRCC_SYSTICK_CLKDIV_RESET_SHIFT (29U)
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/*! RESET - Reset divider counter
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* 0b0..Divider isn't reset
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* 0b1..Divider is reset
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*/
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#define MRCC_MRCC_SYSTICK_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_SYSTICK_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_SYSTICK_CLKDIV_RESET_MASK)
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#define MRCC_MRCC_SYSTICK_CLKDIV_HALT_MASK (0x40000000U)
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#define MRCC_MRCC_SYSTICK_CLKDIV_HALT_SHIFT (30U)
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/*! HALT - Halt divider counter
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|
* 0b0..Divider clock is running
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* 0b1..Divider clock is stopped
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*/
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#define MRCC_MRCC_SYSTICK_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_SYSTICK_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_SYSTICK_CLKDIV_HALT_MASK)
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#define MRCC_MRCC_SYSTICK_CLKDIV_UNSTAB_MASK (0x80000000U)
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#define MRCC_MRCC_SYSTICK_CLKDIV_UNSTAB_SHIFT (31U)
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/*! UNSTAB - Divider status flag
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|
* 0b0..Divider clock is stable
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* 0b1..Clock frequency isn't stable
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|
*/
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#define MRCC_MRCC_SYSTICK_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_SYSTICK_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_SYSTICK_CLKDIV_UNSTAB_MASK)
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/*! @} */
|
|
|
|
/*! @name MRCC_FRO_HF_DIV_CLKDIV - FRO_HF_DIV clock divider control */
|
|
/*! @{ */
|
|
|
|
#define MRCC_MRCC_FRO_HF_DIV_CLKDIV_DIV_MASK (0xFU)
|
|
#define MRCC_MRCC_FRO_HF_DIV_CLKDIV_DIV_SHIFT (0U)
|
|
/*! DIV - Functional Clock Divider */
|
|
#define MRCC_MRCC_FRO_HF_DIV_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FRO_HF_DIV_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_FRO_HF_DIV_CLKDIV_DIV_MASK)
|
|
|
|
#define MRCC_MRCC_FRO_HF_DIV_CLKDIV_UNSTAB_MASK (0x80000000U)
|
|
#define MRCC_MRCC_FRO_HF_DIV_CLKDIV_UNSTAB_SHIFT (31U)
|
|
/*! UNSTAB - Divider status flag
|
|
* 0b0..Divider clock is stable
|
|
* 0b1..Clock frequency isn't stable
|
|
*/
|
|
#define MRCC_MRCC_FRO_HF_DIV_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FRO_HF_DIV_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_FRO_HF_DIV_CLKDIV_UNSTAB_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group MRCC_Register_Masks */
|
|
|
|
|
|
/* MRCC - Peripheral instance base addresses */
|
|
/** Peripheral MRCC0 base address */
|
|
#define MRCC0_BASE (0x40091000u)
|
|
/** Peripheral MRCC0 base pointer */
|
|
#define MRCC0 ((MRCC_Type *)MRCC0_BASE)
|
|
/** Array initializer of MRCC peripheral base addresses */
|
|
#define MRCC_BASE_ADDRS { MRCC0_BASE }
|
|
/** Array initializer of MRCC peripheral base pointers */
|
|
#define MRCC_BASE_PTRS { MRCC0 }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group MRCC_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- OSTIMER Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup OSTIMER_Peripheral_Access_Layer OSTIMER Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** OSTIMER - Register Layout Typedef */
|
|
typedef struct {
|
|
__I uint32_t EVTIMERL; /**< EVTIMER Low, offset: 0x0 */
|
|
__I uint32_t EVTIMERH; /**< EVTIMER High, offset: 0x4 */
|
|
__I uint32_t CAPTURE_L; /**< Local Capture Low for CPU, offset: 0x8 */
|
|
__I uint32_t CAPTURE_H; /**< Local Capture High for CPU, offset: 0xC */
|
|
__IO uint32_t MATCH_L; /**< Local Match Low for CPU, offset: 0x10 */
|
|
__IO uint32_t MATCH_H; /**< Local Match High for CPU, offset: 0x14 */
|
|
uint8_t RESERVED_0[4];
|
|
__IO uint32_t OSEVENT_CTRL; /**< OSTIMER Control for CPU, offset: 0x1C */
|
|
} OSTIMER_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- OSTIMER Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup OSTIMER_Register_Masks OSTIMER Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name EVTIMERL - EVTIMER Low */
|
|
/*! @{ */
|
|
|
|
#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU)
|
|
#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT (0U)
|
|
/*! EVTIMER_COUNT_VALUE - EVTimer Count Value */
|
|
#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name EVTIMERH - EVTIMER High */
|
|
/*! @{ */
|
|
|
|
#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0x3FFU)
|
|
#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT (0U)
|
|
/*! EVTIMER_COUNT_VALUE - EVTimer Count Value */
|
|
#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAPTURE_L - Local Capture Low for CPU */
|
|
/*! @{ */
|
|
|
|
#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK (0xFFFFFFFFU)
|
|
#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT (0U)
|
|
/*! CAPTURE_VALUE - EVTimer Capture Value */
|
|
#define OSTIMER_CAPTURE_L_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAPTURE_H - Local Capture High for CPU */
|
|
/*! @{ */
|
|
|
|
#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK (0x3FFU)
|
|
#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT (0U)
|
|
/*! CAPTURE_VALUE - EVTimer Capture Value */
|
|
#define OSTIMER_CAPTURE_H_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MATCH_L - Local Match Low for CPU */
|
|
/*! @{ */
|
|
|
|
#define OSTIMER_MATCH_L_MATCH_VALUE_MASK (0xFFFFFFFFU)
|
|
#define OSTIMER_MATCH_L_MATCH_VALUE_SHIFT (0U)
|
|
/*! MATCH_VALUE - EVTimer Match Value */
|
|
#define OSTIMER_MATCH_L_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_L_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_L_MATCH_VALUE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MATCH_H - Local Match High for CPU */
|
|
/*! @{ */
|
|
|
|
#define OSTIMER_MATCH_H_MATCH_VALUE_MASK (0x3FFU)
|
|
#define OSTIMER_MATCH_H_MATCH_VALUE_SHIFT (0U)
|
|
/*! MATCH_VALUE - EVTimer Match Value */
|
|
#define OSTIMER_MATCH_H_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_H_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_H_MATCH_VALUE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name OSEVENT_CTRL - OSTIMER Control for CPU */
|
|
/*! @{ */
|
|
|
|
#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK (0x1U)
|
|
#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT (0U)
|
|
/*! OSTIMER_INTRFLAG - Interrupt Flag */
|
|
#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK)
|
|
|
|
#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK (0x2U)
|
|
#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT (1U)
|
|
/*! OSTIMER_INTENA - Interrupt or Wake-Up Request
|
|
* 0b0..Interrupts blocked
|
|
* 0b1..Interrupts enabled
|
|
*/
|
|
#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK)
|
|
|
|
#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK (0x4U)
|
|
#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT (2U)
|
|
/*! MATCH_WR_RDY - EVTimer Match Write Ready */
|
|
#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT)) & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK)
|
|
|
|
#define OSTIMER_OSEVENT_CTRL_DEBUG_EN_MASK (0x8U)
|
|
#define OSTIMER_OSEVENT_CTRL_DEBUG_EN_SHIFT (3U)
|
|
/*! DEBUG_EN - Debug Enable
|
|
* 0b0..Disables
|
|
* 0b1..Enables
|
|
*/
|
|
#define OSTIMER_OSEVENT_CTRL_DEBUG_EN(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_DEBUG_EN_SHIFT)) & OSTIMER_OSEVENT_CTRL_DEBUG_EN_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group OSTIMER_Register_Masks */
|
|
|
|
|
|
/* OSTIMER - Peripheral instance base addresses */
|
|
/** Peripheral OSTIMER0 base address */
|
|
#define OSTIMER0_BASE (0x400AD000u)
|
|
/** Peripheral OSTIMER0 base pointer */
|
|
#define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE)
|
|
/** Array initializer of OSTIMER peripheral base addresses */
|
|
#define OSTIMER_BASE_ADDRS { OSTIMER0_BASE }
|
|
/** Array initializer of OSTIMER peripheral base pointers */
|
|
#define OSTIMER_BASE_PTRS { OSTIMER0 }
|
|
/** Interrupt vectors for the OSTIMER peripheral type */
|
|
#define OSTIMER_IRQS { OS_EVENT_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group OSTIMER_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- PORT Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** PORT - Register Layout Typedef */
|
|
typedef struct {
|
|
__I uint32_t VERID; /**< Version ID, offset: 0x0 */
|
|
uint8_t RESERVED_0[12];
|
|
__O uint32_t GPCLR; /**< Global Pin Control Low, offset: 0x10 */
|
|
__O uint32_t GPCHR; /**< Global Pin Control High, offset: 0x14 */
|
|
uint8_t RESERVED_1[8];
|
|
__IO uint32_t CONFIG; /**< Configuration, offset: 0x20 */
|
|
uint8_t RESERVED_2[60];
|
|
__IO uint32_t CALIB0; /**< Calibration 0, offset: 0x60, available only on: PORT1, PORT3 (missing on PORT0, PORT2) */
|
|
__IO uint32_t CALIB1; /**< Calibration 1, offset: 0x64, available only on: PORT1, PORT3 (missing on PORT0, PORT2) */
|
|
uint8_t RESERVED_3[24];
|
|
__IO uint32_t PCR[32]; /**< Pin Control 0..Pin Control 31, array offset: 0x80, array step: 0x4, irregular array, not all indices are valid */
|
|
} PORT_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- PORT Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup PORT_Register_Masks PORT Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name VERID - Version ID */
|
|
/*! @{ */
|
|
|
|
#define PORT_VERID_FEATURE_MASK (0xFFFFU)
|
|
#define PORT_VERID_FEATURE_SHIFT (0U)
|
|
/*! FEATURE - Feature Specification Number
|
|
* 0b0000000000000000..Basic implementation
|
|
*/
|
|
#define PORT_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << PORT_VERID_FEATURE_SHIFT)) & PORT_VERID_FEATURE_MASK)
|
|
|
|
#define PORT_VERID_MINOR_MASK (0xFF0000U)
|
|
#define PORT_VERID_MINOR_SHIFT (16U)
|
|
/*! MINOR - Minor Version Number */
|
|
#define PORT_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << PORT_VERID_MINOR_SHIFT)) & PORT_VERID_MINOR_MASK)
|
|
|
|
#define PORT_VERID_MAJOR_MASK (0xFF000000U)
|
|
#define PORT_VERID_MAJOR_SHIFT (24U)
|
|
/*! MAJOR - Major Version Number */
|
|
#define PORT_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << PORT_VERID_MAJOR_SHIFT)) & PORT_VERID_MAJOR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GPCLR - Global Pin Control Low */
|
|
/*! @{ */
|
|
|
|
#define PORT_GPCLR_GPWD_MASK (0xFFFFU)
|
|
#define PORT_GPCLR_GPWD_SHIFT (0U)
|
|
/*! GPWD - Global Pin Write Data */
|
|
#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
|
|
|
|
#define PORT_GPCLR_GPWE0_MASK (0x10000U)
|
|
#define PORT_GPCLR_GPWE0_SHIFT (16U)
|
|
/*! GPWE0 - Global Pin Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define PORT_GPCLR_GPWE0(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE0_SHIFT)) & PORT_GPCLR_GPWE0_MASK)
|
|
|
|
#define PORT_GPCLR_GPWE1_MASK (0x20000U)
|
|
#define PORT_GPCLR_GPWE1_SHIFT (17U)
|
|
/*! GPWE1 - Global Pin Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define PORT_GPCLR_GPWE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE1_SHIFT)) & PORT_GPCLR_GPWE1_MASK)
|
|
|
|
#define PORT_GPCLR_GPWE2_MASK (0x40000U)
|
|
#define PORT_GPCLR_GPWE2_SHIFT (18U)
|
|
/*! GPWE2 - Global Pin Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define PORT_GPCLR_GPWE2(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE2_SHIFT)) & PORT_GPCLR_GPWE2_MASK)
|
|
|
|
#define PORT_GPCLR_GPWE3_MASK (0x80000U)
|
|
#define PORT_GPCLR_GPWE3_SHIFT (19U)
|
|
/*! GPWE3 - Global Pin Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define PORT_GPCLR_GPWE3(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE3_SHIFT)) & PORT_GPCLR_GPWE3_MASK)
|
|
|
|
#define PORT_GPCLR_GPWE4_MASK (0x100000U)
|
|
#define PORT_GPCLR_GPWE4_SHIFT (20U)
|
|
/*! GPWE4 - Global Pin Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define PORT_GPCLR_GPWE4(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE4_SHIFT)) & PORT_GPCLR_GPWE4_MASK)
|
|
|
|
#define PORT_GPCLR_GPWE5_MASK (0x200000U)
|
|
#define PORT_GPCLR_GPWE5_SHIFT (21U)
|
|
/*! GPWE5 - Global Pin Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define PORT_GPCLR_GPWE5(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE5_SHIFT)) & PORT_GPCLR_GPWE5_MASK)
|
|
|
|
#define PORT_GPCLR_GPWE6_MASK (0x400000U)
|
|
#define PORT_GPCLR_GPWE6_SHIFT (22U)
|
|
/*! GPWE6 - Global Pin Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define PORT_GPCLR_GPWE6(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE6_SHIFT)) & PORT_GPCLR_GPWE6_MASK)
|
|
|
|
#define PORT_GPCLR_GPWE7_MASK (0x800000U)
|
|
#define PORT_GPCLR_GPWE7_SHIFT (23U)
|
|
/*! GPWE7 - Global Pin Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define PORT_GPCLR_GPWE7(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE7_SHIFT)) & PORT_GPCLR_GPWE7_MASK)
|
|
|
|
#define PORT_GPCLR_GPWE8_MASK (0x1000000U)
|
|
#define PORT_GPCLR_GPWE8_SHIFT (24U)
|
|
/*! GPWE8 - Global Pin Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define PORT_GPCLR_GPWE8(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE8_SHIFT)) & PORT_GPCLR_GPWE8_MASK)
|
|
|
|
#define PORT_GPCLR_GPWE9_MASK (0x2000000U)
|
|
#define PORT_GPCLR_GPWE9_SHIFT (25U)
|
|
/*! GPWE9 - Global Pin Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define PORT_GPCLR_GPWE9(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE9_SHIFT)) & PORT_GPCLR_GPWE9_MASK)
|
|
|
|
#define PORT_GPCLR_GPWE10_MASK (0x4000000U)
|
|
#define PORT_GPCLR_GPWE10_SHIFT (26U)
|
|
/*! GPWE10 - Global Pin Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define PORT_GPCLR_GPWE10(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE10_SHIFT)) & PORT_GPCLR_GPWE10_MASK)
|
|
|
|
#define PORT_GPCLR_GPWE11_MASK (0x8000000U)
|
|
#define PORT_GPCLR_GPWE11_SHIFT (27U)
|
|
/*! GPWE11 - Global Pin Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define PORT_GPCLR_GPWE11(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE11_SHIFT)) & PORT_GPCLR_GPWE11_MASK)
|
|
|
|
#define PORT_GPCLR_GPWE12_MASK (0x10000000U)
|
|
#define PORT_GPCLR_GPWE12_SHIFT (28U)
|
|
/*! GPWE12 - Global Pin Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define PORT_GPCLR_GPWE12(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE12_SHIFT)) & PORT_GPCLR_GPWE12_MASK)
|
|
|
|
#define PORT_GPCLR_GPWE13_MASK (0x20000000U)
|
|
#define PORT_GPCLR_GPWE13_SHIFT (29U)
|
|
/*! GPWE13 - Global Pin Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define PORT_GPCLR_GPWE13(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE13_SHIFT)) & PORT_GPCLR_GPWE13_MASK)
|
|
|
|
#define PORT_GPCLR_GPWE14_MASK (0x40000000U)
|
|
#define PORT_GPCLR_GPWE14_SHIFT (30U)
|
|
/*! GPWE14 - Global Pin Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define PORT_GPCLR_GPWE14(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE14_SHIFT)) & PORT_GPCLR_GPWE14_MASK)
|
|
|
|
#define PORT_GPCLR_GPWE15_MASK (0x80000000U)
|
|
#define PORT_GPCLR_GPWE15_SHIFT (31U)
|
|
/*! GPWE15 - Global Pin Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define PORT_GPCLR_GPWE15(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE15_SHIFT)) & PORT_GPCLR_GPWE15_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GPCHR - Global Pin Control High */
|
|
/*! @{ */
|
|
|
|
#define PORT_GPCHR_GPWD_MASK (0xFFFFU)
|
|
#define PORT_GPCHR_GPWD_SHIFT (0U)
|
|
/*! GPWD - Global Pin Write Data */
|
|
#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
|
|
|
|
#define PORT_GPCHR_GPWE16_MASK (0x10000U)
|
|
#define PORT_GPCHR_GPWE16_SHIFT (16U)
|
|
/*! GPWE16 - Global Pin Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define PORT_GPCHR_GPWE16(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE16_SHIFT)) & PORT_GPCHR_GPWE16_MASK)
|
|
|
|
#define PORT_GPCHR_GPWE17_MASK (0x20000U)
|
|
#define PORT_GPCHR_GPWE17_SHIFT (17U)
|
|
/*! GPWE17 - Global Pin Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define PORT_GPCHR_GPWE17(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE17_SHIFT)) & PORT_GPCHR_GPWE17_MASK)
|
|
|
|
#define PORT_GPCHR_GPWE18_MASK (0x40000U)
|
|
#define PORT_GPCHR_GPWE18_SHIFT (18U)
|
|
/*! GPWE18 - Global Pin Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define PORT_GPCHR_GPWE18(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE18_SHIFT)) & PORT_GPCHR_GPWE18_MASK)
|
|
|
|
#define PORT_GPCHR_GPWE19_MASK (0x80000U)
|
|
#define PORT_GPCHR_GPWE19_SHIFT (19U)
|
|
/*! GPWE19 - Global Pin Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define PORT_GPCHR_GPWE19(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE19_SHIFT)) & PORT_GPCHR_GPWE19_MASK)
|
|
|
|
#define PORT_GPCHR_GPWE20_MASK (0x100000U)
|
|
#define PORT_GPCHR_GPWE20_SHIFT (20U)
|
|
/*! GPWE20 - Global Pin Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define PORT_GPCHR_GPWE20(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE20_SHIFT)) & PORT_GPCHR_GPWE20_MASK)
|
|
|
|
#define PORT_GPCHR_GPWE21_MASK (0x200000U)
|
|
#define PORT_GPCHR_GPWE21_SHIFT (21U)
|
|
/*! GPWE21 - Global Pin Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define PORT_GPCHR_GPWE21(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE21_SHIFT)) & PORT_GPCHR_GPWE21_MASK)
|
|
|
|
#define PORT_GPCHR_GPWE22_MASK (0x400000U)
|
|
#define PORT_GPCHR_GPWE22_SHIFT (22U)
|
|
/*! GPWE22 - Global Pin Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define PORT_GPCHR_GPWE22(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE22_SHIFT)) & PORT_GPCHR_GPWE22_MASK)
|
|
|
|
#define PORT_GPCHR_GPWE23_MASK (0x800000U)
|
|
#define PORT_GPCHR_GPWE23_SHIFT (23U)
|
|
/*! GPWE23 - Global Pin Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define PORT_GPCHR_GPWE23(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE23_SHIFT)) & PORT_GPCHR_GPWE23_MASK)
|
|
|
|
#define PORT_GPCHR_GPWE24_MASK (0x1000000U)
|
|
#define PORT_GPCHR_GPWE24_SHIFT (24U)
|
|
/*! GPWE24 - Global Pin Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define PORT_GPCHR_GPWE24(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE24_SHIFT)) & PORT_GPCHR_GPWE24_MASK)
|
|
|
|
#define PORT_GPCHR_GPWE25_MASK (0x2000000U)
|
|
#define PORT_GPCHR_GPWE25_SHIFT (25U)
|
|
/*! GPWE25 - Global Pin Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define PORT_GPCHR_GPWE25(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE25_SHIFT)) & PORT_GPCHR_GPWE25_MASK)
|
|
|
|
#define PORT_GPCHR_GPWE26_MASK (0x4000000U)
|
|
#define PORT_GPCHR_GPWE26_SHIFT (26U)
|
|
/*! GPWE26 - Global Pin Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define PORT_GPCHR_GPWE26(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE26_SHIFT)) & PORT_GPCHR_GPWE26_MASK)
|
|
|
|
#define PORT_GPCHR_GPWE27_MASK (0x8000000U)
|
|
#define PORT_GPCHR_GPWE27_SHIFT (27U)
|
|
/*! GPWE27 - Global Pin Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define PORT_GPCHR_GPWE27(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE27_SHIFT)) & PORT_GPCHR_GPWE27_MASK)
|
|
|
|
#define PORT_GPCHR_GPWE28_MASK (0x10000000U)
|
|
#define PORT_GPCHR_GPWE28_SHIFT (28U)
|
|
/*! GPWE28 - Global Pin Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define PORT_GPCHR_GPWE28(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE28_SHIFT)) & PORT_GPCHR_GPWE28_MASK)
|
|
|
|
#define PORT_GPCHR_GPWE29_MASK (0x20000000U)
|
|
#define PORT_GPCHR_GPWE29_SHIFT (29U)
|
|
/*! GPWE29 - Global Pin Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define PORT_GPCHR_GPWE29(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE29_SHIFT)) & PORT_GPCHR_GPWE29_MASK)
|
|
|
|
#define PORT_GPCHR_GPWE30_MASK (0x40000000U)
|
|
#define PORT_GPCHR_GPWE30_SHIFT (30U)
|
|
/*! GPWE30 - Global Pin Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define PORT_GPCHR_GPWE30(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE30_SHIFT)) & PORT_GPCHR_GPWE30_MASK)
|
|
|
|
#define PORT_GPCHR_GPWE31_MASK (0x80000000U)
|
|
#define PORT_GPCHR_GPWE31_SHIFT (31U)
|
|
/*! GPWE31 - Global Pin Write Enable
|
|
* 0b0..Not updated
|
|
* 0b1..Updated
|
|
*/
|
|
#define PORT_GPCHR_GPWE31(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE31_SHIFT)) & PORT_GPCHR_GPWE31_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CONFIG - Configuration */
|
|
/*! @{ */
|
|
|
|
#define PORT_CONFIG_RANGE_MASK (0x1U)
|
|
#define PORT_CONFIG_RANGE_SHIFT (0U)
|
|
/*! RANGE - Port Voltage Range
|
|
* 0b0..1.71 V-3.6 V
|
|
* 0b1..2.70 V-3.6 V
|
|
*/
|
|
#define PORT_CONFIG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << PORT_CONFIG_RANGE_SHIFT)) & PORT_CONFIG_RANGE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CALIB0 - Calibration 0 */
|
|
/*! @{ */
|
|
|
|
#define PORT_CALIB0_NCAL_MASK (0x3FU)
|
|
#define PORT_CALIB0_NCAL_SHIFT (0U)
|
|
/*! NCAL - Calibration of NMOS Output Driver */
|
|
#define PORT_CALIB0_NCAL(x) (((uint32_t)(((uint32_t)(x)) << PORT_CALIB0_NCAL_SHIFT)) & PORT_CALIB0_NCAL_MASK)
|
|
|
|
#define PORT_CALIB0_PCAL_MASK (0x3F0000U)
|
|
#define PORT_CALIB0_PCAL_SHIFT (16U)
|
|
/*! PCAL - Calibration of PMOS Output Driver */
|
|
#define PORT_CALIB0_PCAL(x) (((uint32_t)(((uint32_t)(x)) << PORT_CALIB0_PCAL_SHIFT)) & PORT_CALIB0_PCAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CALIB1 - Calibration 1 */
|
|
/*! @{ */
|
|
|
|
#define PORT_CALIB1_NCAL_MASK (0x3FU)
|
|
#define PORT_CALIB1_NCAL_SHIFT (0U)
|
|
/*! NCAL - Calibration of NMOS Output Driver */
|
|
#define PORT_CALIB1_NCAL(x) (((uint32_t)(((uint32_t)(x)) << PORT_CALIB1_NCAL_SHIFT)) & PORT_CALIB1_NCAL_MASK)
|
|
|
|
#define PORT_CALIB1_PCAL_MASK (0x3F0000U)
|
|
#define PORT_CALIB1_PCAL_SHIFT (16U)
|
|
/*! PCAL - Calibration of PMOS Output Driver */
|
|
#define PORT_CALIB1_PCAL(x) (((uint32_t)(((uint32_t)(x)) << PORT_CALIB1_PCAL_SHIFT)) & PORT_CALIB1_PCAL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PCR - Pin Control 0..Pin Control 31 */
|
|
/*! @{ */
|
|
|
|
#define PORT_PCR_PS_MASK (0x1U)
|
|
#define PORT_PCR_PS_SHIFT (0U)
|
|
/*! PS - Pull Select
|
|
* 0b0..Enables internal pulldown resistor
|
|
* 0b1..Enables internal pullup resistor
|
|
*/
|
|
#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
|
|
|
|
#define PORT_PCR_PE_MASK (0x2U)
|
|
#define PORT_PCR_PE_SHIFT (1U)
|
|
/*! PE - Pull Enable
|
|
* 0b0..Disables
|
|
* 0b1..Enables
|
|
*/
|
|
#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
|
|
|
|
#define PORT_PCR_PV_MASK (0x4U)
|
|
#define PORT_PCR_PV_SHIFT (2U)
|
|
/*! PV - Pull Value
|
|
* 0b0..Low
|
|
* 0b1..High
|
|
*/
|
|
#define PORT_PCR_PV(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PV_SHIFT)) & PORT_PCR_PV_MASK)
|
|
|
|
#define PORT_PCR_SRE_MASK (0x8U)
|
|
#define PORT_PCR_SRE_SHIFT (3U)
|
|
/*! SRE - Slew Rate Enable
|
|
* 0b0..Fast
|
|
* 0b1..Slow
|
|
*/
|
|
#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
|
|
|
|
#define PORT_PCR_PFE_MASK (0x10U)
|
|
#define PORT_PCR_PFE_SHIFT (4U)
|
|
/*! PFE - Passive Filter Enable
|
|
* 0b0..Disables
|
|
* 0b1..Enables
|
|
*/
|
|
#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
|
|
|
|
#define PORT_PCR_ODE_MASK (0x20U)
|
|
#define PORT_PCR_ODE_SHIFT (5U)
|
|
/*! ODE - Open Drain Enable
|
|
* 0b0..Disables
|
|
* 0b1..Enables
|
|
*/
|
|
#define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)
|
|
|
|
#define PORT_PCR_DSE_MASK (0x40U)
|
|
#define PORT_PCR_DSE_SHIFT (6U)
|
|
/*! DSE - Drive Strength Enable
|
|
* 0b0..Low
|
|
* 0b1..High
|
|
*/
|
|
#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
|
|
|
|
#define PORT_PCR_DSE1_MASK (0x80U)
|
|
#define PORT_PCR_DSE1_SHIFT (7U)
|
|
/*! DSE1 - Drive Strength Enable
|
|
* 0b0..Normal
|
|
* 0b1..Double
|
|
*/
|
|
#define PORT_PCR_DSE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE1_SHIFT)) & PORT_PCR_DSE1_MASK)
|
|
|
|
#define PORT_PCR_MUX_MASK (0xF00U) /* Merged from fields with different position or width, of widths (2, 3, 4), largest definition used */
|
|
#define PORT_PCR_MUX_SHIFT (8U)
|
|
/*! MUX - Pin Multiplex Control
|
|
* 0b0000..Alternative 0 (GPIO)
|
|
* 0b0001..Alternative 1 (chip-specific)
|
|
* 0b0010..Alternative 2 (chip-specific)
|
|
* 0b0011..Alternative 3 (chip-specific)
|
|
* 0b0100..Alternative 4 (chip-specific)
|
|
* 0b0101..Alternative 5 (chip-specific)
|
|
* 0b0110..Alternative 6 (chip-specific)
|
|
* 0b0111..Alternative 7 (chip-specific)
|
|
* 0b1000..Alternative 8 (chip-specific)
|
|
* 0b1001..Alternative 9 (chip-specific)
|
|
* 0b1010..Alternative 10 (chip-specific)
|
|
* 0b1011..Alternative 11 (chip-specific)
|
|
* 0b1100..Alternative 12 (chip-specific)
|
|
* 0b1101..Alternative 13 (chip-specific)
|
|
*/
|
|
#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK) /* Merged from fields with different position or width, of widths (2, 3, 4), largest definition used */
|
|
|
|
#define PORT_PCR_IBE_MASK (0x1000U)
|
|
#define PORT_PCR_IBE_SHIFT (12U)
|
|
/*! IBE - Input Buffer Enable
|
|
* 0b0..Disables
|
|
* 0b1..Enables
|
|
*/
|
|
#define PORT_PCR_IBE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IBE_SHIFT)) & PORT_PCR_IBE_MASK)
|
|
|
|
#define PORT_PCR_INV_MASK (0x2000U)
|
|
#define PORT_PCR_INV_SHIFT (13U)
|
|
/*! INV - Invert Input
|
|
* 0b0..Does not invert
|
|
* 0b1..Inverts
|
|
*/
|
|
#define PORT_PCR_INV(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_INV_SHIFT)) & PORT_PCR_INV_MASK)
|
|
|
|
#define PORT_PCR_LK_MASK (0x8000U)
|
|
#define PORT_PCR_LK_SHIFT (15U)
|
|
/*! LK - Lock Register
|
|
* 0b0..Does not lock
|
|
* 0b1..Locks
|
|
*/
|
|
#define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PORT_PCR */
|
|
#define PORT_PCR_COUNT (32U)
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group PORT_Register_Masks */
|
|
|
|
|
|
/* PORT - Peripheral instance base addresses */
|
|
/** Peripheral PORT0 base address */
|
|
#define PORT0_BASE (0x400BC000u)
|
|
/** Peripheral PORT0 base pointer */
|
|
#define PORT0 ((PORT_Type *)PORT0_BASE)
|
|
/** Peripheral PORT1 base address */
|
|
#define PORT1_BASE (0x400BD000u)
|
|
/** Peripheral PORT1 base pointer */
|
|
#define PORT1 ((PORT_Type *)PORT1_BASE)
|
|
/** Peripheral PORT2 base address */
|
|
#define PORT2_BASE (0x400BE000u)
|
|
/** Peripheral PORT2 base pointer */
|
|
#define PORT2 ((PORT_Type *)PORT2_BASE)
|
|
/** Peripheral PORT3 base address */
|
|
#define PORT3_BASE (0x400BF000u)
|
|
/** Peripheral PORT3 base pointer */
|
|
#define PORT3 ((PORT_Type *)PORT3_BASE)
|
|
/** Array initializer of PORT peripheral base addresses */
|
|
#define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE }
|
|
/** Array initializer of PORT peripheral base pointers */
|
|
#define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3 }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group PORT_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- PWM Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** PWM - Register Layout Typedef */
|
|
typedef struct {
|
|
struct { /* offset: 0x0, array step: 0x60 */
|
|
__I uint16_t CNT; /**< Counter Register, array offset: 0x0, array step: 0x60 */
|
|
__IO uint16_t INIT; /**< Initial Count Register, array offset: 0x2, array step: 0x60 */
|
|
__IO uint16_t CTRL2; /**< Control 2 Register, array offset: 0x4, array step: 0x60 */
|
|
__IO uint16_t CTRL; /**< Control Register, array offset: 0x6, array step: 0x60 */
|
|
uint8_t RESERVED_0[2];
|
|
__IO uint16_t VAL0; /**< Value Register 0, array offset: 0xA, array step: 0x60 */
|
|
uint8_t RESERVED_1[2];
|
|
__IO uint16_t VAL1; /**< Value Register 1, array offset: 0xE, array step: 0x60 */
|
|
uint8_t RESERVED_2[2];
|
|
__IO uint16_t VAL2; /**< Value Register 2, array offset: 0x12, array step: 0x60 */
|
|
uint8_t RESERVED_3[2];
|
|
__IO uint16_t VAL3; /**< Value Register 3, array offset: 0x16, array step: 0x60 */
|
|
uint8_t RESERVED_4[2];
|
|
__IO uint16_t VAL4; /**< Value Register 4, array offset: 0x1A, array step: 0x60 */
|
|
uint8_t RESERVED_5[2];
|
|
__IO uint16_t VAL5; /**< Value Register 5, array offset: 0x1E, array step: 0x60 */
|
|
uint8_t RESERVED_6[2];
|
|
__IO uint16_t OCTRL; /**< Output Control Register, array offset: 0x22, array step: 0x60 */
|
|
__IO uint16_t STS; /**< Status Register, array offset: 0x24, array step: 0x60 */
|
|
__IO uint16_t INTEN; /**< Interrupt Enable Register, array offset: 0x26, array step: 0x60 */
|
|
__IO uint16_t DMAEN; /**< DMA Enable Register, array offset: 0x28, array step: 0x60 */
|
|
__IO uint16_t TCTRL; /**< Output Trigger Control Register, array offset: 0x2A, array step: 0x60 */
|
|
__IO uint16_t DISMAP[1]; /**< Fault Disable Mapping Register 0, array offset: 0x2C, array step: index*0x60, index2*0x2 */
|
|
uint8_t RESERVED_7[2];
|
|
__IO uint16_t DTCNT0; /**< Deadtime Count Register 0, array offset: 0x30, array step: 0x60 */
|
|
__IO uint16_t DTCNT1; /**< Deadtime Count Register 1, array offset: 0x32, array step: 0x60 */
|
|
uint8_t RESERVED_8[8];
|
|
__IO uint16_t CAPTCTRLX; /**< Capture Control X Register, array offset: 0x3C, array step: 0x60 */
|
|
__IO uint16_t CAPTCOMPX; /**< Capture Compare X Register, array offset: 0x3E, array step: 0x60 */
|
|
__I uint16_t CVAL0; /**< Capture Value 0 Register, array offset: 0x40, array step: 0x60 */
|
|
__I uint16_t CVAL0CYC; /**< Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60 */
|
|
__I uint16_t CVAL1; /**< Capture Value 1 Register, array offset: 0x44, array step: 0x60 */
|
|
__I uint16_t CVAL1CYC; /**< Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60 */
|
|
uint8_t RESERVED_9[16];
|
|
__IO uint16_t PHASEDLY; /**< Phase Delay Register, array offset: 0x58, array step: 0x60, valid indices: [1-2] */
|
|
uint8_t RESERVED_10[4];
|
|
__IO uint16_t CAPTFILTX; /**< Capture PWM_X Input Filter Register, array offset: 0x5E, array step: 0x60 */
|
|
} SM[3];
|
|
uint8_t RESERVED_0[96];
|
|
__IO uint16_t OUTEN; /**< Output Enable Register, offset: 0x180 */
|
|
__IO uint16_t MASK; /**< Mask Register, offset: 0x182 */
|
|
__IO uint16_t SWCOUT; /**< Software Controlled Output Register, offset: 0x184 */
|
|
__IO uint16_t DTSRCSEL; /**< PWM Source Select Register, offset: 0x186 */
|
|
__IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */
|
|
__IO uint16_t MCTRL2; /**< Master Control 2 Register, offset: 0x18A */
|
|
__IO uint16_t FCTRL; /**< Fault Control Register, offset: 0x18C */
|
|
__IO uint16_t FSTS; /**< Fault Status Register, offset: 0x18E */
|
|
__IO uint16_t FFILT; /**< Fault Filter Register, offset: 0x190 */
|
|
__IO uint16_t FTST; /**< Fault Test Register, offset: 0x192 */
|
|
__IO uint16_t FCTRL2; /**< Fault Control 2 Register, offset: 0x194 */
|
|
} PWM_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- PWM Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup PWM_Register_Masks PWM Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name CNT - Counter Register */
|
|
/*! @{ */
|
|
|
|
#define PWM_CNT_CNT_MASK (0xFFFFU)
|
|
#define PWM_CNT_CNT_SHIFT (0U)
|
|
/*! CNT - Counter Register Bits */
|
|
#define PWM_CNT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_CNT */
|
|
#define PWM_CNT_COUNT (3U)
|
|
|
|
/*! @name INIT - Initial Count Register */
|
|
/*! @{ */
|
|
|
|
#define PWM_INIT_INIT_MASK (0xFFFFU)
|
|
#define PWM_INIT_INIT_SHIFT (0U)
|
|
/*! INIT - Initial Count Register Bits */
|
|
#define PWM_INIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_INIT */
|
|
#define PWM_INIT_COUNT (3U)
|
|
|
|
/*! @name CTRL2 - Control 2 Register */
|
|
/*! @{ */
|
|
|
|
#define PWM_CTRL2_CLK_SEL_MASK (0x3U)
|
|
#define PWM_CTRL2_CLK_SEL_SHIFT (0U)
|
|
/*! CLK_SEL - Clock Source Select
|
|
* 0b00..The IPBus clock is used as the clock for the local prescaler and counter.
|
|
* 0b01..EXT_CLK is used as the clock for the local prescaler and counter.
|
|
* 0b10..Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This
|
|
* setting should not be used in submodule 0 as it forces the clock to logic 0.
|
|
* 0b11..Reserved
|
|
*/
|
|
#define PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)
|
|
|
|
#define PWM_CTRL2_RELOAD_SEL_MASK (0x4U)
|
|
#define PWM_CTRL2_RELOAD_SEL_SHIFT (2U)
|
|
/*! RELOAD_SEL - Reload Source Select
|
|
* 0b0..The local RELOAD signal is used to reload registers.
|
|
* 0b1..The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used
|
|
* in submodule 0 as it forces the RELOAD signal to logic 0.
|
|
*/
|
|
#define PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)
|
|
|
|
#define PWM_CTRL2_FORCE_SEL_MASK (0x38U)
|
|
#define PWM_CTRL2_FORCE_SEL_SHIFT (3U)
|
|
/*! FORCE_SEL - Force Select
|
|
* 0b000..The local force signal, CTRL2[FORCE], from this submodule is used to force updates.
|
|
* 0b001..The master force signal from submodule 0 is used to force updates. This setting should not be used in
|
|
* submodule 0 as it holds the FORCE OUTPUT signal to logic 0.
|
|
* 0b010..The local reload signal from this submodule is used to force updates without regard to the state of LDOK.
|
|
* 0b011..The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should
|
|
* not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0.
|
|
* 0b100..The local sync signal from this submodule is used to force updates.
|
|
* 0b101..The master sync signal from submodule0 is used to force updates. This setting should not be used in
|
|
* submodule0 as it holds the FORCE OUTPUT signal to logic 0.
|
|
* 0b110..The external force signal, EXT_FORCE, from outside the PWM module causes updates.
|
|
* 0b111..The external sync signal, EXT_SYNC, from outside the PWM module causes updates.
|
|
*/
|
|
#define PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)
|
|
|
|
#define PWM_CTRL2_FORCE_MASK (0x40U)
|
|
#define PWM_CTRL2_FORCE_SHIFT (6U)
|
|
/*! FORCE - Force Initialization */
|
|
#define PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK)
|
|
|
|
#define PWM_CTRL2_FRCEN_MASK (0x80U)
|
|
#define PWM_CTRL2_FRCEN_SHIFT (7U)
|
|
/*! FRCEN - Force Enable
|
|
* 0b0..Initialization from a FORCE_OUT is disabled.
|
|
* 0b1..Initialization from a FORCE_OUT is enabled.
|
|
*/
|
|
#define PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)
|
|
|
|
#define PWM_CTRL2_INIT_SEL_MASK (0x300U)
|
|
#define PWM_CTRL2_INIT_SEL_SHIFT (8U)
|
|
/*! INIT_SEL - Initialization Control Select
|
|
* 0b00..Local sync (PWM_X) causes initialization.
|
|
* 0b01..Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as
|
|
* it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload
|
|
* occurs.
|
|
* 0b10..Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0.
|
|
* 0b11..EXT_SYNC causes initialization.
|
|
*/
|
|
#define PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)
|
|
|
|
#define PWM_CTRL2_PWMX_INIT_MASK (0x400U)
|
|
#define PWM_CTRL2_PWMX_INIT_SHIFT (10U)
|
|
/*! PWMX_INIT - PWM_X Initial Value */
|
|
#define PWM_CTRL2_PWMX_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK)
|
|
|
|
#define PWM_CTRL2_PWM45_INIT_MASK (0x800U)
|
|
#define PWM_CTRL2_PWM45_INIT_SHIFT (11U)
|
|
/*! PWM45_INIT - PWM45 Initial Value */
|
|
#define PWM_CTRL2_PWM45_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK)
|
|
|
|
#define PWM_CTRL2_PWM23_INIT_MASK (0x1000U)
|
|
#define PWM_CTRL2_PWM23_INIT_SHIFT (12U)
|
|
/*! PWM23_INIT - PWM23 Initial Value */
|
|
#define PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK)
|
|
|
|
#define PWM_CTRL2_INDEP_MASK (0x2000U)
|
|
#define PWM_CTRL2_INDEP_SHIFT (13U)
|
|
/*! INDEP - Independent or Complementary Pair Operation
|
|
* 0b0..PWM_A and PWM_B form a complementary PWM pair.
|
|
* 0b1..PWM_A and PWM_B outputs are independent PWMs.
|
|
*/
|
|
#define PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)
|
|
|
|
#define PWM_CTRL2_DBGEN_MASK (0x8000U)
|
|
#define PWM_CTRL2_DBGEN_SHIFT (15U)
|
|
/*! DBGEN - Debug Enable */
|
|
#define PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_CTRL2 */
|
|
#define PWM_CTRL2_COUNT (3U)
|
|
|
|
/*! @name CTRL - Control Register */
|
|
/*! @{ */
|
|
|
|
#define PWM_CTRL_DBLEN_MASK (0x1U)
|
|
#define PWM_CTRL_DBLEN_SHIFT (0U)
|
|
/*! DBLEN - Double Switching Enable
|
|
* 0b0..Double switching disabled.
|
|
* 0b1..Double switching enabled.
|
|
*/
|
|
#define PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)
|
|
|
|
#define PWM_CTRL_DBLX_MASK (0x2U)
|
|
#define PWM_CTRL_DBLX_SHIFT (1U)
|
|
/*! DBLX - PWM_X Double Switching Enable
|
|
* 0b0..PWM_X double pulse disabled.
|
|
* 0b1..PWM_X double pulse enabled.
|
|
*/
|
|
#define PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)
|
|
|
|
#define PWM_CTRL_LDMOD_MASK (0x4U)
|
|
#define PWM_CTRL_LDMOD_SHIFT (2U)
|
|
/*! LDMOD - Load Mode Select
|
|
* 0b0..Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set.
|
|
* 0b1..Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set.
|
|
* In this case, it is not necessary to set CTRL[FULL] or CTRL[HALF].
|
|
*/
|
|
#define PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)
|
|
|
|
#define PWM_CTRL_SPLIT_MASK (0x8U)
|
|
#define PWM_CTRL_SPLIT_SHIFT (3U)
|
|
/*! SPLIT - Split the DBLPWM signal to PWM_A and PWM_B
|
|
* 0b0..DBLPWM is not split. PWM_A and PWM_B each have double pulses.
|
|
* 0b1..DBLPWM is split to PWM_A and PWM_B.
|
|
*/
|
|
#define PWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK)
|
|
|
|
#define PWM_CTRL_PRSC_MASK (0x70U)
|
|
#define PWM_CTRL_PRSC_SHIFT (4U)
|
|
/*! PRSC - Prescaler
|
|
* 0b000..Prescaler 1
|
|
* 0b001..Prescaler 2
|
|
* 0b010..Prescaler 4
|
|
* 0b011..Prescaler 8
|
|
* 0b100..Prescaler 16
|
|
* 0b101..Prescaler 32
|
|
* 0b110..Prescaler 64
|
|
* 0b111..Prescaler 128
|
|
*/
|
|
#define PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)
|
|
|
|
#define PWM_CTRL_COMPMODE_MASK (0x80U)
|
|
#define PWM_CTRL_COMPMODE_SHIFT (7U)
|
|
/*! COMPMODE - Compare Mode
|
|
* 0b0..The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges
|
|
* are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A
|
|
* output that is high at the end of a period maintains this state until a match with VAL3 clears the output
|
|
* in the following period.
|
|
* 0b1..The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This
|
|
* means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register
|
|
* values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the
|
|
* next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value.
|
|
*/
|
|
#define PWM_CTRL_COMPMODE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK)
|
|
|
|
#define PWM_CTRL_DT_MASK (0x300U)
|
|
#define PWM_CTRL_DT_SHIFT (8U)
|
|
/*! DT - Deadtime */
|
|
#define PWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)
|
|
|
|
#define PWM_CTRL_FULL_MASK (0x400U)
|
|
#define PWM_CTRL_FULL_SHIFT (10U)
|
|
/*! FULL - Full Cycle Reload
|
|
* 0b0..Full-cycle reloads disabled.
|
|
* 0b1..Full-cycle reloads enabled.
|
|
*/
|
|
#define PWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)
|
|
|
|
#define PWM_CTRL_HALF_MASK (0x800U)
|
|
#define PWM_CTRL_HALF_SHIFT (11U)
|
|
/*! HALF - Half Cycle Reload
|
|
* 0b0..Half-cycle reloads disabled.
|
|
* 0b1..Half-cycle reloads enabled.
|
|
*/
|
|
#define PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)
|
|
|
|
#define PWM_CTRL_LDFQ_MASK (0xF000U)
|
|
#define PWM_CTRL_LDFQ_SHIFT (12U)
|
|
/*! LDFQ - Load Frequency
|
|
* 0b0000..Every PWM opportunity
|
|
* 0b0001..Every 2 PWM opportunities
|
|
* 0b0010..Every 3 PWM opportunities
|
|
* 0b0011..Every 4 PWM opportunities
|
|
* 0b0100..Every 5 PWM opportunities
|
|
* 0b0101..Every 6 PWM opportunities
|
|
* 0b0110..Every 7 PWM opportunities
|
|
* 0b0111..Every 8 PWM opportunities
|
|
* 0b1000..Every 9 PWM opportunities
|
|
* 0b1001..Every 10 PWM opportunities
|
|
* 0b1010..Every 11 PWM opportunities
|
|
* 0b1011..Every 12 PWM opportunities
|
|
* 0b1100..Every 13 PWM opportunities
|
|
* 0b1101..Every 14 PWM opportunities
|
|
* 0b1110..Every 15 PWM opportunities
|
|
* 0b1111..Every 16 PWM opportunities
|
|
*/
|
|
#define PWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_CTRL */
|
|
#define PWM_CTRL_COUNT (3U)
|
|
|
|
/*! @name VAL0 - Value Register 0 */
|
|
/*! @{ */
|
|
|
|
#define PWM_VAL0_VAL0_MASK (0xFFFFU)
|
|
#define PWM_VAL0_VAL0_SHIFT (0U)
|
|
/*! VAL0 - Value 0 */
|
|
#define PWM_VAL0_VAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_VAL0 */
|
|
#define PWM_VAL0_COUNT (3U)
|
|
|
|
/*! @name VAL1 - Value Register 1 */
|
|
/*! @{ */
|
|
|
|
#define PWM_VAL1_VAL1_MASK (0xFFFFU)
|
|
#define PWM_VAL1_VAL1_SHIFT (0U)
|
|
/*! VAL1 - Value 1 */
|
|
#define PWM_VAL1_VAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_VAL1 */
|
|
#define PWM_VAL1_COUNT (3U)
|
|
|
|
/*! @name VAL2 - Value Register 2 */
|
|
/*! @{ */
|
|
|
|
#define PWM_VAL2_VAL2_MASK (0xFFFFU)
|
|
#define PWM_VAL2_VAL2_SHIFT (0U)
|
|
/*! VAL2 - Value 2 */
|
|
#define PWM_VAL2_VAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_VAL2 */
|
|
#define PWM_VAL2_COUNT (3U)
|
|
|
|
/*! @name VAL3 - Value Register 3 */
|
|
/*! @{ */
|
|
|
|
#define PWM_VAL3_VAL3_MASK (0xFFFFU)
|
|
#define PWM_VAL3_VAL3_SHIFT (0U)
|
|
/*! VAL3 - Value 3 */
|
|
#define PWM_VAL3_VAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_VAL3 */
|
|
#define PWM_VAL3_COUNT (3U)
|
|
|
|
/*! @name VAL4 - Value Register 4 */
|
|
/*! @{ */
|
|
|
|
#define PWM_VAL4_VAL4_MASK (0xFFFFU)
|
|
#define PWM_VAL4_VAL4_SHIFT (0U)
|
|
/*! VAL4 - Value 4 */
|
|
#define PWM_VAL4_VAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_VAL4 */
|
|
#define PWM_VAL4_COUNT (3U)
|
|
|
|
/*! @name VAL5 - Value Register 5 */
|
|
/*! @{ */
|
|
|
|
#define PWM_VAL5_VAL5_MASK (0xFFFFU)
|
|
#define PWM_VAL5_VAL5_SHIFT (0U)
|
|
/*! VAL5 - Value 5 */
|
|
#define PWM_VAL5_VAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_VAL5 */
|
|
#define PWM_VAL5_COUNT (3U)
|
|
|
|
/*! @name OCTRL - Output Control Register */
|
|
/*! @{ */
|
|
|
|
#define PWM_OCTRL_PWMXFS_MASK (0x3U)
|
|
#define PWM_OCTRL_PWMXFS_SHIFT (0U)
|
|
/*! PWMXFS - PWM_X Fault State
|
|
* 0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
|
|
* 0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
|
|
* 0b10, 0b11..Output is put in a high-impedance state.
|
|
*/
|
|
#define PWM_OCTRL_PWMXFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK)
|
|
|
|
#define PWM_OCTRL_PWMBFS_MASK (0xCU)
|
|
#define PWM_OCTRL_PWMBFS_SHIFT (2U)
|
|
/*! PWMBFS - PWM_B Fault State
|
|
* 0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
|
|
* 0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
|
|
* 0b10, 0b11..Output is put in a high-impedance state.
|
|
*/
|
|
#define PWM_OCTRL_PWMBFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK)
|
|
|
|
#define PWM_OCTRL_PWMAFS_MASK (0x30U)
|
|
#define PWM_OCTRL_PWMAFS_SHIFT (4U)
|
|
/*! PWMAFS - PWM_A Fault State
|
|
* 0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
|
|
* 0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
|
|
* 0b10, 0b11..Output is put in a high-impedance state.
|
|
*/
|
|
#define PWM_OCTRL_PWMAFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK)
|
|
|
|
#define PWM_OCTRL_POLX_MASK (0x100U)
|
|
#define PWM_OCTRL_POLX_SHIFT (8U)
|
|
/*! POLX - PWM_X Output Polarity
|
|
* 0b0..PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state.
|
|
* 0b1..PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state.
|
|
*/
|
|
#define PWM_OCTRL_POLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK)
|
|
|
|
#define PWM_OCTRL_POLB_MASK (0x200U)
|
|
#define PWM_OCTRL_POLB_SHIFT (9U)
|
|
/*! POLB - PWM_B Output Polarity
|
|
* 0b0..PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state.
|
|
* 0b1..PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state.
|
|
*/
|
|
#define PWM_OCTRL_POLB(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK)
|
|
|
|
#define PWM_OCTRL_POLA_MASK (0x400U)
|
|
#define PWM_OCTRL_POLA_SHIFT (10U)
|
|
/*! POLA - PWM_A Output Polarity
|
|
* 0b0..PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state.
|
|
* 0b1..PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state.
|
|
*/
|
|
#define PWM_OCTRL_POLA(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK)
|
|
|
|
#define PWM_OCTRL_PWMX_IN_MASK (0x2000U)
|
|
#define PWM_OCTRL_PWMX_IN_SHIFT (13U)
|
|
/*! PWMX_IN - PWM_X Input */
|
|
#define PWM_OCTRL_PWMX_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK)
|
|
|
|
#define PWM_OCTRL_PWMB_IN_MASK (0x4000U)
|
|
#define PWM_OCTRL_PWMB_IN_SHIFT (14U)
|
|
/*! PWMB_IN - PWM_B Input */
|
|
#define PWM_OCTRL_PWMB_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK)
|
|
|
|
#define PWM_OCTRL_PWMA_IN_MASK (0x8000U)
|
|
#define PWM_OCTRL_PWMA_IN_SHIFT (15U)
|
|
/*! PWMA_IN - PWM_A Input */
|
|
#define PWM_OCTRL_PWMA_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_OCTRL */
|
|
#define PWM_OCTRL_COUNT (3U)
|
|
|
|
/*! @name STS - Status Register */
|
|
/*! @{ */
|
|
|
|
#define PWM_STS_CMPF_MASK (0x3FU)
|
|
#define PWM_STS_CMPF_SHIFT (0U)
|
|
/*! CMPF - Compare Flags
|
|
* 0b000000..No compare event has occurred for a particular VALx value.
|
|
* 0b000001..A compare event has occurred for a particular VALx value.
|
|
*/
|
|
#define PWM_STS_CMPF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK)
|
|
|
|
#define PWM_STS_CFX0_MASK (0x40U)
|
|
#define PWM_STS_CFX0_SHIFT (6U)
|
|
/*! CFX0 - Capture Flag X0 */
|
|
#define PWM_STS_CFX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK)
|
|
|
|
#define PWM_STS_CFX1_MASK (0x80U)
|
|
#define PWM_STS_CFX1_SHIFT (7U)
|
|
/*! CFX1 - Capture Flag X1 */
|
|
#define PWM_STS_CFX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK)
|
|
|
|
#define PWM_STS_RF_MASK (0x1000U)
|
|
#define PWM_STS_RF_SHIFT (12U)
|
|
/*! RF - Reload Flag
|
|
* 0b0..No new reload cycle since last STS[RF] clearing
|
|
* 0b1..New reload cycle since last STS[RF] clearing
|
|
*/
|
|
#define PWM_STS_RF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK)
|
|
|
|
#define PWM_STS_REF_MASK (0x2000U)
|
|
#define PWM_STS_REF_SHIFT (13U)
|
|
/*! REF - Reload Error Flag
|
|
* 0b0..No reload error occurred.
|
|
* 0b1..Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0.
|
|
*/
|
|
#define PWM_STS_REF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK)
|
|
|
|
#define PWM_STS_RUF_MASK (0x4000U)
|
|
#define PWM_STS_RUF_SHIFT (14U)
|
|
/*! RUF - Registers Updated Flag
|
|
* 0b0..No register update has occurred since last reload.
|
|
* 0b1..At least one of the double buffered registers has been updated since the last reload.
|
|
*/
|
|
#define PWM_STS_RUF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_STS */
|
|
#define PWM_STS_COUNT (3U)
|
|
|
|
/*! @name INTEN - Interrupt Enable Register */
|
|
/*! @{ */
|
|
|
|
#define PWM_INTEN_CMPIE_MASK (0x3FU)
|
|
#define PWM_INTEN_CMPIE_SHIFT (0U)
|
|
/*! CMPIE - Compare Interrupt Enables
|
|
* 0b000000..The corresponding STS[CMPF] bit will not cause an interrupt request.
|
|
* 0b000001..The corresponding STS[CMPF] bit will cause an interrupt request.
|
|
*/
|
|
#define PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK)
|
|
|
|
#define PWM_INTEN_CX0IE_MASK (0x40U)
|
|
#define PWM_INTEN_CX0IE_SHIFT (6U)
|
|
/*! CX0IE - Capture X 0 Interrupt Enable
|
|
* 0b0..Interrupt request disabled for STS[CFX0].
|
|
* 0b1..Interrupt request enabled for STS[CFX0].
|
|
*/
|
|
#define PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK)
|
|
|
|
#define PWM_INTEN_CX1IE_MASK (0x80U)
|
|
#define PWM_INTEN_CX1IE_SHIFT (7U)
|
|
/*! CX1IE - Capture X 1 Interrupt Enable
|
|
* 0b0..Interrupt request disabled for STS[CFX1].
|
|
* 0b1..Interrupt request enabled for STS[CFX1].
|
|
*/
|
|
#define PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK)
|
|
|
|
#define PWM_INTEN_RIE_MASK (0x1000U)
|
|
#define PWM_INTEN_RIE_SHIFT (12U)
|
|
/*! RIE - Reload Interrupt Enable
|
|
* 0b0..STS[RF] CPU interrupt requests disabled
|
|
* 0b1..STS[RF] CPU interrupt requests enabled
|
|
*/
|
|
#define PWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK)
|
|
|
|
#define PWM_INTEN_REIE_MASK (0x2000U)
|
|
#define PWM_INTEN_REIE_SHIFT (13U)
|
|
/*! REIE - Reload Error Interrupt Enable
|
|
* 0b0..STS[REF] CPU interrupt requests disabled
|
|
* 0b1..STS[REF] CPU interrupt requests enabled
|
|
*/
|
|
#define PWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_INTEN */
|
|
#define PWM_INTEN_COUNT (3U)
|
|
|
|
/*! @name DMAEN - DMA Enable Register */
|
|
/*! @{ */
|
|
|
|
#define PWM_DMAEN_CX0DE_MASK (0x1U)
|
|
#define PWM_DMAEN_CX0DE_SHIFT (0U)
|
|
/*! CX0DE - Capture X0 FIFO DMA Enable */
|
|
#define PWM_DMAEN_CX0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK)
|
|
|
|
#define PWM_DMAEN_CX1DE_MASK (0x2U)
|
|
#define PWM_DMAEN_CX1DE_SHIFT (1U)
|
|
/*! CX1DE - Capture X1 FIFO DMA Enable */
|
|
#define PWM_DMAEN_CX1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK)
|
|
|
|
#define PWM_DMAEN_CAPTDE_MASK (0xC0U)
|
|
#define PWM_DMAEN_CAPTDE_SHIFT (6U)
|
|
/*! CAPTDE - Capture DMA Enable Source Select
|
|
* 0b00..Read DMA requests disabled.
|
|
* 0b01..Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE],
|
|
* DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to be set to determine which
|
|
* watermark(s) the DMA request is sensitive.
|
|
* 0b10..A local synchronization (VAL1 matches counter) sets the read DMA request.
|
|
* 0b11..A local reload (STS[RF] being set) sets the read DMA request.
|
|
*/
|
|
#define PWM_DMAEN_CAPTDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK)
|
|
|
|
#define PWM_DMAEN_FAND_MASK (0x100U)
|
|
#define PWM_DMAEN_FAND_SHIFT (8U)
|
|
/*! FAND - FIFO Watermark AND Control
|
|
* 0b0..Selected FIFO watermarks are OR'ed together.
|
|
* 0b1..Selected FIFO watermarks are AND'ed together.
|
|
*/
|
|
#define PWM_DMAEN_FAND(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK)
|
|
|
|
#define PWM_DMAEN_VALDE_MASK (0x200U)
|
|
#define PWM_DMAEN_VALDE_SHIFT (9U)
|
|
/*! VALDE - Value Registers DMA Enable
|
|
* 0b0..DMA write requests disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_DMAEN */
|
|
#define PWM_DMAEN_COUNT (3U)
|
|
|
|
/*! @name TCTRL - Output Trigger Control Register */
|
|
/*! @{ */
|
|
|
|
#define PWM_TCTRL_OUT_TRIG_EN_MASK (0x3FU)
|
|
#define PWM_TCTRL_OUT_TRIG_EN_SHIFT (0U)
|
|
/*! OUT_TRIG_EN - Output Trigger Enables
|
|
* 0bxxxxx1..PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value.
|
|
* 0bxxxx1x..PWM_OUT_TRIG1 will set when the counter value matches the VAL1 value.
|
|
* 0bxxx1xx..PWM_OUT_TRIG0 will set when the counter value matches the VAL2 value.
|
|
* 0bxx1xxx..PWM_OUT_TRIG1 will set when the counter value matches the VAL3 value.
|
|
* 0bx1xxxx..PWM_OUT_TRIG0 will set when the counter value matches the VAL4 value.
|
|
* 0b1xxxxx..PWM_OUT_TRIG1 will set when the counter value matches the VAL5 value.
|
|
*/
|
|
#define PWM_TCTRL_OUT_TRIG_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK)
|
|
|
|
#define PWM_TCTRL_TRGFRQ_MASK (0x1000U)
|
|
#define PWM_TCTRL_TRGFRQ_SHIFT (12U)
|
|
/*! TRGFRQ - Trigger Frequency
|
|
* 0b0..Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.
|
|
* 0b1..Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM
|
|
* is not reloaded every period due to CTRL[LDFQ] being non-zero.
|
|
*/
|
|
#define PWM_TCTRL_TRGFRQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK)
|
|
|
|
#define PWM_TCTRL_PWBOT1_MASK (0x4000U)
|
|
#define PWM_TCTRL_PWBOT1_SHIFT (14U)
|
|
/*! PWBOT1 - Mux Output Trigger 1 Source Select
|
|
* 0b0..Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port.
|
|
* 0b1..Route the PWM_B output to the PWM_MUX_TRIG1 port.
|
|
*/
|
|
#define PWM_TCTRL_PWBOT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK)
|
|
|
|
#define PWM_TCTRL_PWAOT0_MASK (0x8000U)
|
|
#define PWM_TCTRL_PWAOT0_SHIFT (15U)
|
|
/*! PWAOT0 - Mux Output Trigger 0 Source Select
|
|
* 0b0..Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port.
|
|
* 0b1..Route the PWM_A output to the PWM_MUX_TRIG0 port.
|
|
*/
|
|
#define PWM_TCTRL_PWAOT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_TCTRL */
|
|
#define PWM_TCTRL_COUNT (3U)
|
|
|
|
/*! @name DISMAP - Fault Disable Mapping Register 0 */
|
|
/*! @{ */
|
|
|
|
#define PWM_DISMAP_DIS0A_MASK (0xFU)
|
|
#define PWM_DISMAP_DIS0A_SHIFT (0U)
|
|
/*! DIS0A - PWM_A Fault Disable Mask 0 */
|
|
#define PWM_DISMAP_DIS0A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK)
|
|
|
|
#define PWM_DISMAP_DIS0B_MASK (0xF0U)
|
|
#define PWM_DISMAP_DIS0B_SHIFT (4U)
|
|
/*! DIS0B - PWM_B Fault Disable Mask 0 */
|
|
#define PWM_DISMAP_DIS0B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK)
|
|
|
|
#define PWM_DISMAP_DIS0X_MASK (0xF00U)
|
|
#define PWM_DISMAP_DIS0X_SHIFT (8U)
|
|
/*! DIS0X - PWM_X Fault Disable Mask 0 */
|
|
#define PWM_DISMAP_DIS0X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_DISMAP */
|
|
#define PWM_DISMAP_COUNT (3U)
|
|
|
|
/* The count of PWM_DISMAP */
|
|
#define PWM_DISMAP_COUNT2 (1U)
|
|
|
|
/*! @name DTCNT0 - Deadtime Count Register 0 */
|
|
/*! @{ */
|
|
|
|
#define PWM_DTCNT0_DTCNT0_MASK (0x7FFU)
|
|
#define PWM_DTCNT0_DTCNT0_SHIFT (0U)
|
|
/*! DTCNT0 - Deadtime Count Register 0 */
|
|
#define PWM_DTCNT0_DTCNT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_DTCNT0 */
|
|
#define PWM_DTCNT0_COUNT (3U)
|
|
|
|
/*! @name DTCNT1 - Deadtime Count Register 1 */
|
|
/*! @{ */
|
|
|
|
#define PWM_DTCNT1_DTCNT1_MASK (0x7FFU)
|
|
#define PWM_DTCNT1_DTCNT1_SHIFT (0U)
|
|
/*! DTCNT1 - Deadtime Count Register 1 */
|
|
#define PWM_DTCNT1_DTCNT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_DTCNT1 */
|
|
#define PWM_DTCNT1_COUNT (3U)
|
|
|
|
/*! @name CAPTCTRLX - Capture Control X Register */
|
|
/*! @{ */
|
|
|
|
#define PWM_CAPTCTRLX_ARMX_MASK (0x1U)
|
|
#define PWM_CAPTCTRLX_ARMX_SHIFT (0U)
|
|
/*! ARMX - Arm X
|
|
* 0b0..Input capture operation is disabled.
|
|
* 0b1..Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled.
|
|
*/
|
|
#define PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK)
|
|
|
|
#define PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U)
|
|
#define PWM_CAPTCTRLX_ONESHOTX_SHIFT (1U)
|
|
/*! ONESHOTX - One Shot Mode Aux
|
|
* 0b0..Free Running
|
|
* 0b1..One Shot
|
|
*/
|
|
#define PWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK)
|
|
|
|
#define PWM_CAPTCTRLX_EDGX0_MASK (0xCU)
|
|
#define PWM_CAPTCTRLX_EDGX0_SHIFT (2U)
|
|
/*! EDGX0 - Edge X 0
|
|
* 0b00..Disabled
|
|
* 0b01..Capture falling edges
|
|
* 0b10..Capture rising edges
|
|
* 0b11..Capture any edge
|
|
*/
|
|
#define PWM_CAPTCTRLX_EDGX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK)
|
|
|
|
#define PWM_CAPTCTRLX_EDGX1_MASK (0x30U)
|
|
#define PWM_CAPTCTRLX_EDGX1_SHIFT (4U)
|
|
/*! EDGX1 - Edge X 1
|
|
* 0b00..Disabled
|
|
* 0b01..Capture falling edges
|
|
* 0b10..Capture rising edges
|
|
* 0b11..Capture any edge
|
|
*/
|
|
#define PWM_CAPTCTRLX_EDGX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK)
|
|
|
|
#define PWM_CAPTCTRLX_INP_SELX_MASK (0x40U)
|
|
#define PWM_CAPTCTRLX_INP_SELX_SHIFT (6U)
|
|
/*! INP_SELX - Input Select X
|
|
* 0b0..Raw PWM_X input signal selected as source.
|
|
* 0b1..Edge Counter
|
|
*/
|
|
#define PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK)
|
|
|
|
#define PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U)
|
|
#define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT (7U)
|
|
/*! EDGCNTX_EN - Edge Counter X Enable
|
|
* 0b0..Edge counter disabled and held in reset
|
|
* 0b1..Edge counter enabled
|
|
*/
|
|
#define PWM_CAPTCTRLX_EDGCNTX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK)
|
|
|
|
#define PWM_CAPTCTRLX_CFXWM_MASK (0x300U)
|
|
#define PWM_CAPTCTRLX_CFXWM_SHIFT (8U)
|
|
/*! CFXWM - Capture X FIFOs Water Mark */
|
|
#define PWM_CAPTCTRLX_CFXWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK)
|
|
|
|
#define PWM_CAPTCTRLX_CX0CNT_MASK (0x1C00U)
|
|
#define PWM_CAPTCTRLX_CX0CNT_SHIFT (10U)
|
|
/*! CX0CNT - Capture X0 FIFO Word Count */
|
|
#define PWM_CAPTCTRLX_CX0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK)
|
|
|
|
#define PWM_CAPTCTRLX_CX1CNT_MASK (0xE000U)
|
|
#define PWM_CAPTCTRLX_CX1CNT_SHIFT (13U)
|
|
/*! CX1CNT - Capture X1 FIFO Word Count */
|
|
#define PWM_CAPTCTRLX_CX1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_CAPTCTRLX */
|
|
#define PWM_CAPTCTRLX_COUNT (3U)
|
|
|
|
/*! @name CAPTCOMPX - Capture Compare X Register */
|
|
/*! @{ */
|
|
|
|
#define PWM_CAPTCOMPX_EDGCMPX_MASK (0xFFU)
|
|
#define PWM_CAPTCOMPX_EDGCMPX_SHIFT (0U)
|
|
/*! EDGCMPX - Edge Compare X */
|
|
#define PWM_CAPTCOMPX_EDGCMPX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK)
|
|
|
|
#define PWM_CAPTCOMPX_EDGCNTX_MASK (0xFF00U)
|
|
#define PWM_CAPTCOMPX_EDGCNTX_SHIFT (8U)
|
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/*! EDGCNTX - Edge Counter X */
|
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#define PWM_CAPTCOMPX_EDGCNTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK)
|
|
/*! @} */
|
|
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/* The count of PWM_CAPTCOMPX */
|
|
#define PWM_CAPTCOMPX_COUNT (3U)
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|
|
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/*! @name CVAL0 - Capture Value 0 Register */
|
|
/*! @{ */
|
|
|
|
#define PWM_CVAL0_CAPTVAL0_MASK (0xFFFFU)
|
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#define PWM_CVAL0_CAPTVAL0_SHIFT (0U)
|
|
/*! CAPTVAL0 - Capture Value 0 */
|
|
#define PWM_CVAL0_CAPTVAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK)
|
|
/*! @} */
|
|
|
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/* The count of PWM_CVAL0 */
|
|
#define PWM_CVAL0_COUNT (3U)
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|
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/*! @name CVAL0CYC - Capture Value 0 Cycle Register */
|
|
/*! @{ */
|
|
|
|
#define PWM_CVAL0CYC_CVAL0CYC_MASK (0xFU)
|
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#define PWM_CVAL0CYC_CVAL0CYC_SHIFT (0U)
|
|
/*! CVAL0CYC - Capture Value 0 Cycle */
|
|
#define PWM_CVAL0CYC_CVAL0CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK)
|
|
/*! @} */
|
|
|
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/* The count of PWM_CVAL0CYC */
|
|
#define PWM_CVAL0CYC_COUNT (3U)
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|
|
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/*! @name CVAL1 - Capture Value 1 Register */
|
|
/*! @{ */
|
|
|
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#define PWM_CVAL1_CAPTVAL1_MASK (0xFFFFU)
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#define PWM_CVAL1_CAPTVAL1_SHIFT (0U)
|
|
/*! CAPTVAL1 - Capture Value 1 */
|
|
#define PWM_CVAL1_CAPTVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK)
|
|
/*! @} */
|
|
|
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/* The count of PWM_CVAL1 */
|
|
#define PWM_CVAL1_COUNT (3U)
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|
|
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/*! @name CVAL1CYC - Capture Value 1 Cycle Register */
|
|
/*! @{ */
|
|
|
|
#define PWM_CVAL1CYC_CVAL1CYC_MASK (0xFU)
|
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#define PWM_CVAL1CYC_CVAL1CYC_SHIFT (0U)
|
|
/*! CVAL1CYC - Capture Value 1 Cycle */
|
|
#define PWM_CVAL1CYC_CVAL1CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_CVAL1CYC */
|
|
#define PWM_CVAL1CYC_COUNT (3U)
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|
|
|
/*! @name PHASEDLY - Phase Delay Register */
|
|
/*! @{ */
|
|
|
|
#define PWM_PHASEDLY_PHASEDLY_MASK (0xFFFFU)
|
|
#define PWM_PHASEDLY_PHASEDLY_SHIFT (0U)
|
|
/*! PHASEDLY - Initial Count Register Bits */
|
|
#define PWM_PHASEDLY_PHASEDLY(x) (((uint16_t)(((uint16_t)(x)) << PWM_PHASEDLY_PHASEDLY_SHIFT)) & PWM_PHASEDLY_PHASEDLY_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_PHASEDLY */
|
|
#define PWM_PHASEDLY_COUNT (3U)
|
|
|
|
/*! @name CAPTFILTX - Capture PWM_X Input Filter Register */
|
|
/*! @{ */
|
|
|
|
#define PWM_CAPTFILTX_CAPTX_FILT_PER_MASK (0xFFU)
|
|
#define PWM_CAPTFILTX_CAPTX_FILT_PER_SHIFT (0U)
|
|
/*! CAPTX_FILT_PER - Input Capture Filter Period */
|
|
#define PWM_CAPTFILTX_CAPTX_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTX_CAPTX_FILT_PER_SHIFT)) & PWM_CAPTFILTX_CAPTX_FILT_PER_MASK)
|
|
|
|
#define PWM_CAPTFILTX_CAPTX_FILT_CNT_MASK (0x700U)
|
|
#define PWM_CAPTFILTX_CAPTX_FILT_CNT_SHIFT (8U)
|
|
/*! CAPTX_FILT_CNT - Input Capture Filter Count */
|
|
#define PWM_CAPTFILTX_CAPTX_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTX_CAPTX_FILT_CNT_SHIFT)) & PWM_CAPTFILTX_CAPTX_FILT_CNT_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_CAPTFILTX */
|
|
#define PWM_CAPTFILTX_COUNT (3U)
|
|
|
|
/*! @name OUTEN - Output Enable Register */
|
|
/*! @{ */
|
|
|
|
#define PWM_OUTEN_PWMX_EN_MASK (0x7U)
|
|
#define PWM_OUTEN_PWMX_EN_SHIFT (0U)
|
|
/*! PWMX_EN - PWM_X Output Enables */
|
|
#define PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK)
|
|
|
|
#define PWM_OUTEN_PWMB_EN_MASK (0x70U)
|
|
#define PWM_OUTEN_PWMB_EN_SHIFT (4U)
|
|
/*! PWMB_EN - PWM_B Output Enables */
|
|
#define PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK)
|
|
|
|
#define PWM_OUTEN_PWMA_EN_MASK (0x700U)
|
|
#define PWM_OUTEN_PWMA_EN_SHIFT (8U)
|
|
/*! PWMA_EN - PWM_A Output Enables */
|
|
#define PWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MASK - Mask Register */
|
|
/*! @{ */
|
|
|
|
#define PWM_MASK_MASKX_MASK (0x7U)
|
|
#define PWM_MASK_MASKX_SHIFT (0U)
|
|
/*! MASKX - PWM_X Masks */
|
|
#define PWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK)
|
|
|
|
#define PWM_MASK_MASKB_MASK (0x70U)
|
|
#define PWM_MASK_MASKB_SHIFT (4U)
|
|
/*! MASKB - PWM_B Masks */
|
|
#define PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK)
|
|
|
|
#define PWM_MASK_MASKA_MASK (0x700U)
|
|
#define PWM_MASK_MASKA_SHIFT (8U)
|
|
/*! MASKA - PWM_A Masks */
|
|
#define PWM_MASK_MASKA(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK)
|
|
|
|
#define PWM_MASK_UPDATE_MASK_MASK (0x7000U)
|
|
#define PWM_MASK_UPDATE_MASK_SHIFT (12U)
|
|
/*! UPDATE_MASK - Update Mask Bits Immediately */
|
|
#define PWM_MASK_UPDATE_MASK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SWCOUT - Software Controlled Output Register */
|
|
/*! @{ */
|
|
|
|
#define PWM_SWCOUT_SM0OUT45_MASK (0x1U)
|
|
#define PWM_SWCOUT_SM0OUT45_SHIFT (0U)
|
|
/*! SM0OUT45 - Submodule 0 Software Controlled Output 45
|
|
* 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45.
|
|
* 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45.
|
|
*/
|
|
#define PWM_SWCOUT_SM0OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK)
|
|
|
|
#define PWM_SWCOUT_SM0OUT23_MASK (0x2U)
|
|
#define PWM_SWCOUT_SM0OUT23_SHIFT (1U)
|
|
/*! SM0OUT23 - Submodule 0 Software Controlled Output 23
|
|
* 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23.
|
|
* 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23.
|
|
*/
|
|
#define PWM_SWCOUT_SM0OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK)
|
|
|
|
#define PWM_SWCOUT_SM1OUT45_MASK (0x4U)
|
|
#define PWM_SWCOUT_SM1OUT45_SHIFT (2U)
|
|
/*! SM1OUT45 - Submodule 1 Software Controlled Output 45
|
|
* 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45.
|
|
* 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45.
|
|
*/
|
|
#define PWM_SWCOUT_SM1OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK)
|
|
|
|
#define PWM_SWCOUT_SM1OUT23_MASK (0x8U)
|
|
#define PWM_SWCOUT_SM1OUT23_SHIFT (3U)
|
|
/*! SM1OUT23 - Submodule 1 Software Controlled Output 23
|
|
* 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23.
|
|
* 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23.
|
|
*/
|
|
#define PWM_SWCOUT_SM1OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK)
|
|
|
|
#define PWM_SWCOUT_SM2OUT45_MASK (0x10U)
|
|
#define PWM_SWCOUT_SM2OUT45_SHIFT (4U)
|
|
/*! SM2OUT45 - Submodule 2 Software Controlled Output 45
|
|
* 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45.
|
|
* 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45.
|
|
*/
|
|
#define PWM_SWCOUT_SM2OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK)
|
|
|
|
#define PWM_SWCOUT_SM2OUT23_MASK (0x20U)
|
|
#define PWM_SWCOUT_SM2OUT23_SHIFT (5U)
|
|
/*! SM2OUT23 - Submodule 2 Software Controlled Output 23
|
|
* 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23.
|
|
* 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23.
|
|
*/
|
|
#define PWM_SWCOUT_SM2OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DTSRCSEL - PWM Source Select Register */
|
|
/*! @{ */
|
|
|
|
#define PWM_DTSRCSEL_SM0SEL45_MASK (0x3U)
|
|
#define PWM_DTSRCSEL_SM0SEL45_SHIFT (0U)
|
|
/*! SM0SEL45 - Submodule 0 PWM45 Control Select
|
|
* 0b00..Generated SM0PWM45 signal used by the deadtime logic.
|
|
* 0b01..Inverted generated SM0PWM45 signal used by the deadtime logic.
|
|
* 0b10..SWCOUT[SM0OUT45] used by the deadtime logic.
|
|
* 0b11..Reserved
|
|
*/
|
|
#define PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK)
|
|
|
|
#define PWM_DTSRCSEL_SM0SEL23_MASK (0xCU)
|
|
#define PWM_DTSRCSEL_SM0SEL23_SHIFT (2U)
|
|
/*! SM0SEL23 - Submodule 0 PWM23 Control Select
|
|
* 0b00..Generated SM0PWM23 signal used by the deadtime logic.
|
|
* 0b01..Inverted generated SM0PWM23 signal used by the deadtime logic.
|
|
* 0b10..SWCOUT[SM0OUT23] used by the deadtime logic.
|
|
* 0b11..PWM0_EXTA signal used by the deadtime logic.
|
|
*/
|
|
#define PWM_DTSRCSEL_SM0SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK)
|
|
|
|
#define PWM_DTSRCSEL_SM1SEL45_MASK (0x30U)
|
|
#define PWM_DTSRCSEL_SM1SEL45_SHIFT (4U)
|
|
/*! SM1SEL45 - Submodule 1 PWM45 Control Select
|
|
* 0b00..Generated SM1PWM45 signal used by the deadtime logic.
|
|
* 0b01..Inverted generated SM1PWM45 signal used by the deadtime logic.
|
|
* 0b10..SWCOUT[SM1OUT45] used by the deadtime logic.
|
|
* 0b11..Reserved
|
|
*/
|
|
#define PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK)
|
|
|
|
#define PWM_DTSRCSEL_SM1SEL23_MASK (0xC0U)
|
|
#define PWM_DTSRCSEL_SM1SEL23_SHIFT (6U)
|
|
/*! SM1SEL23 - Submodule 1 PWM23 Control Select
|
|
* 0b00..Generated SM1PWM23 signal used by the deadtime logic.
|
|
* 0b01..Inverted generated SM1PWM23 signal used by the deadtime logic.
|
|
* 0b10..SWCOUT[SM1OUT23] used by the deadtime logic.
|
|
* 0b11..PWM1_EXTA signal used by the deadtime logic.
|
|
*/
|
|
#define PWM_DTSRCSEL_SM1SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK)
|
|
|
|
#define PWM_DTSRCSEL_SM2SEL45_MASK (0x300U)
|
|
#define PWM_DTSRCSEL_SM2SEL45_SHIFT (8U)
|
|
/*! SM2SEL45 - Submodule 2 PWM45 Control Select
|
|
* 0b00..Generated SM2PWM45 signal used by the deadtime logic.
|
|
* 0b01..Inverted generated SM2PWM45 signal used by the deadtime logic.
|
|
* 0b10..SWCOUT[SM2OUT45] used by the deadtime logic.
|
|
* 0b11..Reserved
|
|
*/
|
|
#define PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK)
|
|
|
|
#define PWM_DTSRCSEL_SM2SEL23_MASK (0xC00U)
|
|
#define PWM_DTSRCSEL_SM2SEL23_SHIFT (10U)
|
|
/*! SM2SEL23 - Submodule 2 PWM23 Control Select
|
|
* 0b00..Generated SM2PWM23 signal used by the deadtime logic.
|
|
* 0b01..Inverted generated SM2PWM23 signal used by the deadtime logic.
|
|
* 0b10..SWCOUT[SM2OUT23] used by the deadtime logic.
|
|
* 0b11..PWM2_EXTA signal used by the deadtime logic.
|
|
*/
|
|
#define PWM_DTSRCSEL_SM2SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MCTRL - Master Control Register */
|
|
/*! @{ */
|
|
|
|
#define PWM_MCTRL_LDOK_MASK (0x7U)
|
|
#define PWM_MCTRL_LDOK_SHIFT (0U)
|
|
/*! LDOK - Load Okay
|
|
* 0b000..Do not load new values.
|
|
* 0b001..Load prescaler, modulus, and PWM values of the corresponding submodule.
|
|
*/
|
|
#define PWM_MCTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK)
|
|
|
|
#define PWM_MCTRL_CLDOK_MASK (0x70U)
|
|
#define PWM_MCTRL_CLDOK_SHIFT (4U)
|
|
/*! CLDOK - Clear Load Okay */
|
|
#define PWM_MCTRL_CLDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK)
|
|
|
|
#define PWM_MCTRL_RUN_MASK (0x700U)
|
|
#define PWM_MCTRL_RUN_SHIFT (8U)
|
|
/*! RUN - Run
|
|
* 0b000..PWM counter is stopped, but PWM outputs hold the current state.
|
|
* 0b001..PWM counter is started in the corresponding submodule.
|
|
*/
|
|
#define PWM_MCTRL_RUN(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK)
|
|
|
|
#define PWM_MCTRL_IPOL_MASK (0x7000U)
|
|
#define PWM_MCTRL_IPOL_SHIFT (12U)
|
|
/*! IPOL - Current Polarity
|
|
* 0b000..PWM23 is used to generate complementary PWM pair in the corresponding submodule.
|
|
* 0b001..PWM45 is used to generate complementary PWM pair in the corresponding submodule.
|
|
*/
|
|
#define PWM_MCTRL_IPOL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MCTRL2 - Master Control 2 Register */
|
|
/*! @{ */
|
|
|
|
#define PWM_MCTRL2_WRPROT_MASK (0xCU)
|
|
#define PWM_MCTRL2_WRPROT_SHIFT (2U)
|
|
/*! WRPROT - Write protect
|
|
* 0b00..Write protection off (default).
|
|
* 0b01..Write protection on.
|
|
* 0b10..Write protection off and locked until chip reset.
|
|
* 0b11..Write protection on and locked until chip reset.
|
|
*/
|
|
#define PWM_MCTRL2_WRPROT(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_WRPROT_SHIFT)) & PWM_MCTRL2_WRPROT_MASK)
|
|
|
|
#define PWM_MCTRL2_STRETCH_CNT_PRSC_MASK (0xC0U)
|
|
#define PWM_MCTRL2_STRETCH_CNT_PRSC_SHIFT (6U)
|
|
/*! STRETCH_CNT_PRSC - Stretch IPBus clock count prescaler for mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig
|
|
* 0b00..Stretch count is zero, no stretch.
|
|
* 0b01..Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 2 IPBus clock period.
|
|
* 0b10..Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 4 IPBus clock period.
|
|
* 0b11..Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 8 IPBus clock period.
|
|
*/
|
|
#define PWM_MCTRL2_STRETCH_CNT_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_STRETCH_CNT_PRSC_SHIFT)) & PWM_MCTRL2_STRETCH_CNT_PRSC_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FCTRL - Fault Control Register */
|
|
/*! @{ */
|
|
|
|
#define PWM_FCTRL_FIE_MASK (0xFU)
|
|
#define PWM_FCTRL_FIE_SHIFT (0U)
|
|
/*! FIE - Fault Interrupt Enables
|
|
* 0b0000..FAULTx CPU interrupt requests disabled.
|
|
* 0b0001..FAULTx CPU interrupt requests enabled.
|
|
*/
|
|
#define PWM_FCTRL_FIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK)
|
|
|
|
#define PWM_FCTRL_FSAFE_MASK (0xF0U)
|
|
#define PWM_FCTRL_FSAFE_SHIFT (4U)
|
|
/*! FSAFE - Fault Safety Mode
|
|
* 0b0000..Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the
|
|
* start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without regard
|
|
* to the state of FSTS[FFPINx]. If neither FHALF nor FFULL is set, then the fault condition cannot be
|
|
* cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input
|
|
* signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in
|
|
* DISMAPn).
|
|
* 0b0001..Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and
|
|
* FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and
|
|
* FSTS[FFULL]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared.
|
|
*/
|
|
#define PWM_FCTRL_FSAFE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK)
|
|
|
|
#define PWM_FCTRL_FAUTO_MASK (0xF00U)
|
|
#define PWM_FCTRL_FAUTO_SHIFT (8U)
|
|
/*! FAUTO - Automatic Fault Clearing
|
|
* 0b0000..Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear
|
|
* at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL]. If
|
|
* neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled
|
|
* by FCTRL[FSAFE].
|
|
* 0b0001..Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at
|
|
* the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without
|
|
* regard to the state of FSTS[FFLAGx]. If neither FFULL nor FHALF is set, then the fault condition
|
|
* cannot be cleared.
|
|
*/
|
|
#define PWM_FCTRL_FAUTO(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK)
|
|
|
|
#define PWM_FCTRL_FLVL_MASK (0xF000U)
|
|
#define PWM_FCTRL_FLVL_SHIFT (12U)
|
|
/*! FLVL - Fault Level
|
|
* 0b0000..A logic 0 on the fault input indicates a fault condition.
|
|
* 0b0001..A logic 1 on the fault input indicates a fault condition.
|
|
*/
|
|
#define PWM_FCTRL_FLVL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FSTS - Fault Status Register */
|
|
/*! @{ */
|
|
|
|
#define PWM_FSTS_FFLAG_MASK (0xFU)
|
|
#define PWM_FSTS_FFLAG_SHIFT (0U)
|
|
/*! FFLAG - Fault Flags
|
|
* 0b0000..No fault on the FAULTx pin.
|
|
* 0b0001..Fault on the FAULTx pin.
|
|
*/
|
|
#define PWM_FSTS_FFLAG(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK)
|
|
|
|
#define PWM_FSTS_FFULL_MASK (0xF0U)
|
|
#define PWM_FSTS_FFULL_SHIFT (4U)
|
|
/*! FFULL - Full Cycle
|
|
* 0b0000..PWM outputs are not re-enabled at the start of a full cycle
|
|
* 0b0001..PWM outputs are re-enabled at the start of a full cycle
|
|
*/
|
|
#define PWM_FSTS_FFULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK)
|
|
|
|
#define PWM_FSTS_FFPIN_MASK (0xF00U)
|
|
#define PWM_FSTS_FFPIN_SHIFT (8U)
|
|
/*! FFPIN - Filtered Fault Pins */
|
|
#define PWM_FSTS_FFPIN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK)
|
|
|
|
#define PWM_FSTS_FHALF_MASK (0xF000U)
|
|
#define PWM_FSTS_FHALF_SHIFT (12U)
|
|
/*! FHALF - Half Cycle Fault Recovery
|
|
* 0b0000..PWM outputs are not re-enabled at the start of a half cycle.
|
|
* 0b0001..PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0).
|
|
*/
|
|
#define PWM_FSTS_FHALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FFILT - Fault Filter Register */
|
|
/*! @{ */
|
|
|
|
#define PWM_FFILT_FILT_PER_MASK (0xFFU)
|
|
#define PWM_FFILT_FILT_PER_SHIFT (0U)
|
|
/*! FILT_PER - Fault Filter Period */
|
|
#define PWM_FFILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK)
|
|
|
|
#define PWM_FFILT_FILT_CNT_MASK (0x700U)
|
|
#define PWM_FFILT_FILT_CNT_SHIFT (8U)
|
|
/*! FILT_CNT - Fault Filter Count */
|
|
#define PWM_FFILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK)
|
|
|
|
#define PWM_FFILT_GSTR_MASK (0x8000U)
|
|
#define PWM_FFILT_GSTR_SHIFT (15U)
|
|
/*! GSTR - Fault Glitch Stretch Enable
|
|
* 0b0..Fault input glitch stretching is disabled.
|
|
* 0b1..Input fault signals are stretched to at least 2 IPBus clock cycles.
|
|
*/
|
|
#define PWM_FFILT_GSTR(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FTST - Fault Test Register */
|
|
/*! @{ */
|
|
|
|
#define PWM_FTST_FTEST_MASK (0x1U)
|
|
#define PWM_FTST_FTEST_SHIFT (0U)
|
|
/*! FTEST - Fault Test
|
|
* 0b0..No fault
|
|
* 0b1..Cause a simulated fault
|
|
*/
|
|
#define PWM_FTST_FTEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FCTRL2 - Fault Control 2 Register */
|
|
/*! @{ */
|
|
|
|
#define PWM_FCTRL2_NOCOMB_MASK (0xFU)
|
|
#define PWM_FCTRL2_NOCOMB_SHIFT (0U)
|
|
/*! NOCOMB - No Combinational Path From Fault Input To PWM Output
|
|
* 0b0000..There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined
|
|
* with the filtered and latched fault signals to disable the PWM outputs.
|
|
* 0b0001..The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered
|
|
* and latched fault signals are used to disable the PWM outputs.
|
|
*/
|
|
#define PWM_FCTRL2_NOCOMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group PWM_Register_Masks */
|
|
|
|
|
|
/* PWM - Peripheral instance base addresses */
|
|
/** Peripheral FLEXPWM0 base address */
|
|
#define FLEXPWM0_BASE (0x400A9000u)
|
|
/** Peripheral FLEXPWM0 base pointer */
|
|
#define FLEXPWM0 ((PWM_Type *)FLEXPWM0_BASE)
|
|
/** Array initializer of PWM peripheral base addresses */
|
|
#define PWM_BASE_ADDRS { FLEXPWM0_BASE }
|
|
/** Array initializer of PWM peripheral base pointers */
|
|
#define PWM_BASE_PTRS { FLEXPWM0 }
|
|
/** Interrupt vectors for the PWM peripheral type */
|
|
#define PWM_CMP_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn } }
|
|
#define PWM_RELOAD_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn } }
|
|
#define PWM_CAPTURE_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn } }
|
|
#define PWM_FAULT_IRQS { FLEXPWM0_FAULT_IRQn }
|
|
#define PWM_RELOAD_ERROR_IRQS { FLEXPWM0_RELOAD_ERROR_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group PWM_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- SCG Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup SCG_Peripheral_Access_Layer SCG Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** SCG - Register Layout Typedef */
|
|
typedef struct {
|
|
__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
|
|
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
|
|
__IO uint32_t TRIM_LOCK; /**< Trim Lock register, offset: 0x8 */
|
|
uint8_t RESERVED_0[4];
|
|
__I uint32_t CSR; /**< Clock Status Register, offset: 0x10 */
|
|
__IO uint32_t RCCR; /**< Run Clock Control Register, offset: 0x14 */
|
|
uint8_t RESERVED_1[232];
|
|
__IO uint32_t SOSCCSR; /**< SOSC Control Status Register, offset: 0x100 */
|
|
uint8_t RESERVED_2[4];
|
|
__IO uint32_t SOSCCFG; /**< SOSC Configuration Register, offset: 0x108 */
|
|
uint8_t RESERVED_3[244];
|
|
__IO uint32_t SIRCCSR; /**< SIRC Control Status Register, offset: 0x200 */
|
|
uint8_t RESERVED_4[8];
|
|
__IO uint32_t SIRCTCFG; /**< SIRC Trim Configuration Register, offset: 0x20C */
|
|
uint8_t RESERVED_5[8];
|
|
__IO uint32_t SIRCSTAT; /**< SIRC Auto-trimming Status Register, offset: 0x218 */
|
|
uint8_t RESERVED_6[228];
|
|
__IO uint32_t FIRCCSR; /**< FIRC Control Status Register, offset: 0x300 */
|
|
uint8_t RESERVED_7[4];
|
|
__IO uint32_t FIRCCFG; /**< FIRC Configuration Register, offset: 0x308 */
|
|
__IO uint32_t FIRCTCFG; /**< FIRC Trim Configuration Register, offset: 0x30C */
|
|
__IO uint32_t FIRCTRIM; /**< FIRC Trim Register, offset: 0x310 */
|
|
uint8_t RESERVED_8[4];
|
|
__IO uint32_t FIRCSTAT; /**< FIRC Auto-trimming Status Register, offset: 0x318 */
|
|
uint8_t RESERVED_9[228];
|
|
__IO uint32_t ROSCCSR; /**< ROSC Control Status Register, offset: 0x400 */
|
|
} SCG_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- SCG Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup SCG_Register_Masks SCG Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name VERID - Version ID Register */
|
|
/*! @{ */
|
|
|
|
#define SCG_VERID_VERSION_MASK (0xFFFFFFFFU)
|
|
#define SCG_VERID_VERSION_SHIFT (0U)
|
|
/*! VERSION - SCG Version Number */
|
|
#define SCG_VERID_VERSION(x) (((uint32_t)(((uint32_t)(x)) << SCG_VERID_VERSION_SHIFT)) & SCG_VERID_VERSION_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PARAM - Parameter Register */
|
|
/*! @{ */
|
|
|
|
#define SCG_PARAM_SOSCCLKPRES_MASK (0x2U)
|
|
#define SCG_PARAM_SOSCCLKPRES_SHIFT (1U)
|
|
/*! SOSCCLKPRES - SOSC Clock Present
|
|
* 0b1..SOSC clock source is present
|
|
* 0b0..SOSC clock source is not present
|
|
*/
|
|
#define SCG_PARAM_SOSCCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_SOSCCLKPRES_SHIFT)) & SCG_PARAM_SOSCCLKPRES_MASK)
|
|
|
|
#define SCG_PARAM_SIRCCLKPRES_MASK (0x4U)
|
|
#define SCG_PARAM_SIRCCLKPRES_SHIFT (2U)
|
|
/*! SIRCCLKPRES - SIRC Clock Present
|
|
* 0b1..SIRC clock source is present
|
|
* 0b0..SIRC clock source is not present
|
|
*/
|
|
#define SCG_PARAM_SIRCCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_SIRCCLKPRES_SHIFT)) & SCG_PARAM_SIRCCLKPRES_MASK)
|
|
|
|
#define SCG_PARAM_FIRCCLKPRES_MASK (0x8U)
|
|
#define SCG_PARAM_FIRCCLKPRES_SHIFT (3U)
|
|
/*! FIRCCLKPRES - FIRC Clock Present
|
|
* 0b1..FIRC clock source is present
|
|
* 0b0..FIRC clock source is not present
|
|
*/
|
|
#define SCG_PARAM_FIRCCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_FIRCCLKPRES_SHIFT)) & SCG_PARAM_FIRCCLKPRES_MASK)
|
|
|
|
#define SCG_PARAM_ROSCCLKPRES_MASK (0x10U)
|
|
#define SCG_PARAM_ROSCCLKPRES_SHIFT (4U)
|
|
/*! ROSCCLKPRES - ROSC Clock Present
|
|
* 0b1..ROSC clock source is present
|
|
* 0b0..ROSC clock source is not present
|
|
*/
|
|
#define SCG_PARAM_ROSCCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_ROSCCLKPRES_SHIFT)) & SCG_PARAM_ROSCCLKPRES_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TRIM_LOCK - Trim Lock register */
|
|
/*! @{ */
|
|
|
|
#define SCG_TRIM_LOCK_TRIM_UNLOCK_MASK (0x1U)
|
|
#define SCG_TRIM_LOCK_TRIM_UNLOCK_SHIFT (0U)
|
|
/*! TRIM_UNLOCK - TRIM_UNLOCK
|
|
* 0b0..SCG Trim Registers locked and not writable.
|
|
* 0b1..SCG Trim registers unlocked and writable.
|
|
*/
|
|
#define SCG_TRIM_LOCK_TRIM_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << SCG_TRIM_LOCK_TRIM_UNLOCK_SHIFT)) & SCG_TRIM_LOCK_TRIM_UNLOCK_MASK)
|
|
|
|
#define SCG_TRIM_LOCK_IFR_DISABLE_MASK (0x2U)
|
|
#define SCG_TRIM_LOCK_IFR_DISABLE_SHIFT (1U)
|
|
/*! IFR_DISABLE - IFR_DISABLE
|
|
* 0b0..IFR write access to SCG trim registers not disabled. The SCG Trim registers are reprogrammed with the IFR values after any system reset.
|
|
* 0b1..IFR write access to SCG trim registers during system reset is blocked.
|
|
*/
|
|
#define SCG_TRIM_LOCK_IFR_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SCG_TRIM_LOCK_IFR_DISABLE_SHIFT)) & SCG_TRIM_LOCK_IFR_DISABLE_MASK)
|
|
|
|
#define SCG_TRIM_LOCK_TRIM_LOCK_KEY_MASK (0xFFFF0000U)
|
|
#define SCG_TRIM_LOCK_TRIM_LOCK_KEY_SHIFT (16U)
|
|
/*! TRIM_LOCK_KEY - TRIM_LOCK_KEY */
|
|
#define SCG_TRIM_LOCK_TRIM_LOCK_KEY(x) (((uint32_t)(((uint32_t)(x)) << SCG_TRIM_LOCK_TRIM_LOCK_KEY_SHIFT)) & SCG_TRIM_LOCK_TRIM_LOCK_KEY_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CSR - Clock Status Register */
|
|
/*! @{ */
|
|
|
|
#define SCG_CSR_SCS_MASK (0x7000000U)
|
|
#define SCG_CSR_SCS_SHIFT (24U)
|
|
/*! SCS - System Clock Source
|
|
* 0b000..Reserved
|
|
* 0b001..SOSC
|
|
* 0b010..SIRC
|
|
* 0b011..FIRC
|
|
* 0b100..ROSC
|
|
* 0b101-0b111..Reserved
|
|
*/
|
|
#define SCG_CSR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_SCS_SHIFT)) & SCG_CSR_SCS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RCCR - Run Clock Control Register */
|
|
/*! @{ */
|
|
|
|
#define SCG_RCCR_SCS_MASK (0x7000000U)
|
|
#define SCG_RCCR_SCS_SHIFT (24U)
|
|
/*! SCS - System Clock Source
|
|
* 0b000..Reserved
|
|
* 0b001..SOSC
|
|
* 0b010..SIRC
|
|
* 0b011..FIRC
|
|
* 0b100..ROSC
|
|
* 0b101-0b111..Reserved
|
|
*/
|
|
#define SCG_RCCR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_SCS_SHIFT)) & SCG_RCCR_SCS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SOSCCSR - SOSC Control Status Register */
|
|
/*! @{ */
|
|
|
|
#define SCG_SOSCCSR_SOSCEN_MASK (0x1U)
|
|
#define SCG_SOSCCSR_SOSCEN_SHIFT (0U)
|
|
/*! SOSCEN - SOSC Enable
|
|
* 0b0..SOSC is disabled
|
|
* 0b1..SOSC is enabled
|
|
*/
|
|
#define SCG_SOSCCSR_SOSCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCEN_SHIFT)) & SCG_SOSCCSR_SOSCEN_MASK)
|
|
|
|
#define SCG_SOSCCSR_SOSCSTEN_MASK (0x2U)
|
|
#define SCG_SOSCCSR_SOSCSTEN_SHIFT (1U)
|
|
/*! SOSCSTEN - SOSC Stop Enable
|
|
* 0b0..SOSC is disabled in Deep Sleep mode
|
|
* 0b1..SOSC is enabled in Deep Sleep mode only if SOSCEN is set
|
|
*/
|
|
#define SCG_SOSCCSR_SOSCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSTEN_SHIFT)) & SCG_SOSCCSR_SOSCSTEN_MASK)
|
|
|
|
#define SCG_SOSCCSR_SOSCCM_MASK (0x10000U)
|
|
#define SCG_SOSCCSR_SOSCCM_SHIFT (16U)
|
|
/*! SOSCCM - SOSC Clock Monitor Enable
|
|
* 0b0..SOSC Clock Monitor is disabled
|
|
* 0b1..SOSC Clock Monitor is enabled
|
|
*/
|
|
#define SCG_SOSCCSR_SOSCCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCM_SHIFT)) & SCG_SOSCCSR_SOSCCM_MASK)
|
|
|
|
#define SCG_SOSCCSR_SOSCCMRE_MASK (0x20000U)
|
|
#define SCG_SOSCCSR_SOSCCMRE_SHIFT (17U)
|
|
/*! SOSCCMRE - SOSC Clock Monitor Reset Enable
|
|
* 0b0..Clock monitor generates an interrupt when an error is detected
|
|
* 0b1..Clock monitor generates a reset when an error is detected
|
|
*/
|
|
#define SCG_SOSCCSR_SOSCCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCMRE_SHIFT)) & SCG_SOSCCSR_SOSCCMRE_MASK)
|
|
|
|
#define SCG_SOSCCSR_LK_MASK (0x800000U)
|
|
#define SCG_SOSCCSR_LK_SHIFT (23U)
|
|
/*! LK - Lock Register
|
|
* 0b0..This Control Status Register can be written
|
|
* 0b1..This Control Status Register cannot be written
|
|
*/
|
|
#define SCG_SOSCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_LK_SHIFT)) & SCG_SOSCCSR_LK_MASK)
|
|
|
|
#define SCG_SOSCCSR_SOSCVLD_MASK (0x1000000U)
|
|
#define SCG_SOSCCSR_SOSCVLD_SHIFT (24U)
|
|
/*! SOSCVLD - SOSC Valid
|
|
* 0b0..SOSC is not enabled or clock is not valid
|
|
* 0b1..SOSC is enabled and output clock is valid
|
|
*/
|
|
#define SCG_SOSCCSR_SOSCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCVLD_SHIFT)) & SCG_SOSCCSR_SOSCVLD_MASK)
|
|
|
|
#define SCG_SOSCCSR_SOSCSEL_MASK (0x2000000U)
|
|
#define SCG_SOSCCSR_SOSCSEL_SHIFT (25U)
|
|
/*! SOSCSEL - SOSC Selected
|
|
* 0b0..SOSC is not the system clock source
|
|
* 0b1..SOSC is the system clock source
|
|
*/
|
|
#define SCG_SOSCCSR_SOSCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSEL_SHIFT)) & SCG_SOSCCSR_SOSCSEL_MASK)
|
|
|
|
#define SCG_SOSCCSR_SOSCERR_MASK (0x4000000U)
|
|
#define SCG_SOSCCSR_SOSCERR_SHIFT (26U)
|
|
/*! SOSCERR - SOSC Clock Error
|
|
* 0b0..SOSC Clock Monitor is disabled or has not detected an error
|
|
* 0b1..SOSC Clock Monitor is enabled and detected an error
|
|
*/
|
|
#define SCG_SOSCCSR_SOSCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCERR_SHIFT)) & SCG_SOSCCSR_SOSCERR_MASK)
|
|
|
|
#define SCG_SOSCCSR_SOSCVLD_IE_MASK (0x40000000U)
|
|
#define SCG_SOSCCSR_SOSCVLD_IE_SHIFT (30U)
|
|
/*! SOSCVLD_IE - SOSC Valid Interrupt Enable
|
|
* 0b0..SOSCVLD interrupt is not enabled
|
|
* 0b1..SOSCVLD interrupt is enabled
|
|
*/
|
|
#define SCG_SOSCCSR_SOSCVLD_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCVLD_IE_SHIFT)) & SCG_SOSCCSR_SOSCVLD_IE_MASK)
|
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/*! @} */
|
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|
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/*! @name SOSCCFG - SOSC Configuration Register */
|
|
/*! @{ */
|
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|
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#define SCG_SOSCCFG_EREFS_MASK (0x4U)
|
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#define SCG_SOSCCFG_EREFS_SHIFT (2U)
|
|
/*! EREFS - External Reference Select
|
|
* 0b0..External reference clock selected.
|
|
* 0b1..Internal crystal oscillator of OSC selected.
|
|
*/
|
|
#define SCG_SOSCCFG_EREFS(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_EREFS_SHIFT)) & SCG_SOSCCFG_EREFS_MASK)
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#define SCG_SOSCCFG_RANGE_MASK (0x30U)
|
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#define SCG_SOSCCFG_RANGE_SHIFT (4U)
|
|
/*! RANGE - SOSC Range Select
|
|
* 0b00..Frequency range select of 8-16 MHz.
|
|
* 0b01..Frequency range select of 16-25 MHz.
|
|
* 0b10..Frequency range select of 25-40 MHz.
|
|
* 0b11..Frequency range select of 40-50 MHz.
|
|
*/
|
|
#define SCG_SOSCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_RANGE_SHIFT)) & SCG_SOSCCFG_RANGE_MASK)
|
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/*! @} */
|
|
|
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/*! @name SIRCCSR - SIRC Control Status Register */
|
|
/*! @{ */
|
|
|
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#define SCG_SIRCCSR_SIRCSTEN_MASK (0x2U)
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#define SCG_SIRCCSR_SIRCSTEN_SHIFT (1U)
|
|
/*! SIRCSTEN - SIRC Stop Enable
|
|
* 0b0..SIRC is disabled in Deep Sleep mode
|
|
* 0b1..SIRC is enabled in Deep Sleep mode
|
|
*/
|
|
#define SCG_SIRCCSR_SIRCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSTEN_SHIFT)) & SCG_SIRCCSR_SIRCSTEN_MASK)
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|
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#define SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_MASK (0x20U)
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#define SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_SHIFT (5U)
|
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/*! SIRC_CLK_PERIPH_EN - SIRC Clock to Peripherals Enable
|
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* 0b0..SIRC clock to peripherals is disabled
|
|
* 0b1..SIRC clock to peripherals is enabled
|
|
*/
|
|
#define SCG_SIRCCSR_SIRC_CLK_PERIPH_EN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_SHIFT)) & SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_MASK)
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#define SCG_SIRCCSR_SIRCTREN_MASK (0x100U)
|
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#define SCG_SIRCCSR_SIRCTREN_SHIFT (8U)
|
|
/*! SIRCTREN - SIRC 12 MHz Trim Enable (SIRCCFG[RANGE]=1)
|
|
* 0b0..Disables trimming SIRC to an external clock source
|
|
* 0b1..Enables trimming SIRC to an external clock source
|
|
*/
|
|
#define SCG_SIRCCSR_SIRCTREN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCTREN_SHIFT)) & SCG_SIRCCSR_SIRCTREN_MASK)
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|
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#define SCG_SIRCCSR_SIRCTRUP_MASK (0x200U)
|
|
#define SCG_SIRCCSR_SIRCTRUP_SHIFT (9U)
|
|
/*! SIRCTRUP - SIRC Trim Update
|
|
* 0b0..Disables SIRC trimming updates
|
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* 0b1..Enables SIRC trimming updates
|
|
*/
|
|
#define SCG_SIRCCSR_SIRCTRUP(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCTRUP_SHIFT)) & SCG_SIRCCSR_SIRCTRUP_MASK)
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|
|
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#define SCG_SIRCCSR_TRIM_LOCK_MASK (0x400U)
|
|
#define SCG_SIRCCSR_TRIM_LOCK_SHIFT (10U)
|
|
/*! TRIM_LOCK - SIRC TRIM LOCK
|
|
* 0b0..SIRC auto trim not locked to target frequency range
|
|
* 0b1..SIRC auto trim locked to target frequency range
|
|
*/
|
|
#define SCG_SIRCCSR_TRIM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_TRIM_LOCK_SHIFT)) & SCG_SIRCCSR_TRIM_LOCK_MASK)
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|
|
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#define SCG_SIRCCSR_COARSE_TRIM_BYPASS_MASK (0x800U)
|
|
#define SCG_SIRCCSR_COARSE_TRIM_BYPASS_SHIFT (11U)
|
|
/*! COARSE_TRIM_BYPASS - Coarse Auto Trim Bypass
|
|
* 0b0..SIRC Coarse Auto Trim NOT Bypassed
|
|
* 0b1..SIRC Coarse Auto Trim Bypassed
|
|
*/
|
|
#define SCG_SIRCCSR_COARSE_TRIM_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_COARSE_TRIM_BYPASS_SHIFT)) & SCG_SIRCCSR_COARSE_TRIM_BYPASS_MASK)
|
|
|
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#define SCG_SIRCCSR_LK_MASK (0x800000U)
|
|
#define SCG_SIRCCSR_LK_SHIFT (23U)
|
|
/*! LK - Lock Register
|
|
* 0b0..Control Status Register can be written
|
|
* 0b1..Control Status Register cannot be written
|
|
*/
|
|
#define SCG_SIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_LK_SHIFT)) & SCG_SIRCCSR_LK_MASK)
|
|
|
|
#define SCG_SIRCCSR_SIRCVLD_MASK (0x1000000U)
|
|
#define SCG_SIRCCSR_SIRCVLD_SHIFT (24U)
|
|
/*! SIRCVLD - SIRC Valid
|
|
* 0b0..SIRC is not enabled or clock is not valid
|
|
* 0b1..SIRC is enabled and output clock is valid
|
|
*/
|
|
#define SCG_SIRCCSR_SIRCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCVLD_SHIFT)) & SCG_SIRCCSR_SIRCVLD_MASK)
|
|
|
|
#define SCG_SIRCCSR_SIRCSEL_MASK (0x2000000U)
|
|
#define SCG_SIRCCSR_SIRCSEL_SHIFT (25U)
|
|
/*! SIRCSEL - SIRC Selected
|
|
* 0b0..SIRC is not the system clock source
|
|
* 0b1..SIRC is the system clock source
|
|
*/
|
|
#define SCG_SIRCCSR_SIRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSEL_SHIFT)) & SCG_SIRCCSR_SIRCSEL_MASK)
|
|
|
|
#define SCG_SIRCCSR_SIRCERR_MASK (0x4000000U)
|
|
#define SCG_SIRCCSR_SIRCERR_SHIFT (26U)
|
|
/*! SIRCERR - SIRC Clock Error
|
|
* 0b0..Error not detected with the SIRC trimming
|
|
* 0b1..Error detected with the SIRC trimming
|
|
*/
|
|
#define SCG_SIRCCSR_SIRCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCERR_SHIFT)) & SCG_SIRCCSR_SIRCERR_MASK)
|
|
|
|
#define SCG_SIRCCSR_SIRCERR_IE_MASK (0x8000000U)
|
|
#define SCG_SIRCCSR_SIRCERR_IE_SHIFT (27U)
|
|
/*! SIRCERR_IE - SIRC Clock Error Interrupt Enable
|
|
* 0b0..SIRCERR interrupt is not enabled
|
|
* 0b1..SIRCERR interrupt is enabled
|
|
*/
|
|
#define SCG_SIRCCSR_SIRCERR_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCERR_IE_SHIFT)) & SCG_SIRCCSR_SIRCERR_IE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SIRCTCFG - SIRC Trim Configuration Register */
|
|
/*! @{ */
|
|
|
|
#define SCG_SIRCTCFG_TRIMSRC_MASK (0x3U)
|
|
#define SCG_SIRCTCFG_TRIMSRC_SHIFT (0U)
|
|
/*! TRIMSRC - Trim Source
|
|
* 0b00..Reserved
|
|
* 0b01..Reserved
|
|
* 0b10..SOSC. This option requires that SOSC be divided using the TRIMDIV field to get a frequency of 1 MHz.
|
|
* 0b11..Reserved
|
|
*/
|
|
#define SCG_SIRCTCFG_TRIMSRC(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTCFG_TRIMSRC_SHIFT)) & SCG_SIRCTCFG_TRIMSRC_MASK)
|
|
|
|
#define SCG_SIRCTCFG_TRIMDIV_MASK (0x7F0000U)
|
|
#define SCG_SIRCTCFG_TRIMDIV_SHIFT (16U)
|
|
/*! TRIMDIV - SIRC Trim Pre-divider */
|
|
#define SCG_SIRCTCFG_TRIMDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTCFG_TRIMDIV_SHIFT)) & SCG_SIRCTCFG_TRIMDIV_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SIRCSTAT - SIRC Auto-trimming Status Register */
|
|
/*! @{ */
|
|
|
|
#define SCG_SIRCSTAT_CCOTRIM_MASK (0x3FU)
|
|
#define SCG_SIRCSTAT_CCOTRIM_SHIFT (0U)
|
|
/*! CCOTRIM - CCO Trim */
|
|
#define SCG_SIRCSTAT_CCOTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCSTAT_CCOTRIM_SHIFT)) & SCG_SIRCSTAT_CCOTRIM_MASK)
|
|
|
|
#define SCG_SIRCSTAT_CLTRIM_MASK (0x3F00U)
|
|
#define SCG_SIRCSTAT_CLTRIM_SHIFT (8U)
|
|
/*! CLTRIM - CL Trim */
|
|
#define SCG_SIRCSTAT_CLTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCSTAT_CLTRIM_SHIFT)) & SCG_SIRCSTAT_CLTRIM_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FIRCCSR - FIRC Control Status Register */
|
|
/*! @{ */
|
|
|
|
#define SCG_FIRCCSR_FIRCEN_MASK (0x1U)
|
|
#define SCG_FIRCCSR_FIRCEN_SHIFT (0U)
|
|
/*! FIRCEN - FIRC Enable
|
|
* 0b0..FIRC is disabled
|
|
* 0b1..FIRC is enabled
|
|
*/
|
|
#define SCG_FIRCCSR_FIRCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCEN_SHIFT)) & SCG_FIRCCSR_FIRCEN_MASK)
|
|
|
|
#define SCG_FIRCCSR_FIRCSTEN_MASK (0x2U)
|
|
#define SCG_FIRCCSR_FIRCSTEN_SHIFT (1U)
|
|
/*! FIRCSTEN - FIRC Stop Enable
|
|
* 0b0..FIRC is disabled in Deep Sleep mode
|
|
* 0b1..FIRC is enabled in Deep Sleep mode
|
|
*/
|
|
#define SCG_FIRCCSR_FIRCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSTEN_SHIFT)) & SCG_FIRCCSR_FIRCSTEN_MASK)
|
|
|
|
#define SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK (0x10U)
|
|
#define SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_SHIFT (4U)
|
|
/*! FIRC_SCLK_PERIPH_EN - FIRC 48 MHz Clock to peripherals Enable
|
|
* 0b0..FIRC 48 MHz to peripherals is disabled
|
|
* 0b1..FIRC 48 MHz to peripherals is enabled
|
|
*/
|
|
#define SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_SHIFT)) & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK)
|
|
|
|
#define SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK (0x20U)
|
|
#define SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_SHIFT (5U)
|
|
/*! FIRC_FCLK_PERIPH_EN - FRO_HF Clock to peripherals Enable
|
|
* 0b0..FRO_HF to peripherals is disabled
|
|
* 0b1..FRO_HF to peripherals is enabled
|
|
*/
|
|
#define SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_SHIFT)) & SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK)
|
|
|
|
#define SCG_FIRCCSR_FIRCTREN_MASK (0x100U)
|
|
#define SCG_FIRCCSR_FIRCTREN_SHIFT (8U)
|
|
/*! FIRCTREN - FRO_HF Trim Enable
|
|
* 0b0..Disables trimming FRO_HF by an external clock source
|
|
* 0b1..Enables trimming FRO_HF by an external clock source
|
|
*/
|
|
#define SCG_FIRCCSR_FIRCTREN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCTREN_SHIFT)) & SCG_FIRCCSR_FIRCTREN_MASK)
|
|
|
|
#define SCG_FIRCCSR_FIRCTRUP_MASK (0x200U)
|
|
#define SCG_FIRCCSR_FIRCTRUP_SHIFT (9U)
|
|
/*! FIRCTRUP - FIRC Trim Update
|
|
* 0b0..Disables FIRC trimming updates
|
|
* 0b1..Enables FIRC trimming updates
|
|
*/
|
|
#define SCG_FIRCCSR_FIRCTRUP(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCTRUP_SHIFT)) & SCG_FIRCCSR_FIRCTRUP_MASK)
|
|
|
|
#define SCG_FIRCCSR_TRIM_LOCK_MASK (0x400U)
|
|
#define SCG_FIRCCSR_TRIM_LOCK_SHIFT (10U)
|
|
/*! TRIM_LOCK - FIRC TRIM LOCK
|
|
* 0b0..FIRC auto trim not locked to target frequency range
|
|
* 0b1..FIRC auto trim locked to target frequency range
|
|
*/
|
|
#define SCG_FIRCCSR_TRIM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_TRIM_LOCK_SHIFT)) & SCG_FIRCCSR_TRIM_LOCK_MASK)
|
|
|
|
#define SCG_FIRCCSR_COARSE_TRIM_BYPASS_MASK (0x800U)
|
|
#define SCG_FIRCCSR_COARSE_TRIM_BYPASS_SHIFT (11U)
|
|
/*! COARSE_TRIM_BYPASS - Coarse Auto Trim Bypass
|
|
* 0b0..FIRC Coarse Auto Trim NOT Bypassed
|
|
* 0b1..FIRC Coarse Auto Trim Bypassed
|
|
*/
|
|
#define SCG_FIRCCSR_COARSE_TRIM_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_COARSE_TRIM_BYPASS_SHIFT)) & SCG_FIRCCSR_COARSE_TRIM_BYPASS_MASK)
|
|
|
|
#define SCG_FIRCCSR_LK_MASK (0x800000U)
|
|
#define SCG_FIRCCSR_LK_SHIFT (23U)
|
|
/*! LK - Lock Register
|
|
* 0b0..Control Status Register can be written
|
|
* 0b1..Control Status Register cannot be written
|
|
*/
|
|
#define SCG_FIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_LK_SHIFT)) & SCG_FIRCCSR_LK_MASK)
|
|
|
|
#define SCG_FIRCCSR_FIRCVLD_MASK (0x1000000U)
|
|
#define SCG_FIRCCSR_FIRCVLD_SHIFT (24U)
|
|
/*! FIRCVLD - FIRC Valid status
|
|
* 0b0..FIRC is not enabled or clock is not valid.
|
|
* 0b1..FIRC is enabled and output clock is valid. The clock is valid after there is an output clock from the FIRC analog.
|
|
*/
|
|
#define SCG_FIRCCSR_FIRCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCVLD_SHIFT)) & SCG_FIRCCSR_FIRCVLD_MASK)
|
|
|
|
#define SCG_FIRCCSR_FIRCSEL_MASK (0x2000000U)
|
|
#define SCG_FIRCCSR_FIRCSEL_SHIFT (25U)
|
|
/*! FIRCSEL - FIRC Selected
|
|
* 0b0..FIRC is not the system clock source
|
|
* 0b1..FIRC is the system clock source
|
|
*/
|
|
#define SCG_FIRCCSR_FIRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSEL_SHIFT)) & SCG_FIRCCSR_FIRCSEL_MASK)
|
|
|
|
#define SCG_FIRCCSR_FIRCERR_MASK (0x4000000U)
|
|
#define SCG_FIRCCSR_FIRCERR_SHIFT (26U)
|
|
/*! FIRCERR - FIRC Clock Error
|
|
* 0b0..Error not detected with the FIRC trimming
|
|
* 0b1..Error detected with the FIRC trimming
|
|
*/
|
|
#define SCG_FIRCCSR_FIRCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_SHIFT)) & SCG_FIRCCSR_FIRCERR_MASK)
|
|
|
|
#define SCG_FIRCCSR_FIRCERR_IE_MASK (0x8000000U)
|
|
#define SCG_FIRCCSR_FIRCERR_IE_SHIFT (27U)
|
|
/*! FIRCERR_IE - FIRC Clock Error Interrupt Enable
|
|
* 0b0..FIRCERR interrupt is not enabled
|
|
* 0b1..FIRCERR interrupt is enabled
|
|
*/
|
|
#define SCG_FIRCCSR_FIRCERR_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_IE_SHIFT)) & SCG_FIRCCSR_FIRCERR_IE_MASK)
|
|
|
|
#define SCG_FIRCCSR_FIRCACC_IE_MASK (0x40000000U)
|
|
#define SCG_FIRCCSR_FIRCACC_IE_SHIFT (30U)
|
|
/*! FIRCACC_IE - FIRC Accurate Interrupt Enable
|
|
* 0b0..FIRCACC interrupt is not enabled
|
|
* 0b1..FIRCACC interrupt is enabled
|
|
*/
|
|
#define SCG_FIRCCSR_FIRCACC_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCACC_IE_SHIFT)) & SCG_FIRCCSR_FIRCACC_IE_MASK)
|
|
|
|
#define SCG_FIRCCSR_FIRCACC_MASK (0x80000000U)
|
|
#define SCG_FIRCCSR_FIRCACC_SHIFT (31U)
|
|
/*! FIRCACC - FIRC Frequency Accurate
|
|
* 0b0..FIRC is not enabled or clock is not accurate.
|
|
* 0b1..FIRC is enabled and output clock is accurate. The clock is accurate after 4096 clock cycles of FRO_HF
|
|
* clock(It also takes 4096 clock cycles when FIRCCFG_FREQ_SEL[0] changes) or 1365 clock cycles of 48 MHz from
|
|
* the FIRC analog.
|
|
*/
|
|
#define SCG_FIRCCSR_FIRCACC(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCACC_SHIFT)) & SCG_FIRCCSR_FIRCACC_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FIRCCFG - FIRC Configuration Register */
|
|
/*! @{ */
|
|
|
|
#define SCG_FIRCCFG_FREQ_SEL_MASK (0xEU)
|
|
#define SCG_FIRCCFG_FREQ_SEL_SHIFT (1U)
|
|
/*! FREQ_SEL - Frequency select
|
|
* 0b111..192 MHz FIRC clock selected
|
|
* 0b110..144 MHz FIRC clock selected
|
|
* 0b101..96 MHz FIRC clock selected
|
|
* 0b100..72 MHz FIRC clock selected
|
|
* 0b011..64 MHz FIRC clock selected
|
|
* 0b010..48 MHz FIRC clock selected, divided from 144 MHz
|
|
* 0b001..48 MHz FIRC clock selected, divided from 192 MHz
|
|
* 0b000..36 MHz FIRC clock selected
|
|
*/
|
|
#define SCG_FIRCCFG_FREQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCFG_FREQ_SEL_SHIFT)) & SCG_FIRCCFG_FREQ_SEL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FIRCTCFG - FIRC Trim Configuration Register */
|
|
/*! @{ */
|
|
|
|
#define SCG_FIRCTCFG_TRIMSRC_MASK (0x3U)
|
|
#define SCG_FIRCTCFG_TRIMSRC_SHIFT (0U)
|
|
/*! TRIMSRC - Trim Source
|
|
* 0b00..USB0 Start of Frame (1 KHz). This option does not use TRIMDIV .
|
|
* 0b01..Reserved
|
|
* 0b10..SOSC. This option requires that SOSC be divided using the TRIMDIV field to get a frequency of 1 MHz.
|
|
* 0b11..Reserved
|
|
*/
|
|
#define SCG_FIRCTCFG_TRIMSRC(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTCFG_TRIMSRC_SHIFT)) & SCG_FIRCTCFG_TRIMSRC_MASK)
|
|
|
|
#define SCG_FIRCTCFG_TRIMDIV_MASK (0x7F0000U)
|
|
#define SCG_FIRCTCFG_TRIMDIV_SHIFT (16U)
|
|
/*! TRIMDIV - FIRC Trim Pre-divider */
|
|
#define SCG_FIRCTCFG_TRIMDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTCFG_TRIMDIV_SHIFT)) & SCG_FIRCTCFG_TRIMDIV_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FIRCTRIM - FIRC Trim Register */
|
|
/*! @{ */
|
|
|
|
#define SCG_FIRCTRIM_TRIMFINE_MASK (0xFFU)
|
|
#define SCG_FIRCTRIM_TRIMFINE_SHIFT (0U)
|
|
/*! TRIMFINE - Trim Fine */
|
|
#define SCG_FIRCTRIM_TRIMFINE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMFINE_SHIFT)) & SCG_FIRCTRIM_TRIMFINE_MASK)
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#define SCG_FIRCTRIM_TRIMCOAR_MASK (0x3F00U)
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#define SCG_FIRCTRIM_TRIMCOAR_SHIFT (8U)
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/*! TRIMCOAR - Trim Coarse */
|
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#define SCG_FIRCTRIM_TRIMCOAR(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMCOAR_SHIFT)) & SCG_FIRCTRIM_TRIMCOAR_MASK)
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#define SCG_FIRCTRIM_TRIMTEMP1_MASK (0x30000U)
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#define SCG_FIRCTRIM_TRIMTEMP1_SHIFT (16U)
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/*! TRIMTEMP1 - Trim Temperature1 */
|
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#define SCG_FIRCTRIM_TRIMTEMP1(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMTEMP1_SHIFT)) & SCG_FIRCTRIM_TRIMTEMP1_MASK)
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#define SCG_FIRCTRIM_TRIMTEMP2_MASK (0xC0000U)
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#define SCG_FIRCTRIM_TRIMTEMP2_SHIFT (18U)
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/*! TRIMTEMP2 - Trim Temperature2 */
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#define SCG_FIRCTRIM_TRIMTEMP2(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMTEMP2_SHIFT)) & SCG_FIRCTRIM_TRIMTEMP2_MASK)
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#define SCG_FIRCTRIM_TRIMSTART_MASK (0x3F000000U)
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#define SCG_FIRCTRIM_TRIMSTART_SHIFT (24U)
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/*! TRIMSTART - Trim Start */
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#define SCG_FIRCTRIM_TRIMSTART(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMSTART_SHIFT)) & SCG_FIRCTRIM_TRIMSTART_MASK)
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/*! @} */
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/*! @name FIRCSTAT - FIRC Auto-trimming Status Register */
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/*! @{ */
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#define SCG_FIRCSTAT_TRIMFINE_MASK (0xFFU)
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#define SCG_FIRCSTAT_TRIMFINE_SHIFT (0U)
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/*! TRIMFINE - Trim Fine */
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#define SCG_FIRCSTAT_TRIMFINE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCSTAT_TRIMFINE_SHIFT)) & SCG_FIRCSTAT_TRIMFINE_MASK)
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#define SCG_FIRCSTAT_TRIMCOAR_MASK (0x3F00U)
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#define SCG_FIRCSTAT_TRIMCOAR_SHIFT (8U)
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/*! TRIMCOAR - Trim Coarse */
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#define SCG_FIRCSTAT_TRIMCOAR(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCSTAT_TRIMCOAR_SHIFT)) & SCG_FIRCSTAT_TRIMCOAR_MASK)
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/*! @} */
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/*! @name ROSCCSR - ROSC Control Status Register */
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/*! @{ */
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#define SCG_ROSCCSR_LK_MASK (0x800000U)
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#define SCG_ROSCCSR_LK_SHIFT (23U)
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/*! LK - Lock Register
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* 0b0..Control Status Register can be written
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* 0b1..Control Status Register cannot be written
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*/
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#define SCG_ROSCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_LK_SHIFT)) & SCG_ROSCCSR_LK_MASK)
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#define SCG_ROSCCSR_ROSCVLD_MASK (0x1000000U)
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#define SCG_ROSCCSR_ROSCVLD_SHIFT (24U)
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/*! ROSCVLD - ROSC Valid
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* 0b0..ROSC is not enabled or clock is not valid
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* 0b1..ROSC is enabled and output clock is valid
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*/
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#define SCG_ROSCCSR_ROSCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCVLD_SHIFT)) & SCG_ROSCCSR_ROSCVLD_MASK)
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#define SCG_ROSCCSR_ROSCSEL_MASK (0x2000000U)
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#define SCG_ROSCCSR_ROSCSEL_SHIFT (25U)
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/*! ROSCSEL - ROSC Selected
|
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* 0b0..ROSC is not the system clock source
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* 0b1..ROSC is the system clock source
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*/
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#define SCG_ROSCCSR_ROSCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCSEL_SHIFT)) & SCG_ROSCCSR_ROSCSEL_MASK)
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#define SCG_ROSCCSR_ROSCERR_MASK (0x4000000U)
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#define SCG_ROSCCSR_ROSCERR_SHIFT (26U)
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/*! ROSCERR - ROSC Clock Error
|
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* 0b0..ROSC Clock has not detected an error
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* 0b1..ROSC Clock has detected an error
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*/
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#define SCG_ROSCCSR_ROSCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCERR_SHIFT)) & SCG_ROSCCSR_ROSCERR_MASK)
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/*! @} */
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/*!
|
|
* @}
|
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*/ /* end of group SCG_Register_Masks */
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/* SCG - Peripheral instance base addresses */
|
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/** Peripheral SCG0 base address */
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#define SCG0_BASE (0x4008F000u)
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/** Peripheral SCG0 base pointer */
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#define SCG0 ((SCG_Type *)SCG0_BASE)
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/** Array initializer of SCG peripheral base addresses */
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#define SCG_BASE_ADDRS { SCG0_BASE }
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/** Array initializer of SCG peripheral base pointers */
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#define SCG_BASE_PTRS { SCG0 }
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|
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/*!
|
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* @}
|
|
*/ /* end of group SCG_Peripheral_Access_Layer */
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|
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/* ----------------------------------------------------------------------------
|
|
-- SPC Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
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|
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/*!
|
|
* @addtogroup SPC_Peripheral_Access_Layer SPC Peripheral Access Layer
|
|
* @{
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|
*/
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|
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/** SPC - Register Layout Typedef */
|
|
typedef struct {
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|
__I uint32_t VERID; /**< Version ID, offset: 0x0 */
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uint8_t RESERVED_0[12];
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__IO uint32_t SC; /**< Status Control, offset: 0x10 */
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uint8_t RESERVED_1[8];
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__IO uint32_t LPREQ_CFG; /**< Low-Power Request Configuration, offset: 0x1C */
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__IO uint32_t CFG; /**< SPC Configuration, offset: 0x20 */
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uint8_t RESERVED_2[12];
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|
__IO uint32_t PD_STATUS[1]; /**< SPC Power Domain Mode Status, array offset: 0x30, array step: 0x4 */
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uint8_t RESERVED_3[12];
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__IO uint32_t SRAMCTL; /**< SRAM Control, offset: 0x40 */
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uint8_t RESERVED_4[16];
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__IO uint32_t SRAMRETLDO_REFTRIM; /**< SRAM Retention Reference Trim, offset: 0x54 */
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__IO uint32_t SRAMRETLDO_CNTRL; /**< SRAM Retention LDO Control, offset: 0x58 */
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uint8_t RESERVED_5[164];
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__IO uint32_t ACTIVE_CFG; /**< Active Power Mode Configuration, offset: 0x100 */
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|
__IO uint32_t ACTIVE_CFG1; /**< Active Power Mode Configuration 1, offset: 0x104 */
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__IO uint32_t LP_CFG; /**< Low-Power Mode Configuration, offset: 0x108 */
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|
__IO uint32_t LP_CFG1; /**< Low Power Mode Configuration 1, offset: 0x10C */
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|
uint8_t RESERVED_6[16];
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|
__IO uint32_t LPWKUP_DELAY; /**< Low Power Wake-Up Delay, offset: 0x120 */
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|
__IO uint32_t ACTIVE_VDELAY; /**< Active Voltage Trim Delay, offset: 0x124 */
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|
uint8_t RESERVED_7[8];
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|
__IO uint32_t VD_STAT; /**< Voltage Detect Status, offset: 0x130 */
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|
__IO uint32_t VD_CORE_CFG; /**< Core Voltage Detect Configuration, offset: 0x134 */
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|
__IO uint32_t VD_SYS_CFG; /**< System Voltage Detect Configuration, offset: 0x138 */
|
|
uint8_t RESERVED_8[4];
|
|
__IO uint32_t EVD_CFG; /**< External Voltage Domain Configuration, offset: 0x140 */
|
|
uint8_t RESERVED_9[444];
|
|
uint32_t CORELDO_CFG; /**< LDO_CORE Configuration, offset: 0x300 */
|
|
} SPC_Type;
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|
|
|
/* ----------------------------------------------------------------------------
|
|
-- SPC Register Masks
|
|
---------------------------------------------------------------------------- */
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|
|
|
/*!
|
|
* @addtogroup SPC_Register_Masks SPC Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name VERID - Version ID */
|
|
/*! @{ */
|
|
|
|
#define SPC_VERID_FEATURE_MASK (0xFFFFU)
|
|
#define SPC_VERID_FEATURE_SHIFT (0U)
|
|
/*! FEATURE - Feature Specification Number
|
|
* 0b0000000000000000..Standard features
|
|
* *..
|
|
*/
|
|
#define SPC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VERID_FEATURE_SHIFT)) & SPC_VERID_FEATURE_MASK)
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|
|
|
#define SPC_VERID_MINOR_MASK (0xFF0000U)
|
|
#define SPC_VERID_MINOR_SHIFT (16U)
|
|
/*! MINOR - Minor Version Number */
|
|
#define SPC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SPC_VERID_MINOR_SHIFT)) & SPC_VERID_MINOR_MASK)
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|
|
|
#define SPC_VERID_MAJOR_MASK (0xFF000000U)
|
|
#define SPC_VERID_MAJOR_SHIFT (24U)
|
|
/*! MAJOR - Major Version Number */
|
|
#define SPC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << SPC_VERID_MAJOR_SHIFT)) & SPC_VERID_MAJOR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SC - Status Control */
|
|
/*! @{ */
|
|
|
|
#define SPC_SC_BUSY_MASK (0x1U)
|
|
#define SPC_SC_BUSY_SHIFT (0U)
|
|
/*! BUSY - SPC Busy Status Flag
|
|
* 0b0..Not busy
|
|
* 0b1..Busy
|
|
*/
|
|
#define SPC_SC_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SPC_SC_BUSY_SHIFT)) & SPC_SC_BUSY_MASK)
|
|
|
|
#define SPC_SC_SPC_LP_REQ_MASK (0x2U)
|
|
#define SPC_SC_SPC_LP_REQ_SHIFT (1U)
|
|
/*! SPC_LP_REQ - SPC Power Mode Configuration Status Flag
|
|
* 0b0..SPC is in Active mode; the ACTIVE_CFG register has control
|
|
* 0b1..All power domains requested low-power mode; SPC entered a low-power state; power-mode configuration based on the LP_CFG register
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define SPC_SC_SPC_LP_REQ(x) (((uint32_t)(((uint32_t)(x)) << SPC_SC_SPC_LP_REQ_SHIFT)) & SPC_SC_SPC_LP_REQ_MASK)
|
|
|
|
#define SPC_SC_SPC_LP_MODE_MASK (0xF0U)
|
|
#define SPC_SC_SPC_LP_MODE_SHIFT (4U)
|
|
/*! SPC_LP_MODE - Power Domain Low-Power Mode Request
|
|
* 0b0000..Sleep mode with system clock running
|
|
* 0b0001..DSLEEP with system clock off
|
|
* 0b0010..PDOWN with system clock off
|
|
* 0b0100..
|
|
* 0b1000..DPDOWN with system clock off
|
|
*/
|
|
#define SPC_SC_SPC_LP_MODE(x) (((uint32_t)(((uint32_t)(x)) << SPC_SC_SPC_LP_MODE_SHIFT)) & SPC_SC_SPC_LP_MODE_MASK)
|
|
|
|
#define SPC_SC_ISO_CLR_MASK (0x10000U)
|
|
#define SPC_SC_ISO_CLR_SHIFT (16U)
|
|
/*! ISO_CLR - Isolation Clear Flags */
|
|
#define SPC_SC_ISO_CLR(x) (((uint32_t)(((uint32_t)(x)) << SPC_SC_ISO_CLR_SHIFT)) & SPC_SC_ISO_CLR_MASK)
|
|
|
|
#define SPC_SC_SWITCH_STATE_MASK (0x80000000U)
|
|
#define SPC_SC_SWITCH_STATE_SHIFT (31U)
|
|
/*! SWITCH_STATE - Power Switch State
|
|
* 0b0..Off
|
|
* 0b1..On
|
|
*/
|
|
#define SPC_SC_SWITCH_STATE(x) (((uint32_t)(((uint32_t)(x)) << SPC_SC_SWITCH_STATE_SHIFT)) & SPC_SC_SWITCH_STATE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name LPREQ_CFG - Low-Power Request Configuration */
|
|
/*! @{ */
|
|
|
|
#define SPC_LPREQ_CFG_LPREQOE_MASK (0x1U)
|
|
#define SPC_LPREQ_CFG_LPREQOE_SHIFT (0U)
|
|
/*! LPREQOE - Low-Power Request Output Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define SPC_LPREQ_CFG_LPREQOE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LPREQ_CFG_LPREQOE_SHIFT)) & SPC_LPREQ_CFG_LPREQOE_MASK)
|
|
|
|
#define SPC_LPREQ_CFG_LPREQPOL_MASK (0x2U)
|
|
#define SPC_LPREQ_CFG_LPREQPOL_SHIFT (1U)
|
|
/*! LPREQPOL - Low-Power Request Output Pin Polarity Control
|
|
* 0b0..High
|
|
* 0b1..Low
|
|
*/
|
|
#define SPC_LPREQ_CFG_LPREQPOL(x) (((uint32_t)(((uint32_t)(x)) << SPC_LPREQ_CFG_LPREQPOL_SHIFT)) & SPC_LPREQ_CFG_LPREQPOL_MASK)
|
|
|
|
#define SPC_LPREQ_CFG_LPREQOV_MASK (0xCU)
|
|
#define SPC_LPREQ_CFG_LPREQOV_SHIFT (2U)
|
|
/*! LPREQOV - Low-Power Request Output Override
|
|
* 0b00..Not forced
|
|
* 0b01..
|
|
* 0b10..Forced low (ignore LPREQPOL settings)
|
|
* 0b11..Forced high (ignore LPREQPOL settings)
|
|
*/
|
|
#define SPC_LPREQ_CFG_LPREQOV(x) (((uint32_t)(((uint32_t)(x)) << SPC_LPREQ_CFG_LPREQOV_SHIFT)) & SPC_LPREQ_CFG_LPREQOV_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CFG - SPC Configuration */
|
|
/*! @{ */
|
|
|
|
#define SPC_CFG_INTG_PWSWTCH_SLEEP_EN_MASK (0x1U)
|
|
#define SPC_CFG_INTG_PWSWTCH_SLEEP_EN_SHIFT (0U)
|
|
/*! INTG_PWSWTCH_SLEEP_EN - Integrated Power Switch Sleep Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define SPC_CFG_INTG_PWSWTCH_SLEEP_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_CFG_INTG_PWSWTCH_SLEEP_EN_SHIFT)) & SPC_CFG_INTG_PWSWTCH_SLEEP_EN_MASK)
|
|
|
|
#define SPC_CFG_INTG_PWSWTCH_WKUP_EN_MASK (0x2U)
|
|
#define SPC_CFG_INTG_PWSWTCH_WKUP_EN_SHIFT (1U)
|
|
/*! INTG_PWSWTCH_WKUP_EN - Integrated Power Switch Wake-up Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define SPC_CFG_INTG_PWSWTCH_WKUP_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_CFG_INTG_PWSWTCH_WKUP_EN_SHIFT)) & SPC_CFG_INTG_PWSWTCH_WKUP_EN_MASK)
|
|
|
|
#define SPC_CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN_MASK (0x4U)
|
|
#define SPC_CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN_SHIFT (2U)
|
|
/*! INTG_PWSWTCH_SLEEP_ACTIVE_EN - Integrated Power Switch Active Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define SPC_CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN_SHIFT)) & SPC_CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN_MASK)
|
|
|
|
#define SPC_CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN_MASK (0x8U)
|
|
#define SPC_CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN_SHIFT (3U)
|
|
/*! INTG_PWSWTCH_WKUP_ACTIVE_EN - Integrated Power Switch Wake-up Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define SPC_CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN_SHIFT)) & SPC_CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PD_STATUS - SPC Power Domain Mode Status */
|
|
/*! @{ */
|
|
|
|
#define SPC_PD_STATUS_PWR_REQ_STATUS_MASK (0x1U)
|
|
#define SPC_PD_STATUS_PWR_REQ_STATUS_SHIFT (0U)
|
|
/*! PWR_REQ_STATUS - Power Request Status Flag
|
|
* 0b0..Did not request
|
|
* 0b1..Requested
|
|
*/
|
|
#define SPC_PD_STATUS_PWR_REQ_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SPC_PD_STATUS_PWR_REQ_STATUS_SHIFT)) & SPC_PD_STATUS_PWR_REQ_STATUS_MASK)
|
|
|
|
#define SPC_PD_STATUS_PD_LP_REQ_MASK (0x10U)
|
|
#define SPC_PD_STATUS_PD_LP_REQ_SHIFT (4U)
|
|
/*! PD_LP_REQ - Power Domain Low Power Request Flag
|
|
* 0b0..Did not request
|
|
* 0b1..Requested
|
|
*/
|
|
#define SPC_PD_STATUS_PD_LP_REQ(x) (((uint32_t)(((uint32_t)(x)) << SPC_PD_STATUS_PD_LP_REQ_SHIFT)) & SPC_PD_STATUS_PD_LP_REQ_MASK)
|
|
|
|
#define SPC_PD_STATUS_LP_MODE_MASK (0xF00U)
|
|
#define SPC_PD_STATUS_LP_MODE_SHIFT (8U)
|
|
/*! LP_MODE - Power Domain Low Power Mode Request
|
|
* 0b0000..SLEEP with system clock running
|
|
* 0b0001..DSLEEP with system clock off
|
|
* 0b0010..PDOWN with system clock off
|
|
* 0b0100..
|
|
* 0b1000..DPDOWN with system clock off
|
|
*/
|
|
#define SPC_PD_STATUS_LP_MODE(x) (((uint32_t)(((uint32_t)(x)) << SPC_PD_STATUS_LP_MODE_SHIFT)) & SPC_PD_STATUS_LP_MODE_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of SPC_PD_STATUS */
|
|
#define SPC_PD_STATUS_COUNT (1U)
|
|
|
|
/*! @name SRAMCTL - SRAM Control */
|
|
/*! @{ */
|
|
|
|
#define SPC_SRAMCTL_VSM_MASK (0x3U)
|
|
#define SPC_SRAMCTL_VSM_SHIFT (0U)
|
|
/*! VSM - Voltage Select Margin
|
|
* 0b00..
|
|
* 0b01..1.0 V
|
|
* 0b10..1.1 V
|
|
* 0b11..SRAM configured for 1.2 V operation
|
|
*/
|
|
#define SPC_SRAMCTL_VSM(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMCTL_VSM_SHIFT)) & SPC_SRAMCTL_VSM_MASK)
|
|
|
|
#define SPC_SRAMCTL_REQ_MASK (0x40000000U)
|
|
#define SPC_SRAMCTL_REQ_SHIFT (30U)
|
|
/*! REQ - SRAM Voltage Update Request
|
|
* 0b0..Do not request
|
|
* 0b1..Request
|
|
*/
|
|
#define SPC_SRAMCTL_REQ(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMCTL_REQ_SHIFT)) & SPC_SRAMCTL_REQ_MASK)
|
|
|
|
#define SPC_SRAMCTL_ACK_MASK (0x80000000U)
|
|
#define SPC_SRAMCTL_ACK_SHIFT (31U)
|
|
/*! ACK - SRAM Voltage Update Request Acknowledge
|
|
* 0b0..Not acknowledged
|
|
* 0b1..Acknowledged
|
|
*/
|
|
#define SPC_SRAMCTL_ACK(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMCTL_ACK_SHIFT)) & SPC_SRAMCTL_ACK_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SRAMRETLDO_REFTRIM - SRAM Retention Reference Trim */
|
|
/*! @{ */
|
|
|
|
#define SPC_SRAMRETLDO_REFTRIM_REFTRIM_MASK (0x1FU)
|
|
#define SPC_SRAMRETLDO_REFTRIM_REFTRIM_SHIFT (0U)
|
|
/*! REFTRIM - Reference Trim. Voltage range is around 0.48V - 0.85V. Trim step is 12 mV. */
|
|
#define SPC_SRAMRETLDO_REFTRIM_REFTRIM(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMRETLDO_REFTRIM_REFTRIM_SHIFT)) & SPC_SRAMRETLDO_REFTRIM_REFTRIM_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SRAMRETLDO_CNTRL - SRAM Retention LDO Control */
|
|
/*! @{ */
|
|
|
|
#define SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON_MASK (0x1U)
|
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#define SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON_SHIFT (0U)
|
|
/*! SRAMLDO_ON - SRAM LDO Regulator Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON_SHIFT)) & SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON_MASK)
|
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|
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#define SPC_SRAMRETLDO_CNTRL_SRAM_RET_EN_MASK (0xF00U)
|
|
#define SPC_SRAMRETLDO_CNTRL_SRAM_RET_EN_SHIFT (8U)
|
|
/*! SRAM_RET_EN - SRAM Retention */
|
|
#define SPC_SRAMRETLDO_CNTRL_SRAM_RET_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMRETLDO_CNTRL_SRAM_RET_EN_SHIFT)) & SPC_SRAMRETLDO_CNTRL_SRAM_RET_EN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ACTIVE_CFG - Active Power Mode Configuration */
|
|
/*! @{ */
|
|
|
|
#define SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK (0x1U)
|
|
#define SPC_ACTIVE_CFG_CORELDO_VDD_DS_SHIFT (0U)
|
|
/*! CORELDO_VDD_DS - LDO_CORE VDD Drive Strength
|
|
* 0b0..Low
|
|
* 0b1..Normal
|
|
*/
|
|
#define SPC_ACTIVE_CFG_CORELDO_VDD_DS(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORELDO_VDD_DS_SHIFT)) & SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK)
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#define SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK (0xCU)
|
|
#define SPC_ACTIVE_CFG_CORELDO_VDD_LVL_SHIFT (2U)
|
|
/*! CORELDO_VDD_LVL - LDO_CORE VDD Regulator Voltage Level
|
|
* 0b00..
|
|
* 0b01..Regulate to mid voltage (1.0 V)
|
|
* 0b10..Regulate to normal voltage (1.1 V)
|
|
* 0b11..Regulate to overdrive voltage (1.15 V)
|
|
*/
|
|
#define SPC_ACTIVE_CFG_CORELDO_VDD_LVL(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORELDO_VDD_LVL_SHIFT)) & SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK)
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#define SPC_ACTIVE_CFG_BGMODE_MASK (0x300000U)
|
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#define SPC_ACTIVE_CFG_BGMODE_SHIFT (20U)
|
|
/*! BGMODE - Bandgap Mode
|
|
* 0b00..Bandgap disabled
|
|
* 0b01..Bandgap enabled, buffer disabled
|
|
* 0b10..Bandgap enabled, buffer enabled
|
|
* 0b11..
|
|
*/
|
|
#define SPC_ACTIVE_CFG_BGMODE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_BGMODE_SHIFT)) & SPC_ACTIVE_CFG_BGMODE_MASK)
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#define SPC_ACTIVE_CFG_VDD_VD_DISABLE_MASK (0x800000U)
|
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#define SPC_ACTIVE_CFG_VDD_VD_DISABLE_SHIFT (23U)
|
|
/*! VDD_VD_DISABLE - VDD Voltage Detect Disable
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define SPC_ACTIVE_CFG_VDD_VD_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_VDD_VD_DISABLE_SHIFT)) & SPC_ACTIVE_CFG_VDD_VD_DISABLE_MASK)
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|
|
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#define SPC_ACTIVE_CFG_CORE_LVDE_MASK (0x1000000U)
|
|
#define SPC_ACTIVE_CFG_CORE_LVDE_SHIFT (24U)
|
|
/*! CORE_LVDE - Core Low-Voltage Detection Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define SPC_ACTIVE_CFG_CORE_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORE_LVDE_SHIFT)) & SPC_ACTIVE_CFG_CORE_LVDE_MASK)
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|
|
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#define SPC_ACTIVE_CFG_SYS_LVDE_MASK (0x2000000U)
|
|
#define SPC_ACTIVE_CFG_SYS_LVDE_SHIFT (25U)
|
|
/*! SYS_LVDE - System Low-Voltage Detection Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define SPC_ACTIVE_CFG_SYS_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_SYS_LVDE_SHIFT)) & SPC_ACTIVE_CFG_SYS_LVDE_MASK)
|
|
|
|
#define SPC_ACTIVE_CFG_SYS_HVDE_MASK (0x10000000U)
|
|
#define SPC_ACTIVE_CFG_SYS_HVDE_SHIFT (28U)
|
|
/*! SYS_HVDE - System High-Voltage Detection Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define SPC_ACTIVE_CFG_SYS_HVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_SYS_HVDE_SHIFT)) & SPC_ACTIVE_CFG_SYS_HVDE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ACTIVE_CFG1 - Active Power Mode Configuration 1 */
|
|
/*! @{ */
|
|
|
|
#define SPC_ACTIVE_CFG1_SOC_CNTRL_MASK (0xFFFFFFFFU)
|
|
#define SPC_ACTIVE_CFG1_SOC_CNTRL_SHIFT (0U)
|
|
/*! SOC_CNTRL - Active Config Chip Control */
|
|
#define SPC_ACTIVE_CFG1_SOC_CNTRL(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG1_SOC_CNTRL_SHIFT)) & SPC_ACTIVE_CFG1_SOC_CNTRL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name LP_CFG - Low-Power Mode Configuration */
|
|
/*! @{ */
|
|
|
|
#define SPC_LP_CFG_CORELDO_VDD_DS_MASK (0x1U)
|
|
#define SPC_LP_CFG_CORELDO_VDD_DS_SHIFT (0U)
|
|
/*! CORELDO_VDD_DS - LDO_CORE VDD Drive Strength
|
|
* 0b0..Low
|
|
* 0b1..Normal
|
|
*/
|
|
#define SPC_LP_CFG_CORELDO_VDD_DS(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORELDO_VDD_DS_SHIFT)) & SPC_LP_CFG_CORELDO_VDD_DS_MASK)
|
|
|
|
#define SPC_LP_CFG_CORELDO_VDD_LVL_MASK (0xCU)
|
|
#define SPC_LP_CFG_CORELDO_VDD_LVL_SHIFT (2U)
|
|
/*! CORELDO_VDD_LVL - LDO_CORE VDD Regulator Voltage Level
|
|
* 0b00..Reserved
|
|
* 0b01..Mid voltage (1.0 V)
|
|
* 0b10..Normal voltage (1.1 V)
|
|
* 0b11..Overdrive voltage (1.15 V)
|
|
* *..
|
|
*/
|
|
#define SPC_LP_CFG_CORELDO_VDD_LVL(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORELDO_VDD_LVL_SHIFT)) & SPC_LP_CFG_CORELDO_VDD_LVL_MASK)
|
|
|
|
#define SPC_LP_CFG_SRAMLDO_DPD_ON_MASK (0x80000U)
|
|
#define SPC_LP_CFG_SRAMLDO_DPD_ON_SHIFT (19U)
|
|
/*! SRAMLDO_DPD_ON - SRAM_LDO Deep Power Low Power IREF Enable
|
|
* 0b0..Low Power IREF is disabled for power saving in Deep Power Down mode
|
|
* 0b1..Low Power IREF is enabled
|
|
*/
|
|
#define SPC_LP_CFG_SRAMLDO_DPD_ON(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_SRAMLDO_DPD_ON_SHIFT)) & SPC_LP_CFG_SRAMLDO_DPD_ON_MASK)
|
|
|
|
#define SPC_LP_CFG_BGMODE_MASK (0x300000U)
|
|
#define SPC_LP_CFG_BGMODE_SHIFT (20U)
|
|
/*! BGMODE - Bandgap Mode
|
|
* 0b00..Bandgap disabled
|
|
* 0b01..Bandgap enabled, buffer disabled
|
|
* 0b10..Bandgap enabled, buffer enabled
|
|
* 0b11..
|
|
*/
|
|
#define SPC_LP_CFG_BGMODE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_BGMODE_SHIFT)) & SPC_LP_CFG_BGMODE_MASK)
|
|
|
|
#define SPC_LP_CFG_LP_IREFEN_MASK (0x800000U)
|
|
#define SPC_LP_CFG_LP_IREFEN_SHIFT (23U)
|
|
/*! LP_IREFEN - Low-Power IREF Enable
|
|
* 0b0..Disable for power saving in Deep Power Down mode
|
|
* 0b1..Enable
|
|
*/
|
|
#define SPC_LP_CFG_LP_IREFEN(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_LP_IREFEN_SHIFT)) & SPC_LP_CFG_LP_IREFEN_MASK)
|
|
|
|
#define SPC_LP_CFG_CORE_LVDE_MASK (0x1000000U)
|
|
#define SPC_LP_CFG_CORE_LVDE_SHIFT (24U)
|
|
/*! CORE_LVDE - Core Low Voltage Detect Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define SPC_LP_CFG_CORE_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORE_LVDE_SHIFT)) & SPC_LP_CFG_CORE_LVDE_MASK)
|
|
|
|
#define SPC_LP_CFG_SYS_LVDE_MASK (0x2000000U)
|
|
#define SPC_LP_CFG_SYS_LVDE_SHIFT (25U)
|
|
/*! SYS_LVDE - System Low Voltage Detect Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define SPC_LP_CFG_SYS_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_SYS_LVDE_SHIFT)) & SPC_LP_CFG_SYS_LVDE_MASK)
|
|
|
|
#define SPC_LP_CFG_SYS_HVDE_MASK (0x10000000U)
|
|
#define SPC_LP_CFG_SYS_HVDE_SHIFT (28U)
|
|
/*! SYS_HVDE - System High Voltage Detect Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define SPC_LP_CFG_SYS_HVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_SYS_HVDE_SHIFT)) & SPC_LP_CFG_SYS_HVDE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name LP_CFG1 - Low Power Mode Configuration 1 */
|
|
/*! @{ */
|
|
|
|
#define SPC_LP_CFG1_SOC_CNTRL_MASK (0xFFFFFFFFU)
|
|
#define SPC_LP_CFG1_SOC_CNTRL_SHIFT (0U)
|
|
/*! SOC_CNTRL - Low-Power Configuration Chip Control */
|
|
#define SPC_LP_CFG1_SOC_CNTRL(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG1_SOC_CNTRL_SHIFT)) & SPC_LP_CFG1_SOC_CNTRL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name LPWKUP_DELAY - Low Power Wake-Up Delay */
|
|
/*! @{ */
|
|
|
|
#define SPC_LPWKUP_DELAY_LPWKUP_DELAY_MASK (0xFFFFU)
|
|
#define SPC_LPWKUP_DELAY_LPWKUP_DELAY_SHIFT (0U)
|
|
/*! LPWKUP_DELAY - Low-Power Wake-Up Delay */
|
|
#define SPC_LPWKUP_DELAY_LPWKUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPC_LPWKUP_DELAY_LPWKUP_DELAY_SHIFT)) & SPC_LPWKUP_DELAY_LPWKUP_DELAY_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ACTIVE_VDELAY - Active Voltage Trim Delay */
|
|
/*! @{ */
|
|
|
|
#define SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_MASK (0xFFFFU)
|
|
#define SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_SHIFT (0U)
|
|
/*! ACTIVE_VDELAY - Active Voltage Delay */
|
|
#define SPC_ACTIVE_VDELAY_ACTIVE_VDELAY(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_SHIFT)) & SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name VD_STAT - Voltage Detect Status */
|
|
/*! @{ */
|
|
|
|
#define SPC_VD_STAT_COREVDD_LVDF_MASK (0x1U)
|
|
#define SPC_VD_STAT_COREVDD_LVDF_SHIFT (0U)
|
|
/*! COREVDD_LVDF - Core Low-Voltage Detect Flag
|
|
* 0b0..Event not detected
|
|
* 0b1..Event detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define SPC_VD_STAT_COREVDD_LVDF(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_COREVDD_LVDF_SHIFT)) & SPC_VD_STAT_COREVDD_LVDF_MASK)
|
|
|
|
#define SPC_VD_STAT_SYSVDD_LVDF_MASK (0x2U)
|
|
#define SPC_VD_STAT_SYSVDD_LVDF_SHIFT (1U)
|
|
/*! SYSVDD_LVDF - System Low-Voltage Detect Flag
|
|
* 0b0..Event not detected
|
|
* 0b1..Event detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define SPC_VD_STAT_SYSVDD_LVDF(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_SYSVDD_LVDF_SHIFT)) & SPC_VD_STAT_SYSVDD_LVDF_MASK)
|
|
|
|
#define SPC_VD_STAT_SYSVDD_HVDF_MASK (0x20U)
|
|
#define SPC_VD_STAT_SYSVDD_HVDF_SHIFT (5U)
|
|
/*! SYSVDD_HVDF - System HVD Flag
|
|
* 0b0..Event not detected
|
|
* 0b1..Event detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define SPC_VD_STAT_SYSVDD_HVDF(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_SYSVDD_HVDF_SHIFT)) & SPC_VD_STAT_SYSVDD_HVDF_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name VD_CORE_CFG - Core Voltage Detect Configuration */
|
|
/*! @{ */
|
|
|
|
#define SPC_VD_CORE_CFG_LVDRE_MASK (0x1U)
|
|
#define SPC_VD_CORE_CFG_LVDRE_SHIFT (0U)
|
|
/*! LVDRE - Core LVD Reset Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define SPC_VD_CORE_CFG_LVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_LVDRE_SHIFT)) & SPC_VD_CORE_CFG_LVDRE_MASK)
|
|
|
|
#define SPC_VD_CORE_CFG_LVDIE_MASK (0x2U)
|
|
#define SPC_VD_CORE_CFG_LVDIE_SHIFT (1U)
|
|
/*! LVDIE - Core LVD Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define SPC_VD_CORE_CFG_LVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_LVDIE_SHIFT)) & SPC_VD_CORE_CFG_LVDIE_MASK)
|
|
|
|
#define SPC_VD_CORE_CFG_LOCK_MASK (0x10000U)
|
|
#define SPC_VD_CORE_CFG_LOCK_SHIFT (16U)
|
|
/*! LOCK - Core Voltage Detect Reset Enable Lock
|
|
* 0b0..Allow
|
|
* 0b1..Deny
|
|
*/
|
|
#define SPC_VD_CORE_CFG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_LOCK_SHIFT)) & SPC_VD_CORE_CFG_LOCK_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name VD_SYS_CFG - System Voltage Detect Configuration */
|
|
/*! @{ */
|
|
|
|
#define SPC_VD_SYS_CFG_LVDRE_MASK (0x1U)
|
|
#define SPC_VD_SYS_CFG_LVDRE_SHIFT (0U)
|
|
/*! LVDRE - System LVD Reset Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define SPC_VD_SYS_CFG_LVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LVDRE_SHIFT)) & SPC_VD_SYS_CFG_LVDRE_MASK)
|
|
|
|
#define SPC_VD_SYS_CFG_LVDIE_MASK (0x2U)
|
|
#define SPC_VD_SYS_CFG_LVDIE_SHIFT (1U)
|
|
/*! LVDIE - System LVD Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define SPC_VD_SYS_CFG_LVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LVDIE_SHIFT)) & SPC_VD_SYS_CFG_LVDIE_MASK)
|
|
|
|
#define SPC_VD_SYS_CFG_HVDRE_MASK (0x4U)
|
|
#define SPC_VD_SYS_CFG_HVDRE_SHIFT (2U)
|
|
/*! HVDRE - System HVD Reset Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define SPC_VD_SYS_CFG_HVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_HVDRE_SHIFT)) & SPC_VD_SYS_CFG_HVDRE_MASK)
|
|
|
|
#define SPC_VD_SYS_CFG_HVDIE_MASK (0x8U)
|
|
#define SPC_VD_SYS_CFG_HVDIE_SHIFT (3U)
|
|
/*! HVDIE - System HVD Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define SPC_VD_SYS_CFG_HVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_HVDIE_SHIFT)) & SPC_VD_SYS_CFG_HVDIE_MASK)
|
|
|
|
#define SPC_VD_SYS_CFG_LVSEL_MASK (0x100U)
|
|
#define SPC_VD_SYS_CFG_LVSEL_SHIFT (8U)
|
|
/*! LVSEL - System Low-Voltage Level Select
|
|
* 0b0..Normal
|
|
* 0b1..Safe
|
|
*/
|
|
#define SPC_VD_SYS_CFG_LVSEL(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LVSEL_SHIFT)) & SPC_VD_SYS_CFG_LVSEL_MASK)
|
|
|
|
#define SPC_VD_SYS_CFG_LOCK_MASK (0x10000U)
|
|
#define SPC_VD_SYS_CFG_LOCK_SHIFT (16U)
|
|
/*! LOCK - System Voltage Detect Reset Enable Lock
|
|
* 0b0..Allow
|
|
* 0b1..Deny
|
|
*/
|
|
#define SPC_VD_SYS_CFG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LOCK_SHIFT)) & SPC_VD_SYS_CFG_LOCK_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name EVD_CFG - External Voltage Domain Configuration */
|
|
/*! @{ */
|
|
|
|
#define SPC_EVD_CFG_EVDISO_MASK (0x7U)
|
|
#define SPC_EVD_CFG_EVDISO_SHIFT (0U)
|
|
/*! EVDISO - External Voltage Domain Isolation */
|
|
#define SPC_EVD_CFG_EVDISO(x) (((uint32_t)(((uint32_t)(x)) << SPC_EVD_CFG_EVDISO_SHIFT)) & SPC_EVD_CFG_EVDISO_MASK)
|
|
|
|
#define SPC_EVD_CFG_EVDLPISO_MASK (0x700U)
|
|
#define SPC_EVD_CFG_EVDLPISO_SHIFT (8U)
|
|
/*! EVDLPISO - External Voltage Domain Low-Power Isolation */
|
|
#define SPC_EVD_CFG_EVDLPISO(x) (((uint32_t)(((uint32_t)(x)) << SPC_EVD_CFG_EVDLPISO_SHIFT)) & SPC_EVD_CFG_EVDLPISO_MASK)
|
|
|
|
#define SPC_EVD_CFG_EVDSTAT_MASK (0x70000U)
|
|
#define SPC_EVD_CFG_EVDSTAT_SHIFT (16U)
|
|
/*! EVDSTAT - External Voltage Domain Status */
|
|
#define SPC_EVD_CFG_EVDSTAT(x) (((uint32_t)(((uint32_t)(x)) << SPC_EVD_CFG_EVDSTAT_SHIFT)) & SPC_EVD_CFG_EVDSTAT_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group SPC_Register_Masks */
|
|
|
|
|
|
/* SPC - Peripheral instance base addresses */
|
|
/** Peripheral SPC0 base address */
|
|
#define SPC0_BASE (0x40090000u)
|
|
/** Peripheral SPC0 base pointer */
|
|
#define SPC0 ((SPC_Type *)SPC0_BASE)
|
|
/** Array initializer of SPC peripheral base addresses */
|
|
#define SPC_BASE_ADDRS { SPC0_BASE }
|
|
/** Array initializer of SPC peripheral base pointers */
|
|
#define SPC_BASE_PTRS { SPC0 }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group SPC_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- SYSCON Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer
|
|
* @{
|
|
*/
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/** SYSCON - Register Layout Typedef */
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typedef struct {
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uint8_t RESERVED_0[512];
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__IO uint32_t REMAP; /**< AHB Matrix Remap Control, offset: 0x200 */
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uint8_t RESERVED_1[12];
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__IO uint32_t AHBMATPRIO; /**< AHB Matrix Priority Control, offset: 0x210 */
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uint8_t RESERVED_2[40];
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__IO uint32_t CPU0NSTCKCAL; /**< Non-Secure CPU0 System Tick Calibration, offset: 0x23C */
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uint8_t RESERVED_3[8];
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__IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x248 */
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uint8_t RESERVED_4[300];
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__IO uint32_t SLOWCLKDIV; /**< SLOW_CLK Clock Divider, offset: 0x378 */
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uint8_t RESERVED_5[4];
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__IO uint32_t AHBCLKDIV; /**< System Clock Divider, offset: 0x380 */
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uint8_t RESERVED_6[120];
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__IO uint32_t CLKUNLOCK; /**< Clock Configuration Unlock, offset: 0x3FC */
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__IO uint32_t NVM_CTRL; /**< NVM Control, offset: 0x400 */
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uint32_t ROMCR; /**< ROM Wait State, offset: 0x404 */
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uint8_t RESERVED_7[1028];
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__I uint32_t CPUSTAT; /**< CPU Status, offset: 0x80C */
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uint8_t RESERVED_8[20];
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__IO uint32_t LPCAC_CTRL; /**< LPCAC Control, offset: 0x824 */
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uint8_t RESERVED_9[272];
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__IO uint32_t PWM0SUBCTL; /**< PWM0 Submodule Control, offset: 0x938 */
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uint8_t RESERVED_10[4];
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__IO uint32_t CTIMERGLOBALSTARTEN; /**< CTIMER Global Start Enable, offset: 0x940 */
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__IO uint32_t RAM_CTRL; /**< RAM Control, offset: 0x944 */
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uint8_t RESERVED_11[536];
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__IO uint32_t GRAY_CODE_LSB; /**< Gray to Binary Converter Gray Code [31:0], offset: 0xB60 */
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__IO uint32_t GRAY_CODE_MSB; /**< Gray to Binary Converter Gray Code [41:32], offset: 0xB64 */
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__I uint32_t BINARY_CODE_LSB; /**< Gray to Binary Converter Binary Code [31:0], offset: 0xB68 */
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__I uint32_t BINARY_CODE_MSB; /**< Gray to Binary Converter Binary Code [41:32], offset: 0xB6C */
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uint8_t RESERVED_12[720];
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__I uint32_t OVP_PAD_STATE; /**< OVP_PAD_STATE, offset: 0xE40 */
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__I uint32_t PROBE_STATE; /**< PROBE_STATE, offset: 0xE44 */
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__I uint32_t FT_STATE_A; /**< FT_STATE_A, offset: 0xE48 */
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__I uint32_t ROP_STATE; /**< ROP State Register, offset: 0xE4C */
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uint8_t RESERVED_13[8];
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__IO uint32_t SRAM_XEN; /**< RAM XEN Control, offset: 0xE58 */
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__IO uint32_t SRAM_XEN_DP; /**< RAM XEN Control (Duplicate), offset: 0xE5C */
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uint8_t RESERVED_14[32];
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__I uint32_t ELS_OTP_LC_STATE; /**< Life Cycle State Register, offset: 0xE80 */
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__I uint32_t ELS_OTP_LC_STATE_DP; /**< Life Cycle State Register (Duplicate), offset: 0xE84 */
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uint8_t RESERVED_15[280];
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__IO uint32_t DEBUG_LOCK_EN; /**< Control Write Access to Security, offset: 0xFA0 */
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__IO uint32_t DEBUG_FEATURES; /**< Cortex Debug Features Control, offset: 0xFA4 */
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__IO uint32_t DEBUG_FEATURES_DP; /**< Cortex Debug Features Control (Duplicate), offset: 0xFA8 */
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uint8_t RESERVED_16[8];
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__IO uint32_t SWD_ACCESS_CPU0; /**< CPU0 Software Debug Access, offset: 0xFB4 */
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uint8_t RESERVED_17[8];
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__IO uint32_t DEBUG_AUTH_BEACON; /**< Debug Authentication BEACON, offset: 0xFC0 */
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uint8_t RESERVED_18[44];
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__I uint32_t JTAG_ID; /**< JTAG Chip ID, offset: 0xFF0 */
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__I uint32_t DEVICE_TYPE; /**< Device Type, offset: 0xFF4 */
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__I uint32_t DEVICE_ID0; /**< Device ID, offset: 0xFF8 */
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__I uint32_t DIEID; /**< Chip Revision ID and Number, offset: 0xFFC */
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} SYSCON_Type;
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/* ----------------------------------------------------------------------------
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-- SYSCON Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup SYSCON_Register_Masks SYSCON Register Masks
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* @{
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*/
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/*! @name REMAP - AHB Matrix Remap Control */
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/*! @{ */
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#define SYSCON_REMAP_CPU0_SBUS_MASK (0x3U)
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#define SYSCON_REMAP_CPU0_SBUS_SHIFT (0U)
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/*! CPU0_SBUS - RAMX0 address remap for CPU System bus
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* 0b00..RAMX0: 0x04000000 - 0x04001fff
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* 0b01..RAMX0: 0x20006000 - 0x20007fff
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*/
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#define SYSCON_REMAP_CPU0_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REMAP_CPU0_SBUS_SHIFT)) & SYSCON_REMAP_CPU0_SBUS_MASK)
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#define SYSCON_REMAP_DMA0_MASK (0xCU)
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#define SYSCON_REMAP_DMA0_SHIFT (2U)
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/*! DMA0 - RAMX0 address remap for DMA0
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* 0b00..RAMX0: 0x04000000 - 0x04001fff
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* 0b01..RAMX0: same alias space as CPU0_SBUS
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*/
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#define SYSCON_REMAP_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REMAP_DMA0_SHIFT)) & SYSCON_REMAP_DMA0_MASK)
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#define SYSCON_REMAP_USB0_MASK (0x30U)
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#define SYSCON_REMAP_USB0_SHIFT (4U)
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/*! USB0 - RAMX0 address remap for USB0
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* 0b00..RAMX0: 0x04000000 - 0x04001fff
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* 0b01..RAMX0: same alias space as CPU0_SBUS
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*/
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#define SYSCON_REMAP_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REMAP_USB0_SHIFT)) & SYSCON_REMAP_USB0_MASK)
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#define SYSCON_REMAP_LOCK_MASK (0x80000000U)
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#define SYSCON_REMAP_LOCK_SHIFT (31U)
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/*! LOCK - This 1-bit field provides a mechanism to limit writes to the this register to protect its
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* contents. Once set, this bit remains asserted until the next reset.
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* 0b0..This register is not locked and can be altered.
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* 0b1..This register is locked and cannot be altered.
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*/
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#define SYSCON_REMAP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REMAP_LOCK_SHIFT)) & SYSCON_REMAP_LOCK_MASK)
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/*! @} */
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/*! @name AHBMATPRIO - AHB Matrix Priority Control */
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/*! @{ */
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#define SYSCON_AHBMATPRIO_CPU0_CBUS_MASK (0x3U)
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#define SYSCON_AHBMATPRIO_CPU0_CBUS_SHIFT (0U)
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/*! CPU0_CBUS - CPU0 C-AHB bus master priority level
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* 0b00..level 0
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* 0b01..level 1
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* 0b10..level 2
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* 0b11..level 3
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*/
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#define SYSCON_AHBMATPRIO_CPU0_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_CPU0_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_CPU0_CBUS_MASK)
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#define SYSCON_AHBMATPRIO_CPU0_SBUS_MASK (0xCU)
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#define SYSCON_AHBMATPRIO_CPU0_SBUS_SHIFT (2U)
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/*! CPU0_SBUS - CPU0 S-AHB bus master priority level
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* 0b00..level 0
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* 0b01..level 1
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* 0b10..level 2
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* 0b11..level 3
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*/
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#define SYSCON_AHBMATPRIO_CPU0_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_CPU0_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_CPU0_SBUS_MASK)
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#define SYSCON_AHBMATPRIO_DMA0_MASK (0x300U)
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#define SYSCON_AHBMATPRIO_DMA0_SHIFT (8U)
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/*! DMA0 - DMA0 controller bus master priority level
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* 0b00..level 0
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* 0b01..level 1
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* 0b10..level 2
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* 0b11..level 3
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*/
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#define SYSCON_AHBMATPRIO_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_DMA0_SHIFT)) & SYSCON_AHBMATPRIO_DMA0_MASK)
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#define SYSCON_AHBMATPRIO_USB_FS_ENET_MASK (0x3000000U)
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#define SYSCON_AHBMATPRIO_USB_FS_ENET_SHIFT (24U)
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/*! USB_FS_ENET - USB-FS bus master priority level
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* 0b00..level 0
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* 0b01..level 1
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* 0b10..level 2
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* 0b11..level 3
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*/
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#define SYSCON_AHBMATPRIO_USB_FS_ENET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_USB_FS_ENET_SHIFT)) & SYSCON_AHBMATPRIO_USB_FS_ENET_MASK)
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/*! @} */
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/*! @name CPU0NSTCKCAL - Non-Secure CPU0 System Tick Calibration */
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/*! @{ */
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#define SYSCON_CPU0NSTCKCAL_TENMS_MASK (0xFFFFFFU)
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#define SYSCON_CPU0NSTCKCAL_TENMS_SHIFT (0U)
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/*! TENMS - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the
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* value reads as zero, the calibration value is not known.
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*/
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#define SYSCON_CPU0NSTCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_TENMS_SHIFT)) & SYSCON_CPU0NSTCKCAL_TENMS_MASK)
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#define SYSCON_CPU0NSTCKCAL_SKEW_MASK (0x1000000U)
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#define SYSCON_CPU0NSTCKCAL_SKEW_SHIFT (24U)
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/*! SKEW - Indicates whether the TENMS value is exact.
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* 0b0..TENMS value is exact
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* 0b1..TENMS value is not exact or not given
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*/
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#define SYSCON_CPU0NSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_SKEW_SHIFT)) & SYSCON_CPU0NSTCKCAL_SKEW_MASK)
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#define SYSCON_CPU0NSTCKCAL_NOREF_MASK (0x2000000U)
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#define SYSCON_CPU0NSTCKCAL_NOREF_SHIFT (25U)
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/*! NOREF - Indicates whether the device provides a reference clock to the processor.
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* 0b0..Reference clock is provided
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* 0b1..No reference clock is provided
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*/
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#define SYSCON_CPU0NSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_NOREF_SHIFT)) & SYSCON_CPU0NSTCKCAL_NOREF_MASK)
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/*! @} */
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/*! @name NMISRC - NMI Source Select */
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/*! @{ */
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#define SYSCON_NMISRC_IRQCPU0_MASK (0xFFU)
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#define SYSCON_NMISRC_IRQCPU0_SHIFT (0U)
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/*! IRQCPU0 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for CPU0, if enabled by NMIENCPU0. */
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#define SYSCON_NMISRC_IRQCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU0_SHIFT)) & SYSCON_NMISRC_IRQCPU0_MASK)
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#define SYSCON_NMISRC_NMIENCPU0_MASK (0x80000000U)
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#define SYSCON_NMISRC_NMIENCPU0_SHIFT (31U)
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/*! NMIENCPU0 - Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU0.
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* 0b1..Enable.
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* 0b0..Disable.
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*/
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#define SYSCON_NMISRC_NMIENCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU0_SHIFT)) & SYSCON_NMISRC_NMIENCPU0_MASK)
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/*! @} */
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/*! @name SLOWCLKDIV - SLOW_CLK Clock Divider */
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/*! @{ */
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#define SYSCON_SLOWCLKDIV_RESET_MASK (0x20000000U)
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#define SYSCON_SLOWCLKDIV_RESET_SHIFT (29U)
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/*! RESET - Resets the divider counter
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* 0b1..Divider is reset
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* 0b0..Divider is not reset
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*/
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#define SYSCON_SLOWCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SLOWCLKDIV_RESET_SHIFT)) & SYSCON_SLOWCLKDIV_RESET_MASK)
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#define SYSCON_SLOWCLKDIV_HALT_MASK (0x40000000U)
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#define SYSCON_SLOWCLKDIV_HALT_SHIFT (30U)
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/*! HALT - Halts the divider counter
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* 0b1..Divider clock is stopped
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* 0b0..Divider clock is running
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*/
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#define SYSCON_SLOWCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SLOWCLKDIV_HALT_SHIFT)) & SYSCON_SLOWCLKDIV_HALT_MASK)
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#define SYSCON_SLOWCLKDIV_UNSTAB_MASK (0x80000000U)
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#define SYSCON_SLOWCLKDIV_UNSTAB_SHIFT (31U)
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/*! UNSTAB - Divider status flag
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* 0b1..Clock frequency is not stable
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* 0b0..Divider clock is stable
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*/
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#define SYSCON_SLOWCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SLOWCLKDIV_UNSTAB_SHIFT)) & SYSCON_SLOWCLKDIV_UNSTAB_MASK)
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/*! @} */
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/*! @name AHBCLKDIV - System Clock Divider */
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/*! @{ */
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#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU)
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#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U)
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/*! DIV - Clock divider value */
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#define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)
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#define SYSCON_AHBCLKDIV_UNSTAB_MASK (0x80000000U)
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#define SYSCON_AHBCLKDIV_UNSTAB_SHIFT (31U)
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/*! UNSTAB - Divider status flag
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* 0b1..Clock frequency is not stable
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* 0b0..Divider clock is stable
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*/
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#define SYSCON_AHBCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_UNSTAB_SHIFT)) & SYSCON_AHBCLKDIV_UNSTAB_MASK)
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/*! @} */
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/*! @name CLKUNLOCK - Clock Configuration Unlock */
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/*! @{ */
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#define SYSCON_CLKUNLOCK_UNLOCK_MASK (0x1U)
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#define SYSCON_CLKUNLOCK_UNLOCK_SHIFT (0U)
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/*! UNLOCK - Controls clock configuration registers access (for example, MRCC_xxx_CLKDIV, MRCC_xxx_CLKSEL, MRCC_GLB_xxx)
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* 0b1..Freezes all clock configuration registers update.
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* 0b0..Updates are allowed to all clock configuration registers
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*/
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#define SYSCON_CLKUNLOCK_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKUNLOCK_UNLOCK_SHIFT)) & SYSCON_CLKUNLOCK_UNLOCK_MASK)
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/*! @} */
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/*! @name NVM_CTRL - NVM Control */
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/*! @{ */
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#define SYSCON_NVM_CTRL_DIS_FLASH_SPEC_MASK (0x1U)
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#define SYSCON_NVM_CTRL_DIS_FLASH_SPEC_SHIFT (0U)
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/*! DIS_FLASH_SPEC - Flash speculation control
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* 0b0..Enables flash speculation
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* 0b1..Disables flash speculation
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*/
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#define SYSCON_NVM_CTRL_DIS_FLASH_SPEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_FLASH_SPEC_SHIFT)) & SYSCON_NVM_CTRL_DIS_FLASH_SPEC_MASK)
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#define SYSCON_NVM_CTRL_DIS_DATA_SPEC_MASK (0x2U)
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#define SYSCON_NVM_CTRL_DIS_DATA_SPEC_SHIFT (1U)
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/*! DIS_DATA_SPEC - Flash data speculation control
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* 0b0..Enables data speculation
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* 0b1..Disables data speculation
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*/
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#define SYSCON_NVM_CTRL_DIS_DATA_SPEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_DATA_SPEC_SHIFT)) & SYSCON_NVM_CTRL_DIS_DATA_SPEC_MASK)
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#define SYSCON_NVM_CTRL_FLASH_STALL_EN_MASK (0x400U)
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#define SYSCON_NVM_CTRL_FLASH_STALL_EN_SHIFT (10U)
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/*! FLASH_STALL_EN - FLASH stall on busy control
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* 0b0..No stall on FLASH busy
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* 0b1..Stall on FLASH busy
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*/
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#define SYSCON_NVM_CTRL_FLASH_STALL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_FLASH_STALL_EN_SHIFT)) & SYSCON_NVM_CTRL_FLASH_STALL_EN_MASK)
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#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_MASK (0x10000U)
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#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_SHIFT (16U)
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/*! DIS_MBECC_ERR_INST
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* 0b0..Enables bus error on multi-bit ECC error for instruction
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* 0b1..Disables bus error on multi-bit ECC error for instruction
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*/
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#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_SHIFT)) & SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_MASK)
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#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK (0x20000U)
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#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_SHIFT (17U)
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/*! DIS_MBECC_ERR_DATA
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* 0b0..Enables bus error on multi-bit ECC error for data
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* 0b1..Disables bus error on multi-bit ECC error for data
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*/
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#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_SHIFT)) & SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK)
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/*! @} */
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/*! @name CPUSTAT - CPU Status */
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/*! @{ */
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#define SYSCON_CPUSTAT_CPU0SLEEPING_MASK (0x1U)
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#define SYSCON_CPUSTAT_CPU0SLEEPING_SHIFT (0U)
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/*! CPU0SLEEPING - CPU0 sleeping state
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* 0b1..CPU is sleeping
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* 0b0..CPU is not sleeping
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*/
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#define SYSCON_CPUSTAT_CPU0SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUSTAT_CPU0SLEEPING_SHIFT)) & SYSCON_CPUSTAT_CPU0SLEEPING_MASK)
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#define SYSCON_CPUSTAT_CPU0LOCKUP_MASK (0x4U)
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#define SYSCON_CPUSTAT_CPU0LOCKUP_SHIFT (2U)
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/*! CPU0LOCKUP - CPU0 lockup state
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* 0b1..CPU is in lockup
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* 0b0..CPU is not in lockup
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*/
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#define SYSCON_CPUSTAT_CPU0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUSTAT_CPU0LOCKUP_SHIFT)) & SYSCON_CPUSTAT_CPU0LOCKUP_MASK)
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/*! @} */
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/*! @name LPCAC_CTRL - LPCAC Control */
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/*! @{ */
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#define SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK (0x1U)
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#define SYSCON_LPCAC_CTRL_DIS_LPCAC_SHIFT (0U)
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/*! DIS_LPCAC - Disables/enables the cache function.
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* 0b0..Enabled
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* 0b1..Disabled
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*/
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#define SYSCON_LPCAC_CTRL_DIS_LPCAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_DIS_LPCAC_SHIFT)) & SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK)
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#define SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK (0x2U)
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#define SYSCON_LPCAC_CTRL_CLR_LPCAC_SHIFT (1U)
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/*! CLR_LPCAC - Clears the cache function.
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* 0b0..Unclears the cache
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* 0b1..Clears the cache
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*/
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#define SYSCON_LPCAC_CTRL_CLR_LPCAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_CLR_LPCAC_SHIFT)) & SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK)
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#define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK (0x4U)
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#define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_SHIFT (2U)
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/*! FRC_NO_ALLOC - Forces no allocation.
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* 0b0..Forces allocation
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* 0b1..Forces no allocation
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*/
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#define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_SHIFT)) & SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK)
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#define SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_MASK (0x10U)
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#define SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_SHIFT (4U)
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/*! DIS_LPCAC_WTBF - Disable LPCAC Write Through Buffer.
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* 0b1..Disables write through buffer
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* 0b0..Enables write through buffer
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*/
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#define SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_SHIFT)) & SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_MASK)
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#define SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_MASK (0x20U)
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#define SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_SHIFT (5U)
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/*! LIM_LPCAC_WTBF - Limit LPCAC Write Through Buffer.
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* 0b1..Write buffer enabled when transaction is cacheable and bufferable
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* 0b0..Write buffer enabled when transaction is bufferable.
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*/
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#define SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_SHIFT)) & SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_MASK)
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#define SYSCON_LPCAC_CTRL_LPCAC_XOM_MASK (0x80U)
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#define SYSCON_LPCAC_CTRL_LPCAC_XOM_SHIFT (7U)
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/*! LPCAC_XOM - LPCAC XOM(eXecute-Only-Memory) attribute control
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* 0b1..Enabled.
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* 0b0..Disabled.
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*/
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#define SYSCON_LPCAC_CTRL_LPCAC_XOM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_LPCAC_XOM_SHIFT)) & SYSCON_LPCAC_CTRL_LPCAC_XOM_MASK)
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#define SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ_MASK (0x100U)
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#define SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ_SHIFT (8U)
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/*! LPCAC_MEM_REQ - Request LPCAC memories.
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* 0b1..Configure shared memories RAMX1 as LPCAC memories, write one lock.
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* 0b0..Configure shared memories RAMX1 as general memories.
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*/
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#define SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ_SHIFT)) & SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ_MASK)
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/*! @} */
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/*! @name PWM0SUBCTL - PWM0 Submodule Control */
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/*! @{ */
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#define SYSCON_PWM0SUBCTL_CLK0_EN_MASK (0x1U)
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#define SYSCON_PWM0SUBCTL_CLK0_EN_SHIFT (0U)
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/*! CLK0_EN - Enables PWM0 SUB Clock0
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* 0b1..Enable
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* 0b0..Disable
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*/
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#define SYSCON_PWM0SUBCTL_CLK0_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK0_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK0_EN_MASK)
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#define SYSCON_PWM0SUBCTL_CLK1_EN_MASK (0x2U)
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#define SYSCON_PWM0SUBCTL_CLK1_EN_SHIFT (1U)
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/*! CLK1_EN - Enables PWM0 SUB Clock1
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* 0b1..Enable
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* 0b0..Disable
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*/
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#define SYSCON_PWM0SUBCTL_CLK1_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK1_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK1_EN_MASK)
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#define SYSCON_PWM0SUBCTL_CLK2_EN_MASK (0x4U)
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#define SYSCON_PWM0SUBCTL_CLK2_EN_SHIFT (2U)
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/*! CLK2_EN - Enables PWM0 SUB Clock2
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* 0b1..Enable
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* 0b0..Disable
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*/
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#define SYSCON_PWM0SUBCTL_CLK2_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK2_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK2_EN_MASK)
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#define SYSCON_PWM0SUBCTL_CLK3_EN_MASK (0x8U)
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#define SYSCON_PWM0SUBCTL_CLK3_EN_SHIFT (3U)
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/*! CLK3_EN - Enables PWM0 SUB Clock3
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* 0b1..Enable
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* 0b0..Disable
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*/
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#define SYSCON_PWM0SUBCTL_CLK3_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK3_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK3_EN_MASK)
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/*! @} */
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/*! @name CTIMERGLOBALSTARTEN - CTIMER Global Start Enable */
|
|
/*! @{ */
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#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_MASK (0x1U)
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|
#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_SHIFT (0U)
|
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/*! CTIMER0_CLK_EN - Enables the CTIMER0 function clock
|
|
* 0b1..Enable
|
|
* 0b0..Disable
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|
*/
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|
#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_MASK)
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#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_MASK (0x2U)
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|
#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_SHIFT (1U)
|
|
/*! CTIMER1_CLK_EN - Enables the CTIMER1 function clock
|
|
* 0b1..Enable
|
|
* 0b0..Disable
|
|
*/
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|
#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_MASK)
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#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_MASK (0x4U)
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|
#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_SHIFT (2U)
|
|
/*! CTIMER2_CLK_EN - Enables the CTIMER2 function clock
|
|
* 0b1..Enable
|
|
* 0b0..Disable
|
|
*/
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|
#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_MASK)
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/*! @} */
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/*! @name RAM_CTRL - RAM Control */
|
|
/*! @{ */
|
|
|
|
#define SYSCON_RAM_CTRL_RAMA_ECC_ENABLE_MASK (0x1U)
|
|
#define SYSCON_RAM_CTRL_RAMA_ECC_ENABLE_SHIFT (0U)
|
|
/*! RAMA_ECC_ENABLE - RAMA ECC enable
|
|
* 0b1..ECC is enabled
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|
* 0b0..ECC is disabled
|
|
*/
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|
#define SYSCON_RAM_CTRL_RAMA_ECC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RAM_CTRL_RAMA_ECC_ENABLE_SHIFT)) & SYSCON_RAM_CTRL_RAMA_ECC_ENABLE_MASK)
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#define SYSCON_RAM_CTRL_RAMA_CG_OVERRIDE_MASK (0x10000U)
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|
#define SYSCON_RAM_CTRL_RAMA_CG_OVERRIDE_SHIFT (16U)
|
|
/*! RAMA_CG_OVERRIDE - RAMA bank clock gating control, only avaiable when RAMA_ECC_ENABLE = 0.
|
|
* 0b1..Auto clock gating feature is disabled
|
|
* 0b0..Memory bank clock is gated automatically if no access more than 16 clock cycles
|
|
*/
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|
#define SYSCON_RAM_CTRL_RAMA_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RAM_CTRL_RAMA_CG_OVERRIDE_SHIFT)) & SYSCON_RAM_CTRL_RAMA_CG_OVERRIDE_MASK)
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#define SYSCON_RAM_CTRL_RAMX_CG_OVERRIDE_MASK (0x20000U)
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#define SYSCON_RAM_CTRL_RAMX_CG_OVERRIDE_SHIFT (17U)
|
|
/*! RAMX_CG_OVERRIDE - RAMX bank clock gating control
|
|
* 0b1..Auto clock gating feature is disabled
|
|
* 0b0..Memory bank clock is gated automatically if no access more than 16 clock cycles
|
|
*/
|
|
#define SYSCON_RAM_CTRL_RAMX_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RAM_CTRL_RAMX_CG_OVERRIDE_SHIFT)) & SYSCON_RAM_CTRL_RAMX_CG_OVERRIDE_MASK)
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/*! @} */
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|
/*! @name GRAY_CODE_LSB - Gray to Binary Converter Gray Code [31:0] */
|
|
/*! @{ */
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|
|
|
#define SYSCON_GRAY_CODE_LSB_code_gray_31_0_MASK (0xFFFFFFFFU)
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|
#define SYSCON_GRAY_CODE_LSB_code_gray_31_0_SHIFT (0U)
|
|
/*! code_gray_31_0 - Gray code [31:0] */
|
|
#define SYSCON_GRAY_CODE_LSB_code_gray_31_0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GRAY_CODE_LSB_code_gray_31_0_SHIFT)) & SYSCON_GRAY_CODE_LSB_code_gray_31_0_MASK)
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|
/*! @} */
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|
|
/*! @name GRAY_CODE_MSB - Gray to Binary Converter Gray Code [41:32] */
|
|
/*! @{ */
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|
|
|
#define SYSCON_GRAY_CODE_MSB_code_gray_41_32_MASK (0x3FFU)
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|
#define SYSCON_GRAY_CODE_MSB_code_gray_41_32_SHIFT (0U)
|
|
/*! code_gray_41_32 - Gray code [41:32] */
|
|
#define SYSCON_GRAY_CODE_MSB_code_gray_41_32(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GRAY_CODE_MSB_code_gray_41_32_SHIFT)) & SYSCON_GRAY_CODE_MSB_code_gray_41_32_MASK)
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|
/*! @} */
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|
|
|
/*! @name BINARY_CODE_LSB - Gray to Binary Converter Binary Code [31:0] */
|
|
/*! @{ */
|
|
|
|
#define SYSCON_BINARY_CODE_LSB_code_bin_31_0_MASK (0xFFFFFFFFU)
|
|
#define SYSCON_BINARY_CODE_LSB_code_bin_31_0_SHIFT (0U)
|
|
/*! code_bin_31_0 - Binary code [31:0] */
|
|
#define SYSCON_BINARY_CODE_LSB_code_bin_31_0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BINARY_CODE_LSB_code_bin_31_0_SHIFT)) & SYSCON_BINARY_CODE_LSB_code_bin_31_0_MASK)
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|
/*! @} */
|
|
|
|
/*! @name BINARY_CODE_MSB - Gray to Binary Converter Binary Code [41:32] */
|
|
/*! @{ */
|
|
|
|
#define SYSCON_BINARY_CODE_MSB_code_bin_41_32_MASK (0x3FFU)
|
|
#define SYSCON_BINARY_CODE_MSB_code_bin_41_32_SHIFT (0U)
|
|
/*! code_bin_41_32 - Binary code [41:32] */
|
|
#define SYSCON_BINARY_CODE_MSB_code_bin_41_32(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BINARY_CODE_MSB_code_bin_41_32_SHIFT)) & SYSCON_BINARY_CODE_MSB_code_bin_41_32_MASK)
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|
/*! @} */
|
|
|
|
/*! @name OVP_PAD_STATE - OVP_PAD_STATE */
|
|
/*! @{ */
|
|
|
|
#define SYSCON_OVP_PAD_STATE_OVP_PAD_STATE_MASK (0xFFFFFFFFU)
|
|
#define SYSCON_OVP_PAD_STATE_OVP_PAD_STATE_SHIFT (0U)
|
|
/*! OVP_PAD_STATE - OVP_PAD_STATE */
|
|
#define SYSCON_OVP_PAD_STATE_OVP_PAD_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_OVP_PAD_STATE_OVP_PAD_STATE_SHIFT)) & SYSCON_OVP_PAD_STATE_OVP_PAD_STATE_MASK)
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|
/*! @} */
|
|
|
|
/*! @name PROBE_STATE - PROBE_STATE */
|
|
/*! @{ */
|
|
|
|
#define SYSCON_PROBE_STATE_PROBE_STATE_MASK (0xFFFFFFFFU)
|
|
#define SYSCON_PROBE_STATE_PROBE_STATE_SHIFT (0U)
|
|
/*! PROBE_STATE - PROBE_STATE */
|
|
#define SYSCON_PROBE_STATE_PROBE_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PROBE_STATE_PROBE_STATE_SHIFT)) & SYSCON_PROBE_STATE_PROBE_STATE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FT_STATE_A - FT_STATE_A */
|
|
/*! @{ */
|
|
|
|
#define SYSCON_FT_STATE_A_FT_STATE_A_MASK (0xFFFFFFFFU)
|
|
#define SYSCON_FT_STATE_A_FT_STATE_A_SHIFT (0U)
|
|
/*! FT_STATE_A - FT_STATE_A */
|
|
#define SYSCON_FT_STATE_A_FT_STATE_A(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FT_STATE_A_FT_STATE_A_SHIFT)) & SYSCON_FT_STATE_A_FT_STATE_A_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ROP_STATE - ROP State Register */
|
|
/*! @{ */
|
|
|
|
#define SYSCON_ROP_STATE_ROP_STATE_MASK (0xFFFFFFFFU)
|
|
#define SYSCON_ROP_STATE_ROP_STATE_SHIFT (0U)
|
|
/*! ROP_STATE - ROP state */
|
|
#define SYSCON_ROP_STATE_ROP_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ROP_STATE_ROP_STATE_SHIFT)) & SYSCON_ROP_STATE_ROP_STATE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SRAM_XEN - RAM XEN Control */
|
|
/*! @{ */
|
|
|
|
#define SYSCON_SRAM_XEN_RAMX0_XEN_MASK (0x1U)
|
|
#define SYSCON_SRAM_XEN_RAMX0_XEN_SHIFT (0U)
|
|
/*! RAMX0_XEN - RAMX0 Execute permission control.
|
|
* 0b1..Execute permission is enabled, R/W/X are enabled.
|
|
* 0b0..Execute permission is disabled, R/W are enabled.
|
|
*/
|
|
#define SYSCON_SRAM_XEN_RAMX0_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_RAMX0_XEN_SHIFT)) & SYSCON_SRAM_XEN_RAMX0_XEN_MASK)
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|
|
|
#define SYSCON_SRAM_XEN_RAMX1_XEN_MASK (0x2U)
|
|
#define SYSCON_SRAM_XEN_RAMX1_XEN_SHIFT (1U)
|
|
/*! RAMX1_XEN - RAMX1 Execute permission control.
|
|
* 0b1..Execute permission is enabled, R/W/X are enabled.
|
|
* 0b0..Execute permission is disabled, R/W are enabled.
|
|
*/
|
|
#define SYSCON_SRAM_XEN_RAMX1_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_RAMX1_XEN_SHIFT)) & SYSCON_SRAM_XEN_RAMX1_XEN_MASK)
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|
|
#define SYSCON_SRAM_XEN_RAMA0_XEN_MASK (0x4U)
|
|
#define SYSCON_SRAM_XEN_RAMA0_XEN_SHIFT (2U)
|
|
/*! RAMA0_XEN - RAMA0 Execute permission control.
|
|
* 0b1..Execute permission is enabled, R/W/X are enabled.
|
|
* 0b0..Execute permission is disabled, R/W are enabled.
|
|
*/
|
|
#define SYSCON_SRAM_XEN_RAMA0_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_RAMA0_XEN_SHIFT)) & SYSCON_SRAM_XEN_RAMA0_XEN_MASK)
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|
|
|
#define SYSCON_SRAM_XEN_RAMA1_XEN_MASK (0x8U)
|
|
#define SYSCON_SRAM_XEN_RAMA1_XEN_SHIFT (3U)
|
|
/*! RAMA1_XEN - RAMAx (excepts RAMA0) Execute permission control.
|
|
* 0b1..Execute permission is enabled, R/W/X are enabled.
|
|
* 0b0..Execute permission is disabled, R/W are enabled.
|
|
*/
|
|
#define SYSCON_SRAM_XEN_RAMA1_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_RAMA1_XEN_SHIFT)) & SYSCON_SRAM_XEN_RAMA1_XEN_MASK)
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|
|
|
#define SYSCON_SRAM_XEN_LOCK_MASK (0x80000000U)
|
|
#define SYSCON_SRAM_XEN_LOCK_SHIFT (31U)
|
|
/*! LOCK - This 1-bit field provides a mechanism to limit writes to the this register (and
|
|
* SRAM_XEN_DP) to protect its contents. Once set, this bit remains asserted until the next reset.
|
|
* 0b0..This register is not locked and can be altered.
|
|
* 0b1..This register is locked and cannot be altered.
|
|
*/
|
|
#define SYSCON_SRAM_XEN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_LOCK_SHIFT)) & SYSCON_SRAM_XEN_LOCK_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SRAM_XEN_DP - RAM XEN Control (Duplicate) */
|
|
/*! @{ */
|
|
|
|
#define SYSCON_SRAM_XEN_DP_RAMX0_XEN_MASK (0x1U)
|
|
#define SYSCON_SRAM_XEN_DP_RAMX0_XEN_SHIFT (0U)
|
|
/*! RAMX0_XEN - Refer to SRAM_XEN for more details. */
|
|
#define SYSCON_SRAM_XEN_DP_RAMX0_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_DP_RAMX0_XEN_SHIFT)) & SYSCON_SRAM_XEN_DP_RAMX0_XEN_MASK)
|
|
|
|
#define SYSCON_SRAM_XEN_DP_RAMX1_XEN_MASK (0x2U)
|
|
#define SYSCON_SRAM_XEN_DP_RAMX1_XEN_SHIFT (1U)
|
|
/*! RAMX1_XEN - Refer to SRAM_XEN for more details. */
|
|
#define SYSCON_SRAM_XEN_DP_RAMX1_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_DP_RAMX1_XEN_SHIFT)) & SYSCON_SRAM_XEN_DP_RAMX1_XEN_MASK)
|
|
|
|
#define SYSCON_SRAM_XEN_DP_RAMA0_XEN_MASK (0x4U)
|
|
#define SYSCON_SRAM_XEN_DP_RAMA0_XEN_SHIFT (2U)
|
|
/*! RAMA0_XEN - Refer to SRAM_XEN for more details. */
|
|
#define SYSCON_SRAM_XEN_DP_RAMA0_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_DP_RAMA0_XEN_SHIFT)) & SYSCON_SRAM_XEN_DP_RAMA0_XEN_MASK)
|
|
|
|
#define SYSCON_SRAM_XEN_DP_RAMA1_XEN_MASK (0x8U)
|
|
#define SYSCON_SRAM_XEN_DP_RAMA1_XEN_SHIFT (3U)
|
|
/*! RAMA1_XEN - Refer to SRAM_XEN for more details. */
|
|
#define SYSCON_SRAM_XEN_DP_RAMA1_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_DP_RAMA1_XEN_SHIFT)) & SYSCON_SRAM_XEN_DP_RAMA1_XEN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ELS_OTP_LC_STATE - Life Cycle State Register */
|
|
/*! @{ */
|
|
|
|
#define SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_MASK (0xFFU)
|
|
#define SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_SHIFT (0U)
|
|
/*! OTP_LC_STATE - OTP life cycle state */
|
|
#define SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_SHIFT)) & SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ELS_OTP_LC_STATE_DP - Life Cycle State Register (Duplicate) */
|
|
/*! @{ */
|
|
|
|
#define SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_MASK (0xFFU)
|
|
#define SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_SHIFT (0U)
|
|
/*! OTP_LC_STATE_DP - OTP life cycle state */
|
|
#define SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_SHIFT)) & SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DEBUG_LOCK_EN - Control Write Access to Security */
|
|
/*! @{ */
|
|
|
|
#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK (0xFU)
|
|
#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT (0U)
|
|
/*! LOCK_ALL - Controls write access to the security registers
|
|
* 0b1010..Enables write access to all registers
|
|
* 0b0000..Any other value than b1010: disables write access to all registers
|
|
*/
|
|
#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT)) & SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DEBUG_FEATURES - Cortex Debug Features Control */
|
|
/*! @{ */
|
|
|
|
#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK (0x3U)
|
|
#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT (0U)
|
|
/*! CPU0_DBGEN - CPU0 invasive debug control
|
|
* 0b01..Disables debug
|
|
* 0b10..Enables debug
|
|
*/
|
|
#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK)
|
|
|
|
#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK (0xCU)
|
|
#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT (2U)
|
|
/*! CPU0_NIDEN - CPU0 non-invasive debug control
|
|
* 0b01..Disables debug
|
|
* 0b10..Enables debug
|
|
*/
|
|
#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DEBUG_FEATURES_DP - Cortex Debug Features Control (Duplicate) */
|
|
/*! @{ */
|
|
|
|
#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK (0x3U)
|
|
#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT (0U)
|
|
/*! CPU0_DBGEN - CPU0 invasive debug control
|
|
* 0b01..Disables debug
|
|
* 0b10..Enables debug
|
|
*/
|
|
#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK)
|
|
|
|
#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK (0xCU)
|
|
#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT (2U)
|
|
/*! CPU0_NIDEN - CPU0 non-invasive debug control
|
|
* 0b01..Disables debug
|
|
* 0b10..Enables debug
|
|
*/
|
|
#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SWD_ACCESS_CPU0 - CPU0 Software Debug Access */
|
|
/*! @{ */
|
|
|
|
#define SYSCON_SWD_ACCESS_CPU0_SEC_CODE_MASK (0xFFFFFFFFU)
|
|
#define SYSCON_SWD_ACCESS_CPU0_SEC_CODE_SHIFT (0U)
|
|
/*! SEC_CODE - CPU0 SWD-AP: 0x12345678
|
|
* 0b00010010001101000101011001111000..Value to write to enable CPU0 SWD access. Reading back register is read as 0xA.
|
|
* 0b00000000000000000000000000000000..CPU0 DAP is not allowed. Reading back register is read as 0x5.
|
|
*/
|
|
#define SYSCON_SWD_ACCESS_CPU0_SEC_CODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SWD_ACCESS_CPU0_SEC_CODE_SHIFT)) & SYSCON_SWD_ACCESS_CPU0_SEC_CODE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DEBUG_AUTH_BEACON - Debug Authentication BEACON */
|
|
/*! @{ */
|
|
|
|
#define SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK (0xFFFFFFFFU)
|
|
#define SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT (0U)
|
|
/*! BEACON - Sets by the debug authentication code in ROM to pass the debug beacons (Credential
|
|
* Beacon and Authentication Beacon) to the application code.
|
|
*/
|
|
#define SYSCON_DEBUG_AUTH_BEACON_BEACON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT)) & SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name JTAG_ID - JTAG Chip ID */
|
|
/*! @{ */
|
|
|
|
#define SYSCON_JTAG_ID_JTAG_ID_MASK (0xFFFFFFFFU)
|
|
#define SYSCON_JTAG_ID_JTAG_ID_SHIFT (0U)
|
|
/*! JTAG_ID - Indicates the device ID */
|
|
#define SYSCON_JTAG_ID_JTAG_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_JTAG_ID_JTAG_ID_SHIFT)) & SYSCON_JTAG_ID_JTAG_ID_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DEVICE_TYPE - Device Type */
|
|
/*! @{ */
|
|
|
|
#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_MASK (0xFFFFFFFFU)
|
|
#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_SHIFT (0U)
|
|
/*! DEVICE_TYPE - Indicates DEVICE TYPE. */
|
|
#define SYSCON_DEVICE_TYPE_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_TYPE_DEVICE_TYPE_SHIFT)) & SYSCON_DEVICE_TYPE_DEVICE_TYPE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DEVICE_ID0 - Device ID */
|
|
/*! @{ */
|
|
|
|
#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK (0xF00000U)
|
|
#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT (20U)
|
|
/*! ROM_REV_MINOR - ROM revision. */
|
|
#define SYSCON_DEVICE_ID0_ROM_REV_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT)) & SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DIEID - Chip Revision ID and Number */
|
|
/*! @{ */
|
|
|
|
#define SYSCON_DIEID_MINOR_REVISION_MASK (0xFU)
|
|
#define SYSCON_DIEID_MINOR_REVISION_SHIFT (0U)
|
|
/*! MINOR_REVISION - Chip minor revision */
|
|
#define SYSCON_DIEID_MINOR_REVISION(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MINOR_REVISION_SHIFT)) & SYSCON_DIEID_MINOR_REVISION_MASK)
|
|
|
|
#define SYSCON_DIEID_MAJOR_REVISION_MASK (0xF0U)
|
|
#define SYSCON_DIEID_MAJOR_REVISION_SHIFT (4U)
|
|
/*! MAJOR_REVISION - Chip major revision */
|
|
#define SYSCON_DIEID_MAJOR_REVISION(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MAJOR_REVISION_SHIFT)) & SYSCON_DIEID_MAJOR_REVISION_MASK)
|
|
|
|
#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK (0xFFFFF00U)
|
|
#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT (8U)
|
|
/*! MCO_NUM_IN_DIE_ID - Chip number */
|
|
#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT)) & SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group SYSCON_Register_Masks */
|
|
|
|
|
|
/* SYSCON - Peripheral instance base addresses */
|
|
/** Peripheral SYSCON base address */
|
|
#define SYSCON_BASE (0x40091000u)
|
|
/** Peripheral SYSCON base pointer */
|
|
#define SYSCON ((SYSCON_Type *)SYSCON_BASE)
|
|
/** Array initializer of SYSCON peripheral base addresses */
|
|
#define SYSCON_BASE_ADDRS { SYSCON_BASE }
|
|
/** Array initializer of SYSCON peripheral base pointers */
|
|
#define SYSCON_BASE_PTRS { SYSCON }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group SYSCON_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- USB Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** USB - Register Layout Typedef */
|
|
typedef struct {
|
|
__I uint8_t PERID; /**< Peripheral ID, offset: 0x0 */
|
|
uint8_t RESERVED_0[3];
|
|
__I uint8_t IDCOMP; /**< Peripheral ID Complement, offset: 0x4 */
|
|
uint8_t RESERVED_1[3];
|
|
__I uint8_t REV; /**< Peripheral Revision, offset: 0x8 */
|
|
uint8_t RESERVED_2[19];
|
|
__IO uint8_t OTGCTL; /**< OTG Control, offset: 0x1C */
|
|
uint8_t RESERVED_3[99];
|
|
__IO uint8_t ISTAT; /**< Interrupt Status, offset: 0x80 */
|
|
uint8_t RESERVED_4[3];
|
|
__IO uint8_t INTEN; /**< Interrupt Enable, offset: 0x84 */
|
|
uint8_t RESERVED_5[3];
|
|
__IO uint8_t ERRSTAT; /**< Error Interrupt Status, offset: 0x88 */
|
|
uint8_t RESERVED_6[3];
|
|
__IO uint8_t ERREN; /**< Error Interrupt Enable, offset: 0x8C */
|
|
uint8_t RESERVED_7[3];
|
|
__I uint8_t STAT; /**< Status, offset: 0x90 */
|
|
uint8_t RESERVED_8[3];
|
|
__IO uint8_t CTL; /**< Control, offset: 0x94 */
|
|
uint8_t RESERVED_9[3];
|
|
__IO uint8_t ADDR; /**< Address, offset: 0x98 */
|
|
uint8_t RESERVED_10[3];
|
|
__IO uint8_t BDTPAGE1; /**< BDT Page 1, offset: 0x9C */
|
|
uint8_t RESERVED_11[3];
|
|
__I uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */
|
|
uint8_t RESERVED_12[3];
|
|
__I uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */
|
|
uint8_t RESERVED_13[11];
|
|
__IO uint8_t BDTPAGE2; /**< BDT Page 2, offset: 0xB0 */
|
|
uint8_t RESERVED_14[3];
|
|
__IO uint8_t BDTPAGE3; /**< BDT Page 3, offset: 0xB4 */
|
|
uint8_t RESERVED_15[11];
|
|
struct { /* offset: 0xC0, array step: 0x4 */
|
|
__IO uint8_t ENDPT; /**< Endpoint Control, array offset: 0xC0, array step: 0x4 */
|
|
uint8_t RESERVED_0[3];
|
|
} ENDPOINT[16];
|
|
__IO uint8_t USBCTRL; /**< USB Control, offset: 0x100 */
|
|
uint8_t RESERVED_16[3];
|
|
__I uint8_t OBSERVE; /**< USB OTG Observe, offset: 0x104 */
|
|
uint8_t RESERVED_17[3];
|
|
__IO uint8_t CONTROL; /**< USB OTG Control, offset: 0x108 */
|
|
uint8_t RESERVED_18[3];
|
|
__IO uint8_t USBTRC0; /**< USB Transceiver Control 0, offset: 0x10C */
|
|
uint8_t RESERVED_19[23];
|
|
uint8_t KEEP_ALIVE_CTRL_RSVD; /**< Reserved, offset: 0x124 */
|
|
uint8_t RESERVED_20[3];
|
|
uint8_t KEEP_ALIVE_WKCTRL_RSVD; /**< Reserved, offset: 0x128 */
|
|
uint8_t RESERVED_21[3];
|
|
__IO uint8_t MISCCTRL; /**< Miscellaneous Control, offset: 0x12C */
|
|
uint8_t RESERVED_22[3];
|
|
__IO uint8_t STALL_IL_DIS; /**< Peripheral Mode Stall Disable for Endpoints 7 to 0 in IN Direction, offset: 0x130 */
|
|
uint8_t RESERVED_23[3];
|
|
__IO uint8_t STALL_IH_DIS; /**< Peripheral Mode Stall Disable for Endpoints 15 to 8 in IN Direction, offset: 0x134 */
|
|
uint8_t RESERVED_24[3];
|
|
__IO uint8_t STALL_OL_DIS; /**< Peripheral Mode Stall Disable for Endpoints 7 to 0 in OUT Direction, offset: 0x138 */
|
|
uint8_t RESERVED_25[3];
|
|
__IO uint8_t STALL_OH_DIS; /**< Peripheral Mode Stall Disable for Endpoints 15 to 8 in OUT Direction, offset: 0x13C */
|
|
uint8_t RESERVED_26[3];
|
|
__IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock Recovery Control, offset: 0x140 */
|
|
uint8_t RESERVED_27[3];
|
|
__IO uint8_t CLK_RECOVER_IRC_EN; /**< FIRC Oscillator Enable, offset: 0x144 */
|
|
uint8_t RESERVED_28[15];
|
|
__IO uint8_t CLK_RECOVER_INT_EN; /**< Clock Recovery Combined Interrupt Enable, offset: 0x154 */
|
|
uint8_t RESERVED_29[7];
|
|
__IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock Recovery Separated Interrupt Status, offset: 0x15C */
|
|
} USB_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- USB Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup USB_Register_Masks USB Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name PERID - Peripheral ID */
|
|
/*! @{ */
|
|
|
|
#define USB_PERID_ID_MASK (0x3FU)
|
|
#define USB_PERID_ID_SHIFT (0U)
|
|
/*! ID - Peripheral Identification */
|
|
#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name IDCOMP - Peripheral ID Complement */
|
|
/*! @{ */
|
|
|
|
#define USB_IDCOMP_NID_MASK (0x3FU)
|
|
#define USB_IDCOMP_NID_SHIFT (0U)
|
|
/*! NID - Negative Peripheral ID */
|
|
#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name REV - Peripheral Revision */
|
|
/*! @{ */
|
|
|
|
#define USB_REV_REV_MASK (0xFFU)
|
|
#define USB_REV_REV_SHIFT (0U)
|
|
/*! REV - Revision */
|
|
#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name OTGCTL - OTG Control */
|
|
/*! @{ */
|
|
|
|
#define USB_OTGCTL_DPHIGH_MASK (0x80U)
|
|
#define USB_OTGCTL_DPHIGH_SHIFT (7U)
|
|
/*! DPHIGH - D+ Data Line Pullup Resistor Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ISTAT - Interrupt Status */
|
|
/*! @{ */
|
|
|
|
#define USB_ISTAT_USBRST_MASK (0x1U)
|
|
#define USB_ISTAT_USBRST_SHIFT (0U)
|
|
/*! USBRST - USB Reset Flag
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
|
|
|
|
#define USB_ISTAT_ERROR_MASK (0x2U)
|
|
#define USB_ISTAT_ERROR_SHIFT (1U)
|
|
/*! ERROR - Error Flag
|
|
* 0b0..Error did not occur
|
|
* 0b1..Error occurred
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
|
|
|
|
#define USB_ISTAT_SOFTOK_MASK (0x4U)
|
|
#define USB_ISTAT_SOFTOK_SHIFT (2U)
|
|
/*! SOFTOK - Start Of Frame (SOF) Token Flag
|
|
* 0b0..Did not receive
|
|
* 0b1..Received
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
|
|
|
|
#define USB_ISTAT_TOKDNE_MASK (0x8U)
|
|
#define USB_ISTAT_TOKDNE_SHIFT (3U)
|
|
/*! TOKDNE - Current Token Processing Flag
|
|
* 0b0..Not processed
|
|
* 0b1..Processed
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
|
|
|
|
#define USB_ISTAT_SLEEP_MASK (0x10U)
|
|
#define USB_ISTAT_SLEEP_SHIFT (4U)
|
|
/*! SLEEP - Sleep Flag
|
|
* 0b0..Interrupt did not occur
|
|
* 0b1..Interrupt occurred
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
|
|
|
|
#define USB_ISTAT_RESUME_MASK (0x20U)
|
|
#define USB_ISTAT_RESUME_SHIFT (5U)
|
|
/*! RESUME - Resume Flag
|
|
* 0b0..Interrupt did not occur
|
|
* 0b1..Interrupt occurred
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
|
|
|
|
#define USB_ISTAT_STALL_MASK (0x80U)
|
|
#define USB_ISTAT_STALL_SHIFT (7U)
|
|
/*! STALL - Stall Interrupt Flag
|
|
* 0b0..Interrupt did not occur
|
|
* 0b1..Interrupt occurred
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name INTEN - Interrupt Enable */
|
|
/*! @{ */
|
|
|
|
#define USB_INTEN_USBRSTEN_MASK (0x1U)
|
|
#define USB_INTEN_USBRSTEN_SHIFT (0U)
|
|
/*! USBRSTEN - USBRST Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
|
|
|
|
#define USB_INTEN_ERROREN_MASK (0x2U)
|
|
#define USB_INTEN_ERROREN_SHIFT (1U)
|
|
/*! ERROREN - ERROR Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
|
|
|
|
#define USB_INTEN_SOFTOKEN_MASK (0x4U)
|
|
#define USB_INTEN_SOFTOKEN_SHIFT (2U)
|
|
/*! SOFTOKEN - SOFTOK Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
|
|
|
|
#define USB_INTEN_TOKDNEEN_MASK (0x8U)
|
|
#define USB_INTEN_TOKDNEEN_SHIFT (3U)
|
|
/*! TOKDNEEN - TOKDNE Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
|
|
|
|
#define USB_INTEN_SLEEPEN_MASK (0x10U)
|
|
#define USB_INTEN_SLEEPEN_SHIFT (4U)
|
|
/*! SLEEPEN - SLEEP Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
|
|
|
|
#define USB_INTEN_RESUMEEN_MASK (0x20U)
|
|
#define USB_INTEN_RESUMEEN_SHIFT (5U)
|
|
/*! RESUMEEN - RESUME Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
|
|
|
|
#define USB_INTEN_STALLEN_MASK (0x80U)
|
|
#define USB_INTEN_STALLEN_SHIFT (7U)
|
|
/*! STALLEN - STALL Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ERRSTAT - Error Interrupt Status */
|
|
/*! @{ */
|
|
|
|
#define USB_ERRSTAT_PIDERR_MASK (0x1U)
|
|
#define USB_ERRSTAT_PIDERR_SHIFT (0U)
|
|
/*! PIDERR - PID Error Flag
|
|
* 0b0..Did not fail
|
|
* 0b1..Failed
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
|
|
|
|
#define USB_ERRSTAT_CRC5EOF_MASK (0x2U)
|
|
#define USB_ERRSTAT_CRC5EOF_SHIFT (1U)
|
|
/*! CRC5EOF - CRC5 Error or End of Frame Error Flag
|
|
* 0b0..Interrupt did not occur
|
|
* 0b1..Interrupt occurred
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK)
|
|
|
|
#define USB_ERRSTAT_CRC16_MASK (0x4U)
|
|
#define USB_ERRSTAT_CRC16_SHIFT (2U)
|
|
/*! CRC16 - CRC16 Error Flag
|
|
* 0b0..Not rejected
|
|
* 0b1..Rejected
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
|
|
|
|
#define USB_ERRSTAT_DFN8_MASK (0x8U)
|
|
#define USB_ERRSTAT_DFN8_SHIFT (3U)
|
|
/*! DFN8 - Data Field Not 8 Bits Flag
|
|
* 0b0..Integer number of bytes
|
|
* 0b1..Not an integer number of bytes
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
|
|
|
|
#define USB_ERRSTAT_BTOERR_MASK (0x10U)
|
|
#define USB_ERRSTAT_BTOERR_SHIFT (4U)
|
|
/*! BTOERR - Bus Turnaround Timeout Error Flag
|
|
* 0b0..Not timed out
|
|
* 0b1..Timed out
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
|
|
|
|
#define USB_ERRSTAT_DMAERR_MASK (0x20U)
|
|
#define USB_ERRSTAT_DMAERR_SHIFT (5U)
|
|
/*! DMAERR - DMA Access Error Flag
|
|
* 0b0..Interrupt did not occur
|
|
* 0b1..Interrupt occurred
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
|
|
|
|
#define USB_ERRSTAT_OWNERR_MASK (0x40U)
|
|
#define USB_ERRSTAT_OWNERR_SHIFT (6U)
|
|
/*! OWNERR - BD Unavailable Error Flag
|
|
* 0b0..Interrupt did not occur
|
|
* 0b1..Interrupt occurred
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define USB_ERRSTAT_OWNERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_OWNERR_SHIFT)) & USB_ERRSTAT_OWNERR_MASK)
|
|
|
|
#define USB_ERRSTAT_BTSERR_MASK (0x80U)
|
|
#define USB_ERRSTAT_BTSERR_SHIFT (7U)
|
|
/*! BTSERR - Bit Stuff Error Flag
|
|
* 0b0..Packet not rejected due to the error
|
|
* 0b1..Packet rejected due to the error
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ERREN - Error Interrupt Enable */
|
|
/*! @{ */
|
|
|
|
#define USB_ERREN_PIDERREN_MASK (0x1U)
|
|
#define USB_ERREN_PIDERREN_SHIFT (0U)
|
|
/*! PIDERREN - PIDERR Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
|
|
|
|
#define USB_ERREN_CRC5EOFEN_MASK (0x2U)
|
|
#define USB_ERREN_CRC5EOFEN_SHIFT (1U)
|
|
/*! CRC5EOFEN - CRC5/EOF Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
|
|
|
|
#define USB_ERREN_CRC16EN_MASK (0x4U)
|
|
#define USB_ERREN_CRC16EN_SHIFT (2U)
|
|
/*! CRC16EN - CRC16 Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
|
|
|
|
#define USB_ERREN_DFN8EN_MASK (0x8U)
|
|
#define USB_ERREN_DFN8EN_SHIFT (3U)
|
|
/*! DFN8EN - DFN8 (Data Field Not Integer Number of Bytes) Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
|
|
|
|
#define USB_ERREN_BTOERREN_MASK (0x10U)
|
|
#define USB_ERREN_BTOERREN_SHIFT (4U)
|
|
/*! BTOERREN - BTOERR (Bus Timeout Error) Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
|
|
|
|
#define USB_ERREN_DMAERREN_MASK (0x20U)
|
|
#define USB_ERREN_DMAERREN_SHIFT (5U)
|
|
/*! DMAERREN - DMAERR Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
|
|
|
|
#define USB_ERREN_OWNERREN_MASK (0x40U)
|
|
#define USB_ERREN_OWNERREN_SHIFT (6U)
|
|
/*! OWNERREN - OWNERR Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define USB_ERREN_OWNERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_OWNERREN_SHIFT)) & USB_ERREN_OWNERREN_MASK)
|
|
|
|
#define USB_ERREN_BTSERREN_MASK (0x80U)
|
|
#define USB_ERREN_BTSERREN_SHIFT (7U)
|
|
/*! BTSERREN - BTSERR (Bit Stuff Error) Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name STAT - Status */
|
|
/*! @{ */
|
|
|
|
#define USB_STAT_ODD_MASK (0x4U)
|
|
#define USB_STAT_ODD_SHIFT (2U)
|
|
/*! ODD - Odd Bank
|
|
* 0b0..Not in the odd bank
|
|
* 0b1..In the odd bank
|
|
*/
|
|
#define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
|
|
|
|
#define USB_STAT_TX_MASK (0x8U)
|
|
#define USB_STAT_TX_SHIFT (3U)
|
|
/*! TX - Transmit Indicator
|
|
* 0b0..Receive
|
|
* 0b1..Transmit
|
|
*/
|
|
#define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
|
|
|
|
#define USB_STAT_ENDP_MASK (0xF0U)
|
|
#define USB_STAT_ENDP_SHIFT (4U)
|
|
/*! ENDP - Endpoint address */
|
|
#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CTL - Control */
|
|
/*! @{ */
|
|
|
|
#define USB_CTL_USBENSOFEN_MASK (0x1U)
|
|
#define USB_CTL_USBENSOFEN_SHIFT (0U)
|
|
/*! USBENSOFEN - USB Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
|
|
|
|
#define USB_CTL_ODDRST_MASK (0x2U)
|
|
#define USB_CTL_ODDRST_SHIFT (1U)
|
|
/*! ODDRST - Odd Reset */
|
|
#define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
|
|
|
|
#define USB_CTL_RESUME_MASK (0x4U)
|
|
#define USB_CTL_RESUME_SHIFT (2U)
|
|
/*! RESUME - Resume */
|
|
#define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK)
|
|
|
|
#define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U)
|
|
#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U)
|
|
/*! TXSUSPENDTOKENBUSY - TXD Suspend And Token Busy */
|
|
#define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
|
|
|
|
#define USB_CTL_SE0_MASK (0x40U)
|
|
#define USB_CTL_SE0_SHIFT (6U)
|
|
/*! SE0 - Live USB Single-Ended Zero signal */
|
|
#define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ADDR - Address */
|
|
/*! @{ */
|
|
|
|
#define USB_ADDR_ADDR_MASK (0x7FU)
|
|
#define USB_ADDR_ADDR_SHIFT (0U)
|
|
/*! ADDR - USB Address */
|
|
#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name BDTPAGE1 - BDT Page 1 */
|
|
/*! @{ */
|
|
|
|
#define USB_BDTPAGE1_BDTBA_MASK (0xFEU)
|
|
#define USB_BDTPAGE1_BDTBA_SHIFT (1U)
|
|
/*! BDTBA - BDT Base Address */
|
|
#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FRMNUML - Frame Number Register Low */
|
|
/*! @{ */
|
|
|
|
#define USB_FRMNUML_FRM_MASK (0xFFU)
|
|
#define USB_FRMNUML_FRM_SHIFT (0U)
|
|
/*! FRM - Frame Number, Bits 0-7 */
|
|
#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FRMNUMH - Frame Number Register High */
|
|
/*! @{ */
|
|
|
|
#define USB_FRMNUMH_FRM_MASK (0x7U)
|
|
#define USB_FRMNUMH_FRM_SHIFT (0U)
|
|
/*! FRM - Frame Number, Bits 8-10 */
|
|
#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name BDTPAGE2 - BDT Page 2 */
|
|
/*! @{ */
|
|
|
|
#define USB_BDTPAGE2_BDTBA_MASK (0xFFU)
|
|
#define USB_BDTPAGE2_BDTBA_SHIFT (0U)
|
|
/*! BDTBA - BDT Base Address */
|
|
#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name BDTPAGE3 - BDT Page 3 */
|
|
/*! @{ */
|
|
|
|
#define USB_BDTPAGE3_BDTBA_MASK (0xFFU)
|
|
#define USB_BDTPAGE3_BDTBA_SHIFT (0U)
|
|
/*! BDTBA - BDT Base Address */
|
|
#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ENDPT - Endpoint Control */
|
|
/*! @{ */
|
|
|
|
#define USB_ENDPT_EPHSHK_MASK (0x1U)
|
|
#define USB_ENDPT_EPHSHK_SHIFT (0U)
|
|
/*! EPHSHK - Endpoint Handshaking Enable */
|
|
#define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
|
|
|
|
#define USB_ENDPT_EPSTALL_MASK (0x2U)
|
|
#define USB_ENDPT_EPSTALL_SHIFT (1U)
|
|
/*! EPSTALL - Endpoint Stalled */
|
|
#define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
|
|
|
|
#define USB_ENDPT_EPTXEN_MASK (0x4U)
|
|
#define USB_ENDPT_EPTXEN_SHIFT (2U)
|
|
/*! EPTXEN - Endpoint for TX transfers enable */
|
|
#define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
|
|
|
|
#define USB_ENDPT_EPRXEN_MASK (0x8U)
|
|
#define USB_ENDPT_EPRXEN_SHIFT (3U)
|
|
/*! EPRXEN - Endpoint for RX transfers enable */
|
|
#define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
|
|
|
|
#define USB_ENDPT_EPCTLDIS_MASK (0x10U)
|
|
#define USB_ENDPT_EPCTLDIS_SHIFT (4U)
|
|
/*! EPCTLDIS - Control Transfer Disable
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of USB_ENDPT */
|
|
#define USB_ENDPT_COUNT (16U)
|
|
|
|
/*! @name USBCTRL - USB Control */
|
|
/*! @{ */
|
|
|
|
#define USB_USBCTRL_DPDM_LANE_REVERSE_MASK (0x4U)
|
|
#define USB_USBCTRL_DPDM_LANE_REVERSE_SHIFT (2U)
|
|
/*! DPDM_LANE_REVERSE - DP and DM Lane Reversal Control
|
|
* 0b0..Standard USB DP and DM package pin assignment
|
|
* 0b1..Reverse roles of USB DP and DM package pins
|
|
*/
|
|
#define USB_USBCTRL_DPDM_LANE_REVERSE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_DPDM_LANE_REVERSE_SHIFT)) & USB_USBCTRL_DPDM_LANE_REVERSE_MASK)
|
|
|
|
#define USB_USBCTRL_UARTSEL_MASK (0x10U)
|
|
#define USB_USBCTRL_UARTSEL_SHIFT (4U)
|
|
/*! UARTSEL - UART Select
|
|
* 0b0..USB DP and DM external package pins are used for USB signaling.
|
|
* 0b1..USB DP and DM external package pins are used for UART signaling.
|
|
*/
|
|
#define USB_USBCTRL_UARTSEL(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTSEL_SHIFT)) & USB_USBCTRL_UARTSEL_MASK)
|
|
|
|
#define USB_USBCTRL_UARTCHLS_MASK (0x20U)
|
|
#define USB_USBCTRL_UARTCHLS_SHIFT (5U)
|
|
/*! UARTCHLS - UART Signal Channel Select
|
|
* 0b0..USB DP and DM signals are used as UART TX/RX.
|
|
* 0b1..USB DP and DM signals are used as UART RX/TX.
|
|
*/
|
|
#define USB_USBCTRL_UARTCHLS(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTCHLS_SHIFT)) & USB_USBCTRL_UARTCHLS_MASK)
|
|
|
|
#define USB_USBCTRL_PDE_MASK (0x40U)
|
|
#define USB_USBCTRL_PDE_SHIFT (6U)
|
|
/*! PDE - Pulldown Enable
|
|
* 0b0..Disable on D+ and D-
|
|
* 0b1..Enable on D+ and D-
|
|
*/
|
|
#define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
|
|
|
|
#define USB_USBCTRL_SUSP_MASK (0x80U)
|
|
#define USB_USBCTRL_SUSP_SHIFT (7U)
|
|
/*! SUSP - Suspend
|
|
* 0b0..Not in Suspend state
|
|
* 0b1..In Suspend state
|
|
*/
|
|
#define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name OBSERVE - USB OTG Observe */
|
|
/*! @{ */
|
|
|
|
#define USB_OBSERVE_DMPD_MASK (0x10U)
|
|
#define USB_OBSERVE_DMPD_SHIFT (4U)
|
|
/*! DMPD - D- Pulldown
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
|
|
|
|
#define USB_OBSERVE_DPPD_MASK (0x40U)
|
|
#define USB_OBSERVE_DPPD_SHIFT (6U)
|
|
/*! DPPD - D+ Pulldown
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
|
|
|
|
#define USB_OBSERVE_DPPU_MASK (0x80U)
|
|
#define USB_OBSERVE_DPPU_SHIFT (7U)
|
|
/*! DPPU - D+ Pullup
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CONTROL - USB OTG Control */
|
|
/*! @{ */
|
|
|
|
#define USB_CONTROL_VBUS_SOURCE_SEL_MASK (0x1U)
|
|
#define USB_CONTROL_VBUS_SOURCE_SEL_SHIFT (0U)
|
|
/*! VBUS_SOURCE_SEL - VBUS Monitoring Source Select
|
|
* 0b0..Reserved
|
|
* 0b1..Resistive divider attached to a GPIO pin
|
|
*/
|
|
#define USB_CONTROL_VBUS_SOURCE_SEL(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_VBUS_SOURCE_SEL_SHIFT)) & USB_CONTROL_VBUS_SOURCE_SEL_MASK)
|
|
|
|
#define USB_CONTROL_SESS_VLD_MASK (0x2U)
|
|
#define USB_CONTROL_SESS_VLD_SHIFT (1U)
|
|
/*! SESS_VLD - VBUS Session Valid status
|
|
* 0b1..Above
|
|
* 0b0..Below
|
|
*/
|
|
#define USB_CONTROL_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_SESS_VLD_SHIFT)) & USB_CONTROL_SESS_VLD_MASK)
|
|
|
|
#define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U)
|
|
#define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U)
|
|
/*! DPPULLUPNONOTG - DP Pullup in Non-OTG Device Mode
|
|
* 0b0..Disable
|
|
* 0b1..Enabled
|
|
*/
|
|
#define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name USBTRC0 - USB Transceiver Control 0 */
|
|
/*! @{ */
|
|
|
|
#define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U)
|
|
#define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U)
|
|
/*! USB_RESUME_INT - USB Asynchronous Interrupt
|
|
* 0b0..Not generated
|
|
* 0b1..Generated because of the USB asynchronous interrupt
|
|
*/
|
|
#define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
|
|
|
|
#define USB_USBTRC0_SYNC_DET_MASK (0x2U)
|
|
#define USB_USBTRC0_SYNC_DET_SHIFT (1U)
|
|
/*! SYNC_DET - Synchronous USB Interrupt Detect
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
*/
|
|
#define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
|
|
|
|
#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U)
|
|
#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U)
|
|
/*! USB_CLK_RECOVERY_INT - Combined USB Clock Recovery interrupt status */
|
|
#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
|
|
|
|
#define USB_USBTRC0_VREDG_DET_MASK (0x8U)
|
|
#define USB_USBTRC0_VREDG_DET_SHIFT (3U)
|
|
/*! VREDG_DET - VREGIN Rising Edge Interrupt Detect
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
*/
|
|
#define USB_USBTRC0_VREDG_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VREDG_DET_SHIFT)) & USB_USBTRC0_VREDG_DET_MASK)
|
|
|
|
#define USB_USBTRC0_VFEDG_DET_MASK (0x10U)
|
|
#define USB_USBTRC0_VFEDG_DET_SHIFT (4U)
|
|
/*! VFEDG_DET - VREGIN Falling Edge Interrupt Detect
|
|
* 0b0..Not detected
|
|
* 0b1..Detected
|
|
*/
|
|
#define USB_USBTRC0_VFEDG_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VFEDG_DET_SHIFT)) & USB_USBTRC0_VFEDG_DET_MASK)
|
|
|
|
#define USB_USBTRC0_USBRESMEN_MASK (0x20U)
|
|
#define USB_USBTRC0_USBRESMEN_SHIFT (5U)
|
|
/*! USBRESMEN - Asynchronous Resume Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
|
|
|
|
#define USB_USBTRC0_VREGIN_STS_MASK (0x40U)
|
|
#define USB_USBTRC0_VREGIN_STS_SHIFT (6U)
|
|
/*! VREGIN_STS - VREGIN Status */
|
|
#define USB_USBTRC0_VREGIN_STS(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VREGIN_STS_SHIFT)) & USB_USBTRC0_VREGIN_STS_MASK)
|
|
|
|
#define USB_USBTRC0_USBRESET_MASK (0x80U)
|
|
#define USB_USBTRC0_USBRESET_SHIFT (7U)
|
|
/*! USBRESET - USB Reset
|
|
* 0b0..Normal USBFS operation
|
|
* 0b1..Returns USBFS to its reset state
|
|
*/
|
|
#define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MISCCTRL - Miscellaneous Control */
|
|
/*! @{ */
|
|
|
|
#define USB_MISCCTRL_OWNERRISODIS_MASK (0x4U)
|
|
#define USB_MISCCTRL_OWNERRISODIS_SHIFT (2U)
|
|
/*! OWNERRISODIS - OWN Error Detect for ISO IN and ISO OUT Disable
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define USB_MISCCTRL_OWNERRISODIS(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_OWNERRISODIS_SHIFT)) & USB_MISCCTRL_OWNERRISODIS_MASK)
|
|
|
|
#define USB_MISCCTRL_VREDG_EN_MASK (0x8U)
|
|
#define USB_MISCCTRL_VREDG_EN_SHIFT (3U)
|
|
/*! VREDG_EN - VREGIN Rising Edge Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define USB_MISCCTRL_VREDG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VREDG_EN_SHIFT)) & USB_MISCCTRL_VREDG_EN_MASK)
|
|
|
|
#define USB_MISCCTRL_VFEDG_EN_MASK (0x10U)
|
|
#define USB_MISCCTRL_VFEDG_EN_SHIFT (4U)
|
|
/*! VFEDG_EN - VREGIN Falling Edge Interrupt Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define USB_MISCCTRL_VFEDG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VFEDG_EN_SHIFT)) & USB_MISCCTRL_VFEDG_EN_MASK)
|
|
|
|
#define USB_MISCCTRL_STL_ADJ_EN_MASK (0x80U)
|
|
#define USB_MISCCTRL_STL_ADJ_EN_SHIFT (7U)
|
|
/*! STL_ADJ_EN - USB Peripheral Mode Stall Adjust Enable
|
|
* 0b0..If ENDPTn[END_STALL] = 1, both IN and OUT directions for the associated endpoint stalls.
|
|
* 0b1..If ENDPTn[END_STALL] = 1, the STALL_xx_DIS registers control which directions for the associated endpoint stalls.
|
|
*/
|
|
#define USB_MISCCTRL_STL_ADJ_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_STL_ADJ_EN_SHIFT)) & USB_MISCCTRL_STL_ADJ_EN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name STALL_IL_DIS - Peripheral Mode Stall Disable for Endpoints 7 to 0 in IN Direction */
|
|
/*! @{ */
|
|
|
|
#define USB_STALL_IL_DIS_STALL_I_DIS0_MASK (0x1U)
|
|
#define USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT (0U)
|
|
/*! STALL_I_DIS0 - Disable Endpoint 0 IN Direction
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define USB_STALL_IL_DIS_STALL_I_DIS0(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS0_MASK)
|
|
|
|
#define USB_STALL_IL_DIS_STALL_I_DIS1_MASK (0x2U)
|
|
#define USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT (1U)
|
|
/*! STALL_I_DIS1 - Disable Endpoint 1 IN Direction
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define USB_STALL_IL_DIS_STALL_I_DIS1(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS1_MASK)
|
|
|
|
#define USB_STALL_IL_DIS_STALL_I_DIS2_MASK (0x4U)
|
|
#define USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT (2U)
|
|
/*! STALL_I_DIS2 - Disable Endpoint 2 IN Direction
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define USB_STALL_IL_DIS_STALL_I_DIS2(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS2_MASK)
|
|
|
|
#define USB_STALL_IL_DIS_STALL_I_DIS3_MASK (0x8U)
|
|
#define USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT (3U)
|
|
/*! STALL_I_DIS3 - Disable Endpoint 3 IN Direction
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define USB_STALL_IL_DIS_STALL_I_DIS3(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS3_MASK)
|
|
|
|
#define USB_STALL_IL_DIS_STALL_I_DIS4_MASK (0x10U)
|
|
#define USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT (4U)
|
|
/*! STALL_I_DIS4 - Disable Endpoint 4 IN Direction
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define USB_STALL_IL_DIS_STALL_I_DIS4(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS4_MASK)
|
|
|
|
#define USB_STALL_IL_DIS_STALL_I_DIS5_MASK (0x20U)
|
|
#define USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT (5U)
|
|
/*! STALL_I_DIS5 - Disable Endpoint 5 IN Direction
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define USB_STALL_IL_DIS_STALL_I_DIS5(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS5_MASK)
|
|
|
|
#define USB_STALL_IL_DIS_STALL_I_DIS6_MASK (0x40U)
|
|
#define USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT (6U)
|
|
/*! STALL_I_DIS6 - Disable Endpoint 6 IN Direction
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define USB_STALL_IL_DIS_STALL_I_DIS6(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS6_MASK)
|
|
|
|
#define USB_STALL_IL_DIS_STALL_I_DIS7_MASK (0x80U)
|
|
#define USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT (7U)
|
|
/*! STALL_I_DIS7 - Disable Endpoint 7 IN Direction
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define USB_STALL_IL_DIS_STALL_I_DIS7(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS7_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name STALL_IH_DIS - Peripheral Mode Stall Disable for Endpoints 15 to 8 in IN Direction */
|
|
/*! @{ */
|
|
|
|
#define USB_STALL_IH_DIS_STALL_I_DIS8_MASK (0x1U)
|
|
#define USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT (0U)
|
|
/*! STALL_I_DIS8 - Disable Endpoint 8 IN Direction
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define USB_STALL_IH_DIS_STALL_I_DIS8(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS8_MASK)
|
|
|
|
#define USB_STALL_IH_DIS_STALL_I_DIS9_MASK (0x2U)
|
|
#define USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT (1U)
|
|
/*! STALL_I_DIS9 - Disable Endpoint 9 IN Direction
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define USB_STALL_IH_DIS_STALL_I_DIS9(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS9_MASK)
|
|
|
|
#define USB_STALL_IH_DIS_STALL_I_DIS10_MASK (0x4U)
|
|
#define USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT (2U)
|
|
/*! STALL_I_DIS10 - Disable Endpoint 10 IN Direction
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define USB_STALL_IH_DIS_STALL_I_DIS10(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS10_MASK)
|
|
|
|
#define USB_STALL_IH_DIS_STALL_I_DIS11_MASK (0x8U)
|
|
#define USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT (3U)
|
|
/*! STALL_I_DIS11 - Disable Endpoint 11 IN Direction
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define USB_STALL_IH_DIS_STALL_I_DIS11(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS11_MASK)
|
|
|
|
#define USB_STALL_IH_DIS_STALL_I_DIS12_MASK (0x10U)
|
|
#define USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT (4U)
|
|
/*! STALL_I_DIS12 - Disable Endpoint 12 IN Direction
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define USB_STALL_IH_DIS_STALL_I_DIS12(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS12_MASK)
|
|
|
|
#define USB_STALL_IH_DIS_STALL_I_DIS13_MASK (0x20U)
|
|
#define USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT (5U)
|
|
/*! STALL_I_DIS13 - Disable Endpoint 13 IN Direction
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define USB_STALL_IH_DIS_STALL_I_DIS13(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS13_MASK)
|
|
|
|
#define USB_STALL_IH_DIS_STALL_I_DIS14_MASK (0x40U)
|
|
#define USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT (6U)
|
|
/*! STALL_I_DIS14 - Disable Endpoint 14 IN Direction
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define USB_STALL_IH_DIS_STALL_I_DIS14(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS14_MASK)
|
|
|
|
#define USB_STALL_IH_DIS_STALL_I_DIS15_MASK (0x80U)
|
|
#define USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT (7U)
|
|
/*! STALL_I_DIS15 - Disable Endpoint 15 IN Direction
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define USB_STALL_IH_DIS_STALL_I_DIS15(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS15_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name STALL_OL_DIS - Peripheral Mode Stall Disable for Endpoints 7 to 0 in OUT Direction */
|
|
/*! @{ */
|
|
|
|
#define USB_STALL_OL_DIS_STALL_O_DIS0_MASK (0x1U)
|
|
#define USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT (0U)
|
|
/*! STALL_O_DIS0 - Disable Endpoint 0 OUT Direction
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define USB_STALL_OL_DIS_STALL_O_DIS0(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS0_MASK)
|
|
|
|
#define USB_STALL_OL_DIS_STALL_O_DIS1_MASK (0x2U)
|
|
#define USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT (1U)
|
|
/*! STALL_O_DIS1 - Disable Endpoint 1 OUT Direction
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define USB_STALL_OL_DIS_STALL_O_DIS1(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS1_MASK)
|
|
|
|
#define USB_STALL_OL_DIS_STALL_O_DIS2_MASK (0x4U)
|
|
#define USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT (2U)
|
|
/*! STALL_O_DIS2 - Disable Endpoint 2 OUT Direction
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define USB_STALL_OL_DIS_STALL_O_DIS2(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS2_MASK)
|
|
|
|
#define USB_STALL_OL_DIS_STALL_O_DIS3_MASK (0x8U)
|
|
#define USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT (3U)
|
|
/*! STALL_O_DIS3 - Disable Endpoint 3 OUT Direction
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define USB_STALL_OL_DIS_STALL_O_DIS3(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS3_MASK)
|
|
|
|
#define USB_STALL_OL_DIS_STALL_O_DIS4_MASK (0x10U)
|
|
#define USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT (4U)
|
|
/*! STALL_O_DIS4 - Disable Endpoint 4 OUT Direction
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define USB_STALL_OL_DIS_STALL_O_DIS4(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS4_MASK)
|
|
|
|
#define USB_STALL_OL_DIS_STALL_O_DIS5_MASK (0x20U)
|
|
#define USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT (5U)
|
|
/*! STALL_O_DIS5 - Disable Endpoint 5 OUT Direction
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define USB_STALL_OL_DIS_STALL_O_DIS5(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS5_MASK)
|
|
|
|
#define USB_STALL_OL_DIS_STALL_O_DIS6_MASK (0x40U)
|
|
#define USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT (6U)
|
|
/*! STALL_O_DIS6 - Disable Endpoint 6 OUT Direction
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define USB_STALL_OL_DIS_STALL_O_DIS6(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS6_MASK)
|
|
|
|
#define USB_STALL_OL_DIS_STALL_O_DIS7_MASK (0x80U)
|
|
#define USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT (7U)
|
|
/*! STALL_O_DIS7 - Disable Endpoint 7 OUT Direction
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define USB_STALL_OL_DIS_STALL_O_DIS7(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS7_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name STALL_OH_DIS - Peripheral Mode Stall Disable for Endpoints 15 to 8 in OUT Direction */
|
|
/*! @{ */
|
|
|
|
#define USB_STALL_OH_DIS_STALL_O_DIS8_MASK (0x1U)
|
|
#define USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT (0U)
|
|
/*! STALL_O_DIS8 - Disable Endpoint 8 OUT Direction
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define USB_STALL_OH_DIS_STALL_O_DIS8(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS8_MASK)
|
|
|
|
#define USB_STALL_OH_DIS_STALL_O_DIS9_MASK (0x2U)
|
|
#define USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT (1U)
|
|
/*! STALL_O_DIS9 - Disable Endpoint 9 OUT Direction
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define USB_STALL_OH_DIS_STALL_O_DIS9(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS9_MASK)
|
|
|
|
#define USB_STALL_OH_DIS_STALL_O_DIS10_MASK (0x4U)
|
|
#define USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT (2U)
|
|
/*! STALL_O_DIS10 - Disable Endpoint 10 OUT Direction
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define USB_STALL_OH_DIS_STALL_O_DIS10(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS10_MASK)
|
|
|
|
#define USB_STALL_OH_DIS_STALL_O_DIS11_MASK (0x8U)
|
|
#define USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT (3U)
|
|
/*! STALL_O_DIS11 - Disable Endpoint 11 OUT Direction
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define USB_STALL_OH_DIS_STALL_O_DIS11(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS11_MASK)
|
|
|
|
#define USB_STALL_OH_DIS_STALL_O_DIS12_MASK (0x10U)
|
|
#define USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT (4U)
|
|
/*! STALL_O_DIS12 - Disable endpoint 12 OUT direction
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define USB_STALL_OH_DIS_STALL_O_DIS12(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS12_MASK)
|
|
|
|
#define USB_STALL_OH_DIS_STALL_O_DIS13_MASK (0x20U)
|
|
#define USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT (5U)
|
|
/*! STALL_O_DIS13 - Disable Endpoint 13 OUT Direction
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define USB_STALL_OH_DIS_STALL_O_DIS13(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS13_MASK)
|
|
|
|
#define USB_STALL_OH_DIS_STALL_O_DIS14_MASK (0x40U)
|
|
#define USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT (6U)
|
|
/*! STALL_O_DIS14 - Disable Endpoint 14 OUT Direction
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define USB_STALL_OH_DIS_STALL_O_DIS14(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS14_MASK)
|
|
|
|
#define USB_STALL_OH_DIS_STALL_O_DIS15_MASK (0x80U)
|
|
#define USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT (7U)
|
|
/*! STALL_O_DIS15 - Disable Endpoint 15 OUT Direction
|
|
* 0b0..Enable
|
|
* 0b1..Disable
|
|
*/
|
|
#define USB_STALL_OH_DIS_STALL_O_DIS15(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS15_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CLK_RECOVER_CTRL - USB Clock Recovery Control */
|
|
/*! @{ */
|
|
|
|
#define USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL_MASK (0x8U)
|
|
#define USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL_SHIFT (3U)
|
|
/*! TRIM_INIT_VAL_SEL - Selects the source for the initial FIRC trim fine value used after a reset.
|
|
* 0b0..Mid-scale
|
|
* 0b1..IFR
|
|
*/
|
|
#define USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL_SHIFT)) & USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL_MASK)
|
|
|
|
#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U)
|
|
#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U)
|
|
/*! RESTART_IFRTRIM_EN - Restart from IFR Trim Value
|
|
* 0b0..Trim fine adjustment always works based on the previous updated trim fine value.
|
|
* 0b1..Trim fine restarts from the IFR trim value whenever you detect bus_reset or bus_resume or deassert module enable.
|
|
*/
|
|
#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
|
|
|
|
#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U)
|
|
#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U)
|
|
/*! RESET_RESUME_ROUGH_EN - Reset or Resume to Rough Phase Enable
|
|
* 0b0..Always works in tracking phase after the first time rough phase, to track transition.
|
|
* 0b1..Go back to rough stage whenever a bus reset or bus resume occurs.
|
|
*/
|
|
#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
|
|
|
|
#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U)
|
|
#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U)
|
|
/*! CLOCK_RECOVER_EN - Crystal-Less USB Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CLK_RECOVER_IRC_EN - FIRC Oscillator Enable */
|
|
/*! @{ */
|
|
|
|
#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U)
|
|
#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U)
|
|
/*! IRC_EN - Fast IRC enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CLK_RECOVER_INT_EN - Clock Recovery Combined Interrupt Enable */
|
|
/*! @{ */
|
|
|
|
#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U)
|
|
#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U)
|
|
/*! OVF_ERROR_EN - Overflow error interrupt enable
|
|
* 0b0..The interrupt is masked
|
|
* 0b1..The interrupt is enabled
|
|
*/
|
|
#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CLK_RECOVER_INT_STATUS - Clock Recovery Separated Interrupt Status */
|
|
/*! @{ */
|
|
|
|
#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U)
|
|
#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U)
|
|
/*! OVF_ERROR - Overflow Error Interrupt Status Flag
|
|
* 0b0..Interrupt did not occur
|
|
* 0b1..Unmasked interrupt occurred
|
|
* 0b0..No effect
|
|
* 0b1..Clear the flag
|
|
*/
|
|
#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group USB_Register_Masks */
|
|
|
|
|
|
/* USB - Peripheral instance base addresses */
|
|
/** Peripheral USB0 base address */
|
|
#define USB0_BASE (0x400A4000u)
|
|
/** Peripheral USB0 base pointer */
|
|
#define USB0 ((USB_Type *)USB0_BASE)
|
|
/** Array initializer of USB peripheral base addresses */
|
|
#define USB_BASE_ADDRS { USB0_BASE }
|
|
/** Array initializer of USB peripheral base pointers */
|
|
#define USB_BASE_PTRS { USB0 }
|
|
/** Interrupt vectors for the USB peripheral type */
|
|
#define USB_IRQS { USB0_IRQn }
|
|
/* Backward compatibility */
|
|
#define USBFS_IRQS USB_IRQS
|
|
#define USBFS_IRQHandler USB0_IRQHandler
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group USB_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- UTICK Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** UTICK - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t CTRL; /**< Control, offset: 0x0 */
|
|
__IO uint32_t STAT; /**< Status, offset: 0x4 */
|
|
__IO uint32_t CFG; /**< Capture Configuration, offset: 0x8 */
|
|
__O uint32_t CAPCLR; /**< Capture Clear, offset: 0xC */
|
|
__I uint32_t CAP[4]; /**< Capture, array offset: 0x10, array step: 0x4 */
|
|
} UTICK_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- UTICK Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup UTICK_Register_Masks UTICK Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name CTRL - Control */
|
|
/*! @{ */
|
|
|
|
#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU)
|
|
#define UTICK_CTRL_DELAYVAL_SHIFT (0U)
|
|
/*! DELAYVAL - Tick Interval
|
|
* 0b0000000000000000000000000000000..
|
|
* *..Clock cycles as defined in the description
|
|
*/
|
|
#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK)
|
|
|
|
#define UTICK_CTRL_REPEAT_MASK (0x80000000U)
|
|
#define UTICK_CTRL_REPEAT_SHIFT (31U)
|
|
/*! REPEAT - Repeat Delay
|
|
* 0b0..One-time delay
|
|
* 0b1..Delay repeats continuously
|
|
*/
|
|
#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name STAT - Status */
|
|
/*! @{ */
|
|
|
|
#define UTICK_STAT_INTR_MASK (0x1U)
|
|
#define UTICK_STAT_INTR_SHIFT (0U)
|
|
/*! INTR - Interrupt Flag
|
|
* 0b0..Not pending
|
|
* 0b1..Pending
|
|
*/
|
|
#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK)
|
|
|
|
#define UTICK_STAT_ACTIVE_MASK (0x2U)
|
|
#define UTICK_STAT_ACTIVE_SHIFT (1U)
|
|
/*! ACTIVE - Timer Active Flag
|
|
* 0b0..Inactive (stopped)
|
|
* 0b1..Active
|
|
*/
|
|
#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CFG - Capture Configuration */
|
|
/*! @{ */
|
|
|
|
#define UTICK_CFG_CAPEN0_MASK (0x1U)
|
|
#define UTICK_CFG_CAPEN0_SHIFT (0U)
|
|
/*! CAPEN0 - Enable Capture 0
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK)
|
|
|
|
#define UTICK_CFG_CAPEN1_MASK (0x2U)
|
|
#define UTICK_CFG_CAPEN1_SHIFT (1U)
|
|
/*! CAPEN1 - Enable Capture 1
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK)
|
|
|
|
#define UTICK_CFG_CAPEN2_MASK (0x4U)
|
|
#define UTICK_CFG_CAPEN2_SHIFT (2U)
|
|
/*! CAPEN2 - Enable Capture 2
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK)
|
|
|
|
#define UTICK_CFG_CAPEN3_MASK (0x8U)
|
|
#define UTICK_CFG_CAPEN3_SHIFT (3U)
|
|
/*! CAPEN3 - Enable Capture 3
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK)
|
|
|
|
#define UTICK_CFG_CAPPOL0_MASK (0x100U)
|
|
#define UTICK_CFG_CAPPOL0_SHIFT (8U)
|
|
/*! CAPPOL0 - Capture Polarity 0
|
|
* 0b0..Positive
|
|
* 0b1..Negative
|
|
*/
|
|
#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK)
|
|
|
|
#define UTICK_CFG_CAPPOL1_MASK (0x200U)
|
|
#define UTICK_CFG_CAPPOL1_SHIFT (9U)
|
|
/*! CAPPOL1 - Capture-Polarity 1
|
|
* 0b0..Positive
|
|
* 0b1..Negative
|
|
*/
|
|
#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK)
|
|
|
|
#define UTICK_CFG_CAPPOL2_MASK (0x400U)
|
|
#define UTICK_CFG_CAPPOL2_SHIFT (10U)
|
|
/*! CAPPOL2 - Capture Polarity 2
|
|
* 0b0..Positive
|
|
* 0b1..Negative
|
|
*/
|
|
#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK)
|
|
|
|
#define UTICK_CFG_CAPPOL3_MASK (0x800U)
|
|
#define UTICK_CFG_CAPPOL3_SHIFT (11U)
|
|
/*! CAPPOL3 - Capture Polarity 3
|
|
* 0b0..Positive
|
|
* 0b1..Negative
|
|
*/
|
|
#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAPCLR - Capture Clear */
|
|
/*! @{ */
|
|
|
|
#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U)
|
|
#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U)
|
|
/*! CAPCLR0 - Clear Capture 0
|
|
* 0b0..Does nothing
|
|
* 0b1..Clears the CAP0 register value
|
|
*/
|
|
#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK)
|
|
|
|
#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U)
|
|
#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U)
|
|
/*! CAPCLR1 - Clear Capture 1
|
|
* 0b0..Does nothing
|
|
* 0b1..Clears the CAP1 register value
|
|
*/
|
|
#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK)
|
|
|
|
#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U)
|
|
#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U)
|
|
/*! CAPCLR2 - Clear Capture 2
|
|
* 0b0..Does nothing
|
|
* 0b1..Clears the CAP2 register value
|
|
*/
|
|
#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK)
|
|
|
|
#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U)
|
|
#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U)
|
|
/*! CAPCLR3 - Clear Capture 3
|
|
* 0b0..Does nothing
|
|
* 0b1..Clears the CAP3 register value
|
|
*/
|
|
#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAP - Capture */
|
|
/*! @{ */
|
|
|
|
#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU)
|
|
#define UTICK_CAP_CAP_VALUE_SHIFT (0U)
|
|
/*! CAP_VALUE - Captured Value for the Related Capture Event */
|
|
#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK)
|
|
|
|
#define UTICK_CAP_VALID_MASK (0x80000000U)
|
|
#define UTICK_CAP_VALID_SHIFT (31U)
|
|
/*! VALID - Captured Value Valid Flag
|
|
* 0b0..Valid value not captured
|
|
* 0b1..Valid value captured
|
|
*/
|
|
#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of UTICK_CAP */
|
|
#define UTICK_CAP_COUNT (4U)
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group UTICK_Register_Masks */
|
|
|
|
|
|
/* UTICK - Peripheral instance base addresses */
|
|
/** Peripheral UTICK0 base address */
|
|
#define UTICK0_BASE (0x4000B000u)
|
|
/** Peripheral UTICK0 base pointer */
|
|
#define UTICK0 ((UTICK_Type *)UTICK0_BASE)
|
|
/** Array initializer of UTICK peripheral base addresses */
|
|
#define UTICK_BASE_ADDRS { UTICK0_BASE }
|
|
/** Array initializer of UTICK peripheral base pointers */
|
|
#define UTICK_BASE_PTRS { UTICK0 }
|
|
/** Interrupt vectors for the UTICK peripheral type */
|
|
#define UTICK_IRQS { UTICK0_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group UTICK_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- VBAT Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup VBAT_Peripheral_Access_Layer VBAT Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** VBAT - Register Layout Typedef */
|
|
typedef struct {
|
|
__I uint32_t VERID; /**< Version ID, offset: 0x0 */
|
|
uint8_t RESERVED_0[508];
|
|
__IO uint32_t FROCTLA; /**< FRO16K Control A, offset: 0x200 */
|
|
uint8_t RESERVED_1[20];
|
|
__IO uint32_t FROLCKA; /**< FRO16K Lock A, offset: 0x218 */
|
|
uint8_t RESERVED_2[4];
|
|
__IO uint32_t FROCLKE; /**< FRO16K Clock Enable, offset: 0x220 */
|
|
uint8_t RESERVED_3[1244];
|
|
struct { /* offset: 0x700, array step: 0x8 */
|
|
__IO uint32_t WAKEUPA; /**< Wakeup 0 Register A, array offset: 0x700, array step: 0x8 */
|
|
uint8_t RESERVED_0[4];
|
|
} WAKEUP[2];
|
|
uint8_t RESERVED_4[232];
|
|
__IO uint32_t WAKLCKA; /**< Wakeup Lock A, offset: 0x7F8 */
|
|
} VBAT_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- VBAT Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup VBAT_Register_Masks VBAT Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name VERID - Version ID */
|
|
/*! @{ */
|
|
|
|
#define VBAT_VERID_FEATURE_MASK (0xFFFFU)
|
|
#define VBAT_VERID_FEATURE_SHIFT (0U)
|
|
/*! FEATURE - Feature Specification Number */
|
|
#define VBAT_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_VERID_FEATURE_SHIFT)) & VBAT_VERID_FEATURE_MASK)
|
|
|
|
#define VBAT_VERID_MINOR_MASK (0xFF0000U)
|
|
#define VBAT_VERID_MINOR_SHIFT (16U)
|
|
/*! MINOR - Minor Version Number */
|
|
#define VBAT_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << VBAT_VERID_MINOR_SHIFT)) & VBAT_VERID_MINOR_MASK)
|
|
|
|
#define VBAT_VERID_MAJOR_MASK (0xFF000000U)
|
|
#define VBAT_VERID_MAJOR_SHIFT (24U)
|
|
/*! MAJOR - Major Version Number */
|
|
#define VBAT_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << VBAT_VERID_MAJOR_SHIFT)) & VBAT_VERID_MAJOR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FROCTLA - FRO16K Control A */
|
|
/*! @{ */
|
|
|
|
#define VBAT_FROCTLA_FRO_EN_MASK (0x1U)
|
|
#define VBAT_FROCTLA_FRO_EN_SHIFT (0U)
|
|
/*! FRO_EN - FRO16K Enable
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define VBAT_FROCTLA_FRO_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_FROCTLA_FRO_EN_SHIFT)) & VBAT_FROCTLA_FRO_EN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FROLCKA - FRO16K Lock A */
|
|
/*! @{ */
|
|
|
|
#define VBAT_FROLCKA_LOCK_MASK (0x1U)
|
|
#define VBAT_FROLCKA_LOCK_SHIFT (0U)
|
|
/*! LOCK - Lock
|
|
* 0b0..Do not block
|
|
* 0b1..Block
|
|
*/
|
|
#define VBAT_FROLCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_FROLCKA_LOCK_SHIFT)) & VBAT_FROLCKA_LOCK_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FROCLKE - FRO16K Clock Enable */
|
|
/*! @{ */
|
|
|
|
#define VBAT_FROCLKE_CLKE_MASK (0x3U)
|
|
#define VBAT_FROCLKE_CLKE_SHIFT (0U)
|
|
/*! CLKE - Clock Enable */
|
|
#define VBAT_FROCLKE_CLKE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_FROCLKE_CLKE_SHIFT)) & VBAT_FROCLKE_CLKE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name WAKEUP_WAKEUPA - Wakeup 0 Register A */
|
|
/*! @{ */
|
|
|
|
#define VBAT_WAKEUP_WAKEUPA_REG_MASK (0xFFFFFFFFU)
|
|
#define VBAT_WAKEUP_WAKEUPA_REG_SHIFT (0U)
|
|
/*! REG - Register */
|
|
#define VBAT_WAKEUP_WAKEUPA_REG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKEUP_WAKEUPA_REG_SHIFT)) & VBAT_WAKEUP_WAKEUPA_REG_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of VBAT_WAKEUP_WAKEUPA */
|
|
#define VBAT_WAKEUP_WAKEUPA_COUNT (2U)
|
|
|
|
/*! @name WAKLCKA - Wakeup Lock A */
|
|
/*! @{ */
|
|
|
|
#define VBAT_WAKLCKA_LOCK_MASK (0x1U)
|
|
#define VBAT_WAKLCKA_LOCK_SHIFT (0U)
|
|
/*! LOCK - Lock
|
|
* 0b0..Lock is disabled
|
|
* 0b1..Lock is enabled
|
|
*/
|
|
#define VBAT_WAKLCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKLCKA_LOCK_SHIFT)) & VBAT_WAKLCKA_LOCK_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group VBAT_Register_Masks */
|
|
|
|
|
|
/* VBAT - Peripheral instance base addresses */
|
|
/** Peripheral VBAT0 base address */
|
|
#define VBAT0_BASE (0x40093000u)
|
|
/** Peripheral VBAT0 base pointer */
|
|
#define VBAT0 ((VBAT_Type *)VBAT0_BASE)
|
|
/** Array initializer of VBAT peripheral base addresses */
|
|
#define VBAT_BASE_ADDRS { VBAT0_BASE }
|
|
/** Array initializer of VBAT peripheral base pointers */
|
|
#define VBAT_BASE_PTRS { VBAT0 }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group VBAT_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- WAKETIMER Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup WAKETIMER_Peripheral_Access_Layer WAKETIMER Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** WAKETIMER - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t WAKE_TIMER_CTRL; /**< Wake Timer Control, offset: 0x0 */
|
|
uint8_t RESERVED_0[8];
|
|
__IO uint32_t WAKE_TIMER_CNT; /**< Wake Timer Counter, offset: 0xC */
|
|
} WAKETIMER_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- WAKETIMER Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup WAKETIMER_Register_Masks WAKETIMER Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name WAKE_TIMER_CTRL - Wake Timer Control */
|
|
/*! @{ */
|
|
|
|
#define WAKETIMER_WAKE_TIMER_CTRL_WAKE_FLAG_MASK (0x2U)
|
|
#define WAKETIMER_WAKE_TIMER_CTRL_WAKE_FLAG_SHIFT (1U)
|
|
/*! WAKE_FLAG - Wake Timer Status Flag
|
|
* 0b0..Wake timer has not timed out.
|
|
* 0b1..Wake timer has timed out.
|
|
*/
|
|
#define WAKETIMER_WAKE_TIMER_CTRL_WAKE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << WAKETIMER_WAKE_TIMER_CTRL_WAKE_FLAG_SHIFT)) & WAKETIMER_WAKE_TIMER_CTRL_WAKE_FLAG_MASK)
|
|
|
|
#define WAKETIMER_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_MASK (0x4U)
|
|
#define WAKETIMER_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_SHIFT (2U)
|
|
/*! CLR_WAKE_TIMER - Clear Wake Timer
|
|
* 0b0..No effect.
|
|
* 0b1..Clears the wake timer counter and halts operation until a new count value is loaded.
|
|
*/
|
|
#define WAKETIMER_WAKE_TIMER_CTRL_CLR_WAKE_TIMER(x) (((uint32_t)(((uint32_t)(x)) << WAKETIMER_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_SHIFT)) & WAKETIMER_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_MASK)
|
|
|
|
#define WAKETIMER_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK (0x10U)
|
|
#define WAKETIMER_WAKE_TIMER_CTRL_OSC_DIV_ENA_SHIFT (4U)
|
|
/*! OSC_DIV_ENA - OSC Divide Enable
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define WAKETIMER_WAKE_TIMER_CTRL_OSC_DIV_ENA(x) (((uint32_t)(((uint32_t)(x)) << WAKETIMER_WAKE_TIMER_CTRL_OSC_DIV_ENA_SHIFT)) & WAKETIMER_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK)
|
|
|
|
#define WAKETIMER_WAKE_TIMER_CTRL_INTR_EN_MASK (0x20U)
|
|
#define WAKETIMER_WAKE_TIMER_CTRL_INTR_EN_SHIFT (5U)
|
|
/*! INTR_EN - Enable Interrupt
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define WAKETIMER_WAKE_TIMER_CTRL_INTR_EN(x) (((uint32_t)(((uint32_t)(x)) << WAKETIMER_WAKE_TIMER_CTRL_INTR_EN_SHIFT)) & WAKETIMER_WAKE_TIMER_CTRL_INTR_EN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name WAKE_TIMER_CNT - Wake Timer Counter */
|
|
/*! @{ */
|
|
|
|
#define WAKETIMER_WAKE_TIMER_CNT_WAKE_CNT_MASK (0xFFFFFFFFU)
|
|
#define WAKETIMER_WAKE_TIMER_CNT_WAKE_CNT_SHIFT (0U)
|
|
/*! WAKE_CNT - Wake Counter */
|
|
#define WAKETIMER_WAKE_TIMER_CNT_WAKE_CNT(x) (((uint32_t)(((uint32_t)(x)) << WAKETIMER_WAKE_TIMER_CNT_WAKE_CNT_SHIFT)) & WAKETIMER_WAKE_TIMER_CNT_WAKE_CNT_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group WAKETIMER_Register_Masks */
|
|
|
|
|
|
/* WAKETIMER - Peripheral instance base addresses */
|
|
/** Peripheral WAKETIMER0 base address */
|
|
#define WAKETIMER0_BASE (0x400AE000u)
|
|
/** Peripheral WAKETIMER0 base pointer */
|
|
#define WAKETIMER0 ((WAKETIMER_Type *)WAKETIMER0_BASE)
|
|
/** Array initializer of WAKETIMER peripheral base addresses */
|
|
#define WAKETIMER_BASE_ADDRS { WAKETIMER0_BASE }
|
|
/** Array initializer of WAKETIMER peripheral base pointers */
|
|
#define WAKETIMER_BASE_PTRS { WAKETIMER0 }
|
|
/** Interrupt vectors for the WAKETIMER peripheral type */
|
|
#define WAKETIMER_IRQS { WAKETIMER0_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group WAKETIMER_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- WUU Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup WUU_Peripheral_Access_Layer WUU Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** WUU - Register Layout Typedef */
|
|
typedef struct {
|
|
__I uint32_t VERID; /**< Version ID, offset: 0x0 */
|
|
__I uint32_t PARAM; /**< Parameter, offset: 0x4 */
|
|
__IO uint32_t PE1; /**< Pin Enable 1, offset: 0x8 */
|
|
__IO uint32_t PE2; /**< Pin Enable 2, offset: 0xC */
|
|
uint8_t RESERVED_0[8];
|
|
__IO uint32_t ME; /**< Module Interrupt Enable, offset: 0x18 */
|
|
__IO uint32_t DE; /**< Module DMA/Trigger Enable, offset: 0x1C */
|
|
__IO uint32_t PF; /**< Pin Flag, offset: 0x20 */
|
|
uint8_t RESERVED_1[12];
|
|
__IO uint32_t FILT; /**< Pin Filter, offset: 0x30 */
|
|
uint8_t RESERVED_2[4];
|
|
__IO uint32_t PDC1; /**< Pin DMA/Trigger Configuration 1, offset: 0x38 */
|
|
__IO uint32_t PDC2; /**< Pin DMA/Trigger Configuration 2, offset: 0x3C */
|
|
uint8_t RESERVED_3[8];
|
|
__IO uint32_t FDC; /**< Pin Filter DMA/Trigger Configuration, offset: 0x48 */
|
|
uint8_t RESERVED_4[4];
|
|
__IO uint32_t PMC; /**< Pin Mode Configuration, offset: 0x50 */
|
|
uint8_t RESERVED_5[4];
|
|
__IO uint32_t FMC; /**< Pin Filter Mode Configuration, offset: 0x58 */
|
|
} WUU_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- WUU Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup WUU_Register_Masks WUU Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name VERID - Version ID */
|
|
/*! @{ */
|
|
|
|
#define WUU_VERID_FEATURE_MASK (0xFFFFU)
|
|
#define WUU_VERID_FEATURE_SHIFT (0U)
|
|
/*! FEATURE - Feature Specification Number
|
|
* 0b0000000000000000..Standard features implemented
|
|
* 0b0000000000000001..Support for DMA/Trigger generation from wake-up pins and filters enabled. Support for
|
|
* external pin/filter detection during all power modes enabled.
|
|
* *..
|
|
*/
|
|
#define WUU_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << WUU_VERID_FEATURE_SHIFT)) & WUU_VERID_FEATURE_MASK)
|
|
|
|
#define WUU_VERID_MINOR_MASK (0xFF0000U)
|
|
#define WUU_VERID_MINOR_SHIFT (16U)
|
|
/*! MINOR - Minor Version Number */
|
|
#define WUU_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << WUU_VERID_MINOR_SHIFT)) & WUU_VERID_MINOR_MASK)
|
|
|
|
#define WUU_VERID_MAJOR_MASK (0xFF000000U)
|
|
#define WUU_VERID_MAJOR_SHIFT (24U)
|
|
/*! MAJOR - Major Version Number */
|
|
#define WUU_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << WUU_VERID_MAJOR_SHIFT)) & WUU_VERID_MAJOR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PARAM - Parameter */
|
|
/*! @{ */
|
|
|
|
#define WUU_PARAM_FILTERS_MASK (0xFFU)
|
|
#define WUU_PARAM_FILTERS_SHIFT (0U)
|
|
/*! FILTERS - Filter Number */
|
|
#define WUU_PARAM_FILTERS(x) (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_FILTERS_SHIFT)) & WUU_PARAM_FILTERS_MASK)
|
|
|
|
#define WUU_PARAM_DMAS_MASK (0xFF00U)
|
|
#define WUU_PARAM_DMAS_SHIFT (8U)
|
|
/*! DMAS - DMA Number */
|
|
#define WUU_PARAM_DMAS(x) (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_DMAS_SHIFT)) & WUU_PARAM_DMAS_MASK)
|
|
|
|
#define WUU_PARAM_MODULES_MASK (0xFF0000U)
|
|
#define WUU_PARAM_MODULES_SHIFT (16U)
|
|
/*! MODULES - Module Number */
|
|
#define WUU_PARAM_MODULES(x) (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_MODULES_SHIFT)) & WUU_PARAM_MODULES_MASK)
|
|
|
|
#define WUU_PARAM_PINS_MASK (0xFF000000U)
|
|
#define WUU_PARAM_PINS_SHIFT (24U)
|
|
/*! PINS - Pin Number */
|
|
#define WUU_PARAM_PINS(x) (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_PINS_SHIFT)) & WUU_PARAM_PINS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PE1 - Pin Enable 1 */
|
|
/*! @{ */
|
|
|
|
#define WUU_PE1_Reserved0_MASK (0x3U)
|
|
#define WUU_PE1_Reserved0_SHIFT (0U)
|
|
/*! Reserved0 - Reserved
|
|
* 0b00..Not supported
|
|
* 0b01..Not supported
|
|
* 0b10..Not supported
|
|
* 0b11..Not supported
|
|
*/
|
|
#define WUU_PE1_Reserved0(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_Reserved0_SHIFT)) & WUU_PE1_Reserved0_MASK)
|
|
|
|
#define WUU_PE1_Reserved1_MASK (0xCU)
|
|
#define WUU_PE1_Reserved1_SHIFT (2U)
|
|
/*! Reserved1 - Reserved
|
|
* 0b00..Not supported
|
|
* 0b01..Not supported
|
|
* 0b10..Not supported
|
|
* 0b11..Not supported
|
|
*/
|
|
#define WUU_PE1_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_Reserved1_SHIFT)) & WUU_PE1_Reserved1_MASK)
|
|
|
|
#define WUU_PE1_WUPE2_MASK (0x30U)
|
|
#define WUU_PE1_WUPE2_SHIFT (4U)
|
|
/*! WUPE2 - Wake-up Pin Enable for WUU_Pn
|
|
* 0b00..Disable
|
|
* 0b01..Enable (detect on rising edge or high level)
|
|
* 0b10..Enable (detect on falling edge or low level)
|
|
* 0b11..Enable (detect on any edge)
|
|
*/
|
|
#define WUU_PE1_WUPE2(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE2_SHIFT)) & WUU_PE1_WUPE2_MASK)
|
|
|
|
#define WUU_PE1_Reserved3_MASK (0xC0U)
|
|
#define WUU_PE1_Reserved3_SHIFT (6U)
|
|
/*! Reserved3 - Reserved
|
|
* 0b00..Not supported
|
|
* 0b01..Not supported
|
|
* 0b10..Not supported
|
|
* 0b11..Not supported
|
|
*/
|
|
#define WUU_PE1_Reserved3(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_Reserved3_SHIFT)) & WUU_PE1_Reserved3_MASK)
|
|
|
|
#define WUU_PE1_Reserved4_MASK (0x300U)
|
|
#define WUU_PE1_Reserved4_SHIFT (8U)
|
|
/*! Reserved4 - Reserved
|
|
* 0b00..Not supported
|
|
* 0b01..Not supported
|
|
* 0b10..Not supported
|
|
* 0b11..Not supported
|
|
*/
|
|
#define WUU_PE1_Reserved4(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_Reserved4_SHIFT)) & WUU_PE1_Reserved4_MASK)
|
|
|
|
#define WUU_PE1_Reserved5_MASK (0xC00U)
|
|
#define WUU_PE1_Reserved5_SHIFT (10U)
|
|
/*! Reserved5 - Reserved
|
|
* 0b00..Not supported
|
|
* 0b01..Not supported
|
|
* 0b10..Not supported
|
|
* 0b11..Not supported
|
|
*/
|
|
#define WUU_PE1_Reserved5(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_Reserved5_SHIFT)) & WUU_PE1_Reserved5_MASK)
|
|
|
|
#define WUU_PE1_WUPE6_MASK (0x3000U)
|
|
#define WUU_PE1_WUPE6_SHIFT (12U)
|
|
/*! WUPE6 - Wake-up Pin Enable for WUU_Pn
|
|
* 0b00..Disable
|
|
* 0b01..Enable (detect on rising edge or high level)
|
|
* 0b10..Enable (detect on falling edge or low level)
|
|
* 0b11..Enable (detect on any edge)
|
|
*/
|
|
#define WUU_PE1_WUPE6(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE6_SHIFT)) & WUU_PE1_WUPE6_MASK)
|
|
|
|
#define WUU_PE1_WUPE7_MASK (0xC000U)
|
|
#define WUU_PE1_WUPE7_SHIFT (14U)
|
|
/*! WUPE7 - Wake-up Pin Enable for WUU_Pn
|
|
* 0b00..Disable
|
|
* 0b01..Enable (detect on rising edge or high level)
|
|
* 0b10..Enable (detect on falling edge or low level)
|
|
* 0b11..Enable (detect on any edge)
|
|
*/
|
|
#define WUU_PE1_WUPE7(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE7_SHIFT)) & WUU_PE1_WUPE7_MASK)
|
|
|
|
#define WUU_PE1_WUPE8_MASK (0x30000U)
|
|
#define WUU_PE1_WUPE8_SHIFT (16U)
|
|
/*! WUPE8 - Wake-up Pin Enable for WUU_Pn
|
|
* 0b00..Disable
|
|
* 0b01..Enable (detect on rising edge or high level)
|
|
* 0b10..Enable (detect on falling edge or low level)
|
|
* 0b11..Enable (detect on any edge)
|
|
*/
|
|
#define WUU_PE1_WUPE8(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE8_SHIFT)) & WUU_PE1_WUPE8_MASK)
|
|
|
|
#define WUU_PE1_WUPE9_MASK (0xC0000U)
|
|
#define WUU_PE1_WUPE9_SHIFT (18U)
|
|
/*! WUPE9 - Wake-up Pin Enable for WUU_Pn
|
|
* 0b00..Disable
|
|
* 0b01..Enable (detect on rising edge or high level)
|
|
* 0b10..Enable (detect on falling edge or low level)
|
|
* 0b11..Enable (detect on any edge)
|
|
*/
|
|
#define WUU_PE1_WUPE9(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE9_SHIFT)) & WUU_PE1_WUPE9_MASK)
|
|
|
|
#define WUU_PE1_WUPE10_MASK (0x300000U)
|
|
#define WUU_PE1_WUPE10_SHIFT (20U)
|
|
/*! WUPE10 - Wake-up Pin Enable for WUU_Pn
|
|
* 0b00..Disable
|
|
* 0b01..Enable (detect on rising edge or high level)
|
|
* 0b10..Enable (detect on falling edge or low level)
|
|
* 0b11..Enable (detect on any edge)
|
|
*/
|
|
#define WUU_PE1_WUPE10(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE10_SHIFT)) & WUU_PE1_WUPE10_MASK)
|
|
|
|
#define WUU_PE1_WUPE11_MASK (0xC00000U)
|
|
#define WUU_PE1_WUPE11_SHIFT (22U)
|
|
/*! WUPE11 - Wake-up Pin Enable for WUU_Pn
|
|
* 0b00..Disable
|
|
* 0b01..Enable (detect on rising edge or high level)
|
|
* 0b10..Enable (detect on falling edge or low level)
|
|
* 0b11..Enable (detect on any edge)
|
|
*/
|
|
#define WUU_PE1_WUPE11(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE11_SHIFT)) & WUU_PE1_WUPE11_MASK)
|
|
|
|
#define WUU_PE1_WUPE12_MASK (0x3000000U)
|
|
#define WUU_PE1_WUPE12_SHIFT (24U)
|
|
/*! WUPE12 - Wake-up Pin Enable for WUU_Pn
|
|
* 0b00..Disable
|
|
* 0b01..Enable (detect on rising edge or high level)
|
|
* 0b10..Enable (detect on falling edge or low level)
|
|
* 0b11..Enable (detect on any edge)
|
|
*/
|
|
#define WUU_PE1_WUPE12(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE12_SHIFT)) & WUU_PE1_WUPE12_MASK)
|
|
|
|
#define WUU_PE1_Reserved13_MASK (0xC000000U)
|
|
#define WUU_PE1_Reserved13_SHIFT (26U)
|
|
/*! Reserved13 - Reserved
|
|
* 0b00..Not supported
|
|
* 0b01..Not supported
|
|
* 0b10..Not supported
|
|
* 0b11..Not supported
|
|
*/
|
|
#define WUU_PE1_Reserved13(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_Reserved13_SHIFT)) & WUU_PE1_Reserved13_MASK)
|
|
|
|
#define WUU_PE1_Reserved14_MASK (0x30000000U)
|
|
#define WUU_PE1_Reserved14_SHIFT (28U)
|
|
/*! Reserved14 - Reserved
|
|
* 0b00..Not supported
|
|
* 0b01..Not supported
|
|
* 0b10..Not supported
|
|
* 0b11..Not supported
|
|
*/
|
|
#define WUU_PE1_Reserved14(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_Reserved14_SHIFT)) & WUU_PE1_Reserved14_MASK)
|
|
|
|
#define WUU_PE1_Reserved15_MASK (0xC0000000U)
|
|
#define WUU_PE1_Reserved15_SHIFT (30U)
|
|
/*! Reserved15 - Reserved
|
|
* 0b00..Not supported
|
|
* 0b01..Not supported
|
|
* 0b10..Not supported
|
|
* 0b11..Not supported
|
|
*/
|
|
#define WUU_PE1_Reserved15(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_Reserved15_SHIFT)) & WUU_PE1_Reserved15_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PE2 - Pin Enable 2 */
|
|
/*! @{ */
|
|
|
|
#define WUU_PE2_Reserved16_MASK (0x3U)
|
|
#define WUU_PE2_Reserved16_SHIFT (0U)
|
|
/*! Reserved16 - Reserved
|
|
* 0b00..Not supported
|
|
* 0b01..Not supported
|
|
* 0b10..Not supported
|
|
* 0b11..Not supported
|
|
*/
|
|
#define WUU_PE2_Reserved16(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_Reserved16_SHIFT)) & WUU_PE2_Reserved16_MASK)
|
|
|
|
#define WUU_PE2_Reserved17_MASK (0xCU)
|
|
#define WUU_PE2_Reserved17_SHIFT (2U)
|
|
/*! Reserved17 - Reserved
|
|
* 0b00..Not supported
|
|
* 0b01..Not supported
|
|
* 0b10..Not supported
|
|
* 0b11..Not supported
|
|
*/
|
|
#define WUU_PE2_Reserved17(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_Reserved17_SHIFT)) & WUU_PE2_Reserved17_MASK)
|
|
|
|
#define WUU_PE2_WUPE18_MASK (0x30U)
|
|
#define WUU_PE2_WUPE18_SHIFT (4U)
|
|
/*! WUPE18 - Wake-up Pin Enable for WUU_Pn
|
|
* 0b00..Disable
|
|
* 0b01..Enable (detect on rising edge or high level)
|
|
* 0b10..Enable (detect on falling edge or low level)
|
|
* 0b11..Enable (detect on any edge)
|
|
*/
|
|
#define WUU_PE2_WUPE18(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE18_SHIFT)) & WUU_PE2_WUPE18_MASK)
|
|
|
|
#define WUU_PE2_WUPE19_MASK (0xC0U)
|
|
#define WUU_PE2_WUPE19_SHIFT (6U)
|
|
/*! WUPE19 - Wake-up Pin Enable for WUU_Pn
|
|
* 0b00..Disable
|
|
* 0b01..Enable (detect on rising edge or high level)
|
|
* 0b10..Enable (detect on falling edge or low level)
|
|
* 0b11..Enable (detect on any edge)
|
|
*/
|
|
#define WUU_PE2_WUPE19(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE19_SHIFT)) & WUU_PE2_WUPE19_MASK)
|
|
|
|
#define WUU_PE2_WUPE20_MASK (0x300U)
|
|
#define WUU_PE2_WUPE20_SHIFT (8U)
|
|
/*! WUPE20 - Wake-up Pin Enable for WUU_Pn
|
|
* 0b00..Disable
|
|
* 0b01..Enable (detect on rising edge or high level)
|
|
* 0b10..Enable (detect on falling edge or low level)
|
|
* 0b11..Enable (detect on any edge)
|
|
*/
|
|
#define WUU_PE2_WUPE20(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE20_SHIFT)) & WUU_PE2_WUPE20_MASK)
|
|
|
|
#define WUU_PE2_Reserved21_MASK (0xC00U)
|
|
#define WUU_PE2_Reserved21_SHIFT (10U)
|
|
/*! Reserved21 - Reserved
|
|
* 0b00..Not supported
|
|
* 0b01..Not supported
|
|
* 0b10..Not supported
|
|
* 0b11..Not supported
|
|
*/
|
|
#define WUU_PE2_Reserved21(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_Reserved21_SHIFT)) & WUU_PE2_Reserved21_MASK)
|
|
|
|
#define WUU_PE2_WUPE22_MASK (0x3000U)
|
|
#define WUU_PE2_WUPE22_SHIFT (12U)
|
|
/*! WUPE22 - Wake-up Pin Enable for WUU_Pn
|
|
* 0b00..Disable
|
|
* 0b01..Enable (detect on rising edge or high level)
|
|
* 0b10..Enable (detect on falling edge or low level)
|
|
* 0b11..Enable (detect on any edge)
|
|
*/
|
|
#define WUU_PE2_WUPE22(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE22_SHIFT)) & WUU_PE2_WUPE22_MASK)
|
|
|
|
#define WUU_PE2_WUPE23_MASK (0xC000U)
|
|
#define WUU_PE2_WUPE23_SHIFT (14U)
|
|
/*! WUPE23 - Wake-up Pin Enable for WUU_Pn
|
|
* 0b00..Disable
|
|
* 0b01..Enable (detect on rising edge or high level)
|
|
* 0b10..Enable (detect on falling edge or low level)
|
|
* 0b11..Enable (detect on any edge)
|
|
*/
|
|
#define WUU_PE2_WUPE23(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE23_SHIFT)) & WUU_PE2_WUPE23_MASK)
|
|
|
|
#define WUU_PE2_WUPE24_MASK (0x30000U)
|
|
#define WUU_PE2_WUPE24_SHIFT (16U)
|
|
/*! WUPE24 - Wake-up Pin Enable for WUU_Pn
|
|
* 0b00..Disable
|
|
* 0b01..Enable (detect on rising edge or high level)
|
|
* 0b10..Enable (detect on falling edge or low level)
|
|
* 0b11..Enable (detect on any edge)
|
|
*/
|
|
#define WUU_PE2_WUPE24(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE24_SHIFT)) & WUU_PE2_WUPE24_MASK)
|
|
|
|
#define WUU_PE2_WUPE25_MASK (0xC0000U)
|
|
#define WUU_PE2_WUPE25_SHIFT (18U)
|
|
/*! WUPE25 - Wake-up Pin Enable for WUU_Pn
|
|
* 0b00..Disable
|
|
* 0b01..Enable (detect on rising edge or high level)
|
|
* 0b10..Enable (detect on falling edge or low level)
|
|
* 0b11..Enable (detect on any edge)
|
|
*/
|
|
#define WUU_PE2_WUPE25(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE25_SHIFT)) & WUU_PE2_WUPE25_MASK)
|
|
|
|
#define WUU_PE2_WUPE26_MASK (0x300000U)
|
|
#define WUU_PE2_WUPE26_SHIFT (20U)
|
|
/*! WUPE26 - Wake-up Pin Enable for WUU_Pn
|
|
* 0b00..Disable
|
|
* 0b01..Enable (detect on rising edge or high level)
|
|
* 0b10..Enable (detect on falling edge or low level)
|
|
* 0b11..Enable (detect on any edge)
|
|
*/
|
|
#define WUU_PE2_WUPE26(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE26_SHIFT)) & WUU_PE2_WUPE26_MASK)
|
|
|
|
#define WUU_PE2_WUPE27_MASK (0xC00000U)
|
|
#define WUU_PE2_WUPE27_SHIFT (22U)
|
|
/*! WUPE27 - Wake-up Pin Enable for WUU_Pn
|
|
* 0b00..Disable
|
|
* 0b01..Enable (detect on rising edge or high level)
|
|
* 0b10..Enable (detect on falling edge or low level)
|
|
* 0b11..Enable (detect on any edge)
|
|
*/
|
|
#define WUU_PE2_WUPE27(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE27_SHIFT)) & WUU_PE2_WUPE27_MASK)
|
|
|
|
#define WUU_PE2_WUPE28_MASK (0x3000000U)
|
|
#define WUU_PE2_WUPE28_SHIFT (24U)
|
|
/*! WUPE28 - Wake-up Pin Enable for WUU_Pn
|
|
* 0b00..Disable
|
|
* 0b01..Enable (detect on rising edge or high level)
|
|
* 0b10..Enable (detect on falling edge or low level)
|
|
* 0b11..Enable (detect on any edge)
|
|
*/
|
|
#define WUU_PE2_WUPE28(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE28_SHIFT)) & WUU_PE2_WUPE28_MASK)
|
|
|
|
#define WUU_PE2_WUPE29_MASK (0xC000000U)
|
|
#define WUU_PE2_WUPE29_SHIFT (26U)
|
|
/*! WUPE29 - Wake-up Pin Enable for WUU_Pn
|
|
* 0b00..Disable
|
|
* 0b01..Enable (detect on rising edge or high level)
|
|
* 0b10..Enable (detect on falling edge or low level)
|
|
* 0b11..Enable (detect on any edge)
|
|
*/
|
|
#define WUU_PE2_WUPE29(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE29_SHIFT)) & WUU_PE2_WUPE29_MASK)
|
|
|
|
#define WUU_PE2_Reserved30_MASK (0x30000000U)
|
|
#define WUU_PE2_Reserved30_SHIFT (28U)
|
|
/*! Reserved30 - Reserved
|
|
* 0b00..Not supported
|
|
* 0b01..Not supported
|
|
* 0b10..Not supported
|
|
* 0b11..Not supported
|
|
*/
|
|
#define WUU_PE2_Reserved30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_Reserved30_SHIFT)) & WUU_PE2_Reserved30_MASK)
|
|
|
|
#define WUU_PE2_WUPE31_MASK (0xC0000000U)
|
|
#define WUU_PE2_WUPE31_SHIFT (30U)
|
|
/*! WUPE31 - Wake-up Pin Enable for WUU_Pn
|
|
* 0b00..Disable
|
|
* 0b01..Enable (detect on rising edge or high level)
|
|
* 0b10..Enable (detect on falling edge or low level)
|
|
* 0b11..Enable (detect on any edge)
|
|
*/
|
|
#define WUU_PE2_WUPE31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE31_SHIFT)) & WUU_PE2_WUPE31_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ME - Module Interrupt Enable */
|
|
/*! @{ */
|
|
|
|
#define WUU_ME_WUME0_MASK (0x1U)
|
|
#define WUU_ME_WUME0_SHIFT (0U)
|
|
/*! WUME0 - Module Interrupt Wake-up Enable for Module 0 */
|
|
#define WUU_ME_WUME0(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME0_SHIFT)) & WUU_ME_WUME0_MASK)
|
|
|
|
#define WUU_ME_WUME2_MASK (0x4U)
|
|
#define WUU_ME_WUME2_SHIFT (2U)
|
|
/*! WUME2 - Module Interrupt Wake-up Enable for Module 2 */
|
|
#define WUU_ME_WUME2(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME2_SHIFT)) & WUU_ME_WUME2_MASK)
|
|
|
|
#define WUU_ME_WUME6_MASK (0x40U)
|
|
#define WUU_ME_WUME6_SHIFT (6U)
|
|
/*! WUME6 - Module Interrupt Wake-up Enable for Module 6 */
|
|
#define WUU_ME_WUME6(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME6_SHIFT)) & WUU_ME_WUME6_MASK)
|
|
|
|
#define WUU_ME_WUME8_MASK (0x100U)
|
|
#define WUU_ME_WUME8_SHIFT (8U)
|
|
/*! WUME8 - Module Interrupt Wake-up Enable for Module 8 */
|
|
#define WUU_ME_WUME8(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME8_SHIFT)) & WUU_ME_WUME8_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DE - Module DMA/Trigger Enable */
|
|
/*! @{ */
|
|
|
|
#define WUU_DE_WUDE4_MASK (0x10U)
|
|
#define WUU_DE_WUDE4_SHIFT (4U)
|
|
/*! WUDE4 - DMA/Trigger Wake-up Enable for Module 4 */
|
|
#define WUU_DE_WUDE4(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE4_SHIFT)) & WUU_DE_WUDE4_MASK)
|
|
|
|
#define WUU_DE_WUDE6_MASK (0x40U)
|
|
#define WUU_DE_WUDE6_SHIFT (6U)
|
|
/*! WUDE6 - DMA/Trigger Wake-up Enable for Module 6 */
|
|
#define WUU_DE_WUDE6(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE6_SHIFT)) & WUU_DE_WUDE6_MASK)
|
|
|
|
#define WUU_DE_WUDE8_MASK (0x100U)
|
|
#define WUU_DE_WUDE8_SHIFT (8U)
|
|
/*! WUDE8 - DMA/Trigger Wake-up Enable for Module 8 */
|
|
#define WUU_DE_WUDE8(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE8_SHIFT)) & WUU_DE_WUDE8_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PF - Pin Flag */
|
|
/*! @{ */
|
|
|
|
#define WUU_PF_Reserved0_MASK (0x1U)
|
|
#define WUU_PF_Reserved0_SHIFT (0U)
|
|
/*! Reserved0 - Reserved
|
|
* 0b0..Not supported
|
|
* 0b1..Not supported
|
|
*/
|
|
#define WUU_PF_Reserved0(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved0_SHIFT)) & WUU_PF_Reserved0_MASK)
|
|
|
|
#define WUU_PF_Reserved1_MASK (0x2U)
|
|
#define WUU_PF_Reserved1_SHIFT (1U)
|
|
/*! Reserved1 - Reserved
|
|
* 0b0..Not supported
|
|
* 0b1..Not supported
|
|
*/
|
|
#define WUU_PF_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved1_SHIFT)) & WUU_PF_Reserved1_MASK)
|
|
|
|
#define WUU_PF_WUF2_MASK (0x4U)
|
|
#define WUU_PF_WUF2_SHIFT (2U)
|
|
/*! WUF2 - Wake-up Flag for WUU_Pn
|
|
* 0b0..No
|
|
* 0b1..Yes
|
|
*/
|
|
#define WUU_PF_WUF2(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF2_SHIFT)) & WUU_PF_WUF2_MASK)
|
|
|
|
#define WUU_PF_Reserved3_MASK (0x8U)
|
|
#define WUU_PF_Reserved3_SHIFT (3U)
|
|
/*! Reserved3 - Reserved
|
|
* 0b0..Not supported
|
|
* 0b1..Not supported
|
|
*/
|
|
#define WUU_PF_Reserved3(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved3_SHIFT)) & WUU_PF_Reserved3_MASK)
|
|
|
|
#define WUU_PF_Reserved4_MASK (0x10U)
|
|
#define WUU_PF_Reserved4_SHIFT (4U)
|
|
/*! Reserved4 - Reserved
|
|
* 0b0..Not supported
|
|
* 0b1..Not supported
|
|
*/
|
|
#define WUU_PF_Reserved4(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved4_SHIFT)) & WUU_PF_Reserved4_MASK)
|
|
|
|
#define WUU_PF_Reserved5_MASK (0x20U)
|
|
#define WUU_PF_Reserved5_SHIFT (5U)
|
|
/*! Reserved5 - Reserved
|
|
* 0b0..Not supported
|
|
* 0b1..Not supported
|
|
*/
|
|
#define WUU_PF_Reserved5(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved5_SHIFT)) & WUU_PF_Reserved5_MASK)
|
|
|
|
#define WUU_PF_WUF6_MASK (0x40U)
|
|
#define WUU_PF_WUF6_SHIFT (6U)
|
|
/*! WUF6 - Wake-up Flag for WUU_Pn
|
|
* 0b0..No
|
|
* 0b1..Yes
|
|
*/
|
|
#define WUU_PF_WUF6(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF6_SHIFT)) & WUU_PF_WUF6_MASK)
|
|
|
|
#define WUU_PF_WUF7_MASK (0x80U)
|
|
#define WUU_PF_WUF7_SHIFT (7U)
|
|
/*! WUF7 - Wake-up Flag for WUU_Pn
|
|
* 0b0..No
|
|
* 0b1..Yes
|
|
*/
|
|
#define WUU_PF_WUF7(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF7_SHIFT)) & WUU_PF_WUF7_MASK)
|
|
|
|
#define WUU_PF_WUF8_MASK (0x100U)
|
|
#define WUU_PF_WUF8_SHIFT (8U)
|
|
/*! WUF8 - Wake-up Flag for WUU_Pn
|
|
* 0b0..No
|
|
* 0b1..Yes
|
|
*/
|
|
#define WUU_PF_WUF8(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF8_SHIFT)) & WUU_PF_WUF8_MASK)
|
|
|
|
#define WUU_PF_WUF9_MASK (0x200U)
|
|
#define WUU_PF_WUF9_SHIFT (9U)
|
|
/*! WUF9 - Wake-up Flag for WUU_Pn
|
|
* 0b0..No
|
|
* 0b1..Yes
|
|
*/
|
|
#define WUU_PF_WUF9(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF9_SHIFT)) & WUU_PF_WUF9_MASK)
|
|
|
|
#define WUU_PF_WUF10_MASK (0x400U)
|
|
#define WUU_PF_WUF10_SHIFT (10U)
|
|
/*! WUF10 - Wake-up Flag for WUU_Pn
|
|
* 0b0..No
|
|
* 0b1..Yes
|
|
*/
|
|
#define WUU_PF_WUF10(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF10_SHIFT)) & WUU_PF_WUF10_MASK)
|
|
|
|
#define WUU_PF_WUF11_MASK (0x800U)
|
|
#define WUU_PF_WUF11_SHIFT (11U)
|
|
/*! WUF11 - Wake-up Flag for WUU_Pn
|
|
* 0b0..No
|
|
* 0b1..Yes
|
|
*/
|
|
#define WUU_PF_WUF11(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF11_SHIFT)) & WUU_PF_WUF11_MASK)
|
|
|
|
#define WUU_PF_WUF12_MASK (0x1000U)
|
|
#define WUU_PF_WUF12_SHIFT (12U)
|
|
/*! WUF12 - Wake-up Flag for WUU_Pn
|
|
* 0b0..No
|
|
* 0b1..Yes
|
|
*/
|
|
#define WUU_PF_WUF12(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF12_SHIFT)) & WUU_PF_WUF12_MASK)
|
|
|
|
#define WUU_PF_Reserved13_MASK (0x2000U)
|
|
#define WUU_PF_Reserved13_SHIFT (13U)
|
|
/*! Reserved13 - Reserved
|
|
* 0b0..Not supported
|
|
* 0b1..Not supported
|
|
*/
|
|
#define WUU_PF_Reserved13(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved13_SHIFT)) & WUU_PF_Reserved13_MASK)
|
|
|
|
#define WUU_PF_Reserved14_MASK (0x4000U)
|
|
#define WUU_PF_Reserved14_SHIFT (14U)
|
|
/*! Reserved14 - Reserved
|
|
* 0b0..Not supported
|
|
* 0b1..Not supported
|
|
*/
|
|
#define WUU_PF_Reserved14(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved14_SHIFT)) & WUU_PF_Reserved14_MASK)
|
|
|
|
#define WUU_PF_Reserved15_MASK (0x8000U)
|
|
#define WUU_PF_Reserved15_SHIFT (15U)
|
|
/*! Reserved15 - Reserved
|
|
* 0b0..Not supported
|
|
* 0b1..Not supported
|
|
*/
|
|
#define WUU_PF_Reserved15(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved15_SHIFT)) & WUU_PF_Reserved15_MASK)
|
|
|
|
#define WUU_PF_Reserved16_MASK (0x10000U)
|
|
#define WUU_PF_Reserved16_SHIFT (16U)
|
|
/*! Reserved16 - Reserved
|
|
* 0b0..Not supported
|
|
* 0b1..Not supported
|
|
*/
|
|
#define WUU_PF_Reserved16(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved16_SHIFT)) & WUU_PF_Reserved16_MASK)
|
|
|
|
#define WUU_PF_Reserved17_MASK (0x20000U)
|
|
#define WUU_PF_Reserved17_SHIFT (17U)
|
|
/*! Reserved17 - Reserved
|
|
* 0b0..Not supported
|
|
* 0b1..Not supported
|
|
*/
|
|
#define WUU_PF_Reserved17(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved17_SHIFT)) & WUU_PF_Reserved17_MASK)
|
|
|
|
#define WUU_PF_WUF18_MASK (0x40000U)
|
|
#define WUU_PF_WUF18_SHIFT (18U)
|
|
/*! WUF18 - Wake-up Flag for WUU_Pn
|
|
* 0b0..No
|
|
* 0b1..Yes
|
|
*/
|
|
#define WUU_PF_WUF18(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF18_SHIFT)) & WUU_PF_WUF18_MASK)
|
|
|
|
#define WUU_PF_WUF19_MASK (0x80000U)
|
|
#define WUU_PF_WUF19_SHIFT (19U)
|
|
/*! WUF19 - Wake-up Flag for WUU_Pn
|
|
* 0b0..No
|
|
* 0b1..Yes
|
|
*/
|
|
#define WUU_PF_WUF19(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF19_SHIFT)) & WUU_PF_WUF19_MASK)
|
|
|
|
#define WUU_PF_WUF20_MASK (0x100000U)
|
|
#define WUU_PF_WUF20_SHIFT (20U)
|
|
/*! WUF20 - Wake-up Flag for WUU_Pn
|
|
* 0b0..No
|
|
* 0b1..Yes
|
|
*/
|
|
#define WUU_PF_WUF20(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF20_SHIFT)) & WUU_PF_WUF20_MASK)
|
|
|
|
#define WUU_PF_Reserved21_MASK (0x200000U)
|
|
#define WUU_PF_Reserved21_SHIFT (21U)
|
|
/*! Reserved21 - Reserved
|
|
* 0b0..Not supported
|
|
* 0b1..Not supported
|
|
*/
|
|
#define WUU_PF_Reserved21(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved21_SHIFT)) & WUU_PF_Reserved21_MASK)
|
|
|
|
#define WUU_PF_WUF22_MASK (0x400000U)
|
|
#define WUU_PF_WUF22_SHIFT (22U)
|
|
/*! WUF22 - Wake-up Flag for WUU_Pn
|
|
* 0b0..No
|
|
* 0b1..Yes
|
|
*/
|
|
#define WUU_PF_WUF22(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF22_SHIFT)) & WUU_PF_WUF22_MASK)
|
|
|
|
#define WUU_PF_WUF23_MASK (0x800000U)
|
|
#define WUU_PF_WUF23_SHIFT (23U)
|
|
/*! WUF23 - Wake-up Flag for WUU_Pn
|
|
* 0b0..No
|
|
* 0b1..Yes
|
|
*/
|
|
#define WUU_PF_WUF23(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF23_SHIFT)) & WUU_PF_WUF23_MASK)
|
|
|
|
#define WUU_PF_WUF24_MASK (0x1000000U)
|
|
#define WUU_PF_WUF24_SHIFT (24U)
|
|
/*! WUF24 - Wake-up Flag for WUU_Pn
|
|
* 0b0..No
|
|
* 0b1..Yes
|
|
*/
|
|
#define WUU_PF_WUF24(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF24_SHIFT)) & WUU_PF_WUF24_MASK)
|
|
|
|
#define WUU_PF_WUF25_MASK (0x2000000U)
|
|
#define WUU_PF_WUF25_SHIFT (25U)
|
|
/*! WUF25 - Wake-up Flag for WUU_Pn
|
|
* 0b0..No
|
|
* 0b1..Yes
|
|
*/
|
|
#define WUU_PF_WUF25(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF25_SHIFT)) & WUU_PF_WUF25_MASK)
|
|
|
|
#define WUU_PF_WUF26_MASK (0x4000000U)
|
|
#define WUU_PF_WUF26_SHIFT (26U)
|
|
/*! WUF26 - Wake-up Flag for WUU_Pn
|
|
* 0b0..No
|
|
* 0b1..Yes
|
|
*/
|
|
#define WUU_PF_WUF26(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF26_SHIFT)) & WUU_PF_WUF26_MASK)
|
|
|
|
#define WUU_PF_WUF27_MASK (0x8000000U)
|
|
#define WUU_PF_WUF27_SHIFT (27U)
|
|
/*! WUF27 - Wake-up Flag for WUU_Pn
|
|
* 0b0..No
|
|
* 0b1..Yes
|
|
*/
|
|
#define WUU_PF_WUF27(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF27_SHIFT)) & WUU_PF_WUF27_MASK)
|
|
|
|
#define WUU_PF_WUF28_MASK (0x10000000U)
|
|
#define WUU_PF_WUF28_SHIFT (28U)
|
|
/*! WUF28 - Wake-up Flag for WUU_Pn
|
|
* 0b0..No
|
|
* 0b1..Yes
|
|
*/
|
|
#define WUU_PF_WUF28(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF28_SHIFT)) & WUU_PF_WUF28_MASK)
|
|
|
|
#define WUU_PF_WUF29_MASK (0x20000000U)
|
|
#define WUU_PF_WUF29_SHIFT (29U)
|
|
/*! WUF29 - Wake-up Flag for WUU_Pn
|
|
* 0b0..No
|
|
* 0b1..Yes
|
|
*/
|
|
#define WUU_PF_WUF29(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF29_SHIFT)) & WUU_PF_WUF29_MASK)
|
|
|
|
#define WUU_PF_Reserved30_MASK (0x40000000U)
|
|
#define WUU_PF_Reserved30_SHIFT (30U)
|
|
/*! Reserved30 - Reserved
|
|
* 0b0..Not supported
|
|
* 0b1..Not supported
|
|
*/
|
|
#define WUU_PF_Reserved30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved30_SHIFT)) & WUU_PF_Reserved30_MASK)
|
|
|
|
#define WUU_PF_WUF31_MASK (0x80000000U)
|
|
#define WUU_PF_WUF31_SHIFT (31U)
|
|
/*! WUF31 - Wake-up Flag for WUU_Pn
|
|
* 0b0..No
|
|
* 0b1..Yes
|
|
*/
|
|
#define WUU_PF_WUF31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF31_SHIFT)) & WUU_PF_WUF31_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FILT - Pin Filter */
|
|
/*! @{ */
|
|
|
|
#define WUU_FILT_FILTSEL1_MASK (0x1FU)
|
|
#define WUU_FILT_FILTSEL1_SHIFT (0U)
|
|
/*! FILTSEL1 - Filter 1 Pin Select */
|
|
#define WUU_FILT_FILTSEL1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTSEL1_SHIFT)) & WUU_FILT_FILTSEL1_MASK)
|
|
|
|
#define WUU_FILT_FILTE1_MASK (0x60U)
|
|
#define WUU_FILT_FILTE1_SHIFT (5U)
|
|
/*! FILTE1 - Filter 1 Enable
|
|
* 0b00..Disable
|
|
* 0b01..Enable (Detect on rising edge or high level)
|
|
* 0b10..Enable (Detect on falling edge or low level)
|
|
* 0b11..Enable (Detect on any edge)
|
|
*/
|
|
#define WUU_FILT_FILTE1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTE1_SHIFT)) & WUU_FILT_FILTE1_MASK)
|
|
|
|
#define WUU_FILT_FILTF1_MASK (0x80U)
|
|
#define WUU_FILT_FILTF1_SHIFT (7U)
|
|
/*! FILTF1 - Filter 1 Flag
|
|
* 0b0..No
|
|
* 0b1..Yes
|
|
*/
|
|
#define WUU_FILT_FILTF1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTF1_SHIFT)) & WUU_FILT_FILTF1_MASK)
|
|
|
|
#define WUU_FILT_FILTSEL2_MASK (0x1F00U)
|
|
#define WUU_FILT_FILTSEL2_SHIFT (8U)
|
|
/*! FILTSEL2 - Filter 2 Pin Select */
|
|
#define WUU_FILT_FILTSEL2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTSEL2_SHIFT)) & WUU_FILT_FILTSEL2_MASK)
|
|
|
|
#define WUU_FILT_FILTE2_MASK (0x6000U)
|
|
#define WUU_FILT_FILTE2_SHIFT (13U)
|
|
/*! FILTE2 - Filter 2 Enable
|
|
* 0b00..Disable
|
|
* 0b01..Enable (Detect on rising edge or high level)
|
|
* 0b10..Enable (Detect on falling edge or low level)
|
|
* 0b11..Enable (Detect on any edge)
|
|
*/
|
|
#define WUU_FILT_FILTE2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTE2_SHIFT)) & WUU_FILT_FILTE2_MASK)
|
|
|
|
#define WUU_FILT_FILTF2_MASK (0x8000U)
|
|
#define WUU_FILT_FILTF2_SHIFT (15U)
|
|
/*! FILTF2 - Filter 2 Flag
|
|
* 0b0..No
|
|
* 0b1..Yes
|
|
*/
|
|
#define WUU_FILT_FILTF2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTF2_SHIFT)) & WUU_FILT_FILTF2_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PDC1 - Pin DMA/Trigger Configuration 1 */
|
|
/*! @{ */
|
|
|
|
#define WUU_PDC1_Reserved0_MASK (0x3U)
|
|
#define WUU_PDC1_Reserved0_SHIFT (0U)
|
|
/*! Reserved0 - Reserved
|
|
* 0b00..Not supported
|
|
* 0b01..Not supported
|
|
* 0b10..Not supported
|
|
* 0b11..Not supported
|
|
*/
|
|
#define WUU_PDC1_Reserved0(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_Reserved0_SHIFT)) & WUU_PDC1_Reserved0_MASK)
|
|
|
|
#define WUU_PDC1_Reserved1_MASK (0xCU)
|
|
#define WUU_PDC1_Reserved1_SHIFT (2U)
|
|
/*! Reserved1 - Reserved
|
|
* 0b00..Not supported
|
|
* 0b01..Not supported
|
|
* 0b10..Not supported
|
|
* 0b11..Not supported
|
|
*/
|
|
#define WUU_PDC1_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_Reserved1_SHIFT)) & WUU_PDC1_Reserved1_MASK)
|
|
|
|
#define WUU_PDC1_WUPDC2_MASK (0x30U)
|
|
#define WUU_PDC1_WUPDC2_SHIFT (4U)
|
|
/*! WUPDC2 - Wake-up Pin Configuration for WUU_Pn
|
|
* 0b00..Interrupt
|
|
* 0b01..DMA request
|
|
* 0b10..Trigger event
|
|
* 0b11..Reserved
|
|
*/
|
|
#define WUU_PDC1_WUPDC2(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC2_SHIFT)) & WUU_PDC1_WUPDC2_MASK)
|
|
|
|
#define WUU_PDC1_Reserved3_MASK (0xC0U)
|
|
#define WUU_PDC1_Reserved3_SHIFT (6U)
|
|
/*! Reserved3 - Reserved
|
|
* 0b00..Not supported
|
|
* 0b01..Not supported
|
|
* 0b10..Not supported
|
|
* 0b11..Not supported
|
|
*/
|
|
#define WUU_PDC1_Reserved3(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_Reserved3_SHIFT)) & WUU_PDC1_Reserved3_MASK)
|
|
|
|
#define WUU_PDC1_Reserved4_MASK (0x300U)
|
|
#define WUU_PDC1_Reserved4_SHIFT (8U)
|
|
/*! Reserved4 - Reserved
|
|
* 0b00..Not supported
|
|
* 0b01..Not supported
|
|
* 0b10..Not supported
|
|
* 0b11..Not supported
|
|
*/
|
|
#define WUU_PDC1_Reserved4(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_Reserved4_SHIFT)) & WUU_PDC1_Reserved4_MASK)
|
|
|
|
#define WUU_PDC1_Reserved5_MASK (0xC00U)
|
|
#define WUU_PDC1_Reserved5_SHIFT (10U)
|
|
/*! Reserved5 - Reserved
|
|
* 0b00..Not supported
|
|
* 0b01..Not supported
|
|
* 0b10..Not supported
|
|
* 0b11..Not supported
|
|
*/
|
|
#define WUU_PDC1_Reserved5(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_Reserved5_SHIFT)) & WUU_PDC1_Reserved5_MASK)
|
|
|
|
#define WUU_PDC1_WUPDC6_MASK (0x3000U)
|
|
#define WUU_PDC1_WUPDC6_SHIFT (12U)
|
|
/*! WUPDC6 - Wake-up Pin Configuration for WUU_Pn
|
|
* 0b00..Interrupt
|
|
* 0b01..DMA request
|
|
* 0b10..Trigger event
|
|
* 0b11..Reserved
|
|
*/
|
|
#define WUU_PDC1_WUPDC6(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC6_SHIFT)) & WUU_PDC1_WUPDC6_MASK)
|
|
|
|
#define WUU_PDC1_WUPDC7_MASK (0xC000U)
|
|
#define WUU_PDC1_WUPDC7_SHIFT (14U)
|
|
/*! WUPDC7 - Wake-up Pin Configuration for WUU_Pn
|
|
* 0b00..Interrupt
|
|
* 0b01..DMA request
|
|
* 0b10..Trigger event
|
|
* 0b11..Reserved
|
|
*/
|
|
#define WUU_PDC1_WUPDC7(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC7_SHIFT)) & WUU_PDC1_WUPDC7_MASK)
|
|
|
|
#define WUU_PDC1_WUPDC8_MASK (0x30000U)
|
|
#define WUU_PDC1_WUPDC8_SHIFT (16U)
|
|
/*! WUPDC8 - Wake-up Pin Configuration for WUU_Pn
|
|
* 0b00..Interrupt
|
|
* 0b01..DMA request
|
|
* 0b10..Trigger event
|
|
* 0b11..Reserved
|
|
*/
|
|
#define WUU_PDC1_WUPDC8(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC8_SHIFT)) & WUU_PDC1_WUPDC8_MASK)
|
|
|
|
#define WUU_PDC1_WUPDC9_MASK (0xC0000U)
|
|
#define WUU_PDC1_WUPDC9_SHIFT (18U)
|
|
/*! WUPDC9 - Wake-up Pin Configuration for WUU_Pn
|
|
* 0b00..Interrupt
|
|
* 0b01..DMA request
|
|
* 0b10..Trigger event
|
|
* 0b11..Reserved
|
|
*/
|
|
#define WUU_PDC1_WUPDC9(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC9_SHIFT)) & WUU_PDC1_WUPDC9_MASK)
|
|
|
|
#define WUU_PDC1_WUPDC10_MASK (0x300000U)
|
|
#define WUU_PDC1_WUPDC10_SHIFT (20U)
|
|
/*! WUPDC10 - Wake-up Pin Configuration for WUU_Pn
|
|
* 0b00..Interrupt
|
|
* 0b01..DMA request
|
|
* 0b10..Trigger event
|
|
* 0b11..Reserved
|
|
*/
|
|
#define WUU_PDC1_WUPDC10(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC10_SHIFT)) & WUU_PDC1_WUPDC10_MASK)
|
|
|
|
#define WUU_PDC1_WUPDC11_MASK (0xC00000U)
|
|
#define WUU_PDC1_WUPDC11_SHIFT (22U)
|
|
/*! WUPDC11 - Wake-up Pin Configuration for WUU_Pn
|
|
* 0b00..Interrupt
|
|
* 0b01..DMA request
|
|
* 0b10..Trigger event
|
|
* 0b11..Reserved
|
|
*/
|
|
#define WUU_PDC1_WUPDC11(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC11_SHIFT)) & WUU_PDC1_WUPDC11_MASK)
|
|
|
|
#define WUU_PDC1_WUPDC12_MASK (0x3000000U)
|
|
#define WUU_PDC1_WUPDC12_SHIFT (24U)
|
|
/*! WUPDC12 - Wake-up Pin Configuration for WUU_Pn
|
|
* 0b00..Interrupt
|
|
* 0b01..DMA request
|
|
* 0b10..Trigger event
|
|
* 0b11..Reserved
|
|
*/
|
|
#define WUU_PDC1_WUPDC12(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC12_SHIFT)) & WUU_PDC1_WUPDC12_MASK)
|
|
|
|
#define WUU_PDC1_Reserved13_MASK (0xC000000U)
|
|
#define WUU_PDC1_Reserved13_SHIFT (26U)
|
|
/*! Reserved13 - Reserved
|
|
* 0b00..Not supported
|
|
* 0b01..Not supported
|
|
* 0b10..Not supported
|
|
* 0b11..Not supported
|
|
*/
|
|
#define WUU_PDC1_Reserved13(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_Reserved13_SHIFT)) & WUU_PDC1_Reserved13_MASK)
|
|
|
|
#define WUU_PDC1_Reserved14_MASK (0x30000000U)
|
|
#define WUU_PDC1_Reserved14_SHIFT (28U)
|
|
/*! Reserved14 - Reserved
|
|
* 0b00..Not supported
|
|
* 0b01..Not supported
|
|
* 0b10..Not supported
|
|
* 0b11..Not supported
|
|
*/
|
|
#define WUU_PDC1_Reserved14(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_Reserved14_SHIFT)) & WUU_PDC1_Reserved14_MASK)
|
|
|
|
#define WUU_PDC1_Reserved15_MASK (0xC0000000U)
|
|
#define WUU_PDC1_Reserved15_SHIFT (30U)
|
|
/*! Reserved15 - Reserved
|
|
* 0b00..Not supported
|
|
* 0b01..Not supported
|
|
* 0b10..Not supported
|
|
* 0b11..Not supported
|
|
*/
|
|
#define WUU_PDC1_Reserved15(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_Reserved15_SHIFT)) & WUU_PDC1_Reserved15_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PDC2 - Pin DMA/Trigger Configuration 2 */
|
|
/*! @{ */
|
|
|
|
#define WUU_PDC2_Reserved16_MASK (0x3U)
|
|
#define WUU_PDC2_Reserved16_SHIFT (0U)
|
|
/*! Reserved16 - Reserved
|
|
* 0b00..Not supported
|
|
* 0b01..Not supported
|
|
* 0b10..Not supported
|
|
* 0b11..Not supported
|
|
*/
|
|
#define WUU_PDC2_Reserved16(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved16_SHIFT)) & WUU_PDC2_Reserved16_MASK)
|
|
|
|
#define WUU_PDC2_Reserved17_MASK (0xCU)
|
|
#define WUU_PDC2_Reserved17_SHIFT (2U)
|
|
/*! Reserved17 - Reserved
|
|
* 0b00..Not supported
|
|
* 0b01..Not supported
|
|
* 0b10..Not supported
|
|
* 0b11..Not supported
|
|
*/
|
|
#define WUU_PDC2_Reserved17(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved17_SHIFT)) & WUU_PDC2_Reserved17_MASK)
|
|
|
|
#define WUU_PDC2_WUPDC18_MASK (0x30U)
|
|
#define WUU_PDC2_WUPDC18_SHIFT (4U)
|
|
/*! WUPDC18 - Wake-up Pin Configuration for WUU_Pn
|
|
* 0b00..Interrupt
|
|
* 0b01..DMA request
|
|
* 0b10..Trigger event
|
|
* 0b11..Reserved
|
|
*/
|
|
#define WUU_PDC2_WUPDC18(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC18_SHIFT)) & WUU_PDC2_WUPDC18_MASK)
|
|
|
|
#define WUU_PDC2_WUPDC19_MASK (0xC0U)
|
|
#define WUU_PDC2_WUPDC19_SHIFT (6U)
|
|
/*! WUPDC19 - Wake-up Pin Configuration for WUU_Pn
|
|
* 0b00..Interrupt
|
|
* 0b01..DMA request
|
|
* 0b10..Trigger event
|
|
* 0b11..Reserved
|
|
*/
|
|
#define WUU_PDC2_WUPDC19(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC19_SHIFT)) & WUU_PDC2_WUPDC19_MASK)
|
|
|
|
#define WUU_PDC2_WUPDC20_MASK (0x300U)
|
|
#define WUU_PDC2_WUPDC20_SHIFT (8U)
|
|
/*! WUPDC20 - Wake-up Pin Configuration for WUU_Pn
|
|
* 0b00..Interrupt
|
|
* 0b01..DMA request
|
|
* 0b10..Trigger event
|
|
* 0b11..Reserved
|
|
*/
|
|
#define WUU_PDC2_WUPDC20(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC20_SHIFT)) & WUU_PDC2_WUPDC20_MASK)
|
|
|
|
#define WUU_PDC2_Reserved21_MASK (0xC00U)
|
|
#define WUU_PDC2_Reserved21_SHIFT (10U)
|
|
/*! Reserved21 - Reserved
|
|
* 0b00..Not supported
|
|
* 0b01..Not supported
|
|
* 0b10..Not supported
|
|
* 0b11..Not supported
|
|
*/
|
|
#define WUU_PDC2_Reserved21(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved21_SHIFT)) & WUU_PDC2_Reserved21_MASK)
|
|
|
|
#define WUU_PDC2_WUPDC22_MASK (0x3000U)
|
|
#define WUU_PDC2_WUPDC22_SHIFT (12U)
|
|
/*! WUPDC22 - Wake-up Pin Configuration for WUU_Pn
|
|
* 0b00..Interrupt
|
|
* 0b01..DMA request
|
|
* 0b10..Trigger event
|
|
* 0b11..Reserved
|
|
*/
|
|
#define WUU_PDC2_WUPDC22(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC22_SHIFT)) & WUU_PDC2_WUPDC22_MASK)
|
|
|
|
#define WUU_PDC2_WUPDC23_MASK (0xC000U)
|
|
#define WUU_PDC2_WUPDC23_SHIFT (14U)
|
|
/*! WUPDC23 - Wake-up Pin Configuration for WUU_Pn
|
|
* 0b00..Interrupt
|
|
* 0b01..DMA request
|
|
* 0b10..Trigger event
|
|
* 0b11..Reserved
|
|
*/
|
|
#define WUU_PDC2_WUPDC23(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC23_SHIFT)) & WUU_PDC2_WUPDC23_MASK)
|
|
|
|
#define WUU_PDC2_WUPDC24_MASK (0x30000U)
|
|
#define WUU_PDC2_WUPDC24_SHIFT (16U)
|
|
/*! WUPDC24 - Wake-up Pin Configuration for WUU_Pn
|
|
* 0b00..Interrupt
|
|
* 0b01..DMA request
|
|
* 0b10..Trigger event
|
|
* 0b11..Reserved
|
|
*/
|
|
#define WUU_PDC2_WUPDC24(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC24_SHIFT)) & WUU_PDC2_WUPDC24_MASK)
|
|
|
|
#define WUU_PDC2_WUPDC25_MASK (0xC0000U)
|
|
#define WUU_PDC2_WUPDC25_SHIFT (18U)
|
|
/*! WUPDC25 - Wake-up Pin Configuration for WUU_Pn
|
|
* 0b00..Interrupt
|
|
* 0b01..DMA request
|
|
* 0b10..Trigger event
|
|
* 0b11..Reserved
|
|
*/
|
|
#define WUU_PDC2_WUPDC25(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC25_SHIFT)) & WUU_PDC2_WUPDC25_MASK)
|
|
|
|
#define WUU_PDC2_WUPDC26_MASK (0x300000U)
|
|
#define WUU_PDC2_WUPDC26_SHIFT (20U)
|
|
/*! WUPDC26 - Wake-up Pin Configuration for WUU_Pn
|
|
* 0b00..Interrupt
|
|
* 0b01..DMA request
|
|
* 0b10..Trigger event
|
|
* 0b11..Reserved
|
|
*/
|
|
#define WUU_PDC2_WUPDC26(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC26_SHIFT)) & WUU_PDC2_WUPDC26_MASK)
|
|
|
|
#define WUU_PDC2_WUPDC27_MASK (0xC00000U)
|
|
#define WUU_PDC2_WUPDC27_SHIFT (22U)
|
|
/*! WUPDC27 - Wake-up Pin Configuration for WUU_Pn
|
|
* 0b00..Interrupt
|
|
* 0b01..DMA request
|
|
* 0b10..Trigger event
|
|
* 0b11..Reserved
|
|
*/
|
|
#define WUU_PDC2_WUPDC27(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC27_SHIFT)) & WUU_PDC2_WUPDC27_MASK)
|
|
|
|
#define WUU_PDC2_WUPDC28_MASK (0x3000000U)
|
|
#define WUU_PDC2_WUPDC28_SHIFT (24U)
|
|
/*! WUPDC28 - Wake-up Pin Configuration for WUU_Pn
|
|
* 0b00..Interrupt
|
|
* 0b01..DMA request
|
|
* 0b10..Trigger event
|
|
* 0b11..Reserved
|
|
*/
|
|
#define WUU_PDC2_WUPDC28(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC28_SHIFT)) & WUU_PDC2_WUPDC28_MASK)
|
|
|
|
#define WUU_PDC2_WUPDC29_MASK (0xC000000U)
|
|
#define WUU_PDC2_WUPDC29_SHIFT (26U)
|
|
/*! WUPDC29 - Wake-up Pin Configuration for WUU_Pn
|
|
* 0b00..Interrupt
|
|
* 0b01..DMA request
|
|
* 0b10..Trigger event
|
|
* 0b11..Reserved
|
|
*/
|
|
#define WUU_PDC2_WUPDC29(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC29_SHIFT)) & WUU_PDC2_WUPDC29_MASK)
|
|
|
|
#define WUU_PDC2_Reserved30_MASK (0x30000000U)
|
|
#define WUU_PDC2_Reserved30_SHIFT (28U)
|
|
/*! Reserved30 - Reserved
|
|
* 0b00..Not supported
|
|
* 0b01..Not supported
|
|
* 0b10..Not supported
|
|
* 0b11..Not supported
|
|
*/
|
|
#define WUU_PDC2_Reserved30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved30_SHIFT)) & WUU_PDC2_Reserved30_MASK)
|
|
|
|
#define WUU_PDC2_WUPDC31_MASK (0xC0000000U)
|
|
#define WUU_PDC2_WUPDC31_SHIFT (30U)
|
|
/*! WUPDC31 - Wake-up Pin Configuration for WUU_Pn
|
|
* 0b00..Interrupt
|
|
* 0b01..DMA request
|
|
* 0b10..Trigger event
|
|
* 0b11..Reserved
|
|
*/
|
|
#define WUU_PDC2_WUPDC31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC31_SHIFT)) & WUU_PDC2_WUPDC31_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FDC - Pin Filter DMA/Trigger Configuration */
|
|
/*! @{ */
|
|
|
|
#define WUU_FDC_FILTC1_MASK (0x3U)
|
|
#define WUU_FDC_FILTC1_SHIFT (0U)
|
|
/*! FILTC1 - Filter Configuration for FILTn
|
|
* 0b00..Interrupt
|
|
* 0b01..DMA request
|
|
* 0b10..Trigger event
|
|
* 0b11..Reserved
|
|
*/
|
|
#define WUU_FDC_FILTC1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FDC_FILTC1_SHIFT)) & WUU_FDC_FILTC1_MASK)
|
|
|
|
#define WUU_FDC_FILTC2_MASK (0xCU)
|
|
#define WUU_FDC_FILTC2_SHIFT (2U)
|
|
/*! FILTC2 - Filter Configuration for FILTn
|
|
* 0b00..Interrupt
|
|
* 0b01..DMA request
|
|
* 0b10..Trigger event
|
|
* 0b11..Reserved
|
|
*/
|
|
#define WUU_FDC_FILTC2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FDC_FILTC2_SHIFT)) & WUU_FDC_FILTC2_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PMC - Pin Mode Configuration */
|
|
/*! @{ */
|
|
|
|
#define WUU_PMC_Reserved0_MASK (0x1U)
|
|
#define WUU_PMC_Reserved0_SHIFT (0U)
|
|
/*! Reserved0 - Reserved
|
|
* 0b0..Not supported
|
|
* 0b1..Not supported
|
|
*/
|
|
#define WUU_PMC_Reserved0(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved0_SHIFT)) & WUU_PMC_Reserved0_MASK)
|
|
|
|
#define WUU_PMC_Reserved1_MASK (0x2U)
|
|
#define WUU_PMC_Reserved1_SHIFT (1U)
|
|
/*! Reserved1 - Reserved
|
|
* 0b0..Not supported
|
|
* 0b1..Not supported
|
|
*/
|
|
#define WUU_PMC_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved1_SHIFT)) & WUU_PMC_Reserved1_MASK)
|
|
|
|
#define WUU_PMC_WUPMC2_MASK (0x4U)
|
|
#define WUU_PMC_WUPMC2_SHIFT (2U)
|
|
/*! WUPMC2 - Wake-up Pin Mode Configuration for WUU_Pn
|
|
* 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
|
|
* Pin DMA/Trigger Configuration (PDCn).
|
|
* 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
|
|
*/
|
|
#define WUU_PMC_WUPMC2(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC2_SHIFT)) & WUU_PMC_WUPMC2_MASK)
|
|
|
|
#define WUU_PMC_Reserved3_MASK (0x8U)
|
|
#define WUU_PMC_Reserved3_SHIFT (3U)
|
|
/*! Reserved3 - Reserved
|
|
* 0b0..Not supported
|
|
* 0b1..Not supported
|
|
*/
|
|
#define WUU_PMC_Reserved3(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved3_SHIFT)) & WUU_PMC_Reserved3_MASK)
|
|
|
|
#define WUU_PMC_Reserved4_MASK (0x10U)
|
|
#define WUU_PMC_Reserved4_SHIFT (4U)
|
|
/*! Reserved4 - Reserved
|
|
* 0b0..Not supported
|
|
* 0b1..Not supported
|
|
*/
|
|
#define WUU_PMC_Reserved4(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved4_SHIFT)) & WUU_PMC_Reserved4_MASK)
|
|
|
|
#define WUU_PMC_Reserved5_MASK (0x20U)
|
|
#define WUU_PMC_Reserved5_SHIFT (5U)
|
|
/*! Reserved5 - Reserved
|
|
* 0b0..Not supported
|
|
* 0b1..Not supported
|
|
*/
|
|
#define WUU_PMC_Reserved5(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved5_SHIFT)) & WUU_PMC_Reserved5_MASK)
|
|
|
|
#define WUU_PMC_WUPMC6_MASK (0x40U)
|
|
#define WUU_PMC_WUPMC6_SHIFT (6U)
|
|
/*! WUPMC6 - Wake-up Pin Mode Configuration for WUU_Pn
|
|
* 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
|
|
* Pin DMA/Trigger Configuration (PDCn).
|
|
* 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
|
|
*/
|
|
#define WUU_PMC_WUPMC6(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC6_SHIFT)) & WUU_PMC_WUPMC6_MASK)
|
|
|
|
#define WUU_PMC_WUPMC7_MASK (0x80U)
|
|
#define WUU_PMC_WUPMC7_SHIFT (7U)
|
|
/*! WUPMC7 - Wake-up Pin Mode Configuration for WUU_Pn
|
|
* 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
|
|
* Pin DMA/Trigger Configuration (PDCn).
|
|
* 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
|
|
*/
|
|
#define WUU_PMC_WUPMC7(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC7_SHIFT)) & WUU_PMC_WUPMC7_MASK)
|
|
|
|
#define WUU_PMC_WUPMC8_MASK (0x100U)
|
|
#define WUU_PMC_WUPMC8_SHIFT (8U)
|
|
/*! WUPMC8 - Wake-up Pin Mode Configuration for WUU_Pn
|
|
* 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
|
|
* Pin DMA/Trigger Configuration (PDCn).
|
|
* 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
|
|
*/
|
|
#define WUU_PMC_WUPMC8(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC8_SHIFT)) & WUU_PMC_WUPMC8_MASK)
|
|
|
|
#define WUU_PMC_WUPMC9_MASK (0x200U)
|
|
#define WUU_PMC_WUPMC9_SHIFT (9U)
|
|
/*! WUPMC9 - Wake-up Pin Mode Configuration for WUU_Pn
|
|
* 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
|
|
* Pin DMA/Trigger Configuration (PDCn).
|
|
* 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
|
|
*/
|
|
#define WUU_PMC_WUPMC9(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC9_SHIFT)) & WUU_PMC_WUPMC9_MASK)
|
|
|
|
#define WUU_PMC_WUPMC10_MASK (0x400U)
|
|
#define WUU_PMC_WUPMC10_SHIFT (10U)
|
|
/*! WUPMC10 - Wake-up Pin Mode Configuration for WUU_Pn
|
|
* 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
|
|
* Pin DMA/Trigger Configuration (PDCn).
|
|
* 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
|
|
*/
|
|
#define WUU_PMC_WUPMC10(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC10_SHIFT)) & WUU_PMC_WUPMC10_MASK)
|
|
|
|
#define WUU_PMC_WUPMC11_MASK (0x800U)
|
|
#define WUU_PMC_WUPMC11_SHIFT (11U)
|
|
/*! WUPMC11 - Wake-up Pin Mode Configuration for WUU_Pn
|
|
* 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
|
|
* Pin DMA/Trigger Configuration (PDCn).
|
|
* 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
|
|
*/
|
|
#define WUU_PMC_WUPMC11(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC11_SHIFT)) & WUU_PMC_WUPMC11_MASK)
|
|
|
|
#define WUU_PMC_WUPMC12_MASK (0x1000U)
|
|
#define WUU_PMC_WUPMC12_SHIFT (12U)
|
|
/*! WUPMC12 - Wake-up Pin Mode Configuration for WUU_Pn
|
|
* 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
|
|
* Pin DMA/Trigger Configuration (PDCn).
|
|
* 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
|
|
*/
|
|
#define WUU_PMC_WUPMC12(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC12_SHIFT)) & WUU_PMC_WUPMC12_MASK)
|
|
|
|
#define WUU_PMC_Reserved13_MASK (0x2000U)
|
|
#define WUU_PMC_Reserved13_SHIFT (13U)
|
|
/*! Reserved13 - Reserved
|
|
* 0b0..Not supported
|
|
* 0b1..Not supported
|
|
*/
|
|
#define WUU_PMC_Reserved13(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved13_SHIFT)) & WUU_PMC_Reserved13_MASK)
|
|
|
|
#define WUU_PMC_Reserved14_MASK (0x4000U)
|
|
#define WUU_PMC_Reserved14_SHIFT (14U)
|
|
/*! Reserved14 - Reserved
|
|
* 0b0..Not supported
|
|
* 0b1..Not supported
|
|
*/
|
|
#define WUU_PMC_Reserved14(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved14_SHIFT)) & WUU_PMC_Reserved14_MASK)
|
|
|
|
#define WUU_PMC_Reserved15_MASK (0x8000U)
|
|
#define WUU_PMC_Reserved15_SHIFT (15U)
|
|
/*! Reserved15 - Reserved
|
|
* 0b0..Not supported
|
|
* 0b1..Not supported
|
|
*/
|
|
#define WUU_PMC_Reserved15(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved15_SHIFT)) & WUU_PMC_Reserved15_MASK)
|
|
|
|
#define WUU_PMC_Reserved16_MASK (0x10000U)
|
|
#define WUU_PMC_Reserved16_SHIFT (16U)
|
|
/*! Reserved16 - Reserved
|
|
* 0b0..Not supported
|
|
* 0b1..Not supported
|
|
*/
|
|
#define WUU_PMC_Reserved16(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved16_SHIFT)) & WUU_PMC_Reserved16_MASK)
|
|
|
|
#define WUU_PMC_Reserved17_MASK (0x20000U)
|
|
#define WUU_PMC_Reserved17_SHIFT (17U)
|
|
/*! Reserved17 - Reserved
|
|
* 0b0..Not supported
|
|
* 0b1..Not supported
|
|
*/
|
|
#define WUU_PMC_Reserved17(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved17_SHIFT)) & WUU_PMC_Reserved17_MASK)
|
|
|
|
#define WUU_PMC_WUPMC18_MASK (0x40000U)
|
|
#define WUU_PMC_WUPMC18_SHIFT (18U)
|
|
/*! WUPMC18 - Wake-up Pin Mode Configuration for WUU_Pn
|
|
* 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
|
|
* Pin DMA/Trigger Configuration (PDCn).
|
|
* 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
|
|
*/
|
|
#define WUU_PMC_WUPMC18(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC18_SHIFT)) & WUU_PMC_WUPMC18_MASK)
|
|
|
|
#define WUU_PMC_WUPMC19_MASK (0x80000U)
|
|
#define WUU_PMC_WUPMC19_SHIFT (19U)
|
|
/*! WUPMC19 - Wake-up Pin Mode Configuration for WUU_Pn
|
|
* 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
|
|
* Pin DMA/Trigger Configuration (PDCn).
|
|
* 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
|
|
*/
|
|
#define WUU_PMC_WUPMC19(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC19_SHIFT)) & WUU_PMC_WUPMC19_MASK)
|
|
|
|
#define WUU_PMC_WUPMC20_MASK (0x100000U)
|
|
#define WUU_PMC_WUPMC20_SHIFT (20U)
|
|
/*! WUPMC20 - Wake-up Pin Mode Configuration for WUU_Pn
|
|
* 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
|
|
* Pin DMA/Trigger Configuration (PDCn).
|
|
* 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
|
|
*/
|
|
#define WUU_PMC_WUPMC20(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC20_SHIFT)) & WUU_PMC_WUPMC20_MASK)
|
|
|
|
#define WUU_PMC_Reserved21_MASK (0x200000U)
|
|
#define WUU_PMC_Reserved21_SHIFT (21U)
|
|
/*! Reserved21 - Reserved
|
|
* 0b0..Not supported
|
|
* 0b1..Not supported
|
|
*/
|
|
#define WUU_PMC_Reserved21(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved21_SHIFT)) & WUU_PMC_Reserved21_MASK)
|
|
|
|
#define WUU_PMC_WUPMC22_MASK (0x400000U)
|
|
#define WUU_PMC_WUPMC22_SHIFT (22U)
|
|
/*! WUPMC22 - Wake-up Pin Mode Configuration for WUU_Pn
|
|
* 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
|
|
* Pin DMA/Trigger Configuration (PDCn).
|
|
* 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
|
|
*/
|
|
#define WUU_PMC_WUPMC22(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC22_SHIFT)) & WUU_PMC_WUPMC22_MASK)
|
|
|
|
#define WUU_PMC_WUPMC23_MASK (0x800000U)
|
|
#define WUU_PMC_WUPMC23_SHIFT (23U)
|
|
/*! WUPMC23 - Wake-up Pin Mode Configuration for WUU_Pn
|
|
* 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
|
|
* Pin DMA/Trigger Configuration (PDCn).
|
|
* 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
|
|
*/
|
|
#define WUU_PMC_WUPMC23(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC23_SHIFT)) & WUU_PMC_WUPMC23_MASK)
|
|
|
|
#define WUU_PMC_WUPMC24_MASK (0x1000000U)
|
|
#define WUU_PMC_WUPMC24_SHIFT (24U)
|
|
/*! WUPMC24 - Wake-up Pin Mode Configuration for WUU_Pn
|
|
* 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
|
|
* Pin DMA/Trigger Configuration (PDCn).
|
|
* 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
|
|
*/
|
|
#define WUU_PMC_WUPMC24(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC24_SHIFT)) & WUU_PMC_WUPMC24_MASK)
|
|
|
|
#define WUU_PMC_WUPMC25_MASK (0x2000000U)
|
|
#define WUU_PMC_WUPMC25_SHIFT (25U)
|
|
/*! WUPMC25 - Wake-up Pin Mode Configuration for WUU_Pn
|
|
* 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
|
|
* Pin DMA/Trigger Configuration (PDCn).
|
|
* 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
|
|
*/
|
|
#define WUU_PMC_WUPMC25(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC25_SHIFT)) & WUU_PMC_WUPMC25_MASK)
|
|
|
|
#define WUU_PMC_WUPMC26_MASK (0x4000000U)
|
|
#define WUU_PMC_WUPMC26_SHIFT (26U)
|
|
/*! WUPMC26 - Wake-up Pin Mode Configuration for WUU_Pn
|
|
* 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
|
|
* Pin DMA/Trigger Configuration (PDCn).
|
|
* 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
|
|
*/
|
|
#define WUU_PMC_WUPMC26(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC26_SHIFT)) & WUU_PMC_WUPMC26_MASK)
|
|
|
|
#define WUU_PMC_WUPMC27_MASK (0x8000000U)
|
|
#define WUU_PMC_WUPMC27_SHIFT (27U)
|
|
/*! WUPMC27 - Wake-up Pin Mode Configuration for WUU_Pn
|
|
* 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
|
|
* Pin DMA/Trigger Configuration (PDCn).
|
|
* 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
|
|
*/
|
|
#define WUU_PMC_WUPMC27(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC27_SHIFT)) & WUU_PMC_WUPMC27_MASK)
|
|
|
|
#define WUU_PMC_WUPMC28_MASK (0x10000000U)
|
|
#define WUU_PMC_WUPMC28_SHIFT (28U)
|
|
/*! WUPMC28 - Wake-up Pin Mode Configuration for WUU_Pn
|
|
* 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
|
|
* Pin DMA/Trigger Configuration (PDCn).
|
|
* 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
|
|
*/
|
|
#define WUU_PMC_WUPMC28(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC28_SHIFT)) & WUU_PMC_WUPMC28_MASK)
|
|
|
|
#define WUU_PMC_WUPMC29_MASK (0x20000000U)
|
|
#define WUU_PMC_WUPMC29_SHIFT (29U)
|
|
/*! WUPMC29 - Wake-up Pin Mode Configuration for WUU_Pn
|
|
* 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
|
|
* Pin DMA/Trigger Configuration (PDCn).
|
|
* 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
|
|
*/
|
|
#define WUU_PMC_WUPMC29(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC29_SHIFT)) & WUU_PMC_WUPMC29_MASK)
|
|
|
|
#define WUU_PMC_Reserved30_MASK (0x40000000U)
|
|
#define WUU_PMC_Reserved30_SHIFT (30U)
|
|
/*! Reserved30 - Reserved
|
|
* 0b0..Not supported
|
|
* 0b1..Not supported
|
|
*/
|
|
#define WUU_PMC_Reserved30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved30_SHIFT)) & WUU_PMC_Reserved30_MASK)
|
|
|
|
#define WUU_PMC_WUPMC31_MASK (0x80000000U)
|
|
#define WUU_PMC_WUPMC31_SHIFT (31U)
|
|
/*! WUPMC31 - Wake-up Pin Mode Configuration for WUU_Pn
|
|
* 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
|
|
* Pin DMA/Trigger Configuration (PDCn).
|
|
* 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
|
|
*/
|
|
#define WUU_PMC_WUPMC31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC31_SHIFT)) & WUU_PMC_WUPMC31_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FMC - Pin Filter Mode Configuration */
|
|
/*! @{ */
|
|
|
|
#define WUU_FMC_FILTM1_MASK (0x1U)
|
|
#define WUU_FMC_FILTM1_SHIFT (0U)
|
|
/*! FILTM1 - Filter Mode for FILTn
|
|
* 0b0..Active only during Power Down/Deep Power Down mode
|
|
* 0b1..Active during all power modes
|
|
*/
|
|
#define WUU_FMC_FILTM1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FMC_FILTM1_SHIFT)) & WUU_FMC_FILTM1_MASK)
|
|
|
|
#define WUU_FMC_FILTM2_MASK (0x2U)
|
|
#define WUU_FMC_FILTM2_SHIFT (1U)
|
|
/*! FILTM2 - Filter Mode for FILTn
|
|
* 0b0..Active only during Power Down/Deep Power Down mode
|
|
* 0b1..Active during all power modes
|
|
*/
|
|
#define WUU_FMC_FILTM2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FMC_FILTM2_SHIFT)) & WUU_FMC_FILTM2_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group WUU_Register_Masks */
|
|
|
|
|
|
/* WUU - Peripheral instance base addresses */
|
|
/** Peripheral WUU0 base address */
|
|
#define WUU0_BASE (0x40092000u)
|
|
/** Peripheral WUU0 base pointer */
|
|
#define WUU0 ((WUU_Type *)WUU0_BASE)
|
|
/** Array initializer of WUU peripheral base addresses */
|
|
#define WUU_BASE_ADDRS { WUU0_BASE }
|
|
/** Array initializer of WUU peripheral base pointers */
|
|
#define WUU_BASE_PTRS { WUU0 }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group WUU_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- WWDT Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** WWDT - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t MOD; /**< Mode, offset: 0x0 */
|
|
__IO uint32_t TC; /**< Timer Constant, offset: 0x4 */
|
|
__O uint32_t FEED; /**< Feed Sequence, offset: 0x8 */
|
|
__I uint32_t TV; /**< Timer Value, offset: 0xC */
|
|
uint8_t RESERVED_0[4];
|
|
__IO uint32_t WARNINT; /**< Warning Interrupt Compare Value, offset: 0x14 */
|
|
__IO uint32_t WINDOW; /**< Window Compare Value, offset: 0x18 */
|
|
} WWDT_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- WWDT Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup WWDT_Register_Masks WWDT Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name MOD - Mode */
|
|
/*! @{ */
|
|
|
|
#define WWDT_MOD_WDEN_MASK (0x1U)
|
|
#define WWDT_MOD_WDEN_SHIFT (0U)
|
|
/*! WDEN - Watchdog Enable
|
|
* 0b0..Timer stopped
|
|
* 0b1..Timer running
|
|
*/
|
|
#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK)
|
|
|
|
#define WWDT_MOD_WDRESET_MASK (0x2U)
|
|
#define WWDT_MOD_WDRESET_SHIFT (1U)
|
|
/*! WDRESET - Watchdog Reset Enable
|
|
* 0b0..Interrupt
|
|
* 0b1..Reset
|
|
*/
|
|
#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK)
|
|
|
|
#define WWDT_MOD_WDTOF_MASK (0x4U)
|
|
#define WWDT_MOD_WDTOF_SHIFT (2U)
|
|
/*! WDTOF - Watchdog Timeout Flag
|
|
* 0b0..Watchdog event has not occurred.
|
|
* 0b1..Watchdog event has occurred (causes a chip reset if WDRESET = 1).
|
|
*/
|
|
#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK)
|
|
|
|
#define WWDT_MOD_WDINT_MASK (0x8U)
|
|
#define WWDT_MOD_WDINT_SHIFT (3U)
|
|
/*! WDINT - Warning Interrupt Flag
|
|
* 0b0..No flag
|
|
* 0b1..Flag
|
|
*/
|
|
#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK)
|
|
|
|
#define WWDT_MOD_WDPROTECT_MASK (0x10U)
|
|
#define WWDT_MOD_WDPROTECT_SHIFT (4U)
|
|
/*! WDPROTECT - Watchdog Update Mode
|
|
* 0b0..Flexible
|
|
* 0b1..Threshold
|
|
*/
|
|
#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK)
|
|
|
|
#define WWDT_MOD_LOCK_MASK (0x20U)
|
|
#define WWDT_MOD_LOCK_SHIFT (5U)
|
|
/*! LOCK - Lock
|
|
* 0b0..No Lock
|
|
* 0b1..Lock
|
|
*/
|
|
#define WWDT_MOD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK)
|
|
|
|
#define WWDT_MOD_DEBUG_EN_MASK (0x40U)
|
|
#define WWDT_MOD_DEBUG_EN_SHIFT (6U)
|
|
/*! DEBUG_EN - Debug Enable
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define WWDT_MOD_DEBUG_EN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_DEBUG_EN_SHIFT)) & WWDT_MOD_DEBUG_EN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TC - Timer Constant */
|
|
/*! @{ */
|
|
|
|
#define WWDT_TC_COUNT_MASK (0xFFFFFFU)
|
|
#define WWDT_TC_COUNT_SHIFT (0U)
|
|
/*! COUNT - Watchdog Timeout Value */
|
|
#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FEED - Feed Sequence */
|
|
/*! @{ */
|
|
|
|
#define WWDT_FEED_FEED_MASK (0xFFU)
|
|
#define WWDT_FEED_FEED_SHIFT (0U)
|
|
/*! FEED - Feed Value */
|
|
#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TV - Timer Value */
|
|
/*! @{ */
|
|
|
|
#define WWDT_TV_COUNT_MASK (0xFFFFFFU)
|
|
#define WWDT_TV_COUNT_SHIFT (0U)
|
|
/*! COUNT - Counter Timer Value */
|
|
#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name WARNINT - Warning Interrupt Compare Value */
|
|
/*! @{ */
|
|
|
|
#define WWDT_WARNINT_WARNINT_MASK (0x3FFU)
|
|
#define WWDT_WARNINT_WARNINT_SHIFT (0U)
|
|
/*! WARNINT - Watchdog Warning Interrupt Compare Value */
|
|
#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name WINDOW - Window Compare Value */
|
|
/*! @{ */
|
|
|
|
#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU)
|
|
#define WWDT_WINDOW_WINDOW_SHIFT (0U)
|
|
/*! WINDOW - Watchdog Window Value */
|
|
#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group WWDT_Register_Masks */
|
|
|
|
|
|
/* WWDT - Peripheral instance base addresses */
|
|
/** Peripheral WWDT0 base address */
|
|
#define WWDT0_BASE (0x4000C000u)
|
|
/** Peripheral WWDT0 base pointer */
|
|
#define WWDT0 ((WWDT_Type *)WWDT0_BASE)
|
|
/** Array initializer of WWDT peripheral base addresses */
|
|
#define WWDT_BASE_ADDRS { WWDT0_BASE }
|
|
/** Array initializer of WWDT peripheral base pointers */
|
|
#define WWDT_BASE_PTRS { WWDT0 }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group WWDT_Peripheral_Access_Layer */
|
|
|
|
|
|
/*
|
|
** End of section using anonymous unions
|
|
*/
|
|
|
|
#if defined(__ARMCC_VERSION)
|
|
#if (__ARMCC_VERSION >= 6010050)
|
|
#pragma clang diagnostic pop
|
|
#else
|
|
#pragma pop
|
|
#endif
|
|
#elif defined(__GNUC__)
|
|
/* leave anonymous unions enabled */
|
|
#elif defined(__IAR_SYSTEMS_ICC__)
|
|
#pragma language=default
|
|
#else
|
|
#error Not supported compiler type
|
|
#endif
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group Peripheral_access_layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
|
|
* @{
|
|
*/
|
|
|
|
#if defined(__ARMCC_VERSION)
|
|
#if (__ARMCC_VERSION >= 6010050)
|
|
#pragma clang system_header
|
|
#endif
|
|
#elif defined(__IAR_SYSTEMS_ICC__)
|
|
#pragma system_include
|
|
#endif
|
|
|
|
/**
|
|
* @brief Mask and left-shift a bit field value for use in a register bit range.
|
|
* @param field Name of the register bit field.
|
|
* @param value Value of the bit field.
|
|
* @return Masked and shifted value.
|
|
*/
|
|
#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))
|
|
/**
|
|
* @brief Mask and right-shift a register value to extract a bit field value.
|
|
* @param field Name of the register bit field.
|
|
* @param value Value of the register.
|
|
* @return Masked and shifted bit field value.
|
|
*/
|
|
#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group Bit_Field_Generic_Macros */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- SDK Compatibility
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup SDK_Compatibility_Symbols SDK Compatibility
|
|
* @{
|
|
*/
|
|
|
|
/** High Speed SPI (Flexcomm 8) interrupt name */
|
|
#define LSPI_HS_IRQn FLEXCOMM8_IRQn
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group SDK_Compatibility_Symbols */
|
|
|
|
|
|
#endif /* MCXA153_H_ */
|
|
|