597 lines
28 KiB
C
597 lines
28 KiB
C
/*
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** ###################################################################
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** Version: rev. 1.0, 2022-03-29
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** Build: b231122
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**
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** Abstract:
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** Chip specific module features.
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**
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** Copyright 2016 Freescale Semiconductor, Inc.
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** Copyright 2016-2023 NXP
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** SPDX-License-Identifier: BSD-3-Clause
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**
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** http: www.nxp.com
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** mail: support@nxp.com
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**
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** Revisions:
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** - rev. 1.0 (2022-03-29)
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** Initial version based on v0.1UM
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**
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** ###################################################################
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*/
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#ifndef _MCXA153_FEATURES_H_
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#define _MCXA153_FEATURES_H_
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/* SOC module features */
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/* @brief AOI availability on the SoC. */
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#define FSL_FEATURE_SOC_AOI_COUNT (1)
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/* @brief CDOG availability on the SoC. */
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#define FSL_FEATURE_SOC_CDOG_COUNT (1)
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/* @brief CMC availability on the SoC. */
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#define FSL_FEATURE_SOC_CMC_COUNT (1)
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/* @brief CRC availability on the SoC. */
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#define FSL_FEATURE_SOC_CRC_COUNT (1)
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/* @brief CTIMER availability on the SoC. */
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#define FSL_FEATURE_SOC_CTIMER_COUNT (3)
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/* @brief EDMA availability on the SoC. */
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#define FSL_FEATURE_SOC_EDMA_COUNT (1)
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/* @brief EIM availability on the SoC. */
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#define FSL_FEATURE_SOC_EIM_COUNT (1)
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/* @brief EQDC availability on the SoC. */
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#define FSL_FEATURE_SOC_EQDC_COUNT (1)
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/* @brief FMC availability on the SoC. */
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#define FSL_FEATURE_SOC_FMC_COUNT (1)
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/* @brief FREQME availability on the SoC. */
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#define FSL_FEATURE_SOC_FREQME_COUNT (1)
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/* @brief GPIO availability on the SoC. */
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#define FSL_FEATURE_SOC_GPIO_COUNT (4)
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/* @brief SPC availability on the SoC. */
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#define FSL_FEATURE_SOC_SPC_COUNT (1)
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/* @brief I3C availability on the SoC. */
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#define FSL_FEATURE_SOC_I3C_COUNT (1)
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/* @brief INPUTMUX availability on the SoC. */
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#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
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/* @brief LPADC availability on the SoC. */
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#define FSL_FEATURE_SOC_LPADC_COUNT (1)
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/* @brief LPCMP availability on the SoC. */
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#define FSL_FEATURE_SOC_LPCMP_COUNT (2)
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/* @brief LPI2C availability on the SoC. */
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#define FSL_FEATURE_SOC_LPI2C_COUNT (1)
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/* @brief LPSPI availability on the SoC. */
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#define FSL_FEATURE_SOC_LPSPI_COUNT (2)
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/* @brief LPTMR availability on the SoC. */
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#define FSL_FEATURE_SOC_LPTMR_COUNT (1)
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/* @brief LPUART availability on the SoC. */
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#define FSL_FEATURE_SOC_LPUART_COUNT (3)
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/* @brief OSTIMER availability on the SoC. */
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#define FSL_FEATURE_SOC_OSTIMER_COUNT (1)
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/* @brief PORT availability on the SoC. */
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#define FSL_FEATURE_SOC_PORT_COUNT (4)
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/* @brief PWM availability on the SoC. */
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#define FSL_FEATURE_SOC_PWM_COUNT (1)
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/* @brief SCG availability on the SoC. */
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#define FSL_FEATURE_SOC_SCG_COUNT (1)
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/* @brief SYSCON availability on the SoC. */
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#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
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/* @brief USB availability on the SoC. */
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#define FSL_FEATURE_SOC_USB_COUNT (1)
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/* @brief UTICK availability on the SoC. */
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#define FSL_FEATURE_SOC_UTICK_COUNT (1)
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/* @brief WAKETIMER availability on the SoC. */
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#define FSL_FEATURE_SOC_WAKETIMER_COUNT (1)
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/* @brief WWDT availability on the SoC. */
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#define FSL_FEATURE_SOC_WWDT_COUNT (1)
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/* @brief WUU availability on the SoC. */
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#define FSL_FEATURE_SOC_WUU_COUNT (1)
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/* LPADC module features */
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/* @brief FIFO availability on the SoC. */
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#define FSL_FEATURE_LPADC_FIFO_COUNT (1)
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/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */
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#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1)
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/* @brief Has differential mode (bitfield CMDLn[DIFF]). */
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#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0)
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/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */
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#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0)
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/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */
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#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1)
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/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */
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#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1)
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/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */
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#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1)
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/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */
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#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1)
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/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */
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#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1)
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/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */
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#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1)
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/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */
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#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1)
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/* @brief Has internal clock (bitfield CFG[ADCKEN]). */
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#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0)
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/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */
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#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0)
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/* @brief Has calibration (bitfield CFG[CALOFS]). */
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#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0)
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/* @brief Has offset trim (register OFSTRIM). */
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#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1)
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/* @brief Has Trigger status register. */
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#define FSL_FEATURE_LPADC_HAS_TSTAT (1)
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/* @brief Has power select (bitfield CFG[PWRSEL]). */
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#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1)
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/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */
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#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0)
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/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */
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#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0)
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/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */
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#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0)
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/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */
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#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0)
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/* @brief Conversion averaged bitfiled width. */
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#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4)
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/* @brief Has B side channels. */
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#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (0)
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/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */
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#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1)
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/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */
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#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1)
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/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */
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#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1)
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/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */
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#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1)
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/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */
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#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1)
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/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */
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#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1)
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/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */
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#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1)
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/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */
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#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1)
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/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */
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#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1)
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/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */
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#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2)
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/* @brief Number of OFSTRIM bitField */
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#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (1)
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/* AOI module features */
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/* @brief Maximum value of input mux. */
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#define FSL_FEATURE_AOI_MODULE_INPUTS (4)
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/* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */
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#define FSL_FEATURE_AOI_EVENT_COUNT (4)
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/* CDOG module features */
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/* @brief CDOG Has No Reset */
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#define FSL_FEATURE_CDOG_HAS_NO_RESET (1)
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/* CMC module features */
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/* @brief Has SRAM_DIS register */
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#define FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG (0)
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/* @brief Has BSR register */
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#define FSL_FEATURE_MCX_CMC_HAS_BSR_REG (0)
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/* @brief Has RSTCNT register */
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#define FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG (1)
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/* @brief Has BLR register */
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#define FSL_FEATURE_MCX_CMC_HAS_BLR_REG (0)
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/* LPCMP module features */
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/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */
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#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1)
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/* @brief Has IER RRF_IE bitfield. */
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#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1)
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/* @brief Has CSR RRF bitfield. */
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#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1)
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/* @brief Has Round Robin mode (related to existence of registers RRCR0). */
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#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1)
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/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */
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#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1)
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/* CTIMER module features */
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/* @brief CTIMER has no capture channel. */
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#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0)
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/* @brief CTIMER has no capture 2 interrupt. */
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#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0)
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/* @brief CTIMER capture 3 interrupt. */
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#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1)
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/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */
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#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0)
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/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */
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#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1)
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/* @brief CTIMER Has register MSR */
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#define FSL_FEATURE_CTIMER_HAS_MSR (1)
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/* EDMA module features */
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/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
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#define FSL_FEATURE_EDMA_MODULE_CHANNEL (4)
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/* @brief If 8 bytes transfer supported. */
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#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1)
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/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
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#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
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/* @brief If 16 bytes transfer supported. */
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#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1)
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/* @brief Has DMA_Error interrupt vector. */
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#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1)
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/* @brief If 64 bytes transfer supported. */
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#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (1)
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/* @brief If channel clock controlled independently */
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#define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1)
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/* @brief If 128 bytes transfer supported. */
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#define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (1)
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/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */
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#define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (4)
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/* @brief If 128 bytes transfer supported. */
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#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (1)
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/* @brief Has no register bit fields MP_CSR[EBW]. */
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#define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1)
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/* @brief Has register CH_CSR. */
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#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1)
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/* @brief If dma has common clock gate */
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#define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0)
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/* @brief Has channel mux */
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#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1)
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/* @brief If dma channel IRQ support parameter */
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#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0)
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/* @brief Instance has channel mux */
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#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (1)
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/* @brief NBYTES must be multiple of 8 when using scatter gather. */
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#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0)
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/* @brief Has register CH_SBR. */
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#define FSL_FEATURE_EDMA_HAS_SBR (1)
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/* @brief NBYTES must be multiple of 8 when using scatter gather. */
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#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0)
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/* @brief Has no register bit fields CH_SBR[ATTR]. */
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#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1)
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/* @brief Has register bit fields MP_CSR[GMRC]. */
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#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1)
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/* @brief Has register bit field CH_CSR[SWAP]. */
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#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0)
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/* @brief Instance has register bit field CH_CSR[SWAP]. */
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#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0)
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/* @brief Has register bit field CH_SBR[INSTR]. */
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#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0)
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/* @brief Instance has register bit field CH_SBR[INSTR]. */
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#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0)
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/* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */
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#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE (0)
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/* @brief Instance has register CH_MATTR. */
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#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0)
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/* @brief Has register bit field CH_CSR[SIGNEXT]. */
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#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0)
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/* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */
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#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0)
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/* @brief Has register bit field TCD_CSR[BWC]. */
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#define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1)
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/* @brief Instance has register bit field TCD_CSR[BWC]. */
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#define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1)
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/* @brief Has register bit fields TCD_CSR[TMC]. */
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#define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0)
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/* @brief Instance has register bit fields TCD_CSR[TMC]. */
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#define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0)
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/* @brief Has no register bit fields CH_SBR[SEC]. */
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#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (1)
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/* PWM module features */
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/* @brief If (e)FlexPWM has module A channels (outputs). */
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#define FSL_FEATURE_PWM_HAS_CHANNELA (1)
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/* @brief If (e)FlexPWM has module B channels (outputs). */
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#define FSL_FEATURE_PWM_HAS_CHANNELB (1)
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/* @brief If (e)FlexPWM has module X channels (outputs). */
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#define FSL_FEATURE_PWM_HAS_CHANNELX (1)
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/* @brief If (e)FlexPWM has fractional feature. */
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#define FSL_FEATURE_PWM_HAS_FRACTIONAL (0)
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/* @brief If (e)FlexPWM has mux trigger source select bit field. */
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#define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1)
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/* @brief Number of submodules in each (e)FlexPWM module. */
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#define FSL_FEATURE_PWM_SUBMODULE_COUNT (3)
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/* @brief Number of fault channel in each (e)FlexPWM module. */
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#define FSL_FEATURE_PWM_FAULT_CH_COUNT (1)
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/* @brief (e)FlexPWM has no WAITEN Bitfield In CTRL2 Register. */
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#define FSL_FEATURE_PWM_HAS_NO_WAITEN (1)
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/* @brief If (e)FlexPWM has phase delay feature. */
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#define FSL_FEATURE_PWM_HAS_PHASE_DELAY (1)
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/* @brief If (e)FlexPWM has input filter capture feature. */
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#define FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE (1)
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/* @brief If (e)FlexPWM has module capture functionality on A channels (inputs). */
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#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA (0)
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/* @brief If (e)FlexPWM has module capture functionality on B channels (inputs). */
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#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (0)
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/* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */
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#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1)
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/* GPIO module features */
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/* @brief Has GPIO attribute checker register (GACR). */
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#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0)
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/* @brief Has GPIO version ID register (VERID). */
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#define FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER (1)
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/* @brief Has secure/non-secure access protection registers (LOCK, PCNS, PCNP, ICNS, ICNP). */
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#define FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL (0)
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/* @brief Has GPIO port input disable register (PIDR). */
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#define FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL (1)
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/* @brief Has GPIO interrupt/DMA request/trigger output selection. */
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#define FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT (0)
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/* I3C module features */
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/* @brief Has TERM bitfile in MERRWARN register. */
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#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (0)
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/* @brief SOC has no reset driver. */
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#define FSL_FEATURE_I3C_HAS_NO_RESET (0)
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/* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */
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#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0)
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/* @brief Register SCONFIG do not have IDRAND bitfield. */
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#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1)
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/* @brief Register SCONFIG has HDROK bitfield. */
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#define FSL_FEATURE_I3C_HAS_HDROK (1)
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/* @brief Has IBI bytes. */
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#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (1)
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/* LPI2C module features */
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/* @brief Has separate DMA RX and TX requests. */
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#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
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/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
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#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4)
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/* LPSPI module features */
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/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
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#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (4)
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/* @brief Has separate DMA RX and TX requests. */
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#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
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/* @brief Has CCR1 (related to existence of registers CCR1). */
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#define FSL_FEATURE_LPSPI_HAS_CCR1 (1)
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/* LPTMR module features */
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/* @brief Has shared interrupt handler with another LPTMR module. */
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#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
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/* @brief Whether LPTMR counter is 32 bits width. */
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#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1)
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/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */
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#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1)
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/* @brief Do not has prescaler clock source 1. */
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#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0)
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/* @brief Do not has prescaler clock source 3. */
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#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0)
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/* LPUART module features */
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/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
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#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
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/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
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#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
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/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
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#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
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/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
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#define FSL_FEATURE_LPUART_HAS_FIFO (1)
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/* @brief Has 32-bit register MODIR */
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#define FSL_FEATURE_LPUART_HAS_MODIR (1)
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/* @brief Hardware flow control (RTS, CTS) is supported. */
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#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
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/* @brief Infrared (modulation) is supported. */
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#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1)
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/* @brief 2 bits long stop bit is available. */
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#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
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/* @brief If 10-bit mode is supported. */
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#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
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/* @brief If 7-bit mode is supported. */
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#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1)
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/* @brief Baud rate fine adjustment is available. */
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#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
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/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
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#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
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/* @brief Baud rate oversampling is available. */
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#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
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/* @brief Baud rate oversampling is available. */
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#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
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/* @brief Peripheral type. */
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#define FSL_FEATURE_LPUART_IS_SCI (1)
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/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
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#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4)
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/* @brief Supports two match addresses to filter incoming frames. */
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#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
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/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
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#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
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/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
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#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
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/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
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#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
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/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
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#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
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/* @brief Has improved smart card (ISO7816 protocol) support. */
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#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
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/* @brief Has local operation network (CEA709.1-B protocol) support. */
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#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
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/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
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#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
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/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */
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#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1)
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/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
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#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0)
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/* @brief Has separate DMA RX and TX requests. */
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#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
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/* @brief Has separate RX and TX interrupts. */
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#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0)
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/* @brief Has LPAURT_PARAM. */
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#define FSL_FEATURE_LPUART_HAS_PARAM (1)
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/* @brief Has LPUART_VERID. */
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#define FSL_FEATURE_LPUART_HAS_VERID (1)
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/* @brief Has LPUART_GLOBAL. */
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#define FSL_FEATURE_LPUART_HAS_GLOBAL (1)
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/* @brief Has LPUART_PINCFG. */
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#define FSL_FEATURE_LPUART_HAS_PINCFG (1)
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/* @brief Has register MODEM Control. */
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#define FSL_FEATURE_LPUART_HAS_MCR (0)
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/* @brief Has register Half Duplex Control. */
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#define FSL_FEATURE_LPUART_HAS_HDCR (0)
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/* @brief Has register Timeout. */
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#define FSL_FEATURE_LPUART_HAS_TIMEOUT (0)
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/* PORT module features */
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/* @brief Has control lock (register bit PCR[LK]). */
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#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
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/* @brief Has open drain control (register bit PCR[ODE]). */
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#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
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/* @brief Has digital filter (registers DFER, DFCR and DFWR). */
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#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
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/* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */
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#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (0)
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/* @brief Has pull resistor selection available. */
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#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
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/* @brief Has pull resistor enable (register bit PCR[PE]). */
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#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
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/* @brief Has slew rate control (register bit PCR[SRE]). */
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#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
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/* @brief Has passive filter (register bit field PCR[PFE]). */
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#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
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/* @brief Do not has interrupt control (register ISFR). */
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#define FSL_FEATURE_PORT_HAS_NO_INTERRUPT (1)
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/* @brief Has pull value (register bit field PCR[PV]). */
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#define FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE (1)
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/* @brief Has drive strength1 control (register bit PCR[DSE1]). */
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#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 (1)
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/* @brief Has version ID register (register VERID). */
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#define FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER (1)
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/* @brief Has voltage range control (register bit CONFIG[RANGE]). */
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#define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1)
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/* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */
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#define FSL_FEATURE_PORT_SUPPORT_EFT (0)
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/* @brief Has drive strength control (register bit PCR[DSE]). */
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#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
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/* @brief Defines width of PCR[MUX] field. */
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#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (4)
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/* @brief Has dedicated interrupt vector. */
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#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1)
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/* @brief Has independent interrupt control(register ICR). */
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#define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0)
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/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */
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#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0)
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/* @brief Has Input Buffer Enable (register bit field PCR[IBE]). */
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#define FSL_FEATURE_PORT_HAS_INPUT_BUFFER (1)
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/* @brief Has Invert Input (register bit field PCR[INV]). */
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#define FSL_FEATURE_PORT_HAS_INVERT_INPUT (1)
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/* @brief Defines whether PCR[IRQC] bit-field has flag states. */
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#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0)
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/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
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#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0)
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/* EQDC module features */
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/* @brief If EQDC CTRL2 register has EMIP bit field. */
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#define FSL_FEATURE_EQDC_CTRL2_HAS_EMIP_BIT_FIELD (1)
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/* SPC module features */
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/* @brief Has DCDC */
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#define FSL_FEATURE_MCX_SPC_HAS_DCDC (0)
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/* @brief Has SYS LDO */
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#define FSL_FEATURE_MCX_SPC_HAS_SYS_LDO (0)
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/* @brief Has IOVDD_LVDF */
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#define FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD (0)
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/* @brief Has COREVDD_HVDF */
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#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD (0)
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/* @brief Has CORELDO_VDD_DS */
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#define FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS (1)
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/* @brief Has LPBUFF_EN */
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#define FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT (0)
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/* @brief Has COREVDD_IVS_EN */
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#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT (0)
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/* @brief Has SWITCH_STATE */
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#define FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT (1)
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/* @brief Has SRAMRETLDO */
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#define FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG (1)
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/* @brief Has CFG register */
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#define FSL_FEATURE_MCX_SPC_HAS_CFG_REG (1)
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/* @brief Has SRAMLDO_DPD_ON */
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#define FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT (1)
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/* @brief Has CNTRL register */
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#define FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG (0)
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/* @brief Has DPDOWN_PULLDOWN_DISABLE */
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#define FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT (0)
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/* @brief Not have glitch detect */
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#define FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT (1)
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/* SYSCON module features */
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/* @brief Flash page size in bytes */
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#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (128)
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/* @brief Flash sector size in bytes */
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#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (8192)
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/* @brief Flash size in bytes */
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#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (131072)
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/* @brief Support ROMAPI */
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#define FSL_FEATURE_SYSCON_ROMAPI (1)
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/* @brief Powerlib API is different with other series devices */
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#define FSL_FEATURE_POWERLIB_EXTEND (1)
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/* @brief No OSTIMER register in PMC */
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#define FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG (1)
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/* @brief Starter register discontinuous. */
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#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1)
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/* USB module features */
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/* @brief KHCI module instance count */
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#define FSL_FEATURE_USB_KHCI_COUNT (1)
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/* @brief HOST mode enabled */
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#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (0)
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/* @brief OTG mode enabled */
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#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (0)
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/* @brief Size of the USB dedicated RAM */
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#define FSL_FEATURE_USB_KHCI_USB_RAM (0)
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/* @brief Has KEEP_ALIVE_CTRL register */
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#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0)
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/* @brief Has the Dynamic SOF threshold compare support */
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#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0)
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/* @brief Has the VBUS detect support */
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#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (1)
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/* @brief Has the IRC48M module clock support */
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#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1)
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/* @brief Number of endpoints supported */
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#define FSL_FEATURE_USB_ENDPT_COUNT (16)
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/* @brief Has STALL_IL/OL_DIS registers */
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#define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (1)
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/* @brief Has STALL_IH/OH_DIS registers */
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#define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (1)
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/* UTICK module features */
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/* @brief UTICK does not support PD configure. */
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#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1)
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/* VBAT module features */
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/* @brief Has STATUS register */
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#define FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG (0)
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/* @brief Has TAMPER register */
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#define FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG (0)
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/* @brief Has BANDGAP register */
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#define FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER (0)
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/* @brief Has LDOCTL register */
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#define FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG (0)
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/* @brief Has OSCCTL register */
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#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG (0)
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/* @brief Has SWICTL register */
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#define FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG (0)
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/* @brief Has CLKMON register */
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#define FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG (0)
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/* WWDT module features */
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/* @brief Has no RESET register. */
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#define FSL_FEATURE_WWDT_HAS_NO_RESET (1)
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#endif /* _MCXA153_FEATURES_H_ */
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