822 lines
36 KiB
C
822 lines
36 KiB
C
/*
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* Copyright 2023, NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _FSL_CLOCK_H_
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#define _FSL_CLOCK_H_
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#include "fsl_common.h"
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/*! @addtogroup clock */
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/*! @{ */
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/*! @file */
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/*******************************************************************************
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* Definitions
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*****************************************************************************/
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/*! @name Driver version */
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/*@{*/
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/*! @brief CLOCK driver version 1.0.0. */
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#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(1, 0, 0))
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/*@}*/
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/*! @brief Configure whether driver controls clock
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*
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* When set to 0, peripheral drivers will enable clock in initialize function
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* and disable clock in de-initialize function. When set to 1, peripheral
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* driver will not control the clock, application could control the clock out of
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* the driver.
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*
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* @note All drivers share this feature switcher. If it is set to 1, application
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* should handle clock enable and disable for all drivers.
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*/
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
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#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0U
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#endif
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/* Definition for delay API in clock driver, users can redefine it to the real application. */
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#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
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#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (96000000U)
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#endif
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/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
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/*------------------------------------------------------------------------------
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clock_ip_name_t definition:
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------------------------------------------------------------------------------*/
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#define CLK_GATE_REG_OFFSET(value) (((uint32_t)(value)) >> 16U)
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#define CLK_GATE_BIT_SHIFT(value) (((uint32_t)(value)) & 0x0000FFFFU)
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#define REG_PWM0SUBCTL (250U)
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/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
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typedef enum _clock_ip_name
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{
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kCLOCK_GateINPUTMUX0 = (0x00000U | (0U)), /*!< Clock gate name: INPUTMUX0 */
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kCLOCK_InputMux = (0x00000U | (0U)), /*!< Clock gate name: INPUTMUX0 */
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kCLOCK_GateI3C0 = (0x00000U | (1U)), /*!< Clock gate name: I3C0 */
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kCLOCK_GateCTIMER0 = (0x00000U | (2U)), /*!< Clock gate name: CTIMER0 */
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kCLOCK_GateCTIMER1 = (0x00000U | (3U)), /*!< Clock gate name: CTIMER1 */
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kCLOCK_GateCTIMER2 = (0x00000U | (4U)), /*!< Clock gate name: CTIMER2 */
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kCLOCK_GateFREQME = (0x00000U | (5U)), /*!< Clock gate name: FREQME */
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kCLOCK_GateUTICK0 = (0x00000U | (6U)), /*!< Clock gate name: UTICK0 */
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kCLOCK_GateWWDT0 = (0x00000U | (7U)), /*!< Clock gate name: WWDT0 */
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kCLOCK_GateDMA = (0x00000U | (8U)), /*!< Clock gate name: DMA */
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kCLOCK_GateAOI0 = (0x00000U | (9U)), /*!< Clock gate name: AOI0 */
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kCLOCK_GateCRC = (0x00000U | (10U)), /*!< Clock gate name: CRC */
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kCLOCK_Crc0 = (0x00000U | (10U)), /*!< Clock gate name: CRC */
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kCLOCK_GateEIM = (0x00000U | (11U)), /*!< Clock gate name: EIM */
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kCLOCK_GateERM = (0x00000U | (12U)), /*!< Clock gate name: ERM */
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kCLOCK_GateLPI2C0 = (0x00000U | (16U)), /*!< Clock gate name: LPI2C0 */
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kCLOCK_GateLPSPI0 = (0x00000U | (17U)), /*!< Clock gate name: LPSPI0 */
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kCLOCK_GateLPSPI1 = (0x00000U | (18U)), /*!< Clock gate name: LPSPI1 */
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kCLOCK_GateLPUART0 = (0x00000U | (19U)), /*!< Clock gate name: LPUART0 */
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kCLOCK_GateLPUART1 = (0x00000U | (20U)), /*!< Clock gate name: LPUART1 */
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kCLOCK_GateLPUART2 = (0x00000U | (21U)), /*!< Clock gate name: LPUART2 */
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kCLOCK_GateUSB0 = (0x00000U | (22U)), /*!< Clock gate name: USB0 */
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kCLOCK_GateQDC0 = (0x00000U | (23U)), /*!< Clock gate name: QDC0 */
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kCLOCK_GateFLEXPWM0 = (0x00000U | (24U)), /*!< Clock gate name: FLEXPWM0 */
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kCLOCK_GateOSTIMER0 = (0x00000U | (25U)), /*!< Clock gate name: OSTIMER0 */
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kCLOCK_GateADC0 = (0x00000U | (26U)), /*!< Clock gate name: ADC0 */
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kCLOCK_GateCMP0 = (0x00000U | (27U)), /*!< Clock gate name: CMP0 */
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kCLOCK_GateCMP1 = (0x00000U | (28U)), /*!< Clock gate name: CMP1 */
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kCLOCK_GatePORT0 = (0x00000U | (29U)), /*!< Clock gate name: PORT0 */
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kCLOCK_GatePORT1 = (0x00000U | (30U)), /*!< Clock gate name: PORT1 */
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kCLOCK_GatePORT2 = (0x00000U | (31U)), /*!< Clock gate name: PORT2 */
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kCLOCK_GatePORT3 = ((0x10U << 16U) | (0U)), /*!< Clock gate name: PORT3 */
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kCLOCK_GateATX0 = ((0x10U << 16U) | (1U)), /*!< Clock gate name: ATX0 */
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kCLOCK_GateMTR = ((0x10U << 16U) | (2U)), /*!< Clock gate name: MTR */
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kCLOCK_GateTCU = ((0x10U << 16U) | (3U)), /*!< Clock gate name: TCU */
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kCLOCK_GateEZRAMC_RAMA = ((0x10U << 16U) | (4U)), /*!< Clock gate name: EZRAMC_RAMA */
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kCLOCK_GateGPIO0 = ((0x10U << 16U) | (5U)), /*!< Clock gate name: GPIO0 */
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kCLOCK_GateGPIO1 = ((0x10U << 16U) | (6U)), /*!< Clock gate name: GPIO1 */
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kCLOCK_GateGPIO2 = ((0x10U << 16U) | (7U)), /*!< Clock gate name: GPIO2 */
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kCLOCK_GateGPIO3 = ((0x10U << 16U) | (8U)), /*!< Clock gate name: GPIO3 */
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kCLOCK_GateROMCP = ((0x10U << 16U) | (9U)), /*!< Clock gate name: ROMCP */
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kCLOCK_GatePWMSM0 = ((REG_PWM0SUBCTL << 16U) | (0U)), /*!< Clock gate name: FlexPWM SM0 */
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kCLOCK_GatePWMSM1 = ((REG_PWM0SUBCTL << 16U) | (1U)), /*!< Clock gate name: FlexPWM SM1 */
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kCLOCK_GatePWMSM2 = ((REG_PWM0SUBCTL << 16U) | (2U)), /*!< Clock gate name: FlexPWM SM2 */
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kCLOCK_GateNotAvail = (0xFFFFFFFFU), /**< Clock gate name: None */
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} clock_ip_name_t;
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/*! @brief Clock ip name array for AOI. */
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#define AOI_CLOCKS \
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{ \
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kCLOCK_GateAOI0 \
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}
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/*! @brief Clock ip name array for CRC. */
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#define CRC_CLOCKS \
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{ \
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kCLOCK_GateCRC \
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}
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/*! @brief Clock ip name array for CTIMER. */
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#define CTIMER_CLOCKS \
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{ \
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kCLOCK_GateCTIMER0, kCLOCK_GateCTIMER1, kCLOCK_GateCTIMER2 \
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}
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/*! @brief Clock ip name array for DMA. */
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#define DMA_CLOCKS \
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{ \
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kCLOCK_GateDMA \
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}
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/*! @brief Clock gate name array for EDMA. */
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#define EDMA_CLOCKS \
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{ \
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kCLOCK_GateDMA \
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}
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/*! @brief Clock ip name array for ERM. */
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#define ERM_CLOCKS \
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{ \
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kCLOCK_GateERM \
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}
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/*! @brief Clock ip name array for EIM. */
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#define EIM_CLOCKS \
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{ \
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kCLOCK_GateEIM \
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}
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/*! @brief Clock ip name array for FREQME. */
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#define FREQME_CLOCKS \
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{ \
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kCLOCK_GateFREQME \
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}
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/*! @brief Clock ip name array for GPIO. */
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#define GPIO_CLOCKS \
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{ \
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kCLOCK_GateGPIO0, kCLOCK_GateGPIO1, kCLOCK_GateGPIO2, kCLOCK_GateGPIO3 \
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}
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/*! @brief Clock ip name array for I3C */
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#define I3C_CLOCKS \
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{ \
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kCLOCK_GateI3C0 \
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}
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/*! @brief Clock ip name array for INPUTMUX. */
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#define INPUTMUX_CLOCKS \
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{ \
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kCLOCK_GateINPUTMUX0 \
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}
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/*! @brief Clock ip name array for GPIO. */
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#define LPCMP_CLOCKS \
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{ \
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kCLOCK_GateCMP0, kCLOCK_GateCMP1 \
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}
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/*! @brief Clock ip name array for LPADC. */
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#define LPADC_CLOCKS \
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{ \
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kCLOCK_GateADC0 \
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}
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/*! @brief Clock ip name array for LPUART. */
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#define LPUART_CLOCKS \
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{ \
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kCLOCK_GateLPUART0, kCLOCK_GateLPUART1, kCLOCK_GateLPUART2 \
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}
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/*! @brief Clock ip name array for LPI2C. */
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#define LPI2C_CLOCKS \
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{ \
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kCLOCK_GateLPI2C0 \
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}
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/*! @brief Clock ip name array for LSPI. */
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#define LPSPI_CLOCKS \
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{ \
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kCLOCK_GateLPSPI0, kCLOCK_GateLPSPI1 \
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}
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/*! @brief Clock ip name array for MTR. */
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#define MTR_CLOCKS \
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{ \
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kCLOCK_GateMTR \
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}
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/*! @brief Clock ip name array for OSTIMER. */
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#define OSTIMER_CLOCKS \
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{ \
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kCLOCK_GateOSTIMER0 \
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}
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/*! @brief Clock ip name array for PWM. */
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#define PWM_CLOCKS \
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{ \
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{ \
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kCLOCK_GatePWMSM0, kCLOCK_GatePWMSM1, kCLOCK_GatePWMSM2 \
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} \
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}
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/*! @brief Clock ip name array for QDC. */
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#define QDC_CLOCKS \
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{ \
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kCLOCK_GateQDC0 \
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}
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/*! @brief Clock ip name array for UTICK. */
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#define UTICK_CLOCKS \
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{ \
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kCLOCK_GateUTICK0 \
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}
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/*! @brief Clock ip name array for WWDT. */
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#define WWDT_CLOCKS \
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{ \
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kCLOCK_GateWWDT0 \
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}
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/*! @brief Peripherals clock source definition. */
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#define BUS_CLK kCLOCK_BusClk
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/*! @brief Clock name used to get clock frequency. */
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typedef enum _clock_name
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{
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kCLOCK_MainClk, /*!< MAIN_CLK */
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kCLOCK_CoreSysClk, /*!< Core/system clock(CPU_CLK) */
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kCLOCK_SYSTEM_CLK, /*!< AHB clock */
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kCLOCK_BusClk, /*!< Bus clock (AHB clock) */
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kCLOCK_ExtClk, /*!< External Clock */
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kCLOCK_FroHf, /*!< FRO192 */
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kCLOCK_FroHfDiv, /*!< Divided by FRO192 */
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kCLOCK_Clk48M, /*!< CLK48M */
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kCLOCK_Fro12M, /*!< FRO12M */
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kCLOCK_Clk1M, /*!< CLK1M */
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kCLOCK_Fro16K, /*!< FRO16K */
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kCLOCK_Clk16K0, /*!< CLK16K[0] */
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kCLOCK_Clk16K1, /*!< CLK16K[1] */
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kCLOCK_SLOW_CLK, /*!< SYSTEM_CLK divided by 4 */
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} clock_name_t;
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/*! @brief Clock Mux Switches
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* The encoding is as follows each connection identified is 32bits wide while 24bits are valuable
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* starting from LSB upwards
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*
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* [4 bits for choice, 0 means invalid choice] [8 bits mux ID]*
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*
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*/
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#define CLK_ATTACH_REG_OFFSET(value) (((uint32_t)(value)) >> 16U)
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#define CLK_ATTACH_CLK_SEL(value) (((uint32_t)(value)) & 0x0000FFFFU)
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#define CLK_ATTACH_MUX(reg, sel) ((((uint32_t)(reg)) << 16U) | (sel))
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/*! @brief Clock name used to get clock frequency. */
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typedef enum _clock_select_name
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{
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kCLOCK_SelI3C0_FCLK = (0x0A0U), /*!< I3C0_FCLK clock selection */
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kCLOCK_SelCTIMER0 = (0x0A8U), /*!< CTIMER0 clock selection */
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kCLOCK_SelCTIMER1 = (0x0B0U), /*!< CTIMER1 clock selection */
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kCLOCK_SelCTIMER2 = (0x0B8U), /*!< CTIMER2 clock selection */
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kCLOCK_SelLPI2C0 = (0x0C8U), /*!< LPI2C0 clock selection */
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kCLOCK_SelLPSPI0 = (0x0D0U), /*!< LPSPI0 clock selection */
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kCLOCK_SelLPSPI1 = (0x0D8U), /*!< LPSPI1 clock selection */
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kCLOCK_SelLPUART0 = (0x0E0U), /*!< LPUART0 clock selection */
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kCLOCK_SelLPUART1 = (0x0E8U), /*!< LPUART1 clock selection */
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kCLOCK_SelLPUART2 = (0x0F0U), /*!< LPUART2 clock selection */
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kCLOCK_SelUSB0 = (0x0F8U), /*!< USB0 clock selection */
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kCLOCK_SelLPTMR0 = (0x100U), /*!< LPTMR0 clock selection */
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kCLOCK_SelOSTIMER0 = (0x108U), /*!< OSTIMER0 clock selection */
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kCLOCK_SelADC0 = (0x110U), /*!< ADC0 clock selection */
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kCLOCK_SelCMP0_RR = (0x120U), /*!< CMP0_RR clock selection */
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kCLOCK_SelCMP1_RR = (0x130U), /*!< CMP1_RR clock selection */
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kCLOCK_SelTRACE = (0x138U), /*!< TRACE clock selection */
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kCLOCK_SelCLKOUT = (0x140U), /*!< CLKOUT clock selection */
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kCLOCK_SelSYSTICK = (0x148U), /*!< SYSTICK clock selection */
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kCLOCK_SelSCGSCS = (0x200U), /*!< SCG SCS clock selection */
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kCLOCK_SelMax = (0x200U), /*!< MAX clock selection */
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} clock_select_name_t;
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/*!
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* @brief The enumerator of clock attach Id.
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*/
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typedef enum _clock_attach_id
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{
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kCLK_IN_to_MAIN_CLK = CLK_ATTACH_MUX(kCLOCK_SelSCGSCS, 1U), /*!< Attach clk_in to MAIN_CLK. */
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kFRO12M_to_MAIN_CLK = CLK_ATTACH_MUX(kCLOCK_SelSCGSCS, 2U), /*!< Attach FRO_12M to MAIN_CLK. */
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kFRO_HF_to_MAIN_CLK = CLK_ATTACH_MUX(kCLOCK_SelSCGSCS, 3U), /*!< Attach FRO_HF to MAIN_CLK. */
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kCLK_16K_to_MAIN_CLK = CLK_ATTACH_MUX(kCLOCK_SelSCGSCS, 4U), /*!< Attach CLK_16K[1] to MAIN_CLK. */
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kNONE_to_MAIN_CLK = CLK_ATTACH_MUX(kCLOCK_SelSCGSCS, 7U), /*!< Attach NONE to MAIN_CLK. */
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kFRO12M_to_I3C0FCLK = CLK_ATTACH_MUX(kCLOCK_SelI3C0_FCLK, 0U), /*!< Attach FRO12M to I3C0FCLK. */
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kFRO_HF_DIV_to_I3C0FCLK = CLK_ATTACH_MUX(kCLOCK_SelI3C0_FCLK, 2U), /*!< Attach FRO_HF_DIV to I3C0FCLK. */
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kCLK_IN_to_I3C0FCLK = CLK_ATTACH_MUX(kCLOCK_SelI3C0_FCLK, 3U), /*!< Attach CLK_IN to I3C0FCLK. */
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kCLK_1M_to_I3C0FCLK = CLK_ATTACH_MUX(kCLOCK_SelI3C0_FCLK, 5U), /*!< Attach CLK_1M to I3C0FCLK. */
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kNONE_to_I3C0FCLK = CLK_ATTACH_MUX(kCLOCK_SelI3C0_FCLK, 7U), /*!< Attach NONE to I3C0FCLK. */
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kFRO12M_to_CTIMER0 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER0, 0U), /*!< Attach FRO12M to CTIMER0. */
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kFRO_HF_to_CTIMER0 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER0, 1U), /*!< Attach FRO_HF to CTIMER0. */
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kCLK_IN_to_CTIMER0 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER0, 3U), /*!< Attach CLK_IN to CTIMER0. */
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kCLK_16K_to_CTIMER0 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER0, 4U), /*!< Attach CLK_16K to CTIMER0. */
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kCLK_1M_to_CTIMER0 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER0, 5U), /*!< Attach CLK_1M to CTIMER0. */
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kNONE_to_CTIMER0 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER0, 7U), /*!< Attach NONE to CTIMER0. */
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kFRO12M_to_CTIMER1 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER1, 0U), /*!< Attach FRO12M to CTIMER1. */
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kFRO_HF_to_CTIMER1 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER1, 1U), /*!< Attach FRO_HF to CTIMER1. */
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kCLK_IN_to_CTIMER1 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER1, 3U), /*!< Attach CLK_IN to CTIMER1. */
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kCLK_16K_to_CTIMER1 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER1, 4U), /*!< Attach CLK_16K to CTIMER1. */
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kCLK_1M_to_CTIMER1 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER1, 5U), /*!< Attach CLK_1M to CTIMER1. */
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kNONE_to_CTIMER1 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER1, 7U), /*!< Attach NONE to CTIMER1. */
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kFRO12M_to_CTIMER2 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER2, 0U), /*!< Attach FRO12M to CTIMER2. */
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kFRO_HF_to_CTIMER2 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER2, 1U), /*!< Attach FRO_HF to CTIMER2. */
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kCLK_IN_to_CTIMER2 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER2, 3U), /*!< Attach CLK_IN to CTIMER2. */
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kCLK_16K_to_CTIMER2 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER2, 4U), /*!< Attach CLK_16K to CTIMER2. */
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kCLK_1M_to_CTIMER2 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER2, 5U), /*!< Attach CLK_1M to CTIMER2. */
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kNONE_to_CTIMER2 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER2, 7U), /*!< Attach NONE to CTIMER2. */
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kFRO12M_to_LPI2C0 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C0, 0U), /*!< Attach FRO12M to LPI2C0. */
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kFRO_HF_DIV_to_LPI2C0 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C0, 2U), /*!< Attach FRO_HF_DIV to LPI2C0. */
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kCLK_IN_to_LPI2C0 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C0, 3U), /*!< Attach CLK_IN to LPI2C0. */
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kCLK_1M_to_LPI2C0 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C0, 5U), /*!< Attach CLK_1M to LPI2C0. */
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kNONE_to_LPI2C0 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C0, 7U), /*!< Attach NONE to LPI2C0. */
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kFRO12M_to_LPSPI0 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI0, 0U), /*!< Attach FRO12M to LPSPI0. */
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kFRO_HF_DIV_to_LPSPI0 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI0, 2U), /*!< Attach FRO_HF_DIV to LPSPI0. */
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kCLK_IN_to_LPSPI0 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI0, 3U), /*!< Attach CLK_IN to LPSPI0. */
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kCLK_1M_to_LPSPI0 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI0, 5U), /*!< Attach CLK_1M to LPSPI0. */
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kNONE_to_LPSPI0 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI0, 7U), /*!< Attach NONE to LPSPI0. */
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kFRO12M_to_LPSPI1 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI1, 0U), /*!< Attach FRO12M to LPSPI1. */
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kFRO_HF_DIV_to_LPSPI1 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI1, 2U), /*!< Attach FRO_HF_DIV to LPSPI1. */
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kCLK_IN_to_LPSPI1 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI1, 3U), /*!< Attach CLK_IN to LPSPI1. */
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kCLK_1M_to_LPSPI1 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI1, 5U), /*!< Attach CLK_1M to LPSPI1. */
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kNONE_to_LPSPI1 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI1, 7U), /*!< Attach NONE to LPSPI1. */
|
|
|
|
kFRO12M_to_LPUART0 = CLK_ATTACH_MUX(kCLOCK_SelLPUART0, 0U), /*!< Attach FRO12M to LPUART0. */
|
|
kFRO_HF_DIV_to_LPUART0 = CLK_ATTACH_MUX(kCLOCK_SelLPUART0, 2U), /*!< Attach FRO_HF_DIV to LPUART0. */
|
|
kCLK_IN_to_LPUART0 = CLK_ATTACH_MUX(kCLOCK_SelLPUART0, 3U), /*!< Attach CLK_IN to LPUART0. */
|
|
kCLK_16K_to_LPUART0 = CLK_ATTACH_MUX(kCLOCK_SelLPUART0, 4U), /*!< Attach CLK_16K to LPUART0. */
|
|
kCLK_1M_to_LPUART0 = CLK_ATTACH_MUX(kCLOCK_SelLPUART0, 5U), /*!< Attach CLK_1M to LPUART0. */
|
|
kNONE_to_LPUART0 = CLK_ATTACH_MUX(kCLOCK_SelLPUART0, 7U), /*!< Attach NONE to LPUART0. */
|
|
|
|
kFRO12M_to_LPUART1 = CLK_ATTACH_MUX(kCLOCK_SelLPUART1, 0U), /*!< Attach FRO12M to LPUART1. */
|
|
kFRO_HF_DIV_to_LPUART1 = CLK_ATTACH_MUX(kCLOCK_SelLPUART1, 2U), /*!< Attach FRO_HF_DIV to LPUART1. */
|
|
kCLK_IN_to_LPUART1 = CLK_ATTACH_MUX(kCLOCK_SelLPUART1, 3U), /*!< Attach CLK_IN to LPUART1. */
|
|
kCLK_16K_to_LPUART1 = CLK_ATTACH_MUX(kCLOCK_SelLPUART1, 4U), /*!< Attach CLK_16K to LPUART1. */
|
|
kCLK_1M_to_LPUART1 = CLK_ATTACH_MUX(kCLOCK_SelLPUART1, 5U), /*!< Attach CLK_1M to LPUART1. */
|
|
kNONE_to_LPUART1 = CLK_ATTACH_MUX(kCLOCK_SelLPUART1, 7U), /*!< Attach NONE to LPUART1. */
|
|
|
|
kFRO12M_to_LPUART2 = CLK_ATTACH_MUX(kCLOCK_SelLPUART2, 0U), /*!< Attach FRO12M to LPUART2. */
|
|
kFRO_HF_DIV_to_LPUART2 = CLK_ATTACH_MUX(kCLOCK_SelLPUART2, 2U), /*!< Attach FRO_HF_DIV to LPUART2. */
|
|
kCLK_IN_to_LPUART2 = CLK_ATTACH_MUX(kCLOCK_SelLPUART2, 3U), /*!< Attach CLK_IN to LPUART2. */
|
|
kCLK_16K_to_LPUART2 = CLK_ATTACH_MUX(kCLOCK_SelLPUART2, 4U), /*!< Attach CLK_16K to LPUART2. */
|
|
kCLK_1M_to_LPUART2 = CLK_ATTACH_MUX(kCLOCK_SelLPUART2, 5U), /*!< Attach CLK_1M to LPUART2. */
|
|
kNONE_to_LPUART2 = CLK_ATTACH_MUX(kCLOCK_SelLPUART2, 7U), /*!< Attach NONE to LPUART2. */
|
|
|
|
kCLK_48M_to_USB0 = CLK_ATTACH_MUX(kCLOCK_SelUSB0, 1U), /*!< Attach FRO12M to USB0. */
|
|
kCLK_IN_to_USB0 = CLK_ATTACH_MUX(kCLOCK_SelUSB0, 2U), /*!< Attach CLK_IN to USB0. */
|
|
kNONE_to_USB0 = CLK_ATTACH_MUX(kCLOCK_SelUSB0, 3U), /*!< Attach NONE to USB0. */
|
|
|
|
kFRO12M_to_LPTMR0 = CLK_ATTACH_MUX(kCLOCK_SelLPTMR0, 0U), /*!< Attach FRO12M to LPTMR0. */
|
|
kFRO_HF_DIV_to_LPTMR0 = CLK_ATTACH_MUX(kCLOCK_SelLPTMR0, 2U), /*!< Attach FRO_HF_DIV to LPTMR0. */
|
|
kCLK_IN_to_LPTMR0 = CLK_ATTACH_MUX(kCLOCK_SelLPTMR0, 3U), /*!< Attach CLK_IN to LPTMR0. */
|
|
kCLK_1M_to_LPTMR0 = CLK_ATTACH_MUX(kCLOCK_SelLPTMR0, 5U), /*!< Attach CLK_1M to LPTMR0. */
|
|
kNONE_to_LPTMR0 = CLK_ATTACH_MUX(kCLOCK_SelLPTMR0, 7U), /*!< Attach NONE to LPTMR0. */
|
|
|
|
kCLK_16K_to_OSTIMER = CLK_ATTACH_MUX(kCLOCK_SelOSTIMER0, 0U), /*!< Attach FRO16K to OSTIMER0. */
|
|
kCLK_1M_to_OSTIMER = CLK_ATTACH_MUX(kCLOCK_SelOSTIMER0, 2U), /*!< Attach CLK_1M to OSTIMER0. */
|
|
kNONE_to_OSTIMER = CLK_ATTACH_MUX(kCLOCK_SelOSTIMER0, 3U), /*!< Attach NONE to OSTIMER0. */
|
|
|
|
kFRO12M_to_ADC0 = CLK_ATTACH_MUX(kCLOCK_SelADC0, 0U), /*!< Attach FRO12M to ADC0. */
|
|
kFRO_HF_to_ADC0 = CLK_ATTACH_MUX(kCLOCK_SelADC0, 1U), /*!< Attach FRO_HF to ADC0. */
|
|
kCLK_IN_to_ADC0 = CLK_ATTACH_MUX(kCLOCK_SelADC0, 3U), /*!< Attach CLK_IN to ADC0. */
|
|
kCLK_1M_to_ADC0 = CLK_ATTACH_MUX(kCLOCK_SelADC0, 5U), /*!< Attach CLK_1M to ADC0. */
|
|
kNONE_to_ADC0 = CLK_ATTACH_MUX(kCLOCK_SelADC0, 7U), /*!< Attach NONE to ADC0. */
|
|
|
|
kFRO12M_to_CMP0 = CLK_ATTACH_MUX(kCLOCK_SelCMP0_RR, 0U), /*!< Attach FRO12M to CMP0. */
|
|
kFRO_HF_DIV_to_CMP0 = CLK_ATTACH_MUX(kCLOCK_SelCMP0_RR, 2U), /*!< Attach FRO_HF_DIV to CMP0. */
|
|
kCLK_IN_to_CMP0 = CLK_ATTACH_MUX(kCLOCK_SelCMP0_RR, 3U), /*!< Attach CLK_IN to CMP0. */
|
|
kCLK_1M_to_CMP0 = CLK_ATTACH_MUX(kCLOCK_SelCMP0_RR, 5U), /*!< Attach CLK_1M to CMP0. */
|
|
kNONE_to_CMP0 = CLK_ATTACH_MUX(kCLOCK_SelCMP0_RR, 7U), /*!< Attach NONE to CMP0. */
|
|
|
|
kFRO12M_to_CMP1 = CLK_ATTACH_MUX(kCLOCK_SelCMP1_RR, 0U), /*!< Attach FRO12M to CMP1. */
|
|
kFRO_HF_DIV_to_CMP1 = CLK_ATTACH_MUX(kCLOCK_SelCMP1_RR, 2U), /*!< Attach FRO_HF_DIV to CMP1. */
|
|
kCLK_IN_to_CMP1 = CLK_ATTACH_MUX(kCLOCK_SelCMP1_RR, 3U), /*!< Attach CLK_IN to CMP1. */
|
|
kCLK_1M_to_CMP1 = CLK_ATTACH_MUX(kCLOCK_SelCMP1_RR, 5U), /*!< Attach CLK_1M to CMP1. */
|
|
kNONE_to_CMP1 = CLK_ATTACH_MUX(kCLOCK_SelCMP1_RR, 7U), /*!< Attach NONE to CMP1. */
|
|
|
|
kCPU_CLK_to_TRACE = CLK_ATTACH_MUX(kCLOCK_SelTRACE, 0U), /*!< Attach CPU_CLK to TRACE. */
|
|
kCLK_1M_to_TRACE = CLK_ATTACH_MUX(kCLOCK_SelTRACE, 1U), /*!< Attach CLK_1M to TRACE. */
|
|
kCLK_16K_to_TRACE = CLK_ATTACH_MUX(kCLOCK_SelTRACE, 2U), /*!< Attach CLK_16K to TRACE. */
|
|
kNONE_to_TRACE = CLK_ATTACH_MUX(kCLOCK_SelTRACE, 3U), /*!< Attach NONE to TRACE. */
|
|
|
|
kFRO12M_to_CLKOUT = CLK_ATTACH_MUX(kCLOCK_SelCLKOUT, 0U), /*!< Attach FRO12M to CLKOUT. */
|
|
kFRO_HF_DIV_to_CLKOUT = CLK_ATTACH_MUX(kCLOCK_SelCLKOUT, 1U), /*!< Attach FRO_HF_DIV to CLKOUT. */
|
|
kCLK_IN_to_CLKOUT = CLK_ATTACH_MUX(kCLOCK_SelCLKOUT, 2U), /*!< Attach CLK_IN to CLKOUT. */
|
|
kCLK_16K_to_CLKOUT = CLK_ATTACH_MUX(kCLOCK_SelCLKOUT, 3U), /*!< Attach CLK_16K to CLKOUT. */
|
|
kSLOW_CLK_to_CLKOUT = CLK_ATTACH_MUX(kCLOCK_SelCLKOUT, 6U), /*!< Attach SLOW_CLK to CLKOUT. */
|
|
kNONE_to_CLKOUT = CLK_ATTACH_MUX(kCLOCK_SelCLKOUT, 7U), /*!< Attach NONE to CLKOUT. */
|
|
|
|
kCPU_CLK_to_SYSTICK = CLK_ATTACH_MUX(kCLOCK_SelSYSTICK, 0U), /*!< Attach CPU_CLK to SYSTICK. */
|
|
kCLK_1M_to_SYSTICK = CLK_ATTACH_MUX(kCLOCK_SelSYSTICK, 1U), /*!< Attach CLK_1M to SYSTICK. */
|
|
kCLK_16K_to_SYSTICK = CLK_ATTACH_MUX(kCLOCK_SelSYSTICK, 2U), /*!< Attach CLK_16K to SYSTICK. */
|
|
kNONE_to_SYSTICK = CLK_ATTACH_MUX(kCLOCK_SelSYSTICK, 3U), /*!< Attach NONE to SYSTICK. */
|
|
|
|
kNONE_to_NONE = (0xFFFFFFFFU), /*!< Attach NONE to NONE. */
|
|
|
|
} clock_attach_id_t;
|
|
|
|
/*! @brief Clock dividers */
|
|
typedef enum _clock_div_name
|
|
{
|
|
kCLOCK_DivI3C0_FCLK = (0x0A4U), /*!< I3C0_FCLK clock divider */
|
|
kCLOCK_DivCTIMER0 = (0x0ACU), /*!< CTIMER0 clock divider */
|
|
kCLOCK_DivCTIMER1 = (0x0B4U), /*!< CTIMER1 clock divider */
|
|
kCLOCK_DivCTIMER2 = (0x0BCU), /*!< CTIMER2 clock divider */
|
|
kCLOCK_DivWWDT0 = (0x0C4U), /*!< WWDT0 clock divider */
|
|
kCLOCK_DivLPI2C0 = (0x0CCU), /*!< LPI2C0 clock divider */
|
|
kCLOCK_DivLPSPI0 = (0x0D4U), /*!< LPSPI0 clock divider */
|
|
kCLOCK_DivLPSPI1 = (0x0DCU), /*!< LPSPI1 clock divider */
|
|
kCLOCK_DivLPUART0 = (0x0E4U), /*!< LPUART0 clock divider */
|
|
kCLOCK_DivLPUART1 = (0x0ECU), /*!< LPUART1 clock divider */
|
|
kCLOCK_DivLPUART2 = (0x0F4U), /*!< LPUART2 clock divider */
|
|
kCLOCK_DivLPTMR0 = (0x104U), /*!< LPTMR0 clock divider */
|
|
kCLOCK_DivADC0 = (0x114U), /*!< ADC0 clock divider */
|
|
kCLOCK_DivCMP0_FUNC = (0x11CU), /*!< CMP0_FUNC clock divider */
|
|
kCLOCK_DivCMP0_RR = (0x124U), /*!< CMP0_RR clock divider */
|
|
kCLOCK_DivCMP1_FUNC = (0x12CU), /*!< CMP1_FUNC clock divider */
|
|
kCLOCK_DivCMP1_RR = (0x134U), /*!< CMP1_RR clock divider */
|
|
kCLOCK_DivTRACE = (0x13CU), /*!< TRACE clock divider */
|
|
kCLOCK_DivCLKOUT = (0x144U), /*!< CLKOUT clock divider */
|
|
kCLOCK_DivSYSTICK = (0x14CU), /*!< SYSTICK clock divider */
|
|
kCLOCK_DivFRO_HF_DIV = (0x154U), /*!< FRO_HF_DIV clock divider */
|
|
kCLOCK_DivSLOWCLK = (0x378U), /*!< SLOWCLK clock divider */
|
|
kCLOCK_DivAHBCLK = (0x380U), /*!< System clock divider */
|
|
kCLOCK_DivMax = (0x380U), /*!< MAX clock divider */
|
|
} clock_div_name_t;
|
|
|
|
/*!
|
|
* @brief firc trim mode.
|
|
*/
|
|
typedef enum _firc_trim_mode
|
|
{
|
|
kSCG_FircTrimNonUpdate = SCG_FIRCCSR_FIRCTREN_MASK,
|
|
/*!< Trim enable but not enable trim value update. In this mode, the
|
|
trim value is fixed to the initialized value which is defined by
|
|
trimCoar and trimFine in configure structure \ref firc_trim_config_t.*/
|
|
|
|
kSCG_FircTrimUpdate = SCG_FIRCCSR_FIRCTREN_MASK | SCG_FIRCCSR_FIRCTRUP_MASK
|
|
/*!< Trim enable and trim value update enable. In this mode, the trim
|
|
value is auto update. */
|
|
|
|
} firc_trim_mode_t;
|
|
|
|
/*!
|
|
* @brief firc trim source.
|
|
*/
|
|
typedef enum _firc_trim_src
|
|
{
|
|
kSCG_FircTrimSrcUsb0 = 0U, /*!< USB0 start of frame (1kHz). */
|
|
kSCG_FircTrimSrcSysOsc = 2U, /*!< System OSC. */
|
|
} firc_trim_src_t;
|
|
|
|
/*!
|
|
* @brief firc trim configuration.
|
|
*/
|
|
typedef struct _firc_trim_config
|
|
{
|
|
firc_trim_mode_t trimMode; /*!< Trim mode. */
|
|
firc_trim_src_t trimSrc; /*!< Trim source. */
|
|
uint16_t trimDiv; /*!< Divider of SOSC. */
|
|
uint8_t trimCoar; /*!< Trim coarse value; Irrelevant if trimMode is kSCG_TrimUpdate. */
|
|
uint8_t trimFine; /*!< Trim fine value; Irrelevant if trimMode is kSCG_TrimUpdate. */
|
|
} firc_trim_config_t;
|
|
|
|
/*!
|
|
* @brief sirc trim mode.
|
|
*/
|
|
typedef enum _sirc_trim_mode
|
|
{
|
|
kSCG_SircTrimNonUpdate = SCG_SIRCCSR_SIRCTREN_MASK,
|
|
/*!< Trim enable but not enable trim value update. In this mode, the
|
|
trim value is fixed to the initialized value which is defined by
|
|
trimCoar and trimFine in configure structure \ref sirc_trim_config_t.*/
|
|
|
|
kSCG_SircTrimUpdate = SCG_SIRCCSR_SIRCTREN_MASK | SCG_SIRCCSR_SIRCTRUP_MASK
|
|
/*!< Trim enable and trim value update enable. In this mode, the trim
|
|
value is auto update. */
|
|
|
|
} sirc_trim_mode_t;
|
|
|
|
/*!
|
|
* @brief sirc trim source.
|
|
*/
|
|
typedef enum _sirc_trim_src
|
|
{
|
|
kNoTrimSrc = 0, /*!< No external tirm source. */
|
|
kSCG_SircTrimSrcSysOsc = 2U, /*!< System OSC. */
|
|
} sirc_trim_src_t;
|
|
|
|
/*!
|
|
* @brief sirc trim configuration.
|
|
*/
|
|
typedef struct _sirc_trim_config
|
|
{
|
|
sirc_trim_mode_t trimMode; /*!< Trim mode. */
|
|
sirc_trim_src_t trimSrc; /*!< Trim source. */
|
|
uint16_t trimDiv; /*!< Divider of SOSC. */
|
|
uint8_t cltrim; /*!< Trim coarse value; Irrelevant if trimMode is kSCG_TrimUpdate. */
|
|
uint8_t ccotrim; /*!< Trim fine value; Irrelevant if trimMode is kSCG_TrimUpdate. */
|
|
} sirc_trim_config_t;
|
|
|
|
/*!
|
|
* @brief SCG system OSC monitor mode.
|
|
*/
|
|
typedef enum _scg_sosc_monitor_mode
|
|
{
|
|
kSCG_SysOscMonitorDisable = 0U, /*!< Monitor disabled. */
|
|
kSCG_SysOscMonitorInt = SCG_SOSCCSR_SOSCCM_MASK, /*!< Interrupt when the SOSC error is detected. */
|
|
kSCG_SysOscMonitorReset =
|
|
SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCCMRE_MASK /*!< Reset when the SOSC error is detected. */
|
|
} scg_sosc_monitor_mode_t;
|
|
|
|
/*!
|
|
* @brief firc trim source.
|
|
*/
|
|
typedef enum _clke_16k
|
|
{
|
|
kCLKE_16K_SYSTEM = VBAT_FROCLKE_CLKE(1U), /*!< To VSYS domain. */
|
|
kCLKE_16K_COREMAIN = VBAT_FROCLKE_CLKE(2U) /*!< To VDD_CORE domain. */
|
|
} clke_16k_t;
|
|
|
|
/*******************************************************************************
|
|
* API
|
|
******************************************************************************/
|
|
|
|
#if defined(__cplusplus)
|
|
extern "C" {
|
|
#endif /* __cplusplus */
|
|
|
|
/**
|
|
* @brief Enable the clock for specific IP.
|
|
* @param clk : Clock to be enabled.
|
|
* @return Nothing
|
|
*/
|
|
static inline void CLOCK_EnableClock(clock_ip_name_t clk)
|
|
{
|
|
uint32_t reg_offset = CLK_GATE_REG_OFFSET(clk);
|
|
uint32_t bit_shift = CLK_GATE_BIT_SHIFT(clk);
|
|
volatile uint32_t *pClkCtrl = (volatile uint32_t *)((uint32_t)(&(MRCC0->MRCC_GLB_CC0_SET)) + reg_offset);
|
|
|
|
if (clk == kCLOCK_GateNotAvail)
|
|
{
|
|
return;
|
|
}
|
|
|
|
/* Unlock clock configuration */
|
|
SYSCON->CLKUNLOCK &= ~SYSCON_CLKUNLOCK_UNLOCK_MASK;
|
|
|
|
if (reg_offset == REG_PWM0SUBCTL)
|
|
{
|
|
SYSCON->PWM0SUBCTL |= (1UL << bit_shift);
|
|
MRCC0->MRCC_GLB_CC0_SET = MRCC_MRCC_GLB_CC0_FLEXPWM0_MASK;
|
|
}
|
|
else
|
|
{
|
|
*pClkCtrl = (1UL << bit_shift);
|
|
}
|
|
|
|
/* Freeze clock configuration */
|
|
SYSCON->CLKUNLOCK |= SYSCON_CLKUNLOCK_UNLOCK_MASK;
|
|
}
|
|
|
|
/**
|
|
* @brief Disable the clock for specific IP.
|
|
* @param clk : Clock to be Disabled.
|
|
* @return Nothing
|
|
*/
|
|
static inline void CLOCK_DisableClock(clock_ip_name_t clk)
|
|
{
|
|
uint32_t reg_offset = CLK_GATE_REG_OFFSET(clk);
|
|
uint32_t bit_shift = CLK_GATE_BIT_SHIFT(clk);
|
|
volatile uint32_t *pClkCtrl = (volatile uint32_t *)((uint32_t)(&(MRCC0->MRCC_GLB_CC0_CLR)) + reg_offset);
|
|
|
|
if (clk == kCLOCK_GateNotAvail)
|
|
{
|
|
return;
|
|
}
|
|
|
|
/* Unlock clock configuration */
|
|
SYSCON->CLKUNLOCK &= ~SYSCON_CLKUNLOCK_UNLOCK_MASK;
|
|
|
|
if (reg_offset == REG_PWM0SUBCTL)
|
|
{
|
|
SYSCON->PWM0SUBCTL &= ~(1UL << bit_shift);
|
|
|
|
if (0U == (SYSCON->PWM0SUBCTL & 0xFU))
|
|
{
|
|
MRCC0->MRCC_GLB_CC0_CLR = MRCC_MRCC_GLB_CC0_FLEXPWM0_MASK;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
*pClkCtrl = (1UL << bit_shift);
|
|
}
|
|
|
|
/* Freeze clock configuration */
|
|
SYSCON->CLKUNLOCK |= SYSCON_CLKUNLOCK_UNLOCK_MASK;
|
|
}
|
|
|
|
/**
|
|
* @brief Configure the clock selection muxes.
|
|
* @param connection : Clock to be configured.
|
|
* @return Nothing
|
|
*/
|
|
void CLOCK_AttachClk(clock_attach_id_t connection);
|
|
|
|
/**
|
|
* @brief Get the actual clock attach id.
|
|
* This fuction uses the offset in input attach id, then it reads the actual source value in
|
|
* the register and combine the offset to obtain an actual attach id.
|
|
* @param connection : Clock attach id to get.
|
|
* @return Clock source value.
|
|
*/
|
|
clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t connection);
|
|
|
|
/**
|
|
* @brief Set the clock select value.
|
|
* This fuction set the peripheral clock select value.
|
|
* @param sel_name : Clock select.
|
|
* @param value : value to be set.
|
|
*/
|
|
void CLOCK_SetClockSelect(clock_select_name_t sel_name, uint32_t value);
|
|
|
|
/**
|
|
* @brief Get the clock select value.
|
|
* This fuction get the peripheral clock select value.
|
|
* @param sel_name : Clock select.
|
|
* @return Clock source value.
|
|
*/
|
|
uint32_t CLOCK_GetClockSelect(clock_select_name_t sel_name);
|
|
|
|
/**
|
|
* @brief Setup peripheral clock dividers.
|
|
* @param div_name : Clock divider name
|
|
* @param value : Value to be divided
|
|
* @return Nothing
|
|
*/
|
|
void CLOCK_SetClockDiv(clock_div_name_t div_name, uint32_t value);
|
|
|
|
/**
|
|
* @brief Get peripheral clock dividers.
|
|
* @param div_name : Clock divider name
|
|
* @return peripheral clock dividers
|
|
*/
|
|
uint32_t CLOCK_GetClockDiv(clock_div_name_t div_name);
|
|
|
|
/**
|
|
* @brief Halt peripheral clock dividers.
|
|
* @param div_name : Clock divider name
|
|
* @return Nothing
|
|
*/
|
|
void CLOCK_HaltClockDiv(clock_div_name_t div_name);
|
|
|
|
/**
|
|
* @brief Initialize the FROHF to given frequency (48,64,96,192).
|
|
* This function turns on FIRC and select the given frequency as the source of fro_hf
|
|
* @param iFreq : Desired frequency.
|
|
* @return returns success or fail status.
|
|
*/
|
|
status_t CLOCK_SetupFROHFClocking(uint32_t iFreq);
|
|
|
|
/**
|
|
* @brief Initialize the FRO12M.
|
|
* This function turns on FRO12M.
|
|
* @return returns success or fail status.
|
|
*/
|
|
status_t CLOCK_SetupFRO12MClocking(void);
|
|
|
|
/**
|
|
* @brief Initialize the FRO16K.
|
|
* This function turns on FRO16K.
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* @param clk_16k_enable_mask: 0-3
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* 0b00: disable both clk_16k0 and clk_16k1
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* 0b01: only enable clk_16k0
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* 0b10: only enable clk_16k1
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* 0b11: enable both clk_16k0 and clk_16k1
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* @return returns success or fail status.
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*/
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status_t CLOCK_SetupFRO16KClocking(uint8_t clk_16k_enable_mask);
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/**
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* @brief Initialize the external osc clock to given frequency.
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* @param iFreq : Desired frequency (must be equal to exact rate in Hz)
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* @return returns success or fail status.
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*/
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status_t CLOCK_SetupExtClocking(uint32_t iFreq);
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/**
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* @brief Initialize the external reference clock to given frequency.
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* @param iFreq : Desired frequency (must be equal to exact rate in Hz)
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* @return returns success or fail status.
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*/
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status_t CLOCK_SetupExtRefClocking(uint32_t iFreq);
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/*! @brief Return Frequency of selected clock
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* @return Frequency of selected clock
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*/
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uint32_t CLOCK_GetFreq(clock_name_t clockName);
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/*! @brief Return Frequency of core
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* @return Frequency of the core
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*/
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uint32_t CLOCK_GetCoreSysClkFreq(void);
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/*! @brief Return Frequency of I3C FCLK
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* @return Frequency of I3C FCLK.
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*/
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uint32_t CLOCK_GetI3CFClkFreq(void);
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/*! @brief Return Frequency of CTimer functional Clock
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* @return Frequency of CTimer functional Clock
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*/
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uint32_t CLOCK_GetCTimerClkFreq(uint32_t id);
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/*! @brief Return Frequency of LPI2C0 functional Clock
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* @return Frequency of LPI2C0 functional Clock
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*/
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uint32_t CLOCK_GetLpi2cClkFreq(void);
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/*! @brief Return Frequency of LPSPI functional Clock
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* @return Frequency of LPSPI functional Clock
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*/
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uint32_t CLOCK_GetLpspiClkFreq(uint32_t id);
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/*! @brief Return Frequency of LPUART functional Clock
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* @return Frequency of LPUART functional Clock
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*/
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uint32_t CLOCK_GetLpuartClkFreq(uint32_t id);
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/*! @brief Return Frequency of LPTMR functional Clock
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* @return Frequency of LPTMR functional Clock
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*/
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uint32_t CLOCK_GetLptmrClkFreq(void);
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/*! @brief Return Frequency of OSTIMER
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* @return Frequency of OSTIMER Clock
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*/
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uint32_t CLOCK_GetOstimerClkFreq(void);
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/*! @brief Return Frequency of Adc Clock
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* @return Frequency of Adc.
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*/
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uint32_t CLOCK_GetAdcClkFreq(void);
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/*! @brief Return Frequency of CMP Function Clock
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* @return Frequency of CMP Function.
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|
*/
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uint32_t CLOCK_GetCmpFClkFreq(uint32_t id);
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/*! @brief Return Frequency of CMP Round Robin Clock
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* @return Frequency of CMP Round Robin.
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*/
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|
uint32_t CLOCK_GetCmpRRClkFreq(uint32_t id);
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/*! @brief Return Frequency of Trace Clock
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|
* @return Frequency of Trace.
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|
*/
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|
uint32_t CLOCK_GetTraceClkFreq(void);
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/*! @brief Return Frequency of CLKOUT Clock
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|
* @return Frequency of CLKOUT.
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|
*/
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|
uint32_t CLOCK_GetClkoutClkFreq(void);
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|
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/*! @brief Return Frequency of Systick Clock
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|
* @return Frequency of Systick.
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|
*/
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|
uint32_t CLOCK_GetSystickClkFreq(void);
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/*! brief Return Frequency of Systick Clock
|
|
* return Frequency of Systick.
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|
*/
|
|
uint32_t CLOCK_GetWwdtClkFreq(void);
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|
|
|
/**
|
|
* @brief Setup FROHF trim.
|
|
* @param config : FROHF trim value
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|
* @return returns success or fail status.
|
|
*/
|
|
status_t CLOCK_FROHFTrimConfig(firc_trim_config_t config);
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|
|
|
/**
|
|
* @brief Setup FRO 12M trim.
|
|
* @param config : FRO 12M trim value
|
|
* @return returns success or fail status.
|
|
*/
|
|
status_t CLOCK_FRO12MTrimConfig(sirc_trim_config_t config);
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|
|
|
/*!
|
|
* @brief Sets the system OSC monitor mode.
|
|
*
|
|
* This function sets the system OSC monitor mode. The mode can be disabled,
|
|
* it can generate an interrupt when the error is disabled, or reset when the error is detected.
|
|
*
|
|
* @param mode Monitor mode to set.
|
|
*/
|
|
void CLOCK_SetSysOscMonitorMode(scg_sosc_monitor_mode_t mode);
|
|
|
|
/*! brief Enable USB FS clock.
|
|
* Enable USB Full Speed clock.
|
|
*/
|
|
bool CLOCK_EnableUsbfsClock(void);
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|
|
|
#if defined(__cplusplus)
|
|
}
|
|
#endif /* __cplusplus */
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|
|
|
/*! @} */
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|
|
|
#endif /* _FSL_CLOCK_H_ */
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