64 lines
1.5 KiB
C
64 lines
1.5 KiB
C
/*
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* Copyright 2022 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _FSL_EDMA_SOC_H_
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#define _FSL_EDMA_SOC_H_
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#include "fsl_common.h"
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/*!
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* @addtogroup edma_soc
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* @{
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @name Driver version */
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/*@{*/
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/*! @brief Driver version 2.0.0. */
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#define FSL_EDMA_SOC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
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/*@}*/
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/*!@brief DMA IP version */
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#define FSL_EDMA_SOC_IP_DMA3 (1)
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#define FSL_EDMA_SOC_IP_DMA4 (0)
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/*!@brief DMA base table */
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#define EDMA_BASE_PTRS \
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{ \
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DMA0 \
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}
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#define EDMA_CHN_IRQS \
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{ \
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{ \
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DMA_CH0_IRQn, DMA_CH1_IRQn, DMA_CH2_IRQn, DMA_CH3_IRQn \
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} \
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}
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/*!@brief EDMA base address convert macro */
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#define EDMA_CHANNEL_OFFSET 0x1000U
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#define EDMA_CHANNEL_ARRAY_STEP(base) (0x1000U)
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/*******************************************************************************
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* API
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******************************************************************************/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef __cplusplus
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}
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#endif
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/*!
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* @}
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*/
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#endif /* _FSL_EDMA_SOC_H_ */
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