313 lines
9.1 KiB
C
313 lines
9.1 KiB
C
/*
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* Copyright 2022 NXP
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* All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_eim.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.eim"
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#endif
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*! @brief Pointers to EIM bases for each instance. */
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static EIM_Type *const s_eimBases[] = EIM_BASE_PTRS;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/*! @brief Pointers to EIM clocks for each instance. */
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static const clock_ip_name_t s_eimClocks[] = EIM_CLOCKS;
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/*******************************************************************************
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* Code
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******************************************************************************/
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static uint32_t EIM_GetInstance(EIM_Type *base)
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{
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uint32_t instance;
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ARRAY_SIZE(s_eimBases); instance++)
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{
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if (s_eimBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ARRAY_SIZE(s_eimBases));
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return instance;
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}
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/*!
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* brief EIM module initialization function.
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*
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* param base EIM base address.
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*/
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void EIM_Init(EIM_Type *base)
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{
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Ungate EIM clock. */
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CLOCK_EnableClock(s_eimClocks[EIM_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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base->EIMCR = 0x00U;
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base->EICHEN = 0x00U;
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}
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/*!
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* brief Deinitializes the EIM.
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*
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*/
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void EIM_Deinit(EIM_Type *base)
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{
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Ungate EIM clock. */
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CLOCK_DisableClock(s_eimClocks[EIM_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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void EIM_InjectCheckBitError(EIM_Type *base, eim_memory_channel_t channel, uint8_t mask)
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{
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switch ((uint8_t)channel)
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{
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case 0U:
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base->EICHD0_WORD0 = EIM_EICHD0_WORD0_CHKBIT_MASK(mask);
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break;
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#ifdef EIM_EICHEN_EICH1EN_MASK
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case 1U:
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base->EICHD1_WORD0 = EIM_EICHD1_WORD0_CHKBIT_MASK(mask);
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break;
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#endif
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#ifdef EIM_EICHEN_EICH2EN_MASK
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case 2U:
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base->EICHD2_WORD0 = EIM_EICHD2_WORD0_CHKBIT_MASK(mask);
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break;
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#endif
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#ifdef EIM_EICHEN_EICH3EN_MASK
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case 3U:
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base->EICHD3_WORD0 = EIM_EICHD3_WORD0_CHKBIT_MASK(mask);
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break;
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#endif
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#ifdef EIM_EICHEN_EICH4EN_MASK
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case 4U:
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base->EICHD4_WORD0 = EIM_EICHD4_WORD0_CHKBIT_MASK(mask);
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break;
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#endif
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#ifdef EIM_EICHEN_EICH5EN_MASK
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case 5U:
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base->EICHD5_WORD0 = EIM_EICHD5_WORD0_CHKBIT_MASK(mask);
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break;
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#endif
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#ifdef EIM_EICHEN_EICH6EN_MASK
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case 6U:
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base->EICHD6_WORD0 = EIM_EICHD6_WORD0_CHKBIT_MASK(mask);
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break;
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#endif
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#ifdef EIM_EICHEN_EICH7EN_MASK
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case 7U:
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base->EICHD7_WORD0 = EIM_EICHD7_WORD0_CHKBIT_MASK(mask);
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break;
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#endif
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#ifdef EIM_EICHEN_EICH8EN_MASK
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case 8U:
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base->EICHD8_WORD0 = EIM_EICHD8_WORD0_CHKBIT_MASK(mask);
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break;
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#endif
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default:
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assert(NULL);
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break;
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}
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}
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uint8_t EIM_GetCheckBitMask(EIM_Type *base, eim_memory_channel_t channel)
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{
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uint8_t mask = 0x00U;
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switch ((uint8_t)channel)
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{
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case 0U:
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mask = (uint8_t)((base->EICHD0_WORD0 & EIM_EICHD0_WORD0_CHKBIT_MASK_MASK) >>
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EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT);
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break;
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#ifdef EIM_EICHEN_EICH1EN_MASK
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case 1U:
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mask = (uint8_t)((base->EICHD1_WORD0 & EIM_EICHD1_WORD0_CHKBIT_MASK_MASK) >>
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EIM_EICHD1_WORD0_CHKBIT_MASK_SHIFT);
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break;
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#endif
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#ifdef EIM_EICHEN_EICH2EN_MASK
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case 2U:
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mask = (uint8_t)((base->EICHD2_WORD0 & EIM_EICHD2_WORD0_CHKBIT_MASK_MASK) >>
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EIM_EICHD2_WORD0_CHKBIT_MASK_SHIFT);
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break;
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#endif
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#ifdef EIM_EICHEN_EICH3EN_MASK
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case 3U:
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mask = (uint8_t)((base->EICHD3_WORD0 & EIM_EICHD3_WORD0_CHKBIT_MASK_MASK) >>
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EIM_EICHD3_WORD0_CHKBIT_MASK_SHIFT);
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break;
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#endif
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#ifdef EIM_EICHEN_EICH4EN_MASK
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case 4U:
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mask = (uint8_t)((base->EICHD4_WORD0 & EIM_EICHD4_WORD0_CHKBIT_MASK_MASK) >>
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EIM_EICHD4_WORD0_CHKBIT_MASK_SHIFT);
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break;
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#endif
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#ifdef EIM_EICHEN_EICH5EN_MASK
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case 5U:
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mask = (uint8_t)((base->EICHD5_WORD0 & EIM_EICHD5_WORD0_CHKBIT_MASK_MASK) >>
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EIM_EICHD5_WORD0_CHKBIT_MASK_SHIFT);
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break;
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#endif
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#ifdef EIM_EICHEN_EICH6EN_MASK
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case 6U:
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mask = (uint8_t)((base->EICHD6_WORD0 & EIM_EICHD6_WORD0_CHKBIT_MASK_MASK) >>
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EIM_EICHD6_WORD0_CHKBIT_MASK_SHIFT);
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break;
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#endif
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#ifdef EIM_EICHEN_EICH7EN_MASK
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case 7U:
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mask = (uint8_t)((base->EICHD7_WORD0 & EIM_EICHD7_WORD0_CHKBIT_MASK_MASK) >>
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EIM_EICHD7_WORD0_CHKBIT_MASK_SHIFT);
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break;
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#endif
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#ifdef EIM_EICHEN_EICH8EN_MASK
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case 8U:
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mask = (uint8_t)((base->EICHD8_WORD0 & EIM_EICHD8_WORD0_CHKBIT_MASK_MASK) >>
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EIM_EICHD8_WORD0_CHKBIT_MASK_SHIFT);
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break;
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#endif
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default:
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assert(NULL);
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break;
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}
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return mask;
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}
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void EIM_InjectDataBitError(EIM_Type *base, eim_memory_channel_t channel, uint8_t mask)
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{
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switch ((uint8_t)channel)
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{
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case 0U:
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base->EICHD0_WORD1 = mask;
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break;
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#ifdef EIM_EICHEN_EICH1EN_MASK
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case 1U:
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base->EICHD1_WORD1 = mask;
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break;
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#endif
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#ifdef EIM_EICHEN_EICH2EN_MASK
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case 2U:
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base->EICHD2_WORD1 = mask;
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break;
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#endif
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#ifdef EIM_EICHEN_EICH3EN_MASK
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case kEIM_MemoryChannelRAMC:
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base->EICHD3_WORD1 = mask;
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break;
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#endif
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#ifdef EIM_EICHEN_EICH4EN_MASK
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case kEIM_MemoryChannelRAMD:
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base->EICHD4_WORD1 = mask;
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break;
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#endif
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#ifdef EIM_EICHEN_EICH5EN_MASK
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case kEIM_MemoryChannelRAME:
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base->EICHD5_WORD1 = mask;
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break;
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#endif
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#ifdef EIM_EICHEN_EICH6EN_MASK
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case kEIM_MemoryChannelRAMF:
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base->EICHD6_WORD1 = mask;
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break;
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#endif
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#ifdef EIM_EICHEN_EICH7EN_MASK
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case kEIM_MemoryChannelLPCACRAM:
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base->EICHD7_WORD1 = mask;
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break;
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#endif
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#ifdef EIM_EICHEN_EICH8EN_MASK
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case kEIM_MemoryChannelPKCRAM:
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base->EICHD8_WORD1 = mask;
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break;
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#endif
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default:
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assert(NULL);
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break;
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}
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}
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uint32_t EIM_GetDataBitMask(EIM_Type *base, eim_memory_channel_t channel)
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{
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uint32_t mask = 0x00U;
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switch ((uint8_t)channel)
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{
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case 0U:
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mask = (base->EICHD0_WORD0 & EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT;
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break;
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#ifdef EIM_EICHEN_EICH1EN_MASK
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case 1U:
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mask = (base->EICHD1_WORD0 & EIM_EICHD1_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT;
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break;
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#endif
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#ifdef EIM_EICHEN_EICH2EN_MASK
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case 2U:
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mask = (base->EICHD2_WORD0 & EIM_EICHD2_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD2_WORD1_B0_3DATA_MASK_SHIFT;
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break;
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#endif
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#ifdef EIM_EICHEN_EICH3EN_MASK
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case 3U:
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mask = (base->EICHD3_WORD0 & EIM_EICHD3_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD3_WORD1_B0_3DATA_MASK_SHIFT;
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break;
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#endif
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#ifdef EIM_EICHEN_EICH4EN_MASK
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case 4U:
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mask = (base->EICHD4_WORD0 & EIM_EICHD4_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD4_WORD1_B0_3DATA_MASK_SHIFT;
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break;
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#endif
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#ifdef EIM_EICHEN_EICH5EN_MASK
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case 5U:
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mask = (base->EICHD5_WORD0 & EIM_EICHD5_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD5_WORD1_B0_3DATA_MASK_SHIFT;
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break;
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#endif
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#ifdef EIM_EICHEN_EICH6EN_MASK
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case 6U:
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mask = (base->EICHD6_WORD0 & EIM_EICHD6_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD6_WORD1_B0_3DATA_MASK_SHIFT;
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break;
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#endif
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#ifdef EIM_EICHEN_EICH7EN_MASK
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case 7U:
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mask = (base->EICHD7_WORD0 & EIM_EICHD7_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD7_WORD1_B0_3DATA_MASK_SHIFT;
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break;
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#endif
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#ifdef EIM_EICHEN_EICH8EN_MASK
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case 8U:
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mask = (base->EICHD8_WORD1 & EIM_EICHD8_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD8_WORD1_B0_3DATA_MASK_SHIFT;
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break;
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#endif
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default:
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assert(NULL);
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break;
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}
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return mask;
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}
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