Update to SDK_2_12_1.
Signed-off-by: Yilin Sun <imi415@imi.moe>
This commit is contained in:
parent
d983b267f0
commit
ec9dcda9ee
File diff suppressed because it is too large
Load Diff
|
@ -1,5 +1,5 @@
|
|||
Release Name: MCUXpresso Software Development Kit (SDK)
|
||||
Release Version: 2.12.0
|
||||
Release Version: 2.12.1
|
||||
Package License: LA_OPT_NXP_Software_License.txt v35 May 2022- Additional Distribution License granted, license in Section 2.3 applies
|
||||
|
||||
SDK_Peripheral_Driver Name: SDK Peripheral Driver
|
||||
|
@ -499,3 +499,15 @@ freertos_corehttp name: FreeRTOS coreHTTP library
|
|||
Location: rtos/freertos/libraries/coreHTTP
|
||||
Origin: FreeRTOS -
|
||||
https://github.com/FreeRTOS/coreHTTP
|
||||
|
||||
soem Name: Simple Open EtherCAT Master Library (SOEM)
|
||||
Version: 1.4.0
|
||||
Outgoing License: GPL-2.0 with a special exception
|
||||
License File: middleware/soem/LICENSE
|
||||
Format: source code
|
||||
Description: An opensource EtherCAT master stack
|
||||
which is used to write custom EtherCAT Master
|
||||
applications.
|
||||
Location: middleware/soem
|
||||
Origin: RT-Labs
|
||||
Url: https://github.com/OpenEtherCATsociety/soem
|
||||
|
|
|
@ -0,0 +1,3 @@
|
|||
<#if memory.name=="BOARD_SDRAM">
|
||||
*(.bss*)
|
||||
</#if>
|
|
@ -0,0 +1,4 @@
|
|||
<#if memory.name=="SRAM_ITC">
|
||||
*mflash_drv.o(.text .text* .rodata .rodata*)
|
||||
*fsl_flexspi.o(.text .text* .rodata .rodata*)
|
||||
</#if>
|
|
@ -0,0 +1 @@
|
|||
*(EXCLUDE_FILE(*mflash_drv.o *fsl_flexspi.o) .text*)
|
|
@ -0,0 +1,3 @@
|
|||
<#if memory.name=="BOARD_SDRAM">
|
||||
*(.bss*)
|
||||
</#if>
|
|
@ -0,0 +1,4 @@
|
|||
<#if memory.name=="SRAM_ITC">
|
||||
*mflash_drv.o(.text .text* .rodata .rodata*)
|
||||
*fsl_flexspi.o(.text .text* .rodata .rodata*)
|
||||
</#if>
|
|
@ -0,0 +1 @@
|
|||
*(EXCLUDE_FILE(*mflash_drv.o *fsl_flexspi.o) .text*)
|
|
@ -0,0 +1,3 @@
|
|||
<#if memory.name=="BOARD_SDRAM">
|
||||
*(.bss*)
|
||||
</#if>
|
|
@ -0,0 +1,4 @@
|
|||
<#if memory.name=="SRAM_ITC">
|
||||
*mflash_drv.o(.text .text* .rodata .rodata*)
|
||||
*fsl_flexspi.o(.text .text* .rodata .rodata*)
|
||||
</#if>
|
|
@ -0,0 +1 @@
|
|||
*(EXCLUDE_FILE(*mflash_drv.o *fsl_flexspi.o) .text*)
|
|
@ -0,0 +1,3 @@
|
|||
<#if memory.name=="BOARD_SDRAM">
|
||||
*(.bss*)
|
||||
</#if>
|
|
@ -0,0 +1,4 @@
|
|||
<#if memory.name=="SRAM_ITC">
|
||||
*mflash_drv.o(.text .text* .rodata .rodata*)
|
||||
*fsl_flexspi.o(.text .text* .rodata .rodata*)
|
||||
</#if>
|
|
@ -0,0 +1 @@
|
|||
*(EXCLUDE_FILE(*mflash_drv.o *fsl_flexspi.o) .text*)
|
|
@ -0,0 +1,89 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<ksdk:examples xmlns:ksdk="http://nxp.com/ksdk/2.0/ksdk_manifest_v3.0.xsd" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://nxp.com/ksdk/2.0/ksdk_manifest_v3.0.xsd manifest.xsd">
|
||||
<externalDefinitions>
|
||||
<definition extID="middleware.azure_rtos.fx.lib.MIMXRT1021"/>
|
||||
<definition extID="platform.utilities.misc_utilities.MIMXRT1021"/>
|
||||
<definition extID="mcuxpresso"/>
|
||||
<definition extID="iar"/>
|
||||
<definition extID="mdk"/>
|
||||
<definition extID="com.nxp.mcuxpresso"/>
|
||||
<definition extID="armgcc"/>
|
||||
</externalDefinitions>
|
||||
<example id="evkmimxrt1020_filex_lib" name="filex_lib" dependency="middleware.azure_rtos.fx.lib.MIMXRT1021 platform.utilities.misc_utilities.MIMXRT1021" category="azure_rtos_libs">
|
||||
<projects>
|
||||
<project type="com.crt.advproject.projecttype.lib" nature="org.eclipse.cdt.core.cnature"/>
|
||||
</projects>
|
||||
<toolchainSettings>
|
||||
<toolchainSetting id_refs="com.nxp.mcuxpresso">
|
||||
<option id="com.crt.advproject.gcc.fpu" type="enum">
|
||||
<value>com.crt.advproject.gcc.fpu.fpv5dp.hard</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.optimization.flags" type="string">
|
||||
<value>-fno-common</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.c.misc.dialect" type="enum">
|
||||
<value>com.crt.advproject.misc.dialect.gnu99</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.gcc.exe.debug.option.debugging.level" type="enum">
|
||||
<value>gnu.c.debugging.level.none</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.misc.other" type="string">
|
||||
<value>-Wno-unused-but-set-variable -c -ffunction-sections -fdata-sections -ffreestanding -fno-builtin</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.warnings.nowarn" type="boolean">
|
||||
<value>false</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.warnings.allwarn" type="boolean">
|
||||
<value>false</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.warnings.extrawarn" type="boolean">
|
||||
<value>false</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.warnings.wconversion" type="boolean">
|
||||
<value>false</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.warnings.toerrors" type="boolean">
|
||||
<value>false</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.preprocessor.def.symbols" type="stringList">
|
||||
<value>CPU_MIMXRT1021DAG5A</value>
|
||||
<value>TX_INCLUDE_USER_DEFINE_FILE</value>
|
||||
<value>FX_INCLUDE_USER_DEFINE_FILE</value>
|
||||
<value>MCUXPRESSO_SDK</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.gas.fpu" type="enum">
|
||||
<value>com.crt.advproject.gas.fpu.fpv5dp.hard</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.cpp.fpu" type="enum">
|
||||
<value>com.crt.advproject.cpp.fpu.fpv5dp.hard</value>
|
||||
</option>
|
||||
<option id="gnu.cpp.compiler.option.optimization.flags" type="string">
|
||||
<value>-fno-common</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.cpp.misc.dialect" type="enum">
|
||||
<value>com.crt.advproject.misc.dialect.gnupp11</value>
|
||||
</option>
|
||||
</toolchainSetting>
|
||||
</toolchainSettings>
|
||||
<include_paths>
|
||||
<include_path path="." project_relative_path="azure-rtos/config" type="c_include"/>
|
||||
</include_paths>
|
||||
<source path="iar" project_relative_path="./" type="workspace" toolchain="iar">
|
||||
<files mask="filex_lib.ewp"/>
|
||||
<files mask="filex_lib.eww"/>
|
||||
</source>
|
||||
<source path="mdk" project_relative_path="./" type="workspace" toolchain="mdk">
|
||||
<files mask="filex_lib.uvprojx"/>
|
||||
<files mask="filex_lib.uvmpw"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="doc" type="doc" toolchain="iar mdk mcuxpresso armgcc">
|
||||
<files mask="readme.txt"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="azure-rtos/config" type="c_include">
|
||||
<files mask="tx_user.h"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="azure-rtos/config" type="c_include">
|
||||
<files mask="fx_user.h"/>
|
||||
</source>
|
||||
</example>
|
||||
</ksdk:examples>
|
|
@ -0,0 +1,54 @@
|
|||
/*
|
||||
* Copyright 2020 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef FX_USER_H
|
||||
#define FX_USER_H
|
||||
|
||||
//#define FX_MAX_LONG_NAME_LEN 256
|
||||
|
||||
//#define FX_MAX_LAST_NAME_LEN 256
|
||||
|
||||
//#define FX_MAX_SECTOR_CACHE 256
|
||||
|
||||
//#define FX_FAT_MAP_SIZE 128
|
||||
|
||||
//#define FX_MAX_FAT_CACHE 16
|
||||
|
||||
//#define FX_UPDATE_RATE_IN_SECONDS 10
|
||||
|
||||
//#define FX_UPDATE_RATE_IN_TICKS 1000
|
||||
|
||||
//#define FX_NO_TIMER
|
||||
|
||||
//#define FX_DONT_UPDATE_OPEN_FILES
|
||||
|
||||
//#define FX_MEDIA_DISABLE_SEARCH_CACHE
|
||||
|
||||
//#define FX_DISABLE_DIRECT_DATA_READ_CACHE_FILL
|
||||
|
||||
//#define FX_MEDIA_STATISTICS_DISABLE
|
||||
|
||||
//#define FX_SINGLE_OPEN_LEGACY
|
||||
|
||||
//#define FX_RENAME_PATH_INHERIT
|
||||
|
||||
//#define FX_NO_LOCAL_PATH
|
||||
|
||||
//#define FX_ENABLE_EXFAT
|
||||
|
||||
//#define FX_SINGLE_THREAD
|
||||
|
||||
//#define FX_FAULT_TOLERANT_DATA
|
||||
|
||||
//#define FX_FAULT_TOLERANT
|
||||
|
||||
//#define FX_DRIVER_USE_64BIT_LBA
|
||||
|
||||
//#define FX_ENABLE_FAULT_TOLERANT
|
||||
|
||||
//#define FX_FAULT_TOLERANT_BOOT_INDEX
|
||||
|
||||
#endif
|
|
@ -0,0 +1,5 @@
|
|||
Overview
|
||||
========
|
||||
This is a library project for Azure RTOS FileX, which can be used to generate a FileX library for application use.
|
||||
|
||||
This example cannot be imported into Config Tools because it doesn't contain files generated by config tool.
|
|
@ -0,0 +1,62 @@
|
|||
/*
|
||||
* Copyright 2020 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef TX_USER_H
|
||||
#define TX_USER_H
|
||||
|
||||
|
||||
#define TX_ENABLE_FPU_SUPPORT
|
||||
|
||||
//#define TX_MAX_PRIORITIES 32
|
||||
|
||||
//#define TX_MINIMUM_STACK
|
||||
|
||||
//#define TX_THREAD_USER_EXTENSION
|
||||
|
||||
//#define TX_TIMER_THREAD_STACK_SIZE
|
||||
|
||||
//#define TX_TIMER_THREAD_PRIORITY
|
||||
|
||||
//#define TX_TIMER_PROCESS_IN_ISR
|
||||
|
||||
//#define TX_REACTIVATE_INLINE
|
||||
|
||||
//#define TX_DISABLE_STACK_FILLING
|
||||
|
||||
//#define TX_ENABLE_STACK_CHECKING
|
||||
|
||||
//#define TX_DISABLE_PREEMPTION_THRESHOLD
|
||||
|
||||
//#define TX_DISABLE_REDUNDANT_CLEARING
|
||||
|
||||
//#define TX_NO_TIMER
|
||||
|
||||
//#define TX_DISABLE_NOTIFY_CALLBACKS
|
||||
|
||||
//#define TX_INLINE_THREAD_RESUME_SUSPEND
|
||||
|
||||
//#define TX_NOT_INTERRUPTABLE
|
||||
|
||||
//#define TX_ENABLE_EVENT_TRACE
|
||||
|
||||
//#define TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO
|
||||
|
||||
//#define TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO
|
||||
|
||||
//#define TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO
|
||||
|
||||
//#define TX_MUTEX_ENABLE_PERFORMANCE_INFO
|
||||
|
||||
//#define TX_QUEUE_ENABLE_PERFORMANCE_INFO
|
||||
|
||||
//#define TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO
|
||||
|
||||
//#define TX_THREAD_ENABLE_PERFORMANCE_INFO
|
||||
|
||||
//#define TX_TIMER_ENABLE_PERFORMANCE_INFO
|
||||
|
||||
//#define TX_TIMER_TICKS_PER_SECOND 100
|
||||
#endif
|
|
@ -0,0 +1,54 @@
|
|||
/*
|
||||
* Copyright 2020 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef FX_USER_H
|
||||
#define FX_USER_H
|
||||
|
||||
//#define FX_MAX_LONG_NAME_LEN 256
|
||||
|
||||
//#define FX_MAX_LAST_NAME_LEN 256
|
||||
|
||||
//#define FX_MAX_SECTOR_CACHE 256
|
||||
|
||||
//#define FX_FAT_MAP_SIZE 128
|
||||
|
||||
//#define FX_MAX_FAT_CACHE 16
|
||||
|
||||
//#define FX_UPDATE_RATE_IN_SECONDS 10
|
||||
|
||||
//#define FX_UPDATE_RATE_IN_TICKS 1000
|
||||
|
||||
//#define FX_NO_TIMER
|
||||
|
||||
//#define FX_DONT_UPDATE_OPEN_FILES
|
||||
|
||||
//#define FX_MEDIA_DISABLE_SEARCH_CACHE
|
||||
|
||||
//#define FX_DISABLE_DIRECT_DATA_READ_CACHE_FILL
|
||||
|
||||
//#define FX_MEDIA_STATISTICS_DISABLE
|
||||
|
||||
//#define FX_SINGLE_OPEN_LEGACY
|
||||
|
||||
//#define FX_RENAME_PATH_INHERIT
|
||||
|
||||
//#define FX_NO_LOCAL_PATH
|
||||
|
||||
//#define FX_ENABLE_EXFAT
|
||||
|
||||
//#define FX_SINGLE_THREAD
|
||||
|
||||
//#define FX_FAULT_TOLERANT_DATA
|
||||
|
||||
//#define FX_FAULT_TOLERANT
|
||||
|
||||
//#define FX_DRIVER_USE_64BIT_LBA
|
||||
|
||||
//#define FX_ENABLE_FAULT_TOLERANT
|
||||
|
||||
//#define FX_FAULT_TOLERANT_BOOT_INDEX
|
||||
|
||||
#endif
|
|
@ -0,0 +1,93 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<ksdk:examples xmlns:ksdk="http://nxp.com/ksdk/2.0/ksdk_manifest_v3.0.xsd" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://nxp.com/ksdk/2.0/ksdk_manifest_v3.0.xsd manifest.xsd">
|
||||
<externalDefinitions>
|
||||
<definition extID="middleware.azure_rtos.nxd.lib.MIMXRT1021"/>
|
||||
<definition extID="platform.utilities.misc_utilities.MIMXRT1021"/>
|
||||
<definition extID="mcuxpresso"/>
|
||||
<definition extID="iar"/>
|
||||
<definition extID="mdk"/>
|
||||
<definition extID="com.nxp.mcuxpresso"/>
|
||||
<definition extID="armgcc"/>
|
||||
</externalDefinitions>
|
||||
<example id="evkmimxrt1020_netxduo_lib" name="netxduo_lib" dependency="middleware.azure_rtos.nxd.lib.MIMXRT1021 platform.utilities.misc_utilities.MIMXRT1021" category="azure_rtos_libs">
|
||||
<projects>
|
||||
<project type="com.crt.advproject.projecttype.lib" nature="org.eclipse.cdt.core.cnature"/>
|
||||
</projects>
|
||||
<toolchainSettings>
|
||||
<toolchainSetting id_refs="com.nxp.mcuxpresso">
|
||||
<option id="com.crt.advproject.gcc.fpu" type="enum">
|
||||
<value>com.crt.advproject.gcc.fpu.fpv5dp.hard</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.optimization.flags" type="string">
|
||||
<value>-fno-common</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.c.misc.dialect" type="enum">
|
||||
<value>com.crt.advproject.misc.dialect.gnu99</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.gcc.exe.debug.option.debugging.level" type="enum">
|
||||
<value>gnu.c.debugging.level.none</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.misc.other" type="string">
|
||||
<value>-Wno-unused-but-set-variable -c -ffunction-sections -fdata-sections -ffreestanding -fno-builtin</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.warnings.nowarn" type="boolean">
|
||||
<value>false</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.warnings.allwarn" type="boolean">
|
||||
<value>false</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.warnings.extrawarn" type="boolean">
|
||||
<value>false</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.warnings.wconversion" type="boolean">
|
||||
<value>false</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.warnings.toerrors" type="boolean">
|
||||
<value>false</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.preprocessor.def.symbols" type="stringList">
|
||||
<value>CPU_MIMXRT1021DAG5A</value>
|
||||
<value>TX_INCLUDE_USER_DEFINE_FILE</value>
|
||||
<value>FX_INCLUDE_USER_DEFINE_FILE</value>
|
||||
<value>NX_INCLUDE_USER_DEFINE_FILE</value>
|
||||
<value>MCUXPRESSO_SDK</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.gas.fpu" type="enum">
|
||||
<value>com.crt.advproject.gas.fpu.fpv5dp.hard</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.cpp.fpu" type="enum">
|
||||
<value>com.crt.advproject.cpp.fpu.fpv5dp.hard</value>
|
||||
</option>
|
||||
<option id="gnu.cpp.compiler.option.optimization.flags" type="string">
|
||||
<value>-fno-common</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.cpp.misc.dialect" type="enum">
|
||||
<value>com.crt.advproject.misc.dialect.gnupp11</value>
|
||||
</option>
|
||||
</toolchainSetting>
|
||||
</toolchainSettings>
|
||||
<include_paths>
|
||||
<include_path path="." project_relative_path="azure-rtos/config" type="c_include"/>
|
||||
</include_paths>
|
||||
<source path="iar" project_relative_path="./" type="workspace" toolchain="iar">
|
||||
<files mask="netxduo_lib.ewp"/>
|
||||
<files mask="netxduo_lib.eww"/>
|
||||
</source>
|
||||
<source path="mdk" project_relative_path="./" type="workspace" toolchain="mdk">
|
||||
<files mask="netxduo_lib.uvprojx"/>
|
||||
<files mask="netxduo_lib.uvmpw"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="doc" type="doc" toolchain="iar mdk mcuxpresso armgcc">
|
||||
<files mask="readme.txt"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="azure-rtos/config" type="c_include">
|
||||
<files mask="tx_user.h"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="azure-rtos/config" type="c_include">
|
||||
<files mask="fx_user.h"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="azure-rtos/config" type="c_include">
|
||||
<files mask="nx_user.h"/>
|
||||
</source>
|
||||
</example>
|
||||
</ksdk:examples>
|
|
@ -0,0 +1,62 @@
|
|||
/*
|
||||
* Copyright 2020,2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef NX_USER_H
|
||||
#define NX_USER_H
|
||||
|
||||
/* Refer to nx_user_sample.h for more information. */
|
||||
|
||||
/* The driver enables the checksum offload feature. Therefore
|
||||
* the following symbols must be defined.
|
||||
*/
|
||||
|
||||
#define NX_PACKET_ALIGNMENT 32
|
||||
|
||||
#define NX_DISABLE_ICMPV4_RX_CHECKSUM
|
||||
#define NX_DISABLE_ICMPV4_TX_CHECKSUM
|
||||
#define NX_DISABLE_IP_RX_CHECKSUM
|
||||
#define NX_DISABLE_IP_TX_CHECKSUM
|
||||
#define NX_DISABLE_TCP_RX_CHECKSUM
|
||||
#define NX_DISABLE_TCP_TX_CHECKSUM
|
||||
#define NX_DISABLE_UDP_RX_CHECKSUM
|
||||
#define NX_DISABLE_UDP_TX_CHECKSUM
|
||||
|
||||
#define NX_DISABLE_ERROR_CHECKING
|
||||
#define NX_TCP_ACK_EVERY_N_PACKETS 2
|
||||
#define NX_DISABLE_RX_SIZE_CHECKING
|
||||
#define NX_DISABLE_ARP_INFO
|
||||
#define NX_DISABLE_IP_INFO
|
||||
//#define NX_DISABLE_ICMP_INFO
|
||||
#define NX_DISABLE_IGMPV2
|
||||
#define NX_DISABLE_IGMP_INFO
|
||||
#define NX_DISABLE_PACKET_INFO
|
||||
#define NX_DISABLE_RARP_INFO
|
||||
#define NX_DISABLE_TCP_INFO
|
||||
#define NX_DISABLE_UDP_INFO
|
||||
#define NX_DISABLE_EXTENDED_NOTIFY_SUPPORT
|
||||
#define NX_DISABLE_INCLUDE_SOURCE_CODE
|
||||
|
||||
/* config for DNS */
|
||||
#define NX_DNS_CLIENT_USER_CREATE_PACKET_POOL
|
||||
#define NX_DNS_CLIENT_CLEAR_QUEUE
|
||||
|
||||
/* config for MQTT */
|
||||
#define NXD_MQTT_REQUIRE_TLS
|
||||
|
||||
/* NXD for MQTT non-blocking. */
|
||||
#define NX_ENABLE_EXTENDED_NOTIFY_SUPPORT
|
||||
|
||||
/* MQTT */
|
||||
#define NXD_MQTT_CLOUD_ENABLE
|
||||
#define NXD_MQTT_PING_TIMEOUT_DELAY 500
|
||||
#define NXD_MQTT_SOCKET_TIMEOUT 0
|
||||
|
||||
/* Secure */
|
||||
#define NX_SECURE_ENABLE
|
||||
#define NX_SECURE_TLS_DISABLE_TLS_1_1
|
||||
#define NX_ENABLE_IP_PACKET_FILTER
|
||||
|
||||
#endif /* NX_USER_H */
|
|
@ -0,0 +1,5 @@
|
|||
Overview
|
||||
========
|
||||
This is a library project for Azure RTOS NetX Duo, which can be used to generate a NetX Duo library for application use.
|
||||
|
||||
This example cannot be imported into Config Tools because it doesn't contain files generated by config tool.
|
|
@ -0,0 +1,62 @@
|
|||
/*
|
||||
* Copyright 2020 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef TX_USER_H
|
||||
#define TX_USER_H
|
||||
|
||||
|
||||
#define TX_ENABLE_FPU_SUPPORT
|
||||
|
||||
//#define TX_MAX_PRIORITIES 32
|
||||
|
||||
//#define TX_MINIMUM_STACK
|
||||
|
||||
//#define TX_THREAD_USER_EXTENSION
|
||||
|
||||
//#define TX_TIMER_THREAD_STACK_SIZE
|
||||
|
||||
//#define TX_TIMER_THREAD_PRIORITY
|
||||
|
||||
//#define TX_TIMER_PROCESS_IN_ISR
|
||||
|
||||
//#define TX_REACTIVATE_INLINE
|
||||
|
||||
//#define TX_DISABLE_STACK_FILLING
|
||||
|
||||
//#define TX_ENABLE_STACK_CHECKING
|
||||
|
||||
//#define TX_DISABLE_PREEMPTION_THRESHOLD
|
||||
|
||||
//#define TX_DISABLE_REDUNDANT_CLEARING
|
||||
|
||||
//#define TX_NO_TIMER
|
||||
|
||||
//#define TX_DISABLE_NOTIFY_CALLBACKS
|
||||
|
||||
//#define TX_INLINE_THREAD_RESUME_SUSPEND
|
||||
|
||||
//#define TX_NOT_INTERRUPTABLE
|
||||
|
||||
//#define TX_ENABLE_EVENT_TRACE
|
||||
|
||||
//#define TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO
|
||||
|
||||
//#define TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO
|
||||
|
||||
//#define TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO
|
||||
|
||||
//#define TX_MUTEX_ENABLE_PERFORMANCE_INFO
|
||||
|
||||
//#define TX_QUEUE_ENABLE_PERFORMANCE_INFO
|
||||
|
||||
//#define TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO
|
||||
|
||||
//#define TX_THREAD_ENABLE_PERFORMANCE_INFO
|
||||
|
||||
//#define TX_TIMER_ENABLE_PERFORMANCE_INFO
|
||||
|
||||
//#define TX_TIMER_TICKS_PER_SECOND 100
|
||||
#endif
|
|
@ -0,0 +1,5 @@
|
|||
Overview
|
||||
========
|
||||
This is a library project for Azure RTOS ThreadX, which can be used to generate a ThreadX library for application use.
|
||||
|
||||
This example cannot be imported into Config Tools because it doesn't contain files generated by config tool.
|
|
@ -0,0 +1,85 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<ksdk:examples xmlns:ksdk="http://nxp.com/ksdk/2.0/ksdk_manifest_v3.0.xsd" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://nxp.com/ksdk/2.0/ksdk_manifest_v3.0.xsd manifest.xsd">
|
||||
<externalDefinitions>
|
||||
<definition extID="middleware.azure_rtos.tx.lib.MIMXRT1021"/>
|
||||
<definition extID="platform.utilities.misc_utilities.MIMXRT1021"/>
|
||||
<definition extID="mcuxpresso"/>
|
||||
<definition extID="iar"/>
|
||||
<definition extID="mdk"/>
|
||||
<definition extID="com.nxp.mcuxpresso"/>
|
||||
<definition extID="armgcc"/>
|
||||
</externalDefinitions>
|
||||
<example id="evkmimxrt1020_threadx_lib" name="threadx_lib" dependency="middleware.azure_rtos.tx.lib.MIMXRT1021 platform.utilities.misc_utilities.MIMXRT1021" category="azure_rtos_libs">
|
||||
<projects>
|
||||
<project type="com.crt.advproject.projecttype.lib" nature="org.eclipse.cdt.core.cnature"/>
|
||||
</projects>
|
||||
<toolchainSettings>
|
||||
<toolchainSetting id_refs="com.nxp.mcuxpresso">
|
||||
<option id="com.crt.advproject.gcc.fpu" type="enum">
|
||||
<value>com.crt.advproject.gcc.fpu.fpv5dp.hard</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.optimization.flags" type="string">
|
||||
<value>-fno-common</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.c.misc.dialect" type="enum">
|
||||
<value>com.crt.advproject.misc.dialect.gnu99</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.gcc.exe.debug.option.debugging.level" type="enum">
|
||||
<value>gnu.c.debugging.level.none</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.misc.other" type="string">
|
||||
<value>-Wno-unused-but-set-variable -c -ffunction-sections -fdata-sections -ffreestanding -fno-builtin</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.warnings.nowarn" type="boolean">
|
||||
<value>false</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.warnings.allwarn" type="boolean">
|
||||
<value>false</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.warnings.extrawarn" type="boolean">
|
||||
<value>false</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.warnings.wconversion" type="boolean">
|
||||
<value>false</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.warnings.toerrors" type="boolean">
|
||||
<value>false</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.preprocessor.def.symbols" type="stringList">
|
||||
<value>CPU_MIMXRT1021DAG5A</value>
|
||||
<value>TX_INCLUDE_USER_DEFINE_FILE</value>
|
||||
<value>MCUXPRESSO_SDK</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.gas.fpu" type="enum">
|
||||
<value>com.crt.advproject.gas.fpu.fpv5dp.hard</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.cpp.fpu" type="enum">
|
||||
<value>com.crt.advproject.cpp.fpu.fpv5dp.hard</value>
|
||||
</option>
|
||||
<option id="gnu.cpp.compiler.option.optimization.flags" type="string">
|
||||
<value>-fno-common</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.cpp.misc.dialect" type="enum">
|
||||
<value>com.crt.advproject.misc.dialect.gnupp11</value>
|
||||
</option>
|
||||
</toolchainSetting>
|
||||
</toolchainSettings>
|
||||
<include_paths>
|
||||
<include_path path="." project_relative_path="azure-rtos/config" type="c_include"/>
|
||||
</include_paths>
|
||||
<source path="iar" project_relative_path="./" type="workspace" toolchain="iar">
|
||||
<files mask="threadx_lib.ewp"/>
|
||||
<files mask="threadx_lib.eww"/>
|
||||
</source>
|
||||
<source path="mdk" project_relative_path="./" type="workspace" toolchain="mdk">
|
||||
<files mask="threadx_lib.uvprojx"/>
|
||||
<files mask="threadx_lib.uvmpw"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="doc" type="doc" toolchain="iar mdk mcuxpresso armgcc">
|
||||
<files mask="readme.txt"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="azure-rtos/config" type="c_include">
|
||||
<files mask="tx_user.h"/>
|
||||
</source>
|
||||
</example>
|
||||
</ksdk:examples>
|
|
@ -0,0 +1,62 @@
|
|||
/*
|
||||
* Copyright 2020 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef TX_USER_H
|
||||
#define TX_USER_H
|
||||
|
||||
|
||||
#define TX_ENABLE_FPU_SUPPORT
|
||||
|
||||
//#define TX_MAX_PRIORITIES 32
|
||||
|
||||
//#define TX_MINIMUM_STACK
|
||||
|
||||
//#define TX_THREAD_USER_EXTENSION
|
||||
|
||||
//#define TX_TIMER_THREAD_STACK_SIZE
|
||||
|
||||
//#define TX_TIMER_THREAD_PRIORITY
|
||||
|
||||
//#define TX_TIMER_PROCESS_IN_ISR
|
||||
|
||||
//#define TX_REACTIVATE_INLINE
|
||||
|
||||
//#define TX_DISABLE_STACK_FILLING
|
||||
|
||||
//#define TX_ENABLE_STACK_CHECKING
|
||||
|
||||
//#define TX_DISABLE_PREEMPTION_THRESHOLD
|
||||
|
||||
//#define TX_DISABLE_REDUNDANT_CLEARING
|
||||
|
||||
//#define TX_NO_TIMER
|
||||
|
||||
//#define TX_DISABLE_NOTIFY_CALLBACKS
|
||||
|
||||
//#define TX_INLINE_THREAD_RESUME_SUSPEND
|
||||
|
||||
//#define TX_NOT_INTERRUPTABLE
|
||||
|
||||
//#define TX_ENABLE_EVENT_TRACE
|
||||
|
||||
//#define TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO
|
||||
|
||||
//#define TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO
|
||||
|
||||
//#define TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO
|
||||
|
||||
//#define TX_MUTEX_ENABLE_PERFORMANCE_INFO
|
||||
|
||||
//#define TX_QUEUE_ENABLE_PERFORMANCE_INFO
|
||||
|
||||
//#define TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO
|
||||
|
||||
//#define TX_THREAD_ENABLE_PERFORMANCE_INFO
|
||||
|
||||
//#define TX_TIMER_ENABLE_PERFORMANCE_INFO
|
||||
|
||||
//#define TX_TIMER_TICKS_PER_SECOND 100
|
||||
#endif
|
|
@ -0,0 +1,54 @@
|
|||
/*
|
||||
* Copyright 2020 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef FX_USER_H
|
||||
#define FX_USER_H
|
||||
|
||||
//#define FX_MAX_LONG_NAME_LEN 256
|
||||
|
||||
//#define FX_MAX_LAST_NAME_LEN 256
|
||||
|
||||
//#define FX_MAX_SECTOR_CACHE 256
|
||||
|
||||
//#define FX_FAT_MAP_SIZE 128
|
||||
|
||||
//#define FX_MAX_FAT_CACHE 16
|
||||
|
||||
//#define FX_UPDATE_RATE_IN_SECONDS 10
|
||||
|
||||
//#define FX_UPDATE_RATE_IN_TICKS 1000
|
||||
|
||||
//#define FX_NO_TIMER
|
||||
|
||||
//#define FX_DONT_UPDATE_OPEN_FILES
|
||||
|
||||
//#define FX_MEDIA_DISABLE_SEARCH_CACHE
|
||||
|
||||
//#define FX_DISABLE_DIRECT_DATA_READ_CACHE_FILL
|
||||
|
||||
//#define FX_MEDIA_STATISTICS_DISABLE
|
||||
|
||||
//#define FX_SINGLE_OPEN_LEGACY
|
||||
|
||||
//#define FX_RENAME_PATH_INHERIT
|
||||
|
||||
//#define FX_NO_LOCAL_PATH
|
||||
|
||||
//#define FX_ENABLE_EXFAT
|
||||
|
||||
//#define FX_SINGLE_THREAD
|
||||
|
||||
//#define FX_FAULT_TOLERANT_DATA
|
||||
|
||||
//#define FX_FAULT_TOLERANT
|
||||
|
||||
//#define FX_DRIVER_USE_64BIT_LBA
|
||||
|
||||
//#define FX_ENABLE_FAULT_TOLERANT
|
||||
|
||||
//#define FX_FAULT_TOLERANT_BOOT_INDEX
|
||||
|
||||
#endif
|
|
@ -0,0 +1,62 @@
|
|||
/*
|
||||
* Copyright 2020,2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef NX_USER_H
|
||||
#define NX_USER_H
|
||||
|
||||
/* Refer to nx_user_sample.h for more information. */
|
||||
|
||||
/* The driver enables the checksum offload feature. Therefore
|
||||
* the following symbols must be defined.
|
||||
*/
|
||||
|
||||
#define NX_PACKET_ALIGNMENT 32
|
||||
|
||||
#define NX_DISABLE_ICMPV4_RX_CHECKSUM
|
||||
#define NX_DISABLE_ICMPV4_TX_CHECKSUM
|
||||
#define NX_DISABLE_IP_RX_CHECKSUM
|
||||
#define NX_DISABLE_IP_TX_CHECKSUM
|
||||
#define NX_DISABLE_TCP_RX_CHECKSUM
|
||||
#define NX_DISABLE_TCP_TX_CHECKSUM
|
||||
#define NX_DISABLE_UDP_RX_CHECKSUM
|
||||
#define NX_DISABLE_UDP_TX_CHECKSUM
|
||||
|
||||
#define NX_DISABLE_ERROR_CHECKING
|
||||
#define NX_TCP_ACK_EVERY_N_PACKETS 2
|
||||
#define NX_DISABLE_RX_SIZE_CHECKING
|
||||
#define NX_DISABLE_ARP_INFO
|
||||
#define NX_DISABLE_IP_INFO
|
||||
//#define NX_DISABLE_ICMP_INFO
|
||||
#define NX_DISABLE_IGMPV2
|
||||
#define NX_DISABLE_IGMP_INFO
|
||||
#define NX_DISABLE_PACKET_INFO
|
||||
#define NX_DISABLE_RARP_INFO
|
||||
#define NX_DISABLE_TCP_INFO
|
||||
#define NX_DISABLE_UDP_INFO
|
||||
#define NX_DISABLE_EXTENDED_NOTIFY_SUPPORT
|
||||
#define NX_DISABLE_INCLUDE_SOURCE_CODE
|
||||
|
||||
/* config for DNS */
|
||||
#define NX_DNS_CLIENT_USER_CREATE_PACKET_POOL
|
||||
#define NX_DNS_CLIENT_CLEAR_QUEUE
|
||||
|
||||
/* config for MQTT */
|
||||
#define NXD_MQTT_REQUIRE_TLS
|
||||
|
||||
/* NXD for MQTT non-blocking. */
|
||||
#define NX_ENABLE_EXTENDED_NOTIFY_SUPPORT
|
||||
|
||||
/* MQTT */
|
||||
#define NXD_MQTT_CLOUD_ENABLE
|
||||
#define NXD_MQTT_PING_TIMEOUT_DELAY 500
|
||||
#define NXD_MQTT_SOCKET_TIMEOUT 0
|
||||
|
||||
/* Secure */
|
||||
#define NX_SECURE_ENABLE
|
||||
#define NX_SECURE_TLS_DISABLE_TLS_1_1
|
||||
#define NX_ENABLE_IP_PACKET_FILTER
|
||||
|
||||
#endif /* NX_USER_H */
|
|
@ -0,0 +1,5 @@
|
|||
Overview
|
||||
========
|
||||
This is a library project for Azure RTOS USBX, which can be used to generate a USBX ThreadX library for application use.
|
||||
|
||||
This example cannot be imported into Config Tools because it doesn't contain files generated by config tool.
|
|
@ -0,0 +1,62 @@
|
|||
/*
|
||||
* Copyright 2020 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef TX_USER_H
|
||||
#define TX_USER_H
|
||||
|
||||
|
||||
#define TX_ENABLE_FPU_SUPPORT
|
||||
|
||||
//#define TX_MAX_PRIORITIES 32
|
||||
|
||||
//#define TX_MINIMUM_STACK
|
||||
|
||||
//#define TX_THREAD_USER_EXTENSION
|
||||
|
||||
//#define TX_TIMER_THREAD_STACK_SIZE
|
||||
|
||||
//#define TX_TIMER_THREAD_PRIORITY
|
||||
|
||||
//#define TX_TIMER_PROCESS_IN_ISR
|
||||
|
||||
//#define TX_REACTIVATE_INLINE
|
||||
|
||||
//#define TX_DISABLE_STACK_FILLING
|
||||
|
||||
//#define TX_ENABLE_STACK_CHECKING
|
||||
|
||||
//#define TX_DISABLE_PREEMPTION_THRESHOLD
|
||||
|
||||
//#define TX_DISABLE_REDUNDANT_CLEARING
|
||||
|
||||
//#define TX_NO_TIMER
|
||||
|
||||
//#define TX_DISABLE_NOTIFY_CALLBACKS
|
||||
|
||||
//#define TX_INLINE_THREAD_RESUME_SUSPEND
|
||||
|
||||
//#define TX_NOT_INTERRUPTABLE
|
||||
|
||||
//#define TX_ENABLE_EVENT_TRACE
|
||||
|
||||
//#define TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO
|
||||
|
||||
//#define TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO
|
||||
|
||||
//#define TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO
|
||||
|
||||
//#define TX_MUTEX_ENABLE_PERFORMANCE_INFO
|
||||
|
||||
//#define TX_QUEUE_ENABLE_PERFORMANCE_INFO
|
||||
|
||||
//#define TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO
|
||||
|
||||
//#define TX_THREAD_ENABLE_PERFORMANCE_INFO
|
||||
|
||||
//#define TX_TIMER_ENABLE_PERFORMANCE_INFO
|
||||
|
||||
//#define TX_TIMER_TICKS_PER_SECOND 100
|
||||
#endif
|
|
@ -0,0 +1,99 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<ksdk:examples xmlns:ksdk="http://nxp.com/ksdk/2.0/ksdk_manifest_v3.0.xsd" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://nxp.com/ksdk/2.0/ksdk_manifest_v3.0.xsd manifest.xsd">
|
||||
<externalDefinitions>
|
||||
<definition extID="middleware.azure_rtos.ux.lib.MIMXRT1021"/>
|
||||
<definition extID="platform.utilities.misc_utilities.MIMXRT1021"/>
|
||||
<definition extID="mcuxpresso"/>
|
||||
<definition extID="iar"/>
|
||||
<definition extID="mdk"/>
|
||||
<definition extID="com.nxp.mcuxpresso"/>
|
||||
<definition extID="armgcc"/>
|
||||
</externalDefinitions>
|
||||
<example id="evkmimxrt1020_usbx_lib" name="usbx_lib" dependency="middleware.azure_rtos.ux.lib.MIMXRT1021 platform.utilities.misc_utilities.MIMXRT1021" category="azure_rtos_libs">
|
||||
<projects>
|
||||
<project type="com.crt.advproject.projecttype.lib" nature="org.eclipse.cdt.core.cnature"/>
|
||||
</projects>
|
||||
<toolchainSettings>
|
||||
<toolchainSetting id_refs="com.nxp.mcuxpresso">
|
||||
<option id="com.crt.advproject.gcc.fpu" type="enum">
|
||||
<value>com.crt.advproject.gcc.fpu.fpv5dp.hard</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.optimization.flags" type="string">
|
||||
<value>-fno-common</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.c.misc.dialect" type="enum">
|
||||
<value>com.crt.advproject.misc.dialect.gnu99</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.gcc.exe.debug.option.debugging.level" type="enum">
|
||||
<value>gnu.c.debugging.level.none</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.misc.other" type="string">
|
||||
<value>-Wno-unused-but-set-variable -c -ffunction-sections -fdata-sections -ffreestanding -fno-builtin</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.warnings.nowarn" type="boolean">
|
||||
<value>false</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.warnings.allwarn" type="boolean">
|
||||
<value>false</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.warnings.extrawarn" type="boolean">
|
||||
<value>false</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.warnings.wconversion" type="boolean">
|
||||
<value>false</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.warnings.toerrors" type="boolean">
|
||||
<value>false</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.preprocessor.def.symbols" type="stringList">
|
||||
<value>CPU_MIMXRT1021DAG5A</value>
|
||||
<value>MIMXRT</value>
|
||||
<value>UX_OTG_SUPPORT</value>
|
||||
<value>TX_INCLUDE_USER_DEFINE_FILE</value>
|
||||
<value>FX_INCLUDE_USER_DEFINE_FILE</value>
|
||||
<value>NX_INCLUDE_USER_DEFINE_FILE</value>
|
||||
<value>UX_INCLUDE_USER_DEFINE_FILE</value>
|
||||
<value>MCUXPRESSO_SDK</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.gas.fpu" type="enum">
|
||||
<value>com.crt.advproject.gas.fpu.fpv5dp.hard</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.cpp.fpu" type="enum">
|
||||
<value>com.crt.advproject.cpp.fpu.fpv5dp.hard</value>
|
||||
</option>
|
||||
<option id="gnu.cpp.compiler.option.optimization.flags" type="string">
|
||||
<value>-fno-common</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.cpp.misc.dialect" type="enum">
|
||||
<value>com.crt.advproject.misc.dialect.gnupp11</value>
|
||||
</option>
|
||||
</toolchainSetting>
|
||||
</toolchainSettings>
|
||||
<include_paths>
|
||||
<include_path path="." project_relative_path="azure-rtos/config" type="c_include"/>
|
||||
</include_paths>
|
||||
<source path="iar" project_relative_path="./" type="workspace" toolchain="iar">
|
||||
<files mask="usbx_lib.ewp"/>
|
||||
<files mask="usbx_lib.eww"/>
|
||||
</source>
|
||||
<source path="mdk" project_relative_path="./" type="workspace" toolchain="mdk">
|
||||
<files mask="usbx_lib.uvprojx"/>
|
||||
<files mask="usbx_lib.uvmpw"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="doc" type="doc" toolchain="iar mdk mcuxpresso armgcc">
|
||||
<files mask="readme.txt"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="azure-rtos/config" type="c_include">
|
||||
<files mask="tx_user.h"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="azure-rtos/config" type="c_include">
|
||||
<files mask="fx_user.h"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="azure-rtos/config" type="c_include">
|
||||
<files mask="nx_user.h"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="azure-rtos/config" type="c_include">
|
||||
<files mask="ux_user.h"/>
|
||||
</source>
|
||||
</example>
|
||||
</ksdk:examples>
|
|
@ -0,0 +1,109 @@
|
|||
/*
|
||||
* Copyright 2020 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef UX_USER_H
|
||||
#define UX_USER_H
|
||||
|
||||
#define UX_PERIODIC_RATE (TX_TIMER_TICKS_PER_SECOND)
|
||||
|
||||
#define UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH 512
|
||||
#define UX_SLAVE_REQUEST_DATA_MAX_LENGTH (1024 * 2)
|
||||
#define UX_HOST_CLASS_STORAGE_MEMORY_BUFFER_SIZE (1024 * 8)
|
||||
|
||||
/*
|
||||
* Defined, this value represents the maximum number of devices that can be attached to the USB.
|
||||
* Normally, the theoretical maximum number on a single USB is 127 devices. This value can be
|
||||
* scaled down to conserve memory. Note that this value represents the total number of devices
|
||||
* regardless of the number of USB buses in the system.
|
||||
*/
|
||||
/* #define UX_MAX_DEVICES 127 */
|
||||
|
||||
/*
|
||||
* Defined, this value represents the maximum number of Ed,
|
||||
* regular TDs and Isochronous TDs. These values depend on
|
||||
* the type of host controller and can be reduced in memory
|
||||
* constraint environments.
|
||||
*/
|
||||
#define UX_MAX_ED 80
|
||||
#define UX_MAX_TD 64
|
||||
#define UX_MAX_ISO_TD 1
|
||||
|
||||
/*
|
||||
* Defined, this value represents the maximum size of
|
||||
* the HID decompressed buffer. This cannot be determined
|
||||
* in advance so we allocate a big block, usually 4K
|
||||
* but for simple HID devices like keyboard and mouse
|
||||
* it can be reduced a lot.
|
||||
*/
|
||||
#define UX_HOST_CLASS_HID_DECOMPRESSION_BUFFER 4096
|
||||
|
||||
/*
|
||||
* Defined, this value represents the maximum number of HID usages
|
||||
* for a HID device. Default is 2048 but for simple HID devices
|
||||
* like keyboard and mouse it can be reduced a lot.
|
||||
*/
|
||||
#define UX_HOST_CLASS_HID_USAGES 2048
|
||||
|
||||
/*
|
||||
* Defined, this value represents the maximum number of media for
|
||||
* the host storage class. Default is 8 but for memory contrained
|
||||
* resource systems this can ne reduced to 1.
|
||||
*/
|
||||
#define UX_HOST_CLASS_STORAGE_MAX_MEDIA 2
|
||||
|
||||
/*
|
||||
* Defined, this value represents the number of packets in the
|
||||
* CDC_ECM device class.
|
||||
* The default is 16.
|
||||
*/
|
||||
#define UX_DEVICE_CLASS_CDC_ECM_NX_PKPOOL_ENTRIES 32
|
||||
|
||||
/* Defined, this enables CDC ECM class to use the packet pool from NetX instance. */
|
||||
#define UX_HOST_CLASS_CDC_ECM_USE_PACKET_POOL_FROM_NETX
|
||||
|
||||
/* Defined, this value will only enable the host side of usbx. */
|
||||
/* #define UX_HOST_SIDE_ONLY */
|
||||
|
||||
/* Defined, this value will only enable the device side of usbx. */
|
||||
/* #define UX_DEVICE_SIDE_ONLY */
|
||||
|
||||
/* defined, this macro enables device audio feedback endpoint support. */
|
||||
#define UX_DEVICE_CLASS_AUDIO_FEEDBACK_SUPPORT
|
||||
|
||||
/* Defined, device HID interrupt OUT transfer is supported. */
|
||||
/* #define UX_DEVICE_CLASS_HID_INTERRUPT_OUT_SUPPORT */
|
||||
|
||||
/* Defined, this macro enables device bi-directional-endpoint support. */
|
||||
#define UX_DEVICE_BIDIRECTIONAL_ENDPOINT_SUPPORT
|
||||
|
||||
/*
|
||||
* Defined, this value will include the OTG polling thread.
|
||||
* OTG can only be active if both host/device are present.
|
||||
*/
|
||||
#ifndef UX_HOST_SIDE_ONLY
|
||||
#ifndef UX_DEVICE_SIDE_ONLY
|
||||
/* #define UX_OTG_SUPPORT */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Defined, this value represents the maximum size of single
|
||||
* tansfers for the SCSI data phase.
|
||||
*/
|
||||
#define UX_HOST_CLASS_STORAGE_MAX_TRANSFER_SIZE (1024 * 1)
|
||||
|
||||
/* Defined, this value represents the size of the log pool. */
|
||||
#define UX_DEBUG_LOG_SIZE (1024 * 16)
|
||||
|
||||
extern void usbphy_set_highspeed_mode(void *regs, int on_off);
|
||||
|
||||
#define UX_HCD_EHCI_EXT_USBPHY_HIGHSPEED_MODE_SET(hcd_ehci, on_off) \
|
||||
usbphy_set_highspeed_mode(hcd_ehci, on_off)
|
||||
|
||||
/* Defined, this value will enable split transaction on EHCI host. */
|
||||
#define UX_HCD_EHCI_SPLIT_TRANSFER_ENABLE
|
||||
|
||||
#endif
|
|
@ -0,0 +1,157 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1021CAF4A
|
||||
** MIMXRT1021CAG4A
|
||||
** MIMXRT1021DAF5A
|
||||
** MIMXRT1021DAG5A
|
||||
**
|
||||
** Compiler: GNU C Compiler
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the GNU C Compiler
|
||||
**
|
||||
** Copyright (c) 2015 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2018 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0;
|
||||
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1800;
|
||||
|
||||
/* Specify the memory areas */
|
||||
|
||||
MEMORY
|
||||
{
|
||||
m_interrupts (RX) : ORIGIN = 0x2020a000, LENGTH = 0x00000400
|
||||
m_text (RW) : ORIGIN = 0x2020a400, LENGTH = 0x00015c00
|
||||
m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00010000
|
||||
}
|
||||
|
||||
GROUP (
|
||||
libnosys.a
|
||||
libgcc.a
|
||||
libc_nano.a
|
||||
libm.a
|
||||
libcr_newlib_none.a
|
||||
)
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code goes first into internal RAM */
|
||||
.interrupts :
|
||||
{
|
||||
__VECTOR_TABLE = .;
|
||||
__Vectors = .;
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} > m_interrupts
|
||||
|
||||
__VECTOR_RAM = __VECTOR_TABLE;
|
||||
__RAM_VECTOR_TABLE_SIZE_BYTES = 0x0;
|
||||
|
||||
/* The program code and other data goes into internal RAM */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} > m_text
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > m_text
|
||||
|
||||
.ARM :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} > m_text
|
||||
|
||||
__etext = .; /* define a global symbol at end of code */
|
||||
__DATA_ROM = .; /* Symbol is used by startup for data initialization */
|
||||
|
||||
.data : AT(__DATA_ROM)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__DATA_RAM = .;
|
||||
__data_start__ = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
. = ALIGN(4);
|
||||
__data_end__ = .; /* define a global symbol at data end */
|
||||
} > m_data
|
||||
|
||||
__DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
|
||||
|
||||
/* Uninitialized data section */
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
. = ALIGN(4);
|
||||
__START_BSS = .;
|
||||
__bss_start__ = .;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
__END_BSS = .;
|
||||
} > m_data
|
||||
|
||||
m_usb_bdt :
|
||||
{
|
||||
. = ALIGN(512);
|
||||
__START_USBGLOBAL = .;
|
||||
*(m_usb_bdt)
|
||||
KEEP(*(m_usb_bdt))
|
||||
} > m_data
|
||||
|
||||
m_usb_global :
|
||||
{
|
||||
*(m_usb_global)
|
||||
KEEP(*(m_usb_global))
|
||||
__END_USBGLOBAL = .;
|
||||
} > m_data
|
||||
|
||||
.heap :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__end__ = .;
|
||||
PROVIDE(end = .);
|
||||
__HeapBase = .;
|
||||
_pvHeapStart = .;
|
||||
. += HEAP_SIZE;
|
||||
__HeapLimit = .;
|
||||
} > m_data
|
||||
|
||||
.stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__StackLimit = .;
|
||||
. += STACK_SIZE;
|
||||
__StackTop = .;
|
||||
__STACK_TOP = .;
|
||||
PROVIDE(__stack = __StackTop);
|
||||
} > m_data
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
|
||||
ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
|
||||
}
|
|
@ -992,7 +992,12 @@ static usb_status_t USB_DeviceControlCallback(usb_device_handle handle,
|
|||
uint8_t state = 0U;
|
||||
|
||||
/* endpoint callback length is USB_CANCELLED_TRANSFER_LENGTH (0xFFFFFFFFU) when transfer is canceled */
|
||||
if ((USB_CANCELLED_TRANSFER_LENGTH == message->length) || (NULL == callbackParam))
|
||||
if (USB_CANCELLED_TRANSFER_LENGTH == message->length)
|
||||
{
|
||||
return kStatus_USB_Success;
|
||||
}
|
||||
|
||||
if (NULL == callbackParam)
|
||||
{
|
||||
return status;
|
||||
}
|
||||
|
|
|
@ -0,0 +1,3 @@
|
|||
<#if memory.name=="SRAM_DTC">
|
||||
*(.bss*)
|
||||
</#if>
|
|
@ -0,0 +1,6 @@
|
|||
<#if memory.name=="SRAM_ITC">
|
||||
*fsl_flexspi_nor_flash.o(.text*)
|
||||
*nor_flash_ops.o(.text*)
|
||||
*fsl_flexspi.o(.text*)
|
||||
*fsl_clock.o(.text*)
|
||||
</#if>
|
|
@ -0,0 +1 @@
|
|||
*(EXCLUDE_FILE(*fsl_flexspi_nor_flash.o *nor_flash_ops.o *fsl_flexspi.o *fsl_clock.o) .text*)
|
Binary file not shown.
|
@ -0,0 +1,26 @@
|
|||
M_VECTOR_RAM_SIZE = 0x00000180;
|
||||
/* Main DATA section (SRAM) */
|
||||
.data : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
_data = . ;
|
||||
*(vtable)
|
||||
*(.ramfunc*)
|
||||
KEEP(*(CodeQuickAccess))
|
||||
KEEP(*(DataQuickAccess))
|
||||
*flexspi_nor_flash_ops.o(.text .text* .rodata .rodata*)
|
||||
*fsl_flexspi.o(.text .text* .rodata .rodata*)
|
||||
*fsl_edma.o(.text .text* .rodata .rodata*)
|
||||
*fsl_flexspi_edma.o(.text .text* .rodata .rodata*)
|
||||
*(.data*)
|
||||
. = ALIGN(128);
|
||||
__VECTOR_RAM = .;
|
||||
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
|
||||
*(.m_interrupts_ram) /* This is a user defined section */
|
||||
. += M_VECTOR_RAM_SIZE;
|
||||
. = ALIGN(4) ;
|
||||
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
|
||||
_edata = . ;
|
||||
} > SRAM_DTC AT>BOARD_FLASH
|
||||
__VECTOR_TABLE = __vectors_start__;
|
||||
__RAM_VECTOR_TABLE_SIZE_BYTES = (__interrupts_ram_end__ - __interrupts_ram_start__);
|
|
@ -0,0 +1 @@
|
|||
*(EXCLUDE_FILE(*flexspi_nor_flash_ops.o *fsl_flexspi.o *fsl_flexspi_edma.o *fsl_edma.o) .text*)
|
|
@ -0,0 +1,3 @@
|
|||
<#if memory.name=="BOARD_SDRAM">
|
||||
*(.bss*)
|
||||
</#if>
|
|
@ -0,0 +1,4 @@
|
|||
<#if memory.name=="SRAM_ITC">
|
||||
*flexspi_nor_flash_ops.o(.text*)
|
||||
*fsl_flexspi.o(.text*)
|
||||
</#if>
|
|
@ -0,0 +1 @@
|
|||
*(EXCLUDE_FILE(*flexspi_nor_flash_ops.o *fsl_flexspi.o) .text*)
|
|
@ -992,7 +992,12 @@ static usb_status_t USB_DeviceControlCallback(usb_device_handle handle,
|
|||
uint8_t state = 0U;
|
||||
|
||||
/* endpoint callback length is USB_CANCELLED_TRANSFER_LENGTH (0xFFFFFFFFU) when transfer is canceled */
|
||||
if ((USB_CANCELLED_TRANSFER_LENGTH == message->length) || (NULL == callbackParam))
|
||||
if (USB_CANCELLED_TRANSFER_LENGTH == message->length)
|
||||
{
|
||||
return kStatus_USB_Success;
|
||||
}
|
||||
|
||||
if (NULL == callbackParam)
|
||||
{
|
||||
return status;
|
||||
}
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2020 NXP
|
||||
* Copyright 2020-2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
|
@ -189,14 +189,14 @@ static void flash_operation_task(void *pvParameters)
|
|||
uint8_t *nor_program_buffer = pvPortMalloc(256);
|
||||
if (NULL == nor_program_buffer)
|
||||
{
|
||||
PRINTF("nor_program_buffer memory allock failed!\r\n");
|
||||
PRINTF("nor_program_buffer memory allocation failed!\r\n");
|
||||
configASSERT(NULL);
|
||||
}
|
||||
|
||||
uint8_t *nor_read_buffer = pvPortMalloc(256);
|
||||
if (NULL == nor_read_buffer)
|
||||
{
|
||||
PRINTF("nor_read_buffer memory allock failed!\r\n");
|
||||
PRINTF("nor_read_buffer memory allocation failed!\r\n");
|
||||
configASSERT(NULL);
|
||||
}
|
||||
|
||||
|
|
|
@ -0,0 +1,3 @@
|
|||
<#if memory.name=="SRAM_DTC">
|
||||
*(.bss*)
|
||||
</#if>
|
|
@ -0,0 +1,5 @@
|
|||
<#if memory.name=="SRAM_ITC">
|
||||
*flexspi_nor_flash_ops.o(.text*)
|
||||
*fsl_flexspi.o(.text*)
|
||||
*fsl_clock.o(.text*)
|
||||
</#if>
|
|
@ -0,0 +1 @@
|
|||
*(EXCLUDE_FILE(*flexspi_nor_flash_ops.o *fsl_flexspi.o *fsl_clock.o) .text*)
|
|
@ -0,0 +1,3 @@
|
|||
<#if memory.name=="SRAM_ITC">
|
||||
*fsl_lpspi.o(.text .text* .rodata .rodata*)
|
||||
</#if>
|
|
@ -0,0 +1 @@
|
|||
*(EXCLUDE_FILE(*fsl_lpspi.o) .text*)
|
|
@ -0,0 +1,3 @@
|
|||
<#if memory.name=="SRAM_ITC">
|
||||
*fsl_lpspi.o(.text .text* .rodata .rodata*)
|
||||
</#if>
|
|
@ -0,0 +1 @@
|
|||
*(EXCLUDE_FILE(*fsl_lpspi.o) .text*)
|
|
@ -0,0 +1,136 @@
|
|||
# CROSS COMPILER SETTING
|
||||
SET(CMAKE_SYSTEM_NAME Generic)
|
||||
CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
|
||||
|
||||
# THE VERSION NUMBER
|
||||
SET (Tutorial_VERSION_MAJOR 1)
|
||||
SET (Tutorial_VERSION_MINOR 0)
|
||||
|
||||
# ENABLE ASM
|
||||
ENABLE_LANGUAGE(ASM)
|
||||
|
||||
SET(CMAKE_STATIC_LIBRARY_PREFIX)
|
||||
SET(CMAKE_STATIC_LIBRARY_SUFFIX)
|
||||
|
||||
SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
|
||||
SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
|
||||
|
||||
# CURRENT DIRECTORY
|
||||
SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
|
||||
|
||||
SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
|
||||
SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
|
||||
|
||||
|
||||
project(soem_gpio_pulse_bm)
|
||||
|
||||
set(MCUX_SDK_PROJECT_NAME soem_gpio_pulse_bm.elf)
|
||||
|
||||
include(${ProjDirPath}/flags.cmake)
|
||||
|
||||
include(${ProjDirPath}/config.cmake)
|
||||
|
||||
add_executable(${MCUX_SDK_PROJECT_NAME}
|
||||
"${ProjDirPath}/../pin_mux.c"
|
||||
"${ProjDirPath}/../pin_mux.h"
|
||||
"${ProjDirPath}/../soem_gpio_pulse.c"
|
||||
"${ProjDirPath}/../board.c"
|
||||
"${ProjDirPath}/../board.h"
|
||||
"${ProjDirPath}/../clock_config.c"
|
||||
"${ProjDirPath}/../clock_config.h"
|
||||
"${ProjDirPath}/../dcd.c"
|
||||
"${ProjDirPath}/../dcd.h"
|
||||
)
|
||||
|
||||
target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
|
||||
${ProjDirPath}/..
|
||||
${ProjDirPath}/../../../../../../middleware/soem/osal/baremetal
|
||||
)
|
||||
|
||||
set(CMAKE_MODULE_PATH
|
||||
${ProjDirPath}/../../../../../../components/phy/mdio/enet
|
||||
${ProjDirPath}/../../../../../../components/phy/device/phyksz8081
|
||||
${ProjDirPath}/../../../../../../devices/MIMXRT1021/drivers
|
||||
${ProjDirPath}/../../../../../../middleware/soem
|
||||
${ProjDirPath}/../../../../../../middleware
|
||||
${ProjDirPath}/../../../../../../devices/MIMXRT1021
|
||||
${ProjDirPath}/../../../../../../devices/MIMXRT1021/utilities
|
||||
${ProjDirPath}/../../../../../../components/uart
|
||||
${ProjDirPath}/../../../../../../components/serial_manager
|
||||
${ProjDirPath}/../../../../../../components/lists
|
||||
${ProjDirPath}/../../../../../../devices/MIMXRT1021/xip
|
||||
${ProjDirPath}/../../../../xip
|
||||
${ProjDirPath}/../../../../../../components/silicon_id
|
||||
${ProjDirPath}/../../../../../../components/phy
|
||||
${ProjDirPath}/../../../../../../CMSIS/Core/Include
|
||||
)
|
||||
|
||||
# include modules
|
||||
include(driver_mdio-enet_MIMXRT1021)
|
||||
|
||||
include(driver_phy-device-ksz8081_MIMXRT1021)
|
||||
|
||||
include(driver_gpt_MIMXRT1021)
|
||||
|
||||
include(middleware_soem_MIMXRT1021)
|
||||
|
||||
include(middleware_baremetal_MIMXRT1021)
|
||||
|
||||
include(driver_clock_MIMXRT1021)
|
||||
|
||||
include(driver_common_MIMXRT1021)
|
||||
|
||||
include(device_MIMXRT1021_CMSIS_MIMXRT1021)
|
||||
|
||||
include(utility_debug_console_MIMXRT1021)
|
||||
|
||||
include(component_lpuart_adapter_MIMXRT1021)
|
||||
|
||||
include(component_serial_manager_MIMXRT1021)
|
||||
|
||||
include(component_lists_MIMXRT1021)
|
||||
|
||||
include(component_serial_manager_uart_MIMXRT1021)
|
||||
|
||||
include(driver_lpuart_MIMXRT1021)
|
||||
|
||||
include(device_MIMXRT1021_startup_MIMXRT1021)
|
||||
|
||||
include(driver_iomuxc_MIMXRT1021)
|
||||
|
||||
include(utility_assert_MIMXRT1021)
|
||||
|
||||
include(driver_igpio_MIMXRT1021)
|
||||
|
||||
include(driver_xip_device_MIMXRT1021)
|
||||
|
||||
include(driver_xip_board_evkmimxrt1020_MIMXRT1021)
|
||||
|
||||
include(component_silicon_id_MIMXRT1021)
|
||||
|
||||
include(driver_mdio-common_MIMXRT1021)
|
||||
|
||||
include(CMSIS_Include_core_cm_MIMXRT1021)
|
||||
|
||||
include(driver_enet_MIMXRT1021)
|
||||
|
||||
include(driver_phy-common_MIMXRT1021)
|
||||
|
||||
include(utilities_misc_utilities_MIMXRT1021)
|
||||
|
||||
include(device_MIMXRT1021_system_MIMXRT1021)
|
||||
|
||||
|
||||
TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
|
||||
|
||||
target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m)
|
||||
|
||||
target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c)
|
||||
|
||||
target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc)
|
||||
|
||||
target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys)
|
||||
|
||||
TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
|
||||
|
||||
|
|
@ -0,0 +1,280 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1021CAF4A
|
||||
** MIMXRT1021CAG4A
|
||||
** MIMXRT1021DAF5A
|
||||
** MIMXRT1021DAG5A
|
||||
**
|
||||
** Compiler: GNU C Compiler
|
||||
** Reference manual: IMXRT1020RM Rev.1, 12/2018 | IMXRT1020SRM Rev.3
|
||||
** Version: rev. 0.1, 2017-06-06
|
||||
** Build: b210709
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the GNU C Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2021 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x10000;
|
||||
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
|
||||
VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x00000400 : 0;
|
||||
NCACHE_HEAP_START = DEFINED(__heap_noncacheable__) ? 0x82000000 - HEAP_SIZE : 0x81E00000 - HEAP_SIZE;
|
||||
NCACHE_HEAP_SIZE = DEFINED(__heap_noncacheable__) ? HEAP_SIZE : 0x0000;
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
m_flash_config (RX) : ORIGIN = 0x60000000, LENGTH = 0x00001000
|
||||
m_ivt (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000
|
||||
m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400
|
||||
m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x007FDC00
|
||||
m_qacode (RX) : ORIGIN = 0x00000000, LENGTH = 0x00010000
|
||||
m_data (RW) : ORIGIN = 0x80000000, LENGTH = DEFINED(__heap_noncacheable__) ? 0x01E00000 : 0x01E00000 - HEAP_SIZE
|
||||
m_ncache (RW) : ORIGIN = 0x81E00000, LENGTH = DEFINED(__heap_noncacheable__) ? 0x00200000 - HEAP_SIZE : 0x00200000
|
||||
m_data2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00010000
|
||||
m_data3 (RW) : ORIGIN = 0x20200000, LENGTH = 0x00020000
|
||||
m_heap (RW) : ORIGIN = NCACHE_HEAP_START, LENGTH = HEAP_SIZE
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
__NCACHE_REGION_START = ORIGIN(m_ncache);
|
||||
__NCACHE_REGION_SIZE = LENGTH(m_ncache) + NCACHE_HEAP_SIZE;
|
||||
|
||||
.flash_config :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__FLASH_BASE = .;
|
||||
KEEP(* (.boot_hdr.conf)) /* flash config section */
|
||||
. = ALIGN(4);
|
||||
} > m_flash_config
|
||||
|
||||
ivt_begin = ORIGIN(m_flash_config) + LENGTH(m_flash_config);
|
||||
|
||||
.ivt : AT(ivt_begin)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(* (.boot_hdr.ivt)) /* ivt section */
|
||||
KEEP(* (.boot_hdr.boot_data)) /* boot section */
|
||||
KEEP(* (.boot_hdr.dcd_data)) /* dcd section */
|
||||
. = ALIGN(4);
|
||||
} > m_ivt
|
||||
|
||||
/* The startup code goes first into internal RAM */
|
||||
.interrupts :
|
||||
{
|
||||
__VECTOR_TABLE = .;
|
||||
__Vectors = .;
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} > m_interrupts
|
||||
|
||||
/* The program code and other data goes into internal RAM */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
. = ALIGN(4);
|
||||
} > m_text
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > m_text
|
||||
|
||||
.ARM :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} > m_text
|
||||
|
||||
.ctors :
|
||||
{
|
||||
__CTOR_LIST__ = .;
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
from the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
__CTOR_END__ = .;
|
||||
} > m_text
|
||||
|
||||
.dtors :
|
||||
{
|
||||
__DTOR_LIST__ = .;
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
__DTOR_END__ = .;
|
||||
} > m_text
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} > m_text
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} > m_text
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} > m_text
|
||||
|
||||
__etext = .; /* define a global symbol at end of code */
|
||||
__DATA_ROM = .; /* Symbol is used by startup for data initialization */
|
||||
|
||||
.interrupts_ram :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__VECTOR_RAM__ = .;
|
||||
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
|
||||
*(.m_interrupts_ram) /* This is a user defined section */
|
||||
. += VECTOR_RAM_SIZE;
|
||||
. = ALIGN(4);
|
||||
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
|
||||
} > m_data
|
||||
|
||||
__VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);
|
||||
__RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;
|
||||
|
||||
.data : AT(__DATA_ROM)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__DATA_RAM = .;
|
||||
__data_start__ = .; /* create a global symbol at data start */
|
||||
*(m_usb_dma_init_data)
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
KEEP(*(.jcr*))
|
||||
. = ALIGN(4);
|
||||
__data_end__ = .; /* define a global symbol at data end */
|
||||
} > m_data
|
||||
|
||||
__ram_function_flash_start = __DATA_ROM + (__data_end__ - __data_start__); /* Symbol is used by startup for TCM data initialization */
|
||||
|
||||
.ram_function : AT(__ram_function_flash_start)
|
||||
{
|
||||
. = ALIGN(32);
|
||||
__ram_function_start__ = .;
|
||||
*(CodeQuickAccess)
|
||||
. = ALIGN(128);
|
||||
__ram_function_end__ = .;
|
||||
} > m_qacode
|
||||
|
||||
__NDATA_ROM = __ram_function_flash_start + (__ram_function_end__ - __ram_function_start__);
|
||||
.ncache.init : AT(__NDATA_ROM)
|
||||
{
|
||||
__noncachedata_start__ = .; /* create a global symbol at ncache data start */
|
||||
*(NonCacheable.init)
|
||||
. = ALIGN(4);
|
||||
__noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
|
||||
} > m_ncache
|
||||
. = __noncachedata_init_end__;
|
||||
.ncache :
|
||||
{
|
||||
*(NonCacheable)
|
||||
. = ALIGN(4);
|
||||
__noncachedata_end__ = .; /* define a global symbol at ncache data end */
|
||||
} > m_ncache
|
||||
|
||||
__DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
|
||||
text_end = ORIGIN(m_text) + LENGTH(m_text);
|
||||
ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
|
||||
|
||||
.qadata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(DataQuickAccess) /* quick access data section */
|
||||
. = ALIGN(4);
|
||||
} > m_data2
|
||||
|
||||
/* Uninitialized data section */
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
. = ALIGN(4);
|
||||
__START_BSS = .;
|
||||
__bss_start__ = .;
|
||||
*(m_usb_dma_noninit_data)
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
__END_BSS = .;
|
||||
} > m_data
|
||||
|
||||
.heap :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__end__ = .;
|
||||
PROVIDE(end = .);
|
||||
__HeapBase = .;
|
||||
. += HEAP_SIZE;
|
||||
__HeapLimit = .;
|
||||
__heap_limit = .; /* Add for _sbrk */
|
||||
} > m_heap
|
||||
|
||||
.stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
. += STACK_SIZE;
|
||||
} > m_data
|
||||
|
||||
/* Initializes stack on the end of block */
|
||||
__StackTop = ORIGIN(m_data) + LENGTH(m_data);
|
||||
__StackLimit = __StackTop - STACK_SIZE;
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
|
@ -0,0 +1,15 @@
|
|||
if exist CMakeFiles (RD /s /Q CMakeFiles)
|
||||
if exist Makefile (DEL /s /Q /F Makefile)
|
||||
if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
|
||||
if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
|
||||
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flexspi_nor_sdram_debug .
|
||||
mingw32-make -j
|
||||
|
||||
if exist CMakeFiles (RD /s /Q CMakeFiles)
|
||||
if exist Makefile (DEL /s /Q /F Makefile)
|
||||
if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
|
||||
if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
|
||||
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flexspi_nor_sdram_release .
|
||||
mingw32-make -j
|
||||
|
||||
IF "%1" == "" ( pause )
|
|
@ -0,0 +1,15 @@
|
|||
#!/bin/sh
|
||||
if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
|
||||
if [ -f "Makefile" ];then rm -f Makefile; fi
|
||||
if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
|
||||
if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
|
||||
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flexspi_nor_sdram_debug .
|
||||
make -j
|
||||
|
||||
if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
|
||||
if [ -f "Makefile" ];then rm -f Makefile; fi
|
||||
if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
|
||||
if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
|
||||
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flexspi_nor_sdram_release .
|
||||
make -j
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
if exist CMakeFiles (RD /s /Q CMakeFiles)
|
||||
if exist Makefile (DEL /s /Q /F Makefile)
|
||||
if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
|
||||
if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
|
||||
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flexspi_nor_sdram_debug .
|
||||
mingw32-make -j 2> build_log.txt
|
|
@ -0,0 +1,7 @@
|
|||
#!/bin/sh
|
||||
if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
|
||||
if [ -f "Makefile" ];then rm -f Makefile; fi
|
||||
if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
|
||||
if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
|
||||
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flexspi_nor_sdram_debug .
|
||||
make -j 2>&1 | tee build_log.txt
|
|
@ -0,0 +1,6 @@
|
|||
if exist CMakeFiles (RD /s /Q CMakeFiles)
|
||||
if exist Makefile (DEL /s /Q /F Makefile)
|
||||
if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
|
||||
if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
|
||||
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flexspi_nor_sdram_release .
|
||||
mingw32-make -j 2> build_log.txt
|
|
@ -0,0 +1,7 @@
|
|||
#!/bin/sh
|
||||
if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
|
||||
if [ -f "Makefile" ];then rm -f Makefile; fi
|
||||
if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
|
||||
if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
|
||||
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flexspi_nor_sdram_release .
|
||||
make -j 2>&1 | tee build_log.txt
|
|
@ -0,0 +1,3 @@
|
|||
RD /s /Q flexspi_nor_sdram_debug flexspi_nor_sdram_release CMakeFiles
|
||||
DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
|
||||
pause
|
|
@ -0,0 +1,3 @@
|
|||
#!/bin/sh
|
||||
rm -rf flexspi_nor_sdram_debug flexspi_nor_sdram_release CMakeFiles
|
||||
rm -rf Makefile cmake_install.cmake CMakeCache.txt
|
|
@ -0,0 +1,5 @@
|
|||
# config to select component, the format is CONFIG_USE_${component}
|
||||
set(CONFIG_USE_middleware_baremetal_MIMXRT1021 true)
|
||||
set(CONFIG_USE_component_serial_manager_uart_MIMXRT1021 true)
|
||||
set(CONFIG_USE_driver_lpuart_MIMXRT1021 true)
|
||||
set(CONFIG_USE_driver_common_MIMXRT1021 true)
|
|
@ -0,0 +1,191 @@
|
|||
SET(CMAKE_ASM_FLAGS_FLEXSPI_NOR_SDRAM_DEBUG " \
|
||||
${CMAKE_ASM_FLAGS_FLEXSPI_NOR_SDRAM_DEBUG} \
|
||||
-D__STARTUP_CLEAR_BSS \
|
||||
-DDEBUG \
|
||||
-D__STARTUP_INITIALIZE_NONCACHEDATA \
|
||||
-mcpu=cortex-m7 \
|
||||
-mfloat-abi=hard \
|
||||
-mfpu=fpv5-d16 \
|
||||
-mthumb \
|
||||
")
|
||||
SET(CMAKE_ASM_FLAGS_FLEXSPI_NOR_SDRAM_RELEASE " \
|
||||
${CMAKE_ASM_FLAGS_FLEXSPI_NOR_SDRAM_RELEASE} \
|
||||
-D__STARTUP_CLEAR_BSS \
|
||||
-DNDEBUG \
|
||||
-D__STARTUP_INITIALIZE_NONCACHEDATA \
|
||||
-mcpu=cortex-m7 \
|
||||
-mfloat-abi=hard \
|
||||
-mfpu=fpv5-d16 \
|
||||
-mthumb \
|
||||
")
|
||||
SET(CMAKE_C_FLAGS_FLEXSPI_NOR_SDRAM_DEBUG " \
|
||||
${CMAKE_C_FLAGS_FLEXSPI_NOR_SDRAM_DEBUG} \
|
||||
-DXIP_EXTERNAL_FLASH=1 \
|
||||
-DXIP_BOOT_HEADER_ENABLE=1 \
|
||||
-DXIP_BOOT_HEADER_DCD_ENABLE=1 \
|
||||
-DSKIP_SYSCLK_INIT \
|
||||
-DDATA_SECTION_IS_CACHEABLE=1 \
|
||||
-DDEBUG \
|
||||
-DCPU_MIMXRT1021DAG5A \
|
||||
-DSDK_DEBUGCONSOLE_UART \
|
||||
-DSERIAL_PORT_TYPE_UART=1 \
|
||||
-DPRINTF_ADVANCED_ENABLE=1 \
|
||||
-DFSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE \
|
||||
-DMCUXPRESSO_SDK \
|
||||
-g \
|
||||
-O0 \
|
||||
-mcpu=cortex-m7 \
|
||||
-Wall \
|
||||
-mfloat-abi=hard \
|
||||
-mfpu=fpv5-d16 \
|
||||
-mthumb \
|
||||
-MMD \
|
||||
-MP \
|
||||
-fno-common \
|
||||
-ffunction-sections \
|
||||
-fdata-sections \
|
||||
-ffreestanding \
|
||||
-fno-builtin \
|
||||
-mapcs \
|
||||
-std=gnu99 \
|
||||
")
|
||||
SET(CMAKE_C_FLAGS_FLEXSPI_NOR_SDRAM_RELEASE " \
|
||||
${CMAKE_C_FLAGS_FLEXSPI_NOR_SDRAM_RELEASE} \
|
||||
-DXIP_EXTERNAL_FLASH=1 \
|
||||
-DXIP_BOOT_HEADER_ENABLE=1 \
|
||||
-DXIP_BOOT_HEADER_DCD_ENABLE=1 \
|
||||
-DSKIP_SYSCLK_INIT \
|
||||
-DDATA_SECTION_IS_CACHEABLE=1 \
|
||||
-DNDEBUG \
|
||||
-DCPU_MIMXRT1021DAG5A \
|
||||
-DSDK_DEBUGCONSOLE_UART \
|
||||
-DSERIAL_PORT_TYPE_UART=1 \
|
||||
-DPRINTF_ADVANCED_ENABLE=1 \
|
||||
-DFSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE \
|
||||
-DMCUXPRESSO_SDK \
|
||||
-Os \
|
||||
-mcpu=cortex-m7 \
|
||||
-Wall \
|
||||
-mfloat-abi=hard \
|
||||
-mfpu=fpv5-d16 \
|
||||
-mthumb \
|
||||
-MMD \
|
||||
-MP \
|
||||
-fno-common \
|
||||
-ffunction-sections \
|
||||
-fdata-sections \
|
||||
-ffreestanding \
|
||||
-fno-builtin \
|
||||
-mapcs \
|
||||
-std=gnu99 \
|
||||
")
|
||||
SET(CMAKE_CXX_FLAGS_FLEXSPI_NOR_SDRAM_DEBUG " \
|
||||
${CMAKE_CXX_FLAGS_FLEXSPI_NOR_SDRAM_DEBUG} \
|
||||
-DDEBUG \
|
||||
-DSERIAL_PORT_TYPE_UART=1 \
|
||||
-DMCUXPRESSO_SDK \
|
||||
-g \
|
||||
-O0 \
|
||||
-mcpu=cortex-m7 \
|
||||
-Wall \
|
||||
-mfloat-abi=hard \
|
||||
-mfpu=fpv5-d16 \
|
||||
-mthumb \
|
||||
-MMD \
|
||||
-MP \
|
||||
-fno-common \
|
||||
-ffunction-sections \
|
||||
-fdata-sections \
|
||||
-ffreestanding \
|
||||
-fno-builtin \
|
||||
-mapcs \
|
||||
-fno-rtti \
|
||||
-fno-exceptions \
|
||||
")
|
||||
SET(CMAKE_CXX_FLAGS_FLEXSPI_NOR_SDRAM_RELEASE " \
|
||||
${CMAKE_CXX_FLAGS_FLEXSPI_NOR_SDRAM_RELEASE} \
|
||||
-DNDEBUG \
|
||||
-DSERIAL_PORT_TYPE_UART=1 \
|
||||
-DMCUXPRESSO_SDK \
|
||||
-Os \
|
||||
-mcpu=cortex-m7 \
|
||||
-Wall \
|
||||
-mfloat-abi=hard \
|
||||
-mfpu=fpv5-d16 \
|
||||
-mthumb \
|
||||
-MMD \
|
||||
-MP \
|
||||
-fno-common \
|
||||
-ffunction-sections \
|
||||
-fdata-sections \
|
||||
-ffreestanding \
|
||||
-fno-builtin \
|
||||
-mapcs \
|
||||
-fno-rtti \
|
||||
-fno-exceptions \
|
||||
")
|
||||
SET(CMAKE_EXE_LINKER_FLAGS_FLEXSPI_NOR_SDRAM_DEBUG " \
|
||||
${CMAKE_EXE_LINKER_FLAGS_FLEXSPI_NOR_SDRAM_DEBUG} \
|
||||
-g \
|
||||
-mcpu=cortex-m7 \
|
||||
-Wall \
|
||||
-mfloat-abi=hard \
|
||||
-mfpu=fpv5-d16 \
|
||||
--specs=nano.specs \
|
||||
--specs=nosys.specs \
|
||||
-fno-common \
|
||||
-ffunction-sections \
|
||||
-fdata-sections \
|
||||
-ffreestanding \
|
||||
-fno-builtin \
|
||||
-mthumb \
|
||||
-mapcs \
|
||||
-Xlinker \
|
||||
--gc-sections \
|
||||
-Xlinker \
|
||||
-static \
|
||||
-Xlinker \
|
||||
-z \
|
||||
-Xlinker \
|
||||
muldefs \
|
||||
-Xlinker \
|
||||
-Map=output.map \
|
||||
-Wl,--print-memory-usage \
|
||||
-Xlinker \
|
||||
--defsym=__stack_size__=0x1000 \
|
||||
-Xlinker \
|
||||
--defsym=__heap_size__=0x10000 \
|
||||
-T${ProjDirPath}/MIMXRT1021xxxxx_flexspi_nor_sdram.ld -static \
|
||||
")
|
||||
SET(CMAKE_EXE_LINKER_FLAGS_FLEXSPI_NOR_SDRAM_RELEASE " \
|
||||
${CMAKE_EXE_LINKER_FLAGS_FLEXSPI_NOR_SDRAM_RELEASE} \
|
||||
-mcpu=cortex-m7 \
|
||||
-Wall \
|
||||
-mfloat-abi=hard \
|
||||
-mfpu=fpv5-d16 \
|
||||
--specs=nano.specs \
|
||||
--specs=nosys.specs \
|
||||
-fno-common \
|
||||
-ffunction-sections \
|
||||
-fdata-sections \
|
||||
-ffreestanding \
|
||||
-fno-builtin \
|
||||
-mthumb \
|
||||
-mapcs \
|
||||
-Xlinker \
|
||||
--gc-sections \
|
||||
-Xlinker \
|
||||
-static \
|
||||
-Xlinker \
|
||||
-z \
|
||||
-Xlinker \
|
||||
muldefs \
|
||||
-Xlinker \
|
||||
-Map=output.map \
|
||||
-Wl,--print-memory-usage \
|
||||
-Xlinker \
|
||||
--defsym=__stack_size__=0x1000 \
|
||||
-Xlinker \
|
||||
--defsym=__heap_size__=0x10000 \
|
||||
-T${ProjDirPath}/MIMXRT1021xxxxx_flexspi_nor_sdram.ld -static \
|
||||
")
|
|
@ -0,0 +1,294 @@
|
|||
/*
|
||||
* Copyright 2018-2019 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_debug_console.h"
|
||||
#include "board.h"
|
||||
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
|
||||
#include "fsl_lpi2c.h"
|
||||
#endif /* SDK_I2C_BASED_COMPONENT_USED */
|
||||
#include "fsl_iomuxc.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
/* Get debug console frequency. */
|
||||
uint32_t BOARD_DebugConsoleSrcFreq(void)
|
||||
{
|
||||
uint32_t freq;
|
||||
|
||||
/* To make it simple, we assume default PLL and divider settings, and the only variable
|
||||
from application is use PLL3 source or OSC source */
|
||||
if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
|
||||
{
|
||||
freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
|
||||
}
|
||||
else
|
||||
{
|
||||
freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
|
||||
}
|
||||
|
||||
return freq;
|
||||
}
|
||||
|
||||
/* Initialize debug console. */
|
||||
void BOARD_InitDebugConsole(void)
|
||||
{
|
||||
uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
|
||||
|
||||
DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
|
||||
}
|
||||
|
||||
/* MPU configuration. */
|
||||
void BOARD_ConfigMPU(void)
|
||||
{
|
||||
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
|
||||
extern uint32_t Image$$RW_m_ncache$$Base[];
|
||||
/* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
|
||||
extern uint32_t Image$$RW_m_ncache_unused$$Base[];
|
||||
extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
|
||||
uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
|
||||
uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
|
||||
0 :
|
||||
((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
|
||||
#elif defined(__MCUXPRESSO)
|
||||
extern uint32_t __base_NCACHE_REGION;
|
||||
extern uint32_t __top_NCACHE_REGION;
|
||||
uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
|
||||
uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
|
||||
#elif defined(__ICCARM__) || defined(__GNUC__)
|
||||
extern uint32_t __NCACHE_REGION_START[];
|
||||
extern uint32_t __NCACHE_REGION_SIZE[];
|
||||
uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
|
||||
uint32_t size = (uint32_t)__NCACHE_REGION_SIZE;
|
||||
#endif
|
||||
volatile uint32_t i = 0;
|
||||
|
||||
/* Disable I cache and D cache */
|
||||
if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
|
||||
{
|
||||
SCB_DisableICache();
|
||||
}
|
||||
if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
|
||||
{
|
||||
SCB_DisableDCache();
|
||||
}
|
||||
|
||||
/* Disable MPU */
|
||||
ARM_MPU_Disable();
|
||||
|
||||
/* MPU configure:
|
||||
* Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
|
||||
* SubRegionDisable, Size)
|
||||
* API in mpu_armv7.h.
|
||||
* param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
|
||||
* disabled.
|
||||
* param AccessPermission Data access permissions, allows you to configure read/write access for User and
|
||||
* Privileged mode.
|
||||
* Use MACROS defined in mpu_armv7.h:
|
||||
* ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
|
||||
* Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
|
||||
* TypeExtField IsShareable IsCacheable IsBufferable Memory Attribute Shareability Cache
|
||||
* 0 x 0 0 Strongly Ordered shareable
|
||||
* 0 x 0 1 Device shareable
|
||||
* 0 0 1 0 Normal not shareable Outer and inner write
|
||||
* through no write allocate
|
||||
* 0 0 1 1 Normal not shareable Outer and inner write
|
||||
* back no write allocate
|
||||
* 0 1 1 0 Normal shareable Outer and inner write
|
||||
* through no write allocate
|
||||
* 0 1 1 1 Normal shareable Outer and inner write
|
||||
* back no write allocate
|
||||
* 1 0 0 0 Normal not shareable outer and inner
|
||||
* noncache
|
||||
* 1 1 0 0 Normal shareable outer and inner
|
||||
* noncache
|
||||
* 1 0 1 1 Normal not shareable outer and inner write
|
||||
* back write/read acllocate
|
||||
* 1 1 1 1 Normal shareable outer and inner write
|
||||
* back write/read acllocate
|
||||
* 2 x 0 0 Device not shareable
|
||||
* Above are normal use settings, if your want to see more details or want to config different inner/outter cache
|
||||
* policy.
|
||||
* please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
|
||||
* param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
|
||||
* param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
|
||||
* mpu_armv7.h.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Add default region to deny access to whole address space to workaround speculative prefetch.
|
||||
* Refer to Arm errata 1013783-B for more details.
|
||||
*
|
||||
*/
|
||||
/* Region 0 setting: Instruction access disabled, No data access permission. */
|
||||
MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 0, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
|
||||
|
||||
/* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
|
||||
MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
|
||||
|
||||
/* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */
|
||||
MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
|
||||
|
||||
#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
|
||||
/* Region 3 setting: Memory with Normal type, not shareable, outer/inner write back. */
|
||||
MPU->RBAR = ARM_MPU_RBAR(3, 0x60000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_8MB);
|
||||
#endif
|
||||
|
||||
/* Region 4 setting: Memory with Device type, not shareable, non-cacheable. */
|
||||
MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
|
||||
|
||||
/* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||||
MPU->RBAR = ARM_MPU_RBAR(5, 0x00000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64KB);
|
||||
|
||||
/* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||||
MPU->RBAR = ARM_MPU_RBAR(6, 0x20000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64KB);
|
||||
|
||||
/* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||||
MPU->RBAR = ARM_MPU_RBAR(7, 0x20200000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
|
||||
|
||||
/* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||||
MPU->RBAR = ARM_MPU_RBAR(8, 0x80000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
|
||||
|
||||
while ((size >> i) > 0x1U)
|
||||
{
|
||||
i++;
|
||||
}
|
||||
|
||||
if (i != 0)
|
||||
{
|
||||
/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
|
||||
assert(!(nonCacheStart % size));
|
||||
assert(size == (uint32_t)(1 << i));
|
||||
assert(i >= 5);
|
||||
|
||||
/* Region 9 setting: Memory with Normal type, not shareable, non-cacheable */
|
||||
MPU->RBAR = ARM_MPU_RBAR(9, nonCacheStart);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
|
||||
}
|
||||
|
||||
/* Region 10 setting: Memory with Device type, not shareable, non-cacheable */
|
||||
MPU->RBAR = ARM_MPU_RBAR(10, 0x40000000);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4MB);
|
||||
|
||||
/* Enable MPU */
|
||||
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
|
||||
|
||||
/* Enable I cache and D cache */
|
||||
SCB_EnableDCache();
|
||||
SCB_EnableICache();
|
||||
}
|
||||
|
||||
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
|
||||
void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
|
||||
{
|
||||
lpi2c_master_config_t lpi2cConfig = {0};
|
||||
|
||||
/*
|
||||
* lpi2cConfig.debugEnable = false;
|
||||
* lpi2cConfig.ignoreAck = false;
|
||||
* lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
|
||||
* lpi2cConfig.baudRate_Hz = 100000U;
|
||||
* lpi2cConfig.busIdleTimeout_ns = 0;
|
||||
* lpi2cConfig.pinLowTimeout_ns = 0;
|
||||
* lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
|
||||
* lpi2cConfig.sclGlitchFilterWidth_ns = 0;
|
||||
*/
|
||||
LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
|
||||
LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
|
||||
}
|
||||
|
||||
status_t BOARD_LPI2C_Send(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subAddressSize,
|
||||
uint8_t *txBuff,
|
||||
uint8_t txBuffSize)
|
||||
{
|
||||
lpi2c_master_transfer_t xfer;
|
||||
|
||||
xfer.flags = kLPI2C_TransferDefaultFlag;
|
||||
xfer.slaveAddress = deviceAddress;
|
||||
xfer.direction = kLPI2C_Write;
|
||||
xfer.subaddress = subAddress;
|
||||
xfer.subaddressSize = subAddressSize;
|
||||
xfer.data = txBuff;
|
||||
xfer.dataSize = txBuffSize;
|
||||
|
||||
return LPI2C_MasterTransferBlocking(base, &xfer);
|
||||
}
|
||||
|
||||
status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subAddressSize,
|
||||
uint8_t *rxBuff,
|
||||
uint8_t rxBuffSize)
|
||||
{
|
||||
lpi2c_master_transfer_t xfer;
|
||||
|
||||
xfer.flags = kLPI2C_TransferDefaultFlag;
|
||||
xfer.slaveAddress = deviceAddress;
|
||||
xfer.direction = kLPI2C_Read;
|
||||
xfer.subaddress = subAddress;
|
||||
xfer.subaddressSize = subAddressSize;
|
||||
xfer.data = rxBuff;
|
||||
xfer.dataSize = rxBuffSize;
|
||||
|
||||
return LPI2C_MasterTransferBlocking(base, &xfer);
|
||||
}
|
||||
|
||||
void BOARD_Accel_I2C_Init(void)
|
||||
{
|
||||
BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
|
||||
}
|
||||
|
||||
status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
|
||||
{
|
||||
uint8_t data = (uint8_t)txBuff;
|
||||
|
||||
return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
|
||||
}
|
||||
|
||||
status_t BOARD_Accel_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
|
||||
{
|
||||
return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
|
||||
}
|
||||
|
||||
void BOARD_Codec_I2C_Init(void)
|
||||
{
|
||||
BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
|
||||
}
|
||||
|
||||
status_t BOARD_Codec_I2C_Send(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
|
||||
{
|
||||
return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
|
||||
txBuffSize);
|
||||
}
|
||||
|
||||
status_t BOARD_Codec_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
|
||||
{
|
||||
return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
|
||||
}
|
||||
#endif /* SDK_I2C_BASED_COMPONENT_USED */
|
|
@ -0,0 +1,156 @@
|
|||
/*
|
||||
* Copyright 2018-2019 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _BOARD_H_
|
||||
#define _BOARD_H_
|
||||
|
||||
#include "clock_config.h"
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_gpio.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
/*! @brief The board name */
|
||||
#define BOARD_NAME "MIMXRT1020-EVK"
|
||||
|
||||
/* The UART to use for debug messages. */
|
||||
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
|
||||
#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1
|
||||
#define BOARD_DEBUG_UART_INSTANCE 1U
|
||||
|
||||
#define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
|
||||
|
||||
#define BOARD_UART_IRQ LPUART1_IRQn
|
||||
#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler
|
||||
|
||||
#ifndef BOARD_DEBUG_UART_BAUDRATE
|
||||
#define BOARD_DEBUG_UART_BAUDRATE (115200U)
|
||||
#endif /* BOARD_DEBUG_UART_BAUDRATE */
|
||||
|
||||
/* @Brief Board accelerator sensor configuration */
|
||||
#define BOARD_ACCEL_I2C_BASEADDR LPI2C4
|
||||
#define BOARD_ACCEL_I2C_CLOCK_SOURCE_SELECT (0U)
|
||||
#define BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER (5U)
|
||||
#define BOARD_ACCEL_I2C_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER + 1U))
|
||||
|
||||
#define BOARD_CODEC_I2C_BASEADDR LPI2C1
|
||||
#define BOARD_CODEC_I2C_INSTANCE 1U
|
||||
#define BOARD_CODEC_I2C_CLOCK_SOURCE_SELECT (0U)
|
||||
#define BOARD_CODEC_I2C_CLOCK_SOURCE_DIVIDER (5U)
|
||||
#define BOARD_CODEC_I2C_CLOCK_FREQ (10000000U)
|
||||
|
||||
/*! @brief The USER_LED used for board */
|
||||
#define LOGIC_LED_ON (0U)
|
||||
#define LOGIC_LED_OFF (1U)
|
||||
#ifndef BOARD_USER_LED_GPIO
|
||||
#define BOARD_USER_LED_GPIO GPIO1
|
||||
#endif
|
||||
#ifndef BOARD_USER_LED_GPIO_PIN
|
||||
#define BOARD_USER_LED_GPIO_PIN (5U)
|
||||
#endif
|
||||
|
||||
#define USER_LED_INIT(output) \
|
||||
GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, output); \
|
||||
BOARD_USER_LED_GPIO->GDIR |= (1U << BOARD_USER_LED_GPIO_PIN) /*!< Enable target USER_LED */
|
||||
#define USER_LED_ON() \
|
||||
GPIO_PortClear(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!< Turn off target USER_LED */
|
||||
#define USER_LED_OFF() GPIO_PortSet(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!<Turn on target USER_LED*/
|
||||
#define USER_LED_TOGGLE() \
|
||||
GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, \
|
||||
0x1 ^ GPIO_PinRead(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN)) /*!< Toggle target USER_LED */
|
||||
|
||||
/*! @brief Define the port interrupt number for the board switches */
|
||||
#ifndef BOARD_USER_BUTTON_GPIO
|
||||
#define BOARD_USER_BUTTON_GPIO GPIO5
|
||||
#endif
|
||||
#ifndef BOARD_USER_BUTTON_GPIO_PIN
|
||||
#define BOARD_USER_BUTTON_GPIO_PIN (0U)
|
||||
#endif
|
||||
#define BOARD_USER_BUTTON_IRQ GPIO5_Combined_0_15_IRQn
|
||||
#define BOARD_USER_BUTTON_IRQ_HANDLER GPIO5_Combined_0_15_IRQHandler
|
||||
#define BOARD_USER_BUTTON_NAME "SW4"
|
||||
|
||||
/*! @brief The hyper flash size */
|
||||
#define BOARD_FLASH_SIZE (0x800000U)
|
||||
|
||||
/*! @brief The ENET PHY address. */
|
||||
#define BOARD_ENET0_PHY_ADDRESS (0x02U) /* Phy address of enet port 0. */
|
||||
|
||||
/* USB PHY condfiguration */
|
||||
#define BOARD_USB_PHY_D_CAL (0x0CU)
|
||||
#define BOARD_USB_PHY_TXCAL45DP (0x06U)
|
||||
#define BOARD_USB_PHY_TXCAL45DM (0x06U)
|
||||
|
||||
#define BOARD_ARDUINO_INT_IRQ (GPIO1_Combined_16_31_IRQn)
|
||||
#define BOARD_ARDUINO_I2C_IRQ (LPI2C4_IRQn)
|
||||
#define BOARD_ARDUINO_I2C_INDEX (4)
|
||||
|
||||
/* Display. */
|
||||
#define BOARD_LCD_DC_GPIO GPIO1 /*! LCD data/command port */
|
||||
#define BOARD_LCD_DC_GPIO_PIN 15U /*! LCD data/command pin */
|
||||
|
||||
/* @Brief Board Bluetooth HCI UART configuration */
|
||||
#define BOARD_BT_UART_BASEADDR LPUART3
|
||||
#define BOARD_BT_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
|
||||
#define BOARD_BT_UART_IRQ LPUART3_IRQn
|
||||
#define BOARD_BT_UART_IRQ_HANDLER LPUART3_IRQHandler
|
||||
|
||||
/*! @brief board has sdcard */
|
||||
#define BOARD_HAS_SDCARD (1U)
|
||||
|
||||
/* Serial MWM WIFI */
|
||||
#define BOARD_SERIAL_MWM_PORT_CLK_FREQ BOARD_DebugConsoleSrcFreq()
|
||||
#define BOARD_SERIAL_MWM_PORT LPUART2
|
||||
#define BOARD_SERIAL_MWM_PORT_IRQn LPUART2_IRQn
|
||||
#define BOARD_SERIAL_MWM_RST_GPIO GPIO1
|
||||
#define BOARD_SERIAL_MWM_RST_PIN 22
|
||||
#define BOARD_SERIAL_MWM_RST_WRITE(output) GPIO_PinWrite(BOARD_SERIAL_MWM_RST_GPIO, BOARD_SERIAL_MWM_RST_PIN, output)
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
uint32_t BOARD_DebugConsoleSrcFreq(void);
|
||||
|
||||
void BOARD_InitDebugConsole(void);
|
||||
void BOARD_ConfigMPU(void);
|
||||
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
|
||||
void BOARD_InitDebugConsole(void);
|
||||
void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz);
|
||||
status_t BOARD_LPI2C_Send(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subaddressSize,
|
||||
uint8_t *txBuff,
|
||||
uint8_t txBuffSize);
|
||||
status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subaddressSize,
|
||||
uint8_t *rxBuff,
|
||||
uint8_t rxBuffSize);
|
||||
void BOARD_Accel_I2C_Init(void);
|
||||
status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
|
||||
status_t BOARD_Accel_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
|
||||
void BOARD_Codec_I2C_Init(void);
|
||||
status_t BOARD_Codec_I2C_Send(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
|
||||
status_t BOARD_Codec_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
|
||||
#endif /* SDK_I2C_BASED_COMPONENT_USED */
|
||||
void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength);
|
||||
void BOARD_MMC_Pin_Config(uint32_t speed, uint32_t strength);
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* _BOARD_H_ */
|
|
@ -0,0 +1,428 @@
|
|||
/*
|
||||
* Copyright 2018-2020,2021 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
/*
|
||||
* How to setup clock using clock driver functions:
|
||||
*
|
||||
* 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
|
||||
*
|
||||
* 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
|
||||
*
|
||||
* 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
|
||||
*
|
||||
* 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
|
||||
*
|
||||
* 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
|
||||
*
|
||||
*/
|
||||
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Clocks v8.0
|
||||
processor: MIMXRT1021xxxxx
|
||||
package_id: MIMXRT1021DAG5A
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 10.0.0
|
||||
board: MIMXRT1020-EVK
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
|
||||
#include "clock_config.h"
|
||||
#include "fsl_iomuxc.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/* System clock frequency. */
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
void BOARD_InitBootClocks(void)
|
||||
{
|
||||
BOARD_BootClockRUN();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
********************** Configuration BOARD_BootClockRUN ***********************
|
||||
******************************************************************************/
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockRUN
|
||||
called_from_default_init: true
|
||||
outputs:
|
||||
- {id: AHB_CLK_ROOT.outFreq, value: 500 MHz}
|
||||
- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
|
||||
- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
|
||||
- {id: CLK_1M.outFreq, value: 1 MHz}
|
||||
- {id: CLK_24M.outFreq, value: 24 MHz}
|
||||
- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
|
||||
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
|
||||
- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
|
||||
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
|
||||
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
|
||||
- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
|
||||
- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
|
||||
- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
|
||||
- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
|
||||
- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
|
||||
- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
|
||||
- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
|
||||
- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
|
||||
- {id: SEMC_CLK_ROOT.outFreq, value: 62.5 MHz}
|
||||
- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
|
||||
- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
|
||||
- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
|
||||
- {id: USDHC1_CLK_ROOT.outFreq, value: 176 MHz}
|
||||
- {id: USDHC2_CLK_ROOT.outFreq, value: 176 MHz}
|
||||
settings:
|
||||
- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
|
||||
- {id: CCM.ARM_PODF.scale, value: '1', locked: true}
|
||||
- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true}
|
||||
- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL2_PFD2_CLK}
|
||||
- {id: CCM.IPG_PODF.scale, value: '4'}
|
||||
- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
|
||||
- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
|
||||
- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM.ARM_PODF}
|
||||
- {id: CCM.SEMC_PODF.scale, value: '8'}
|
||||
- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
|
||||
- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
|
||||
- {id: CCM.USDHC1_PODF.scale, value: '3', locked: true}
|
||||
- {id: CCM.USDHC2_PODF.scale, value: '3', locked: true}
|
||||
- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
|
||||
- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
|
||||
- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
|
||||
- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
|
||||
- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
|
||||
- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
|
||||
- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
|
||||
- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
|
||||
- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
|
||||
- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
|
||||
- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
|
||||
- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
|
||||
- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
|
||||
- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
|
||||
- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
|
||||
- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
|
||||
- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
|
||||
- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
|
||||
- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
|
||||
- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
|
||||
- {id: CCM_ANALOG.PLL4.denom, value: '50'}
|
||||
- {id: CCM_ANALOG.PLL4.div, value: '47'}
|
||||
- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
|
||||
- {id: CCM_ANALOG_PLL_ENET_ENABLE_CFG, value: Disabled}
|
||||
- {id: CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_CFG, value: Disabled}
|
||||
- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
|
||||
sources:
|
||||
- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
|
||||
{
|
||||
.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
|
||||
.numerator = 0, /* 30 bit numerator of fractional loop divider */
|
||||
.denominator = 1, /* 30 bit denominator of fractional loop divider */
|
||||
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
|
||||
};
|
||||
const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
|
||||
{
|
||||
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
|
||||
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
|
||||
};
|
||||
const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN =
|
||||
{
|
||||
.enableClkOutput = false, /* Disable the PLL providing the ENET 125MHz reference clock */
|
||||
.enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */
|
||||
.enableClkOutput25M = false, /* Disable the PLL providing the ENET 25MHz reference clock */
|
||||
.loopDivider = 1, /* Set frequency of ethernet reference clock to 50 MHz */
|
||||
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
|
||||
};
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockRUN(void)
|
||||
{
|
||||
/* Init RTC OSC clock frequency. */
|
||||
CLOCK_SetRtcXtalFreq(32768U);
|
||||
/* Enable 1MHz clock output. */
|
||||
XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
|
||||
/* Use free 1MHz clock output. */
|
||||
XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
|
||||
/* Set XTAL 24MHz clock frequency. */
|
||||
CLOCK_SetXtalFreq(24000000U);
|
||||
/* Enable XTAL 24MHz clock source. */
|
||||
CLOCK_InitExternalClk(0);
|
||||
/* Enable internal RC. */
|
||||
CLOCK_InitRcOsc24M();
|
||||
/* Switch clock source to external OSC. */
|
||||
CLOCK_SwitchOsc(kCLOCK_XtalOsc);
|
||||
/* Set Oscillator ready counter value. */
|
||||
CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
|
||||
/* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
|
||||
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
|
||||
CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
|
||||
/* Setting the VDD_SOC to 1.25V. It is necessary to config AHB to 500Mhz. */
|
||||
DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
|
||||
/* Waiting for DCDC_STS_DC_OK bit is asserted */
|
||||
while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
|
||||
{
|
||||
}
|
||||
/* Set AHB_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
|
||||
/* Disable IPG clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Adc1);
|
||||
CLOCK_DisableClock(kCLOCK_Adc2);
|
||||
CLOCK_DisableClock(kCLOCK_Xbar1);
|
||||
CLOCK_DisableClock(kCLOCK_Xbar2);
|
||||
/* Set IPG_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
|
||||
/* Set ARM_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_ArmDiv, 0);
|
||||
/* Set PERIPH_CLK2_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
|
||||
/* Disable PERCLK clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Gpt1);
|
||||
CLOCK_DisableClock(kCLOCK_Gpt1S);
|
||||
CLOCK_DisableClock(kCLOCK_Gpt2);
|
||||
CLOCK_DisableClock(kCLOCK_Gpt2S);
|
||||
CLOCK_DisableClock(kCLOCK_Pit);
|
||||
/* Set PERCLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
|
||||
/* Disable USDHC1 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Usdhc1);
|
||||
/* Set USDHC1_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Usdhc1Div, 2);
|
||||
/* Set Usdhc1 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
|
||||
/* Disable USDHC2 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Usdhc2);
|
||||
/* Set USDHC2_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Usdhc2Div, 2);
|
||||
/* Set Usdhc2 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
|
||||
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
|
||||
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
|
||||
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
|
||||
#ifndef SKIP_SYSCLK_INIT
|
||||
/* Disable Semc clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Semc);
|
||||
/* Set SEMC_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
|
||||
/* Set Semc alt clock source. */
|
||||
CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
|
||||
/* Set Semc clock source. */
|
||||
CLOCK_SetMux(kCLOCK_SemcMux, 0);
|
||||
#endif
|
||||
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
|
||||
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
|
||||
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
|
||||
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
|
||||
/* Disable Flexspi clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_FlexSpi);
|
||||
/* Set FLEXSPI_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
|
||||
/* Set Flexspi clock source. */
|
||||
CLOCK_SetMux(kCLOCK_FlexspiMux, 2);
|
||||
#endif
|
||||
/* Disable LPSPI clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Lpspi1);
|
||||
CLOCK_DisableClock(kCLOCK_Lpspi2);
|
||||
CLOCK_DisableClock(kCLOCK_Lpspi3);
|
||||
CLOCK_DisableClock(kCLOCK_Lpspi4);
|
||||
/* Set LPSPI_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
|
||||
/* Set Lpspi clock source. */
|
||||
CLOCK_SetMux(kCLOCK_LpspiMux, 2);
|
||||
/* Disable TRACE clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Trace);
|
||||
/* Set TRACE_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
|
||||
/* Set Trace clock source. */
|
||||
CLOCK_SetMux(kCLOCK_TraceMux, 0);
|
||||
/* Disable SAI1 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Sai1);
|
||||
/* Set SAI1_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
|
||||
/* Set SAI1_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
|
||||
/* Set Sai1 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
|
||||
/* Disable SAI2 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Sai2);
|
||||
/* Set SAI2_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
|
||||
/* Set SAI2_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
|
||||
/* Set Sai2 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
|
||||
/* Disable SAI3 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Sai3);
|
||||
/* Set SAI3_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
|
||||
/* Set SAI3_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
|
||||
/* Set Sai3 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
|
||||
/* Disable Lpi2c clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Lpi2c1);
|
||||
CLOCK_DisableClock(kCLOCK_Lpi2c2);
|
||||
CLOCK_DisableClock(kCLOCK_Lpi2c3);
|
||||
/* Set LPI2C_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
|
||||
/* Set Lpi2c clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
|
||||
/* Disable CAN clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Can1);
|
||||
CLOCK_DisableClock(kCLOCK_Can2);
|
||||
CLOCK_DisableClock(kCLOCK_Can1S);
|
||||
CLOCK_DisableClock(kCLOCK_Can2S);
|
||||
/* Set CAN_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_CanDiv, 1);
|
||||
/* Set Can clock source. */
|
||||
CLOCK_SetMux(kCLOCK_CanMux, 2);
|
||||
/* Disable UART clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart1);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart2);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart3);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart4);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart5);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart6);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart7);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart8);
|
||||
/* Set UART_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_UartDiv, 0);
|
||||
/* Set Uart clock source. */
|
||||
CLOCK_SetMux(kCLOCK_UartMux, 0);
|
||||
/* Disable SPDIF clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Spdif);
|
||||
/* Set SPDIF0_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
|
||||
/* Set SPDIF0_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
|
||||
/* Set Spdif clock source. */
|
||||
CLOCK_SetMux(kCLOCK_SpdifMux, 3);
|
||||
/* Disable Flexio1 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Flexio1);
|
||||
/* Set FLEXIO1_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
|
||||
/* Set FLEXIO1_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
|
||||
/* Set Flexio1 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
|
||||
/* Set Pll3 sw clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
|
||||
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
|
||||
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
|
||||
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
|
||||
#ifndef SKIP_SYSCLK_INIT
|
||||
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
|
||||
#warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
|
||||
#endif
|
||||
/* Init System PLL. */
|
||||
CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
|
||||
/* Init System pfd0. */
|
||||
CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
|
||||
/* Init System pfd1. */
|
||||
CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
|
||||
/* Init System pfd2. */
|
||||
CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
|
||||
/* Init System pfd3. */
|
||||
CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
|
||||
#endif
|
||||
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
|
||||
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
|
||||
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
|
||||
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
|
||||
/* Init Usb1 PLL. */
|
||||
CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
|
||||
/* Init Usb1 pfd0. */
|
||||
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
|
||||
/* Init Usb1 pfd1. */
|
||||
CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
|
||||
/* Init Usb1 pfd2. */
|
||||
CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
|
||||
/* Init Usb1 pfd3. */
|
||||
CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
|
||||
/* Disable Usb1 PLL output for USBPHY1. */
|
||||
CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
|
||||
#endif
|
||||
/* DeInit Audio PLL. */
|
||||
CLOCK_DeinitAudioPll();
|
||||
/* Bypass Audio PLL. */
|
||||
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
|
||||
/* Set divider for Audio PLL. */
|
||||
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
|
||||
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
|
||||
/* Enable Audio PLL output. */
|
||||
CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
|
||||
/* Init Enet PLL. */
|
||||
CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
|
||||
/* Set preperiph clock source. */
|
||||
CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
|
||||
/* Set periph clock source. */
|
||||
CLOCK_SetMux(kCLOCK_PeriphMux, 0);
|
||||
/* Set periph clock2 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
|
||||
/* Set per clock source. */
|
||||
CLOCK_SetMux(kCLOCK_PerclkMux, 0);
|
||||
/* Set clock out1 divider. */
|
||||
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
|
||||
/* Set clock out1 source. */
|
||||
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
|
||||
/* Set clock out2 divider. */
|
||||
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
|
||||
/* Set clock out2 source. */
|
||||
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(3);
|
||||
/* Set clock out1 drives clock out1. */
|
||||
CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
|
||||
/* Disable clock out1. */
|
||||
CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
|
||||
/* Disable clock out2. */
|
||||
CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
|
||||
/* Set SAI1 MCLK1 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
|
||||
/* Set SAI1 MCLK2 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
|
||||
/* Set SAI1 MCLK3 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
|
||||
/* Set SAI2 MCLK3 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
|
||||
/* Set SAI3 MCLK3 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
|
||||
/* Set MQS configuration. */
|
||||
IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
|
||||
/* Set ENET Ref clock source. */
|
||||
#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK)
|
||||
IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK;
|
||||
#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
|
||||
/* Backward compatibility for original bitfield name */
|
||||
IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
|
||||
#else
|
||||
#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined."
|
||||
#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */
|
||||
/* Set GPT1 High frequency reference clock source. */
|
||||
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
|
||||
/* Set GPT2 High frequency reference clock source. */
|
||||
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
|
||||
/* Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
|
||||
}
|
|
@ -0,0 +1,114 @@
|
|||
/*
|
||||
* Copyright 2018-2020,2021 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _CLOCK_CONFIG_H_
|
||||
#define _CLOCK_CONFIG_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
|
||||
|
||||
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes default configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootClocks(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
********************** Configuration BOARD_BootClockRUN ***********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */
|
||||
|
||||
/* Clock outputs (values are in Hz): */
|
||||
#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 500000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
|
||||
#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL
|
||||
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL
|
||||
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
|
||||
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 62500000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 176000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 176000000UL
|
||||
|
||||
/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
|
||||
/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
|
||||
/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockRUN(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
#endif /* _CLOCK_CONFIG_H_ */
|
|
@ -0,0 +1,302 @@
|
|||
/*
|
||||
* Copyright 2020-2021 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#include "dcd.h"
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
|
||||
#endif
|
||||
|
||||
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
|
||||
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
|
||||
__attribute__((section(".boot_hdr.dcd_data"), used))
|
||||
#elif defined(__ICCARM__)
|
||||
#pragma location = ".boot_hdr.dcd_data"
|
||||
#endif
|
||||
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: DCDx V2.0
|
||||
processor: MIMXRT1021xxxxx
|
||||
package_id: MIMXRT1021DAG5A
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 9.0.1
|
||||
output_format: c_array
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */
|
||||
const uint8_t dcd_data[] = {
|
||||
/* HEADER */
|
||||
/* Tag */
|
||||
0xD2,
|
||||
/* Image Length */
|
||||
0x03, 0xE0,
|
||||
/* Version */
|
||||
0x41,
|
||||
|
||||
/* COMMANDS */
|
||||
|
||||
/* group: 'Imported Commands' */
|
||||
/* #1.1-107, command header bytes for merged 'Write - value' command */
|
||||
0xCC, 0x03, 0x5C, 0x04,
|
||||
/* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
/* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
/* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
/* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
/* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
/* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
/* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
/* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */
|
||||
0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01,
|
||||
/* #1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x1018101B, size: 4 */
|
||||
0x40, 0x0D, 0x81, 0x00, 0x10, 0x18, 0x10, 0x1B,
|
||||
/* #1.10, command: write_value, address: CCM_CBCDR, value: 0xA8340, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x14, 0x00, 0x0A, 0x83, 0x40,
|
||||
/* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x10, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x10,
|
||||
/* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0x88, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0x8C, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0x90, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0x94, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0x98, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0x9C, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xA0, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xA4, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xA8, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xAC, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xB0, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xB4, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xB8, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xBC, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xC0, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xC4, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xC8, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xCC, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xD0, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xD4, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xD8, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xDC, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xE0, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xE4, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xE8, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xEC, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xF0, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xF4, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xF8, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xFC, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x00, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x04, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x08, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x0C, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x10, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x14, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x18, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x1C, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x20, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x24, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.91, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04,
|
||||
/* #1.92, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81,
|
||||
/* #1.93, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81,
|
||||
/* #1.94, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B,
|
||||
/* #1.95, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B,
|
||||
/* #1.96, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B,
|
||||
/* #1.97, command: write_value, address: SEMC_IOCR, value: 0x7988, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0x88,
|
||||
/* #1.98, command: write_value, address: SEMC_SDRAMCR0, value: 0xF07, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x07,
|
||||
/* #1.99, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22,
|
||||
/* #1.100, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20,
|
||||
/* #1.101, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08,
|
||||
/* #1.102, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21,
|
||||
/* #1.103, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88,
|
||||
/* #1.104, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02,
|
||||
/* #1.105, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.106, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
|
||||
/* #1.107, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F,
|
||||
/* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
|
||||
0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
|
||||
/* #3.1-2, command header bytes for merged 'Write - value' command */
|
||||
0xCC, 0x00, 0x14, 0x04,
|
||||
/* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
|
||||
/* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
|
||||
/* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
|
||||
0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
|
||||
/* #5.1-2, command header bytes for merged 'Write - value' command */
|
||||
0xCC, 0x00, 0x14, 0x04,
|
||||
/* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
|
||||
/* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
|
||||
/* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
|
||||
0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
|
||||
/* #7.1-3, command header bytes for merged 'Write - value' command */
|
||||
0xCC, 0x00, 0x1C, 0x04,
|
||||
/* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x30, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x30,
|
||||
/* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
|
||||
/* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A,
|
||||
/* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
|
||||
0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
|
||||
/* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */
|
||||
0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09
|
||||
};
|
||||
/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */
|
||||
|
||||
#else
|
||||
const uint8_t dcd_data[] = {0x00};
|
||||
#endif /* XIP_BOOT_HEADER_DCD_ENABLE */
|
||||
#endif /* XIP_BOOT_HEADER_ENABLE */
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* Copyright 2020 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef __DCD__
|
||||
#define __DCD__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief XIP_BOARD driver version 2.0.1. */
|
||||
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
|
||||
/*@}*/
|
||||
|
||||
/*************************************
|
||||
* DCD Data
|
||||
*************************************/
|
||||
#define DCD_TAG_HEADER (0xD2)
|
||||
#define DCD_VERSION (0x41)
|
||||
#define DCD_TAG_HEADER_SHIFT (24)
|
||||
#define DCD_ARRAY_SIZE 1
|
||||
|
||||
#endif /* __DCD__ */
|
|
@ -0,0 +1,236 @@
|
|||
/*
|
||||
* Copyright 2018-2020 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
void Clock_Init()
|
||||
{
|
||||
unsigned int reg;
|
||||
// Enable all clocks
|
||||
MEM_WriteU32(0x400FC068,0xffffffff);
|
||||
MEM_WriteU32(0x400FC06C,0xffffffff);
|
||||
MEM_WriteU32(0x400FC070,0xffffffff);
|
||||
MEM_WriteU32(0x400FC074,0xffffffff);
|
||||
MEM_WriteU32(0x400FC078,0xffffffff);
|
||||
MEM_WriteU32(0x400FC07C,0xffffffff);
|
||||
MEM_WriteU32(0x400FC080,0xffffffff);
|
||||
|
||||
// IPG_PODF: 2 divide by 3
|
||||
MEM_WriteU32(0x400FC014,0x000A8200);
|
||||
// PERCLK_PODF: 1 divide by 2
|
||||
MEM_WriteU32(0x400FC01C,0x04900001);
|
||||
// Enable SYS PLL but keep it bypassed.
|
||||
MEM_WriteU32(0x400D8030,0x00012001);
|
||||
do
|
||||
{
|
||||
reg = MEM_ReadU32(0x400D8030);
|
||||
} while((reg & 0x80000000) == 0);
|
||||
// Disable bypass of SYS PLL
|
||||
MEM_WriteU32(0x400D8030,0x00002001);
|
||||
|
||||
// PFD2_FRAC: 24, PLL2 PFD2=528*18/PFD2_FRAC=396
|
||||
// Ungate SYS PLL PFD2
|
||||
reg = MEM_ReadU32(0x400D8100);
|
||||
reg &= ~0xBF0000;
|
||||
reg |= 0x180000;
|
||||
MEM_WriteU32(0x400D8100, reg);
|
||||
|
||||
// SEMC_ALT_CLK_SEL: 0 PLL2 (SYS PLL) PFD2
|
||||
// SEMC_CLK_SEL: 1 SEMC_ALT_CLK
|
||||
// SEMC_PODF: 2 divide by 3
|
||||
reg = MEM_ReadU32(0x400FC014);
|
||||
reg &= ~0x700C0;
|
||||
reg |= 0x20040;
|
||||
MEM_WriteU32(0x400FC014, reg);
|
||||
|
||||
// Disable MPU which will be enabled by ROM to prevent code execution
|
||||
reg = MEM_ReadU32(0xE000ED94);
|
||||
reg &= ~0x1;
|
||||
MEM_WriteU32(0xE000ED94, reg);
|
||||
|
||||
Report("Clock Init Done");
|
||||
}
|
||||
|
||||
void SDRAM_WaitIpCmdDone(void)
|
||||
{
|
||||
unsigned int reg;
|
||||
do
|
||||
{
|
||||
reg = MEM_ReadU32(0x402F003C);
|
||||
}while((reg & 0x3) == 0);
|
||||
}
|
||||
|
||||
void SDRAM_Init() {
|
||||
// Config IOMUX for SDRAM
|
||||
MEM_WriteU32(0x401F8014,0x00000000); // EMC_00
|
||||
MEM_WriteU32(0x401F8018,0x00000000); // EMC_01
|
||||
MEM_WriteU32(0x401F801C,0x00000000); // EMC_02
|
||||
MEM_WriteU32(0x401F8020,0x00000000); // EMC_03
|
||||
MEM_WriteU32(0x401F8024,0x00000000); // EMC_04
|
||||
MEM_WriteU32(0x401F8028,0x00000000); // EMC_05
|
||||
MEM_WriteU32(0x401F802C,0x00000000); // EMC_06
|
||||
MEM_WriteU32(0x401F8030,0x00000000); // EMC_07
|
||||
MEM_WriteU32(0x401F8034,0x00000000); // EMC_08
|
||||
MEM_WriteU32(0x401F8038,0x00000000); // EMC_09
|
||||
MEM_WriteU32(0x401F803C,0x00000000); // EMC_10
|
||||
MEM_WriteU32(0x401F8040,0x00000000); // EMC_11
|
||||
MEM_WriteU32(0x401F8044,0x00000000); // EMC_12
|
||||
MEM_WriteU32(0x401F8048,0x00000000); // EMC_13
|
||||
MEM_WriteU32(0x401F804C,0x00000000); // EMC_14
|
||||
MEM_WriteU32(0x401F8050,0x00000000); // EMC_15
|
||||
MEM_WriteU32(0x401F8054,0x00000000); // EMC_16
|
||||
MEM_WriteU32(0x401F8058,0x00000000); // EMC_17
|
||||
MEM_WriteU32(0x401F805C,0x00000000); // EMC_18
|
||||
MEM_WriteU32(0x401F8060,0x00000000); // EMC_19
|
||||
MEM_WriteU32(0x401F8064,0x00000000); // EMC_20
|
||||
MEM_WriteU32(0x401F8068,0x00000000); // EMC_21
|
||||
MEM_WriteU32(0x401F806C,0x00000000); // EMC_22
|
||||
MEM_WriteU32(0x401F8070,0x00000000); // EMC_23
|
||||
MEM_WriteU32(0x401F8074,0x00000000); // EMC_24
|
||||
MEM_WriteU32(0x401F8078,0x00000000); // EMC_25
|
||||
MEM_WriteU32(0x401F807C,0x00000000); // EMC_26
|
||||
MEM_WriteU32(0x401F8080,0x00000000); // EMC_27
|
||||
MEM_WriteU32(0x401F8084,0x00000010); // EMC_28, DQS PIN, enable SION
|
||||
MEM_WriteU32(0x401F8088,0x00000000); // EMC_29
|
||||
MEM_WriteU32(0x401F808C,0x00000000); // EMC_30
|
||||
MEM_WriteU32(0x401F8090,0x00000000); // EMC_31
|
||||
MEM_WriteU32(0x401F8094,0x00000000); // EMC_32
|
||||
MEM_WriteU32(0x401F8098,0x00000000); // EMC_33
|
||||
MEM_WriteU32(0x401F809C,0x00000000); // EMC_34
|
||||
MEM_WriteU32(0x401F80A0,0x00000000); // EMC_35
|
||||
MEM_WriteU32(0x401F80A4,0x00000000); // EMC_36
|
||||
MEM_WriteU32(0x401F80A8,0x00000000); // EMC_37
|
||||
MEM_WriteU32(0x401F80AC,0x00000000); // EMC_38
|
||||
MEM_WriteU32(0x401F80B0,0x00000000); // EMC_39
|
||||
|
||||
// PAD ctrl
|
||||
// drive strength = 0x7 to increase drive strength
|
||||
// otherwise the data7 bit may fail.
|
||||
MEM_WriteU32(0x401F8188,0x000000F1); // EMC_00
|
||||
MEM_WriteU32(0x401F818C,0x000000F1); // EMC_01
|
||||
MEM_WriteU32(0x401F8190,0x000000F1); // EMC_02
|
||||
MEM_WriteU32(0x401F8194,0x000000F1); // EMC_03
|
||||
MEM_WriteU32(0x401F8198,0x000000F1); // EMC_04
|
||||
MEM_WriteU32(0x401F819C,0x000000F1); // EMC_05
|
||||
MEM_WriteU32(0x401F81A0,0x000000F1); // EMC_06
|
||||
MEM_WriteU32(0x401F81A4,0x000000F1); // EMC_07
|
||||
MEM_WriteU32(0x401F81A8,0x000000F1); // EMC_08
|
||||
MEM_WriteU32(0x401F81AC,0x000000F1); // EMC_09
|
||||
MEM_WriteU32(0x401F81B0,0x000000F1); // EMC_10
|
||||
MEM_WriteU32(0x401F81B4,0x000000F1); // EMC_11
|
||||
MEM_WriteU32(0x401F81B8,0x000000F1); // EMC_12
|
||||
MEM_WriteU32(0x401F81BC,0x000000F1); // EMC_13
|
||||
MEM_WriteU32(0x401F81C0,0x000000F1); // EMC_14
|
||||
MEM_WriteU32(0x401F81C4,0x000000F1); // EMC_15
|
||||
MEM_WriteU32(0x401F81C8,0x000000F1); // EMC_16
|
||||
MEM_WriteU32(0x401F81CC,0x000000F1); // EMC_17
|
||||
MEM_WriteU32(0x401F81D0,0x000000F1); // EMC_18
|
||||
MEM_WriteU32(0x401F81D4,0x000000F1); // EMC_19
|
||||
MEM_WriteU32(0x401F81D8,0x000000F1); // EMC_20
|
||||
MEM_WriteU32(0x401F81DC,0x000000F1); // EMC_21
|
||||
MEM_WriteU32(0x401F81E0,0x000000F1); // EMC_22
|
||||
MEM_WriteU32(0x401F81E4,0x000000F1); // EMC_23
|
||||
MEM_WriteU32(0x401F81E8,0x000000F1); // EMC_24
|
||||
MEM_WriteU32(0x401F81EC,0x000000F1); // EMC_25
|
||||
MEM_WriteU32(0x401F81F0,0x000000F1); // EMC_26
|
||||
MEM_WriteU32(0x401F81F4,0x000000F1); // EMC_27
|
||||
MEM_WriteU32(0x401F81F8,0x000000F1); // EMC_28
|
||||
MEM_WriteU32(0x401F81FC,0x000000F1); // EMC_29
|
||||
MEM_WriteU32(0x401F8200,0x000000F1); // EMC_30
|
||||
MEM_WriteU32(0x401F8204,0x000000F1); // EMC_31
|
||||
MEM_WriteU32(0x401F8208,0x000000F1); // EMC_32
|
||||
MEM_WriteU32(0x401F820C,0x000000F1); // EMC_33
|
||||
MEM_WriteU32(0x401F8210,0x000000F1); // EMC_34
|
||||
MEM_WriteU32(0x401F8214,0x000000F1); // EMC_35
|
||||
MEM_WriteU32(0x401F8218,0x000000F1); // EMC_36
|
||||
MEM_WriteU32(0x401F821C,0x000000F1); // EMC_37
|
||||
MEM_WriteU32(0x401F8220,0x000000F1); // EMC_38
|
||||
MEM_WriteU32(0x401F8224,0x000000F1); // EMC_39
|
||||
|
||||
// Config SDR Controller Registers/
|
||||
MEM_WriteU32(0x402F0000,0x10000004); // MCR
|
||||
MEM_WriteU32(0x402F0008,0x00000081); // BMCR0
|
||||
MEM_WriteU32(0x402F000C,0x00000081); // BMCR1
|
||||
MEM_WriteU32(0x402F0010,0x8000001B); // BR0, 32MB
|
||||
MEM_WriteU32(0x402F0014,0x8200001B); // BR1, 32MB
|
||||
MEM_WriteU32(0x402F0018,0x8400001B); // BR2, 32MB
|
||||
MEM_WriteU32(0x402F001C,0x8600001B); // BR3, 32MB
|
||||
MEM_WriteU32(0x402F0020,0x90000021); // BR4,
|
||||
MEM_WriteU32(0x402F0024,0xA0000019); // BR5,
|
||||
MEM_WriteU32(0x402F0028,0xA8000017); // BR6,
|
||||
MEM_WriteU32(0x402F002C,0xA900001B); // BR7,
|
||||
MEM_WriteU32(0x402F0030,0x00000021); // BR8,
|
||||
MEM_WriteU32(0x402F0004,0x000079A8); //IOCR,SEMC_CCSX0 as NOR CE, SEMC_CSX1 as PSRAM CE, SEMC_CSX2 as NAND CE, SEMC_CSX3 as DBI CE.
|
||||
|
||||
// MEM_WriteU32(0x402F0004,0x00000008); // IOCR, SEMC_CCSX0 as SDRAM_CS1
|
||||
MEM_WriteU32(0x402F0040,0x00000F31); // SDRAMCR0
|
||||
MEM_WriteU32(0x402F0044,0x00652922); // SDRAMCR1
|
||||
MEM_WriteU32(0x402F0048,0x00010920); // SDRAMCR2
|
||||
MEM_WriteU32(0x402F004C,0x50210A09); // SDRAMCR3
|
||||
|
||||
MEM_WriteU32(0x402F0080,0x00000021); // DBICR0
|
||||
MEM_WriteU32(0x402F0084,0x00888888); // DBICR1
|
||||
MEM_WriteU32(0x402F0094,0x00000002); // IPCR1
|
||||
MEM_WriteU32(0x402F0098,0x00000000); // IPCR2
|
||||
|
||||
MEM_WriteU32(0x402F0090,0x80000000); // IPCR0
|
||||
MEM_WriteU32(0x402F009C,0xA55A000F); // IPCMD, SD_CC_IPREA
|
||||
SDRAM_WaitIpCmdDone();
|
||||
MEM_WriteU32(0x402F0090,0x80000000); // IPCR0
|
||||
MEM_WriteU32(0x402F009C,0xA55A000C); // SD_CC_IAF
|
||||
SDRAM_WaitIpCmdDone();
|
||||
MEM_WriteU32(0x402F0090,0x80000000); // IPCR0
|
||||
MEM_WriteU32(0x402F009C,0xA55A000C); // SD_CC_IAF
|
||||
SDRAM_WaitIpCmdDone();
|
||||
MEM_WriteU32(0x402F00A0,0x00000033); // IPTXDAT
|
||||
MEM_WriteU32(0x402F0090,0x80000000); // IPCR0
|
||||
MEM_WriteU32(0x402F009C,0xA55A000A); // SD_CC_IMS
|
||||
SDRAM_WaitIpCmdDone();
|
||||
MEM_WriteU32(0x402F004C,0x50210A09 ); // enable sdram self refresh again after initialization done.
|
||||
|
||||
Report("SDRAM Init Done");
|
||||
}
|
||||
|
||||
void RestoreFlexRAM()
|
||||
{
|
||||
unsigned int base;
|
||||
unsigned int value;
|
||||
|
||||
base = 0x400AC000;
|
||||
|
||||
value = MEM_ReadU32(base + 0x44);
|
||||
value &= ~(0xFFFF);
|
||||
value |= 0x5FA5;
|
||||
MEM_WriteU32(base + 0x44, value);
|
||||
|
||||
value = MEM_ReadU32(base + 0x40);
|
||||
value |= (1 << 2);
|
||||
MEM_WriteU32(base + 0x40, value);
|
||||
Report("FlexRAM configuration is restored");
|
||||
}
|
||||
|
||||
/* ConfigTarget */
|
||||
void ConfigTargetSettings(void)
|
||||
{
|
||||
Report("Config JTAG Speed to 4000kHz");
|
||||
JTAG_Speed = 4000;
|
||||
}
|
||||
|
||||
/* SetupTarget */
|
||||
void SetupTarget(void) {
|
||||
|
||||
Report("Enabling i.MXRT SDRAM");
|
||||
RestoreFlexRAM();
|
||||
Clock_Init();
|
||||
SDRAM_Init();
|
||||
}
|
||||
|
||||
/* AfterResetTarget */
|
||||
void AfterResetTarget(void) {
|
||||
|
||||
RestoreFlexRAM();
|
||||
Clock_Init();
|
||||
SDRAM_Init();
|
||||
}
|
|
@ -0,0 +1,115 @@
|
|||
/*
|
||||
* Copyright 2018 ,2021 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Pins v9.0
|
||||
processor: MIMXRT1021xxxxx
|
||||
package_id: MIMXRT1021DAG5A
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 9.0.1
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_iomuxc.h"
|
||||
#include "pin_mux.h"
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitBootPins
|
||||
* Description : Calls initialization functions.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitBootPins(void) {
|
||||
BOARD_InitPins();
|
||||
}
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitPins:
|
||||
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: '101', peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_07, slew_rate: Slow, software_input_on: Disable, open_drain: Disable, speed: MHZ_100,
|
||||
drive_strength: R0_6, pull_keeper_select: Keeper, pull_keeper_enable: Enable, pull_up_down_config: Pull_Down_100K_Ohm, hysteresis_enable: Disable}
|
||||
- {pin_num: '105', peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_06, slew_rate: Slow, software_input_on: Disable, open_drain: Disable, speed: MHZ_100,
|
||||
drive_strength: R0_6, pull_keeper_select: Keeper, pull_keeper_enable: Enable, pull_up_down_config: Pull_Down_100K_Ohm, hysteresis_enable: Disable}
|
||||
- {pin_num: '98', peripheral: ENET, signal: 'enet_rx_data, 0', pin_signal: GPIO_AD_B0_10, slew_rate: Fast, software_input_on: Disable, open_drain: Disable, speed: MHZ_200,
|
||||
drive_strength: R0_5, pull_keeper_select: Pull, pull_keeper_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, hysteresis_enable: Disable}
|
||||
- {pin_num: '99', peripheral: ENET, signal: 'enet_rx_data, 1', pin_signal: GPIO_AD_B0_09, slew_rate: Fast, software_input_on: Disable, open_drain: Disable, speed: MHZ_200,
|
||||
drive_strength: R0_5, pull_keeper_select: Pull, pull_keeper_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, hysteresis_enable: Disable}
|
||||
- {pin_num: '97', peripheral: ENET, signal: enet_rx_en, pin_signal: GPIO_AD_B0_11, slew_rate: Fast, software_input_on: Disable, open_drain: Disable, speed: MHZ_200,
|
||||
drive_strength: R0_5, pull_keeper_select: Pull, pull_keeper_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, hysteresis_enable: Disable}
|
||||
- {pin_num: '94', peripheral: ENET, signal: 'enet_tx_data, 0', pin_signal: GPIO_AD_B0_14, slew_rate: Fast, software_input_on: Disable, open_drain: Disable, speed: MHZ_200,
|
||||
drive_strength: R0_5, pull_keeper_select: Pull, pull_keeper_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, hysteresis_enable: Disable}
|
||||
- {pin_num: '93', peripheral: ENET, signal: 'enet_tx_data, 1', pin_signal: GPIO_AD_B0_15, slew_rate: Fast, software_input_on: Disable, open_drain: Disable, speed: MHZ_200,
|
||||
drive_strength: R0_5, pull_keeper_select: Pull, pull_keeper_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, hysteresis_enable: Disable}
|
||||
- {pin_num: '95', peripheral: ENET, signal: enet_tx_en, pin_signal: GPIO_AD_B0_13, slew_rate: Fast, software_input_on: Disable, open_drain: Disable, speed: MHZ_200,
|
||||
drive_strength: R0_5, pull_keeper_select: Pull, pull_keeper_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, hysteresis_enable: Disable}
|
||||
- {pin_num: '100', peripheral: ENET, signal: enet_ref_clk, pin_signal: GPIO_AD_B0_08, slew_rate: Fast, software_input_on: Enable, open_drain: Disable, speed: MHZ_200,
|
||||
drive_strength: R0_5, pull_keeper_select: Pull, pull_keeper_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, hysteresis_enable: Disable}
|
||||
- {pin_num: '96', peripheral: ENET, signal: enet_rx_er, pin_signal: GPIO_AD_B0_12, slew_rate: Fast, software_input_on: Disable, open_drain: Disable, speed: MHZ_200,
|
||||
drive_strength: R0_5, pull_keeper_select: Pull, pull_keeper_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, hysteresis_enable: Disable}
|
||||
- {pin_num: '116', peripheral: ENET, signal: enet_mdio, pin_signal: GPIO_EMC_40, slew_rate: Fast, software_input_on: Disable, open_drain: Disable, speed: MHZ_200,
|
||||
drive_strength: R0_5, pull_keeper_select: Pull, pull_keeper_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, hysteresis_enable: Disable}
|
||||
- {pin_num: '115', peripheral: ENET, signal: enet_mdc, pin_signal: GPIO_EMC_41, slew_rate: Fast, software_input_on: Disable, open_drain: Disable, speed: MHZ_200,
|
||||
drive_strength: R0_5, pull_keeper_select: Pull, pull_keeper_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, hysteresis_enable: Disable}
|
||||
- {pin_num: '107', peripheral: GPIO1, signal: 'gpio_io, 04', pin_signal: GPIO_AD_B0_04, slew_rate: Fast, software_input_on: Disable, open_drain: Disable, speed: MHZ_100,
|
||||
drive_strength: R0_5, pull_keeper_select: Pull, pull_keeper_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, hysteresis_enable: Disable}
|
||||
- {pin_num: '84', peripheral: GPIO1, signal: 'gpio_io, 22', pin_signal: GPIO_AD_B1_06, slew_rate: Fast, software_input_on: Disable, open_drain: Disable, speed: MHZ_100,
|
||||
drive_strength: R0_5, pull_keeper_select: Pull, pull_keeper_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, hysteresis_enable: Disable}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitPins(void) {
|
||||
CLOCK_EnableClock(kCLOCK_Iomuxc);
|
||||
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_04_GPIO1_IO04, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_06_LPUART1_TX, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK1, 1U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_ENET_RDATA01, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_10_ENET_RDATA00, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_11_ENET_RX_EN, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_ENET_RX_ER, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_ENET_TX_EN, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_14_ENET_TDATA00, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_15_ENET_TDATA01, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_GPIO1_IO22, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_ENET_MDIO, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDC, 0U);
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_04_GPIO1_IO04, 0xB0A9U);
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_06_LPUART1_TX, 0x10B0U);
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0x10B0U);
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK1, 0xB0E9U);
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_ENET_RDATA01, 0xB0E9U);
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_10_ENET_RDATA00, 0xB0E9U);
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_11_ENET_RX_EN, 0xB0E9U);
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_ENET_RX_ER, 0xB0E9U);
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_ENET_TX_EN, 0xB0E9U);
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_14_ENET_TDATA00, 0xB0E9U);
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_15_ENET_TDATA01, 0xB0E9U);
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_06_GPIO1_IO22, 0xB0A9U);
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_40_ENET_MDIO, 0xB0E9U);
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_41_ENET_MDC, 0xB0E9U);
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
|
@ -0,0 +1,65 @@
|
|||
/*
|
||||
* Copyright 2018 ,2021 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef _PIN_MUX_H_
|
||||
#define _PIN_MUX_H_
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*! @brief Direction type */
|
||||
typedef enum _pin_mux_direction
|
||||
{
|
||||
kPIN_MUX_DirectionInput = 0U, /* Input direction */
|
||||
kPIN_MUX_DirectionOutput = 1U, /* Output direction */
|
||||
kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
|
||||
} pin_mux_direction_t;
|
||||
|
||||
/*!
|
||||
* @addtogroup pin_mux
|
||||
* @{
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* API
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Calls initialization functions.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootPins(void);
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitPins(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @}
|
||||
*/
|
||||
#endif /* _PIN_MUX_H_ */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
|
@ -0,0 +1,106 @@
|
|||
Overview
|
||||
========
|
||||
This example demonstrates how to use the Simple Open EtherCAT Master (SOEM) Library to communicate with EhterCAT devices.
|
||||
|
||||
In this example there are three EhterCAT devices, one EtherCAT Coupler EK1100, one EtherCAT Terminal EL2008 (slave0),
|
||||
and one EtherCAT Terminal EL1018 (slave1).
|
||||
|
||||
This example controls a stepper motor system using two outputs and one input remote IO:
|
||||
Outputs:
|
||||
-Pluse: The pulse signal with the period of 200us and the duty cycle of 50%.
|
||||
-Dir: The direction signal.
|
||||
Inputs:
|
||||
-Limit signal: This signal comes from the Limit Switchs on the stepper motor system.
|
||||
The Dir signal changes once when one of the Limit Switchs has been touched.
|
||||
|
||||
|
||||
Toolchain supported
|
||||
===================
|
||||
- IAR embedded Workbench 9.30.1
|
||||
- Keil MDK 5.37
|
||||
- GCC ARM Embedded 10.3.1
|
||||
- MCUXpresso 11.6.0
|
||||
|
||||
Hardware requirements
|
||||
=====================
|
||||
- Mini/micro USB cable
|
||||
- Network cable RJ45 standard
|
||||
- EVK-MIMXRT1020 board
|
||||
- One BECKHOFF EK1100 EtherCAT Coupler
|
||||
- Personal Computer
|
||||
|
||||
Board settings
|
||||
==============
|
||||
No special settings are required.
|
||||
|
||||
Prepare the Demo
|
||||
================
|
||||
1. Connect a USB cable between the host PC and the OpenSDA USB port on the target board.
|
||||
2. Power up the EtherCAT Coupler and connect it to the target board via an Ethernet Cable.
|
||||
3. Open a serial terminal with the following settings:
|
||||
- 115200 baud rate
|
||||
- 8 data bits
|
||||
- No parity
|
||||
- One stop bit
|
||||
- No flow control
|
||||
4. Write the program to the flash of the target board.
|
||||
5. Press the reset button on your board to start the demo.
|
||||
|
||||
Running the demo
|
||||
================
|
||||
If the test passes, the led2 of slave0 lights up at 50% brightness.
|
||||
|
||||
If the stepper motor system is not setup properly, you can get information from
|
||||
the console log and the led4 status of slave0.
|
||||
|
||||
When the demo is running, the serial port will output:
|
||||
|
||||
|
||||
Start the soem_gpio_pulse baremetal example...
|
||||
|
||||
ec_init on enet0 succeeded.
|
||||
|
||||
ec_config_init 0
|
||||
3 slaves found and configured.
|
||||
|
||||
ec_config_map_group IOmap:80000089 group:0
|
||||
>Slave 1, configadr 1001, state 12
|
||||
>Slave 2, configadr 1002, state 12
|
||||
>Slave 3, configadr 1003, state 12
|
||||
SII Isize:0
|
||||
SII Osize:0
|
||||
ISIZE:0 0 OSIZE:0
|
||||
SM programming
|
||||
SII Isize:0
|
||||
SII Osize:8
|
||||
SM0 length 8
|
||||
ISIZE:0 0 OSIZE:8
|
||||
SM programming
|
||||
SM0 Type:3 StartAddr: f00 Flags: 90044
|
||||
SII Isize:8
|
||||
SM0 length 8
|
||||
SII Osize:0
|
||||
ISIZE:8 8 OSIZE:0
|
||||
SM programming
|
||||
SM0 Type:4 StartAddr:1000 Flags: 10000
|
||||
OUTPUT MAPPING
|
||||
FMMU 0
|
||||
SM0
|
||||
slave 2 Outputs 80000089 startbit 0
|
||||
=Slave 3, INPUT MAPPING
|
||||
FMMU 0
|
||||
SM0
|
||||
Inputs 8000008A startbit 0
|
||||
IOmapSize 2
|
||||
Slaves mapped, state to SAFE_OP.
|
||||
|
||||
oloop = 1, iloop = 1
|
||||
|
||||
segments : 1 : 2 0 0 0
|
||||
|
||||
Request operational state for all slaves
|
||||
|
||||
Calculated workcounter 3
|
||||
|
||||
Operational state reached for all slaves.
|
||||
|
|
@ -0,0 +1,371 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Includes
|
||||
******************************************************************************/
|
||||
#include <stdlib.h>
|
||||
#include <stdio.h>
|
||||
|
||||
#include "pin_mux.h"
|
||||
#include "clock_config.h"
|
||||
#include "board.h"
|
||||
#include "fsl_gpio.h"
|
||||
#include "fsl_iomuxc.h"
|
||||
#include "fsl_gpt.h"
|
||||
#include "fsl_enet_mdio.h"
|
||||
#include "fsl_phyksz8081.h"
|
||||
#include "fsl_debug_console.h"
|
||||
|
||||
#include "ethercattype.h"
|
||||
#include "nicdrv.h"
|
||||
#include "ethercatbase.h"
|
||||
#include "ethercatmain.h"
|
||||
#include "ethercatdc.h"
|
||||
#include "ethercatcoe.h"
|
||||
#include "ethercatfoe.h"
|
||||
#include "ethercatconfig.h"
|
||||
#include "ethercatprint.h"
|
||||
#include "enet/soem_enet.h"
|
||||
#include "soem_port.h"
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef PHY_AUTONEGO_TIMEOUT_COUNT
|
||||
#define PHY_AUTONEGO_TIMEOUT_COUNT (100000)
|
||||
#endif
|
||||
|
||||
#ifndef PHY_STABILITY_DELAY_US
|
||||
#define PHY_STABILITY_DELAY_US (0U)
|
||||
#endif
|
||||
|
||||
/*! @brief GPT timer will be used to calculate the system time and delay */
|
||||
#define OSAL_TIMER_IRQ_ID GPT2_IRQn
|
||||
#define OSAL_TIMER GPT2
|
||||
#define OSAL_TIMER_IRQHandler GPT2_IRQHandler
|
||||
#define OSAL_TIMER_CLK_FREQ CLOCK_GetFreq(kCLOCK_PerClk)
|
||||
|
||||
|
||||
#define NUM_1M (1000000UL)
|
||||
#define SOEM_PERIOD NUM_1M /* 1 second */
|
||||
|
||||
#define OSEM_PORT_NAME "enet0"
|
||||
|
||||
#define ENET_RXBD_NUM (4)
|
||||
#define ENET_TXBD_NUM (4)
|
||||
|
||||
#define ENET_RXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN)
|
||||
#define ENET_TXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN)
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
static struct enet_if_port if_port;
|
||||
|
||||
static uint32_t timer_irq_period = 0; /* unit: microsecond*/
|
||||
|
||||
volatile struct timeval system_time_base =
|
||||
{
|
||||
.tv_sec = 0,
|
||||
.tv_usec = 0
|
||||
};
|
||||
|
||||
|
||||
/*! @brief Buffer descriptors should be in non-cacheable region and should be align to "ENET_BUFF_ALIGNMENT". */
|
||||
AT_NONCACHEABLE_SECTION_ALIGN(static enet_rx_bd_struct_t g_rxBuffDescrip[ENET_RXBD_NUM], ENET_BUFF_ALIGNMENT);
|
||||
AT_NONCACHEABLE_SECTION_ALIGN(static enet_tx_bd_struct_t g_txBuffDescrip[ENET_TXBD_NUM], ENET_BUFF_ALIGNMENT);
|
||||
|
||||
/*! @brief The data buffers can be in cacheable region or in non-cacheable region.
|
||||
* If use cacheable region, the alignment size should be the maximum size of "CACHE LINE SIZE" and "ENET_BUFF_ALIGNMENT"
|
||||
* If use non-cache region, the alignment size is the "ENET_BUFF_ALIGNMENT".
|
||||
*/
|
||||
AT_NONCACHEABLE_SECTION_ALIGN(static uint8_t g_rxDataBuff[ENET_RXBD_NUM][SDK_SIZEALIGN(ENET_RXBUFF_SIZE, ENET_BUFF_ALIGNMENT)],
|
||||
ENET_BUFF_ALIGNMENT);
|
||||
AT_NONCACHEABLE_SECTION_ALIGN(static uint8_t g_txDataBuff[ENET_TXBD_NUM][SDK_SIZEALIGN(ENET_TXBUFF_SIZE, ENET_BUFF_ALIGNMENT)],
|
||||
ENET_BUFF_ALIGNMENT);
|
||||
|
||||
static enet_buffer_config_t buffConfig[] = {{
|
||||
ENET_RXBD_NUM,
|
||||
ENET_TXBD_NUM,
|
||||
SDK_SIZEALIGN(ENET_RXBUFF_SIZE, ENET_BUFF_ALIGNMENT),
|
||||
SDK_SIZEALIGN(ENET_TXBUFF_SIZE, ENET_BUFF_ALIGNMENT),
|
||||
&g_rxBuffDescrip[0],
|
||||
&g_txBuffDescrip[0],
|
||||
&g_rxDataBuff[0][0],
|
||||
&g_txDataBuff[0][0],
|
||||
true,
|
||||
true,
|
||||
NULL,
|
||||
}};
|
||||
|
||||
static char IOmap[100];
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
void irq_wake_task(void);
|
||||
|
||||
void BOARD_InitModuleClock(void)
|
||||
{
|
||||
const clock_enet_pll_config_t config = {
|
||||
.enableClkOutput = true,
|
||||
.enableClkOutput25M = false,
|
||||
.loopDivider = 1,
|
||||
};
|
||||
CLOCK_InitEnetPll(&config);
|
||||
}
|
||||
|
||||
|
||||
void OSAL_TIMER_IRQHandler(void)
|
||||
{
|
||||
/* Clear interrupt flag. */
|
||||
GPT_ClearStatusFlags(OSAL_TIMER, kGPT_OutputCompare1Flag);
|
||||
|
||||
system_time_base.tv_usec += timer_irq_period;
|
||||
|
||||
if (system_time_base.tv_usec >= NUM_1M)
|
||||
{
|
||||
system_time_base.tv_sec += system_time_base.tv_usec / NUM_1M;
|
||||
system_time_base.tv_usec = system_time_base.tv_usec % NUM_1M;
|
||||
}
|
||||
|
||||
irq_wake_task();
|
||||
|
||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F, Cortex-M7, Cortex-M7F
|
||||
* Store immediate overlapping
|
||||
* exception return operation might vector to incorrect interrupt
|
||||
*/
|
||||
SDK_ISR_EXIT_BARRIER;
|
||||
}
|
||||
|
||||
static void osal_timer_init(uint32_t usec, uint32_t priority)
|
||||
{
|
||||
uint32_t gptFreq;
|
||||
gpt_config_t gptConfig;
|
||||
|
||||
assert(usec != 0);
|
||||
assert(priority < (1UL << __NVIC_PRIO_BITS));
|
||||
|
||||
timer_irq_period = usec;
|
||||
GPT_GetDefaultConfig(&gptConfig);
|
||||
GPT_Init(OSAL_TIMER, &gptConfig);
|
||||
gptFreq = OSAL_TIMER_CLK_FREQ;
|
||||
/* Divide GPT clock source frequency to 1MHz */
|
||||
GPT_SetClockDivider(OSAL_TIMER, gptFreq / NUM_1M);
|
||||
/* Set both GPT modules to 1 second duration */
|
||||
GPT_SetOutputCompareValue(OSAL_TIMER, kGPT_OutputCompare_Channel1, timer_irq_period);
|
||||
/* Enable GPT Output Compare1 interrupt */
|
||||
GPT_EnableInterrupts(OSAL_TIMER, kGPT_OutputCompare1InterruptEnable);
|
||||
/* Enable at the Interrupt */
|
||||
NVIC_SetPriority(OSAL_TIMER_IRQ_ID, priority);
|
||||
EnableIRQ(OSAL_TIMER_IRQ_ID);
|
||||
GPT_StartTimer(OSAL_TIMER);
|
||||
}
|
||||
|
||||
void osal_gettime(struct timeval *current_time)
|
||||
{
|
||||
uint32_t usec_base;
|
||||
uint32_t cur_usec;
|
||||
uint32_t usec_again;
|
||||
|
||||
usec_base = system_time_base.tv_usec;
|
||||
cur_usec = GPT_GetCurrentTimerCount(OSAL_TIMER);
|
||||
usec_again = system_time_base.tv_usec;
|
||||
|
||||
if (usec_again != usec_base)
|
||||
{
|
||||
usec_base = system_time_base.tv_usec;
|
||||
cur_usec = GPT_GetCurrentTimerCount(OSAL_TIMER);
|
||||
}
|
||||
|
||||
current_time->tv_sec = system_time_base.tv_sec;
|
||||
current_time->tv_usec = usec_base + cur_usec;
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/* OSHW: register enet port to SOEM stack */
|
||||
static int if_port_init(void)
|
||||
{
|
||||
memset(&if_port, 0, sizeof(if_port));
|
||||
if_port.mdioHandle.ops = &enet_ops;
|
||||
if_port.phyHandle.ops = &phyksz8081_ops;
|
||||
if_port.bufferConfig = buffConfig;
|
||||
if_port.base = ENET;
|
||||
/* The miiMode should be set according to the different PHY interfaces. */
|
||||
if_port.mii_mode = kENET_RmiiMode;
|
||||
if_port.phy_config.autoNeg = true;
|
||||
if_port.phy_config.phyAddr = 0x02U;
|
||||
if_port.srcClock_Hz = CLOCK_GetFreq(kCLOCK_IpgClk);
|
||||
if_port.phy_autonego_timeout_count = PHY_AUTONEGO_TIMEOUT_COUNT;
|
||||
if_port.phy_stability_delay_us = PHY_STABILITY_DELAY_US;
|
||||
|
||||
return register_soem_port(OSEM_PORT_NAME, "enet", &if_port);
|
||||
}
|
||||
|
||||
|
||||
void irq_wake_task(void)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
void control_task(char *ifname)
|
||||
{
|
||||
int oloop, iloop;
|
||||
int expectedWKC;
|
||||
volatile int wkc;
|
||||
int old_switch0 = 0;
|
||||
int old_switch1 = 0;
|
||||
struct timeval current_time;
|
||||
struct timeval sleep_time;
|
||||
struct timeval target_time;
|
||||
struct timeval last_time;
|
||||
struct timeval diff_time;
|
||||
sleep_time.tv_sec = 0;
|
||||
sleep_time.tv_usec = 125;
|
||||
|
||||
/* initialise SOEM, and if_port */
|
||||
if (ec_init(ifname))
|
||||
{
|
||||
PRINTF("ec_init on %s succeeded.\r\n", ifname);
|
||||
if (ec_config_init(FALSE) > 0)
|
||||
{
|
||||
PRINTF("%d slaves found and configured.\r\n", ec_slavecount);
|
||||
ec_config_map(&IOmap);
|
||||
ec_configdc();
|
||||
PRINTF("Slaves mapped, state to SAFE_OP.\r\n");
|
||||
/* wait for all slaves to reach SAFE_OP state */
|
||||
ec_statecheck(0, EC_STATE_SAFE_OP, EC_TIMEOUTSTATE * 4);
|
||||
oloop = ec_slave[2].Obytes;
|
||||
iloop = ec_slave[3].Ibytes;
|
||||
PRINTF("oloop = %d, iloop = %d\r\n", oloop, iloop);
|
||||
PRINTF("segments : %d : %d %d %d %d\r\n", ec_group[0].nsegments, ec_group[0].IOsegment[0],
|
||||
ec_group[0].IOsegment[1], ec_group[0].IOsegment[2], ec_group[0].IOsegment[3]);
|
||||
|
||||
PRINTF("Request operational state for all slaves\r\n");
|
||||
expectedWKC = (ec_group[0].outputsWKC * 2) + ec_group[0].inputsWKC;
|
||||
PRINTF("Calculated workcounter %d\r\n", expectedWKC);
|
||||
ec_slave[0].state = EC_STATE_OPERATIONAL;
|
||||
/* send one valid process data to make outputs in slaves happy*/
|
||||
ec_send_processdata();
|
||||
ec_receive_processdata(EC_TIMEOUTRET);
|
||||
/* request OP state for all slaves */
|
||||
ec_writestate(0);
|
||||
char chk = 40;
|
||||
/* wait for all slaves to reach OP state */
|
||||
do
|
||||
{
|
||||
ec_send_processdata();
|
||||
ec_receive_processdata(EC_TIMEOUTRET);
|
||||
ec_statecheck(0, EC_STATE_OPERATIONAL, 50000);
|
||||
} while (chk-- && (ec_slave[0].state != EC_STATE_OPERATIONAL));
|
||||
PRINTF("Operational state reached for all slaves.\r\n");
|
||||
/* cyclic loop */
|
||||
int is_expired;
|
||||
osal_gettime(&last_time);
|
||||
while (1)
|
||||
{
|
||||
osal_gettime(¤t_time);
|
||||
timeradd(¤t_time, &sleep_time, &target_time);
|
||||
ec_send_processdata();
|
||||
wkc = ec_receive_processdata(EC_TIMEOUTRET);
|
||||
if (wkc >= expectedWKC)
|
||||
{
|
||||
if ((*(ec_slave[3].inputs) & 0x01) && old_switch0 == 0)
|
||||
{
|
||||
if (*(ec_slave[2].outputs) & 0x04)
|
||||
*(ec_slave[2].outputs) &= ~0x04;
|
||||
else
|
||||
*(ec_slave[2].outputs) |= 0x04;
|
||||
}
|
||||
|
||||
if ((*(ec_slave[3].inputs) & 0x02) && old_switch1 == 0)
|
||||
{
|
||||
if (*(ec_slave[2].outputs) & 0x04)
|
||||
*(ec_slave[2].outputs) &= ~0x04;
|
||||
else
|
||||
*(ec_slave[2].outputs) |= 0x04;
|
||||
}
|
||||
|
||||
old_switch0 = *(ec_slave[3].inputs) & 0x01;
|
||||
old_switch1 = *(ec_slave[3].inputs) & 0x02;
|
||||
if (*(ec_slave[2].outputs) & 0x02)
|
||||
*(ec_slave[2].outputs) &= ~0x02;
|
||||
else
|
||||
*(ec_slave[2].outputs) |= 0x02;
|
||||
}
|
||||
osal_gettime(¤t_time);
|
||||
timersub(¤t_time, &last_time, &diff_time);
|
||||
is_expired = timercmp(&target_time, ¤t_time, <=);
|
||||
if (diff_time.tv_usec > 130)
|
||||
{
|
||||
last_time.tv_usec = current_time.tv_usec;
|
||||
}
|
||||
last_time.tv_usec = current_time.tv_usec;
|
||||
last_time.tv_sec = current_time.tv_sec;
|
||||
if (!is_expired)
|
||||
{
|
||||
timersub(&target_time, ¤t_time, &sleep_time);
|
||||
osal_usleep(sleep_time.tv_usec);
|
||||
sleep_time.tv_usec = 125;
|
||||
}
|
||||
else
|
||||
{
|
||||
while (1)
|
||||
;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Main function
|
||||
*/
|
||||
int main(void)
|
||||
{
|
||||
gpio_pin_config_t gpio_config = {
|
||||
kGPIO_DigitalOutput,
|
||||
0,
|
||||
kGPIO_NoIntmode
|
||||
};
|
||||
|
||||
BOARD_ConfigMPU();
|
||||
BOARD_InitBootPins();
|
||||
BOARD_InitBootClocks();
|
||||
BOARD_InitDebugConsole();
|
||||
BOARD_InitModuleClock();
|
||||
|
||||
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true);
|
||||
|
||||
GPIO_PinInit(GPIO1, 9, &gpio_config);
|
||||
GPIO_PinInit(GPIO1, 10, &gpio_config);
|
||||
/* pull up the ENET_INT before RESET. */
|
||||
GPIO_WritePinOutput(GPIO1, 10, 1);
|
||||
GPIO_WritePinOutput(GPIO1, 9, 0);
|
||||
SDK_DelayAtLeastUs(NUM_1M, CLOCK_GetFreq(kCLOCK_CpuClk));
|
||||
GPIO_WritePinOutput(GPIO1, 9, 1);
|
||||
|
||||
PRINTF("Start the soem_gpio_pulse baremetal example...\r\n");
|
||||
|
||||
osal_timer_init(SOEM_PERIOD, 0);
|
||||
if_port_init();
|
||||
control_task(OSEM_PORT_NAME);
|
||||
return 0;
|
||||
}
|
|
@ -0,0 +1,201 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<ksdk:examples xmlns:ksdk="http://nxp.com/ksdk/2.0/ksdk_manifest_v3.0.xsd" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://nxp.com/ksdk/2.0/ksdk_manifest_v3.0.xsd manifest.xsd">
|
||||
<externalDefinitions>
|
||||
<definition extID="driver.mdio-enet.MIMXRT1021"/>
|
||||
<definition extID="driver.phy-device-ksz8081.MIMXRT1021"/>
|
||||
<definition extID="platform.drivers.gpt.MIMXRT1021"/>
|
||||
<definition extID="middleware.soem.MIMXRT1021"/>
|
||||
<definition extID="middleware.baremetal.MIMXRT1021"/>
|
||||
<definition extID="platform.drivers.clock.MIMXRT1021"/>
|
||||
<definition extID="platform.drivers.common.MIMXRT1021"/>
|
||||
<definition extID="device.MIMXRT1021_CMSIS.MIMXRT1021"/>
|
||||
<definition extID="utility.debug_console.MIMXRT1021"/>
|
||||
<definition extID="component.lpuart_adapter.MIMXRT1021"/>
|
||||
<definition extID="component.serial_manager.MIMXRT1021"/>
|
||||
<definition extID="component.lists.MIMXRT1021"/>
|
||||
<definition extID="component.serial_manager_uart.MIMXRT1021"/>
|
||||
<definition extID="platform.drivers.lpuart.MIMXRT1021"/>
|
||||
<definition extID="device.MIMXRT1021_startup.MIMXRT1021"/>
|
||||
<definition extID="platform.drivers.iomuxc.MIMXRT1021"/>
|
||||
<definition extID="platform.utilities.assert.MIMXRT1021"/>
|
||||
<definition extID="platform.drivers.igpio.MIMXRT1021"/>
|
||||
<definition extID="platform.drivers.xip_device.MIMXRT1021"/>
|
||||
<definition extID="platform.drivers.xip_board.evkmimxrt1020.MIMXRT1021"/>
|
||||
<definition extID="component.silicon_id.MIMXRT1021"/>
|
||||
<definition extID="driver.mdio-common.MIMXRT1021"/>
|
||||
<definition extID="CMSIS_Include_core_cm.MIMXRT1021"/>
|
||||
<definition extID="platform.drivers.enet.MIMXRT1021"/>
|
||||
<definition extID="driver.phy-common.MIMXRT1021"/>
|
||||
<definition extID="platform.utilities.misc_utilities.MIMXRT1021"/>
|
||||
<definition extID="device.MIMXRT1021_system.MIMXRT1021"/>
|
||||
<definition extID="iar"/>
|
||||
<definition extID="mdk"/>
|
||||
<definition extID="armgcc"/>
|
||||
<definition extID="mcuxpresso"/>
|
||||
<definition extID="com.nxp.mcuxpresso"/>
|
||||
<definition extID="com.nxp.mcuxpresso.core.debug.support.segger.debug"/>
|
||||
<definition extID="com.nxp.mcuxpresso.core.debug.support.segger.release"/>
|
||||
<definition extID="com.crt.advproject.config.exe.debug"/>
|
||||
<definition extID="com.crt.advproject.config.exe.release"/>
|
||||
</externalDefinitions>
|
||||
<example id="evkmimxrt1020_soem_gpio_pulse_bm" name="soem_gpio_pulse_bm" dependency="driver.mdio-enet.MIMXRT1021 driver.phy-device-ksz8081.MIMXRT1021 platform.drivers.gpt.MIMXRT1021 middleware.soem.MIMXRT1021 middleware.baremetal.MIMXRT1021 platform.drivers.clock.MIMXRT1021 platform.drivers.common.MIMXRT1021 device.MIMXRT1021_CMSIS.MIMXRT1021 utility.debug_console.MIMXRT1021 component.lpuart_adapter.MIMXRT1021 component.serial_manager.MIMXRT1021 component.lists.MIMXRT1021 component.serial_manager_uart.MIMXRT1021 platform.drivers.lpuart.MIMXRT1021 device.MIMXRT1021_startup.MIMXRT1021 platform.drivers.iomuxc.MIMXRT1021 platform.utilities.assert.MIMXRT1021 platform.drivers.igpio.MIMXRT1021 platform.drivers.xip_device.MIMXRT1021 platform.drivers.xip_board.evkmimxrt1020.MIMXRT1021 component.silicon_id.MIMXRT1021 driver.mdio-common.MIMXRT1021 CMSIS_Include_core_cm.MIMXRT1021 platform.drivers.enet.MIMXRT1021 driver.phy-common.MIMXRT1021 platform.utilities.misc_utilities.MIMXRT1021 device.MIMXRT1021_system.MIMXRT1021" category="soem_examples">
|
||||
<projects>
|
||||
<project type="com.crt.advproject.projecttype.exe" nature="org.eclipse.cdt.core.cnature"/>
|
||||
</projects>
|
||||
<memory>
|
||||
<memoryBlock id="BOARD_FLASH_evkmimxrt1020" name="BOARD_FLASH" addr="60000000" size="00800000" type="ExtFlash" access="RO"/>
|
||||
<memoryBlock id="BOARD_SDRAM_evkmimxrt1020" name="BOARD_SDRAM" addr="80000000" size="01E00000" type="RAM" access="RW"/>
|
||||
<memoryBlock id="NCACHE_REGION_evkmimxrt1020" name="NCACHE_REGION" addr="81E00000" size="00200000" type="RAM" access="RW"/>
|
||||
<memoryBlock id="SRAM_DTC_evkmimxrt1020" name="SRAM_DTC" addr="20000000" size="00010000" type="RAM" access="RW"/>
|
||||
<memoryBlock id="SRAM_ITC_evkmimxrt1020" name="SRAM_ITC" addr="00000000" size="00010000" type="RAM" access="RW"/>
|
||||
<memoryBlock id="SRAM_OC_evkmimxrt1020" name="SRAM_OC" addr="20200000" size="00020000" type="RAM" access="RW"/>
|
||||
</memory>
|
||||
<toolchainSettings>
|
||||
<toolchainSetting id_refs="com.nxp.mcuxpresso">
|
||||
<option id="gnu.c.compiler.option.preprocessor.def.symbols" type="stringList">
|
||||
<value>XIP_BOOT_HEADER_DCD_ENABLE=1</value>
|
||||
<value>SKIP_SYSCLK_INIT</value>
|
||||
<value>DATA_SECTION_IS_CACHEABLE=1</value>
|
||||
<value>CPU_MIMXRT1021DAG5A</value>
|
||||
<value>SDK_DEBUGCONSOLE=1</value>
|
||||
<value>XIP_EXTERNAL_FLASH=1</value>
|
||||
<value>XIP_BOOT_HEADER_ENABLE=1</value>
|
||||
<value>SDK_DEBUGCONSOLE_UART</value>
|
||||
<value>SERIAL_PORT_TYPE_UART=1</value>
|
||||
<value>PRINTF_ADVANCED_ENABLE=1</value>
|
||||
<value>FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE</value>
|
||||
<value>MCUXPRESSO_SDK</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.gas.fpu" type="enum">
|
||||
<value>com.crt.advproject.gas.fpu.fpv5dp.hard</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.gcc.fpu" type="enum">
|
||||
<value>com.crt.advproject.gcc.fpu.fpv5dp.hard</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.optimization.flags" type="string">
|
||||
<value>-fno-common</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.c.misc.dialect" type="enum">
|
||||
<value>com.crt.advproject.misc.dialect.gnu99</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.misc.other" type="string">
|
||||
<value>-c -ffunction-sections -fdata-sections -ffreestanding -fno-builtin</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.warnings.allwarn" type="boolean">
|
||||
<value>false</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.warnings.toerrors" type="boolean">
|
||||
<value>false</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.link.fpu" type="enum">
|
||||
<value>com.crt.advproject.link.fpu.fpv5dp.hard</value>
|
||||
</option>
|
||||
<option id="gnu.c.link.option.nostdlibs" type="boolean">
|
||||
<value>true</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.link.memory.sections" type="stringList">
|
||||
<value>isd=*(NonCacheable.init);region=NCACHE_REGION;type=.data</value>
|
||||
<value>isd=*(NonCacheable);region=NCACHE_REGION;type=.bss</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.link.memory.heapAndStack" type="string">
|
||||
<value>&Heap:Default;Default;0x10000&Stack:Default;Default;0x1000</value>
|
||||
</option>
|
||||
</toolchainSetting>
|
||||
</toolchainSettings>
|
||||
<debug_configurations>
|
||||
<debug_configuration id_refs="com.nxp.mcuxpresso.core.debug.support.segger.debug">
|
||||
<scripts>
|
||||
<script type="segger_script">
|
||||
<source path="." project_relative_path="script" type="script">
|
||||
<files mask="evkmimxrt1020_sdram_init.jlinkscript"/>
|
||||
</source>
|
||||
</script>
|
||||
</scripts>
|
||||
</debug_configuration>
|
||||
<debug_configuration id_refs="com.nxp.mcuxpresso.core.debug.support.segger.release">
|
||||
<scripts>
|
||||
<script type="segger_script">
|
||||
<source path="." project_relative_path="script" type="script">
|
||||
<files mask="evkmimxrt1020_sdram_init.jlinkscript"/>
|
||||
</source>
|
||||
</script>
|
||||
</scripts>
|
||||
</debug_configuration>
|
||||
<debug_configuration id_refs="com.crt.advproject.config.exe.debug com.crt.advproject.config.exe.release">
|
||||
<drivers>
|
||||
<driver id_refs="BOARD_FLASH_evkmimxrt1020">
|
||||
<driverBinary path="../../../../../devices/MIMXRT1021/mcuxpresso" project_relative_path="binary" type="binary">
|
||||
<files mask="MIMXRT1020-EVK_IS25LP064.cfx"/>
|
||||
</driverBinary>
|
||||
</driver>
|
||||
</drivers>
|
||||
</debug_configuration>
|
||||
</debug_configurations>
|
||||
<include_paths>
|
||||
<include_path path="../../../../../middleware/soem/osal/baremetal" project_relative_path="soem/osal/baremetal" type="c_include"/>
|
||||
<include_path path="." project_relative_path="source" type="c_include"/>
|
||||
<include_path path="." project_relative_path="board" type="c_include"/>
|
||||
<include_path path="." project_relative_path="source" type="asm_include"/>
|
||||
</include_paths>
|
||||
<source path="iar" project_relative_path="./" type="workspace" toolchain="iar">
|
||||
<files mask="soem_gpio_pulse_bm.ewd"/>
|
||||
<files mask="soem_gpio_pulse_bm.ewp"/>
|
||||
<files mask="soem_gpio_pulse_bm.eww"/>
|
||||
</source>
|
||||
<source path="mdk" project_relative_path="./" type="workspace" toolchain="mdk">
|
||||
<files mask="soem_gpio_pulse_bm.uvprojx"/>
|
||||
<files mask="soem_gpio_pulse_bm.uvoptx"/>
|
||||
<files mask="soem_gpio_pulse_bm.uvmpw"/>
|
||||
</source>
|
||||
<source path="armgcc" project_relative_path="./" type="workspace" toolchain="armgcc">
|
||||
<files mask="build_all.bat"/>
|
||||
<files mask="build_all.sh"/>
|
||||
<files mask="clean.bat"/>
|
||||
<files mask="clean.sh"/>
|
||||
<files mask="CMakeLists.txt"/>
|
||||
<files mask="flags.cmake"/>
|
||||
<files mask="config.cmake"/>
|
||||
<files mask="build_flexspi_nor_sdram_debug.bat"/>
|
||||
<files mask="build_flexspi_nor_sdram_debug.sh"/>
|
||||
<files mask="build_flexspi_nor_sdram_release.bat"/>
|
||||
<files mask="build_flexspi_nor_sdram_release.sh"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="board" type="src">
|
||||
<files mask="pin_mux.c"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="board" type="c_include">
|
||||
<files mask="pin_mux.h"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="source" type="src">
|
||||
<files mask="soem_gpio_pulse.c"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="board" type="src">
|
||||
<files mask="board.c"/>
|
||||
<files mask="clock_config.c"/>
|
||||
<files mask="dcd.c"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="board" type="c_include">
|
||||
<files mask="board.h"/>
|
||||
<files mask="clock_config.h"/>
|
||||
<files mask="dcd.h"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="doc" type="doc" toolchain="iar mdk mcuxpresso armgcc">
|
||||
<files mask="readme.txt"/>
|
||||
</source>
|
||||
<source path="iar" project_relative_path="MIMXRT1021/iar" type="linker" toolchain="iar">
|
||||
<files mask="MIMXRT1021xxxxx_flexspi_nor_sdram.icf"/>
|
||||
</source>
|
||||
<source path="mdk" project_relative_path="MIMXRT1021/arm" type="linker" toolchain="mdk">
|
||||
<files mask="MIMXRT1021xxxxx_flexspi_nor_sdram.scf"/>
|
||||
</source>
|
||||
<source path="armgcc" project_relative_path="MIMXRT1021/gcc" type="linker" toolchain="armgcc">
|
||||
<files mask="MIMXRT1021xxxxx_flexspi_nor_sdram.ld"/>
|
||||
</source>
|
||||
<source path="iar" project_relative_path="evkmimxrt1020" type="other" toolchain="iar">
|
||||
<files mask="evkmimxrt1020_sdram_init.mac"/>
|
||||
</source>
|
||||
<source path="mdk" project_relative_path="evkmimxrt1020" type="configuration" toolchain="mdk">
|
||||
<files mask="evkmimxrt1020_flexspi_nor_sdram.ini"/>
|
||||
</source>
|
||||
</example>
|
||||
</ksdk:examples>
|
|
@ -0,0 +1,157 @@
|
|||
/*
|
||||
FreeRTOS Kernel V10.3.0
|
||||
Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
this software and associated documentation files (the "Software"), to deal in
|
||||
the Software without restriction, including without limitation the rights to
|
||||
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
http://aws.amazon.com/freertos
|
||||
http://www.FreeRTOS.org
|
||||
*/
|
||||
|
||||
#ifndef FREERTOS_CONFIG_H
|
||||
#define FREERTOS_CONFIG_H
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Application specific definitions.
|
||||
*
|
||||
* These definitions should be adjusted for your particular hardware and
|
||||
* application requirements.
|
||||
*
|
||||
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
|
||||
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
|
||||
*
|
||||
* See http://www.freertos.org/a00110.html.
|
||||
*----------------------------------------------------------*/
|
||||
|
||||
#define configUSE_PREEMPTION 1
|
||||
#define configUSE_TICKLESS_IDLE 0
|
||||
#define configCPU_CLOCK_HZ (SystemCoreClock)
|
||||
#define configTICK_RATE_HZ ((TickType_t)1000)
|
||||
#define configMAX_PRIORITIES 5
|
||||
#define configMINIMAL_STACK_SIZE ((unsigned short)90)
|
||||
#define configMAX_TASK_NAME_LEN 20
|
||||
#define configUSE_16_BIT_TICKS 0
|
||||
#define configIDLE_SHOULD_YIELD 1
|
||||
#define configUSE_TASK_NOTIFICATIONS 1
|
||||
#define configUSE_MUTEXES 1
|
||||
#define configUSE_RECURSIVE_MUTEXES 1
|
||||
#define configUSE_COUNTING_SEMAPHORES 1
|
||||
#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */
|
||||
#define configQUEUE_REGISTRY_SIZE 8
|
||||
#define configUSE_QUEUE_SETS 0
|
||||
#define configUSE_TIME_SLICING 0
|
||||
#define configUSE_NEWLIB_REENTRANT 0
|
||||
#define configENABLE_BACKWARD_COMPATIBILITY 0
|
||||
#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5
|
||||
|
||||
/* Used memory allocation (heap_x.c) */
|
||||
#define configFRTOS_MEMORY_SCHEME 1
|
||||
/* Tasks.c additions (e.g. Thread Aware Debug capability) */
|
||||
#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 0
|
||||
|
||||
/* Memory allocation related definitions. */
|
||||
#define configSUPPORT_STATIC_ALLOCATION 1
|
||||
#define configSUPPORT_DYNAMIC_ALLOCATION 0
|
||||
#define configTOTAL_HEAP_SIZE ((size_t)(10 * 1024))
|
||||
#define configAPPLICATION_ALLOCATED_HEAP 0
|
||||
|
||||
/* Hook function related definitions. */
|
||||
#define configUSE_IDLE_HOOK 0
|
||||
#define configUSE_TICK_HOOK 0
|
||||
#define configCHECK_FOR_STACK_OVERFLOW 0
|
||||
#define configUSE_MALLOC_FAILED_HOOK 0
|
||||
#define configUSE_DAEMON_TASK_STARTUP_HOOK 0
|
||||
|
||||
/* Run time and task stats gathering related definitions. */
|
||||
#define configGENERATE_RUN_TIME_STATS 0
|
||||
#define configUSE_TRACE_FACILITY 0
|
||||
#define configUSE_STATS_FORMATTING_FUNCTIONS 0
|
||||
|
||||
/* Task aware debugging. */
|
||||
#define configRECORD_STACK_HIGH_ADDRESS 0
|
||||
|
||||
/* Co-routine related definitions. */
|
||||
#define configUSE_CO_ROUTINES 0
|
||||
#define configMAX_CO_ROUTINE_PRIORITIES 0
|
||||
|
||||
/* Software timer related definitions. */
|
||||
#define configUSE_TIMERS 1
|
||||
#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1)
|
||||
#define configTIMER_QUEUE_LENGTH 10
|
||||
#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2)
|
||||
|
||||
/* Define to trap errors during development. */
|
||||
#define configASSERT(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);}
|
||||
|
||||
/* Optional functions - most linkers will remove unused functions anyway. */
|
||||
#define INCLUDE_vTaskPrioritySet 1
|
||||
#define INCLUDE_uxTaskPriorityGet 1
|
||||
#define INCLUDE_vTaskDelete 1
|
||||
#define INCLUDE_vTaskSuspend 1
|
||||
#define INCLUDE_vTaskDelayUntil 1
|
||||
#define INCLUDE_vTaskDelay 1
|
||||
#define INCLUDE_xTaskGetSchedulerState 0
|
||||
#define INCLUDE_xTaskGetCurrentTaskHandle 0
|
||||
#define INCLUDE_uxTaskGetStackHighWaterMark 0
|
||||
#define INCLUDE_xTaskGetIdleTaskHandle 0
|
||||
#define INCLUDE_eTaskGetState 1
|
||||
#define INCLUDE_xTimerPendFunctionCall 1
|
||||
#define INCLUDE_xTaskAbortDelay 0
|
||||
#define INCLUDE_xTaskGetHandle 0
|
||||
#define INCLUDE_xTaskResumeFromISR 1
|
||||
|
||||
|
||||
|
||||
#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__)
|
||||
/* Clock manager provides in this variable system core clock frequency */
|
||||
#include <stdint.h>
|
||||
extern uint32_t SystemCoreClock;
|
||||
#endif
|
||||
|
||||
/* Interrupt nesting behaviour configuration. Cortex-M specific. */
|
||||
#ifdef __NVIC_PRIO_BITS
|
||||
/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
|
||||
#define configPRIO_BITS __NVIC_PRIO_BITS
|
||||
#else
|
||||
#define configPRIO_BITS 4 /* 15 priority levels */
|
||||
#endif
|
||||
|
||||
/* The lowest interrupt priority that can be used in a call to a "set priority"
|
||||
function. */
|
||||
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1)
|
||||
|
||||
/* The highest interrupt priority that can be used by any interrupt service
|
||||
routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
|
||||
INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
|
||||
PRIORITY THAN THIS! (higher priorities are lower numeric values. */
|
||||
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2
|
||||
|
||||
/* Interrupt priorities used by the kernel port layer itself. These are generic
|
||||
to all Cortex-M ports, and do not rely on any particular library functions. */
|
||||
#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
|
||||
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
|
||||
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
|
||||
#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
|
||||
|
||||
/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
|
||||
standard names. */
|
||||
#define vPortSVCHandler SVC_Handler
|
||||
#define xPortPendSVHandler PendSV_Handler
|
||||
#define xPortSysTickHandler SysTick_Handler
|
||||
|
||||
#endif /* FREERTOS_CONFIG_H */
|
|
@ -0,0 +1,139 @@
|
|||
# CROSS COMPILER SETTING
|
||||
SET(CMAKE_SYSTEM_NAME Generic)
|
||||
CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
|
||||
|
||||
# THE VERSION NUMBER
|
||||
SET (Tutorial_VERSION_MAJOR 1)
|
||||
SET (Tutorial_VERSION_MINOR 0)
|
||||
|
||||
# ENABLE ASM
|
||||
ENABLE_LANGUAGE(ASM)
|
||||
|
||||
SET(CMAKE_STATIC_LIBRARY_PREFIX)
|
||||
SET(CMAKE_STATIC_LIBRARY_SUFFIX)
|
||||
|
||||
SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
|
||||
SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
|
||||
|
||||
# CURRENT DIRECTORY
|
||||
SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
|
||||
|
||||
SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
|
||||
SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
|
||||
|
||||
|
||||
project(soem_gpio_pulse_freertos)
|
||||
|
||||
set(MCUX_SDK_PROJECT_NAME soem_gpio_pulse_freertos.elf)
|
||||
|
||||
include(${ProjDirPath}/flags.cmake)
|
||||
|
||||
include(${ProjDirPath}/config.cmake)
|
||||
|
||||
add_executable(${MCUX_SDK_PROJECT_NAME}
|
||||
"${ProjDirPath}/../pin_mux.c"
|
||||
"${ProjDirPath}/../pin_mux.h"
|
||||
"${ProjDirPath}/../soem_gpio_pulse.c"
|
||||
"${ProjDirPath}/../FreeRTOSConfig.h"
|
||||
"${ProjDirPath}/../board.c"
|
||||
"${ProjDirPath}/../board.h"
|
||||
"${ProjDirPath}/../clock_config.c"
|
||||
"${ProjDirPath}/../clock_config.h"
|
||||
"${ProjDirPath}/../dcd.c"
|
||||
"${ProjDirPath}/../dcd.h"
|
||||
)
|
||||
|
||||
target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
|
||||
${ProjDirPath}/..
|
||||
${ProjDirPath}/../../../../../../middleware/soem/osal/freertos
|
||||
)
|
||||
|
||||
set(CMAKE_MODULE_PATH
|
||||
${ProjDirPath}/../../../../../../components/phy/mdio/enet
|
||||
${ProjDirPath}/../../../../../../components/phy/device/phyksz8081
|
||||
${ProjDirPath}/../../../../../../devices/MIMXRT1021/drivers
|
||||
${ProjDirPath}/../../../../../../middleware/soem
|
||||
${ProjDirPath}/../../../../../../rtos/freertos/freertos_kernel
|
||||
${ProjDirPath}/../../../../../../devices/MIMXRT1021
|
||||
${ProjDirPath}/../../../../../../devices/MIMXRT1021/utilities
|
||||
${ProjDirPath}/../../../../../../components/uart
|
||||
${ProjDirPath}/../../../../../../components/serial_manager
|
||||
${ProjDirPath}/../../../../../../components/lists
|
||||
${ProjDirPath}/../../../../../../devices/MIMXRT1021/xip
|
||||
${ProjDirPath}/../../../../xip
|
||||
${ProjDirPath}/../../../../../../components/silicon_id
|
||||
${ProjDirPath}/../../../../../../components/phy
|
||||
${ProjDirPath}/../../../../../../CMSIS/Core/Include
|
||||
)
|
||||
|
||||
# include modules
|
||||
include(driver_mdio-enet_MIMXRT1021)
|
||||
|
||||
include(driver_phy-device-ksz8081_MIMXRT1021)
|
||||
|
||||
include(driver_gpt_MIMXRT1021)
|
||||
|
||||
include(middleware_soem_MIMXRT1021)
|
||||
|
||||
include(middleware_freertos-kernel_MIMXRT1021)
|
||||
|
||||
include(driver_clock_MIMXRT1021)
|
||||
|
||||
include(driver_common_MIMXRT1021)
|
||||
|
||||
include(device_MIMXRT1021_CMSIS_MIMXRT1021)
|
||||
|
||||
include(utility_debug_console_MIMXRT1021)
|
||||
|
||||
include(component_lpuart_adapter_MIMXRT1021)
|
||||
|
||||
include(component_serial_manager_MIMXRT1021)
|
||||
|
||||
include(component_lists_MIMXRT1021)
|
||||
|
||||
include(component_serial_manager_uart_MIMXRT1021)
|
||||
|
||||
include(driver_lpuart_MIMXRT1021)
|
||||
|
||||
include(device_MIMXRT1021_startup_MIMXRT1021)
|
||||
|
||||
include(driver_iomuxc_MIMXRT1021)
|
||||
|
||||
include(utility_assert_MIMXRT1021)
|
||||
|
||||
include(driver_igpio_MIMXRT1021)
|
||||
|
||||
include(driver_xip_device_MIMXRT1021)
|
||||
|
||||
include(driver_xip_board_evkmimxrt1020_MIMXRT1021)
|
||||
|
||||
include(component_silicon_id_MIMXRT1021)
|
||||
|
||||
include(driver_mdio-common_MIMXRT1021)
|
||||
|
||||
include(CMSIS_Include_core_cm_MIMXRT1021)
|
||||
|
||||
include(driver_enet_MIMXRT1021)
|
||||
|
||||
include(driver_phy-common_MIMXRT1021)
|
||||
|
||||
include(middleware_freertos-kernel_extension_MIMXRT1021)
|
||||
|
||||
include(utilities_misc_utilities_MIMXRT1021)
|
||||
|
||||
include(device_MIMXRT1021_system_MIMXRT1021)
|
||||
|
||||
|
||||
TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
|
||||
|
||||
target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m)
|
||||
|
||||
target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c)
|
||||
|
||||
target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc)
|
||||
|
||||
target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys)
|
||||
|
||||
TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
|
||||
|
||||
|
|
@ -0,0 +1,280 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1021CAF4A
|
||||
** MIMXRT1021CAG4A
|
||||
** MIMXRT1021DAF5A
|
||||
** MIMXRT1021DAG5A
|
||||
**
|
||||
** Compiler: GNU C Compiler
|
||||
** Reference manual: IMXRT1020RM Rev.1, 12/2018 | IMXRT1020SRM Rev.3
|
||||
** Version: rev. 0.1, 2017-06-06
|
||||
** Build: b210709
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the GNU C Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2021 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x1000;
|
||||
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
|
||||
VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x00000400 : 0;
|
||||
NCACHE_HEAP_START = DEFINED(__heap_noncacheable__) ? 0x82000000 - HEAP_SIZE : 0x81E00000 - HEAP_SIZE;
|
||||
NCACHE_HEAP_SIZE = DEFINED(__heap_noncacheable__) ? HEAP_SIZE : 0x0000;
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
m_flash_config (RX) : ORIGIN = 0x60000000, LENGTH = 0x00001000
|
||||
m_ivt (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000
|
||||
m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400
|
||||
m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x007FDC00
|
||||
m_qacode (RX) : ORIGIN = 0x00000000, LENGTH = 0x00010000
|
||||
m_data (RW) : ORIGIN = 0x80000000, LENGTH = DEFINED(__heap_noncacheable__) ? 0x01E00000 : 0x01E00000 - HEAP_SIZE
|
||||
m_ncache (RW) : ORIGIN = 0x81E00000, LENGTH = DEFINED(__heap_noncacheable__) ? 0x00200000 - HEAP_SIZE : 0x00200000
|
||||
m_data2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00010000
|
||||
m_data3 (RW) : ORIGIN = 0x20200000, LENGTH = 0x00020000
|
||||
m_heap (RW) : ORIGIN = NCACHE_HEAP_START, LENGTH = HEAP_SIZE
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
__NCACHE_REGION_START = ORIGIN(m_ncache);
|
||||
__NCACHE_REGION_SIZE = LENGTH(m_ncache) + NCACHE_HEAP_SIZE;
|
||||
|
||||
.flash_config :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__FLASH_BASE = .;
|
||||
KEEP(* (.boot_hdr.conf)) /* flash config section */
|
||||
. = ALIGN(4);
|
||||
} > m_flash_config
|
||||
|
||||
ivt_begin = ORIGIN(m_flash_config) + LENGTH(m_flash_config);
|
||||
|
||||
.ivt : AT(ivt_begin)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(* (.boot_hdr.ivt)) /* ivt section */
|
||||
KEEP(* (.boot_hdr.boot_data)) /* boot section */
|
||||
KEEP(* (.boot_hdr.dcd_data)) /* dcd section */
|
||||
. = ALIGN(4);
|
||||
} > m_ivt
|
||||
|
||||
/* The startup code goes first into internal RAM */
|
||||
.interrupts :
|
||||
{
|
||||
__VECTOR_TABLE = .;
|
||||
__Vectors = .;
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} > m_interrupts
|
||||
|
||||
/* The program code and other data goes into internal RAM */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
. = ALIGN(4);
|
||||
} > m_text
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > m_text
|
||||
|
||||
.ARM :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} > m_text
|
||||
|
||||
.ctors :
|
||||
{
|
||||
__CTOR_LIST__ = .;
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
from the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
__CTOR_END__ = .;
|
||||
} > m_text
|
||||
|
||||
.dtors :
|
||||
{
|
||||
__DTOR_LIST__ = .;
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
__DTOR_END__ = .;
|
||||
} > m_text
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} > m_text
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} > m_text
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} > m_text
|
||||
|
||||
__etext = .; /* define a global symbol at end of code */
|
||||
__DATA_ROM = .; /* Symbol is used by startup for data initialization */
|
||||
|
||||
.interrupts_ram :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__VECTOR_RAM__ = .;
|
||||
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
|
||||
*(.m_interrupts_ram) /* This is a user defined section */
|
||||
. += VECTOR_RAM_SIZE;
|
||||
. = ALIGN(4);
|
||||
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
|
||||
} > m_data
|
||||
|
||||
__VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);
|
||||
__RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;
|
||||
|
||||
.data : AT(__DATA_ROM)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__DATA_RAM = .;
|
||||
__data_start__ = .; /* create a global symbol at data start */
|
||||
*(m_usb_dma_init_data)
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
KEEP(*(.jcr*))
|
||||
. = ALIGN(4);
|
||||
__data_end__ = .; /* define a global symbol at data end */
|
||||
} > m_data
|
||||
|
||||
__ram_function_flash_start = __DATA_ROM + (__data_end__ - __data_start__); /* Symbol is used by startup for TCM data initialization */
|
||||
|
||||
.ram_function : AT(__ram_function_flash_start)
|
||||
{
|
||||
. = ALIGN(32);
|
||||
__ram_function_start__ = .;
|
||||
*(CodeQuickAccess)
|
||||
. = ALIGN(128);
|
||||
__ram_function_end__ = .;
|
||||
} > m_qacode
|
||||
|
||||
__NDATA_ROM = __ram_function_flash_start + (__ram_function_end__ - __ram_function_start__);
|
||||
.ncache.init : AT(__NDATA_ROM)
|
||||
{
|
||||
__noncachedata_start__ = .; /* create a global symbol at ncache data start */
|
||||
*(NonCacheable.init)
|
||||
. = ALIGN(4);
|
||||
__noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
|
||||
} > m_ncache
|
||||
. = __noncachedata_init_end__;
|
||||
.ncache :
|
||||
{
|
||||
*(NonCacheable)
|
||||
. = ALIGN(4);
|
||||
__noncachedata_end__ = .; /* define a global symbol at ncache data end */
|
||||
} > m_ncache
|
||||
|
||||
__DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
|
||||
text_end = ORIGIN(m_text) + LENGTH(m_text);
|
||||
ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
|
||||
|
||||
.qadata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(DataQuickAccess) /* quick access data section */
|
||||
. = ALIGN(4);
|
||||
} > m_data2
|
||||
|
||||
/* Uninitialized data section */
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
. = ALIGN(4);
|
||||
__START_BSS = .;
|
||||
__bss_start__ = .;
|
||||
*(m_usb_dma_noninit_data)
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
__END_BSS = .;
|
||||
} > m_data
|
||||
|
||||
.heap :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__end__ = .;
|
||||
PROVIDE(end = .);
|
||||
__HeapBase = .;
|
||||
. += HEAP_SIZE;
|
||||
__HeapLimit = .;
|
||||
__heap_limit = .; /* Add for _sbrk */
|
||||
} > m_heap
|
||||
|
||||
.stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
. += STACK_SIZE;
|
||||
} > m_data
|
||||
|
||||
/* Initializes stack on the end of block */
|
||||
__StackTop = ORIGIN(m_data) + LENGTH(m_data);
|
||||
__StackLimit = __StackTop - STACK_SIZE;
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
|
@ -0,0 +1,15 @@
|
|||
if exist CMakeFiles (RD /s /Q CMakeFiles)
|
||||
if exist Makefile (DEL /s /Q /F Makefile)
|
||||
if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
|
||||
if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
|
||||
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flexspi_nor_sdram_debug .
|
||||
mingw32-make -j
|
||||
|
||||
if exist CMakeFiles (RD /s /Q CMakeFiles)
|
||||
if exist Makefile (DEL /s /Q /F Makefile)
|
||||
if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
|
||||
if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
|
||||
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flexspi_nor_sdram_release .
|
||||
mingw32-make -j
|
||||
|
||||
IF "%1" == "" ( pause )
|
|
@ -0,0 +1,15 @@
|
|||
#!/bin/sh
|
||||
if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
|
||||
if [ -f "Makefile" ];then rm -f Makefile; fi
|
||||
if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
|
||||
if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
|
||||
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flexspi_nor_sdram_debug .
|
||||
make -j
|
||||
|
||||
if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
|
||||
if [ -f "Makefile" ];then rm -f Makefile; fi
|
||||
if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
|
||||
if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
|
||||
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flexspi_nor_sdram_release .
|
||||
make -j
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
if exist CMakeFiles (RD /s /Q CMakeFiles)
|
||||
if exist Makefile (DEL /s /Q /F Makefile)
|
||||
if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
|
||||
if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
|
||||
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flexspi_nor_sdram_debug .
|
||||
mingw32-make -j 2> build_log.txt
|
|
@ -0,0 +1,7 @@
|
|||
#!/bin/sh
|
||||
if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
|
||||
if [ -f "Makefile" ];then rm -f Makefile; fi
|
||||
if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
|
||||
if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
|
||||
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flexspi_nor_sdram_debug .
|
||||
make -j 2>&1 | tee build_log.txt
|
|
@ -0,0 +1,6 @@
|
|||
if exist CMakeFiles (RD /s /Q CMakeFiles)
|
||||
if exist Makefile (DEL /s /Q /F Makefile)
|
||||
if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
|
||||
if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
|
||||
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flexspi_nor_sdram_release .
|
||||
mingw32-make -j 2> build_log.txt
|
|
@ -0,0 +1,7 @@
|
|||
#!/bin/sh
|
||||
if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
|
||||
if [ -f "Makefile" ];then rm -f Makefile; fi
|
||||
if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
|
||||
if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
|
||||
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flexspi_nor_sdram_release .
|
||||
make -j 2>&1 | tee build_log.txt
|
|
@ -0,0 +1,3 @@
|
|||
RD /s /Q flexspi_nor_sdram_debug flexspi_nor_sdram_release CMakeFiles
|
||||
DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
|
||||
pause
|
|
@ -0,0 +1,3 @@
|
|||
#!/bin/sh
|
||||
rm -rf flexspi_nor_sdram_debug flexspi_nor_sdram_release CMakeFiles
|
||||
rm -rf Makefile cmake_install.cmake CMakeCache.txt
|
|
@ -0,0 +1,5 @@
|
|||
# config to select component, the format is CONFIG_USE_${component}
|
||||
set(CONFIG_USE_middleware_freertos-kernel_MIMXRT1021 true)
|
||||
set(CONFIG_USE_component_serial_manager_uart_MIMXRT1021 true)
|
||||
set(CONFIG_USE_driver_lpuart_MIMXRT1021 true)
|
||||
set(CONFIG_USE_driver_common_MIMXRT1021 true)
|
|
@ -0,0 +1,193 @@
|
|||
SET(CMAKE_ASM_FLAGS_FLEXSPI_NOR_SDRAM_DEBUG " \
|
||||
${CMAKE_ASM_FLAGS_FLEXSPI_NOR_SDRAM_DEBUG} \
|
||||
-D__STARTUP_CLEAR_BSS \
|
||||
-DDEBUG \
|
||||
-D__STARTUP_INITIALIZE_NONCACHEDATA \
|
||||
-mcpu=cortex-m7 \
|
||||
-mfloat-abi=hard \
|
||||
-mfpu=fpv5-d16 \
|
||||
-mthumb \
|
||||
")
|
||||
SET(CMAKE_ASM_FLAGS_FLEXSPI_NOR_SDRAM_RELEASE " \
|
||||
${CMAKE_ASM_FLAGS_FLEXSPI_NOR_SDRAM_RELEASE} \
|
||||
-D__STARTUP_CLEAR_BSS \
|
||||
-DNDEBUG \
|
||||
-D__STARTUP_INITIALIZE_NONCACHEDATA \
|
||||
-mcpu=cortex-m7 \
|
||||
-mfloat-abi=hard \
|
||||
-mfpu=fpv5-d16 \
|
||||
-mthumb \
|
||||
")
|
||||
SET(CMAKE_C_FLAGS_FLEXSPI_NOR_SDRAM_DEBUG " \
|
||||
${CMAKE_C_FLAGS_FLEXSPI_NOR_SDRAM_DEBUG} \
|
||||
-DXIP_EXTERNAL_FLASH=1 \
|
||||
-DXIP_BOOT_HEADER_ENABLE=1 \
|
||||
-DXIP_BOOT_HEADER_DCD_ENABLE=1 \
|
||||
-DSKIP_SYSCLK_INIT \
|
||||
-DDATA_SECTION_IS_CACHEABLE=1 \
|
||||
-DDEBUG \
|
||||
-DCPU_MIMXRT1021DAG5A \
|
||||
-DSDK_DEBUGCONSOLE_UART \
|
||||
-DSERIAL_PORT_TYPE_UART=1 \
|
||||
-DPRINTF_ADVANCED_ENABLE=1 \
|
||||
-DFSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE \
|
||||
-DSDK_OS_FREE_RTOS \
|
||||
-DMCUXPRESSO_SDK \
|
||||
-g \
|
||||
-O0 \
|
||||
-mcpu=cortex-m7 \
|
||||
-Wall \
|
||||
-mfloat-abi=hard \
|
||||
-mfpu=fpv5-d16 \
|
||||
-mthumb \
|
||||
-MMD \
|
||||
-MP \
|
||||
-fno-common \
|
||||
-ffunction-sections \
|
||||
-fdata-sections \
|
||||
-ffreestanding \
|
||||
-fno-builtin \
|
||||
-mapcs \
|
||||
-std=gnu99 \
|
||||
")
|
||||
SET(CMAKE_C_FLAGS_FLEXSPI_NOR_SDRAM_RELEASE " \
|
||||
${CMAKE_C_FLAGS_FLEXSPI_NOR_SDRAM_RELEASE} \
|
||||
-DXIP_EXTERNAL_FLASH=1 \
|
||||
-DXIP_BOOT_HEADER_ENABLE=1 \
|
||||
-DXIP_BOOT_HEADER_DCD_ENABLE=1 \
|
||||
-DSKIP_SYSCLK_INIT \
|
||||
-DDATA_SECTION_IS_CACHEABLE=1 \
|
||||
-DNDEBUG \
|
||||
-DCPU_MIMXRT1021DAG5A \
|
||||
-DSDK_DEBUGCONSOLE_UART \
|
||||
-DSERIAL_PORT_TYPE_UART=1 \
|
||||
-DPRINTF_ADVANCED_ENABLE=1 \
|
||||
-DFSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE \
|
||||
-DSDK_OS_FREE_RTOS \
|
||||
-DMCUXPRESSO_SDK \
|
||||
-Os \
|
||||
-mcpu=cortex-m7 \
|
||||
-Wall \
|
||||
-mfloat-abi=hard \
|
||||
-mfpu=fpv5-d16 \
|
||||
-mthumb \
|
||||
-MMD \
|
||||
-MP \
|
||||
-fno-common \
|
||||
-ffunction-sections \
|
||||
-fdata-sections \
|
||||
-ffreestanding \
|
||||
-fno-builtin \
|
||||
-mapcs \
|
||||
-std=gnu99 \
|
||||
")
|
||||
SET(CMAKE_CXX_FLAGS_FLEXSPI_NOR_SDRAM_DEBUG " \
|
||||
${CMAKE_CXX_FLAGS_FLEXSPI_NOR_SDRAM_DEBUG} \
|
||||
-DDEBUG \
|
||||
-DSERIAL_PORT_TYPE_UART=1 \
|
||||
-DMCUXPRESSO_SDK \
|
||||
-g \
|
||||
-O0 \
|
||||
-mcpu=cortex-m7 \
|
||||
-Wall \
|
||||
-mfloat-abi=hard \
|
||||
-mfpu=fpv5-d16 \
|
||||
-mthumb \
|
||||
-MMD \
|
||||
-MP \
|
||||
-fno-common \
|
||||
-ffunction-sections \
|
||||
-fdata-sections \
|
||||
-ffreestanding \
|
||||
-fno-builtin \
|
||||
-mapcs \
|
||||
-fno-rtti \
|
||||
-fno-exceptions \
|
||||
")
|
||||
SET(CMAKE_CXX_FLAGS_FLEXSPI_NOR_SDRAM_RELEASE " \
|
||||
${CMAKE_CXX_FLAGS_FLEXSPI_NOR_SDRAM_RELEASE} \
|
||||
-DNDEBUG \
|
||||
-DSERIAL_PORT_TYPE_UART=1 \
|
||||
-DMCUXPRESSO_SDK \
|
||||
-Os \
|
||||
-mcpu=cortex-m7 \
|
||||
-Wall \
|
||||
-mfloat-abi=hard \
|
||||
-mfpu=fpv5-d16 \
|
||||
-mthumb \
|
||||
-MMD \
|
||||
-MP \
|
||||
-fno-common \
|
||||
-ffunction-sections \
|
||||
-fdata-sections \
|
||||
-ffreestanding \
|
||||
-fno-builtin \
|
||||
-mapcs \
|
||||
-fno-rtti \
|
||||
-fno-exceptions \
|
||||
")
|
||||
SET(CMAKE_EXE_LINKER_FLAGS_FLEXSPI_NOR_SDRAM_DEBUG " \
|
||||
${CMAKE_EXE_LINKER_FLAGS_FLEXSPI_NOR_SDRAM_DEBUG} \
|
||||
-g \
|
||||
-mcpu=cortex-m7 \
|
||||
-Wall \
|
||||
-mfloat-abi=hard \
|
||||
-mfpu=fpv5-d16 \
|
||||
--specs=nano.specs \
|
||||
--specs=nosys.specs \
|
||||
-fno-common \
|
||||
-ffunction-sections \
|
||||
-fdata-sections \
|
||||
-ffreestanding \
|
||||
-fno-builtin \
|
||||
-mthumb \
|
||||
-mapcs \
|
||||
-Xlinker \
|
||||
--gc-sections \
|
||||
-Xlinker \
|
||||
-static \
|
||||
-Xlinker \
|
||||
-z \
|
||||
-Xlinker \
|
||||
muldefs \
|
||||
-Xlinker \
|
||||
-Map=output.map \
|
||||
-Wl,--print-memory-usage \
|
||||
-Xlinker \
|
||||
--defsym=__stack_size__=0x1000 \
|
||||
-Xlinker \
|
||||
--defsym=__heap_size__=0x1000 \
|
||||
-T${ProjDirPath}/MIMXRT1021xxxxx_flexspi_nor_sdram.ld -static \
|
||||
")
|
||||
SET(CMAKE_EXE_LINKER_FLAGS_FLEXSPI_NOR_SDRAM_RELEASE " \
|
||||
${CMAKE_EXE_LINKER_FLAGS_FLEXSPI_NOR_SDRAM_RELEASE} \
|
||||
-mcpu=cortex-m7 \
|
||||
-Wall \
|
||||
-mfloat-abi=hard \
|
||||
-mfpu=fpv5-d16 \
|
||||
--specs=nano.specs \
|
||||
--specs=nosys.specs \
|
||||
-fno-common \
|
||||
-ffunction-sections \
|
||||
-fdata-sections \
|
||||
-ffreestanding \
|
||||
-fno-builtin \
|
||||
-mthumb \
|
||||
-mapcs \
|
||||
-Xlinker \
|
||||
--gc-sections \
|
||||
-Xlinker \
|
||||
-static \
|
||||
-Xlinker \
|
||||
-z \
|
||||
-Xlinker \
|
||||
muldefs \
|
||||
-Xlinker \
|
||||
-Map=output.map \
|
||||
-Wl,--print-memory-usage \
|
||||
-Xlinker \
|
||||
--defsym=__stack_size__=0x1000 \
|
||||
-Xlinker \
|
||||
--defsym=__heap_size__=0x1000 \
|
||||
-T${ProjDirPath}/MIMXRT1021xxxxx_flexspi_nor_sdram.ld -static \
|
||||
")
|
|
@ -0,0 +1,294 @@
|
|||
/*
|
||||
* Copyright 2018-2019 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_debug_console.h"
|
||||
#include "board.h"
|
||||
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
|
||||
#include "fsl_lpi2c.h"
|
||||
#endif /* SDK_I2C_BASED_COMPONENT_USED */
|
||||
#include "fsl_iomuxc.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
/* Get debug console frequency. */
|
||||
uint32_t BOARD_DebugConsoleSrcFreq(void)
|
||||
{
|
||||
uint32_t freq;
|
||||
|
||||
/* To make it simple, we assume default PLL and divider settings, and the only variable
|
||||
from application is use PLL3 source or OSC source */
|
||||
if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
|
||||
{
|
||||
freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
|
||||
}
|
||||
else
|
||||
{
|
||||
freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
|
||||
}
|
||||
|
||||
return freq;
|
||||
}
|
||||
|
||||
/* Initialize debug console. */
|
||||
void BOARD_InitDebugConsole(void)
|
||||
{
|
||||
uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
|
||||
|
||||
DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
|
||||
}
|
||||
|
||||
/* MPU configuration. */
|
||||
void BOARD_ConfigMPU(void)
|
||||
{
|
||||
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
|
||||
extern uint32_t Image$$RW_m_ncache$$Base[];
|
||||
/* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
|
||||
extern uint32_t Image$$RW_m_ncache_unused$$Base[];
|
||||
extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
|
||||
uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
|
||||
uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
|
||||
0 :
|
||||
((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
|
||||
#elif defined(__MCUXPRESSO)
|
||||
extern uint32_t __base_NCACHE_REGION;
|
||||
extern uint32_t __top_NCACHE_REGION;
|
||||
uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
|
||||
uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
|
||||
#elif defined(__ICCARM__) || defined(__GNUC__)
|
||||
extern uint32_t __NCACHE_REGION_START[];
|
||||
extern uint32_t __NCACHE_REGION_SIZE[];
|
||||
uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
|
||||
uint32_t size = (uint32_t)__NCACHE_REGION_SIZE;
|
||||
#endif
|
||||
volatile uint32_t i = 0;
|
||||
|
||||
/* Disable I cache and D cache */
|
||||
if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
|
||||
{
|
||||
SCB_DisableICache();
|
||||
}
|
||||
if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
|
||||
{
|
||||
SCB_DisableDCache();
|
||||
}
|
||||
|
||||
/* Disable MPU */
|
||||
ARM_MPU_Disable();
|
||||
|
||||
/* MPU configure:
|
||||
* Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
|
||||
* SubRegionDisable, Size)
|
||||
* API in mpu_armv7.h.
|
||||
* param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
|
||||
* disabled.
|
||||
* param AccessPermission Data access permissions, allows you to configure read/write access for User and
|
||||
* Privileged mode.
|
||||
* Use MACROS defined in mpu_armv7.h:
|
||||
* ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
|
||||
* Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
|
||||
* TypeExtField IsShareable IsCacheable IsBufferable Memory Attribute Shareability Cache
|
||||
* 0 x 0 0 Strongly Ordered shareable
|
||||
* 0 x 0 1 Device shareable
|
||||
* 0 0 1 0 Normal not shareable Outer and inner write
|
||||
* through no write allocate
|
||||
* 0 0 1 1 Normal not shareable Outer and inner write
|
||||
* back no write allocate
|
||||
* 0 1 1 0 Normal shareable Outer and inner write
|
||||
* through no write allocate
|
||||
* 0 1 1 1 Normal shareable Outer and inner write
|
||||
* back no write allocate
|
||||
* 1 0 0 0 Normal not shareable outer and inner
|
||||
* noncache
|
||||
* 1 1 0 0 Normal shareable outer and inner
|
||||
* noncache
|
||||
* 1 0 1 1 Normal not shareable outer and inner write
|
||||
* back write/read acllocate
|
||||
* 1 1 1 1 Normal shareable outer and inner write
|
||||
* back write/read acllocate
|
||||
* 2 x 0 0 Device not shareable
|
||||
* Above are normal use settings, if your want to see more details or want to config different inner/outter cache
|
||||
* policy.
|
||||
* please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
|
||||
* param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
|
||||
* param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
|
||||
* mpu_armv7.h.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Add default region to deny access to whole address space to workaround speculative prefetch.
|
||||
* Refer to Arm errata 1013783-B for more details.
|
||||
*
|
||||
*/
|
||||
/* Region 0 setting: Instruction access disabled, No data access permission. */
|
||||
MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 0, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
|
||||
|
||||
/* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
|
||||
MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
|
||||
|
||||
/* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */
|
||||
MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
|
||||
|
||||
#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
|
||||
/* Region 3 setting: Memory with Normal type, not shareable, outer/inner write back. */
|
||||
MPU->RBAR = ARM_MPU_RBAR(3, 0x60000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_8MB);
|
||||
#endif
|
||||
|
||||
/* Region 4 setting: Memory with Device type, not shareable, non-cacheable. */
|
||||
MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
|
||||
|
||||
/* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||||
MPU->RBAR = ARM_MPU_RBAR(5, 0x00000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64KB);
|
||||
|
||||
/* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||||
MPU->RBAR = ARM_MPU_RBAR(6, 0x20000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64KB);
|
||||
|
||||
/* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||||
MPU->RBAR = ARM_MPU_RBAR(7, 0x20200000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
|
||||
|
||||
/* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||||
MPU->RBAR = ARM_MPU_RBAR(8, 0x80000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
|
||||
|
||||
while ((size >> i) > 0x1U)
|
||||
{
|
||||
i++;
|
||||
}
|
||||
|
||||
if (i != 0)
|
||||
{
|
||||
/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
|
||||
assert(!(nonCacheStart % size));
|
||||
assert(size == (uint32_t)(1 << i));
|
||||
assert(i >= 5);
|
||||
|
||||
/* Region 9 setting: Memory with Normal type, not shareable, non-cacheable */
|
||||
MPU->RBAR = ARM_MPU_RBAR(9, nonCacheStart);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
|
||||
}
|
||||
|
||||
/* Region 10 setting: Memory with Device type, not shareable, non-cacheable */
|
||||
MPU->RBAR = ARM_MPU_RBAR(10, 0x40000000);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4MB);
|
||||
|
||||
/* Enable MPU */
|
||||
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
|
||||
|
||||
/* Enable I cache and D cache */
|
||||
SCB_EnableDCache();
|
||||
SCB_EnableICache();
|
||||
}
|
||||
|
||||
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
|
||||
void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
|
||||
{
|
||||
lpi2c_master_config_t lpi2cConfig = {0};
|
||||
|
||||
/*
|
||||
* lpi2cConfig.debugEnable = false;
|
||||
* lpi2cConfig.ignoreAck = false;
|
||||
* lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
|
||||
* lpi2cConfig.baudRate_Hz = 100000U;
|
||||
* lpi2cConfig.busIdleTimeout_ns = 0;
|
||||
* lpi2cConfig.pinLowTimeout_ns = 0;
|
||||
* lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
|
||||
* lpi2cConfig.sclGlitchFilterWidth_ns = 0;
|
||||
*/
|
||||
LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
|
||||
LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
|
||||
}
|
||||
|
||||
status_t BOARD_LPI2C_Send(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subAddressSize,
|
||||
uint8_t *txBuff,
|
||||
uint8_t txBuffSize)
|
||||
{
|
||||
lpi2c_master_transfer_t xfer;
|
||||
|
||||
xfer.flags = kLPI2C_TransferDefaultFlag;
|
||||
xfer.slaveAddress = deviceAddress;
|
||||
xfer.direction = kLPI2C_Write;
|
||||
xfer.subaddress = subAddress;
|
||||
xfer.subaddressSize = subAddressSize;
|
||||
xfer.data = txBuff;
|
||||
xfer.dataSize = txBuffSize;
|
||||
|
||||
return LPI2C_MasterTransferBlocking(base, &xfer);
|
||||
}
|
||||
|
||||
status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subAddressSize,
|
||||
uint8_t *rxBuff,
|
||||
uint8_t rxBuffSize)
|
||||
{
|
||||
lpi2c_master_transfer_t xfer;
|
||||
|
||||
xfer.flags = kLPI2C_TransferDefaultFlag;
|
||||
xfer.slaveAddress = deviceAddress;
|
||||
xfer.direction = kLPI2C_Read;
|
||||
xfer.subaddress = subAddress;
|
||||
xfer.subaddressSize = subAddressSize;
|
||||
xfer.data = rxBuff;
|
||||
xfer.dataSize = rxBuffSize;
|
||||
|
||||
return LPI2C_MasterTransferBlocking(base, &xfer);
|
||||
}
|
||||
|
||||
void BOARD_Accel_I2C_Init(void)
|
||||
{
|
||||
BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
|
||||
}
|
||||
|
||||
status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
|
||||
{
|
||||
uint8_t data = (uint8_t)txBuff;
|
||||
|
||||
return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
|
||||
}
|
||||
|
||||
status_t BOARD_Accel_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
|
||||
{
|
||||
return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
|
||||
}
|
||||
|
||||
void BOARD_Codec_I2C_Init(void)
|
||||
{
|
||||
BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
|
||||
}
|
||||
|
||||
status_t BOARD_Codec_I2C_Send(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
|
||||
{
|
||||
return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
|
||||
txBuffSize);
|
||||
}
|
||||
|
||||
status_t BOARD_Codec_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
|
||||
{
|
||||
return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
|
||||
}
|
||||
#endif /* SDK_I2C_BASED_COMPONENT_USED */
|
|
@ -0,0 +1,156 @@
|
|||
/*
|
||||
* Copyright 2018-2019 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _BOARD_H_
|
||||
#define _BOARD_H_
|
||||
|
||||
#include "clock_config.h"
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_gpio.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
/*! @brief The board name */
|
||||
#define BOARD_NAME "MIMXRT1020-EVK"
|
||||
|
||||
/* The UART to use for debug messages. */
|
||||
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
|
||||
#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1
|
||||
#define BOARD_DEBUG_UART_INSTANCE 1U
|
||||
|
||||
#define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
|
||||
|
||||
#define BOARD_UART_IRQ LPUART1_IRQn
|
||||
#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler
|
||||
|
||||
#ifndef BOARD_DEBUG_UART_BAUDRATE
|
||||
#define BOARD_DEBUG_UART_BAUDRATE (115200U)
|
||||
#endif /* BOARD_DEBUG_UART_BAUDRATE */
|
||||
|
||||
/* @Brief Board accelerator sensor configuration */
|
||||
#define BOARD_ACCEL_I2C_BASEADDR LPI2C4
|
||||
#define BOARD_ACCEL_I2C_CLOCK_SOURCE_SELECT (0U)
|
||||
#define BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER (5U)
|
||||
#define BOARD_ACCEL_I2C_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER + 1U))
|
||||
|
||||
#define BOARD_CODEC_I2C_BASEADDR LPI2C1
|
||||
#define BOARD_CODEC_I2C_INSTANCE 1U
|
||||
#define BOARD_CODEC_I2C_CLOCK_SOURCE_SELECT (0U)
|
||||
#define BOARD_CODEC_I2C_CLOCK_SOURCE_DIVIDER (5U)
|
||||
#define BOARD_CODEC_I2C_CLOCK_FREQ (10000000U)
|
||||
|
||||
/*! @brief The USER_LED used for board */
|
||||
#define LOGIC_LED_ON (0U)
|
||||
#define LOGIC_LED_OFF (1U)
|
||||
#ifndef BOARD_USER_LED_GPIO
|
||||
#define BOARD_USER_LED_GPIO GPIO1
|
||||
#endif
|
||||
#ifndef BOARD_USER_LED_GPIO_PIN
|
||||
#define BOARD_USER_LED_GPIO_PIN (5U)
|
||||
#endif
|
||||
|
||||
#define USER_LED_INIT(output) \
|
||||
GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, output); \
|
||||
BOARD_USER_LED_GPIO->GDIR |= (1U << BOARD_USER_LED_GPIO_PIN) /*!< Enable target USER_LED */
|
||||
#define USER_LED_ON() \
|
||||
GPIO_PortClear(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!< Turn off target USER_LED */
|
||||
#define USER_LED_OFF() GPIO_PortSet(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!<Turn on target USER_LED*/
|
||||
#define USER_LED_TOGGLE() \
|
||||
GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, \
|
||||
0x1 ^ GPIO_PinRead(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN)) /*!< Toggle target USER_LED */
|
||||
|
||||
/*! @brief Define the port interrupt number for the board switches */
|
||||
#ifndef BOARD_USER_BUTTON_GPIO
|
||||
#define BOARD_USER_BUTTON_GPIO GPIO5
|
||||
#endif
|
||||
#ifndef BOARD_USER_BUTTON_GPIO_PIN
|
||||
#define BOARD_USER_BUTTON_GPIO_PIN (0U)
|
||||
#endif
|
||||
#define BOARD_USER_BUTTON_IRQ GPIO5_Combined_0_15_IRQn
|
||||
#define BOARD_USER_BUTTON_IRQ_HANDLER GPIO5_Combined_0_15_IRQHandler
|
||||
#define BOARD_USER_BUTTON_NAME "SW4"
|
||||
|
||||
/*! @brief The hyper flash size */
|
||||
#define BOARD_FLASH_SIZE (0x800000U)
|
||||
|
||||
/*! @brief The ENET PHY address. */
|
||||
#define BOARD_ENET0_PHY_ADDRESS (0x02U) /* Phy address of enet port 0. */
|
||||
|
||||
/* USB PHY condfiguration */
|
||||
#define BOARD_USB_PHY_D_CAL (0x0CU)
|
||||
#define BOARD_USB_PHY_TXCAL45DP (0x06U)
|
||||
#define BOARD_USB_PHY_TXCAL45DM (0x06U)
|
||||
|
||||
#define BOARD_ARDUINO_INT_IRQ (GPIO1_Combined_16_31_IRQn)
|
||||
#define BOARD_ARDUINO_I2C_IRQ (LPI2C4_IRQn)
|
||||
#define BOARD_ARDUINO_I2C_INDEX (4)
|
||||
|
||||
/* Display. */
|
||||
#define BOARD_LCD_DC_GPIO GPIO1 /*! LCD data/command port */
|
||||
#define BOARD_LCD_DC_GPIO_PIN 15U /*! LCD data/command pin */
|
||||
|
||||
/* @Brief Board Bluetooth HCI UART configuration */
|
||||
#define BOARD_BT_UART_BASEADDR LPUART3
|
||||
#define BOARD_BT_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
|
||||
#define BOARD_BT_UART_IRQ LPUART3_IRQn
|
||||
#define BOARD_BT_UART_IRQ_HANDLER LPUART3_IRQHandler
|
||||
|
||||
/*! @brief board has sdcard */
|
||||
#define BOARD_HAS_SDCARD (1U)
|
||||
|
||||
/* Serial MWM WIFI */
|
||||
#define BOARD_SERIAL_MWM_PORT_CLK_FREQ BOARD_DebugConsoleSrcFreq()
|
||||
#define BOARD_SERIAL_MWM_PORT LPUART2
|
||||
#define BOARD_SERIAL_MWM_PORT_IRQn LPUART2_IRQn
|
||||
#define BOARD_SERIAL_MWM_RST_GPIO GPIO1
|
||||
#define BOARD_SERIAL_MWM_RST_PIN 22
|
||||
#define BOARD_SERIAL_MWM_RST_WRITE(output) GPIO_PinWrite(BOARD_SERIAL_MWM_RST_GPIO, BOARD_SERIAL_MWM_RST_PIN, output)
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
uint32_t BOARD_DebugConsoleSrcFreq(void);
|
||||
|
||||
void BOARD_InitDebugConsole(void);
|
||||
void BOARD_ConfigMPU(void);
|
||||
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
|
||||
void BOARD_InitDebugConsole(void);
|
||||
void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz);
|
||||
status_t BOARD_LPI2C_Send(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subaddressSize,
|
||||
uint8_t *txBuff,
|
||||
uint8_t txBuffSize);
|
||||
status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subaddressSize,
|
||||
uint8_t *rxBuff,
|
||||
uint8_t rxBuffSize);
|
||||
void BOARD_Accel_I2C_Init(void);
|
||||
status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
|
||||
status_t BOARD_Accel_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
|
||||
void BOARD_Codec_I2C_Init(void);
|
||||
status_t BOARD_Codec_I2C_Send(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
|
||||
status_t BOARD_Codec_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
|
||||
#endif /* SDK_I2C_BASED_COMPONENT_USED */
|
||||
void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength);
|
||||
void BOARD_MMC_Pin_Config(uint32_t speed, uint32_t strength);
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* _BOARD_H_ */
|
|
@ -0,0 +1,428 @@
|
|||
/*
|
||||
* Copyright 2018-2020,2021 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
/*
|
||||
* How to setup clock using clock driver functions:
|
||||
*
|
||||
* 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
|
||||
*
|
||||
* 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
|
||||
*
|
||||
* 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
|
||||
*
|
||||
* 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
|
||||
*
|
||||
* 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
|
||||
*
|
||||
*/
|
||||
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Clocks v8.0
|
||||
processor: MIMXRT1021xxxxx
|
||||
package_id: MIMXRT1021DAG5A
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 10.0.0
|
||||
board: MIMXRT1020-EVK
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
|
||||
#include "clock_config.h"
|
||||
#include "fsl_iomuxc.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/* System clock frequency. */
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
void BOARD_InitBootClocks(void)
|
||||
{
|
||||
BOARD_BootClockRUN();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
********************** Configuration BOARD_BootClockRUN ***********************
|
||||
******************************************************************************/
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockRUN
|
||||
called_from_default_init: true
|
||||
outputs:
|
||||
- {id: AHB_CLK_ROOT.outFreq, value: 500 MHz}
|
||||
- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
|
||||
- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
|
||||
- {id: CLK_1M.outFreq, value: 1 MHz}
|
||||
- {id: CLK_24M.outFreq, value: 24 MHz}
|
||||
- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
|
||||
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
|
||||
- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
|
||||
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
|
||||
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
|
||||
- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
|
||||
- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
|
||||
- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
|
||||
- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
|
||||
- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
|
||||
- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
|
||||
- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
|
||||
- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
|
||||
- {id: SEMC_CLK_ROOT.outFreq, value: 62.5 MHz}
|
||||
- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
|
||||
- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
|
||||
- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
|
||||
- {id: USDHC1_CLK_ROOT.outFreq, value: 176 MHz}
|
||||
- {id: USDHC2_CLK_ROOT.outFreq, value: 176 MHz}
|
||||
settings:
|
||||
- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
|
||||
- {id: CCM.ARM_PODF.scale, value: '1', locked: true}
|
||||
- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true}
|
||||
- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL2_PFD2_CLK}
|
||||
- {id: CCM.IPG_PODF.scale, value: '4'}
|
||||
- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
|
||||
- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
|
||||
- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM.ARM_PODF}
|
||||
- {id: CCM.SEMC_PODF.scale, value: '8'}
|
||||
- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
|
||||
- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
|
||||
- {id: CCM.USDHC1_PODF.scale, value: '3', locked: true}
|
||||
- {id: CCM.USDHC2_PODF.scale, value: '3', locked: true}
|
||||
- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
|
||||
- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
|
||||
- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
|
||||
- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
|
||||
- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
|
||||
- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
|
||||
- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
|
||||
- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
|
||||
- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
|
||||
- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
|
||||
- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
|
||||
- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
|
||||
- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
|
||||
- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
|
||||
- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
|
||||
- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
|
||||
- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
|
||||
- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
|
||||
- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
|
||||
- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
|
||||
- {id: CCM_ANALOG.PLL4.denom, value: '50'}
|
||||
- {id: CCM_ANALOG.PLL4.div, value: '47'}
|
||||
- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
|
||||
- {id: CCM_ANALOG_PLL_ENET_ENABLE_CFG, value: Disabled}
|
||||
- {id: CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_CFG, value: Disabled}
|
||||
- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
|
||||
sources:
|
||||
- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
|
||||
{
|
||||
.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
|
||||
.numerator = 0, /* 30 bit numerator of fractional loop divider */
|
||||
.denominator = 1, /* 30 bit denominator of fractional loop divider */
|
||||
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
|
||||
};
|
||||
const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
|
||||
{
|
||||
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
|
||||
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
|
||||
};
|
||||
const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN =
|
||||
{
|
||||
.enableClkOutput = false, /* Disable the PLL providing the ENET 125MHz reference clock */
|
||||
.enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */
|
||||
.enableClkOutput25M = false, /* Disable the PLL providing the ENET 25MHz reference clock */
|
||||
.loopDivider = 1, /* Set frequency of ethernet reference clock to 50 MHz */
|
||||
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
|
||||
};
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockRUN(void)
|
||||
{
|
||||
/* Init RTC OSC clock frequency. */
|
||||
CLOCK_SetRtcXtalFreq(32768U);
|
||||
/* Enable 1MHz clock output. */
|
||||
XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
|
||||
/* Use free 1MHz clock output. */
|
||||
XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
|
||||
/* Set XTAL 24MHz clock frequency. */
|
||||
CLOCK_SetXtalFreq(24000000U);
|
||||
/* Enable XTAL 24MHz clock source. */
|
||||
CLOCK_InitExternalClk(0);
|
||||
/* Enable internal RC. */
|
||||
CLOCK_InitRcOsc24M();
|
||||
/* Switch clock source to external OSC. */
|
||||
CLOCK_SwitchOsc(kCLOCK_XtalOsc);
|
||||
/* Set Oscillator ready counter value. */
|
||||
CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
|
||||
/* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
|
||||
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
|
||||
CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
|
||||
/* Setting the VDD_SOC to 1.25V. It is necessary to config AHB to 500Mhz. */
|
||||
DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
|
||||
/* Waiting for DCDC_STS_DC_OK bit is asserted */
|
||||
while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
|
||||
{
|
||||
}
|
||||
/* Set AHB_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
|
||||
/* Disable IPG clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Adc1);
|
||||
CLOCK_DisableClock(kCLOCK_Adc2);
|
||||
CLOCK_DisableClock(kCLOCK_Xbar1);
|
||||
CLOCK_DisableClock(kCLOCK_Xbar2);
|
||||
/* Set IPG_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
|
||||
/* Set ARM_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_ArmDiv, 0);
|
||||
/* Set PERIPH_CLK2_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
|
||||
/* Disable PERCLK clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Gpt1);
|
||||
CLOCK_DisableClock(kCLOCK_Gpt1S);
|
||||
CLOCK_DisableClock(kCLOCK_Gpt2);
|
||||
CLOCK_DisableClock(kCLOCK_Gpt2S);
|
||||
CLOCK_DisableClock(kCLOCK_Pit);
|
||||
/* Set PERCLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
|
||||
/* Disable USDHC1 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Usdhc1);
|
||||
/* Set USDHC1_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Usdhc1Div, 2);
|
||||
/* Set Usdhc1 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
|
||||
/* Disable USDHC2 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Usdhc2);
|
||||
/* Set USDHC2_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Usdhc2Div, 2);
|
||||
/* Set Usdhc2 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
|
||||
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
|
||||
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
|
||||
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
|
||||
#ifndef SKIP_SYSCLK_INIT
|
||||
/* Disable Semc clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Semc);
|
||||
/* Set SEMC_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
|
||||
/* Set Semc alt clock source. */
|
||||
CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
|
||||
/* Set Semc clock source. */
|
||||
CLOCK_SetMux(kCLOCK_SemcMux, 0);
|
||||
#endif
|
||||
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
|
||||
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
|
||||
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
|
||||
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
|
||||
/* Disable Flexspi clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_FlexSpi);
|
||||
/* Set FLEXSPI_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
|
||||
/* Set Flexspi clock source. */
|
||||
CLOCK_SetMux(kCLOCK_FlexspiMux, 2);
|
||||
#endif
|
||||
/* Disable LPSPI clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Lpspi1);
|
||||
CLOCK_DisableClock(kCLOCK_Lpspi2);
|
||||
CLOCK_DisableClock(kCLOCK_Lpspi3);
|
||||
CLOCK_DisableClock(kCLOCK_Lpspi4);
|
||||
/* Set LPSPI_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
|
||||
/* Set Lpspi clock source. */
|
||||
CLOCK_SetMux(kCLOCK_LpspiMux, 2);
|
||||
/* Disable TRACE clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Trace);
|
||||
/* Set TRACE_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
|
||||
/* Set Trace clock source. */
|
||||
CLOCK_SetMux(kCLOCK_TraceMux, 0);
|
||||
/* Disable SAI1 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Sai1);
|
||||
/* Set SAI1_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
|
||||
/* Set SAI1_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
|
||||
/* Set Sai1 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
|
||||
/* Disable SAI2 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Sai2);
|
||||
/* Set SAI2_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
|
||||
/* Set SAI2_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
|
||||
/* Set Sai2 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
|
||||
/* Disable SAI3 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Sai3);
|
||||
/* Set SAI3_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
|
||||
/* Set SAI3_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
|
||||
/* Set Sai3 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
|
||||
/* Disable Lpi2c clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Lpi2c1);
|
||||
CLOCK_DisableClock(kCLOCK_Lpi2c2);
|
||||
CLOCK_DisableClock(kCLOCK_Lpi2c3);
|
||||
/* Set LPI2C_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
|
||||
/* Set Lpi2c clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
|
||||
/* Disable CAN clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Can1);
|
||||
CLOCK_DisableClock(kCLOCK_Can2);
|
||||
CLOCK_DisableClock(kCLOCK_Can1S);
|
||||
CLOCK_DisableClock(kCLOCK_Can2S);
|
||||
/* Set CAN_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_CanDiv, 1);
|
||||
/* Set Can clock source. */
|
||||
CLOCK_SetMux(kCLOCK_CanMux, 2);
|
||||
/* Disable UART clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart1);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart2);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart3);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart4);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart5);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart6);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart7);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart8);
|
||||
/* Set UART_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_UartDiv, 0);
|
||||
/* Set Uart clock source. */
|
||||
CLOCK_SetMux(kCLOCK_UartMux, 0);
|
||||
/* Disable SPDIF clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Spdif);
|
||||
/* Set SPDIF0_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
|
||||
/* Set SPDIF0_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
|
||||
/* Set Spdif clock source. */
|
||||
CLOCK_SetMux(kCLOCK_SpdifMux, 3);
|
||||
/* Disable Flexio1 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Flexio1);
|
||||
/* Set FLEXIO1_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
|
||||
/* Set FLEXIO1_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
|
||||
/* Set Flexio1 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
|
||||
/* Set Pll3 sw clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
|
||||
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
|
||||
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
|
||||
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
|
||||
#ifndef SKIP_SYSCLK_INIT
|
||||
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
|
||||
#warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
|
||||
#endif
|
||||
/* Init System PLL. */
|
||||
CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
|
||||
/* Init System pfd0. */
|
||||
CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
|
||||
/* Init System pfd1. */
|
||||
CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
|
||||
/* Init System pfd2. */
|
||||
CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
|
||||
/* Init System pfd3. */
|
||||
CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
|
||||
#endif
|
||||
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
|
||||
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
|
||||
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
|
||||
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
|
||||
/* Init Usb1 PLL. */
|
||||
CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
|
||||
/* Init Usb1 pfd0. */
|
||||
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
|
||||
/* Init Usb1 pfd1. */
|
||||
CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
|
||||
/* Init Usb1 pfd2. */
|
||||
CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
|
||||
/* Init Usb1 pfd3. */
|
||||
CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
|
||||
/* Disable Usb1 PLL output for USBPHY1. */
|
||||
CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
|
||||
#endif
|
||||
/* DeInit Audio PLL. */
|
||||
CLOCK_DeinitAudioPll();
|
||||
/* Bypass Audio PLL. */
|
||||
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
|
||||
/* Set divider for Audio PLL. */
|
||||
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
|
||||
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
|
||||
/* Enable Audio PLL output. */
|
||||
CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
|
||||
/* Init Enet PLL. */
|
||||
CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
|
||||
/* Set preperiph clock source. */
|
||||
CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
|
||||
/* Set periph clock source. */
|
||||
CLOCK_SetMux(kCLOCK_PeriphMux, 0);
|
||||
/* Set periph clock2 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
|
||||
/* Set per clock source. */
|
||||
CLOCK_SetMux(kCLOCK_PerclkMux, 0);
|
||||
/* Set clock out1 divider. */
|
||||
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
|
||||
/* Set clock out1 source. */
|
||||
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
|
||||
/* Set clock out2 divider. */
|
||||
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
|
||||
/* Set clock out2 source. */
|
||||
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(3);
|
||||
/* Set clock out1 drives clock out1. */
|
||||
CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
|
||||
/* Disable clock out1. */
|
||||
CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
|
||||
/* Disable clock out2. */
|
||||
CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
|
||||
/* Set SAI1 MCLK1 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
|
||||
/* Set SAI1 MCLK2 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
|
||||
/* Set SAI1 MCLK3 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
|
||||
/* Set SAI2 MCLK3 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
|
||||
/* Set SAI3 MCLK3 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
|
||||
/* Set MQS configuration. */
|
||||
IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
|
||||
/* Set ENET Ref clock source. */
|
||||
#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK)
|
||||
IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK;
|
||||
#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
|
||||
/* Backward compatibility for original bitfield name */
|
||||
IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
|
||||
#else
|
||||
#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined."
|
||||
#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */
|
||||
/* Set GPT1 High frequency reference clock source. */
|
||||
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
|
||||
/* Set GPT2 High frequency reference clock source. */
|
||||
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
|
||||
/* Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
|
||||
}
|
|
@ -0,0 +1,114 @@
|
|||
/*
|
||||
* Copyright 2018-2020,2021 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _CLOCK_CONFIG_H_
|
||||
#define _CLOCK_CONFIG_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
|
||||
|
||||
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes default configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootClocks(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
********************** Configuration BOARD_BootClockRUN ***********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */
|
||||
|
||||
/* Clock outputs (values are in Hz): */
|
||||
#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 500000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
|
||||
#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL
|
||||
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL
|
||||
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
|
||||
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 62500000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 176000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 176000000UL
|
||||
|
||||
/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
|
||||
/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
|
||||
/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockRUN(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
#endif /* _CLOCK_CONFIG_H_ */
|
|
@ -0,0 +1,302 @@
|
|||
/*
|
||||
* Copyright 2020-2021 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#include "dcd.h"
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
|
||||
#endif
|
||||
|
||||
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
|
||||
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
|
||||
__attribute__((section(".boot_hdr.dcd_data"), used))
|
||||
#elif defined(__ICCARM__)
|
||||
#pragma location = ".boot_hdr.dcd_data"
|
||||
#endif
|
||||
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: DCDx V2.0
|
||||
processor: MIMXRT1021xxxxx
|
||||
package_id: MIMXRT1021DAG5A
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 9.0.1
|
||||
output_format: c_array
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */
|
||||
const uint8_t dcd_data[] = {
|
||||
/* HEADER */
|
||||
/* Tag */
|
||||
0xD2,
|
||||
/* Image Length */
|
||||
0x03, 0xE0,
|
||||
/* Version */
|
||||
0x41,
|
||||
|
||||
/* COMMANDS */
|
||||
|
||||
/* group: 'Imported Commands' */
|
||||
/* #1.1-107, command header bytes for merged 'Write - value' command */
|
||||
0xCC, 0x03, 0x5C, 0x04,
|
||||
/* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
/* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
/* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
/* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
/* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
/* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
/* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
/* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */
|
||||
0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01,
|
||||
/* #1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x1018101B, size: 4 */
|
||||
0x40, 0x0D, 0x81, 0x00, 0x10, 0x18, 0x10, 0x1B,
|
||||
/* #1.10, command: write_value, address: CCM_CBCDR, value: 0xA8340, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x14, 0x00, 0x0A, 0x83, 0x40,
|
||||
/* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x10, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x10,
|
||||
/* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0x88, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0x8C, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0x90, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0x94, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0x98, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0x9C, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xA0, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xA4, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xA8, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xAC, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xB0, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xB4, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xB8, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xBC, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xC0, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xC4, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xC8, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xCC, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xD0, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xD4, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xD8, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xDC, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xE0, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xE4, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xE8, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xEC, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xF0, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xF4, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xF8, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x81, 0xFC, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x00, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x04, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x08, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x0C, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x10, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x14, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x18, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x1C, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x20, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0xE1, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x24, 0x00, 0x00, 0x00, 0xE1,
|
||||
/* #1.91, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04,
|
||||
/* #1.92, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81,
|
||||
/* #1.93, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81,
|
||||
/* #1.94, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B,
|
||||
/* #1.95, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B,
|
||||
/* #1.96, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B,
|
||||
/* #1.97, command: write_value, address: SEMC_IOCR, value: 0x7988, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0x88,
|
||||
/* #1.98, command: write_value, address: SEMC_SDRAMCR0, value: 0xF07, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x07,
|
||||
/* #1.99, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22,
|
||||
/* #1.100, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20,
|
||||
/* #1.101, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08,
|
||||
/* #1.102, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21,
|
||||
/* #1.103, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88,
|
||||
/* #1.104, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02,
|
||||
/* #1.105, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.106, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
|
||||
/* #1.107, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F,
|
||||
/* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
|
||||
0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
|
||||
/* #3.1-2, command header bytes for merged 'Write - value' command */
|
||||
0xCC, 0x00, 0x14, 0x04,
|
||||
/* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
|
||||
/* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
|
||||
/* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
|
||||
0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
|
||||
/* #5.1-2, command header bytes for merged 'Write - value' command */
|
||||
0xCC, 0x00, 0x14, 0x04,
|
||||
/* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
|
||||
/* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
|
||||
/* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
|
||||
0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
|
||||
/* #7.1-3, command header bytes for merged 'Write - value' command */
|
||||
0xCC, 0x00, 0x1C, 0x04,
|
||||
/* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x30, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x30,
|
||||
/* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
|
||||
/* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A,
|
||||
/* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
|
||||
0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
|
||||
/* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */
|
||||
0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09
|
||||
};
|
||||
/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */
|
||||
|
||||
#else
|
||||
const uint8_t dcd_data[] = {0x00};
|
||||
#endif /* XIP_BOOT_HEADER_DCD_ENABLE */
|
||||
#endif /* XIP_BOOT_HEADER_ENABLE */
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* Copyright 2020 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef __DCD__
|
||||
#define __DCD__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief XIP_BOARD driver version 2.0.1. */
|
||||
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
|
||||
/*@}*/
|
||||
|
||||
/*************************************
|
||||
* DCD Data
|
||||
*************************************/
|
||||
#define DCD_TAG_HEADER (0xD2)
|
||||
#define DCD_VERSION (0x41)
|
||||
#define DCD_TAG_HEADER_SHIFT (24)
|
||||
#define DCD_ARRAY_SIZE 1
|
||||
|
||||
#endif /* __DCD__ */
|
|
@ -0,0 +1,236 @@
|
|||
/*
|
||||
* Copyright 2018-2020 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
void Clock_Init()
|
||||
{
|
||||
unsigned int reg;
|
||||
// Enable all clocks
|
||||
MEM_WriteU32(0x400FC068,0xffffffff);
|
||||
MEM_WriteU32(0x400FC06C,0xffffffff);
|
||||
MEM_WriteU32(0x400FC070,0xffffffff);
|
||||
MEM_WriteU32(0x400FC074,0xffffffff);
|
||||
MEM_WriteU32(0x400FC078,0xffffffff);
|
||||
MEM_WriteU32(0x400FC07C,0xffffffff);
|
||||
MEM_WriteU32(0x400FC080,0xffffffff);
|
||||
|
||||
// IPG_PODF: 2 divide by 3
|
||||
MEM_WriteU32(0x400FC014,0x000A8200);
|
||||
// PERCLK_PODF: 1 divide by 2
|
||||
MEM_WriteU32(0x400FC01C,0x04900001);
|
||||
// Enable SYS PLL but keep it bypassed.
|
||||
MEM_WriteU32(0x400D8030,0x00012001);
|
||||
do
|
||||
{
|
||||
reg = MEM_ReadU32(0x400D8030);
|
||||
} while((reg & 0x80000000) == 0);
|
||||
// Disable bypass of SYS PLL
|
||||
MEM_WriteU32(0x400D8030,0x00002001);
|
||||
|
||||
// PFD2_FRAC: 24, PLL2 PFD2=528*18/PFD2_FRAC=396
|
||||
// Ungate SYS PLL PFD2
|
||||
reg = MEM_ReadU32(0x400D8100);
|
||||
reg &= ~0xBF0000;
|
||||
reg |= 0x180000;
|
||||
MEM_WriteU32(0x400D8100, reg);
|
||||
|
||||
// SEMC_ALT_CLK_SEL: 0 PLL2 (SYS PLL) PFD2
|
||||
// SEMC_CLK_SEL: 1 SEMC_ALT_CLK
|
||||
// SEMC_PODF: 2 divide by 3
|
||||
reg = MEM_ReadU32(0x400FC014);
|
||||
reg &= ~0x700C0;
|
||||
reg |= 0x20040;
|
||||
MEM_WriteU32(0x400FC014, reg);
|
||||
|
||||
// Disable MPU which will be enabled by ROM to prevent code execution
|
||||
reg = MEM_ReadU32(0xE000ED94);
|
||||
reg &= ~0x1;
|
||||
MEM_WriteU32(0xE000ED94, reg);
|
||||
|
||||
Report("Clock Init Done");
|
||||
}
|
||||
|
||||
void SDRAM_WaitIpCmdDone(void)
|
||||
{
|
||||
unsigned int reg;
|
||||
do
|
||||
{
|
||||
reg = MEM_ReadU32(0x402F003C);
|
||||
}while((reg & 0x3) == 0);
|
||||
}
|
||||
|
||||
void SDRAM_Init() {
|
||||
// Config IOMUX for SDRAM
|
||||
MEM_WriteU32(0x401F8014,0x00000000); // EMC_00
|
||||
MEM_WriteU32(0x401F8018,0x00000000); // EMC_01
|
||||
MEM_WriteU32(0x401F801C,0x00000000); // EMC_02
|
||||
MEM_WriteU32(0x401F8020,0x00000000); // EMC_03
|
||||
MEM_WriteU32(0x401F8024,0x00000000); // EMC_04
|
||||
MEM_WriteU32(0x401F8028,0x00000000); // EMC_05
|
||||
MEM_WriteU32(0x401F802C,0x00000000); // EMC_06
|
||||
MEM_WriteU32(0x401F8030,0x00000000); // EMC_07
|
||||
MEM_WriteU32(0x401F8034,0x00000000); // EMC_08
|
||||
MEM_WriteU32(0x401F8038,0x00000000); // EMC_09
|
||||
MEM_WriteU32(0x401F803C,0x00000000); // EMC_10
|
||||
MEM_WriteU32(0x401F8040,0x00000000); // EMC_11
|
||||
MEM_WriteU32(0x401F8044,0x00000000); // EMC_12
|
||||
MEM_WriteU32(0x401F8048,0x00000000); // EMC_13
|
||||
MEM_WriteU32(0x401F804C,0x00000000); // EMC_14
|
||||
MEM_WriteU32(0x401F8050,0x00000000); // EMC_15
|
||||
MEM_WriteU32(0x401F8054,0x00000000); // EMC_16
|
||||
MEM_WriteU32(0x401F8058,0x00000000); // EMC_17
|
||||
MEM_WriteU32(0x401F805C,0x00000000); // EMC_18
|
||||
MEM_WriteU32(0x401F8060,0x00000000); // EMC_19
|
||||
MEM_WriteU32(0x401F8064,0x00000000); // EMC_20
|
||||
MEM_WriteU32(0x401F8068,0x00000000); // EMC_21
|
||||
MEM_WriteU32(0x401F806C,0x00000000); // EMC_22
|
||||
MEM_WriteU32(0x401F8070,0x00000000); // EMC_23
|
||||
MEM_WriteU32(0x401F8074,0x00000000); // EMC_24
|
||||
MEM_WriteU32(0x401F8078,0x00000000); // EMC_25
|
||||
MEM_WriteU32(0x401F807C,0x00000000); // EMC_26
|
||||
MEM_WriteU32(0x401F8080,0x00000000); // EMC_27
|
||||
MEM_WriteU32(0x401F8084,0x00000010); // EMC_28, DQS PIN, enable SION
|
||||
MEM_WriteU32(0x401F8088,0x00000000); // EMC_29
|
||||
MEM_WriteU32(0x401F808C,0x00000000); // EMC_30
|
||||
MEM_WriteU32(0x401F8090,0x00000000); // EMC_31
|
||||
MEM_WriteU32(0x401F8094,0x00000000); // EMC_32
|
||||
MEM_WriteU32(0x401F8098,0x00000000); // EMC_33
|
||||
MEM_WriteU32(0x401F809C,0x00000000); // EMC_34
|
||||
MEM_WriteU32(0x401F80A0,0x00000000); // EMC_35
|
||||
MEM_WriteU32(0x401F80A4,0x00000000); // EMC_36
|
||||
MEM_WriteU32(0x401F80A8,0x00000000); // EMC_37
|
||||
MEM_WriteU32(0x401F80AC,0x00000000); // EMC_38
|
||||
MEM_WriteU32(0x401F80B0,0x00000000); // EMC_39
|
||||
|
||||
// PAD ctrl
|
||||
// drive strength = 0x7 to increase drive strength
|
||||
// otherwise the data7 bit may fail.
|
||||
MEM_WriteU32(0x401F8188,0x000000F1); // EMC_00
|
||||
MEM_WriteU32(0x401F818C,0x000000F1); // EMC_01
|
||||
MEM_WriteU32(0x401F8190,0x000000F1); // EMC_02
|
||||
MEM_WriteU32(0x401F8194,0x000000F1); // EMC_03
|
||||
MEM_WriteU32(0x401F8198,0x000000F1); // EMC_04
|
||||
MEM_WriteU32(0x401F819C,0x000000F1); // EMC_05
|
||||
MEM_WriteU32(0x401F81A0,0x000000F1); // EMC_06
|
||||
MEM_WriteU32(0x401F81A4,0x000000F1); // EMC_07
|
||||
MEM_WriteU32(0x401F81A8,0x000000F1); // EMC_08
|
||||
MEM_WriteU32(0x401F81AC,0x000000F1); // EMC_09
|
||||
MEM_WriteU32(0x401F81B0,0x000000F1); // EMC_10
|
||||
MEM_WriteU32(0x401F81B4,0x000000F1); // EMC_11
|
||||
MEM_WriteU32(0x401F81B8,0x000000F1); // EMC_12
|
||||
MEM_WriteU32(0x401F81BC,0x000000F1); // EMC_13
|
||||
MEM_WriteU32(0x401F81C0,0x000000F1); // EMC_14
|
||||
MEM_WriteU32(0x401F81C4,0x000000F1); // EMC_15
|
||||
MEM_WriteU32(0x401F81C8,0x000000F1); // EMC_16
|
||||
MEM_WriteU32(0x401F81CC,0x000000F1); // EMC_17
|
||||
MEM_WriteU32(0x401F81D0,0x000000F1); // EMC_18
|
||||
MEM_WriteU32(0x401F81D4,0x000000F1); // EMC_19
|
||||
MEM_WriteU32(0x401F81D8,0x000000F1); // EMC_20
|
||||
MEM_WriteU32(0x401F81DC,0x000000F1); // EMC_21
|
||||
MEM_WriteU32(0x401F81E0,0x000000F1); // EMC_22
|
||||
MEM_WriteU32(0x401F81E4,0x000000F1); // EMC_23
|
||||
MEM_WriteU32(0x401F81E8,0x000000F1); // EMC_24
|
||||
MEM_WriteU32(0x401F81EC,0x000000F1); // EMC_25
|
||||
MEM_WriteU32(0x401F81F0,0x000000F1); // EMC_26
|
||||
MEM_WriteU32(0x401F81F4,0x000000F1); // EMC_27
|
||||
MEM_WriteU32(0x401F81F8,0x000000F1); // EMC_28
|
||||
MEM_WriteU32(0x401F81FC,0x000000F1); // EMC_29
|
||||
MEM_WriteU32(0x401F8200,0x000000F1); // EMC_30
|
||||
MEM_WriteU32(0x401F8204,0x000000F1); // EMC_31
|
||||
MEM_WriteU32(0x401F8208,0x000000F1); // EMC_32
|
||||
MEM_WriteU32(0x401F820C,0x000000F1); // EMC_33
|
||||
MEM_WriteU32(0x401F8210,0x000000F1); // EMC_34
|
||||
MEM_WriteU32(0x401F8214,0x000000F1); // EMC_35
|
||||
MEM_WriteU32(0x401F8218,0x000000F1); // EMC_36
|
||||
MEM_WriteU32(0x401F821C,0x000000F1); // EMC_37
|
||||
MEM_WriteU32(0x401F8220,0x000000F1); // EMC_38
|
||||
MEM_WriteU32(0x401F8224,0x000000F1); // EMC_39
|
||||
|
||||
// Config SDR Controller Registers/
|
||||
MEM_WriteU32(0x402F0000,0x10000004); // MCR
|
||||
MEM_WriteU32(0x402F0008,0x00000081); // BMCR0
|
||||
MEM_WriteU32(0x402F000C,0x00000081); // BMCR1
|
||||
MEM_WriteU32(0x402F0010,0x8000001B); // BR0, 32MB
|
||||
MEM_WriteU32(0x402F0014,0x8200001B); // BR1, 32MB
|
||||
MEM_WriteU32(0x402F0018,0x8400001B); // BR2, 32MB
|
||||
MEM_WriteU32(0x402F001C,0x8600001B); // BR3, 32MB
|
||||
MEM_WriteU32(0x402F0020,0x90000021); // BR4,
|
||||
MEM_WriteU32(0x402F0024,0xA0000019); // BR5,
|
||||
MEM_WriteU32(0x402F0028,0xA8000017); // BR6,
|
||||
MEM_WriteU32(0x402F002C,0xA900001B); // BR7,
|
||||
MEM_WriteU32(0x402F0030,0x00000021); // BR8,
|
||||
MEM_WriteU32(0x402F0004,0x000079A8); //IOCR,SEMC_CCSX0 as NOR CE, SEMC_CSX1 as PSRAM CE, SEMC_CSX2 as NAND CE, SEMC_CSX3 as DBI CE.
|
||||
|
||||
// MEM_WriteU32(0x402F0004,0x00000008); // IOCR, SEMC_CCSX0 as SDRAM_CS1
|
||||
MEM_WriteU32(0x402F0040,0x00000F31); // SDRAMCR0
|
||||
MEM_WriteU32(0x402F0044,0x00652922); // SDRAMCR1
|
||||
MEM_WriteU32(0x402F0048,0x00010920); // SDRAMCR2
|
||||
MEM_WriteU32(0x402F004C,0x50210A09); // SDRAMCR3
|
||||
|
||||
MEM_WriteU32(0x402F0080,0x00000021); // DBICR0
|
||||
MEM_WriteU32(0x402F0084,0x00888888); // DBICR1
|
||||
MEM_WriteU32(0x402F0094,0x00000002); // IPCR1
|
||||
MEM_WriteU32(0x402F0098,0x00000000); // IPCR2
|
||||
|
||||
MEM_WriteU32(0x402F0090,0x80000000); // IPCR0
|
||||
MEM_WriteU32(0x402F009C,0xA55A000F); // IPCMD, SD_CC_IPREA
|
||||
SDRAM_WaitIpCmdDone();
|
||||
MEM_WriteU32(0x402F0090,0x80000000); // IPCR0
|
||||
MEM_WriteU32(0x402F009C,0xA55A000C); // SD_CC_IAF
|
||||
SDRAM_WaitIpCmdDone();
|
||||
MEM_WriteU32(0x402F0090,0x80000000); // IPCR0
|
||||
MEM_WriteU32(0x402F009C,0xA55A000C); // SD_CC_IAF
|
||||
SDRAM_WaitIpCmdDone();
|
||||
MEM_WriteU32(0x402F00A0,0x00000033); // IPTXDAT
|
||||
MEM_WriteU32(0x402F0090,0x80000000); // IPCR0
|
||||
MEM_WriteU32(0x402F009C,0xA55A000A); // SD_CC_IMS
|
||||
SDRAM_WaitIpCmdDone();
|
||||
MEM_WriteU32(0x402F004C,0x50210A09 ); // enable sdram self refresh again after initialization done.
|
||||
|
||||
Report("SDRAM Init Done");
|
||||
}
|
||||
|
||||
void RestoreFlexRAM()
|
||||
{
|
||||
unsigned int base;
|
||||
unsigned int value;
|
||||
|
||||
base = 0x400AC000;
|
||||
|
||||
value = MEM_ReadU32(base + 0x44);
|
||||
value &= ~(0xFFFF);
|
||||
value |= 0x5FA5;
|
||||
MEM_WriteU32(base + 0x44, value);
|
||||
|
||||
value = MEM_ReadU32(base + 0x40);
|
||||
value |= (1 << 2);
|
||||
MEM_WriteU32(base + 0x40, value);
|
||||
Report("FlexRAM configuration is restored");
|
||||
}
|
||||
|
||||
/* ConfigTarget */
|
||||
void ConfigTargetSettings(void)
|
||||
{
|
||||
Report("Config JTAG Speed to 4000kHz");
|
||||
JTAG_Speed = 4000;
|
||||
}
|
||||
|
||||
/* SetupTarget */
|
||||
void SetupTarget(void) {
|
||||
|
||||
Report("Enabling i.MXRT SDRAM");
|
||||
RestoreFlexRAM();
|
||||
Clock_Init();
|
||||
SDRAM_Init();
|
||||
}
|
||||
|
||||
/* AfterResetTarget */
|
||||
void AfterResetTarget(void) {
|
||||
|
||||
RestoreFlexRAM();
|
||||
Clock_Init();
|
||||
SDRAM_Init();
|
||||
}
|
|
@ -0,0 +1,115 @@
|
|||
/*
|
||||
* Copyright 2018 ,2021 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Pins v9.0
|
||||
processor: MIMXRT1021xxxxx
|
||||
package_id: MIMXRT1021DAG5A
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 9.0.1
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_iomuxc.h"
|
||||
#include "pin_mux.h"
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitBootPins
|
||||
* Description : Calls initialization functions.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitBootPins(void) {
|
||||
BOARD_InitPins();
|
||||
}
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitPins:
|
||||
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: '101', peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_07, slew_rate: Slow, software_input_on: Disable, open_drain: Disable, speed: MHZ_100,
|
||||
drive_strength: R0_6, pull_keeper_select: Keeper, pull_keeper_enable: Enable, pull_up_down_config: Pull_Down_100K_Ohm, hysteresis_enable: Disable}
|
||||
- {pin_num: '105', peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_06, slew_rate: Slow, software_input_on: Disable, open_drain: Disable, speed: MHZ_100,
|
||||
drive_strength: R0_6, pull_keeper_select: Keeper, pull_keeper_enable: Enable, pull_up_down_config: Pull_Down_100K_Ohm, hysteresis_enable: Disable}
|
||||
- {pin_num: '98', peripheral: ENET, signal: 'enet_rx_data, 0', pin_signal: GPIO_AD_B0_10, slew_rate: Fast, software_input_on: Disable, open_drain: Disable, speed: MHZ_200,
|
||||
drive_strength: R0_5, pull_keeper_select: Pull, pull_keeper_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, hysteresis_enable: Disable}
|
||||
- {pin_num: '99', peripheral: ENET, signal: 'enet_rx_data, 1', pin_signal: GPIO_AD_B0_09, slew_rate: Fast, software_input_on: Disable, open_drain: Disable, speed: MHZ_200,
|
||||
drive_strength: R0_5, pull_keeper_select: Pull, pull_keeper_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, hysteresis_enable: Disable}
|
||||
- {pin_num: '97', peripheral: ENET, signal: enet_rx_en, pin_signal: GPIO_AD_B0_11, slew_rate: Fast, software_input_on: Disable, open_drain: Disable, speed: MHZ_200,
|
||||
drive_strength: R0_5, pull_keeper_select: Pull, pull_keeper_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, hysteresis_enable: Disable}
|
||||
- {pin_num: '94', peripheral: ENET, signal: 'enet_tx_data, 0', pin_signal: GPIO_AD_B0_14, slew_rate: Fast, software_input_on: Disable, open_drain: Disable, speed: MHZ_200,
|
||||
drive_strength: R0_5, pull_keeper_select: Pull, pull_keeper_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, hysteresis_enable: Disable}
|
||||
- {pin_num: '93', peripheral: ENET, signal: 'enet_tx_data, 1', pin_signal: GPIO_AD_B0_15, slew_rate: Fast, software_input_on: Disable, open_drain: Disable, speed: MHZ_200,
|
||||
drive_strength: R0_5, pull_keeper_select: Pull, pull_keeper_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, hysteresis_enable: Disable}
|
||||
- {pin_num: '95', peripheral: ENET, signal: enet_tx_en, pin_signal: GPIO_AD_B0_13, slew_rate: Fast, software_input_on: Disable, open_drain: Disable, speed: MHZ_200,
|
||||
drive_strength: R0_5, pull_keeper_select: Pull, pull_keeper_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, hysteresis_enable: Disable}
|
||||
- {pin_num: '100', peripheral: ENET, signal: enet_ref_clk, pin_signal: GPIO_AD_B0_08, slew_rate: Fast, software_input_on: Enable, open_drain: Disable, speed: MHZ_200,
|
||||
drive_strength: R0_5, pull_keeper_select: Pull, pull_keeper_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, hysteresis_enable: Disable}
|
||||
- {pin_num: '96', peripheral: ENET, signal: enet_rx_er, pin_signal: GPIO_AD_B0_12, slew_rate: Fast, software_input_on: Disable, open_drain: Disable, speed: MHZ_200,
|
||||
drive_strength: R0_5, pull_keeper_select: Pull, pull_keeper_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, hysteresis_enable: Disable}
|
||||
- {pin_num: '116', peripheral: ENET, signal: enet_mdio, pin_signal: GPIO_EMC_40, slew_rate: Fast, software_input_on: Disable, open_drain: Disable, speed: MHZ_200,
|
||||
drive_strength: R0_5, pull_keeper_select: Pull, pull_keeper_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, hysteresis_enable: Disable}
|
||||
- {pin_num: '115', peripheral: ENET, signal: enet_mdc, pin_signal: GPIO_EMC_41, slew_rate: Fast, software_input_on: Disable, open_drain: Disable, speed: MHZ_200,
|
||||
drive_strength: R0_5, pull_keeper_select: Pull, pull_keeper_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, hysteresis_enable: Disable}
|
||||
- {pin_num: '107', peripheral: GPIO1, signal: 'gpio_io, 04', pin_signal: GPIO_AD_B0_04, slew_rate: Fast, software_input_on: Disable, open_drain: Disable, speed: MHZ_100,
|
||||
drive_strength: R0_5, pull_keeper_select: Pull, pull_keeper_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, hysteresis_enable: Disable}
|
||||
- {pin_num: '84', peripheral: GPIO1, signal: 'gpio_io, 22', pin_signal: GPIO_AD_B1_06, slew_rate: Fast, software_input_on: Disable, open_drain: Disable, speed: MHZ_100,
|
||||
drive_strength: R0_5, pull_keeper_select: Pull, pull_keeper_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, hysteresis_enable: Disable}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitPins(void) {
|
||||
CLOCK_EnableClock(kCLOCK_Iomuxc);
|
||||
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_04_GPIO1_IO04, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_06_LPUART1_TX, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK1, 1U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_ENET_RDATA01, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_10_ENET_RDATA00, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_11_ENET_RX_EN, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_ENET_RX_ER, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_ENET_TX_EN, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_14_ENET_TDATA00, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_15_ENET_TDATA01, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_GPIO1_IO22, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_ENET_MDIO, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDC, 0U);
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_04_GPIO1_IO04, 0xB0A9U);
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_06_LPUART1_TX, 0x10B0U);
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0x10B0U);
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK1, 0xB0E9U);
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_ENET_RDATA01, 0xB0E9U);
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_10_ENET_RDATA00, 0xB0E9U);
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_11_ENET_RX_EN, 0xB0E9U);
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_ENET_RX_ER, 0xB0E9U);
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_ENET_TX_EN, 0xB0E9U);
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_14_ENET_TDATA00, 0xB0E9U);
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_15_ENET_TDATA01, 0xB0E9U);
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_06_GPIO1_IO22, 0xB0A9U);
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_40_ENET_MDIO, 0xB0E9U);
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_41_ENET_MDC, 0xB0E9U);
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
|
@ -0,0 +1,65 @@
|
|||
/*
|
||||
* Copyright 2018 ,2021 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef _PIN_MUX_H_
|
||||
#define _PIN_MUX_H_
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*! @brief Direction type */
|
||||
typedef enum _pin_mux_direction
|
||||
{
|
||||
kPIN_MUX_DirectionInput = 0U, /* Input direction */
|
||||
kPIN_MUX_DirectionOutput = 1U, /* Output direction */
|
||||
kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
|
||||
} pin_mux_direction_t;
|
||||
|
||||
/*!
|
||||
* @addtogroup pin_mux
|
||||
* @{
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* API
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Calls initialization functions.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootPins(void);
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitPins(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @}
|
||||
*/
|
||||
#endif /* _PIN_MUX_H_ */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
|
@ -0,0 +1,106 @@
|
|||
Overview
|
||||
========
|
||||
This example demonstrates how to use the Simple Open EtherCAT Master (SOEM) Library to communicate with EhterCAT devices.
|
||||
|
||||
In this example there are three EhterCAT devices, one EtherCAT Coupler EK1100, one EtherCAT Terminal EL2008 (slave0),
|
||||
and one EtherCAT Terminal EL1018 (slave1).
|
||||
|
||||
This example controls a stepper motor system using two outputs and one input remote IO:
|
||||
Outputs:
|
||||
-Pluse: The pulse signal with the period of 200us and the duty cycle of 50%.
|
||||
-Dir: The direction signal.
|
||||
Inputs:
|
||||
-Limit signal: This signal comes from the Limit Switchs on the stepper motor system.
|
||||
The Dir signal changes once when one of the Limit Switchs has been touched.
|
||||
|
||||
|
||||
Toolchain supported
|
||||
===================
|
||||
- IAR embedded Workbench 9.30.1
|
||||
- Keil MDK 5.37
|
||||
- GCC ARM Embedded 10.3.1
|
||||
- MCUXpresso 11.6.0
|
||||
|
||||
Hardware requirements
|
||||
=====================
|
||||
- Mini/micro USB cable
|
||||
- Network cable RJ45 standard
|
||||
- EVK-MIMXRT1020 board
|
||||
- One BECKHOFF EK1100 EtherCAT Coupler
|
||||
- Personal Computer
|
||||
|
||||
Board settings
|
||||
==============
|
||||
No special settings are required.
|
||||
|
||||
Prepare the Demo
|
||||
================
|
||||
1. Connect a USB cable between the host PC and the OpenSDA USB port on the target board.
|
||||
2. Power up the EtherCAT Coupler and connect it to the target board via an Ethernet Cable.
|
||||
3. Open a serial terminal with the following settings:
|
||||
- 115200 baud rate
|
||||
- 8 data bits
|
||||
- No parity
|
||||
- One stop bit
|
||||
- No flow control
|
||||
4. Write the program to the flash of the target board.
|
||||
5. Press the reset button on your board to start the demo.
|
||||
|
||||
Running the demo
|
||||
================
|
||||
If the test passes, the led2 of slave0 lights up at 50% brightness.
|
||||
|
||||
If the stepper motor system is not setup properly, you can get information from
|
||||
the console log and the led4 status of slave0.
|
||||
|
||||
When the demo is running, the serial port will output:
|
||||
|
||||
|
||||
Start the soem_gpio_pulse FreeRTOS example...
|
||||
|
||||
ec_init on enet0 succeeded.
|
||||
|
||||
ec_config_init 0
|
||||
3 slaves found and configured.
|
||||
|
||||
ec_config_map_group IOmap:80000089 group:0
|
||||
>Slave 1, configadr 1001, state 12
|
||||
>Slave 2, configadr 1002, state 12
|
||||
>Slave 3, configadr 1003, state 12
|
||||
SII Isize:0
|
||||
SII Osize:0
|
||||
ISIZE:0 0 OSIZE:0
|
||||
SM programming
|
||||
SII Isize:0
|
||||
SII Osize:8
|
||||
SM0 length 8
|
||||
ISIZE:0 0 OSIZE:8
|
||||
SM programming
|
||||
SM0 Type:3 StartAddr: f00 Flags: 90044
|
||||
SII Isize:8
|
||||
SM0 length 8
|
||||
SII Osize:0
|
||||
ISIZE:8 8 OSIZE:0
|
||||
SM programming
|
||||
SM0 Type:4 StartAddr:1000 Flags: 10000
|
||||
OUTPUT MAPPING
|
||||
FMMU 0
|
||||
SM0
|
||||
slave 2 Outputs 80000089 startbit 0
|
||||
=Slave 3, INPUT MAPPING
|
||||
FMMU 0
|
||||
SM0
|
||||
Inputs 8000008A startbit 0
|
||||
IOmapSize 2
|
||||
Slaves mapped, state to SAFE_OP.
|
||||
|
||||
oloop = 1, iloop = 1
|
||||
|
||||
segments : 1 : 2 0 0 0
|
||||
|
||||
Request operational state for all slaves
|
||||
|
||||
Calculated workcounter 3
|
||||
|
||||
Operational state reached for all slaves.
|
||||
|
|
@ -0,0 +1,389 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Includes
|
||||
******************************************************************************/
|
||||
#include <stdlib.h>
|
||||
#include <stdio.h>
|
||||
|
||||
#include "pin_mux.h"
|
||||
#include "clock_config.h"
|
||||
#include "board.h"
|
||||
#include "fsl_gpio.h"
|
||||
#include "fsl_iomuxc.h"
|
||||
#include "fsl_gpt.h"
|
||||
#include "fsl_enet_mdio.h"
|
||||
#include "fsl_phyksz8081.h"
|
||||
#include "fsl_debug_console.h"
|
||||
|
||||
#include "nicdrv.h"
|
||||
#include "ethercattype.h"
|
||||
#include "ethercatbase.h"
|
||||
#include "ethercatmain.h"
|
||||
#include "ethercatdc.h"
|
||||
#include "ethercatcoe.h"
|
||||
#include "ethercatfoe.h"
|
||||
#include "ethercatconfig.h"
|
||||
#include "ethercatprint.h"
|
||||
#include "enet/soem_enet.h"
|
||||
#include "soem_port.h"
|
||||
#include "FreeRTOS.h"
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef PHY_AUTONEGO_TIMEOUT_COUNT
|
||||
#define PHY_AUTONEGO_TIMEOUT_COUNT (100000)
|
||||
#endif
|
||||
|
||||
#ifndef PHY_STABILITY_DELAY_US
|
||||
#define PHY_STABILITY_DELAY_US (0U)
|
||||
#endif
|
||||
|
||||
/*! @brief GPT timer will be used to calculate the system time and delay */
|
||||
#define OSAL_TIMER_IRQ_ID GPT2_IRQn
|
||||
#define OSAL_TIMER GPT2
|
||||
#define OSAL_TIMER_IRQHandler GPT2_IRQHandler
|
||||
#define OSAL_TIMER_CLK_FREQ CLOCK_GetFreq(kCLOCK_PerClk)
|
||||
|
||||
|
||||
#define NUM_1M (1000000UL)
|
||||
|
||||
#define OSEM_PORT_NAME "enet0"
|
||||
#define EC_TIMEOUTMON 500
|
||||
|
||||
#define SOEM_PERIOD 125 /* 125us */
|
||||
#define RT_TASK_STACK_SIZE 1024
|
||||
|
||||
#define ENET_RXBD_NUM (4)
|
||||
#define ENET_TXBD_NUM (4)
|
||||
|
||||
#define ENET_RXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN)
|
||||
#define ENET_TXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN)
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
static struct enet_if_port if_port;
|
||||
|
||||
static uint32_t timer_irq_period = 0; /* unit: microsecond*/
|
||||
|
||||
volatile struct timeval system_time_base =
|
||||
{
|
||||
.tv_sec = 0,
|
||||
.tv_usec = 0
|
||||
};
|
||||
|
||||
|
||||
/*! @brief Buffer descriptors should be in non-cacheable region and should be align to "ENET_BUFF_ALIGNMENT". */
|
||||
AT_NONCACHEABLE_SECTION_ALIGN(static enet_rx_bd_struct_t g_rxBuffDescrip[ENET_RXBD_NUM], ENET_BUFF_ALIGNMENT);
|
||||
AT_NONCACHEABLE_SECTION_ALIGN(static enet_tx_bd_struct_t g_txBuffDescrip[ENET_TXBD_NUM], ENET_BUFF_ALIGNMENT);
|
||||
|
||||
/*! @brief The data buffers can be in cacheable region or in non-cacheable region.
|
||||
* If use cacheable region, the alignment size should be the maximum size of "CACHE LINE SIZE" and "ENET_BUFF_ALIGNMENT"
|
||||
* If use non-cache region, the alignment size is the "ENET_BUFF_ALIGNMENT".
|
||||
*/
|
||||
AT_NONCACHEABLE_SECTION_ALIGN(static uint8_t g_rxDataBuff[ENET_RXBD_NUM][SDK_SIZEALIGN(ENET_RXBUFF_SIZE, ENET_BUFF_ALIGNMENT)],
|
||||
ENET_BUFF_ALIGNMENT);
|
||||
AT_NONCACHEABLE_SECTION_ALIGN(static uint8_t g_txDataBuff[ENET_TXBD_NUM][SDK_SIZEALIGN(ENET_TXBUFF_SIZE, ENET_BUFF_ALIGNMENT)],
|
||||
ENET_BUFF_ALIGNMENT);
|
||||
|
||||
static enet_buffer_config_t buffConfig[] = {{
|
||||
ENET_RXBD_NUM,
|
||||
ENET_TXBD_NUM,
|
||||
SDK_SIZEALIGN(ENET_RXBUFF_SIZE, ENET_BUFF_ALIGNMENT),
|
||||
SDK_SIZEALIGN(ENET_TXBUFF_SIZE, ENET_BUFF_ALIGNMENT),
|
||||
&g_rxBuffDescrip[0],
|
||||
&g_txBuffDescrip[0],
|
||||
&g_rxDataBuff[0][0],
|
||||
&g_txDataBuff[0][0],
|
||||
true,
|
||||
true,
|
||||
NULL,
|
||||
}};
|
||||
|
||||
static char IOmap[100];
|
||||
|
||||
static StackType_t IdleTaskStack[configMINIMAL_STACK_SIZE];
|
||||
static StaticTask_t IdleTaskTCB;
|
||||
|
||||
static StackType_t TimerTaskStacj[configMINIMAL_STACK_SIZE];
|
||||
static StaticTask_t TimerTaskTCB;
|
||||
|
||||
static StaticTask_t xTaskBuffer;
|
||||
static TaskHandle_t rt_task = NULL;
|
||||
static StackType_t rt_task_stack[RT_TASK_STACK_SIZE];
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
void irq_wake_task(void);
|
||||
|
||||
void BOARD_InitModuleClock(void)
|
||||
{
|
||||
const clock_enet_pll_config_t config = {
|
||||
.enableClkOutput = true,
|
||||
.enableClkOutput25M = false,
|
||||
.loopDivider = 1,
|
||||
};
|
||||
CLOCK_InitEnetPll(&config);
|
||||
}
|
||||
|
||||
|
||||
void OSAL_TIMER_IRQHandler(void)
|
||||
{
|
||||
/* Clear interrupt flag. */
|
||||
GPT_ClearStatusFlags(OSAL_TIMER, kGPT_OutputCompare1Flag);
|
||||
|
||||
system_time_base.tv_usec += timer_irq_period;
|
||||
|
||||
if (system_time_base.tv_usec >= NUM_1M)
|
||||
{
|
||||
system_time_base.tv_sec += system_time_base.tv_usec / NUM_1M;
|
||||
system_time_base.tv_usec = system_time_base.tv_usec % NUM_1M;
|
||||
}
|
||||
|
||||
irq_wake_task();
|
||||
|
||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F, Cortex-M7, Cortex-M7F
|
||||
* Store immediate overlapping
|
||||
* exception return operation might vector to incorrect interrupt
|
||||
*/
|
||||
SDK_ISR_EXIT_BARRIER;
|
||||
}
|
||||
|
||||
static void osal_timer_init(uint32_t usec, uint32_t priority)
|
||||
{
|
||||
uint32_t gptFreq;
|
||||
gpt_config_t gptConfig;
|
||||
|
||||
assert(usec != 0);
|
||||
assert(priority < (1UL << __NVIC_PRIO_BITS));
|
||||
|
||||
timer_irq_period = usec;
|
||||
GPT_GetDefaultConfig(&gptConfig);
|
||||
GPT_Init(OSAL_TIMER, &gptConfig);
|
||||
gptFreq = OSAL_TIMER_CLK_FREQ;
|
||||
/* Divide GPT clock source frequency to 1MHz */
|
||||
GPT_SetClockDivider(OSAL_TIMER, gptFreq / NUM_1M);
|
||||
/* Set both GPT modules to 1 second duration */
|
||||
GPT_SetOutputCompareValue(OSAL_TIMER, kGPT_OutputCompare_Channel1, timer_irq_period);
|
||||
/* Enable GPT Output Compare1 interrupt */
|
||||
GPT_EnableInterrupts(OSAL_TIMER, kGPT_OutputCompare1InterruptEnable);
|
||||
/* Enable at the Interrupt */
|
||||
NVIC_SetPriority(OSAL_TIMER_IRQ_ID, priority);
|
||||
EnableIRQ(OSAL_TIMER_IRQ_ID);
|
||||
GPT_StartTimer(OSAL_TIMER);
|
||||
}
|
||||
|
||||
void osal_gettime(struct timeval *current_time)
|
||||
{
|
||||
uint32_t usec_base;
|
||||
uint32_t cur_usec;
|
||||
uint32_t usec_again;
|
||||
|
||||
usec_base = system_time_base.tv_usec;
|
||||
cur_usec = GPT_GetCurrentTimerCount(OSAL_TIMER);
|
||||
usec_again = system_time_base.tv_usec;
|
||||
|
||||
if (usec_again != usec_base)
|
||||
{
|
||||
usec_base = system_time_base.tv_usec;
|
||||
cur_usec = GPT_GetCurrentTimerCount(OSAL_TIMER);
|
||||
}
|
||||
|
||||
current_time->tv_sec = system_time_base.tv_sec;
|
||||
current_time->tv_usec = usec_base + cur_usec;
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/* OSHW: register enet port to SOEM stack */
|
||||
static int if_port_init(void)
|
||||
{
|
||||
memset(&if_port, 0, sizeof(if_port));
|
||||
if_port.mdioHandle.ops = &enet_ops;
|
||||
if_port.phyHandle.ops = &phyksz8081_ops;
|
||||
if_port.bufferConfig = buffConfig;
|
||||
if_port.base = ENET;
|
||||
/* The miiMode should be set according to the different PHY interfaces. */
|
||||
if_port.mii_mode = kENET_RmiiMode;
|
||||
if_port.phy_config.autoNeg = true;
|
||||
if_port.phy_config.phyAddr = 0x02U;
|
||||
if_port.srcClock_Hz = CLOCK_GetFreq(kCLOCK_IpgClk);
|
||||
if_port.phy_autonego_timeout_count = PHY_AUTONEGO_TIMEOUT_COUNT;
|
||||
if_port.phy_stability_delay_us = PHY_STABILITY_DELAY_US;
|
||||
|
||||
return register_soem_port(OSEM_PORT_NAME, "enet", &if_port);
|
||||
}
|
||||
|
||||
|
||||
void vApplicationGetIdleTaskMemory(StaticTask_t **ppxIdleTaskTCBBuffer,
|
||||
StackType_t **ppxIdleTaskStackBuffer,
|
||||
uint32_t *pulIdleTaskStackSize)
|
||||
{
|
||||
*ppxIdleTaskTCBBuffer = &IdleTaskTCB;
|
||||
*ppxIdleTaskStackBuffer = &IdleTaskStack[0];
|
||||
*pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
|
||||
}
|
||||
|
||||
void vApplicationGetTimerTaskMemory(StaticTask_t **ppxTimerTaskTCBBuffer,
|
||||
StackType_t **ppxTimerTaskStackBuffer,
|
||||
uint32_t *pulTimerTaskStackSize)
|
||||
{
|
||||
*ppxTimerTaskTCBBuffer = &TimerTaskTCB;
|
||||
*ppxTimerTaskStackBuffer = &TimerTaskStacj[0];
|
||||
*pulTimerTaskStackSize = configMINIMAL_STACK_SIZE;
|
||||
}
|
||||
|
||||
void irq_wake_task(void)
|
||||
{
|
||||
BaseType_t xHigherPriorityTaskWoken;
|
||||
|
||||
if (rt_task)
|
||||
{
|
||||
xHigherPriorityTaskWoken = pdFALSE;
|
||||
vTaskNotifyGiveFromISR(rt_task, &xHigherPriorityTaskWoken);
|
||||
portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
|
||||
}
|
||||
}
|
||||
|
||||
void control_task(void *ifname)
|
||||
{
|
||||
int oloop, iloop;
|
||||
int expectedWKC;
|
||||
volatile int wkc;
|
||||
int old_switch0 = 0;
|
||||
int old_switch1 = 0;
|
||||
struct timeval target_time;
|
||||
const TickType_t xBlockTime = pdMS_TO_TICKS(500);
|
||||
char chk = 40;
|
||||
|
||||
/* initialise SOEM, and if_port */
|
||||
if (ec_init(ifname))
|
||||
{
|
||||
PRINTF("ec_init on %s succeeded.\r\n", ifname);
|
||||
if (ec_config_init(FALSE) > 0)
|
||||
{
|
||||
PRINTF("%d slaves found and configured.\r\n", ec_slavecount);
|
||||
ec_config_map(&IOmap);
|
||||
ec_configdc();
|
||||
PRINTF("Slaves mapped, state to SAFE_OP.\r\n");
|
||||
/* wait for all slaves to reach SAFE_OP state */
|
||||
ec_statecheck(0, EC_STATE_SAFE_OP, EC_TIMEOUTSTATE * 4);
|
||||
oloop = ec_slave[2].Obytes;
|
||||
iloop = ec_slave[3].Ibytes;
|
||||
PRINTF("oloop = %d, iloop = %d\r\n", oloop, iloop);
|
||||
PRINTF("segments : %d : %d %d %d %d\r\n", ec_group[0].nsegments, ec_group[0].IOsegment[0],
|
||||
ec_group[0].IOsegment[1], ec_group[0].IOsegment[2], ec_group[0].IOsegment[3]);
|
||||
|
||||
PRINTF("Request operational state for all slaves\r\n");
|
||||
expectedWKC = (ec_group[0].outputsWKC * 2) + ec_group[0].inputsWKC;
|
||||
PRINTF("Calculated workcounter %d\r\n", expectedWKC);
|
||||
ec_slave[0].state = EC_STATE_OPERATIONAL;
|
||||
/* send one valid process data to make outputs in slaves happy*/
|
||||
ec_send_processdata();
|
||||
ec_receive_processdata(EC_TIMEOUTRET);
|
||||
/* request OP state for all slaves */
|
||||
ec_writestate(0);
|
||||
/* wait for all slaves to reach OP state */
|
||||
do
|
||||
{
|
||||
ec_send_processdata();
|
||||
ec_receive_processdata(EC_TIMEOUTRET);
|
||||
ec_statecheck(0, EC_STATE_OPERATIONAL, 50000);
|
||||
} while (chk-- && (ec_slave[0].state != EC_STATE_OPERATIONAL));
|
||||
PRINTF("Operational state reached for all slaves.\r\n");
|
||||
/* cyclic loop */
|
||||
ulTaskNotifyTake(pdTRUE, xBlockTime);
|
||||
osal_gettime(&target_time);
|
||||
for (;;)
|
||||
{
|
||||
ec_send_processdata();
|
||||
wkc = ec_receive_processdata(EC_TIMEOUTRET);
|
||||
if (wkc >= expectedWKC)
|
||||
{
|
||||
if ((*(ec_slave[3].inputs) & 0x01) && old_switch0 == 0)
|
||||
{
|
||||
if (*(ec_slave[2].outputs) & 0x04)
|
||||
*(ec_slave[2].outputs) &= ~0x04;
|
||||
else
|
||||
*(ec_slave[2].outputs) |= 0x04;
|
||||
}
|
||||
|
||||
if ((*(ec_slave[3].inputs) & 0x02) && old_switch1 == 0)
|
||||
{
|
||||
if (*(ec_slave[2].outputs) & 0x04)
|
||||
*(ec_slave[2].outputs) &= ~0x04;
|
||||
else
|
||||
*(ec_slave[2].outputs) |= 0x04;
|
||||
}
|
||||
|
||||
old_switch0 = *(ec_slave[3].inputs) & 0x01;
|
||||
old_switch1 = *(ec_slave[3].inputs) & 0x02;
|
||||
if (*(ec_slave[2].outputs) & 0x02)
|
||||
*(ec_slave[2].outputs) &= ~0x02;
|
||||
else
|
||||
*(ec_slave[2].outputs) |= 0x02;
|
||||
}
|
||||
ulTaskNotifyTake(pdFALSE, xBlockTime);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Main function
|
||||
*/
|
||||
int main(void)
|
||||
{
|
||||
gpio_pin_config_t gpio_config = {
|
||||
kGPIO_DigitalOutput,
|
||||
0,
|
||||
kGPIO_NoIntmode
|
||||
};
|
||||
|
||||
BOARD_ConfigMPU();
|
||||
BOARD_InitBootPins();
|
||||
BOARD_InitBootClocks();
|
||||
BOARD_InitDebugConsole();
|
||||
BOARD_InitModuleClock();
|
||||
|
||||
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true);
|
||||
|
||||
GPIO_PinInit(GPIO1, 9, &gpio_config);
|
||||
GPIO_PinInit(GPIO1, 10, &gpio_config);
|
||||
/* pull up the ENET_INT before RESET. */
|
||||
GPIO_WritePinOutput(GPIO1, 10, 1);
|
||||
GPIO_WritePinOutput(GPIO1, 9, 0);
|
||||
SDK_DelayAtLeastUs(NUM_1M, CLOCK_GetFreq(kCLOCK_CpuClk));
|
||||
GPIO_WritePinOutput(GPIO1, 9, 1);
|
||||
|
||||
PRINTF("Start the soem_gpio_pulse FreeRTOS example...\r\n");
|
||||
|
||||
osal_timer_init(SOEM_PERIOD, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
|
||||
if_port_init();
|
||||
rt_task = xTaskCreateStatic(/* The function that implements the task. */
|
||||
control_task, "RT_task", RT_TASK_STACK_SIZE, OSEM_PORT_NAME, configMAX_PRIORITIES - 1,
|
||||
rt_task_stack, &xTaskBuffer);
|
||||
|
||||
vTaskStartScheduler();
|
||||
for (;;)
|
||||
;
|
||||
return 0;
|
||||
}
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue