/* * Copyright 2018-2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ void Clock_Init() { unsigned int reg; // Enable all clocks MEM_WriteU32(0x400FC068,0xffffffff); MEM_WriteU32(0x400FC06C,0xffffffff); MEM_WriteU32(0x400FC070,0xffffffff); MEM_WriteU32(0x400FC074,0xffffffff); MEM_WriteU32(0x400FC078,0xffffffff); MEM_WriteU32(0x400FC07C,0xffffffff); MEM_WriteU32(0x400FC080,0xffffffff); // IPG_PODF: 2 divide by 3 MEM_WriteU32(0x400FC014,0x000A8200); // PERCLK_PODF: 1 divide by 2 MEM_WriteU32(0x400FC01C,0x04900001); // Enable SYS PLL but keep it bypassed. MEM_WriteU32(0x400D8030,0x00012001); do { reg = MEM_ReadU32(0x400D8030); } while((reg & 0x80000000) == 0); // Disable bypass of SYS PLL MEM_WriteU32(0x400D8030,0x00002001); // PFD2_FRAC: 24, PLL2 PFD2=528*18/PFD2_FRAC=396 // Ungate SYS PLL PFD2 reg = MEM_ReadU32(0x400D8100); reg &= ~0xBF0000; reg |= 0x180000; MEM_WriteU32(0x400D8100, reg); // SEMC_ALT_CLK_SEL: 0 PLL2 (SYS PLL) PFD2 // SEMC_CLK_SEL: 1 SEMC_ALT_CLK // SEMC_PODF: 2 divide by 3 reg = MEM_ReadU32(0x400FC014); reg &= ~0x700C0; reg |= 0x20040; MEM_WriteU32(0x400FC014, reg); // Disable MPU which will be enabled by ROM to prevent code execution reg = MEM_ReadU32(0xE000ED94); reg &= ~0x1; MEM_WriteU32(0xE000ED94, reg); Report("Clock Init Done"); } void SDRAM_WaitIpCmdDone(void) { unsigned int reg; do { reg = MEM_ReadU32(0x402F003C); }while((reg & 0x3) == 0); } void SDRAM_Init() { // Config IOMUX for SDRAM MEM_WriteU32(0x401F8014,0x00000000); // EMC_00 MEM_WriteU32(0x401F8018,0x00000000); // EMC_01 MEM_WriteU32(0x401F801C,0x00000000); // EMC_02 MEM_WriteU32(0x401F8020,0x00000000); // EMC_03 MEM_WriteU32(0x401F8024,0x00000000); // EMC_04 MEM_WriteU32(0x401F8028,0x00000000); // EMC_05 MEM_WriteU32(0x401F802C,0x00000000); // EMC_06 MEM_WriteU32(0x401F8030,0x00000000); // EMC_07 MEM_WriteU32(0x401F8034,0x00000000); // EMC_08 MEM_WriteU32(0x401F8038,0x00000000); // EMC_09 MEM_WriteU32(0x401F803C,0x00000000); // EMC_10 MEM_WriteU32(0x401F8040,0x00000000); // EMC_11 MEM_WriteU32(0x401F8044,0x00000000); // EMC_12 MEM_WriteU32(0x401F8048,0x00000000); // EMC_13 MEM_WriteU32(0x401F804C,0x00000000); // EMC_14 MEM_WriteU32(0x401F8050,0x00000000); // EMC_15 MEM_WriteU32(0x401F8054,0x00000000); // EMC_16 MEM_WriteU32(0x401F8058,0x00000000); // EMC_17 MEM_WriteU32(0x401F805C,0x00000000); // EMC_18 MEM_WriteU32(0x401F8060,0x00000000); // EMC_19 MEM_WriteU32(0x401F8064,0x00000000); // EMC_20 MEM_WriteU32(0x401F8068,0x00000000); // EMC_21 MEM_WriteU32(0x401F806C,0x00000000); // EMC_22 MEM_WriteU32(0x401F8070,0x00000000); // EMC_23 MEM_WriteU32(0x401F8074,0x00000000); // EMC_24 MEM_WriteU32(0x401F8078,0x00000000); // EMC_25 MEM_WriteU32(0x401F807C,0x00000000); // EMC_26 MEM_WriteU32(0x401F8080,0x00000000); // EMC_27 MEM_WriteU32(0x401F8084,0x00000010); // EMC_28, DQS PIN, enable SION MEM_WriteU32(0x401F8088,0x00000000); // EMC_29 MEM_WriteU32(0x401F808C,0x00000000); // EMC_30 MEM_WriteU32(0x401F8090,0x00000000); // EMC_31 MEM_WriteU32(0x401F8094,0x00000000); // EMC_32 MEM_WriteU32(0x401F8098,0x00000000); // EMC_33 MEM_WriteU32(0x401F809C,0x00000000); // EMC_34 MEM_WriteU32(0x401F80A0,0x00000000); // EMC_35 MEM_WriteU32(0x401F80A4,0x00000000); // EMC_36 MEM_WriteU32(0x401F80A8,0x00000000); // EMC_37 MEM_WriteU32(0x401F80AC,0x00000000); // EMC_38 MEM_WriteU32(0x401F80B0,0x00000000); // EMC_39 // PAD ctrl // drive strength = 0x7 to increase drive strength // otherwise the data7 bit may fail. MEM_WriteU32(0x401F8188,0x000000F1); // EMC_00 MEM_WriteU32(0x401F818C,0x000000F1); // EMC_01 MEM_WriteU32(0x401F8190,0x000000F1); // EMC_02 MEM_WriteU32(0x401F8194,0x000000F1); // EMC_03 MEM_WriteU32(0x401F8198,0x000000F1); // EMC_04 MEM_WriteU32(0x401F819C,0x000000F1); // EMC_05 MEM_WriteU32(0x401F81A0,0x000000F1); // EMC_06 MEM_WriteU32(0x401F81A4,0x000000F1); // EMC_07 MEM_WriteU32(0x401F81A8,0x000000F1); // EMC_08 MEM_WriteU32(0x401F81AC,0x000000F1); // EMC_09 MEM_WriteU32(0x401F81B0,0x000000F1); // EMC_10 MEM_WriteU32(0x401F81B4,0x000000F1); // EMC_11 MEM_WriteU32(0x401F81B8,0x000000F1); // EMC_12 MEM_WriteU32(0x401F81BC,0x000000F1); // EMC_13 MEM_WriteU32(0x401F81C0,0x000000F1); // EMC_14 MEM_WriteU32(0x401F81C4,0x000000F1); // EMC_15 MEM_WriteU32(0x401F81C8,0x000000F1); // EMC_16 MEM_WriteU32(0x401F81CC,0x000000F1); // EMC_17 MEM_WriteU32(0x401F81D0,0x000000F1); // EMC_18 MEM_WriteU32(0x401F81D4,0x000000F1); // EMC_19 MEM_WriteU32(0x401F81D8,0x000000F1); // EMC_20 MEM_WriteU32(0x401F81DC,0x000000F1); // EMC_21 MEM_WriteU32(0x401F81E0,0x000000F1); // EMC_22 MEM_WriteU32(0x401F81E4,0x000000F1); // EMC_23 MEM_WriteU32(0x401F81E8,0x000000F1); // EMC_24 MEM_WriteU32(0x401F81EC,0x000000F1); // EMC_25 MEM_WriteU32(0x401F81F0,0x000000F1); // EMC_26 MEM_WriteU32(0x401F81F4,0x000000F1); // EMC_27 MEM_WriteU32(0x401F81F8,0x000000F1); // EMC_28 MEM_WriteU32(0x401F81FC,0x000000F1); // EMC_29 MEM_WriteU32(0x401F8200,0x000000F1); // EMC_30 MEM_WriteU32(0x401F8204,0x000000F1); // EMC_31 MEM_WriteU32(0x401F8208,0x000000F1); // EMC_32 MEM_WriteU32(0x401F820C,0x000000F1); // EMC_33 MEM_WriteU32(0x401F8210,0x000000F1); // EMC_34 MEM_WriteU32(0x401F8214,0x000000F1); // EMC_35 MEM_WriteU32(0x401F8218,0x000000F1); // EMC_36 MEM_WriteU32(0x401F821C,0x000000F1); // EMC_37 MEM_WriteU32(0x401F8220,0x000000F1); // EMC_38 MEM_WriteU32(0x401F8224,0x000000F1); // EMC_39 // Config SDR Controller Registers/ MEM_WriteU32(0x402F0000,0x10000004); // MCR MEM_WriteU32(0x402F0008,0x00000081); // BMCR0 MEM_WriteU32(0x402F000C,0x00000081); // BMCR1 MEM_WriteU32(0x402F0010,0x8000001B); // BR0, 32MB MEM_WriteU32(0x402F0014,0x8200001B); // BR1, 32MB MEM_WriteU32(0x402F0018,0x8400001B); // BR2, 32MB MEM_WriteU32(0x402F001C,0x8600001B); // BR3, 32MB MEM_WriteU32(0x402F0020,0x90000021); // BR4, MEM_WriteU32(0x402F0024,0xA0000019); // BR5, MEM_WriteU32(0x402F0028,0xA8000017); // BR6, MEM_WriteU32(0x402F002C,0xA900001B); // BR7, MEM_WriteU32(0x402F0030,0x00000021); // BR8, MEM_WriteU32(0x402F0004,0x000079A8); //IOCR,SEMC_CCSX0 as NOR CE, SEMC_CSX1 as PSRAM CE, SEMC_CSX2 as NAND CE, SEMC_CSX3 as DBI CE. // MEM_WriteU32(0x402F0004,0x00000008); // IOCR, SEMC_CCSX0 as SDRAM_CS1 MEM_WriteU32(0x402F0040,0x00000F31); // SDRAMCR0 MEM_WriteU32(0x402F0044,0x00652922); // SDRAMCR1 MEM_WriteU32(0x402F0048,0x00010920); // SDRAMCR2 MEM_WriteU32(0x402F004C,0x50210A09); // SDRAMCR3 MEM_WriteU32(0x402F0080,0x00000021); // DBICR0 MEM_WriteU32(0x402F0084,0x00888888); // DBICR1 MEM_WriteU32(0x402F0094,0x00000002); // IPCR1 MEM_WriteU32(0x402F0098,0x00000000); // IPCR2 MEM_WriteU32(0x402F0090,0x80000000); // IPCR0 MEM_WriteU32(0x402F009C,0xA55A000F); // IPCMD, SD_CC_IPREA SDRAM_WaitIpCmdDone(); MEM_WriteU32(0x402F0090,0x80000000); // IPCR0 MEM_WriteU32(0x402F009C,0xA55A000C); // SD_CC_IAF SDRAM_WaitIpCmdDone(); MEM_WriteU32(0x402F0090,0x80000000); // IPCR0 MEM_WriteU32(0x402F009C,0xA55A000C); // SD_CC_IAF SDRAM_WaitIpCmdDone(); MEM_WriteU32(0x402F00A0,0x00000033); // IPTXDAT MEM_WriteU32(0x402F0090,0x80000000); // IPCR0 MEM_WriteU32(0x402F009C,0xA55A000A); // SD_CC_IMS SDRAM_WaitIpCmdDone(); MEM_WriteU32(0x402F004C,0x50210A09 ); // enable sdram self refresh again after initialization done. Report("SDRAM Init Done"); } void RestoreFlexRAM() { unsigned int base; unsigned int value; base = 0x400AC000; value = MEM_ReadU32(base + 0x44); value &= ~(0xFFFF); value |= 0x5FA5; MEM_WriteU32(base + 0x44, value); value = MEM_ReadU32(base + 0x40); value |= (1 << 2); MEM_WriteU32(base + 0x40, value); Report("FlexRAM configuration is restored"); } /* ConfigTarget */ void ConfigTargetSettings(void) { Report("Config JTAG Speed to 4000kHz"); JTAG_Speed = 4000; } /* SetupTarget */ void SetupTarget(void) { Report("Enabling i.MXRT SDRAM"); RestoreFlexRAM(); Clock_Init(); SDRAM_Init(); } /* AfterResetTarget */ void AfterResetTarget(void) { RestoreFlexRAM(); Clock_Init(); SDRAM_Init(); }