110 lines
2.8 KiB
C
110 lines
2.8 KiB
C
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#include "fsl_common.h"
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#include "fsl_clock.h"
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#include "pin_mux.h"
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#include "usb.h"
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#include "usb_phy.h"
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#include "board.h"
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#include "ux_api.h"
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#include "ux_hcd_ehci.h"
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#define USB_INTERRUPT_PRIORITY (6U)
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#define UX_HCD_NAME "EHCI HOST"
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#ifndef USBX_MEMORY_SIZE
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#define USBX_MEMORY_SIZE (60 * 1024)
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#endif
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#ifndef USBX_MEMORY_CACHESAFE_SIZE
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#define USBX_MEMORY_CACHESAFE_SIZE (60 * 1024)
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#endif
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ULONG usb_memory[USBX_MEMORY_SIZE / sizeof(ULONG)];
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AT_NONCACHEABLE_SECTION_ALIGN(char usb_memory_cachesafe[USBX_MEMORY_CACHESAFE_SIZE], 64);
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static ULONG usb_host_base(VOID)
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{
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/* For EHCI core. */
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return (USB_BASE + 0x100);
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}
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static void usb_interrupt_setup(void)
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{
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IRQn_Type irqNumber = USB_OTG1_IRQn;
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/* Clear pending IRQ, set priority, and enable IRQ. */
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NVIC_ClearPendingIRQ(irqNumber);
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NVIC_SetPriority(irqNumber, USB_INTERRUPT_PRIORITY);
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EnableIRQ((IRQn_Type)irqNumber);
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}
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void board_setup(void)
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{
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/* Init board hardware. */
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BOARD_ConfigMPU();
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BOARD_InitBootPins();
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BOARD_InitBootClocks();
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BOARD_InitDebugConsole();
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}
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void usb_host_hw_setup(void)
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{
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usb_phy_config_struct_t phyConfig = {
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BOARD_USB_PHY_D_CAL,
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BOARD_USB_PHY_TXCAL45DP,
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BOARD_USB_PHY_TXCAL45DM,
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};
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CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, 480000000U);
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CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, 480000000U);
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USB_EhciPhyInit(kUSB_ControllerEhci0, BOARD_XTAL0_CLK_HZ, &phyConfig);
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usb_interrupt_setup();
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}
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UINT usbx_host_hcd_register(VOID)
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{
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UINT status;
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status = ux_host_stack_hcd_register((UCHAR *)UX_HCD_NAME,
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_ux_hcd_ehci_initialize,
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usb_host_base(), (ULONG)USB_OTG1_IRQn);
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return status;
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}
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VOID usbx_mem_init(VOID)
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{
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ux_system_initialize((VOID *)usb_memory, USBX_MEMORY_SIZE,
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usb_memory_cachesafe, USBX_MEMORY_CACHESAFE_SIZE);
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}
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/* this function is for the macro UX_HCD_EHCI_EXT_USBPHY_HIGHSPEED_MODE_SET in ux_user.h */
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void usbphy_set_highspeed_mode(void *regs, int on_off)
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{
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USB_Type* usb_base[] = USB_BASE_PTRS;
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USBPHY_Type* usbphy_base[] = USBPHY_BASE_PTRS;
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uint32_t ehci_base;
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UX_HCD_EHCI *hcd_ehci;
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int i;
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hcd_ehci = (UX_HCD_EHCI *)regs;
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if (hcd_ehci->ux_hcd_ehci_base == 0)
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return;
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/* the first value in USB_BASE_ADDRS is always zero, so skip it */
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for (i = 1; i < sizeof(usb_base) / sizeof(usb_base[0]); i++)
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{
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ehci_base = (uint32_t)(&usb_base[i]->CAPLENGTH);
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if ((uint32_t)hcd_ehci->ux_hcd_ehci_base == ehci_base) {
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if (on_off)
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usbphy_base[i]->CTRL_SET = USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK;
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else
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usbphy_base[i]->CTRL_CLR = USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK;
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}
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}
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}
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